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TARGET_ARCH_MAX/stm32f4xx_ll_fmc.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Child:: 92:4fc01daae5a5

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	89:552587b429a1	1	/**
bogdanm	89:552587b429a1	2	******************************************************************************
bogdanm	89:552587b429a1	3	* @file stm32f4xx_ll_fmc.h
bogdanm	89:552587b429a1	4	* @author MCD Application Team
bogdanm	89:552587b429a1	5	* @version V1.1.0RC2
bogdanm	89:552587b429a1	6	* @date 14-May-2014
bogdanm	89:552587b429a1	7	* @brief Header file of FMC HAL module.
bogdanm	89:552587b429a1	8	******************************************************************************
bogdanm	89:552587b429a1	9	* @attention
bogdanm	89:552587b429a1	10	*
bogdanm	89:552587b429a1	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	89:552587b429a1	12	*
bogdanm	89:552587b429a1	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	89:552587b429a1	14	* are permitted provided that the following conditions are met:
bogdanm	89:552587b429a1	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	89:552587b429a1	16	* this list of conditions and the following disclaimer.
bogdanm	89:552587b429a1	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	89:552587b429a1	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	89:552587b429a1	19	* and/or other materials provided with the distribution.
bogdanm	89:552587b429a1	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	89:552587b429a1	21	* may be used to endorse or promote products derived from this software
bogdanm	89:552587b429a1	22	* without specific prior written permission.
bogdanm	89:552587b429a1	23	*
bogdanm	89:552587b429a1	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	89:552587b429a1	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	89:552587b429a1	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	89:552587b429a1	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	89:552587b429a1	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	89:552587b429a1	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	89:552587b429a1	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	89:552587b429a1	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	89:552587b429a1	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	89:552587b429a1	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	89:552587b429a1	34	*
bogdanm	89:552587b429a1	35	******************************************************************************
bogdanm	89:552587b429a1	36	*/
bogdanm	89:552587b429a1	37
bogdanm	89:552587b429a1	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	89:552587b429a1	39	#ifndef __STM32F4xx_LL_FMC_H
bogdanm	89:552587b429a1	40	#define __STM32F4xx_LL_FMC_H
bogdanm	89:552587b429a1	41
bogdanm	89:552587b429a1	42	#ifdef __cplusplus
bogdanm	89:552587b429a1	43	extern "C" {
bogdanm	89:552587b429a1	44	#endif
bogdanm	89:552587b429a1	45
bogdanm	89:552587b429a1	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	89:552587b429a1	47
bogdanm	89:552587b429a1	48	/* Includes ------------------------------------------------------------------*/
bogdanm	89:552587b429a1	49	#include "stm32f4xx_hal_def.h"
bogdanm	89:552587b429a1	50
bogdanm	89:552587b429a1	51	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	89:552587b429a1	52	* @{
bogdanm	89:552587b429a1	53	*/
bogdanm	89:552587b429a1	54
bogdanm	89:552587b429a1	55	/** @addtogroup FMC
bogdanm	89:552587b429a1	56	* @{
bogdanm	89:552587b429a1	57	*/
bogdanm	89:552587b429a1	58
bogdanm	89:552587b429a1	59	/* Exported typedef ----------------------------------------------------------*/
bogdanm	89:552587b429a1	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
bogdanm	89:552587b429a1	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
bogdanm	89:552587b429a1	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
bogdanm	89:552587b429a1	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
bogdanm	89:552587b429a1	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
bogdanm	89:552587b429a1	65
bogdanm	89:552587b429a1	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
bogdanm	89:552587b429a1	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
bogdanm	89:552587b429a1	68	#define FMC_NAND_DEVICE FMC_Bank2_3
bogdanm	89:552587b429a1	69	#define FMC_PCCARD_DEVICE FMC_Bank4
bogdanm	89:552587b429a1	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
bogdanm	89:552587b429a1	71
bogdanm	89:552587b429a1	72	/**
bogdanm	89:552587b429a1	73	* @brief FMC_NORSRAM Configuration Structure definition
bogdanm	89:552587b429a1	74	*/
bogdanm	89:552587b429a1	75	typedef struct
bogdanm	89:552587b429a1	76	{
bogdanm	89:552587b429a1	77	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	89:552587b429a1	78	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	89:552587b429a1	79
bogdanm	89:552587b429a1	80	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
bogdanm	89:552587b429a1	81	multiplexed on the data bus or not.
bogdanm	89:552587b429a1	82	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	89:552587b429a1	83
bogdanm	89:552587b429a1	84	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
bogdanm	89:552587b429a1	85	the corresponding memory device.
bogdanm	89:552587b429a1	86	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	89:552587b429a1	87
bogdanm	89:552587b429a1	88	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	89:552587b429a1	89	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	89:552587b429a1	90
bogdanm	89:552587b429a1	91	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
bogdanm	89:552587b429a1	92	valid only with synchronous burst Flash memories.
bogdanm	89:552587b429a1	93	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	89:552587b429a1	94
bogdanm	89:552587b429a1	95	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
bogdanm	89:552587b429a1	96	the Flash memory in burst mode.
bogdanm	89:552587b429a1	97	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	89:552587b429a1	98
bogdanm	89:552587b429a1	99	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
bogdanm	89:552587b429a1	100	memory, valid only when accessing Flash memories in burst mode.
bogdanm	89:552587b429a1	101	This parameter can be a value of @ref FMC_Wrap_Mode */
bogdanm	89:552587b429a1	102
bogdanm	89:552587b429a1	103	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
bogdanm	89:552587b429a1	104	clock cycle before the wait state or during the wait state,
bogdanm	89:552587b429a1	105	valid only when accessing memories in burst mode.
bogdanm	89:552587b429a1	106	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	89:552587b429a1	107
bogdanm	89:552587b429a1	108	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
bogdanm	89:552587b429a1	109	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	89:552587b429a1	110
bogdanm	89:552587b429a1	111	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
bogdanm	89:552587b429a1	112	signal, valid for Flash memory access in burst mode.
bogdanm	89:552587b429a1	113	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	89:552587b429a1	114
bogdanm	89:552587b429a1	115	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
bogdanm	89:552587b429a1	116	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	89:552587b429a1	117
bogdanm	89:552587b429a1	118	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
bogdanm	89:552587b429a1	119	valid only with asynchronous Flash memories.
bogdanm	89:552587b429a1	120	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	89:552587b429a1	121
bogdanm	89:552587b429a1	122	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	89:552587b429a1	123	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	89:552587b429a1	124
bogdanm	89:552587b429a1	125	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
bogdanm	89:552587b429a1	126	This parameter is only enabled through the FMC_BCR1 register, and don't care
bogdanm	89:552587b429a1	127	through FMC_BCR2..4 registers.
bogdanm	89:552587b429a1	128	This parameter can be a value of @ref FMC_Continous_Clock */
bogdanm	89:552587b429a1	129
bogdanm	89:552587b429a1	130	}FMC_NORSRAM_InitTypeDef;
bogdanm	89:552587b429a1	131
bogdanm	89:552587b429a1	132	/**
bogdanm	89:552587b429a1	133	* @brief FMC_NORSRAM Timing parameters structure definition
bogdanm	89:552587b429a1	134	*/
bogdanm	89:552587b429a1	135	typedef struct
bogdanm	89:552587b429a1	136	{
bogdanm	89:552587b429a1	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	89:552587b429a1	138	the duration of the address setup time.
bogdanm	89:552587b429a1	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	89:552587b429a1	140	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	89:552587b429a1	141
bogdanm	89:552587b429a1	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	89:552587b429a1	143	the duration of the address hold time.
bogdanm	89:552587b429a1	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
bogdanm	89:552587b429a1	145	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	89:552587b429a1	146
bogdanm	89:552587b429a1	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
bogdanm	89:552587b429a1	148	the duration of the data setup time.
bogdanm	89:552587b429a1	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
bogdanm	89:552587b429a1	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
bogdanm	89:552587b429a1	151	NOR Flash memories. */
bogdanm	89:552587b429a1	152
bogdanm	89:552587b429a1	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
bogdanm	89:552587b429a1	154	the duration of the bus turnaround.
bogdanm	89:552587b429a1	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
bogdanm	89:552587b429a1	156	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	89:552587b429a1	157
bogdanm	89:552587b429a1	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
bogdanm	89:552587b429a1	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
bogdanm	89:552587b429a1	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
bogdanm	89:552587b429a1	161	accesses. */
bogdanm	89:552587b429a1	162
bogdanm	89:552587b429a1	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
bogdanm	89:552587b429a1	164	to the memory before getting the first data.
bogdanm	89:552587b429a1	165	The parameter value depends on the memory type as shown below:
bogdanm	89:552587b429a1	166	- It must be set to 0 in case of a CRAM
bogdanm	89:552587b429a1	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
bogdanm	89:552587b429a1	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
bogdanm	89:552587b429a1	169	with synchronous burst mode enable */
bogdanm	89:552587b429a1	170
bogdanm	89:552587b429a1	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
bogdanm	89:552587b429a1	172	This parameter can be a value of @ref FMC_Access_Mode */
bogdanm	89:552587b429a1	173	}FMC_NORSRAM_TimingTypeDef;
bogdanm	89:552587b429a1	174
bogdanm	89:552587b429a1	175	/**
bogdanm	89:552587b429a1	176	* @brief FMC_NAND Configuration Structure definition
bogdanm	89:552587b429a1	177	*/
bogdanm	89:552587b429a1	178	typedef struct
bogdanm	89:552587b429a1	179	{
bogdanm	89:552587b429a1	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	89:552587b429a1	181	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	89:552587b429a1	182
bogdanm	89:552587b429a1	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
bogdanm	89:552587b429a1	184	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	89:552587b429a1	185
bogdanm	89:552587b429a1	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
bogdanm	89:552587b429a1	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	89:552587b429a1	188
bogdanm	89:552587b429a1	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
bogdanm	89:552587b429a1	190	This parameter can be any value of @ref FMC_ECC */
bogdanm	89:552587b429a1	191
bogdanm	89:552587b429a1	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
bogdanm	89:552587b429a1	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	89:552587b429a1	194
bogdanm	89:552587b429a1	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	89:552587b429a1	196	delay between CLE low and RE low.
bogdanm	89:552587b429a1	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	198
bogdanm	89:552587b429a1	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	89:552587b429a1	200	delay between ALE low and RE low.
bogdanm	89:552587b429a1	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	202	}FMC_NAND_InitTypeDef;
bogdanm	89:552587b429a1	203
bogdanm	89:552587b429a1	204	/**
bogdanm	89:552587b429a1	205	* @brief FMC_NAND_PCCARD Timing parameters structure definition
bogdanm	89:552587b429a1	206	*/
bogdanm	89:552587b429a1	207	typedef struct
bogdanm	89:552587b429a1	208	{
bogdanm	89:552587b429a1	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
bogdanm	89:552587b429a1	210	the command assertion for NAND-Flash read or write access
bogdanm	89:552587b429a1	211	to common/Attribute or I/O memory space (depending on
bogdanm	89:552587b429a1	212	the memory space timing to be configured).
bogdanm	89:552587b429a1	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	214
bogdanm	89:552587b429a1	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
bogdanm	89:552587b429a1	216	command for NAND-Flash read or write access to
bogdanm	89:552587b429a1	217	common/Attribute or I/O memory space (depending on the
bogdanm	89:552587b429a1	218	memory space timing to be configured).
bogdanm	89:552587b429a1	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	220
bogdanm	89:552587b429a1	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
bogdanm	89:552587b429a1	222	(and data for write access) after the command de-assertion
bogdanm	89:552587b429a1	223	for NAND-Flash read or write access to common/Attribute
bogdanm	89:552587b429a1	224	or I/O memory space (depending on the memory space timing
bogdanm	89:552587b429a1	225	to be configured).
bogdanm	89:552587b429a1	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	227
bogdanm	89:552587b429a1	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
bogdanm	89:552587b429a1	229	data bus is kept in HiZ after the start of a NAND-Flash
bogdanm	89:552587b429a1	230	write access to common/Attribute or I/O memory space (depending
bogdanm	89:552587b429a1	231	on the memory space timing to be configured).
bogdanm	89:552587b429a1	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	233	}FMC_NAND_PCC_TimingTypeDef;
bogdanm	89:552587b429a1	234
bogdanm	89:552587b429a1	235	/**
bogdanm	89:552587b429a1	236	* @brief FMC_NAND Configuration Structure definition
bogdanm	89:552587b429a1	237	*/
bogdanm	89:552587b429a1	238	typedef struct
bogdanm	89:552587b429a1	239	{
bogdanm	89:552587b429a1	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
bogdanm	89:552587b429a1	241	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	89:552587b429a1	242
bogdanm	89:552587b429a1	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	89:552587b429a1	244	delay between CLE low and RE low.
bogdanm	89:552587b429a1	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	246
bogdanm	89:552587b429a1	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
bogdanm	89:552587b429a1	248	delay between ALE low and RE low.
bogdanm	89:552587b429a1	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	89:552587b429a1	250	}FMC_PCCARD_InitTypeDef;
bogdanm	89:552587b429a1	251
bogdanm	89:552587b429a1	252	/**
bogdanm	89:552587b429a1	253	* @brief FMC_SDRAM Configuration Structure definition
bogdanm	89:552587b429a1	254	*/
bogdanm	89:552587b429a1	255	typedef struct
bogdanm	89:552587b429a1	256	{
bogdanm	89:552587b429a1	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	89:552587b429a1	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	89:552587b429a1	259
bogdanm	89:552587b429a1	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	89:552587b429a1	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	89:552587b429a1	262
bogdanm	89:552587b429a1	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
bogdanm	89:552587b429a1	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	89:552587b429a1	265
bogdanm	89:552587b429a1	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
bogdanm	89:552587b429a1	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	89:552587b429a1	268
bogdanm	89:552587b429a1	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
bogdanm	89:552587b429a1	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	89:552587b429a1	271
bogdanm	89:552587b429a1	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
bogdanm	89:552587b429a1	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	89:552587b429a1	274
bogdanm	89:552587b429a1	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
bogdanm	89:552587b429a1	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	89:552587b429a1	277
bogdanm	89:552587b429a1	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
bogdanm	89:552587b429a1	279	to disable the clock before changing frequency.
bogdanm	89:552587b429a1	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	89:552587b429a1	281
bogdanm	89:552587b429a1	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
bogdanm	89:552587b429a1	283	commands during the CAS latency and stores data in the Read FIFO.
bogdanm	89:552587b429a1	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	89:552587b429a1	285
bogdanm	89:552587b429a1	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
bogdanm	89:552587b429a1	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
bogdanm	89:552587b429a1	288	}FMC_SDRAM_InitTypeDef;
bogdanm	89:552587b429a1	289
bogdanm	89:552587b429a1	290	/**
bogdanm	89:552587b429a1	291	* @brief FMC_SDRAM Timing parameters structure definition
bogdanm	89:552587b429a1	292	*/
bogdanm	89:552587b429a1	293	typedef struct
bogdanm	89:552587b429a1	294	{
bogdanm	89:552587b429a1	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
bogdanm	89:552587b429a1	296	an active or Refresh command in number of memory clock cycles.
bogdanm	89:552587b429a1	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	298
bogdanm	89:552587b429a1	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
bogdanm	89:552587b429a1	300	issuing the Activate command in number of memory clock cycles.
bogdanm	89:552587b429a1	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	302
bogdanm	89:552587b429a1	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
bogdanm	89:552587b429a1	304	cycles.
bogdanm	89:552587b429a1	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	306
bogdanm	89:552587b429a1	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
bogdanm	89:552587b429a1	308	and the delay between two consecutive Refresh commands in number of
bogdanm	89:552587b429a1	309	memory clock cycles.
bogdanm	89:552587b429a1	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	311
bogdanm	89:552587b429a1	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
bogdanm	89:552587b429a1	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	314
bogdanm	89:552587b429a1	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
bogdanm	89:552587b429a1	316	in number of memory clock cycles.
bogdanm	89:552587b429a1	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	318
bogdanm	89:552587b429a1	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
bogdanm	89:552587b429a1	320	command in number of memory clock cycles.
bogdanm	89:552587b429a1	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	322	}FMC_SDRAM_TimingTypeDef;
bogdanm	89:552587b429a1	323
bogdanm	89:552587b429a1	324	/**
bogdanm	89:552587b429a1	325	* @brief SDRAM command parameters structure definition
bogdanm	89:552587b429a1	326	*/
bogdanm	89:552587b429a1	327	typedef struct
bogdanm	89:552587b429a1	328	{
bogdanm	89:552587b429a1	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	89:552587b429a1	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	89:552587b429a1	331
bogdanm	89:552587b429a1	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	89:552587b429a1	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	89:552587b429a1	334
bogdanm	89:552587b429a1	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
bogdanm	89:552587b429a1	336	in auto refresh mode.
bogdanm	89:552587b429a1	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	89:552587b429a1	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
bogdanm	89:552587b429a1	339	}FMC_SDRAM_CommandTypeDef;
bogdanm	89:552587b429a1	340
bogdanm	89:552587b429a1	341	/* Exported constants --------------------------------------------------------*/
bogdanm	89:552587b429a1	342
bogdanm	89:552587b429a1	343	/** @defgroup FMC_NOR_SRAM_Controller
bogdanm	89:552587b429a1	344	* @{
bogdanm	89:552587b429a1	345	*/
bogdanm	89:552587b429a1	346
bogdanm	89:552587b429a1	347	/** @defgroup FMC_NORSRAM_Bank
bogdanm	89:552587b429a1	348	* @{
bogdanm	89:552587b429a1	349	*/
bogdanm	89:552587b429a1	350	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	351	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	352	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	353	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
bogdanm	89:552587b429a1	354
bogdanm	89:552587b429a1	355	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
bogdanm	89:552587b429a1	356	((BANK) == FMC_NORSRAM_BANK2) \|\| \
bogdanm	89:552587b429a1	357	((BANK) == FMC_NORSRAM_BANK3) \|\| \
bogdanm	89:552587b429a1	358	((BANK) == FMC_NORSRAM_BANK4))
bogdanm	89:552587b429a1	359	/**
bogdanm	89:552587b429a1	360	* @}
bogdanm	89:552587b429a1	361	*/
bogdanm	89:552587b429a1	362
bogdanm	89:552587b429a1	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing
bogdanm	89:552587b429a1	364	* @{
bogdanm	89:552587b429a1	365	*/
bogdanm	89:552587b429a1	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	368
bogdanm	89:552587b429a1	369	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
bogdanm	89:552587b429a1	370	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
bogdanm	89:552587b429a1	371	/**
bogdanm	89:552587b429a1	372	* @}
bogdanm	89:552587b429a1	373	*/
bogdanm	89:552587b429a1	374
bogdanm	89:552587b429a1	375	/** @defgroup FMC_Memory_Type
bogdanm	89:552587b429a1	376	* @{
bogdanm	89:552587b429a1	377	*/
bogdanm	89:552587b429a1	378	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	379	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	380	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	381
bogdanm	89:552587b429a1	382	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
bogdanm	89:552587b429a1	383	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
bogdanm	89:552587b429a1	384	((MEMORY) == FMC_MEMORY_TYPE_NOR))
bogdanm	89:552587b429a1	385	/**
bogdanm	89:552587b429a1	386	* @}
bogdanm	89:552587b429a1	387	*/
bogdanm	89:552587b429a1	388
bogdanm	89:552587b429a1	389	/** @defgroup FMC_NORSRAM_Data_Width
bogdanm	89:552587b429a1	390	* @{
bogdanm	89:552587b429a1	391	*/
bogdanm	89:552587b429a1	392	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	393	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	394	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	89:552587b429a1	395
bogdanm	89:552587b429a1	396	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	89:552587b429a1	397	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	89:552587b429a1	398	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
bogdanm	89:552587b429a1	399	/**
bogdanm	89:552587b429a1	400	* @}
bogdanm	89:552587b429a1	401	*/
bogdanm	89:552587b429a1	402
bogdanm	89:552587b429a1	403	/** @defgroup FMC_NORSRAM_Flash_Access
bogdanm	89:552587b429a1	404	* @{
bogdanm	89:552587b429a1	405	*/
bogdanm	89:552587b429a1	406	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	407	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	408	/**
bogdanm	89:552587b429a1	409	* @}
bogdanm	89:552587b429a1	410	*/
bogdanm	89:552587b429a1	411
bogdanm	89:552587b429a1	412	/** @defgroup FMC_Burst_Access_Mode
bogdanm	89:552587b429a1	413	* @{
bogdanm	89:552587b429a1	414	*/
bogdanm	89:552587b429a1	415	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	416	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
bogdanm	89:552587b429a1	417
bogdanm	89:552587b429a1	418	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
bogdanm	89:552587b429a1	419	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
bogdanm	89:552587b429a1	420	/**
bogdanm	89:552587b429a1	421	* @}
bogdanm	89:552587b429a1	422	*/
bogdanm	89:552587b429a1	423
bogdanm	89:552587b429a1	424
bogdanm	89:552587b429a1	425	/** @defgroup FMC_Wait_Signal_Polarity
bogdanm	89:552587b429a1	426	* @{
bogdanm	89:552587b429a1	427	*/
bogdanm	89:552587b429a1	428	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	429	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
bogdanm	89:552587b429a1	430
bogdanm	89:552587b429a1	431	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
bogdanm	89:552587b429a1	432	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
bogdanm	89:552587b429a1	433	/**
bogdanm	89:552587b429a1	434	* @}
bogdanm	89:552587b429a1	435	*/
bogdanm	89:552587b429a1	436
bogdanm	89:552587b429a1	437	/** @defgroup FMC_Wrap_Mode
bogdanm	89:552587b429a1	438	* @{
bogdanm	89:552587b429a1	439	*/
bogdanm	89:552587b429a1	440	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	441	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
bogdanm	89:552587b429a1	442
bogdanm	89:552587b429a1	443	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
bogdanm	89:552587b429a1	444	((MODE) == FMC_WRAP_MODE_ENABLE))
bogdanm	89:552587b429a1	445	/**
bogdanm	89:552587b429a1	446	* @}
bogdanm	89:552587b429a1	447	*/
bogdanm	89:552587b429a1	448
bogdanm	89:552587b429a1	449	/** @defgroup FMC_Wait_Timing
bogdanm	89:552587b429a1	450	* @{
bogdanm	89:552587b429a1	451	*/
bogdanm	89:552587b429a1	452	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	453	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
bogdanm	89:552587b429a1	454
bogdanm	89:552587b429a1	455	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
bogdanm	89:552587b429a1	456	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
bogdanm	89:552587b429a1	457	/**
bogdanm	89:552587b429a1	458	* @}
bogdanm	89:552587b429a1	459	*/
bogdanm	89:552587b429a1	460
bogdanm	89:552587b429a1	461	/** @defgroup FMC_Write_Operation
bogdanm	89:552587b429a1	462	* @{
bogdanm	89:552587b429a1	463	*/
bogdanm	89:552587b429a1	464	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	465	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
bogdanm	89:552587b429a1	466
bogdanm	89:552587b429a1	467	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
bogdanm	89:552587b429a1	468	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
bogdanm	89:552587b429a1	469	/**
bogdanm	89:552587b429a1	470	* @}
bogdanm	89:552587b429a1	471	*/
bogdanm	89:552587b429a1	472
bogdanm	89:552587b429a1	473	/** @defgroup FMC_Wait_Signal
bogdanm	89:552587b429a1	474	* @{
bogdanm	89:552587b429a1	475	*/
bogdanm	89:552587b429a1	476	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	477	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
bogdanm	89:552587b429a1	478
bogdanm	89:552587b429a1	479	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
bogdanm	89:552587b429a1	480	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
bogdanm	89:552587b429a1	481	/**
bogdanm	89:552587b429a1	482	* @}
bogdanm	89:552587b429a1	483	*/
bogdanm	89:552587b429a1	484
bogdanm	89:552587b429a1	485	/** @defgroup FMC_Extended_Mode
bogdanm	89:552587b429a1	486	* @{
bogdanm	89:552587b429a1	487	*/
bogdanm	89:552587b429a1	488	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	489	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
bogdanm	89:552587b429a1	490
bogdanm	89:552587b429a1	491	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
bogdanm	89:552587b429a1	492	((MODE) == FMC_EXTENDED_MODE_ENABLE))
bogdanm	89:552587b429a1	493	/**
bogdanm	89:552587b429a1	494	* @}
bogdanm	89:552587b429a1	495	*/
bogdanm	89:552587b429a1	496
bogdanm	89:552587b429a1	497	/** @defgroup FMC_AsynchronousWait
bogdanm	89:552587b429a1	498	* @{
bogdanm	89:552587b429a1	499	*/
bogdanm	89:552587b429a1	500	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	501	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
bogdanm	89:552587b429a1	502
bogdanm	89:552587b429a1	503	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
bogdanm	89:552587b429a1	504	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
bogdanm	89:552587b429a1	505	/**
bogdanm	89:552587b429a1	506	* @}
bogdanm	89:552587b429a1	507	*/
bogdanm	89:552587b429a1	508
bogdanm	89:552587b429a1	509	/** @defgroup FMC_Write_Burst
bogdanm	89:552587b429a1	510	* @{
bogdanm	89:552587b429a1	511	*/
bogdanm	89:552587b429a1	512	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	513	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
bogdanm	89:552587b429a1	514
bogdanm	89:552587b429a1	515	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
bogdanm	89:552587b429a1	516	((BURST) == FMC_WRITE_BURST_ENABLE))
bogdanm	89:552587b429a1	517	/**
bogdanm	89:552587b429a1	518	* @}
bogdanm	89:552587b429a1	519	*/
bogdanm	89:552587b429a1	520
bogdanm	89:552587b429a1	521	/** @defgroup FMC_Continous_Clock
bogdanm	89:552587b429a1	522	* @{
bogdanm	89:552587b429a1	523	*/
bogdanm	89:552587b429a1	524	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	525	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
bogdanm	89:552587b429a1	526
bogdanm	89:552587b429a1	527	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
bogdanm	89:552587b429a1	528	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
bogdanm	89:552587b429a1	529	/**
bogdanm	89:552587b429a1	530	* @}
bogdanm	89:552587b429a1	531	*/
bogdanm	89:552587b429a1	532
bogdanm	89:552587b429a1	533	/** @defgroup FMC_Address_Setup_Time
bogdanm	89:552587b429a1	534	* @{
bogdanm	89:552587b429a1	535	*/
bogdanm	89:552587b429a1	536	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
bogdanm	89:552587b429a1	537	/**
bogdanm	89:552587b429a1	538	* @}
bogdanm	89:552587b429a1	539	*/
bogdanm	89:552587b429a1	540
bogdanm	89:552587b429a1	541	/** @defgroup FMC_Address_Hold_Time
bogdanm	89:552587b429a1	542	* @{
bogdanm	89:552587b429a1	543	*/
bogdanm	89:552587b429a1	544	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
bogdanm	89:552587b429a1	545	/**
bogdanm	89:552587b429a1	546	* @}
bogdanm	89:552587b429a1	547	*/
bogdanm	89:552587b429a1	548
bogdanm	89:552587b429a1	549	/** @defgroup FMC_Data_Setup_Time
bogdanm	89:552587b429a1	550	* @{
bogdanm	89:552587b429a1	551	*/
bogdanm	89:552587b429a1	552	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
bogdanm	89:552587b429a1	553	/**
bogdanm	89:552587b429a1	554	* @}
bogdanm	89:552587b429a1	555	*/
bogdanm	89:552587b429a1	556
bogdanm	89:552587b429a1	557	/** @defgroup FMC_Bus_Turn_around_Duration
bogdanm	89:552587b429a1	558	* @{
bogdanm	89:552587b429a1	559	*/
bogdanm	89:552587b429a1	560	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
bogdanm	89:552587b429a1	561	/**
bogdanm	89:552587b429a1	562	* @}
bogdanm	89:552587b429a1	563	*/
bogdanm	89:552587b429a1	564
bogdanm	89:552587b429a1	565	/** @defgroup FMC_CLK_Division
bogdanm	89:552587b429a1	566	* @{
bogdanm	89:552587b429a1	567	*/
bogdanm	89:552587b429a1	568	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
bogdanm	89:552587b429a1	569	/**
bogdanm	89:552587b429a1	570	* @}
bogdanm	89:552587b429a1	571	*/
bogdanm	89:552587b429a1	572
bogdanm	89:552587b429a1	573	/** @defgroup FMC_Data_Latency
bogdanm	89:552587b429a1	574	* @{
bogdanm	89:552587b429a1	575	*/
bogdanm	89:552587b429a1	576	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
bogdanm	89:552587b429a1	577	/**
bogdanm	89:552587b429a1	578	* @}
bogdanm	89:552587b429a1	579	*/
bogdanm	89:552587b429a1	580
bogdanm	89:552587b429a1	581	/** @defgroup FMC_Access_Mode
bogdanm	89:552587b429a1	582	* @{
bogdanm	89:552587b429a1	583	*/
bogdanm	89:552587b429a1	584	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	585	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
bogdanm	89:552587b429a1	586	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
bogdanm	89:552587b429a1	587	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
bogdanm	89:552587b429a1	588
bogdanm	89:552587b429a1	589	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
bogdanm	89:552587b429a1	590	((MODE) == FMC_ACCESS_MODE_B) \|\| \
bogdanm	89:552587b429a1	591	((MODE) == FMC_ACCESS_MODE_C) \|\| \
bogdanm	89:552587b429a1	592	((MODE) == FMC_ACCESS_MODE_D))
bogdanm	89:552587b429a1	593	/**
bogdanm	89:552587b429a1	594	* @}
bogdanm	89:552587b429a1	595	*/
bogdanm	89:552587b429a1	596
bogdanm	89:552587b429a1	597	/**
bogdanm	89:552587b429a1	598	* @}
bogdanm	89:552587b429a1	599	*/
bogdanm	89:552587b429a1	600
bogdanm	89:552587b429a1	601	/** @defgroup FMC_NAND_Controller
bogdanm	89:552587b429a1	602	* @{
bogdanm	89:552587b429a1	603	*/
bogdanm	89:552587b429a1	604
bogdanm	89:552587b429a1	605	/** @defgroup FMC_NAND_Bank
bogdanm	89:552587b429a1	606	* @{
bogdanm	89:552587b429a1	607	*/
bogdanm	89:552587b429a1	608	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	609	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
bogdanm	89:552587b429a1	610
bogdanm	89:552587b429a1	611	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
bogdanm	89:552587b429a1	612	((BANK) == FMC_NAND_BANK3))
bogdanm	89:552587b429a1	613	/**
bogdanm	89:552587b429a1	614	* @}
bogdanm	89:552587b429a1	615	*/
bogdanm	89:552587b429a1	616
bogdanm	89:552587b429a1	617	/** @defgroup FMC_Wait_feature
bogdanm	89:552587b429a1	618	* @{
bogdanm	89:552587b429a1	619	*/
bogdanm	89:552587b429a1	620	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	621	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	622
bogdanm	89:552587b429a1	623	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
bogdanm	89:552587b429a1	624	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
bogdanm	89:552587b429a1	625	/**
bogdanm	89:552587b429a1	626	* @}
bogdanm	89:552587b429a1	627	*/
bogdanm	89:552587b429a1	628
bogdanm	89:552587b429a1	629	/** @defgroup FMC_PCR_Memory_Type
bogdanm	89:552587b429a1	630	* @{
bogdanm	89:552587b429a1	631	*/
bogdanm	89:552587b429a1	632	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	633	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	634	/**
bogdanm	89:552587b429a1	635	* @}
bogdanm	89:552587b429a1	636	*/
bogdanm	89:552587b429a1	637
bogdanm	89:552587b429a1	638	/** @defgroup FMC_NAND_Data_Width
bogdanm	89:552587b429a1	639	* @{
bogdanm	89:552587b429a1	640	*/
bogdanm	89:552587b429a1	641	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	642	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	643
bogdanm	89:552587b429a1	644	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
bogdanm	89:552587b429a1	645	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
bogdanm	89:552587b429a1	646	/**
bogdanm	89:552587b429a1	647	* @}
bogdanm	89:552587b429a1	648	*/
bogdanm	89:552587b429a1	649
bogdanm	89:552587b429a1	650	/** @defgroup FMC_ECC
bogdanm	89:552587b429a1	651	* @{
bogdanm	89:552587b429a1	652	*/
bogdanm	89:552587b429a1	653	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	654	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	655
bogdanm	89:552587b429a1	656	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
bogdanm	89:552587b429a1	657	((STATE) == FMC_NAND_ECC_ENABLE))
bogdanm	89:552587b429a1	658	/**
bogdanm	89:552587b429a1	659	* @}
bogdanm	89:552587b429a1	660	*/
bogdanm	89:552587b429a1	661
bogdanm	89:552587b429a1	662	/** @defgroup FMC_ECC_Page_Size
bogdanm	89:552587b429a1	663	* @{
bogdanm	89:552587b429a1	664	*/
bogdanm	89:552587b429a1	665	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	666	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
bogdanm	89:552587b429a1	667	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
bogdanm	89:552587b429a1	668	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
bogdanm	89:552587b429a1	669	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
bogdanm	89:552587b429a1	670	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
bogdanm	89:552587b429a1	671
bogdanm	89:552587b429a1	672	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
bogdanm	89:552587b429a1	673	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
bogdanm	89:552587b429a1	674	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
bogdanm	89:552587b429a1	675	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
bogdanm	89:552587b429a1	676	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
bogdanm	89:552587b429a1	677	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
bogdanm	89:552587b429a1	678	/**
bogdanm	89:552587b429a1	679	* @}
bogdanm	89:552587b429a1	680	*/
bogdanm	89:552587b429a1	681
bogdanm	89:552587b429a1	682	/** @defgroup FMC_TCLR_Setup_Time
bogdanm	89:552587b429a1	683	* @{
bogdanm	89:552587b429a1	684	*/
bogdanm	89:552587b429a1	685	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
bogdanm	89:552587b429a1	686	/**
bogdanm	89:552587b429a1	687	* @}
bogdanm	89:552587b429a1	688	*/
bogdanm	89:552587b429a1	689
bogdanm	89:552587b429a1	690	/** @defgroup FMC_TAR_Setup_Time
bogdanm	89:552587b429a1	691	* @{
bogdanm	89:552587b429a1	692	*/
bogdanm	89:552587b429a1	693	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
bogdanm	89:552587b429a1	694	/**
bogdanm	89:552587b429a1	695	* @}
bogdanm	89:552587b429a1	696	*/
bogdanm	89:552587b429a1	697
bogdanm	89:552587b429a1	698	/** @defgroup FMC_Setup_Time
bogdanm	89:552587b429a1	699	* @{
bogdanm	89:552587b429a1	700	*/
bogdanm	89:552587b429a1	701	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
bogdanm	89:552587b429a1	702	/**
bogdanm	89:552587b429a1	703	* @}
bogdanm	89:552587b429a1	704	*/
bogdanm	89:552587b429a1	705
bogdanm	89:552587b429a1	706	/** @defgroup FMC_Wait_Setup_Time
bogdanm	89:552587b429a1	707	* @{
bogdanm	89:552587b429a1	708	*/
bogdanm	89:552587b429a1	709	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
bogdanm	89:552587b429a1	710	/**
bogdanm	89:552587b429a1	711	* @}
bogdanm	89:552587b429a1	712	*/
bogdanm	89:552587b429a1	713
bogdanm	89:552587b429a1	714	/** @defgroup FMC_Hold_Setup_Time
bogdanm	89:552587b429a1	715	* @{
bogdanm	89:552587b429a1	716	*/
bogdanm	89:552587b429a1	717	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
bogdanm	89:552587b429a1	718	/**
bogdanm	89:552587b429a1	719	* @}
bogdanm	89:552587b429a1	720	*/
bogdanm	89:552587b429a1	721
bogdanm	89:552587b429a1	722	/** @defgroup FMC_HiZ_Setup_Time
bogdanm	89:552587b429a1	723	* @{
bogdanm	89:552587b429a1	724	*/
bogdanm	89:552587b429a1	725	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
bogdanm	89:552587b429a1	726	/**
bogdanm	89:552587b429a1	727	* @}
bogdanm	89:552587b429a1	728	*/
bogdanm	89:552587b429a1	729
bogdanm	89:552587b429a1	730	/**
bogdanm	89:552587b429a1	731	* @}
bogdanm	89:552587b429a1	732	*/
bogdanm	89:552587b429a1	733
bogdanm	89:552587b429a1	734	/** @defgroup FMC_SDRAM_Controller
bogdanm	89:552587b429a1	735	* @{
bogdanm	89:552587b429a1	736	*/
bogdanm	89:552587b429a1	737
bogdanm	89:552587b429a1	738	/** @defgroup FMC_SDRAM_Bank
bogdanm	89:552587b429a1	739	* @{
bogdanm	89:552587b429a1	740	*/
bogdanm	89:552587b429a1	741	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	742	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	743
bogdanm	89:552587b429a1	744	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
bogdanm	89:552587b429a1	745	((BANK) == FMC_SDRAM_BANK2))
bogdanm	89:552587b429a1	746	/**
bogdanm	89:552587b429a1	747	* @}
bogdanm	89:552587b429a1	748	*/
bogdanm	89:552587b429a1	749
bogdanm	89:552587b429a1	750	/** @defgroup FMC_SDRAM_Column_Bits_number
bogdanm	89:552587b429a1	751	* @{
bogdanm	89:552587b429a1	752	*/
bogdanm	89:552587b429a1	753	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	754	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	755	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	756	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
bogdanm	89:552587b429a1	757
bogdanm	89:552587b429a1	758	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
bogdanm	89:552587b429a1	759	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
bogdanm	89:552587b429a1	760	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
bogdanm	89:552587b429a1	761	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
bogdanm	89:552587b429a1	762	/**
bogdanm	89:552587b429a1	763	* @}
bogdanm	89:552587b429a1	764	*/
bogdanm	89:552587b429a1	765
bogdanm	89:552587b429a1	766	/** @defgroup FMC_SDRAM_Row_Bits_number
bogdanm	89:552587b429a1	767	* @{
bogdanm	89:552587b429a1	768	*/
bogdanm	89:552587b429a1	769	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	770	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	771	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	772
bogdanm	89:552587b429a1	773	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
bogdanm	89:552587b429a1	774	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
bogdanm	89:552587b429a1	775	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
bogdanm	89:552587b429a1	776	/**
bogdanm	89:552587b429a1	777	* @}
bogdanm	89:552587b429a1	778	*/
bogdanm	89:552587b429a1	779
bogdanm	89:552587b429a1	780	/** @defgroup FMC_SDRAM_Memory_Bus_Width
bogdanm	89:552587b429a1	781	* @{
bogdanm	89:552587b429a1	782	*/
bogdanm	89:552587b429a1	783	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	784	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	785	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
bogdanm	89:552587b429a1	786
bogdanm	89:552587b429a1	787	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
bogdanm	89:552587b429a1	788	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
bogdanm	89:552587b429a1	789	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
bogdanm	89:552587b429a1	790	/**
bogdanm	89:552587b429a1	791	* @}
bogdanm	89:552587b429a1	792	*/
bogdanm	89:552587b429a1	793
bogdanm	89:552587b429a1	794	/** @defgroup FMC_SDRAM_Internal_Banks_Number
bogdanm	89:552587b429a1	795	* @{
bogdanm	89:552587b429a1	796	*/
bogdanm	89:552587b429a1	797	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	798	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	799
bogdanm	89:552587b429a1	800	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
bogdanm	89:552587b429a1	801	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
bogdanm	89:552587b429a1	802	/**
bogdanm	89:552587b429a1	803	* @}
bogdanm	89:552587b429a1	804	*/
bogdanm	89:552587b429a1	805
bogdanm	89:552587b429a1	806	/** @defgroup FMC_SDRAM_CAS_Latency
bogdanm	89:552587b429a1	807	* @{
bogdanm	89:552587b429a1	808	*/
bogdanm	89:552587b429a1	809	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
bogdanm	89:552587b429a1	810	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
bogdanm	89:552587b429a1	811	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
bogdanm	89:552587b429a1	812
bogdanm	89:552587b429a1	813	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
bogdanm	89:552587b429a1	814	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
bogdanm	89:552587b429a1	815	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
bogdanm	89:552587b429a1	816	/**
bogdanm	89:552587b429a1	817	* @}
bogdanm	89:552587b429a1	818	*/
bogdanm	89:552587b429a1	819
bogdanm	89:552587b429a1	820	/** @defgroup FMC_SDRAM_Write_Protection
bogdanm	89:552587b429a1	821	* @{
bogdanm	89:552587b429a1	822	*/
bogdanm	89:552587b429a1	823	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	824	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
bogdanm	89:552587b429a1	825
bogdanm	89:552587b429a1	826	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
bogdanm	89:552587b429a1	827	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
bogdanm	89:552587b429a1	828	/**
bogdanm	89:552587b429a1	829	* @}
bogdanm	89:552587b429a1	830	*/
bogdanm	89:552587b429a1	831
bogdanm	89:552587b429a1	832	/** @defgroup FMC_SDRAM_Clock_Period
bogdanm	89:552587b429a1	833	* @{
bogdanm	89:552587b429a1	834	*/
bogdanm	89:552587b429a1	835	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	836	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
bogdanm	89:552587b429a1	837	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
bogdanm	89:552587b429a1	838
bogdanm	89:552587b429a1	839	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
bogdanm	89:552587b429a1	840	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
bogdanm	89:552587b429a1	841	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
bogdanm	89:552587b429a1	842	/**
bogdanm	89:552587b429a1	843	* @}
bogdanm	89:552587b429a1	844	*/
bogdanm	89:552587b429a1	845
bogdanm	89:552587b429a1	846	/** @defgroup FMC_SDRAM_Read_Burst
bogdanm	89:552587b429a1	847	* @{
bogdanm	89:552587b429a1	848	*/
bogdanm	89:552587b429a1	849	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	850	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
bogdanm	89:552587b429a1	851
bogdanm	89:552587b429a1	852	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
bogdanm	89:552587b429a1	853	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
bogdanm	89:552587b429a1	854	/**
bogdanm	89:552587b429a1	855	* @}
bogdanm	89:552587b429a1	856	*/
bogdanm	89:552587b429a1	857
bogdanm	89:552587b429a1	858	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
bogdanm	89:552587b429a1	859	* @{
bogdanm	89:552587b429a1	860	*/
bogdanm	89:552587b429a1	861	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	862	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
bogdanm	89:552587b429a1	863	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
bogdanm	89:552587b429a1	864
bogdanm	89:552587b429a1	865	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
bogdanm	89:552587b429a1	866	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
bogdanm	89:552587b429a1	867	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
bogdanm	89:552587b429a1	868	/**
bogdanm	89:552587b429a1	869	* @}
bogdanm	89:552587b429a1	870	*/
bogdanm	89:552587b429a1	871
bogdanm	89:552587b429a1	872	/** @defgroup FMC_SDRAM_LoadToActive_Delay
bogdanm	89:552587b429a1	873	* @{
bogdanm	89:552587b429a1	874	*/
bogdanm	89:552587b429a1	875	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	89:552587b429a1	876	/**
bogdanm	89:552587b429a1	877	* @}
bogdanm	89:552587b429a1	878	*/
bogdanm	89:552587b429a1	879
bogdanm	89:552587b429a1	880	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
bogdanm	89:552587b429a1	881	* @{
bogdanm	89:552587b429a1	882	*/
bogdanm	89:552587b429a1	883	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	89:552587b429a1	884	/**
bogdanm	89:552587b429a1	885	* @}
bogdanm	89:552587b429a1	886	*/
bogdanm	89:552587b429a1	887
bogdanm	89:552587b429a1	888	/** @defgroup FMC_SDRAM_SelfRefresh_Time
bogdanm	89:552587b429a1	889	* @{
bogdanm	89:552587b429a1	890	*/
bogdanm	89:552587b429a1	891	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm	89:552587b429a1	892	/**
bogdanm	89:552587b429a1	893	* @}
bogdanm	89:552587b429a1	894	*/
bogdanm	89:552587b429a1	895
bogdanm	89:552587b429a1	896	/** @defgroup FMC_SDRAM_RowCycle_Delay
bogdanm	89:552587b429a1	897	* @{
bogdanm	89:552587b429a1	898	*/
bogdanm	89:552587b429a1	899	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	89:552587b429a1	900	/**
bogdanm	89:552587b429a1	901	* @}
bogdanm	89:552587b429a1	902	*/
bogdanm	89:552587b429a1	903
bogdanm	89:552587b429a1	904	/** @defgroup FMC_SDRAM_Write_Recovery_Time
bogdanm	89:552587b429a1	905	* @{
bogdanm	89:552587b429a1	906	*/
bogdanm	89:552587b429a1	907	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
bogdanm	89:552587b429a1	908	/**
bogdanm	89:552587b429a1	909	* @}
bogdanm	89:552587b429a1	910	*/
bogdanm	89:552587b429a1	911
bogdanm	89:552587b429a1	912	/** @defgroup FMC_SDRAM_RP_Delay
bogdanm	89:552587b429a1	913	* @{
bogdanm	89:552587b429a1	914	*/
bogdanm	89:552587b429a1	915	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	89:552587b429a1	916	/**
bogdanm	89:552587b429a1	917	* @}
bogdanm	89:552587b429a1	918	*/
bogdanm	89:552587b429a1	919
bogdanm	89:552587b429a1	920	/** @defgroup FMC_SDRAM_RCD_Delay
bogdanm	89:552587b429a1	921	* @{
bogdanm	89:552587b429a1	922	*/
bogdanm	89:552587b429a1	923	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
bogdanm	89:552587b429a1	924
bogdanm	89:552587b429a1	925	/**
bogdanm	89:552587b429a1	926	* @}
bogdanm	89:552587b429a1	927	*/
bogdanm	89:552587b429a1	928
bogdanm	89:552587b429a1	929	/** @defgroup FMC_SDRAM_Command_Mode
bogdanm	89:552587b429a1	930	* @{
bogdanm	89:552587b429a1	931	*/
bogdanm	89:552587b429a1	932	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	933	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	934	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	935	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
bogdanm	89:552587b429a1	936	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	937	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
bogdanm	89:552587b429a1	938	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
bogdanm	89:552587b429a1	939
bogdanm	89:552587b429a1	940	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
bogdanm	89:552587b429a1	941	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
bogdanm	89:552587b429a1	942	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
bogdanm	89:552587b429a1	943	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
bogdanm	89:552587b429a1	944	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
bogdanm	89:552587b429a1	945	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
bogdanm	89:552587b429a1	946	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
bogdanm	89:552587b429a1	947	/**
bogdanm	89:552587b429a1	948	* @}
bogdanm	89:552587b429a1	949	*/
bogdanm	89:552587b429a1	950
bogdanm	89:552587b429a1	951	/** @defgroup FMC_SDRAM_Command_Target
bogdanm	89:552587b429a1	952	* @{
bogdanm	89:552587b429a1	953	*/
bogdanm	89:552587b429a1	954	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
bogdanm	89:552587b429a1	955	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
bogdanm	89:552587b429a1	956	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
bogdanm	89:552587b429a1	957
bogdanm	89:552587b429a1	958	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
bogdanm	89:552587b429a1	959	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
bogdanm	89:552587b429a1	960	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
bogdanm	89:552587b429a1	961	/**
bogdanm	89:552587b429a1	962	* @}
bogdanm	89:552587b429a1	963	*/
bogdanm	89:552587b429a1	964
bogdanm	89:552587b429a1	965	/** @defgroup FMC_SDRAM_AutoRefresh_Number
bogdanm	89:552587b429a1	966	* @{
bogdanm	89:552587b429a1	967	*/
bogdanm	89:552587b429a1	968	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
bogdanm	89:552587b429a1	969	/**
bogdanm	89:552587b429a1	970	* @}
bogdanm	89:552587b429a1	971	*/
bogdanm	89:552587b429a1	972
bogdanm	89:552587b429a1	973	/** @defgroup FMC_SDRAM_ModeRegister_Definition
bogdanm	89:552587b429a1	974	* @{
bogdanm	89:552587b429a1	975	*/
bogdanm	89:552587b429a1	976	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
bogdanm	89:552587b429a1	977	/**
bogdanm	89:552587b429a1	978	* @}
bogdanm	89:552587b429a1	979	*/
bogdanm	89:552587b429a1	980
bogdanm	89:552587b429a1	981	/** @defgroup FMC_SDRAM_Refresh_rate
bogdanm	89:552587b429a1	982	* @{
bogdanm	89:552587b429a1	983	*/
bogdanm	89:552587b429a1	984	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
bogdanm	89:552587b429a1	985	/**
bogdanm	89:552587b429a1	986	* @}
bogdanm	89:552587b429a1	987	*/
bogdanm	89:552587b429a1	988
bogdanm	89:552587b429a1	989	/** @defgroup FMC_SDRAM_Mode_Status
bogdanm	89:552587b429a1	990	* @{
bogdanm	89:552587b429a1	991	*/
bogdanm	89:552587b429a1	992	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
bogdanm	89:552587b429a1	993	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
bogdanm	89:552587b429a1	994	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
bogdanm	89:552587b429a1	995	/**
bogdanm	89:552587b429a1	996	* @}
bogdanm	89:552587b429a1	997	*/
bogdanm	89:552587b429a1	998
bogdanm	89:552587b429a1	999	/** @defgroup FMC_NORSRAM_Device_Instance
bogdanm	89:552587b429a1	1000	* @{
bogdanm	89:552587b429a1	1001	*/
bogdanm	89:552587b429a1	1002	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
bogdanm	89:552587b429a1	1003	/**
bogdanm	89:552587b429a1	1004	* @}
bogdanm	89:552587b429a1	1005	*/
bogdanm	89:552587b429a1	1006
bogdanm	89:552587b429a1	1007	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
bogdanm	89:552587b429a1	1008	* @{
bogdanm	89:552587b429a1	1009	*/
bogdanm	89:552587b429a1	1010	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
bogdanm	89:552587b429a1	1011	/**
bogdanm	89:552587b429a1	1012	* @}
bogdanm	89:552587b429a1	1013	*/
bogdanm	89:552587b429a1	1014
bogdanm	89:552587b429a1	1015	/** @defgroup FMC_NAND_Device_Instance
bogdanm	89:552587b429a1	1016	* @{
bogdanm	89:552587b429a1	1017	*/
bogdanm	89:552587b429a1	1018	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
bogdanm	89:552587b429a1	1019	/**
bogdanm	89:552587b429a1	1020	* @}
bogdanm	89:552587b429a1	1021	*/
bogdanm	89:552587b429a1	1022
bogdanm	89:552587b429a1	1023	/** @defgroup FMC_PCCARD_Device_Instance
bogdanm	89:552587b429a1	1024	* @{
bogdanm	89:552587b429a1	1025	*/
bogdanm	89:552587b429a1	1026	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
bogdanm	89:552587b429a1	1027	/**
bogdanm	89:552587b429a1	1028	* @}
bogdanm	89:552587b429a1	1029	*/
bogdanm	89:552587b429a1	1030
bogdanm	89:552587b429a1	1031	/** @defgroup FMC_SDRAM_Device_Instance
bogdanm	89:552587b429a1	1032	* @{
bogdanm	89:552587b429a1	1033	*/
bogdanm	89:552587b429a1	1034	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
bogdanm	89:552587b429a1	1035	/**
bogdanm	89:552587b429a1	1036	* @}
bogdanm	89:552587b429a1	1037	*/
bogdanm	89:552587b429a1	1038
bogdanm	89:552587b429a1	1039	/**
bogdanm	89:552587b429a1	1040	* @}
bogdanm	89:552587b429a1	1041	*/
bogdanm	89:552587b429a1	1042
bogdanm	89:552587b429a1	1043	/** @defgroup FMC_Interrupt_definition
bogdanm	89:552587b429a1	1044	* @brief FMC Interrupt definition
bogdanm	89:552587b429a1	1045	* @{
bogdanm	89:552587b429a1	1046	*/
bogdanm	89:552587b429a1	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
bogdanm	89:552587b429a1	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
bogdanm	89:552587b429a1	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
bogdanm	89:552587b429a1	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
bogdanm	89:552587b429a1	1051
bogdanm	89:552587b429a1	1052	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
bogdanm	89:552587b429a1	1053
bogdanm	89:552587b429a1	1054	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
bogdanm	89:552587b429a1	1055	((IT) == FMC_IT_LEVEL) \|\| \
bogdanm	89:552587b429a1	1056	((IT) == FMC_IT_FALLING_EDGE) \|\| \
bogdanm	89:552587b429a1	1057	((IT) == FMC_IT_REFRESH_ERROR))
bogdanm	89:552587b429a1	1058	/**
bogdanm	89:552587b429a1	1059	* @}
bogdanm	89:552587b429a1	1060	*/
bogdanm	89:552587b429a1	1061
bogdanm	89:552587b429a1	1062	/** @defgroup FMC_Flag_definition
bogdanm	89:552587b429a1	1063	* @brief FMC Flag definition
bogdanm	89:552587b429a1	1064	* @{
bogdanm	89:552587b429a1	1065	*/
bogdanm	89:552587b429a1	1066	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
bogdanm	89:552587b429a1	1067	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
bogdanm	89:552587b429a1	1068	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
bogdanm	89:552587b429a1	1069	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
bogdanm	89:552587b429a1	1070	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
bogdanm	89:552587b429a1	1071	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
bogdanm	89:552587b429a1	1072	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
bogdanm	89:552587b429a1	1073
bogdanm	89:552587b429a1	1074	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
bogdanm	89:552587b429a1	1075	((FLAG) == FMC_FLAG_LEVEL) \|\| \
bogdanm	89:552587b429a1	1076	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
bogdanm	89:552587b429a1	1077	((FLAG) == FMC_FLAG_FEMPT) \|\| \
bogdanm	89:552587b429a1	1078	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
bogdanm	89:552587b429a1	1079	((FLAG) == FMC_SDRAM_FLAG_BUSY))
bogdanm	89:552587b429a1	1080
bogdanm	89:552587b429a1	1081	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
bogdanm	89:552587b429a1	1082	/**
bogdanm	89:552587b429a1	1083	* @}
bogdanm	89:552587b429a1	1084	*/
bogdanm	89:552587b429a1	1085
bogdanm	89:552587b429a1	1086	/* Exported macro ------------------------------------------------------------*/
bogdanm	89:552587b429a1	1087
bogdanm	89:552587b429a1	1088	/** @defgroup FMC_NOR_Macros
bogdanm	89:552587b429a1	1089	* @brief macros to handle NOR device enable/disable and read/write operations
bogdanm	89:552587b429a1	1090	* @{
bogdanm	89:552587b429a1	1091	*/
bogdanm	89:552587b429a1	1092
bogdanm	89:552587b429a1	1093	/**
bogdanm	89:552587b429a1	1094	* @brief Enable the NORSRAM device access.
bogdanm	89:552587b429a1	1095	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	89:552587b429a1	1096	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	89:552587b429a1	1097	* @retval None
bogdanm	89:552587b429a1	1098	*/
bogdanm	89:552587b429a1	1099	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
bogdanm	89:552587b429a1	1100
bogdanm	89:552587b429a1	1101	/**
bogdanm	89:552587b429a1	1102	* @brief Disable the NORSRAM device access.
bogdanm	89:552587b429a1	1103	* @param __INSTANCE__: FMC_NORSRAM Instance
bogdanm	89:552587b429a1	1104	* @param __BANK__: FMC_NORSRAM Bank
bogdanm	89:552587b429a1	1105	* @retval None
bogdanm	89:552587b429a1	1106	*/
bogdanm	89:552587b429a1	1107	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
bogdanm	89:552587b429a1	1108
bogdanm	89:552587b429a1	1109	/**
bogdanm	89:552587b429a1	1110	* @}
bogdanm	89:552587b429a1	1111	*/
bogdanm	89:552587b429a1	1112
bogdanm	89:552587b429a1	1113	/** @defgroup FMC_NAND_Macros
bogdanm	89:552587b429a1	1114	* @brief macros to handle NAND device enable/disable
bogdanm	89:552587b429a1	1115	* @{
bogdanm	89:552587b429a1	1116	*/
bogdanm	89:552587b429a1	1117
bogdanm	89:552587b429a1	1118	/**
bogdanm	89:552587b429a1	1119	* @brief Enable the NAND device access.
bogdanm	89:552587b429a1	1120	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	89:552587b429a1	1121	* @param __BANK__: FMC_NAND Bank
bogdanm	89:552587b429a1	1122	* @retval None
bogdanm	89:552587b429a1	1123	*/
bogdanm	89:552587b429a1	1124	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	89:552587b429a1	1125	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
bogdanm	89:552587b429a1	1126
bogdanm	89:552587b429a1	1127	/**
bogdanm	89:552587b429a1	1128	* @brief Disable the NAND device access.
bogdanm	89:552587b429a1	1129	* @param __INSTANCE__: FMC_NAND Instance
bogdanm	89:552587b429a1	1130	* @param __BANK__: FMC_NAND Bank
bogdanm	89:552587b429a1	1131	* @retval None
bogdanm	89:552587b429a1	1132	*/
bogdanm	89:552587b429a1	1133	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm	89:552587b429a1	1134	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
bogdanm	89:552587b429a1	1135	/**
bogdanm	89:552587b429a1	1136	* @}
bogdanm	89:552587b429a1	1137	*/
bogdanm	89:552587b429a1	1138
bogdanm	89:552587b429a1	1139	/** @defgroup FMC_PCCARD_Macros
bogdanm	89:552587b429a1	1140	* @brief macros to handle SRAM read/write operations
bogdanm	89:552587b429a1	1141	* @{
bogdanm	89:552587b429a1	1142	*/
bogdanm	89:552587b429a1	1143
bogdanm	89:552587b429a1	1144	/**
bogdanm	89:552587b429a1	1145	* @brief Enable the PCCARD device access.
bogdanm	89:552587b429a1	1146	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	89:552587b429a1	1147	* @retval None
bogdanm	89:552587b429a1	1148	*/
bogdanm	89:552587b429a1	1149	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
bogdanm	89:552587b429a1	1150
bogdanm	89:552587b429a1	1151	/**
bogdanm	89:552587b429a1	1152	* @brief Disable the PCCARD device access.
bogdanm	89:552587b429a1	1153	* @param __INSTANCE__: FMC_PCCARD Instance
bogdanm	89:552587b429a1	1154	* @retval None
bogdanm	89:552587b429a1	1155	*/
bogdanm	89:552587b429a1	1156	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
bogdanm	89:552587b429a1	1157	/**
bogdanm	89:552587b429a1	1158	* @}
bogdanm	89:552587b429a1	1159	*/
bogdanm	89:552587b429a1	1160
bogdanm	89:552587b429a1	1161	/** @defgroup FMC_Interrupt
bogdanm	89:552587b429a1	1162	* @brief macros to handle FMC interrupts
bogdanm	89:552587b429a1	1163	* @{
bogdanm	89:552587b429a1	1164	*/
bogdanm	89:552587b429a1	1165
bogdanm	89:552587b429a1	1166	/**
bogdanm	89:552587b429a1	1167	* @brief Enable the NAND device interrupt.
bogdanm	89:552587b429a1	1168	* @param __INSTANCE__: FMC_NAND instance
bogdanm	89:552587b429a1	1169	* @param __BANK__: FMC_NAND Bank
bogdanm	89:552587b429a1	1170	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	89:552587b429a1	1171	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1172	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	89:552587b429a1	1173	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	89:552587b429a1	1174	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	89:552587b429a1	1175	* @retval None
bogdanm	89:552587b429a1	1176	*/
bogdanm	89:552587b429a1	1177	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
bogdanm	89:552587b429a1	1178	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
bogdanm	89:552587b429a1	1179
bogdanm	89:552587b429a1	1180	/**
bogdanm	89:552587b429a1	1181	* @brief Disable the NAND device interrupt.
bogdanm	89:552587b429a1	1182	* @param __INSTANCE__: FMC_NAND handle
bogdanm	89:552587b429a1	1183	* @param __BANK__: FMC_NAND Bank
bogdanm	89:552587b429a1	1184	* @param __INTERRUPT__: FMC_NAND interrupt
bogdanm	89:552587b429a1	1185	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1186	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	89:552587b429a1	1187	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	89:552587b429a1	1188	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	89:552587b429a1	1189	* @retval None
bogdanm	89:552587b429a1	1190	*/
bogdanm	89:552587b429a1	1191	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
bogdanm	89:552587b429a1	1192	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
bogdanm	89:552587b429a1	1193
bogdanm	89:552587b429a1	1194	/**
bogdanm	89:552587b429a1	1195	* @brief Get flag status of the NAND device.
bogdanm	89:552587b429a1	1196	* @param __INSTANCE__: FMC_NAND handle
bogdanm	89:552587b429a1	1197	* @param __BANK__: FMC_NAND Bank
bogdanm	89:552587b429a1	1198	* @param __FLAG__: FMC_NAND flag
bogdanm	89:552587b429a1	1199	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1200	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	89:552587b429a1	1201	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	89:552587b429a1	1202	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	89:552587b429a1	1203	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	89:552587b429a1	1204	* @retval The state of FLAG (SET or RESET).
bogdanm	89:552587b429a1	1205	*/
bogdanm	89:552587b429a1	1206	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
bogdanm	89:552587b429a1	1207	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
bogdanm	89:552587b429a1	1208	/**
bogdanm	89:552587b429a1	1209	* @brief Clear flag status of the NAND device.
bogdanm	89:552587b429a1	1210	* @param __INSTANCE__: FMC_NAND handle
bogdanm	89:552587b429a1	1211	* @param __BANK__: FMC_NAND Bank
bogdanm	89:552587b429a1	1212	* @param __FLAG__: FMC_NAND flag
bogdanm	89:552587b429a1	1213	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1214	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	89:552587b429a1	1215	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	89:552587b429a1	1216	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	89:552587b429a1	1217	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	89:552587b429a1	1218	* @retval None
bogdanm	89:552587b429a1	1219	*/
bogdanm	89:552587b429a1	1220	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
bogdanm	89:552587b429a1	1221	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
bogdanm	89:552587b429a1	1222	/**
bogdanm	89:552587b429a1	1223	* @brief Enable the PCCARD device interrupt.
bogdanm	89:552587b429a1	1224	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	89:552587b429a1	1225	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	89:552587b429a1	1226	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1227	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	89:552587b429a1	1228	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	89:552587b429a1	1229	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	89:552587b429a1	1230	* @retval None
bogdanm	89:552587b429a1	1231	*/
bogdanm	89:552587b429a1	1232	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
bogdanm	89:552587b429a1	1233
bogdanm	89:552587b429a1	1234	/**
bogdanm	89:552587b429a1	1235	* @brief Disable the PCCARD device interrupt.
bogdanm	89:552587b429a1	1236	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	89:552587b429a1	1237	* @param __INTERRUPT__: FMC_PCCARD interrupt
bogdanm	89:552587b429a1	1238	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1239	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
bogdanm	89:552587b429a1	1240	* @arg FMC_IT_LEVEL: Interrupt level.
bogdanm	89:552587b429a1	1241	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
bogdanm	89:552587b429a1	1242	* @retval None
bogdanm	89:552587b429a1	1243	*/
bogdanm	89:552587b429a1	1244	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
bogdanm	89:552587b429a1	1245
bogdanm	89:552587b429a1	1246	/**
bogdanm	89:552587b429a1	1247	* @brief Get flag status of the PCCARD device.
bogdanm	89:552587b429a1	1248	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	89:552587b429a1	1249	* @param __FLAG__: FMC_PCCARD flag
bogdanm	89:552587b429a1	1250	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1251	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	89:552587b429a1	1252	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	89:552587b429a1	1253	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	89:552587b429a1	1254	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	89:552587b429a1	1255	* @retval The state of FLAG (SET or RESET).
bogdanm	89:552587b429a1	1256	*/
bogdanm	89:552587b429a1	1257	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
bogdanm	89:552587b429a1	1258
bogdanm	89:552587b429a1	1259	/**
bogdanm	89:552587b429a1	1260	* @brief Clear flag status of the PCCARD device.
bogdanm	89:552587b429a1	1261	* @param __INSTANCE__: FMC_PCCARD instance
bogdanm	89:552587b429a1	1262	* @param __FLAG__: FMC_PCCARD flag
bogdanm	89:552587b429a1	1263	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1264	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
bogdanm	89:552587b429a1	1265	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
bogdanm	89:552587b429a1	1266	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
bogdanm	89:552587b429a1	1267	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
bogdanm	89:552587b429a1	1268	* @retval None
bogdanm	89:552587b429a1	1269	*/
bogdanm	89:552587b429a1	1270	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
bogdanm	89:552587b429a1	1271
bogdanm	89:552587b429a1	1272	/**
bogdanm	89:552587b429a1	1273	* @brief Enable the SDRAM device interrupt.
bogdanm	89:552587b429a1	1274	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	89:552587b429a1	1275	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	89:552587b429a1	1276	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1277	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	89:552587b429a1	1278	* @retval None
bogdanm	89:552587b429a1	1279	*/
bogdanm	89:552587b429a1	1280	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
bogdanm	89:552587b429a1	1281
bogdanm	89:552587b429a1	1282	/**
bogdanm	89:552587b429a1	1283	* @brief Disable the SDRAM device interrupt.
bogdanm	89:552587b429a1	1284	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	89:552587b429a1	1285	* @param __INTERRUPT__: FMC_SDRAM interrupt
bogdanm	89:552587b429a1	1286	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1287	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
bogdanm	89:552587b429a1	1288	* @retval None
bogdanm	89:552587b429a1	1289	*/
bogdanm	89:552587b429a1	1290	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
bogdanm	89:552587b429a1	1291
bogdanm	89:552587b429a1	1292	/**
bogdanm	89:552587b429a1	1293	* @brief Get flag status of the SDRAM device.
bogdanm	89:552587b429a1	1294	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	89:552587b429a1	1295	* @param __FLAG__: FMC_SDRAM flag
bogdanm	89:552587b429a1	1296	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1297	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
bogdanm	89:552587b429a1	1298	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
bogdanm	89:552587b429a1	1299	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
bogdanm	89:552587b429a1	1300	* @retval The state of FLAG (SET or RESET).
bogdanm	89:552587b429a1	1301	*/
bogdanm	89:552587b429a1	1302	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
bogdanm	89:552587b429a1	1303
bogdanm	89:552587b429a1	1304	/**
bogdanm	89:552587b429a1	1305	* @brief Clear flag status of the SDRAM device.
bogdanm	89:552587b429a1	1306	* @param __INSTANCE__: FMC_SDRAM instance
bogdanm	89:552587b429a1	1307	* @param __FLAG__: FMC_SDRAM flag
bogdanm	89:552587b429a1	1308	* This parameter can be any combination of the following values:
bogdanm	89:552587b429a1	1309	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
bogdanm	89:552587b429a1	1310	* @retval None
bogdanm	89:552587b429a1	1311	*/
bogdanm	89:552587b429a1	1312	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
bogdanm	89:552587b429a1	1313	/**
bogdanm	89:552587b429a1	1314	* @}
bogdanm	89:552587b429a1	1315	*/
bogdanm	89:552587b429a1	1316
bogdanm	89:552587b429a1	1317	/* Exported functions --------------------------------------------------------*/
bogdanm	89:552587b429a1	1318
bogdanm	89:552587b429a1	1319	/* FMC_NORSRAM Controller functions *******************************************/
bogdanm	89:552587b429a1	1320	/* Initialization/de-initialization functions */
bogdanm	89:552587b429a1	1321	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
bogdanm	89:552587b429a1	1322	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	89:552587b429a1	1323	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
bogdanm	89:552587b429a1	1324	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
bogdanm	89:552587b429a1	1325
bogdanm	89:552587b429a1	1326	/* FMC_NORSRAM Control functions */
bogdanm	89:552587b429a1	1327	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1328	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1329
bogdanm	89:552587b429a1	1330	/* FMC_NAND Controller functions **********************************************/
bogdanm	89:552587b429a1	1331	/* Initialization/de-initialization functions */
bogdanm	89:552587b429a1	1332	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
bogdanm	89:552587b429a1	1333	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	89:552587b429a1	1334	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
bogdanm	89:552587b429a1	1335	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1336
bogdanm	89:552587b429a1	1337	/* FMC_NAND Control functions */
bogdanm	89:552587b429a1	1338	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1339	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1340	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
bogdanm	89:552587b429a1	1341
bogdanm	89:552587b429a1	1342	/* FMC_PCCARD Controller functions ********************************************/
bogdanm	89:552587b429a1	1343	/* Initialization/de-initialization functions */
bogdanm	89:552587b429a1	1344	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
bogdanm	89:552587b429a1	1345	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	89:552587b429a1	1346	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	89:552587b429a1	1347	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
bogdanm	89:552587b429a1	1348	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
bogdanm	89:552587b429a1	1349
bogdanm	89:552587b429a1	1350	/* FMC_SDRAM Controller functions *********************************************/
bogdanm	89:552587b429a1	1351	/* Initialization/de-initialization functions */
bogdanm	89:552587b429a1	1352	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
bogdanm	89:552587b429a1	1353	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
bogdanm	89:552587b429a1	1354	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1355
bogdanm	89:552587b429a1	1356	/* FMC_SDRAM Control functions */
bogdanm	89:552587b429a1	1357	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1358	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1359	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
bogdanm	89:552587b429a1	1360	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
bogdanm	89:552587b429a1	1361	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
bogdanm	89:552587b429a1	1362	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
bogdanm	89:552587b429a1	1363
bogdanm	89:552587b429a1	1364	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	89:552587b429a1	1365	/**
bogdanm	89:552587b429a1	1366	* @}
bogdanm	89:552587b429a1	1367	*/
bogdanm	89:552587b429a1	1368
bogdanm	89:552587b429a1	1369	/**
bogdanm	89:552587b429a1	1370	* @}
bogdanm	89:552587b429a1	1371	*/
bogdanm	89:552587b429a1	1372
bogdanm	89:552587b429a1	1373	#ifdef __cplusplus
bogdanm	89:552587b429a1	1374	}
bogdanm	89:552587b429a1	1375	#endif
bogdanm	89:552587b429a1	1376
bogdanm	89:552587b429a1	1377	#endif /* __STM32F4xx_LL_FMC_H */
bogdanm	89:552587b429a1	1378
bogdanm	89:552587b429a1	1379	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
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TARGET_ARCH_MAX/stm32f4xx_ll_fmc.h@89:552587b429a1, 2014-09-12 (annotated)

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