Suga koubou / Mbed 2 deprecated XTouch-djay-bridge

X-TOUCH to djay bridge

Dependencies:   mbed mbed-rtos FATFileSystem

USBHost/targets/TARGET_NXP/USBHALHost_LPC17.cpp@1:0dac72ab5910, 2019-06-05 (annotated)

Committer:
okini3939
Date:
Wed Jun 05 04:54:37 2019 +0000
Revision:
1:0dac72ab5910
sample

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okini3939 1:0dac72ab5910 1 /* mbed USBHost Library
okini3939 1:0dac72ab5910 2 * Copyright (c) 2006-2013 ARM Limited
okini3939 1:0dac72ab5910 3 *
okini3939 1:0dac72ab5910 4 * Licensed under the Apache License, Version 2.0 (the "License");
okini3939 1:0dac72ab5910 5 * you may not use this file except in compliance with the License.
okini3939 1:0dac72ab5910 6 * You may obtain a copy of the License at
okini3939 1:0dac72ab5910 7 *
okini3939 1:0dac72ab5910 8 * http://www.apache.org/licenses/LICENSE-2.0
okini3939 1:0dac72ab5910 9 *
okini3939 1:0dac72ab5910 10 * Unless required by applicable law or agreed to in writing, software
okini3939 1:0dac72ab5910 11 * distributed under the License is distributed on an "AS IS" BASIS,
okini3939 1:0dac72ab5910 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
okini3939 1:0dac72ab5910 13 * See the License for the specific language governing permissions and
okini3939 1:0dac72ab5910 14 * limitations under the License.
okini3939 1:0dac72ab5910 15 */
okini3939 1:0dac72ab5910 16
okini3939 1:0dac72ab5910 17 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2460)
okini3939 1:0dac72ab5910 18
okini3939 1:0dac72ab5910 19 #include "mbed.h"
okini3939 1:0dac72ab5910 20 #include "USBHALHost.h"
okini3939 1:0dac72ab5910 21 #include "dbg.h"
okini3939 1:0dac72ab5910 22
okini3939 1:0dac72ab5910 23 // bits of the USB/OTG clock control register
okini3939 1:0dac72ab5910 24 #define HOST_CLK_EN (1<<0)
okini3939 1:0dac72ab5910 25 #define DEV_CLK_EN (1<<1)
okini3939 1:0dac72ab5910 26 #define PORTSEL_CLK_EN (1<<3)
okini3939 1:0dac72ab5910 27 #define AHB_CLK_EN (1<<4)
okini3939 1:0dac72ab5910 28
okini3939 1:0dac72ab5910 29 // bits of the USB/OTG clock status register
okini3939 1:0dac72ab5910 30 #define HOST_CLK_ON (1<<0)
okini3939 1:0dac72ab5910 31 #define DEV_CLK_ON (1<<1)
okini3939 1:0dac72ab5910 32 #define PORTSEL_CLK_ON (1<<3)
okini3939 1:0dac72ab5910 33 #define AHB_CLK_ON (1<<4)
okini3939 1:0dac72ab5910 34
okini3939 1:0dac72ab5910 35 // we need host clock, OTG/portsel clock and AHB clock
okini3939 1:0dac72ab5910 36 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
okini3939 1:0dac72ab5910 37
okini3939 1:0dac72ab5910 38 #define HCCA_SIZE sizeof(HCCA)
okini3939 1:0dac72ab5910 39 #define ED_SIZE sizeof(HCED)
okini3939 1:0dac72ab5910 40 #define TD_SIZE sizeof(HCTD)
okini3939 1:0dac72ab5910 41
okini3939 1:0dac72ab5910 42 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
okini3939 1:0dac72ab5910 43
okini3939 1:0dac72ab5910 44 static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
okini3939 1:0dac72ab5910 45
okini3939 1:0dac72ab5910 46 USBHALHost * USBHALHost::instHost;
okini3939 1:0dac72ab5910 47
okini3939 1:0dac72ab5910 48 USBHALHost::USBHALHost() {
okini3939 1:0dac72ab5910 49 instHost = this;
okini3939 1:0dac72ab5910 50 memInit();
okini3939 1:0dac72ab5910 51 memset((void*)usb_hcca, 0, HCCA_SIZE);
okini3939 1:0dac72ab5910 52 for (int i = 0; i < MAX_ENDPOINT; i++) {
okini3939 1:0dac72ab5910 53 edBufAlloc[i] = false;
okini3939 1:0dac72ab5910 54 }
okini3939 1:0dac72ab5910 55 for (int i = 0; i < MAX_TD; i++) {
okini3939 1:0dac72ab5910 56 tdBufAlloc[i] = false;
okini3939 1:0dac72ab5910 57 }
okini3939 1:0dac72ab5910 58 }
okini3939 1:0dac72ab5910 59
okini3939 1:0dac72ab5910 60 void USBHALHost::init() {
okini3939 1:0dac72ab5910 61 NVIC_DisableIRQ(USB_IRQn);
okini3939 1:0dac72ab5910 62
okini3939 1:0dac72ab5910 63 //Cut power
okini3939 1:0dac72ab5910 64 LPC_SC->PCONP &= ~(1UL<<31);
okini3939 1:0dac72ab5910 65 wait_ms(100);
okini3939 1:0dac72ab5910 66
okini3939 1:0dac72ab5910 67 // turn on power for USB
okini3939 1:0dac72ab5910 68 LPC_SC->PCONP |= (1UL<<31);
okini3939 1:0dac72ab5910 69
okini3939 1:0dac72ab5910 70 // Enable USB host clock, port selection and AHB clock
okini3939 1:0dac72ab5910 71 LPC_USB->USBClkCtrl |= CLOCK_MASK;
okini3939 1:0dac72ab5910 72
okini3939 1:0dac72ab5910 73 // Wait for clocks to become available
okini3939 1:0dac72ab5910 74 while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
okini3939 1:0dac72ab5910 75
okini3939 1:0dac72ab5910 76 // it seems the bits[0:1] mean the following
okini3939 1:0dac72ab5910 77 // 0: U1=device, U2=host
okini3939 1:0dac72ab5910 78 // 1: U1=host, U2=host
okini3939 1:0dac72ab5910 79 // 2: reserved
okini3939 1:0dac72ab5910 80 // 3: U1=host, U2=device
okini3939 1:0dac72ab5910 81 // NB: this register is only available if OTG clock (aka "port select") is enabled!!
okini3939 1:0dac72ab5910 82 // since we don't care about port 2, set just bit 0 to 1 (U1=host)
okini3939 1:0dac72ab5910 83 LPC_USB->OTGStCtrl |= 1;
okini3939 1:0dac72ab5910 84
okini3939 1:0dac72ab5910 85 // now that we've configured the ports, we can turn off the portsel clock
okini3939 1:0dac72ab5910 86 LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
okini3939 1:0dac72ab5910 87
okini3939 1:0dac72ab5910 88 // configure USB D+/D- pins
okini3939 1:0dac72ab5910 89 // P0[29] = USB_D+, 01
okini3939 1:0dac72ab5910 90 // P0[30] = USB_D-, 01
okini3939 1:0dac72ab5910 91 LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
okini3939 1:0dac72ab5910 92 LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
okini3939 1:0dac72ab5910 93
okini3939 1:0dac72ab5910 94 LPC_USB->HcControl = 0; // HARDWARE RESET
okini3939 1:0dac72ab5910 95 LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
okini3939 1:0dac72ab5910 96 LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
okini3939 1:0dac72ab5910 97
okini3939 1:0dac72ab5910 98 // Wait 100 ms before apply reset
okini3939 1:0dac72ab5910 99 wait_ms(100);
okini3939 1:0dac72ab5910 100
okini3939 1:0dac72ab5910 101 // software reset
okini3939 1:0dac72ab5910 102 LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
okini3939 1:0dac72ab5910 103
okini3939 1:0dac72ab5910 104 // Write Fm Interval and Largest Data Packet Counter
okini3939 1:0dac72ab5910 105 LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
okini3939 1:0dac72ab5910 106 LPC_USB->HcPeriodicStart = FI * 90 / 100;
okini3939 1:0dac72ab5910 107
okini3939 1:0dac72ab5910 108 // Put HC in operational state
okini3939 1:0dac72ab5910 109 LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
okini3939 1:0dac72ab5910 110 // Set Global Power
okini3939 1:0dac72ab5910 111 LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
okini3939 1:0dac72ab5910 112
okini3939 1:0dac72ab5910 113 LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
okini3939 1:0dac72ab5910 114
okini3939 1:0dac72ab5910 115 // Clear Interrrupt Status
okini3939 1:0dac72ab5910 116 LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
okini3939 1:0dac72ab5910 117
okini3939 1:0dac72ab5910 118 LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
okini3939 1:0dac72ab5910 119
okini3939 1:0dac72ab5910 120 // Enable the USB Interrupt
okini3939 1:0dac72ab5910 121 NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
okini3939 1:0dac72ab5910 122 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
okini3939 1:0dac72ab5910 123 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
okini3939 1:0dac72ab5910 124
okini3939 1:0dac72ab5910 125 NVIC_EnableIRQ(USB_IRQn);
okini3939 1:0dac72ab5910 126
okini3939 1:0dac72ab5910 127 // Check for any connected devices
okini3939 1:0dac72ab5910 128 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
okini3939 1:0dac72ab5910 129 //Device connected
okini3939 1:0dac72ab5910 130 wait_ms(150);
okini3939 1:0dac72ab5910 131 USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
okini3939 1:0dac72ab5910 132 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
okini3939 1:0dac72ab5910 133 }
okini3939 1:0dac72ab5910 134 }
okini3939 1:0dac72ab5910 135
okini3939 1:0dac72ab5910 136 uint32_t USBHALHost::controlHeadED() {
okini3939 1:0dac72ab5910 137 return LPC_USB->HcControlHeadED;
okini3939 1:0dac72ab5910 138 }
okini3939 1:0dac72ab5910 139
okini3939 1:0dac72ab5910 140 uint32_t USBHALHost::bulkHeadED() {
okini3939 1:0dac72ab5910 141 return LPC_USB->HcBulkHeadED;
okini3939 1:0dac72ab5910 142 }
okini3939 1:0dac72ab5910 143
okini3939 1:0dac72ab5910 144 uint32_t USBHALHost::interruptHeadED() {
okini3939 1:0dac72ab5910 145 return usb_hcca->IntTable[0];
okini3939 1:0dac72ab5910 146 }
okini3939 1:0dac72ab5910 147
okini3939 1:0dac72ab5910 148 void USBHALHost::updateBulkHeadED(uint32_t addr) {
okini3939 1:0dac72ab5910 149 LPC_USB->HcBulkHeadED = addr;
okini3939 1:0dac72ab5910 150 }
okini3939 1:0dac72ab5910 151
okini3939 1:0dac72ab5910 152
okini3939 1:0dac72ab5910 153 void USBHALHost::updateControlHeadED(uint32_t addr) {
okini3939 1:0dac72ab5910 154 LPC_USB->HcControlHeadED = addr;
okini3939 1:0dac72ab5910 155 }
okini3939 1:0dac72ab5910 156
okini3939 1:0dac72ab5910 157 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
okini3939 1:0dac72ab5910 158 usb_hcca->IntTable[0] = addr;
okini3939 1:0dac72ab5910 159 }
okini3939 1:0dac72ab5910 160
okini3939 1:0dac72ab5910 161
okini3939 1:0dac72ab5910 162 void USBHALHost::enableList(ENDPOINT_TYPE type) {
okini3939 1:0dac72ab5910 163 switch(type) {
okini3939 1:0dac72ab5910 164 case CONTROL_ENDPOINT:
okini3939 1:0dac72ab5910 165 LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
okini3939 1:0dac72ab5910 166 LPC_USB->HcControl |= OR_CONTROL_CLE;
okini3939 1:0dac72ab5910 167 break;
okini3939 1:0dac72ab5910 168 case ISOCHRONOUS_ENDPOINT:
okini3939 1:0dac72ab5910 169 break;
okini3939 1:0dac72ab5910 170 case BULK_ENDPOINT:
okini3939 1:0dac72ab5910 171 LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
okini3939 1:0dac72ab5910 172 LPC_USB->HcControl |= OR_CONTROL_BLE;
okini3939 1:0dac72ab5910 173 break;
okini3939 1:0dac72ab5910 174 case INTERRUPT_ENDPOINT:
okini3939 1:0dac72ab5910 175 LPC_USB->HcControl |= OR_CONTROL_PLE;
okini3939 1:0dac72ab5910 176 break;
okini3939 1:0dac72ab5910 177 }
okini3939 1:0dac72ab5910 178 }
okini3939 1:0dac72ab5910 179
okini3939 1:0dac72ab5910 180
okini3939 1:0dac72ab5910 181 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
okini3939 1:0dac72ab5910 182 switch(type) {
okini3939 1:0dac72ab5910 183 case CONTROL_ENDPOINT:
okini3939 1:0dac72ab5910 184 if(LPC_USB->HcControl & OR_CONTROL_CLE) {
okini3939 1:0dac72ab5910 185 LPC_USB->HcControl &= ~OR_CONTROL_CLE;
okini3939 1:0dac72ab5910 186 return true;
okini3939 1:0dac72ab5910 187 }
okini3939 1:0dac72ab5910 188 return false;
okini3939 1:0dac72ab5910 189 case ISOCHRONOUS_ENDPOINT:
okini3939 1:0dac72ab5910 190 return false;
okini3939 1:0dac72ab5910 191 case BULK_ENDPOINT:
okini3939 1:0dac72ab5910 192 if(LPC_USB->HcControl & OR_CONTROL_BLE){
okini3939 1:0dac72ab5910 193 LPC_USB->HcControl &= ~OR_CONTROL_BLE;
okini3939 1:0dac72ab5910 194 return true;
okini3939 1:0dac72ab5910 195 }
okini3939 1:0dac72ab5910 196 return false;
okini3939 1:0dac72ab5910 197 case INTERRUPT_ENDPOINT:
okini3939 1:0dac72ab5910 198 if(LPC_USB->HcControl & OR_CONTROL_PLE) {
okini3939 1:0dac72ab5910 199 LPC_USB->HcControl &= ~OR_CONTROL_PLE;
okini3939 1:0dac72ab5910 200 return true;
okini3939 1:0dac72ab5910 201 }
okini3939 1:0dac72ab5910 202 return false;
okini3939 1:0dac72ab5910 203 }
okini3939 1:0dac72ab5910 204 return false;
okini3939 1:0dac72ab5910 205 }
okini3939 1:0dac72ab5910 206
okini3939 1:0dac72ab5910 207
okini3939 1:0dac72ab5910 208 void USBHALHost::memInit() {
okini3939 1:0dac72ab5910 209 usb_hcca = (volatile HCCA *)usb_buf;
okini3939 1:0dac72ab5910 210 usb_edBuf = usb_buf + HCCA_SIZE;
okini3939 1:0dac72ab5910 211 usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
okini3939 1:0dac72ab5910 212 }
okini3939 1:0dac72ab5910 213
okini3939 1:0dac72ab5910 214 volatile uint8_t * USBHALHost::getED() {
okini3939 1:0dac72ab5910 215 for (int i = 0; i < MAX_ENDPOINT; i++) {
okini3939 1:0dac72ab5910 216 if ( !edBufAlloc[i] ) {
okini3939 1:0dac72ab5910 217 edBufAlloc[i] = true;
okini3939 1:0dac72ab5910 218 return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
okini3939 1:0dac72ab5910 219 }
okini3939 1:0dac72ab5910 220 }
okini3939 1:0dac72ab5910 221 perror("Could not allocate ED\r\n");
okini3939 1:0dac72ab5910 222 return NULL; //Could not alloc ED
okini3939 1:0dac72ab5910 223 }
okini3939 1:0dac72ab5910 224
okini3939 1:0dac72ab5910 225 volatile uint8_t * USBHALHost::getTD() {
okini3939 1:0dac72ab5910 226 int i;
okini3939 1:0dac72ab5910 227 for (i = 0; i < MAX_TD; i++) {
okini3939 1:0dac72ab5910 228 if ( !tdBufAlloc[i] ) {
okini3939 1:0dac72ab5910 229 tdBufAlloc[i] = true;
okini3939 1:0dac72ab5910 230 return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
okini3939 1:0dac72ab5910 231 }
okini3939 1:0dac72ab5910 232 }
okini3939 1:0dac72ab5910 233 perror("Could not allocate TD\r\n");
okini3939 1:0dac72ab5910 234 return NULL; //Could not alloc TD
okini3939 1:0dac72ab5910 235 }
okini3939 1:0dac72ab5910 236
okini3939 1:0dac72ab5910 237
okini3939 1:0dac72ab5910 238 void USBHALHost::freeED(volatile uint8_t * ed) {
okini3939 1:0dac72ab5910 239 int i;
okini3939 1:0dac72ab5910 240 i = (ed - usb_edBuf) / ED_SIZE;
okini3939 1:0dac72ab5910 241 edBufAlloc[i] = false;
okini3939 1:0dac72ab5910 242 }
okini3939 1:0dac72ab5910 243
okini3939 1:0dac72ab5910 244 void USBHALHost::freeTD(volatile uint8_t * td) {
okini3939 1:0dac72ab5910 245 int i;
okini3939 1:0dac72ab5910 246 i = (td - usb_tdBuf) / TD_SIZE;
okini3939 1:0dac72ab5910 247 tdBufAlloc[i] = false;
okini3939 1:0dac72ab5910 248 }
okini3939 1:0dac72ab5910 249
okini3939 1:0dac72ab5910 250
okini3939 1:0dac72ab5910 251 void USBHALHost::resetRootHub() {
okini3939 1:0dac72ab5910 252 // Initiate port reset
okini3939 1:0dac72ab5910 253 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
okini3939 1:0dac72ab5910 254
okini3939 1:0dac72ab5910 255 while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
okini3939 1:0dac72ab5910 256
okini3939 1:0dac72ab5910 257 // ...and clear port reset signal
okini3939 1:0dac72ab5910 258 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
okini3939 1:0dac72ab5910 259 }
okini3939 1:0dac72ab5910 260
okini3939 1:0dac72ab5910 261
okini3939 1:0dac72ab5910 262 void USBHALHost::_usbisr(void) {
okini3939 1:0dac72ab5910 263 if (instHost) {
okini3939 1:0dac72ab5910 264 instHost->UsbIrqhandler();
okini3939 1:0dac72ab5910 265 }
okini3939 1:0dac72ab5910 266 }
okini3939 1:0dac72ab5910 267
okini3939 1:0dac72ab5910 268 void USBHALHost::UsbIrqhandler() {
okini3939 1:0dac72ab5910 269 if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
okini3939 1:0dac72ab5910 270 {
okini3939 1:0dac72ab5910 271
okini3939 1:0dac72ab5910 272 uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
okini3939 1:0dac72ab5910 273
okini3939 1:0dac72ab5910 274 // Root hub status change interrupt
okini3939 1:0dac72ab5910 275 if (int_status & OR_INTR_STATUS_RHSC) {
okini3939 1:0dac72ab5910 276 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
okini3939 1:0dac72ab5910 277 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
okini3939 1:0dac72ab5910 278 // When DRWE is on, Connect Status Change
okini3939 1:0dac72ab5910 279 // means a remote wakeup event.
okini3939 1:0dac72ab5910 280 } else {
okini3939 1:0dac72ab5910 281
okini3939 1:0dac72ab5910 282 //Root device connected
okini3939 1:0dac72ab5910 283 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
okini3939 1:0dac72ab5910 284
okini3939 1:0dac72ab5910 285 // wait 150ms to avoid bounce
okini3939 1:0dac72ab5910 286 wait_ms(150);
okini3939 1:0dac72ab5910 287
okini3939 1:0dac72ab5910 288 //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
okini3939 1:0dac72ab5910 289 deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
okini3939 1:0dac72ab5910 290 }
okini3939 1:0dac72ab5910 291
okini3939 1:0dac72ab5910 292 //Root device disconnected
okini3939 1:0dac72ab5910 293 else {
okini3939 1:0dac72ab5910 294
okini3939 1:0dac72ab5910 295 if (!(int_status & OR_INTR_STATUS_WDH)) {
okini3939 1:0dac72ab5910 296 usb_hcca->DoneHead = 0;
okini3939 1:0dac72ab5910 297 }
okini3939 1:0dac72ab5910 298
okini3939 1:0dac72ab5910 299 // wait 200ms to avoid bounce
okini3939 1:0dac72ab5910 300 wait_ms(200);
okini3939 1:0dac72ab5910 301
okini3939 1:0dac72ab5910 302 deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
okini3939 1:0dac72ab5910 303
okini3939 1:0dac72ab5910 304 if (int_status & OR_INTR_STATUS_WDH) {
okini3939 1:0dac72ab5910 305 usb_hcca->DoneHead = 0;
okini3939 1:0dac72ab5910 306 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
okini3939 1:0dac72ab5910 307 }
okini3939 1:0dac72ab5910 308 }
okini3939 1:0dac72ab5910 309 }
okini3939 1:0dac72ab5910 310 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
okini3939 1:0dac72ab5910 311 }
okini3939 1:0dac72ab5910 312 if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
okini3939 1:0dac72ab5910 313 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
okini3939 1:0dac72ab5910 314 }
okini3939 1:0dac72ab5910 315 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
okini3939 1:0dac72ab5910 316 }
okini3939 1:0dac72ab5910 317
okini3939 1:0dac72ab5910 318 // Writeback Done Head interrupt
okini3939 1:0dac72ab5910 319 if (int_status & OR_INTR_STATUS_WDH) {
okini3939 1:0dac72ab5910 320 transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
okini3939 1:0dac72ab5910 321 LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
okini3939 1:0dac72ab5910 322 }
okini3939 1:0dac72ab5910 323 }
okini3939 1:0dac72ab5910 324 }
okini3939 1:0dac72ab5910 325 #endif