This is Webservice SDK for mbed. LPCXpresso1769/LPC1768/FRDM-K64F/LPC4088

Dependents:   MbedFileServer_1768MiniDK2 RedWireBridge IssueDebug_gcc MiMicRemoteMCU-for-Mbed ... more

libMiMic(MiMic library for mbed)は、WebService機能を提供するSDKです。 mbedでWebAPIに対応したネットワークデバイスを簡単に作ることが出来ます。

libMiMicはMiMic projectで開発しています。MiMic projectについてはこちらをご覧ください。 http://nyatla.jp/mimic/wp/

構成

libMiMicはmbedRTOS上で動作し、ユーザアプリケーションにAPIを提供します。コアAPIはC言語で記述されていますが、使用頻度の高いものについてはmbed向けのC++APIが準備されています。

/media/uploads/nyatla/libmimic-sdk.png

※libMiMicはmbedの標準イーサネットドライバをしようしていません。

標準イーサネットドライバと同時に使用することはできません。

  • MiMicIP - IPv4スタックです。レテンシとメモリ消費量を抑えたuipベースのライブラリです。
  • ARP/ICMP/UDP/TCP - 基礎的なソケットAPIを提供します。APIは独自です。
  • HTTP/1.1 Server - HTTP/1.1に対応したサーバです。マルチセッション・Chunked・持続性接続に対応しています。
  • HTTP Modules - HTTP/1.1の機能モジュールです。以下のモジュールがあります。
    • ROM file provider - ROMに格納したファイルイメージを公開します。
    • File system provider - mbedファイルシステムを公開します。
    • Onchip configuration - プログラムフラッシュを利用して設定を保存します。
    • MiMicVM processor - RPCリクエスト(MiMicVM)を処理します。
    • FileUpload - ファイルアップロードを受け取ります。
    • URL decoder - HTTPリクエストを解析します。
    • UPnP handler -UPnPメッセージを処理します。
    • WebSocket - Websocketサーバです。
  • mDNS - マルチキャストDNSサービスです。
  • UPnP - UPnP/1.0の機能を提供します。UPnP handlerと協調して動作します。(現在はデバイス探索(SSDP)・デスクリプション(Description)のみ実装してあります。)
  • DHCP/APIPA - ゼロコンフィギュレーション用のモジュールです。
  • HTTP/1.1 Client
  • mbed C++ class library - mbed向けのC++CPIです。C言語のものより簡単です。

対応機種

  • mbed(mbed LPC1768)
  • LPCXpresso1769

プログラム

Import programMiMicRemoteMCU-for-Mbed

MiMic RemoteMCU for mbed. This program provides MCU control API over REST API. It can control MCU from Javascript,PHP or any HTTP rest client directly. And, The application has self development environment.

Import programMbedFileServer

The program publishes files at local directory and SD filesystem. It is a full-fledged webServer somewhat.

サンプル

Import programMiMicSimpleHttpd

This is a simplest HTTP server made ​​of libMiMic. It will echo back a request path.

Import programUPnPBasicDevice

Simplest UPnP basic device example. This program to run UPnP basic device on the mbed.

Import programWebSocketSample

MiMicSDK Websocket module sample program.

Import programHttpClientSamlpe

A http client sample program.

Import programTcpSocketClientSamlpe

MiMicSDK Tcp client socket sample program.

Import programUdpSocketSamlpe

Udp socket sample program. This program will send back the received packet.

チュートリアル

English

libMiMic(MiMic library for mbed) is SDK which provides Webservice functions. It can be created networking device easily using mbed.

See more MiMic information, See MiMic project website. http://nyatla.jp/mimic/wp/

Structure

libMiMic run on mbed RTOS and provides networking API to user application. This library has C++ class API for the mbed, and low-level C language API.

/media/uploads/nyatla/libmimic-sdk.png

For WebService general, it can be written in a simple C + + API.

libMiMic does not have the standard Ethernet driver of mbed. It is not possible that will be used with the standard Ethernet driver.

  • MiMicIP - IPv4 protocol stack. This is based uip which is reduced memory and latency.
  • ARP / ICMP / UDP / TCP - Those are provide basic IP protocols.
  • HTTP/1.1 Server - The Http server compatible HTTP/1.1. It supports multi-session, chunked transport, persistent connection.
  • HTTP Modules - There are addon-module for HTTP server. The following modules.
    • ROM file module - Publish the file images in ROM.
    • File system module - Publish thefiles in mbed file system.
    • Onchip configuration module - To save the network settings to the program flash via REST.
    • MiMicVM module - To handle the (MiMicVM) RPC request.
    • FileUpload module - Accept a file via HTTP POST.
    • URL dedoce module - A versatility URL decoder.
    • UPnP handle module - To handle UPnP messages.
    • UPnP - This provides UPnP/1.0 device functions. It works together with UPnP handler.
    • Websocket - websocket (version13) server
  • mDNS Service - DNS-SD protocol server.
  • UPnP - This provides UPnP/1.0 device functions which works with UPnP handler. (You have been implemented (SSDP) ? description only (Description) device search now.) It is a module zero configuration for - DHCP / APIPA. mbed C + + class library - C of mbed for + + is the CPI. It is simple than that of the C language.
  • DHCP/APIPA - It support zero-cpnfigulation.
  • mbed C++ class library. Almost APIs for Web applications are available.
  • HTTP/1.1 Client

Supported target

  • mbed(mbed LPC1768)
  • LPCXpresso1769

Application

Import programMiMicRemoteMCU-for-Mbed

MiMic RemoteMCU for mbed. This program provides MCU control API over REST API. It can control MCU from Javascript,PHP or any HTTP rest client directly. And, The application has self development environment.

Import programMbedFileServer

The program publishes files at local directory and SD filesystem. It is a full-fledged webServer somewhat.

Sample

Import programMiMicSimpleHttpd

This is a simplest HTTP server made ​​of libMiMic. It will echo back a request path.

Import programUPnPBasicDevice

Simplest UPnP basic device example. This program to run UPnP basic device on the mbed.

Import programWebSocketSample

MiMicSDK Websocket module sample program.

Import programHttpClientSamlpe

A http client sample program.

Import programTcpSocketClientSamlpe

MiMicSDK Tcp client socket sample program.

Import programUdpSocketSamlpe

Udp socket sample program. This program will send back the received packet.

Tutorial

Committer:
nyatla
Date:
Sat Sep 27 13:33:26 2014 +0000
Revision:
91:db8279c869d3
Parent:
69:8c5f220441f5
NyLPC_TTxBufferHeader???????????????????; ???????????; K64F???????????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nyatla 68:f7def7eb5504 1 /*
nyatla 68:f7def7eb5504 2 * @file: EthDev_LPC17xx.h
nyatla 68:f7def7eb5504 3 * @purpose: Ethernet Device Definitions for NXP LPC17xx
nyatla 68:f7def7eb5504 4 * @version: V0.01
nyatla 68:f7def7eb5504 5 * @date: 14. May 2009
nyatla 68:f7def7eb5504 6 *----------------------------------------------------------------------------
nyatla 68:f7def7eb5504 7 *
nyatla 68:f7def7eb5504 8 * Copyright (C) 2009 ARM Limited. All rights reserved.
nyatla 68:f7def7eb5504 9 *
nyatla 68:f7def7eb5504 10 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
nyatla 68:f7def7eb5504 11 * processor based microcontrollers. This file can be freely distributed
nyatla 68:f7def7eb5504 12 * within development tools that are supporting such ARM based processors.
nyatla 68:f7def7eb5504 13 *
nyatla 68:f7def7eb5504 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
nyatla 68:f7def7eb5504 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
nyatla 68:f7def7eb5504 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
nyatla 68:f7def7eb5504 17 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
nyatla 68:f7def7eb5504 18 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
nyatla 68:f7def7eb5504 19 *
nyatla 68:f7def7eb5504 20 */
nyatla 68:f7def7eb5504 21 /*
nyatla 68:f7def7eb5504 22 * Modified by Kenji Arai August 29th, 2010 for XpressoLPC1768 LAN
nyatla 68:f7def7eb5504 23 *
nyatla 68:f7def7eb5504 24 * Changed LPC17xx.h then convert all "EMAC" to "LPC_EMAC"
nyatla 68:f7def7eb5504 25 *
nyatla 68:f7def7eb5504 26 * September 5th, 2010
nyatla 68:f7def7eb5504 27 */
nyatla 68:f7def7eb5504 28 /*
nyatla 68:f7def7eb5504 29 * Modified for MiMic by R.Iizuka. 2011.08.27
nyatla 68:f7def7eb5504 30 * http://nyatla.jp/mimic
nyatla 68:f7def7eb5504 31 */
nyatla 68:f7def7eb5504 32 #ifndef __ETHDEV_LPC17XX_H
nyatla 68:f7def7eb5504 33 #define __ETHDEV_LPC17XX_H
nyatla 68:f7def7eb5504 34
nyatla 68:f7def7eb5504 35 #include <stdint.h>
nyatla 68:f7def7eb5504 36 #include "NyLPC_stdlib.h"
nyatla 68:f7def7eb5504 37 #include "../NyLPC_IEthernetDevice.h"
nyatla 68:f7def7eb5504 38
nyatla 68:f7def7eb5504 39 #ifdef __cplusplus
nyatla 68:f7def7eb5504 40 extern "C" {
nyatla 68:f7def7eb5504 41 #endif /* __cplusplus */
nyatla 68:f7def7eb5504 42
nyatla 68:f7def7eb5504 43 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
nyatla 68:f7def7eb5504 44 #define NUM_RX_FRAG 3 /* Num.of RX Fragments. */
nyatla 68:f7def7eb5504 45 #define NUM_TX_FRAG 16 /* Num.of TX Fragments. */
nyatla 68:f7def7eb5504 46 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
nyatla 68:f7def7eb5504 47
nyatla 68:f7def7eb5504 48 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
nyatla 68:f7def7eb5504 49
nyatla 68:f7def7eb5504 50 typedef struct { /* RX Descriptor struct */
nyatla 68:f7def7eb5504 51 uint32_t Packet;
nyatla 68:f7def7eb5504 52 uint32_t Ctrl;
nyatla 68:f7def7eb5504 53 } RX_DESC_TypeDef;
nyatla 68:f7def7eb5504 54
nyatla 68:f7def7eb5504 55 typedef struct { /* RX Status struct */
nyatla 68:f7def7eb5504 56 uint32_t Info;
nyatla 68:f7def7eb5504 57 uint32_t HashCRC;
nyatla 68:f7def7eb5504 58 } RX_STAT_TypeDef;
nyatla 68:f7def7eb5504 59
nyatla 68:f7def7eb5504 60 typedef struct { /* TX Descriptor struct */
nyatla 68:f7def7eb5504 61 uint32_t Packet;
nyatla 68:f7def7eb5504 62 uint32_t Ctrl;
nyatla 68:f7def7eb5504 63 } TX_DESC_TypeDef;
nyatla 68:f7def7eb5504 64
nyatla 68:f7def7eb5504 65 typedef struct { /* TX Status struct */
nyatla 68:f7def7eb5504 66 uint32_t Info;
nyatla 68:f7def7eb5504 67 } TX_STAT_TypeDef;
nyatla 68:f7def7eb5504 68
nyatla 68:f7def7eb5504 69
nyatla 68:f7def7eb5504 70 /* EMAC variables located in AHB SRAM bank 1*/
nyatla 68:f7def7eb5504 71 #define AHB_SRAM_BANK1_BASE 0x2007c000UL
nyatla 68:f7def7eb5504 72 #define RX_DESC_BASE (AHB_SRAM_BANK1_BASE )
nyatla 68:f7def7eb5504 73 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_DESC_TypeDef */
nyatla 68:f7def7eb5504 74 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_STAT_TypeDef */
nyatla 68:f7def7eb5504 75 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*(2*4)) /* 2 * uint32_t, see TX_DESC_TypeDef */
nyatla 68:f7def7eb5504 76 #define ETH_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*(1*4)) /* 1 * uint32_t, see TX_STAT_TypeDef */
nyatla 68:f7def7eb5504 77
nyatla 68:f7def7eb5504 78 /**
nyatla 68:f7def7eb5504 79 * 消費メモリ量は、
nyatla 68:f7def7eb5504 80 * descriptor = NUM_RX_FRAG*16+NUM_TX_FRAG*12.
nyatla 68:f7def7eb5504 81 * EthnetBuf=ETH_FRAG_SIZE*NUM_RX_FRAG
nyatla 68:f7def7eb5504 82 */
nyatla 68:f7def7eb5504 83
nyatla 68:f7def7eb5504 84 /* RX and TX descriptor and status definitions. */
nyatla 68:f7def7eb5504 85 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
nyatla 68:f7def7eb5504 86 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
nyatla 68:f7def7eb5504 87 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
nyatla 68:f7def7eb5504 88 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
nyatla 68:f7def7eb5504 89 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
nyatla 68:f7def7eb5504 90 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
nyatla 68:f7def7eb5504 91 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
nyatla 68:f7def7eb5504 92 #define ETH_BUF(i) ( ETH_BUF_BASE + ETH_FRAG_SIZE*i )
nyatla 68:f7def7eb5504 93 #define ETH_NUM_BUFFERS ( NUM_TX_FRAG + NUM_RX_FRAG + 1 ) /* There are in fact 2 more buffers than descriptors as the two Tx descriptors use the same buffer to speed up the uip Tx. */
nyatla 68:f7def7eb5504 94
nyatla 68:f7def7eb5504 95
nyatla 68:f7def7eb5504 96 /* MAC Configuration Register 1 */
nyatla 68:f7def7eb5504 97 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
nyatla 68:f7def7eb5504 98 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
nyatla 68:f7def7eb5504 99 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
nyatla 68:f7def7eb5504 100 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
nyatla 68:f7def7eb5504 101 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
nyatla 68:f7def7eb5504 102 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
nyatla 68:f7def7eb5504 103 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
nyatla 68:f7def7eb5504 104 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
nyatla 68:f7def7eb5504 105 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
nyatla 68:f7def7eb5504 106 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
nyatla 68:f7def7eb5504 107 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
nyatla 68:f7def7eb5504 108
nyatla 68:f7def7eb5504 109 /* MAC Configuration Register 2 */
nyatla 68:f7def7eb5504 110 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
nyatla 68:f7def7eb5504 111 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
nyatla 68:f7def7eb5504 112 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
nyatla 68:f7def7eb5504 113 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
nyatla 68:f7def7eb5504 114 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
nyatla 68:f7def7eb5504 115 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
nyatla 68:f7def7eb5504 116 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
nyatla 68:f7def7eb5504 117 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
nyatla 68:f7def7eb5504 118 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
nyatla 68:f7def7eb5504 119 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
nyatla 68:f7def7eb5504 120 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
nyatla 68:f7def7eb5504 121 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
nyatla 68:f7def7eb5504 122 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
nyatla 68:f7def7eb5504 123
nyatla 68:f7def7eb5504 124 /* Back-to-Back Inter-Packet-Gap Register */
nyatla 68:f7def7eb5504 125 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
nyatla 68:f7def7eb5504 126 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
nyatla 68:f7def7eb5504 127
nyatla 68:f7def7eb5504 128 /* Non Back-to-Back Inter-Packet-Gap Register */
nyatla 68:f7def7eb5504 129 #define IPGR_DEF 0x00000012 /* Recommended value */
nyatla 68:f7def7eb5504 130
nyatla 68:f7def7eb5504 131 /* Collision Window/Retry Register */
nyatla 68:f7def7eb5504 132 #define CLRT_DEF 0x0000370F /* Default value */
nyatla 68:f7def7eb5504 133
nyatla 68:f7def7eb5504 134 /* PHY Support Register */
nyatla 68:f7def7eb5504 135 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
nyatla 68:f7def7eb5504 136 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
nyatla 68:f7def7eb5504 137
nyatla 68:f7def7eb5504 138 /* Test Register */
nyatla 68:f7def7eb5504 139 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
nyatla 68:f7def7eb5504 140 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
nyatla 68:f7def7eb5504 141 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
nyatla 68:f7def7eb5504 142
nyatla 68:f7def7eb5504 143 /* MII Management Configuration Register */
nyatla 68:f7def7eb5504 144 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
nyatla 68:f7def7eb5504 145 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
nyatla 68:f7def7eb5504 146 #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
nyatla 68:f7def7eb5504 147 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
nyatla 68:f7def7eb5504 148
nyatla 68:f7def7eb5504 149 #define MCFG_CLK_DIV4 0x00000000 /* MDC = hclk / 4 */
nyatla 68:f7def7eb5504 150 #define MCFG_CLK_DIV6 0x00000008 /* MDC = hclk / 6 */
nyatla 68:f7def7eb5504 151 #define MCFG_CLK_DIV8 0x0000000C /* MDC = hclk / 8 */
nyatla 68:f7def7eb5504 152 #define MCFG_CLK_DIV10 0x00000010 /* MDC = hclk / 10 */
nyatla 68:f7def7eb5504 153 #define MCFG_CLK_DIV14 0x00000014 /* MDC = hclk / 14 */
nyatla 68:f7def7eb5504 154 #define MCFG_CLK_DIV20 0x00000018 /* MDC = hclk / 20 */
nyatla 68:f7def7eb5504 155 #define MCFG_CLK_DIV28 0x0000001C /* MDC = hclk / 28 */
nyatla 68:f7def7eb5504 156
nyatla 68:f7def7eb5504 157 /* MII Management Command Register */
nyatla 68:f7def7eb5504 158 #define MCMD_READ 0x00000001 /* MII Read */
nyatla 68:f7def7eb5504 159 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
nyatla 68:f7def7eb5504 160
nyatla 68:f7def7eb5504 161 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
nyatla 68:f7def7eb5504 162 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
nyatla 68:f7def7eb5504 163
nyatla 68:f7def7eb5504 164 /* MII Management Address Register */
nyatla 68:f7def7eb5504 165 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
nyatla 68:f7def7eb5504 166 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
nyatla 68:f7def7eb5504 167
nyatla 68:f7def7eb5504 168 /* MII Management Indicators Register */
nyatla 68:f7def7eb5504 169 #define MIND_BUSY 0x00000001 /* MII is Busy */
nyatla 68:f7def7eb5504 170 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
nyatla 68:f7def7eb5504 171 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
nyatla 68:f7def7eb5504 172 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
nyatla 68:f7def7eb5504 173
nyatla 68:f7def7eb5504 174 /* Command Register */
nyatla 68:f7def7eb5504 175 #define CR_RX_EN 0x00000001 /* Enable Receive */
nyatla 68:f7def7eb5504 176 #define CR_TX_EN 0x00000002 /* Enable Transmit */
nyatla 68:f7def7eb5504 177 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
nyatla 68:f7def7eb5504 178 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
nyatla 68:f7def7eb5504 179 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
nyatla 68:f7def7eb5504 180 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
nyatla 68:f7def7eb5504 181 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
nyatla 68:f7def7eb5504 182 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
nyatla 68:f7def7eb5504 183 #define CR_RMII 0x00000200 /* Reduced MII Interface */
nyatla 68:f7def7eb5504 184 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
nyatla 68:f7def7eb5504 185
nyatla 68:f7def7eb5504 186 /* Status Register */
nyatla 68:f7def7eb5504 187 #define SR_RX_EN 0x00000001 /* Enable Receive */
nyatla 68:f7def7eb5504 188 #define SR_TX_EN 0x00000002 /* Enable Transmit */
nyatla 68:f7def7eb5504 189
nyatla 68:f7def7eb5504 190 /* Transmit Status Vector 0 Register */
nyatla 68:f7def7eb5504 191 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
nyatla 68:f7def7eb5504 192 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
nyatla 68:f7def7eb5504 193 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
nyatla 68:f7def7eb5504 194 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
nyatla 68:f7def7eb5504 195 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
nyatla 68:f7def7eb5504 196 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
nyatla 68:f7def7eb5504 197 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
nyatla 68:f7def7eb5504 198 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
nyatla 68:f7def7eb5504 199 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
nyatla 68:f7def7eb5504 200 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
nyatla 68:f7def7eb5504 201 #define TSV0_GIANT 0x00000400 /* Giant Frame */
nyatla 68:f7def7eb5504 202 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
nyatla 68:f7def7eb5504 203 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
nyatla 68:f7def7eb5504 204 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
nyatla 68:f7def7eb5504 205 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
nyatla 68:f7def7eb5504 206 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
nyatla 68:f7def7eb5504 207 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
nyatla 68:f7def7eb5504 208
nyatla 68:f7def7eb5504 209 /* Transmit Status Vector 1 Register */
nyatla 68:f7def7eb5504 210 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
nyatla 68:f7def7eb5504 211 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
nyatla 68:f7def7eb5504 212
nyatla 68:f7def7eb5504 213 /* Receive Status Vector Register */
nyatla 68:f7def7eb5504 214 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
nyatla 68:f7def7eb5504 215 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
nyatla 68:f7def7eb5504 216 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
nyatla 68:f7def7eb5504 217 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
nyatla 68:f7def7eb5504 218 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
nyatla 68:f7def7eb5504 219 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
nyatla 68:f7def7eb5504 220 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
nyatla 68:f7def7eb5504 221 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
nyatla 68:f7def7eb5504 222 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
nyatla 68:f7def7eb5504 223 #define RSV_MCAST 0x01000000 /* Multicast Frame */
nyatla 68:f7def7eb5504 224 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
nyatla 68:f7def7eb5504 225 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
nyatla 68:f7def7eb5504 226 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
nyatla 68:f7def7eb5504 227 #define RSV_PAUSE 0x10000000 /* Pause Frame */
nyatla 68:f7def7eb5504 228 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
nyatla 68:f7def7eb5504 229 #define RSV_VLAN 0x40000000 /* VLAN Frame */
nyatla 68:f7def7eb5504 230
nyatla 68:f7def7eb5504 231 /* Flow Control Counter Register */
nyatla 68:f7def7eb5504 232 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
nyatla 68:f7def7eb5504 233 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
nyatla 68:f7def7eb5504 234
nyatla 68:f7def7eb5504 235 /* Flow Control Status Register */
nyatla 68:f7def7eb5504 236 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
nyatla 68:f7def7eb5504 237
nyatla 68:f7def7eb5504 238 /* Receive Filter Control Register */
nyatla 68:f7def7eb5504 239 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
nyatla 68:f7def7eb5504 240 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
nyatla 68:f7def7eb5504 241 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
nyatla 68:f7def7eb5504 242 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
nyatla 68:f7def7eb5504 243 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
nyatla 68:f7def7eb5504 244 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
nyatla 68:f7def7eb5504 245 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
nyatla 68:f7def7eb5504 246 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
nyatla 68:f7def7eb5504 247
nyatla 68:f7def7eb5504 248 /* Receive Filter WoL Status/Clear Registers */
nyatla 68:f7def7eb5504 249 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
nyatla 68:f7def7eb5504 250 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
nyatla 68:f7def7eb5504 251 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
nyatla 68:f7def7eb5504 252 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
nyatla 68:f7def7eb5504 253 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
nyatla 68:f7def7eb5504 254 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
nyatla 68:f7def7eb5504 255 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
nyatla 68:f7def7eb5504 256 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
nyatla 68:f7def7eb5504 257
nyatla 68:f7def7eb5504 258 /* Interrupt Status/Enable/Clear/Set Registers */
nyatla 68:f7def7eb5504 259 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
nyatla 68:f7def7eb5504 260 #define INT_RX_ERR 0x00000002 /* Receive Error */
nyatla 68:f7def7eb5504 261 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
nyatla 68:f7def7eb5504 262 #define INT_RX_DONE 0x00000008 /* Receive Done */
nyatla 68:f7def7eb5504 263 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
nyatla 68:f7def7eb5504 264 #define INT_TX_ERR 0x00000020 /* Transmit Error */
nyatla 68:f7def7eb5504 265 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
nyatla 68:f7def7eb5504 266 #define INT_TX_DONE 0x00000080 /* Transmit Done */
nyatla 68:f7def7eb5504 267 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
nyatla 68:f7def7eb5504 268 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
nyatla 68:f7def7eb5504 269
nyatla 68:f7def7eb5504 270 /* Power Down Register */
nyatla 68:f7def7eb5504 271 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
nyatla 68:f7def7eb5504 272
nyatla 68:f7def7eb5504 273 /* RX Descriptor Control Word */
nyatla 68:f7def7eb5504 274 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
nyatla 68:f7def7eb5504 275 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
nyatla 68:f7def7eb5504 276
nyatla 68:f7def7eb5504 277 /* RX Status Hash CRC Word */
nyatla 68:f7def7eb5504 278 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
nyatla 68:f7def7eb5504 279 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
nyatla 68:f7def7eb5504 280
nyatla 68:f7def7eb5504 281 /* RX Status Information Word */
nyatla 68:f7def7eb5504 282 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
nyatla 68:f7def7eb5504 283 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
nyatla 68:f7def7eb5504 284 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
nyatla 68:f7def7eb5504 285 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
nyatla 68:f7def7eb5504 286 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
nyatla 68:f7def7eb5504 287 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
nyatla 68:f7def7eb5504 288 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
nyatla 68:f7def7eb5504 289 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
nyatla 68:f7def7eb5504 290 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
nyatla 68:f7def7eb5504 291 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
nyatla 68:f7def7eb5504 292 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
nyatla 68:f7def7eb5504 293 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
nyatla 68:f7def7eb5504 294 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
nyatla 68:f7def7eb5504 295 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
nyatla 68:f7def7eb5504 296 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
nyatla 68:f7def7eb5504 297
nyatla 68:f7def7eb5504 298 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
nyatla 68:f7def7eb5504 299 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
nyatla 68:f7def7eb5504 300
nyatla 68:f7def7eb5504 301 /* TX Descriptor Control Word */
nyatla 68:f7def7eb5504 302 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
nyatla 68:f7def7eb5504 303 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
nyatla 68:f7def7eb5504 304 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
nyatla 68:f7def7eb5504 305 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
nyatla 68:f7def7eb5504 306 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
nyatla 68:f7def7eb5504 307 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
nyatla 68:f7def7eb5504 308 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
nyatla 68:f7def7eb5504 309
nyatla 68:f7def7eb5504 310 /* TX Status Information Word */
nyatla 68:f7def7eb5504 311 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
nyatla 68:f7def7eb5504 312 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
nyatla 68:f7def7eb5504 313 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
nyatla 68:f7def7eb5504 314 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
nyatla 68:f7def7eb5504 315 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
nyatla 68:f7def7eb5504 316 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
nyatla 68:f7def7eb5504 317 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
nyatla 68:f7def7eb5504 318 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
nyatla 68:f7def7eb5504 319
nyatla 68:f7def7eb5504 320
nyatla 68:f7def7eb5504 321
nyatla 68:f7def7eb5504 322 void EthDev_LPC17xx_processTx(void);
nyatla 91:db8279c869d3 323 void EthDev_LPC17xx_sendTxEthFrame(void* i_buf,unsigned short i_size);
nyatla 68:f7def7eb5504 324 void* EthDev_LPC17xx_getRxEthFrame(unsigned short* o_len_of_data);
nyatla 68:f7def7eb5504 325 void EthDev_LPC17xx_nextRxEthFrame(void);
nyatla 68:f7def7eb5504 326
nyatla 69:8c5f220441f5 327 void EthDev_LPC17xx_prevTxDescriptor(void);
nyatla 69:8c5f220441f5 328 void EthDev_LPC17xx_prevRxDescriptor(void);
nyatla 69:8c5f220441f5 329 NyLPC_TBool EthDev_LPC17xx_prvWritePHY( long lPhyReg, long lValue );
nyatla 69:8c5f220441f5 330 unsigned short EthDev_LPC17xx_prvReadPHY( unsigned int ucPhyReg, NyLPC_TBool* plStatus );
nyatla 69:8c5f220441f5 331
nyatla 69:8c5f220441f5 332
nyatla 69:8c5f220441f5 333
nyatla 68:f7def7eb5504 334 #ifdef __cplusplus
nyatla 68:f7def7eb5504 335 }
nyatla 68:f7def7eb5504 336 #endif /* __cplusplus */
nyatla 68:f7def7eb5504 337
nyatla 68:f7def7eb5504 338 #endif
nyatla 68:f7def7eb5504 339 /*----------------------------------------------------------------------------
nyatla 68:f7def7eb5504 340 * end of file
nyatla 68:f7def7eb5504 341 *---------------------------------------------------------------------------*/