InetrfaceProducts NXP / Mbed 2 deprecated mini_board_PCU9669

mini board PCU9669 (and PCA9665) sample code

Dependencies:   mbed PCU9669 utility PCA9665 I2C_slaves parallel_bus

Fork of mini_board_PCU9669_old by InetrfaceProducts NXP

Sample code for PCU9669 (PCU9661, PCA9663, PCA9661 and PCA9665) evaluation board.

PCU9669 evaluation board: Mini board PCU9669
User manual is available -> http://www.nxp.com/documents/user_manual/UM10580.pdf

mini_board_libs/PCU9669/PCU9669_access.h@5:57c345099873, 2012-03-26 (annotated)

Committer:
nxp_ip
Date:
Mon Mar 26 06:17:23 2012 +0000
Revision:
5:57c345099873
tempolary version for trouble shooting

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nxp_ip 5:57c345099873 1 /** A sample code for "mini board PCU9669/PCA9665"
nxp_ip 5:57c345099873 2 *
nxp_ip 5:57c345099873 3 * @author Tedd OKANO, NXP Semiconductors
nxp_ip 5:57c345099873 4 * @version 0.9
nxp_ip 5:57c345099873 5 * @date 14-Feb-2011
nxp_ip 5:57c345099873 6 *
nxp_ip 5:57c345099873 7 * Released under the MIT License: http://mbed.org/license/mit
nxp_ip 5:57c345099873 8 *
nxp_ip 5:57c345099873 9 * An operation sample of PCU9669/PCA9665 I2C bus controller.
nxp_ip 5:57c345099873 10 * The mbed accesses the bus controller's parallel port (8/2 bit address and 8 bit data) by bit-banging.
nxp_ip 5:57c345099873 11 * The bit-banging is poerformed by PortInOut function of mbed library.
nxp_ip 5:57c345099873 12 *
nxp_ip 5:57c345099873 13 * To make the code porting easier, all codes are partitioned into layers to abstract other parts.
nxp_ip 5:57c345099873 14 * The mbed specific parts are concentrated in lowest layer: "hardware_abs.*".
nxp_ip 5:57c345099873 15 * This module may need to be modified for the porting.
nxp_ip 5:57c345099873 16 *
nxp_ip 5:57c345099873 17 * All other upper layers are writen in standard-C.
nxp_ip 5:57c345099873 18 *
nxp_ip 5:57c345099873 19 * base code is written from 05-Sep-2011 to 09-Sep-2011.
nxp_ip 5:57c345099873 20 * And demo code has been build on 11-Sep-2011.
nxp_ip 5:57c345099873 21 * Debug and code adjustment has been done on 08-Sep-2011.
nxp_ip 5:57c345099873 22 * Small sanitization for main.cpp. All mbed related codes are moved in to "hardware_abs.*". 13-Oct-2011
nxp_ip 5:57c345099873 23 * hardware_abs are moved into parallel_bus library folder, 3 LED driver operation sample 13-Feb.-2012
nxp_ip 5:57c345099873 24 * PCU9669 and PCA9665 codes are packed in a project 14-Feb-2012.
nxp_ip 5:57c345099873 25 *
nxp_ip 5:57c345099873 26 * Before builidng the code, please edit the file mini_board_PCU9669/config.h
nxp_ip 5:57c345099873 27 * Uncomment the target name what you want to target.
nxp_ip 5:57c345099873 28 */
nxp_ip 5:57c345099873 29
nxp_ip 5:57c345099873 30 /** PCU9669 abstraction layer module
nxp_ip 5:57c345099873 31 *
nxp_ip 5:57c345099873 32 * Common access method is abstracted in this module.
nxp_ip 5:57c345099873 33 * Each channel's registers, global registers and buffer access can be through these interface.
nxp_ip 5:57c345099873 34 * This module works on top of hardware abstraction layer.
nxp_ip 5:57c345099873 35 */
nxp_ip 5:57c345099873 36
nxp_ip 5:57c345099873 37 #ifndef __PCU9669_ACCESS__
nxp_ip 5:57c345099873 38 #define __PCU9669_ACCESS__
nxp_ip 5:57c345099873 39
nxp_ip 5:57c345099873 40 #include "hardware_abs.h"
nxp_ip 5:57c345099873 41
nxp_ip 5:57c345099873 42 /** @def PCU9669_ID / PCA9663_ID / TARGET_BUS_CONTROLLER
nxp_ip 5:57c345099873 43 *
nxp_ip 5:57c345099873 44 * Device IDs which can be read from DEVICE_ID register.
nxp_ip 5:57c345099873 45 * This value may need to be checked before the operation start.
nxp_ip 5:57c345099873 46 */
nxp_ip 5:57c345099873 47 #define PCU9669_ID 0xE9
nxp_ip 5:57c345099873 48 #define PCA9663_ID 0x63
nxp_ip 5:57c345099873 49 //#define TARGET_BUS_CONTROLLER PCA9663_ID
nxp_ip 5:57c345099873 50
nxp_ip 5:57c345099873 51 /** @def CH_FM_PLUS / CH_UFM1 / CH_UFM2
nxp_ip 5:57c345099873 52 *
nxp_ip 5:57c345099873 53 * Channel number abstracted by its characters.
nxp_ip 5:57c345099873 54 */
nxp_ip 5:57c345099873 55 #define CH_FM_PLUS 0
nxp_ip 5:57c345099873 56 #define CH_UFM1 1
nxp_ip 5:57c345099873 57 #define CH_UFM2 2
nxp_ip 5:57c345099873 58
nxp_ip 5:57c345099873 59 #define CH_0 0
nxp_ip 5:57c345099873 60 #define CH_1 1
nxp_ip 5:57c345099873 61 #define CH_2 2
nxp_ip 5:57c345099873 62
nxp_ip 5:57c345099873 63 /** @var Register names
nxp_ip 5:57c345099873 64 *
nxp_ip 5:57c345099873 65 * PCU9669/9663 internal register name and addesses
nxp_ip 5:57c345099873 66 */
nxp_ip 5:57c345099873 67 typedef enum {
nxp_ip 5:57c345099873 68
nxp_ip 5:57c345099873 69 // channel registers
nxp_ip 5:57c345099873 70
nxp_ip 5:57c345099873 71 CONTROL = 0x00, // These are register offsets. offset base CH0=0xC0, CH1=0xD0, CH2=0xE0
nxp_ip 5:57c345099873 72 CHSTATUS,
nxp_ip 5:57c345099873 73 INTMSK,
nxp_ip 5:57c345099873 74 SLATABLE,
nxp_ip 5:57c345099873 75 TRANCONFIG,
nxp_ip 5:57c345099873 76 DATA,
nxp_ip 5:57c345099873 77 TRANSEL,
nxp_ip 5:57c345099873 78 TRANOFS,
nxp_ip 5:57c345099873 79 BYTECOUNT,
nxp_ip 5:57c345099873 80 FRAMECNT,
nxp_ip 5:57c345099873 81 REFRATE,
nxp_ip 5:57c345099873 82 SCLL,
nxp_ip 5:57c345099873 83 SCLH,
nxp_ip 5:57c345099873 84 MODE,
nxp_ip 5:57c345099873 85 TIMEOUT,
nxp_ip 5:57c345099873 86 PRESET,
nxp_ip 5:57c345099873 87
nxp_ip 5:57c345099873 88 SCLPER = 0x0B,
nxp_ip 5:57c345099873 89 SDADLY = 0x0C,
nxp_ip 5:57c345099873 90 RESERVED = 0x0E,
nxp_ip 5:57c345099873 91
nxp_ip 5:57c345099873 92 // global registers
nxp_ip 5:57c345099873 93
nxp_ip 5:57c345099873 94 CTRLSTATUS = 0xF0,
nxp_ip 5:57c345099873 95 CTRLINTMSK,
nxp_ip 5:57c345099873 96 DEVICE_ID = 0xF6,
nxp_ip 5:57c345099873 97 CTRLPRESET,
nxp_ip 5:57c345099873 98 CTRLRDY = 0xFF,
nxp_ip 5:57c345099873 99
nxp_ip 5:57c345099873 100 OFFSET_CH0 = 0xC0,
nxp_ip 5:57c345099873 101 OFFSET_CH1 = 0xD0,
nxp_ip 5:57c345099873 102 OFFSET_CH2 = 0xE0,
nxp_ip 5:57c345099873 103
nxp_ip 5:57c345099873 104 } RegisterName;
nxp_ip 5:57c345099873 105
nxp_ip 5:57c345099873 106
nxp_ip 5:57c345099873 107 /** @var Devide ID code
nxp_ip 5:57c345099873 108 *
nxp_ip 5:57c345099873 109 * Keeps the value which is read from DEVICE_ID register
nxp_ip 5:57c345099873 110 */
nxp_ip 5:57c345099873 111 extern char device_id_code;
nxp_ip 5:57c345099873 112
nxp_ip 5:57c345099873 113
nxp_ip 5:57c345099873 114 /** Write channel register
nxp_ip 5:57c345099873 115 *
nxp_ip 5:57c345099873 116 * Writing 8 bit data into register in specified channel.
nxp_ip 5:57c345099873 117 * Register address offset of each channels is added in this function.
nxp_ip 5:57c345099873 118 *
nxp_ip 5:57c345099873 119 * @param ch target of channel: CH_FM_PLUS | CH_UFM1 | CH_UFM2
nxp_ip 5:57c345099873 120 * @param reg target channel register: RegisterName
nxp_ip 5:57c345099873 121 * @param val target of channel: 8 bit value
nxp_ip 5:57c345099873 122 * @see read_ch_register()
nxp_ip 5:57c345099873 123 */
nxp_ip 5:57c345099873 124 void write_ch_register( char ch, char reg, char val );
nxp_ip 5:57c345099873 125
nxp_ip 5:57c345099873 126 /** Read channel register
nxp_ip 5:57c345099873 127 *
nxp_ip 5:57c345099873 128 * Read 8 bit data from register in specified channel.
nxp_ip 5:57c345099873 129 * Register address offset of each channels is added in this function.
nxp_ip 5:57c345099873 130 *
nxp_ip 5:57c345099873 131 * @return 8 bit value from the register
nxp_ip 5:57c345099873 132 * @param ch target of channel: CH_FM_PLUS | CH_UFM1 | CH_UFM2
nxp_ip 5:57c345099873 133 * @param reg target channel register: RegisterName
nxp_ip 5:57c345099873 134 * @see write_ch_register()
nxp_ip 5:57c345099873 135 */
nxp_ip 5:57c345099873 136 char read_ch_register( char ch, char reg );
nxp_ip 5:57c345099873 137
nxp_ip 5:57c345099873 138 /** Starting the bus controller (i.e. PCU9669)
nxp_ip 5:57c345099873 139 *
nxp_ip 5:57c345099873 140 * Checks the bus controller get ready, and ChipID is correct
nxp_ip 5:57c345099873 141 * Then neccesary register initializations are done.
nxp_ip 5:57c345099873 142 * In this reference code, no register initialization done.
nxp_ip 5:57c345099873 143 * But if user need to do some, edit a module-private function "registers_initialize()" in "PCU9669_access.cpp"
nxp_ip 5:57c345099873 144 *
nxp_ip 5:57c345099873 145 * @return ZERO for no error, 1 for PCU9669 couldn't get ready after reset, 2 for ChipID was not match.
nxp_ip 5:57c345099873 146 */
nxp_ip 5:57c345099873 147 int start_bus_controller( char target_id );
nxp_ip 5:57c345099873 148
nxp_ip 5:57c345099873 149
nxp_ip 5:57c345099873 150 /** BURST_DATA_ACCESS option code
nxp_ip 5:57c345099873 151 *
nxp_ip 5:57c345099873 152 * Following code is enabled only when BURST_DATA_ACCESS is defined in "hardware_abs.h"
nxp_ip 5:57c345099873 153 */
nxp_ip 5:57c345099873 154 #ifdef BURST_DATA_ACCESS
nxp_ip 5:57c345099873 155
nxp_ip 5:57c345099873 156 /** @def PCU9669_BURST_DATA_ACCESS
nxp_ip 5:57c345099873 157 *
nxp_ip 5:57c345099873 158 * PCU9669_BURST_DATA_ACCESS is defied to let upper layer know the burst access is available.
nxp_ip 5:57c345099873 159 * This happens onlny BURST_DATA_ACCESS is defined in "hardware_abs.h"
nxp_ip 5:57c345099873 160 */
nxp_ip 5:57c345099873 161 #define PCU9669_BURST_DATA_ACCESS
nxp_ip 5:57c345099873 162
nxp_ip 5:57c345099873 163 /** Write channel register
nxp_ip 5:57c345099873 164 *
nxp_ip 5:57c345099873 165 * Write multiple bytes into a register in specified channel.
nxp_ip 5:57c345099873 166 * Register address offset of each channels is added in this function.
nxp_ip 5:57c345099873 167 *
nxp_ip 5:57c345099873 168 * @param ch target of channel: CH_FM_PLUS | CH_UFM1 | CH_UFM2
nxp_ip 5:57c345099873 169 * @param reg target channel register: RegisterName
nxp_ip 5:57c345099873 170 * @param *vp a pointer to char array. The data in the array will be written.
nxp_ip 5:57c345099873 171 * @param length length of the data (bytes)
nxp_ip 5:57c345099873 172 * @see read_ch_register_burst()
nxp_ip 5:57c345099873 173 */
nxp_ip 5:57c345099873 174 void write_ch_register_burst( char ch, char reg, char *vp, char length );
nxp_ip 5:57c345099873 175
nxp_ip 5:57c345099873 176 /** Read channel register
nxp_ip 5:57c345099873 177 *
nxp_ip 5:57c345099873 178 * Read multiple bytes from a register in specified channel.
nxp_ip 5:57c345099873 179 * Register address offset of each channels is added in this function.
nxp_ip 5:57c345099873 180 *
nxp_ip 5:57c345099873 181 * @param ch target of channel: CH_FM_PLUS | CH_UFM1 | CH_UFM2
nxp_ip 5:57c345099873 182 * @param reg target channel register: RegisterName
nxp_ip 5:57c345099873 183 * @param *vp a pointer to char array. The data will be read into this.
nxp_ip 5:57c345099873 184 * @param length length of the data (bytes)
nxp_ip 5:57c345099873 185 * @see write_ch_register_burst()
nxp_ip 5:57c345099873 186 */
nxp_ip 5:57c345099873 187 void read_ch_register_burst( char ch, char reg, char *vp, char length );
nxp_ip 5:57c345099873 188
nxp_ip 5:57c345099873 189 #endif // BURST_DATA_ACCESS
nxp_ip 5:57c345099873 190
nxp_ip 5:57c345099873 191 #endif // __PCU9669_ACCESS__
nxp_ip 5:57c345099873 192