Yuta Kitagami / Mbed 2 deprecated EtherCAT_Nucleo_F401

EtherCAT Slave Library (LAN9252) https://www.switch-science.com/catalog/6659/

Dependencies:   mbed

LAN9252.h@0:3516fed95f0b, 2021-01-18 (annotated)

Committer:
nonNoise
Date:
Mon Jan 18 03:46:20 2021 +0000
Revision:
0:3516fed95f0b
EtherCAT-Slave-Lib (LAN9252); Ver1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nonNoise 0:3516fed95f0b 1 /*
nonNoise 0:3516fed95f0b 2 * File: LAN9252.h
nonNoise 0:3516fed95f0b 3 * Author: kitagami
nonNoise 0:3516fed95f0b 4 *
nonNoise 0:3516fed95f0b 5 * Created on January 29, 2020, 9:11 PM
nonNoise 0:3516fed95f0b 6 */
nonNoise 0:3516fed95f0b 7
nonNoise 0:3516fed95f0b 8 #ifndef LAN9252_H
nonNoise 0:3516fed95f0b 9 #define LAN9252_H
nonNoise 0:3516fed95f0b 10
nonNoise 0:3516fed95f0b 11 #include <SPI.h>
nonNoise 0:3516fed95f0b 12 #include <stdint.h>
nonNoise 0:3516fed95f0b 13
nonNoise 0:3516fed95f0b 14 #define ECAT_PRAM_RD_DATA 0x000
nonNoise 0:3516fed95f0b 15 #define ECAT_PRAM_WR_DATA 0x020
nonNoise 0:3516fed95f0b 16 #define ID_REV 0x050
nonNoise 0:3516fed95f0b 17 #define IRQ_CFG 0x054
nonNoise 0:3516fed95f0b 18 #define INT_STS 0x058
nonNoise 0:3516fed95f0b 19 #define INT_EN 0x05C
nonNoise 0:3516fed95f0b 20 #define BYTE_TEST 0x064
nonNoise 0:3516fed95f0b 21 #define HW_CFG 0x074
nonNoise 0:3516fed95f0b 22 #define PMT_CTRL 0x084
nonNoise 0:3516fed95f0b 23 #define GPT_CFG 0x08C
nonNoise 0:3516fed95f0b 24 #define GPT_CNT 0x090
nonNoise 0:3516fed95f0b 25 #define FREE_RUN 0x09C
nonNoise 0:3516fed95f0b 26 #define RESET_CTL 0x1F8
nonNoise 0:3516fed95f0b 27
nonNoise 0:3516fed95f0b 28 #define ETHERCAT_RST 0x40
nonNoise 0:3516fed95f0b 29 #define PHY_B_RST 0x04
nonNoise 0:3516fed95f0b 30 #define PHY_A_RST 0x02
nonNoise 0:3516fed95f0b 31 #define DIGITAL_RST 0x01
nonNoise 0:3516fed95f0b 32
nonNoise 0:3516fed95f0b 33 #define ECAT_CSR_DATA 0x300
nonNoise 0:3516fed95f0b 34 #define ECAT_CSR_CMD 0x304
nonNoise 0:3516fed95f0b 35 #define CSR_BUSY 1<<31
nonNoise 0:3516fed95f0b 36 #define CSR_SIZE_8bit 1
nonNoise 0:3516fed95f0b 37 #define CSR_SIZE_16bit 2
nonNoise 0:3516fed95f0b 38 #define CSR_SIZE_32bit 4
nonNoise 0:3516fed95f0b 39 #define ECAT_PRAM_RD_ADDR_LEN 0x308
nonNoise 0:3516fed95f0b 40 #define ECAT_PRAM_RD_CMD 0x30C
nonNoise 0:3516fed95f0b 41 #define ECAT_PRAM_WR_ADDR_LEN 0x310
nonNoise 0:3516fed95f0b 42 #define ECAT_PRAM_WR_CMD 0x314
nonNoise 0:3516fed95f0b 43
nonNoise 0:3516fed95f0b 44 #define PRAM_READ_BUSY 1<<31
nonNoise 0:3516fed95f0b 45 #define PRAM_READ_ABORT 1<<30
nonNoise 0:3516fed95f0b 46 #define PRAM_WRITE_BUSY 1<<31
nonNoise 0:3516fed95f0b 47 #define PRAM_WRITE_ABORT 1<<30
nonNoise 0:3516fed95f0b 48
nonNoise 0:3516fed95f0b 49 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 50 // ESC Information
nonNoise 0:3516fed95f0b 51 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 52 #define Type_Register 0x0000
nonNoise 0:3516fed95f0b 53 #define Revision_Register 0x0001
nonNoise 0:3516fed95f0b 54 #define Build_Register 0x0002
nonNoise 0:3516fed95f0b 55 #define FMMUs_Supported 0x0004
nonNoise 0:3516fed95f0b 56 #define SyncManagers_Supported 0x0005
nonNoise 0:3516fed95f0b 57 #define RAM_Size 0x0006
nonNoise 0:3516fed95f0b 58 #define Port_Descriptor 0x0007
nonNoise 0:3516fed95f0b 59 #define ESC_Features_Supported 0x0008
nonNoise 0:3516fed95f0b 60 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 61 // Station Address
nonNoise 0:3516fed95f0b 62 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 63 #define Configured_Station 0x0010
nonNoise 0:3516fed95f0b 64 #define Configured_Station_Alias 0x0012
nonNoise 0:3516fed95f0b 65 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 66 // Write Protection
nonNoise 0:3516fed95f0b 67 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 68 #define Write_Enable 0x0020
nonNoise 0:3516fed95f0b 69 #define Write_Protection 0x0021
nonNoise 0:3516fed95f0b 70 #define ESC_Write_Enable 0x0030
nonNoise 0:3516fed95f0b 71 #define ESC_Write_Protection 0x0031
nonNoise 0:3516fed95f0b 72 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 73 // Data Link Layer
nonNoise 0:3516fed95f0b 74 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 75 #define ESC_Reset_ECAT 0x0040
nonNoise 0:3516fed95f0b 76 #define ESC_Reset_PDI 0x0041
nonNoise 0:3516fed95f0b 77 #define ESC_DL_Control 0x0100
nonNoise 0:3516fed95f0b 78 #define Physical_Read_Write_Offset 0x0108
nonNoise 0:3516fed95f0b 79 #define ESC_DL_Status 0x0110
nonNoise 0:3516fed95f0b 80 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 81 // Application Layer
nonNoise 0:3516fed95f0b 82 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 83 #define AL_Control 0x0120
nonNoise 0:3516fed95f0b 84 #define AL_Status 0x0130
nonNoise 0:3516fed95f0b 85 #define AL_Status_Code 0x0134
nonNoise 0:3516fed95f0b 86 #define RUN_LED_Override 0x0138
nonNoise 0:3516fed95f0b 87 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 88 // PDI (Process Data Interface)
nonNoise 0:3516fed95f0b 89 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 90 #define PDI_Control 0x0140
nonNoise 0:3516fed95f0b 91 #define ESC_Configuration 0x0141
nonNoise 0:3516fed95f0b 92 #define ASIC_Configuration 0x0142
nonNoise 0:3516fed95f0b 93 #define PDI_Configuration 0x0150
nonNoise 0:3516fed95f0b 94 #define Sync_Latch_PDI_Configuration 0x0151
nonNoise 0:3516fed95f0b 95 #define Extended_PDI_Configuration 0x0152
nonNoise 0:3516fed95f0b 96 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 97 //Interrupts
nonNoise 0:3516fed95f0b 98 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 99 #define ECAT_Event_Mask 0x0200
nonNoise 0:3516fed95f0b 100 #define AL_Event_Mask 0x0204
nonNoise 0:3516fed95f0b 101 #define ECAT_Event_Request 0x0210
nonNoise 0:3516fed95f0b 102 #define AL_Event_Request 0x0220
nonNoise 0:3516fed95f0b 103 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 104 // Error Counters
nonNoise 0:3516fed95f0b 105 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 106 #define RX_Error_Counters 0x0300
nonNoise 0:3516fed95f0b 107 #define Forwarded_RX_Error_Counters 0x0308
nonNoise 0:3516fed95f0b 108 #define ECAT_Processing_Unit_Error_Counter 0x030C
nonNoise 0:3516fed95f0b 109 #define PDI_Error_Counter 0x030D
nonNoise 0:3516fed95f0b 110 #define PDI_Error_Code 0x030E
nonNoise 0:3516fed95f0b 111 #define Lost_Link_Counters 0x0310
nonNoise 0:3516fed95f0b 112 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 113 // Watchdogs
nonNoise 0:3516fed95f0b 114 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 115 #define Watchdog_Time_PDI 0x0410
nonNoise 0:3516fed95f0b 116 #define Watchdog_Time_Process_Data 0x0420
nonNoise 0:3516fed95f0b 117 #define Watchdog_Status_Process_Data 0x0440
nonNoise 0:3516fed95f0b 118 #define Watchdog_Counter_Process_Data 0x0442
nonNoise 0:3516fed95f0b 119 #define Watchdog_Counter_PDI 0x0443
nonNoise 0:3516fed95f0b 120 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 121 // EEPROM Interface
nonNoise 0:3516fed95f0b 122 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 123 #define EEPROM_Configuration 0x0500
nonNoise 0:3516fed95f0b 124 #define EEPROM_PDI_Access_State 0x0501
nonNoise 0:3516fed95f0b 125 #define EEPROM_Control_Status 0x0502
nonNoise 0:3516fed95f0b 126 #define EEPROM_Address 0x0504
nonNoise 0:3516fed95f0b 127 #define EEPROM_Data 0x0508
nonNoise 0:3516fed95f0b 128 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 129 // MII Management Interface
nonNoise 0:3516fed95f0b 130 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 131 #define MII_Management_Control_Status 0x0510
nonNoise 0:3516fed95f0b 132 #define PHY_Address 0x0512
nonNoise 0:3516fed95f0b 133 #define PHY_Register_Address 0x0513
nonNoise 0:3516fed95f0b 134 #define PHY_DATA 0x0514
nonNoise 0:3516fed95f0b 135 #define MII_Management_ECAT_Access_State 0x0516
nonNoise 0:3516fed95f0b 136 #define MII_Management_PDI_Access_State 0x0517
nonNoise 0:3516fed95f0b 137 #define PHY_Port_Statuss 0x0518
nonNoise 0:3516fed95f0b 138 /*=========================================================
nonNoise 0:3516fed95f0b 139 0600h FMMU[2:0]s (3x16 bytes)
nonNoise 0:3516fed95f0b 140 +0h-3h FMMUx Logical Start Address
nonNoise 0:3516fed95f0b 141 +4h-5h FMMUx Length
nonNoise 0:3516fed95f0b 142 +6h FMMUx Logical Start Bit
nonNoise 0:3516fed95f0b 143 +7h FMMUx Logical Stop Bit
nonNoise 0:3516fed95f0b 144 +8h-9h FMMUx Physical Start Address
nonNoise 0:3516fed95f0b 145 +Ah FMMUx Physical Start Bit
nonNoise 0:3516fed95f0b 146 +Bh FMMUx Type
nonNoise 0:3516fed95f0b 147 +Ch FMMUx Activate
nonNoise 0:3516fed95f0b 148 +Dh-Fh FMMUx Reserved
nonNoise 0:3516fed95f0b 149 0800h-081Fh SyncManager[3:0]s (4x8 bytes)
nonNoise 0:3516fed95f0b 150 +0h-1h SyncManager x Physical Start Address
nonNoise 0:3516fed95f0b 151 +2h-3h SyncManager x Length
nonNoise 0:3516fed95f0b 152 +4h SyncManager x Control
nonNoise 0:3516fed95f0b 153 +5h SyncManager x Status
nonNoise 0:3516fed95f0b 154 +6h SyncManager x Activate
nonNoise 0:3516fed95f0b 155 +7h SyncManager x PDI Control
nonNoise 0:3516fed95f0b 156 ===========================================================*/
nonNoise 0:3516fed95f0b 157 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 158 // Distributed Clocks - Receive Times
nonNoise 0:3516fed95f0b 159 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 160 #define Receive_Time_Port_0 0x0900
nonNoise 0:3516fed95f0b 161 #define Receive_Time_Port_1 0x0904
nonNoise 0:3516fed95f0b 162 #define Receive_Time_Port_2 0x0908
nonNoise 0:3516fed95f0b 163 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 164 //Distributed Clocks - Time Loop Control Unit
nonNoise 0:3516fed95f0b 165 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 166 #define System_Time 0x0910
nonNoise 0:3516fed95f0b 167 #define Receive_Time_ECAT_Processing_Unit 0x0918
nonNoise 0:3516fed95f0b 168 #define System_Time_Offset 0x0920
nonNoise 0:3516fed95f0b 169 #define System_Time_Delay 0x0928
nonNoise 0:3516fed95f0b 170 #define System_Time_Difference 0x092C
nonNoise 0:3516fed95f0b 171 #define Speed_Counter_Start 0x0930
nonNoise 0:3516fed95f0b 172 #define Speed_Counter_Diff 0x0932
nonNoise 0:3516fed95f0b 173 #define System_Time_Difference_Filter_Depth 0x0934
nonNoise 0:3516fed95f0b 174 #define Speed_Counter_Filter_Depth 0x0935
nonNoise 0:3516fed95f0b 175 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 176 // Distributed Clocks - Cyclic Unit Control
nonNoise 0:3516fed95f0b 177 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 178 #define Cyclic Unit Control 0x0980
nonNoise 0:3516fed95f0b 179 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 180 // Distributed Clocks - SYNC Out Unit
nonNoise 0:3516fed95f0b 181 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 182 #define Activation 0x0981
nonNoise 0:3516fed95f0b 183 #define Pulse_Length_of_SyncSignals 0x0982
nonNoise 0:3516fed95f0b 184 #define Activation_Status 0x0984
nonNoise 0:3516fed95f0b 185 #define SYNC0_Status 0x098E
nonNoise 0:3516fed95f0b 186 #define SYNC1_Status 0x098F
nonNoise 0:3516fed95f0b 187 #define Start_Time_Cyclic_Operation 0x0990
nonNoise 0:3516fed95f0b 188 #define Next_SYNC1_Pulse 0x0998
nonNoise 0:3516fed95f0b 189 #define SYNC0_Cycle_Time 0x09A0
nonNoise 0:3516fed95f0b 190 #define SYNC1_Cycle_Time 0x09A4
nonNoise 0:3516fed95f0b 191 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 192 // Distributed Clocks - Latch In Unit
nonNoise 0:3516fed95f0b 193 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 194 #define LATCH0_Control 0x09A8
nonNoise 0:3516fed95f0b 195 #define LATCH1_Control 0x09A9
nonNoise 0:3516fed95f0b 196 #define LATCH0_Status 0x09AE
nonNoise 0:3516fed95f0b 197 #define LATCH1_Status 0x09AF
nonNoise 0:3516fed95f0b 198 #define LATCH0_Time_Positive_Edge 0x09B0
nonNoise 0:3516fed95f0b 199 #define LATCH0_Time_Negative_Edge 0x09B8
nonNoise 0:3516fed95f0b 200 #define LATCH1_Time_Positive_Edge 0x09C0
nonNoise 0:3516fed95f0b 201 #define LATCH1_Time_Negative_Edge 0x09C8
nonNoise 0:3516fed95f0b 202 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 203 // Distributed Clocks - SyncManager Event Times
nonNoise 0:3516fed95f0b 204 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 205 #define EtherCAT_Buffer_Change_Event_Time 0x09F0
nonNoise 0:3516fed95f0b 206 #define PDI_Buffer_Start_Time_Event 0x09F8
nonNoise 0:3516fed95f0b 207 #define PDI_Buffer_Change_Event_Time 0x09FC
nonNoise 0:3516fed95f0b 208 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 209 // ESC Specific
nonNoise 0:3516fed95f0b 210 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 211 #define Product_ID 0x0E00
nonNoise 0:3516fed95f0b 212 #define Vendor_ID 0x0E08
nonNoise 0:3516fed95f0b 213 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 214 // Digital Input/Output
nonNoise 0:3516fed95f0b 215 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 216 #define Digital_IO_Output_Data 0x0F00
nonNoise 0:3516fed95f0b 217 #define General_Purpose_Output 0x0F10
nonNoise 0:3516fed95f0b 218 #define General_Purpose_Input 0x0F18
nonNoise 0:3516fed95f0b 219 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 220 // User RAM
nonNoise 0:3516fed95f0b 221 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 222 #define User_RAM 0x0F80
nonNoise 0:3516fed95f0b 223 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 224 // Process Data RAM
nonNoise 0:3516fed95f0b 225 //-----------------------------------------------------------------------//
nonNoise 0:3516fed95f0b 226 #define Process_Data_RAM 0x1000
nonNoise 0:3516fed95f0b 227
nonNoise 0:3516fed95f0b 228 void LAN9252_RESET(void);
nonNoise 0:3516fed95f0b 229 void LAN9252_EtherCAT_CSR_WRITE(uint8_t CSR_SIZE,uint16_t CSR_ADDR,uint32_t CSR_DATA);
nonNoise 0:3516fed95f0b 230 uint32_t LAN9252_EtherCAT_CSR_READ(uint8_t CSR_SIZE,uint16_t CSR_ADDR);
nonNoise 0:3516fed95f0b 231 uint32_t LAN9252_EtherCAT_PRAM_READ(uint16_t PRAM_READ_LEN,uint16_t PRAM_READ_ADDR);
nonNoise 0:3516fed95f0b 232 void LAN9252_EtherCAT_PRAM_WRITE(uint16_t PRAM_WRITE_LEN,uint16_t PRAM_WRITE_ADDR, uint32_t PRAM_WR_DATA);
nonNoise 0:3516fed95f0b 233
nonNoise 0:3516fed95f0b 234
nonNoise 0:3516fed95f0b 235
nonNoise 0:3516fed95f0b 236 #endif /* LAN9252_H */
nonNoise 0:3516fed95f0b 237
nonNoise 0:3516fed95f0b 238