Sertel_Srinath Gopalan / TARGET_LPC1768i2c

myi2c test

core_cm4_simd.h@0:559a8e4aab60, 2015-06-29 (annotated)

Committer:
mrsoundhar
Date:
Mon Jun 29 12:59:52 2015 +0000
Revision:
0:559a8e4aab60
i2c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mrsoundhar 0:559a8e4aab60 1 /**************************************************************************//**
mrsoundhar 0:559a8e4aab60 2 * @file core_cm4_simd.h
mrsoundhar 0:559a8e4aab60 3 * @brief CMSIS Cortex-M4 SIMD Header File
mrsoundhar 0:559a8e4aab60 4 * @version V3.20
mrsoundhar 0:559a8e4aab60 5 * @date 25. February 2013
mrsoundhar 0:559a8e4aab60 6 *
mrsoundhar 0:559a8e4aab60 7 * @note
mrsoundhar 0:559a8e4aab60 8 *
mrsoundhar 0:559a8e4aab60 9 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:559a8e4aab60 11
mrsoundhar 0:559a8e4aab60 12 All rights reserved.
mrsoundhar 0:559a8e4aab60 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:559a8e4aab60 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:559a8e4aab60 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:559a8e4aab60 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:559a8e4aab60 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:559a8e4aab60 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:559a8e4aab60 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:559a8e4aab60 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:559a8e4aab60 21 to endorse or promote products derived from this software without
mrsoundhar 0:559a8e4aab60 22 specific prior written permission.
mrsoundhar 0:559a8e4aab60 23 *
mrsoundhar 0:559a8e4aab60 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:559a8e4aab60 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:559a8e4aab60 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:559a8e4aab60 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:559a8e4aab60 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:559a8e4aab60 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:559a8e4aab60 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:559a8e4aab60 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:559a8e4aab60 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:559a8e4aab60 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:559a8e4aab60 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:559a8e4aab60 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 36
mrsoundhar 0:559a8e4aab60 37
mrsoundhar 0:559a8e4aab60 38 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 39 extern "C" {
mrsoundhar 0:559a8e4aab60 40 #endif
mrsoundhar 0:559a8e4aab60 41
mrsoundhar 0:559a8e4aab60 42 #ifndef __CORE_CM4_SIMD_H
mrsoundhar 0:559a8e4aab60 43 #define __CORE_CM4_SIMD_H
mrsoundhar 0:559a8e4aab60 44
mrsoundhar 0:559a8e4aab60 45
mrsoundhar 0:559a8e4aab60 46 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 47 * Hardware Abstraction Layer
mrsoundhar 0:559a8e4aab60 48 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 49
mrsoundhar 0:559a8e4aab60 50
mrsoundhar 0:559a8e4aab60 51 /* ################### Compiler specific Intrinsics ########################### */
mrsoundhar 0:559a8e4aab60 52 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
mrsoundhar 0:559a8e4aab60 53 Access to dedicated SIMD instructions
mrsoundhar 0:559a8e4aab60 54 @{
mrsoundhar 0:559a8e4aab60 55 */
mrsoundhar 0:559a8e4aab60 56
mrsoundhar 0:559a8e4aab60 57 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mrsoundhar 0:559a8e4aab60 58 /* ARM armcc specific functions */
mrsoundhar 0:559a8e4aab60 59
mrsoundhar 0:559a8e4aab60 60 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 61 #define __SADD8 __sadd8
mrsoundhar 0:559a8e4aab60 62 #define __QADD8 __qadd8
mrsoundhar 0:559a8e4aab60 63 #define __SHADD8 __shadd8
mrsoundhar 0:559a8e4aab60 64 #define __UADD8 __uadd8
mrsoundhar 0:559a8e4aab60 65 #define __UQADD8 __uqadd8
mrsoundhar 0:559a8e4aab60 66 #define __UHADD8 __uhadd8
mrsoundhar 0:559a8e4aab60 67 #define __SSUB8 __ssub8
mrsoundhar 0:559a8e4aab60 68 #define __QSUB8 __qsub8
mrsoundhar 0:559a8e4aab60 69 #define __SHSUB8 __shsub8
mrsoundhar 0:559a8e4aab60 70 #define __USUB8 __usub8
mrsoundhar 0:559a8e4aab60 71 #define __UQSUB8 __uqsub8
mrsoundhar 0:559a8e4aab60 72 #define __UHSUB8 __uhsub8
mrsoundhar 0:559a8e4aab60 73 #define __SADD16 __sadd16
mrsoundhar 0:559a8e4aab60 74 #define __QADD16 __qadd16
mrsoundhar 0:559a8e4aab60 75 #define __SHADD16 __shadd16
mrsoundhar 0:559a8e4aab60 76 #define __UADD16 __uadd16
mrsoundhar 0:559a8e4aab60 77 #define __UQADD16 __uqadd16
mrsoundhar 0:559a8e4aab60 78 #define __UHADD16 __uhadd16
mrsoundhar 0:559a8e4aab60 79 #define __SSUB16 __ssub16
mrsoundhar 0:559a8e4aab60 80 #define __QSUB16 __qsub16
mrsoundhar 0:559a8e4aab60 81 #define __SHSUB16 __shsub16
mrsoundhar 0:559a8e4aab60 82 #define __USUB16 __usub16
mrsoundhar 0:559a8e4aab60 83 #define __UQSUB16 __uqsub16
mrsoundhar 0:559a8e4aab60 84 #define __UHSUB16 __uhsub16
mrsoundhar 0:559a8e4aab60 85 #define __SASX __sasx
mrsoundhar 0:559a8e4aab60 86 #define __QASX __qasx
mrsoundhar 0:559a8e4aab60 87 #define __SHASX __shasx
mrsoundhar 0:559a8e4aab60 88 #define __UASX __uasx
mrsoundhar 0:559a8e4aab60 89 #define __UQASX __uqasx
mrsoundhar 0:559a8e4aab60 90 #define __UHASX __uhasx
mrsoundhar 0:559a8e4aab60 91 #define __SSAX __ssax
mrsoundhar 0:559a8e4aab60 92 #define __QSAX __qsax
mrsoundhar 0:559a8e4aab60 93 #define __SHSAX __shsax
mrsoundhar 0:559a8e4aab60 94 #define __USAX __usax
mrsoundhar 0:559a8e4aab60 95 #define __UQSAX __uqsax
mrsoundhar 0:559a8e4aab60 96 #define __UHSAX __uhsax
mrsoundhar 0:559a8e4aab60 97 #define __USAD8 __usad8
mrsoundhar 0:559a8e4aab60 98 #define __USADA8 __usada8
mrsoundhar 0:559a8e4aab60 99 #define __SSAT16 __ssat16
mrsoundhar 0:559a8e4aab60 100 #define __USAT16 __usat16
mrsoundhar 0:559a8e4aab60 101 #define __UXTB16 __uxtb16
mrsoundhar 0:559a8e4aab60 102 #define __UXTAB16 __uxtab16
mrsoundhar 0:559a8e4aab60 103 #define __SXTB16 __sxtb16
mrsoundhar 0:559a8e4aab60 104 #define __SXTAB16 __sxtab16
mrsoundhar 0:559a8e4aab60 105 #define __SMUAD __smuad
mrsoundhar 0:559a8e4aab60 106 #define __SMUADX __smuadx
mrsoundhar 0:559a8e4aab60 107 #define __SMLAD __smlad
mrsoundhar 0:559a8e4aab60 108 #define __SMLADX __smladx
mrsoundhar 0:559a8e4aab60 109 #define __SMLALD __smlald
mrsoundhar 0:559a8e4aab60 110 #define __SMLALDX __smlaldx
mrsoundhar 0:559a8e4aab60 111 #define __SMUSD __smusd
mrsoundhar 0:559a8e4aab60 112 #define __SMUSDX __smusdx
mrsoundhar 0:559a8e4aab60 113 #define __SMLSD __smlsd
mrsoundhar 0:559a8e4aab60 114 #define __SMLSDX __smlsdx
mrsoundhar 0:559a8e4aab60 115 #define __SMLSLD __smlsld
mrsoundhar 0:559a8e4aab60 116 #define __SMLSLDX __smlsldx
mrsoundhar 0:559a8e4aab60 117 #define __SEL __sel
mrsoundhar 0:559a8e4aab60 118 #define __QADD __qadd
mrsoundhar 0:559a8e4aab60 119 #define __QSUB __qsub
mrsoundhar 0:559a8e4aab60 120
mrsoundhar 0:559a8e4aab60 121 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
mrsoundhar 0:559a8e4aab60 122 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
mrsoundhar 0:559a8e4aab60 123
mrsoundhar 0:559a8e4aab60 124 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
mrsoundhar 0:559a8e4aab60 125 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
mrsoundhar 0:559a8e4aab60 126
mrsoundhar 0:559a8e4aab60 127 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
mrsoundhar 0:559a8e4aab60 128 ((int64_t)(ARG3) << 32) ) >> 32))
mrsoundhar 0:559a8e4aab60 129
mrsoundhar 0:559a8e4aab60 130 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 131
mrsoundhar 0:559a8e4aab60 132
mrsoundhar 0:559a8e4aab60 133
mrsoundhar 0:559a8e4aab60 134 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mrsoundhar 0:559a8e4aab60 135 /* IAR iccarm specific functions */
mrsoundhar 0:559a8e4aab60 136
mrsoundhar 0:559a8e4aab60 137 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 138 #include <cmsis_iar.h>
mrsoundhar 0:559a8e4aab60 139
mrsoundhar 0:559a8e4aab60 140 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 141
mrsoundhar 0:559a8e4aab60 142
mrsoundhar 0:559a8e4aab60 143
mrsoundhar 0:559a8e4aab60 144 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mrsoundhar 0:559a8e4aab60 145 /* TI CCS specific functions */
mrsoundhar 0:559a8e4aab60 146
mrsoundhar 0:559a8e4aab60 147 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 148 #include <cmsis_ccs.h>
mrsoundhar 0:559a8e4aab60 149
mrsoundhar 0:559a8e4aab60 150 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 151
mrsoundhar 0:559a8e4aab60 152
mrsoundhar 0:559a8e4aab60 153
mrsoundhar 0:559a8e4aab60 154 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mrsoundhar 0:559a8e4aab60 155 /* GNU gcc specific functions */
mrsoundhar 0:559a8e4aab60 156
mrsoundhar 0:559a8e4aab60 157 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 158 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 159 {
mrsoundhar 0:559a8e4aab60 160 uint32_t result;
mrsoundhar 0:559a8e4aab60 161
mrsoundhar 0:559a8e4aab60 162 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 163 return(result);
mrsoundhar 0:559a8e4aab60 164 }
mrsoundhar 0:559a8e4aab60 165
mrsoundhar 0:559a8e4aab60 166 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 167 {
mrsoundhar 0:559a8e4aab60 168 uint32_t result;
mrsoundhar 0:559a8e4aab60 169
mrsoundhar 0:559a8e4aab60 170 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 171 return(result);
mrsoundhar 0:559a8e4aab60 172 }
mrsoundhar 0:559a8e4aab60 173
mrsoundhar 0:559a8e4aab60 174 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 175 {
mrsoundhar 0:559a8e4aab60 176 uint32_t result;
mrsoundhar 0:559a8e4aab60 177
mrsoundhar 0:559a8e4aab60 178 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 179 return(result);
mrsoundhar 0:559a8e4aab60 180 }
mrsoundhar 0:559a8e4aab60 181
mrsoundhar 0:559a8e4aab60 182 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 183 {
mrsoundhar 0:559a8e4aab60 184 uint32_t result;
mrsoundhar 0:559a8e4aab60 185
mrsoundhar 0:559a8e4aab60 186 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 187 return(result);
mrsoundhar 0:559a8e4aab60 188 }
mrsoundhar 0:559a8e4aab60 189
mrsoundhar 0:559a8e4aab60 190 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 191 {
mrsoundhar 0:559a8e4aab60 192 uint32_t result;
mrsoundhar 0:559a8e4aab60 193
mrsoundhar 0:559a8e4aab60 194 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 195 return(result);
mrsoundhar 0:559a8e4aab60 196 }
mrsoundhar 0:559a8e4aab60 197
mrsoundhar 0:559a8e4aab60 198 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 199 {
mrsoundhar 0:559a8e4aab60 200 uint32_t result;
mrsoundhar 0:559a8e4aab60 201
mrsoundhar 0:559a8e4aab60 202 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 203 return(result);
mrsoundhar 0:559a8e4aab60 204 }
mrsoundhar 0:559a8e4aab60 205
mrsoundhar 0:559a8e4aab60 206
mrsoundhar 0:559a8e4aab60 207 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 208 {
mrsoundhar 0:559a8e4aab60 209 uint32_t result;
mrsoundhar 0:559a8e4aab60 210
mrsoundhar 0:559a8e4aab60 211 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 212 return(result);
mrsoundhar 0:559a8e4aab60 213 }
mrsoundhar 0:559a8e4aab60 214
mrsoundhar 0:559a8e4aab60 215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 216 {
mrsoundhar 0:559a8e4aab60 217 uint32_t result;
mrsoundhar 0:559a8e4aab60 218
mrsoundhar 0:559a8e4aab60 219 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 220 return(result);
mrsoundhar 0:559a8e4aab60 221 }
mrsoundhar 0:559a8e4aab60 222
mrsoundhar 0:559a8e4aab60 223 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 224 {
mrsoundhar 0:559a8e4aab60 225 uint32_t result;
mrsoundhar 0:559a8e4aab60 226
mrsoundhar 0:559a8e4aab60 227 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 228 return(result);
mrsoundhar 0:559a8e4aab60 229 }
mrsoundhar 0:559a8e4aab60 230
mrsoundhar 0:559a8e4aab60 231 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 232 {
mrsoundhar 0:559a8e4aab60 233 uint32_t result;
mrsoundhar 0:559a8e4aab60 234
mrsoundhar 0:559a8e4aab60 235 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 236 return(result);
mrsoundhar 0:559a8e4aab60 237 }
mrsoundhar 0:559a8e4aab60 238
mrsoundhar 0:559a8e4aab60 239 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 240 {
mrsoundhar 0:559a8e4aab60 241 uint32_t result;
mrsoundhar 0:559a8e4aab60 242
mrsoundhar 0:559a8e4aab60 243 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 244 return(result);
mrsoundhar 0:559a8e4aab60 245 }
mrsoundhar 0:559a8e4aab60 246
mrsoundhar 0:559a8e4aab60 247 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 248 {
mrsoundhar 0:559a8e4aab60 249 uint32_t result;
mrsoundhar 0:559a8e4aab60 250
mrsoundhar 0:559a8e4aab60 251 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 252 return(result);
mrsoundhar 0:559a8e4aab60 253 }
mrsoundhar 0:559a8e4aab60 254
mrsoundhar 0:559a8e4aab60 255
mrsoundhar 0:559a8e4aab60 256 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 257 {
mrsoundhar 0:559a8e4aab60 258 uint32_t result;
mrsoundhar 0:559a8e4aab60 259
mrsoundhar 0:559a8e4aab60 260 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 261 return(result);
mrsoundhar 0:559a8e4aab60 262 }
mrsoundhar 0:559a8e4aab60 263
mrsoundhar 0:559a8e4aab60 264 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 265 {
mrsoundhar 0:559a8e4aab60 266 uint32_t result;
mrsoundhar 0:559a8e4aab60 267
mrsoundhar 0:559a8e4aab60 268 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 269 return(result);
mrsoundhar 0:559a8e4aab60 270 }
mrsoundhar 0:559a8e4aab60 271
mrsoundhar 0:559a8e4aab60 272 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 273 {
mrsoundhar 0:559a8e4aab60 274 uint32_t result;
mrsoundhar 0:559a8e4aab60 275
mrsoundhar 0:559a8e4aab60 276 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 277 return(result);
mrsoundhar 0:559a8e4aab60 278 }
mrsoundhar 0:559a8e4aab60 279
mrsoundhar 0:559a8e4aab60 280 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 281 {
mrsoundhar 0:559a8e4aab60 282 uint32_t result;
mrsoundhar 0:559a8e4aab60 283
mrsoundhar 0:559a8e4aab60 284 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 285 return(result);
mrsoundhar 0:559a8e4aab60 286 }
mrsoundhar 0:559a8e4aab60 287
mrsoundhar 0:559a8e4aab60 288 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 289 {
mrsoundhar 0:559a8e4aab60 290 uint32_t result;
mrsoundhar 0:559a8e4aab60 291
mrsoundhar 0:559a8e4aab60 292 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 293 return(result);
mrsoundhar 0:559a8e4aab60 294 }
mrsoundhar 0:559a8e4aab60 295
mrsoundhar 0:559a8e4aab60 296 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 297 {
mrsoundhar 0:559a8e4aab60 298 uint32_t result;
mrsoundhar 0:559a8e4aab60 299
mrsoundhar 0:559a8e4aab60 300 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 301 return(result);
mrsoundhar 0:559a8e4aab60 302 }
mrsoundhar 0:559a8e4aab60 303
mrsoundhar 0:559a8e4aab60 304 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 305 {
mrsoundhar 0:559a8e4aab60 306 uint32_t result;
mrsoundhar 0:559a8e4aab60 307
mrsoundhar 0:559a8e4aab60 308 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 309 return(result);
mrsoundhar 0:559a8e4aab60 310 }
mrsoundhar 0:559a8e4aab60 311
mrsoundhar 0:559a8e4aab60 312 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 313 {
mrsoundhar 0:559a8e4aab60 314 uint32_t result;
mrsoundhar 0:559a8e4aab60 315
mrsoundhar 0:559a8e4aab60 316 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 317 return(result);
mrsoundhar 0:559a8e4aab60 318 }
mrsoundhar 0:559a8e4aab60 319
mrsoundhar 0:559a8e4aab60 320 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 321 {
mrsoundhar 0:559a8e4aab60 322 uint32_t result;
mrsoundhar 0:559a8e4aab60 323
mrsoundhar 0:559a8e4aab60 324 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 325 return(result);
mrsoundhar 0:559a8e4aab60 326 }
mrsoundhar 0:559a8e4aab60 327
mrsoundhar 0:559a8e4aab60 328 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 329 {
mrsoundhar 0:559a8e4aab60 330 uint32_t result;
mrsoundhar 0:559a8e4aab60 331
mrsoundhar 0:559a8e4aab60 332 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 333 return(result);
mrsoundhar 0:559a8e4aab60 334 }
mrsoundhar 0:559a8e4aab60 335
mrsoundhar 0:559a8e4aab60 336 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 337 {
mrsoundhar 0:559a8e4aab60 338 uint32_t result;
mrsoundhar 0:559a8e4aab60 339
mrsoundhar 0:559a8e4aab60 340 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 341 return(result);
mrsoundhar 0:559a8e4aab60 342 }
mrsoundhar 0:559a8e4aab60 343
mrsoundhar 0:559a8e4aab60 344 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 345 {
mrsoundhar 0:559a8e4aab60 346 uint32_t result;
mrsoundhar 0:559a8e4aab60 347
mrsoundhar 0:559a8e4aab60 348 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 349 return(result);
mrsoundhar 0:559a8e4aab60 350 }
mrsoundhar 0:559a8e4aab60 351
mrsoundhar 0:559a8e4aab60 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 353 {
mrsoundhar 0:559a8e4aab60 354 uint32_t result;
mrsoundhar 0:559a8e4aab60 355
mrsoundhar 0:559a8e4aab60 356 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 357 return(result);
mrsoundhar 0:559a8e4aab60 358 }
mrsoundhar 0:559a8e4aab60 359
mrsoundhar 0:559a8e4aab60 360 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 361 {
mrsoundhar 0:559a8e4aab60 362 uint32_t result;
mrsoundhar 0:559a8e4aab60 363
mrsoundhar 0:559a8e4aab60 364 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 365 return(result);
mrsoundhar 0:559a8e4aab60 366 }
mrsoundhar 0:559a8e4aab60 367
mrsoundhar 0:559a8e4aab60 368 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 369 {
mrsoundhar 0:559a8e4aab60 370 uint32_t result;
mrsoundhar 0:559a8e4aab60 371
mrsoundhar 0:559a8e4aab60 372 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 373 return(result);
mrsoundhar 0:559a8e4aab60 374 }
mrsoundhar 0:559a8e4aab60 375
mrsoundhar 0:559a8e4aab60 376 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 377 {
mrsoundhar 0:559a8e4aab60 378 uint32_t result;
mrsoundhar 0:559a8e4aab60 379
mrsoundhar 0:559a8e4aab60 380 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 381 return(result);
mrsoundhar 0:559a8e4aab60 382 }
mrsoundhar 0:559a8e4aab60 383
mrsoundhar 0:559a8e4aab60 384 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 385 {
mrsoundhar 0:559a8e4aab60 386 uint32_t result;
mrsoundhar 0:559a8e4aab60 387
mrsoundhar 0:559a8e4aab60 388 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 389 return(result);
mrsoundhar 0:559a8e4aab60 390 }
mrsoundhar 0:559a8e4aab60 391
mrsoundhar 0:559a8e4aab60 392 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 393 {
mrsoundhar 0:559a8e4aab60 394 uint32_t result;
mrsoundhar 0:559a8e4aab60 395
mrsoundhar 0:559a8e4aab60 396 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 397 return(result);
mrsoundhar 0:559a8e4aab60 398 }
mrsoundhar 0:559a8e4aab60 399
mrsoundhar 0:559a8e4aab60 400 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 401 {
mrsoundhar 0:559a8e4aab60 402 uint32_t result;
mrsoundhar 0:559a8e4aab60 403
mrsoundhar 0:559a8e4aab60 404 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 405 return(result);
mrsoundhar 0:559a8e4aab60 406 }
mrsoundhar 0:559a8e4aab60 407
mrsoundhar 0:559a8e4aab60 408 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 409 {
mrsoundhar 0:559a8e4aab60 410 uint32_t result;
mrsoundhar 0:559a8e4aab60 411
mrsoundhar 0:559a8e4aab60 412 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 413 return(result);
mrsoundhar 0:559a8e4aab60 414 }
mrsoundhar 0:559a8e4aab60 415
mrsoundhar 0:559a8e4aab60 416 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 417 {
mrsoundhar 0:559a8e4aab60 418 uint32_t result;
mrsoundhar 0:559a8e4aab60 419
mrsoundhar 0:559a8e4aab60 420 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 421 return(result);
mrsoundhar 0:559a8e4aab60 422 }
mrsoundhar 0:559a8e4aab60 423
mrsoundhar 0:559a8e4aab60 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 425 {
mrsoundhar 0:559a8e4aab60 426 uint32_t result;
mrsoundhar 0:559a8e4aab60 427
mrsoundhar 0:559a8e4aab60 428 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 429 return(result);
mrsoundhar 0:559a8e4aab60 430 }
mrsoundhar 0:559a8e4aab60 431
mrsoundhar 0:559a8e4aab60 432 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 433 {
mrsoundhar 0:559a8e4aab60 434 uint32_t result;
mrsoundhar 0:559a8e4aab60 435
mrsoundhar 0:559a8e4aab60 436 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 437 return(result);
mrsoundhar 0:559a8e4aab60 438 }
mrsoundhar 0:559a8e4aab60 439
mrsoundhar 0:559a8e4aab60 440 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 441 {
mrsoundhar 0:559a8e4aab60 442 uint32_t result;
mrsoundhar 0:559a8e4aab60 443
mrsoundhar 0:559a8e4aab60 444 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 445 return(result);
mrsoundhar 0:559a8e4aab60 446 }
mrsoundhar 0:559a8e4aab60 447
mrsoundhar 0:559a8e4aab60 448 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 449 {
mrsoundhar 0:559a8e4aab60 450 uint32_t result;
mrsoundhar 0:559a8e4aab60 451
mrsoundhar 0:559a8e4aab60 452 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 453 return(result);
mrsoundhar 0:559a8e4aab60 454 }
mrsoundhar 0:559a8e4aab60 455
mrsoundhar 0:559a8e4aab60 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:559a8e4aab60 457 {
mrsoundhar 0:559a8e4aab60 458 uint32_t result;
mrsoundhar 0:559a8e4aab60 459
mrsoundhar 0:559a8e4aab60 460 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:559a8e4aab60 461 return(result);
mrsoundhar 0:559a8e4aab60 462 }
mrsoundhar 0:559a8e4aab60 463
mrsoundhar 0:559a8e4aab60 464 #define __SSAT16(ARG1,ARG2) \
mrsoundhar 0:559a8e4aab60 465 ({ \
mrsoundhar 0:559a8e4aab60 466 uint32_t __RES, __ARG1 = (ARG1); \
mrsoundhar 0:559a8e4aab60 467 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mrsoundhar 0:559a8e4aab60 468 __RES; \
mrsoundhar 0:559a8e4aab60 469 })
mrsoundhar 0:559a8e4aab60 470
mrsoundhar 0:559a8e4aab60 471 #define __USAT16(ARG1,ARG2) \
mrsoundhar 0:559a8e4aab60 472 ({ \
mrsoundhar 0:559a8e4aab60 473 uint32_t __RES, __ARG1 = (ARG1); \
mrsoundhar 0:559a8e4aab60 474 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
mrsoundhar 0:559a8e4aab60 475 __RES; \
mrsoundhar 0:559a8e4aab60 476 })
mrsoundhar 0:559a8e4aab60 477
mrsoundhar 0:559a8e4aab60 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
mrsoundhar 0:559a8e4aab60 479 {
mrsoundhar 0:559a8e4aab60 480 uint32_t result;
mrsoundhar 0:559a8e4aab60 481
mrsoundhar 0:559a8e4aab60 482 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
mrsoundhar 0:559a8e4aab60 483 return(result);
mrsoundhar 0:559a8e4aab60 484 }
mrsoundhar 0:559a8e4aab60 485
mrsoundhar 0:559a8e4aab60 486 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 487 {
mrsoundhar 0:559a8e4aab60 488 uint32_t result;
mrsoundhar 0:559a8e4aab60 489
mrsoundhar 0:559a8e4aab60 490 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 491 return(result);
mrsoundhar 0:559a8e4aab60 492 }
mrsoundhar 0:559a8e4aab60 493
mrsoundhar 0:559a8e4aab60 494 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
mrsoundhar 0:559a8e4aab60 495 {
mrsoundhar 0:559a8e4aab60 496 uint32_t result;
mrsoundhar 0:559a8e4aab60 497
mrsoundhar 0:559a8e4aab60 498 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
mrsoundhar 0:559a8e4aab60 499 return(result);
mrsoundhar 0:559a8e4aab60 500 }
mrsoundhar 0:559a8e4aab60 501
mrsoundhar 0:559a8e4aab60 502 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 503 {
mrsoundhar 0:559a8e4aab60 504 uint32_t result;
mrsoundhar 0:559a8e4aab60 505
mrsoundhar 0:559a8e4aab60 506 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 507 return(result);
mrsoundhar 0:559a8e4aab60 508 }
mrsoundhar 0:559a8e4aab60 509
mrsoundhar 0:559a8e4aab60 510 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 511 {
mrsoundhar 0:559a8e4aab60 512 uint32_t result;
mrsoundhar 0:559a8e4aab60 513
mrsoundhar 0:559a8e4aab60 514 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 515 return(result);
mrsoundhar 0:559a8e4aab60 516 }
mrsoundhar 0:559a8e4aab60 517
mrsoundhar 0:559a8e4aab60 518 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 519 {
mrsoundhar 0:559a8e4aab60 520 uint32_t result;
mrsoundhar 0:559a8e4aab60 521
mrsoundhar 0:559a8e4aab60 522 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 523 return(result);
mrsoundhar 0:559a8e4aab60 524 }
mrsoundhar 0:559a8e4aab60 525
mrsoundhar 0:559a8e4aab60 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:559a8e4aab60 527 {
mrsoundhar 0:559a8e4aab60 528 uint32_t result;
mrsoundhar 0:559a8e4aab60 529
mrsoundhar 0:559a8e4aab60 530 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:559a8e4aab60 531 return(result);
mrsoundhar 0:559a8e4aab60 532 }
mrsoundhar 0:559a8e4aab60 533
mrsoundhar 0:559a8e4aab60 534 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:559a8e4aab60 535 {
mrsoundhar 0:559a8e4aab60 536 uint32_t result;
mrsoundhar 0:559a8e4aab60 537
mrsoundhar 0:559a8e4aab60 538 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:559a8e4aab60 539 return(result);
mrsoundhar 0:559a8e4aab60 540 }
mrsoundhar 0:559a8e4aab60 541
mrsoundhar 0:559a8e4aab60 542 #define __SMLALD(ARG1,ARG2,ARG3) \
mrsoundhar 0:559a8e4aab60 543 ({ \
mrsoundhar 0:559a8e4aab60 544 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:559a8e4aab60 545 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:559a8e4aab60 546 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:559a8e4aab60 547 })
mrsoundhar 0:559a8e4aab60 548
mrsoundhar 0:559a8e4aab60 549 #define __SMLALDX(ARG1,ARG2,ARG3) \
mrsoundhar 0:559a8e4aab60 550 ({ \
mrsoundhar 0:559a8e4aab60 551 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:559a8e4aab60 552 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:559a8e4aab60 553 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:559a8e4aab60 554 })
mrsoundhar 0:559a8e4aab60 555
mrsoundhar 0:559a8e4aab60 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 557 {
mrsoundhar 0:559a8e4aab60 558 uint32_t result;
mrsoundhar 0:559a8e4aab60 559
mrsoundhar 0:559a8e4aab60 560 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 561 return(result);
mrsoundhar 0:559a8e4aab60 562 }
mrsoundhar 0:559a8e4aab60 563
mrsoundhar 0:559a8e4aab60 564 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 565 {
mrsoundhar 0:559a8e4aab60 566 uint32_t result;
mrsoundhar 0:559a8e4aab60 567
mrsoundhar 0:559a8e4aab60 568 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 569 return(result);
mrsoundhar 0:559a8e4aab60 570 }
mrsoundhar 0:559a8e4aab60 571
mrsoundhar 0:559a8e4aab60 572 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:559a8e4aab60 573 {
mrsoundhar 0:559a8e4aab60 574 uint32_t result;
mrsoundhar 0:559a8e4aab60 575
mrsoundhar 0:559a8e4aab60 576 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:559a8e4aab60 577 return(result);
mrsoundhar 0:559a8e4aab60 578 }
mrsoundhar 0:559a8e4aab60 579
mrsoundhar 0:559a8e4aab60 580 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
mrsoundhar 0:559a8e4aab60 581 {
mrsoundhar 0:559a8e4aab60 582 uint32_t result;
mrsoundhar 0:559a8e4aab60 583
mrsoundhar 0:559a8e4aab60 584 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:559a8e4aab60 585 return(result);
mrsoundhar 0:559a8e4aab60 586 }
mrsoundhar 0:559a8e4aab60 587
mrsoundhar 0:559a8e4aab60 588 #define __SMLSLD(ARG1,ARG2,ARG3) \
mrsoundhar 0:559a8e4aab60 589 ({ \
mrsoundhar 0:559a8e4aab60 590 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:559a8e4aab60 591 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:559a8e4aab60 592 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:559a8e4aab60 593 })
mrsoundhar 0:559a8e4aab60 594
mrsoundhar 0:559a8e4aab60 595 #define __SMLSLDX(ARG1,ARG2,ARG3) \
mrsoundhar 0:559a8e4aab60 596 ({ \
mrsoundhar 0:559a8e4aab60 597 uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
mrsoundhar 0:559a8e4aab60 598 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
mrsoundhar 0:559a8e4aab60 599 (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
mrsoundhar 0:559a8e4aab60 600 })
mrsoundhar 0:559a8e4aab60 601
mrsoundhar 0:559a8e4aab60 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 603 {
mrsoundhar 0:559a8e4aab60 604 uint32_t result;
mrsoundhar 0:559a8e4aab60 605
mrsoundhar 0:559a8e4aab60 606 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 607 return(result);
mrsoundhar 0:559a8e4aab60 608 }
mrsoundhar 0:559a8e4aab60 609
mrsoundhar 0:559a8e4aab60 610 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 611 {
mrsoundhar 0:559a8e4aab60 612 uint32_t result;
mrsoundhar 0:559a8e4aab60 613
mrsoundhar 0:559a8e4aab60 614 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 615 return(result);
mrsoundhar 0:559a8e4aab60 616 }
mrsoundhar 0:559a8e4aab60 617
mrsoundhar 0:559a8e4aab60 618 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
mrsoundhar 0:559a8e4aab60 619 {
mrsoundhar 0:559a8e4aab60 620 uint32_t result;
mrsoundhar 0:559a8e4aab60 621
mrsoundhar 0:559a8e4aab60 622 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
mrsoundhar 0:559a8e4aab60 623 return(result);
mrsoundhar 0:559a8e4aab60 624 }
mrsoundhar 0:559a8e4aab60 625
mrsoundhar 0:559a8e4aab60 626 #define __PKHBT(ARG1,ARG2,ARG3) \
mrsoundhar 0:559a8e4aab60 627 ({ \
mrsoundhar 0:559a8e4aab60 628 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mrsoundhar 0:559a8e4aab60 629 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mrsoundhar 0:559a8e4aab60 630 __RES; \
mrsoundhar 0:559a8e4aab60 631 })
mrsoundhar 0:559a8e4aab60 632
mrsoundhar 0:559a8e4aab60 633 #define __PKHTB(ARG1,ARG2,ARG3) \
mrsoundhar 0:559a8e4aab60 634 ({ \
mrsoundhar 0:559a8e4aab60 635 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
mrsoundhar 0:559a8e4aab60 636 if (ARG3 == 0) \
mrsoundhar 0:559a8e4aab60 637 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
mrsoundhar 0:559a8e4aab60 638 else \
mrsoundhar 0:559a8e4aab60 639 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
mrsoundhar 0:559a8e4aab60 640 __RES; \
mrsoundhar 0:559a8e4aab60 641 })
mrsoundhar 0:559a8e4aab60 642
mrsoundhar 0:559a8e4aab60 643 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
mrsoundhar 0:559a8e4aab60 644 {
mrsoundhar 0:559a8e4aab60 645 int32_t result;
mrsoundhar 0:559a8e4aab60 646
mrsoundhar 0:559a8e4aab60 647 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
mrsoundhar 0:559a8e4aab60 648 return(result);
mrsoundhar 0:559a8e4aab60 649 }
mrsoundhar 0:559a8e4aab60 650
mrsoundhar 0:559a8e4aab60 651 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 652
mrsoundhar 0:559a8e4aab60 653
mrsoundhar 0:559a8e4aab60 654
mrsoundhar 0:559a8e4aab60 655 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mrsoundhar 0:559a8e4aab60 656 /* TASKING carm specific functions */
mrsoundhar 0:559a8e4aab60 657
mrsoundhar 0:559a8e4aab60 658
mrsoundhar 0:559a8e4aab60 659 /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 660 /* not yet supported */
mrsoundhar 0:559a8e4aab60 661 /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 662
mrsoundhar 0:559a8e4aab60 663
mrsoundhar 0:559a8e4aab60 664 #endif
mrsoundhar 0:559a8e4aab60 665
mrsoundhar 0:559a8e4aab60 666 /*@} end of group CMSIS_SIMD_intrinsics */
mrsoundhar 0:559a8e4aab60 667
mrsoundhar 0:559a8e4aab60 668
mrsoundhar 0:559a8e4aab60 669 #endif /* __CORE_CM4_SIMD_H */
mrsoundhar 0:559a8e4aab60 670
mrsoundhar 0:559a8e4aab60 671 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 672 }
mrsoundhar 0:559a8e4aab60 673 #endif