Sertel_Srinath Gopalan / TARGET_LPC1768i2c

myi2c test

core_cm0plus.h@0:559a8e4aab60, 2015-06-29 (annotated)

Committer:
mrsoundhar
Date:
Mon Jun 29 12:59:52 2015 +0000
Revision:
0:559a8e4aab60
i2c

Who changed what in which revision?

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mrsoundhar 0:559a8e4aab60 1 /**************************************************************************//**
mrsoundhar 0:559a8e4aab60 2 * @file core_cm0plus.h
mrsoundhar 0:559a8e4aab60 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
mrsoundhar 0:559a8e4aab60 4 * @version V3.20
mrsoundhar 0:559a8e4aab60 5 * @date 25. February 2013
mrsoundhar 0:559a8e4aab60 6 *
mrsoundhar 0:559a8e4aab60 7 * @note
mrsoundhar 0:559a8e4aab60 8 *
mrsoundhar 0:559a8e4aab60 9 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:559a8e4aab60 11
mrsoundhar 0:559a8e4aab60 12 All rights reserved.
mrsoundhar 0:559a8e4aab60 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:559a8e4aab60 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:559a8e4aab60 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:559a8e4aab60 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:559a8e4aab60 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:559a8e4aab60 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:559a8e4aab60 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:559a8e4aab60 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:559a8e4aab60 21 to endorse or promote products derived from this software without
mrsoundhar 0:559a8e4aab60 22 specific prior written permission.
mrsoundhar 0:559a8e4aab60 23 *
mrsoundhar 0:559a8e4aab60 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:559a8e4aab60 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:559a8e4aab60 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:559a8e4aab60 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:559a8e4aab60 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:559a8e4aab60 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:559a8e4aab60 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:559a8e4aab60 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:559a8e4aab60 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:559a8e4aab60 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:559a8e4aab60 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:559a8e4aab60 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 36
mrsoundhar 0:559a8e4aab60 37
mrsoundhar 0:559a8e4aab60 38 #if defined ( __ICCARM__ )
mrsoundhar 0:559a8e4aab60 39 #pragma system_include /* treat file as system include file for MISRA check */
mrsoundhar 0:559a8e4aab60 40 #endif
mrsoundhar 0:559a8e4aab60 41
mrsoundhar 0:559a8e4aab60 42 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 43 extern "C" {
mrsoundhar 0:559a8e4aab60 44 #endif
mrsoundhar 0:559a8e4aab60 45
mrsoundhar 0:559a8e4aab60 46 #ifndef __CORE_CM0PLUS_H_GENERIC
mrsoundhar 0:559a8e4aab60 47 #define __CORE_CM0PLUS_H_GENERIC
mrsoundhar 0:559a8e4aab60 48
mrsoundhar 0:559a8e4aab60 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mrsoundhar 0:559a8e4aab60 50 CMSIS violates the following MISRA-C:2004 rules:
mrsoundhar 0:559a8e4aab60 51
mrsoundhar 0:559a8e4aab60 52 \li Required Rule 8.5, object/function definition in header file.<br>
mrsoundhar 0:559a8e4aab60 53 Function definitions in header files are used to allow 'inlining'.
mrsoundhar 0:559a8e4aab60 54
mrsoundhar 0:559a8e4aab60 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mrsoundhar 0:559a8e4aab60 56 Unions are used for effective representation of core registers.
mrsoundhar 0:559a8e4aab60 57
mrsoundhar 0:559a8e4aab60 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mrsoundhar 0:559a8e4aab60 59 Function-like macros are used to allow more efficient code.
mrsoundhar 0:559a8e4aab60 60 */
mrsoundhar 0:559a8e4aab60 61
mrsoundhar 0:559a8e4aab60 62
mrsoundhar 0:559a8e4aab60 63 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 64 * CMSIS definitions
mrsoundhar 0:559a8e4aab60 65 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 66 /** \ingroup Cortex-M0+
mrsoundhar 0:559a8e4aab60 67 @{
mrsoundhar 0:559a8e4aab60 68 */
mrsoundhar 0:559a8e4aab60 69
mrsoundhar 0:559a8e4aab60 70 /* CMSIS CM0P definitions */
mrsoundhar 0:559a8e4aab60 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mrsoundhar 0:559a8e4aab60 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mrsoundhar 0:559a8e4aab60 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
mrsoundhar 0:559a8e4aab60 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
mrsoundhar 0:559a8e4aab60 75
mrsoundhar 0:559a8e4aab60 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mrsoundhar 0:559a8e4aab60 77
mrsoundhar 0:559a8e4aab60 78
mrsoundhar 0:559a8e4aab60 79 #if defined ( __CC_ARM )
mrsoundhar 0:559a8e4aab60 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mrsoundhar 0:559a8e4aab60 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mrsoundhar 0:559a8e4aab60 82 #define __STATIC_INLINE static __inline
mrsoundhar 0:559a8e4aab60 83
mrsoundhar 0:559a8e4aab60 84 #elif defined ( __ICCARM__ )
mrsoundhar 0:559a8e4aab60 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mrsoundhar 0:559a8e4aab60 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mrsoundhar 0:559a8e4aab60 87 #define __STATIC_INLINE static inline
mrsoundhar 0:559a8e4aab60 88
mrsoundhar 0:559a8e4aab60 89 #elif defined ( __GNUC__ )
mrsoundhar 0:559a8e4aab60 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mrsoundhar 0:559a8e4aab60 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mrsoundhar 0:559a8e4aab60 92 #define __STATIC_INLINE static inline
mrsoundhar 0:559a8e4aab60 93
mrsoundhar 0:559a8e4aab60 94 #elif defined ( __TASKING__ )
mrsoundhar 0:559a8e4aab60 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mrsoundhar 0:559a8e4aab60 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mrsoundhar 0:559a8e4aab60 97 #define __STATIC_INLINE static inline
mrsoundhar 0:559a8e4aab60 98
mrsoundhar 0:559a8e4aab60 99 #endif
mrsoundhar 0:559a8e4aab60 100
mrsoundhar 0:559a8e4aab60 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
mrsoundhar 0:559a8e4aab60 102 */
mrsoundhar 0:559a8e4aab60 103 #define __FPU_USED 0
mrsoundhar 0:559a8e4aab60 104
mrsoundhar 0:559a8e4aab60 105 #if defined ( __CC_ARM )
mrsoundhar 0:559a8e4aab60 106 #if defined __TARGET_FPU_VFP
mrsoundhar 0:559a8e4aab60 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 108 #endif
mrsoundhar 0:559a8e4aab60 109
mrsoundhar 0:559a8e4aab60 110 #elif defined ( __ICCARM__ )
mrsoundhar 0:559a8e4aab60 111 #if defined __ARMVFP__
mrsoundhar 0:559a8e4aab60 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 113 #endif
mrsoundhar 0:559a8e4aab60 114
mrsoundhar 0:559a8e4aab60 115 #elif defined ( __GNUC__ )
mrsoundhar 0:559a8e4aab60 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mrsoundhar 0:559a8e4aab60 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 118 #endif
mrsoundhar 0:559a8e4aab60 119
mrsoundhar 0:559a8e4aab60 120 #elif defined ( __TASKING__ )
mrsoundhar 0:559a8e4aab60 121 #if defined __FPU_VFP__
mrsoundhar 0:559a8e4aab60 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 123 #endif
mrsoundhar 0:559a8e4aab60 124 #endif
mrsoundhar 0:559a8e4aab60 125
mrsoundhar 0:559a8e4aab60 126 #include <stdint.h> /* standard types definitions */
mrsoundhar 0:559a8e4aab60 127 #include <core_cmInstr.h> /* Core Instruction Access */
mrsoundhar 0:559a8e4aab60 128 #include <core_cmFunc.h> /* Core Function Access */
mrsoundhar 0:559a8e4aab60 129
mrsoundhar 0:559a8e4aab60 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
mrsoundhar 0:559a8e4aab60 131
mrsoundhar 0:559a8e4aab60 132 #ifndef __CMSIS_GENERIC
mrsoundhar 0:559a8e4aab60 133
mrsoundhar 0:559a8e4aab60 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
mrsoundhar 0:559a8e4aab60 135 #define __CORE_CM0PLUS_H_DEPENDANT
mrsoundhar 0:559a8e4aab60 136
mrsoundhar 0:559a8e4aab60 137 /* check device defines and use defaults */
mrsoundhar 0:559a8e4aab60 138 #if defined __CHECK_DEVICE_DEFINES
mrsoundhar 0:559a8e4aab60 139 #ifndef __CM0PLUS_REV
mrsoundhar 0:559a8e4aab60 140 #define __CM0PLUS_REV 0x0000
mrsoundhar 0:559a8e4aab60 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 142 #endif
mrsoundhar 0:559a8e4aab60 143
mrsoundhar 0:559a8e4aab60 144 #ifndef __MPU_PRESENT
mrsoundhar 0:559a8e4aab60 145 #define __MPU_PRESENT 0
mrsoundhar 0:559a8e4aab60 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 147 #endif
mrsoundhar 0:559a8e4aab60 148
mrsoundhar 0:559a8e4aab60 149 #ifndef __VTOR_PRESENT
mrsoundhar 0:559a8e4aab60 150 #define __VTOR_PRESENT 0
mrsoundhar 0:559a8e4aab60 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 152 #endif
mrsoundhar 0:559a8e4aab60 153
mrsoundhar 0:559a8e4aab60 154 #ifndef __NVIC_PRIO_BITS
mrsoundhar 0:559a8e4aab60 155 #define __NVIC_PRIO_BITS 2
mrsoundhar 0:559a8e4aab60 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 157 #endif
mrsoundhar 0:559a8e4aab60 158
mrsoundhar 0:559a8e4aab60 159 #ifndef __Vendor_SysTickConfig
mrsoundhar 0:559a8e4aab60 160 #define __Vendor_SysTickConfig 0
mrsoundhar 0:559a8e4aab60 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 162 #endif
mrsoundhar 0:559a8e4aab60 163 #endif
mrsoundhar 0:559a8e4aab60 164
mrsoundhar 0:559a8e4aab60 165 /* IO definitions (access restrictions to peripheral registers) */
mrsoundhar 0:559a8e4aab60 166 /**
mrsoundhar 0:559a8e4aab60 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
mrsoundhar 0:559a8e4aab60 168
mrsoundhar 0:559a8e4aab60 169 <strong>IO Type Qualifiers</strong> are used
mrsoundhar 0:559a8e4aab60 170 \li to specify the access to peripheral variables.
mrsoundhar 0:559a8e4aab60 171 \li for automatic generation of peripheral register debug information.
mrsoundhar 0:559a8e4aab60 172 */
mrsoundhar 0:559a8e4aab60 173 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 174 #define __I volatile /*!< Defines 'read only' permissions */
mrsoundhar 0:559a8e4aab60 175 #else
mrsoundhar 0:559a8e4aab60 176 #define __I volatile const /*!< Defines 'read only' permissions */
mrsoundhar 0:559a8e4aab60 177 #endif
mrsoundhar 0:559a8e4aab60 178 #define __O volatile /*!< Defines 'write only' permissions */
mrsoundhar 0:559a8e4aab60 179 #define __IO volatile /*!< Defines 'read / write' permissions */
mrsoundhar 0:559a8e4aab60 180
mrsoundhar 0:559a8e4aab60 181 /*@} end of group Cortex-M0+ */
mrsoundhar 0:559a8e4aab60 182
mrsoundhar 0:559a8e4aab60 183
mrsoundhar 0:559a8e4aab60 184
mrsoundhar 0:559a8e4aab60 185 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 186 * Register Abstraction
mrsoundhar 0:559a8e4aab60 187 Core Register contain:
mrsoundhar 0:559a8e4aab60 188 - Core Register
mrsoundhar 0:559a8e4aab60 189 - Core NVIC Register
mrsoundhar 0:559a8e4aab60 190 - Core SCB Register
mrsoundhar 0:559a8e4aab60 191 - Core SysTick Register
mrsoundhar 0:559a8e4aab60 192 - Core MPU Register
mrsoundhar 0:559a8e4aab60 193 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
mrsoundhar 0:559a8e4aab60 195 \brief Type definitions and defines for Cortex-M processor based devices.
mrsoundhar 0:559a8e4aab60 196 */
mrsoundhar 0:559a8e4aab60 197
mrsoundhar 0:559a8e4aab60 198 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 199 \defgroup CMSIS_CORE Status and Control Registers
mrsoundhar 0:559a8e4aab60 200 \brief Core Register type definitions.
mrsoundhar 0:559a8e4aab60 201 @{
mrsoundhar 0:559a8e4aab60 202 */
mrsoundhar 0:559a8e4aab60 203
mrsoundhar 0:559a8e4aab60 204 /** \brief Union type to access the Application Program Status Register (APSR).
mrsoundhar 0:559a8e4aab60 205 */
mrsoundhar 0:559a8e4aab60 206 typedef union
mrsoundhar 0:559a8e4aab60 207 {
mrsoundhar 0:559a8e4aab60 208 struct
mrsoundhar 0:559a8e4aab60 209 {
mrsoundhar 0:559a8e4aab60 210 #if (__CORTEX_M != 0x04)
mrsoundhar 0:559a8e4aab60 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mrsoundhar 0:559a8e4aab60 212 #else
mrsoundhar 0:559a8e4aab60 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mrsoundhar 0:559a8e4aab60 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mrsoundhar 0:559a8e4aab60 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mrsoundhar 0:559a8e4aab60 216 #endif
mrsoundhar 0:559a8e4aab60 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mrsoundhar 0:559a8e4aab60 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mrsoundhar 0:559a8e4aab60 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mrsoundhar 0:559a8e4aab60 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mrsoundhar 0:559a8e4aab60 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mrsoundhar 0:559a8e4aab60 222 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 223 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 224 } APSR_Type;
mrsoundhar 0:559a8e4aab60 225
mrsoundhar 0:559a8e4aab60 226
mrsoundhar 0:559a8e4aab60 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mrsoundhar 0:559a8e4aab60 228 */
mrsoundhar 0:559a8e4aab60 229 typedef union
mrsoundhar 0:559a8e4aab60 230 {
mrsoundhar 0:559a8e4aab60 231 struct
mrsoundhar 0:559a8e4aab60 232 {
mrsoundhar 0:559a8e4aab60 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mrsoundhar 0:559a8e4aab60 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mrsoundhar 0:559a8e4aab60 235 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 236 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 237 } IPSR_Type;
mrsoundhar 0:559a8e4aab60 238
mrsoundhar 0:559a8e4aab60 239
mrsoundhar 0:559a8e4aab60 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mrsoundhar 0:559a8e4aab60 241 */
mrsoundhar 0:559a8e4aab60 242 typedef union
mrsoundhar 0:559a8e4aab60 243 {
mrsoundhar 0:559a8e4aab60 244 struct
mrsoundhar 0:559a8e4aab60 245 {
mrsoundhar 0:559a8e4aab60 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mrsoundhar 0:559a8e4aab60 247 #if (__CORTEX_M != 0x04)
mrsoundhar 0:559a8e4aab60 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mrsoundhar 0:559a8e4aab60 249 #else
mrsoundhar 0:559a8e4aab60 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mrsoundhar 0:559a8e4aab60 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mrsoundhar 0:559a8e4aab60 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mrsoundhar 0:559a8e4aab60 253 #endif
mrsoundhar 0:559a8e4aab60 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mrsoundhar 0:559a8e4aab60 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mrsoundhar 0:559a8e4aab60 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mrsoundhar 0:559a8e4aab60 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mrsoundhar 0:559a8e4aab60 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mrsoundhar 0:559a8e4aab60 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mrsoundhar 0:559a8e4aab60 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mrsoundhar 0:559a8e4aab60 261 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 262 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 263 } xPSR_Type;
mrsoundhar 0:559a8e4aab60 264
mrsoundhar 0:559a8e4aab60 265
mrsoundhar 0:559a8e4aab60 266 /** \brief Union type to access the Control Registers (CONTROL).
mrsoundhar 0:559a8e4aab60 267 */
mrsoundhar 0:559a8e4aab60 268 typedef union
mrsoundhar 0:559a8e4aab60 269 {
mrsoundhar 0:559a8e4aab60 270 struct
mrsoundhar 0:559a8e4aab60 271 {
mrsoundhar 0:559a8e4aab60 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mrsoundhar 0:559a8e4aab60 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mrsoundhar 0:559a8e4aab60 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mrsoundhar 0:559a8e4aab60 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mrsoundhar 0:559a8e4aab60 276 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 277 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 278 } CONTROL_Type;
mrsoundhar 0:559a8e4aab60 279
mrsoundhar 0:559a8e4aab60 280 /*@} end of group CMSIS_CORE */
mrsoundhar 0:559a8e4aab60 281
mrsoundhar 0:559a8e4aab60 282
mrsoundhar 0:559a8e4aab60 283 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mrsoundhar 0:559a8e4aab60 285 \brief Type definitions for the NVIC Registers
mrsoundhar 0:559a8e4aab60 286 @{
mrsoundhar 0:559a8e4aab60 287 */
mrsoundhar 0:559a8e4aab60 288
mrsoundhar 0:559a8e4aab60 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mrsoundhar 0:559a8e4aab60 290 */
mrsoundhar 0:559a8e4aab60 291 typedef struct
mrsoundhar 0:559a8e4aab60 292 {
mrsoundhar 0:559a8e4aab60 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mrsoundhar 0:559a8e4aab60 294 uint32_t RESERVED0[31];
mrsoundhar 0:559a8e4aab60 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mrsoundhar 0:559a8e4aab60 296 uint32_t RSERVED1[31];
mrsoundhar 0:559a8e4aab60 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mrsoundhar 0:559a8e4aab60 298 uint32_t RESERVED2[31];
mrsoundhar 0:559a8e4aab60 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mrsoundhar 0:559a8e4aab60 300 uint32_t RESERVED3[31];
mrsoundhar 0:559a8e4aab60 301 uint32_t RESERVED4[64];
mrsoundhar 0:559a8e4aab60 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mrsoundhar 0:559a8e4aab60 303 } NVIC_Type;
mrsoundhar 0:559a8e4aab60 304
mrsoundhar 0:559a8e4aab60 305 /*@} end of group CMSIS_NVIC */
mrsoundhar 0:559a8e4aab60 306
mrsoundhar 0:559a8e4aab60 307
mrsoundhar 0:559a8e4aab60 308 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 309 \defgroup CMSIS_SCB System Control Block (SCB)
mrsoundhar 0:559a8e4aab60 310 \brief Type definitions for the System Control Block Registers
mrsoundhar 0:559a8e4aab60 311 @{
mrsoundhar 0:559a8e4aab60 312 */
mrsoundhar 0:559a8e4aab60 313
mrsoundhar 0:559a8e4aab60 314 /** \brief Structure type to access the System Control Block (SCB).
mrsoundhar 0:559a8e4aab60 315 */
mrsoundhar 0:559a8e4aab60 316 typedef struct
mrsoundhar 0:559a8e4aab60 317 {
mrsoundhar 0:559a8e4aab60 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mrsoundhar 0:559a8e4aab60 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mrsoundhar 0:559a8e4aab60 320 #if (__VTOR_PRESENT == 1)
mrsoundhar 0:559a8e4aab60 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mrsoundhar 0:559a8e4aab60 322 #else
mrsoundhar 0:559a8e4aab60 323 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 324 #endif
mrsoundhar 0:559a8e4aab60 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mrsoundhar 0:559a8e4aab60 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mrsoundhar 0:559a8e4aab60 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mrsoundhar 0:559a8e4aab60 328 uint32_t RESERVED1;
mrsoundhar 0:559a8e4aab60 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mrsoundhar 0:559a8e4aab60 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mrsoundhar 0:559a8e4aab60 331 } SCB_Type;
mrsoundhar 0:559a8e4aab60 332
mrsoundhar 0:559a8e4aab60 333 /* SCB CPUID Register Definitions */
mrsoundhar 0:559a8e4aab60 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mrsoundhar 0:559a8e4aab60 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mrsoundhar 0:559a8e4aab60 336
mrsoundhar 0:559a8e4aab60 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mrsoundhar 0:559a8e4aab60 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mrsoundhar 0:559a8e4aab60 339
mrsoundhar 0:559a8e4aab60 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mrsoundhar 0:559a8e4aab60 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mrsoundhar 0:559a8e4aab60 342
mrsoundhar 0:559a8e4aab60 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mrsoundhar 0:559a8e4aab60 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mrsoundhar 0:559a8e4aab60 345
mrsoundhar 0:559a8e4aab60 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mrsoundhar 0:559a8e4aab60 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mrsoundhar 0:559a8e4aab60 348
mrsoundhar 0:559a8e4aab60 349 /* SCB Interrupt Control State Register Definitions */
mrsoundhar 0:559a8e4aab60 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mrsoundhar 0:559a8e4aab60 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mrsoundhar 0:559a8e4aab60 352
mrsoundhar 0:559a8e4aab60 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mrsoundhar 0:559a8e4aab60 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mrsoundhar 0:559a8e4aab60 355
mrsoundhar 0:559a8e4aab60 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mrsoundhar 0:559a8e4aab60 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mrsoundhar 0:559a8e4aab60 358
mrsoundhar 0:559a8e4aab60 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mrsoundhar 0:559a8e4aab60 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mrsoundhar 0:559a8e4aab60 361
mrsoundhar 0:559a8e4aab60 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mrsoundhar 0:559a8e4aab60 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mrsoundhar 0:559a8e4aab60 364
mrsoundhar 0:559a8e4aab60 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mrsoundhar 0:559a8e4aab60 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mrsoundhar 0:559a8e4aab60 367
mrsoundhar 0:559a8e4aab60 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mrsoundhar 0:559a8e4aab60 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mrsoundhar 0:559a8e4aab60 370
mrsoundhar 0:559a8e4aab60 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mrsoundhar 0:559a8e4aab60 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mrsoundhar 0:559a8e4aab60 373
mrsoundhar 0:559a8e4aab60 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mrsoundhar 0:559a8e4aab60 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mrsoundhar 0:559a8e4aab60 376
mrsoundhar 0:559a8e4aab60 377 #if (__VTOR_PRESENT == 1)
mrsoundhar 0:559a8e4aab60 378 /* SCB Interrupt Control State Register Definitions */
mrsoundhar 0:559a8e4aab60 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
mrsoundhar 0:559a8e4aab60 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mrsoundhar 0:559a8e4aab60 381 #endif
mrsoundhar 0:559a8e4aab60 382
mrsoundhar 0:559a8e4aab60 383 /* SCB Application Interrupt and Reset Control Register Definitions */
mrsoundhar 0:559a8e4aab60 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mrsoundhar 0:559a8e4aab60 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mrsoundhar 0:559a8e4aab60 386
mrsoundhar 0:559a8e4aab60 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mrsoundhar 0:559a8e4aab60 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mrsoundhar 0:559a8e4aab60 389
mrsoundhar 0:559a8e4aab60 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mrsoundhar 0:559a8e4aab60 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mrsoundhar 0:559a8e4aab60 392
mrsoundhar 0:559a8e4aab60 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mrsoundhar 0:559a8e4aab60 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mrsoundhar 0:559a8e4aab60 395
mrsoundhar 0:559a8e4aab60 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mrsoundhar 0:559a8e4aab60 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mrsoundhar 0:559a8e4aab60 398
mrsoundhar 0:559a8e4aab60 399 /* SCB System Control Register Definitions */
mrsoundhar 0:559a8e4aab60 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mrsoundhar 0:559a8e4aab60 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mrsoundhar 0:559a8e4aab60 402
mrsoundhar 0:559a8e4aab60 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mrsoundhar 0:559a8e4aab60 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mrsoundhar 0:559a8e4aab60 405
mrsoundhar 0:559a8e4aab60 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mrsoundhar 0:559a8e4aab60 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mrsoundhar 0:559a8e4aab60 408
mrsoundhar 0:559a8e4aab60 409 /* SCB Configuration Control Register Definitions */
mrsoundhar 0:559a8e4aab60 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mrsoundhar 0:559a8e4aab60 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mrsoundhar 0:559a8e4aab60 412
mrsoundhar 0:559a8e4aab60 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mrsoundhar 0:559a8e4aab60 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mrsoundhar 0:559a8e4aab60 415
mrsoundhar 0:559a8e4aab60 416 /* SCB System Handler Control and State Register Definitions */
mrsoundhar 0:559a8e4aab60 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mrsoundhar 0:559a8e4aab60 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mrsoundhar 0:559a8e4aab60 419
mrsoundhar 0:559a8e4aab60 420 /*@} end of group CMSIS_SCB */
mrsoundhar 0:559a8e4aab60 421
mrsoundhar 0:559a8e4aab60 422
mrsoundhar 0:559a8e4aab60 423 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mrsoundhar 0:559a8e4aab60 425 \brief Type definitions for the System Timer Registers.
mrsoundhar 0:559a8e4aab60 426 @{
mrsoundhar 0:559a8e4aab60 427 */
mrsoundhar 0:559a8e4aab60 428
mrsoundhar 0:559a8e4aab60 429 /** \brief Structure type to access the System Timer (SysTick).
mrsoundhar 0:559a8e4aab60 430 */
mrsoundhar 0:559a8e4aab60 431 typedef struct
mrsoundhar 0:559a8e4aab60 432 {
mrsoundhar 0:559a8e4aab60 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mrsoundhar 0:559a8e4aab60 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mrsoundhar 0:559a8e4aab60 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mrsoundhar 0:559a8e4aab60 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mrsoundhar 0:559a8e4aab60 437 } SysTick_Type;
mrsoundhar 0:559a8e4aab60 438
mrsoundhar 0:559a8e4aab60 439 /* SysTick Control / Status Register Definitions */
mrsoundhar 0:559a8e4aab60 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mrsoundhar 0:559a8e4aab60 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mrsoundhar 0:559a8e4aab60 442
mrsoundhar 0:559a8e4aab60 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mrsoundhar 0:559a8e4aab60 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mrsoundhar 0:559a8e4aab60 445
mrsoundhar 0:559a8e4aab60 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mrsoundhar 0:559a8e4aab60 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mrsoundhar 0:559a8e4aab60 448
mrsoundhar 0:559a8e4aab60 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mrsoundhar 0:559a8e4aab60 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mrsoundhar 0:559a8e4aab60 451
mrsoundhar 0:559a8e4aab60 452 /* SysTick Reload Register Definitions */
mrsoundhar 0:559a8e4aab60 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mrsoundhar 0:559a8e4aab60 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mrsoundhar 0:559a8e4aab60 455
mrsoundhar 0:559a8e4aab60 456 /* SysTick Current Register Definitions */
mrsoundhar 0:559a8e4aab60 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mrsoundhar 0:559a8e4aab60 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mrsoundhar 0:559a8e4aab60 459
mrsoundhar 0:559a8e4aab60 460 /* SysTick Calibration Register Definitions */
mrsoundhar 0:559a8e4aab60 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mrsoundhar 0:559a8e4aab60 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mrsoundhar 0:559a8e4aab60 463
mrsoundhar 0:559a8e4aab60 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mrsoundhar 0:559a8e4aab60 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mrsoundhar 0:559a8e4aab60 466
mrsoundhar 0:559a8e4aab60 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mrsoundhar 0:559a8e4aab60 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mrsoundhar 0:559a8e4aab60 469
mrsoundhar 0:559a8e4aab60 470 /*@} end of group CMSIS_SysTick */
mrsoundhar 0:559a8e4aab60 471
mrsoundhar 0:559a8e4aab60 472 #if (__MPU_PRESENT == 1)
mrsoundhar 0:559a8e4aab60 473 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mrsoundhar 0:559a8e4aab60 475 \brief Type definitions for the Memory Protection Unit (MPU)
mrsoundhar 0:559a8e4aab60 476 @{
mrsoundhar 0:559a8e4aab60 477 */
mrsoundhar 0:559a8e4aab60 478
mrsoundhar 0:559a8e4aab60 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
mrsoundhar 0:559a8e4aab60 480 */
mrsoundhar 0:559a8e4aab60 481 typedef struct
mrsoundhar 0:559a8e4aab60 482 {
mrsoundhar 0:559a8e4aab60 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mrsoundhar 0:559a8e4aab60 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mrsoundhar 0:559a8e4aab60 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mrsoundhar 0:559a8e4aab60 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mrsoundhar 0:559a8e4aab60 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mrsoundhar 0:559a8e4aab60 488 } MPU_Type;
mrsoundhar 0:559a8e4aab60 489
mrsoundhar 0:559a8e4aab60 490 /* MPU Type Register */
mrsoundhar 0:559a8e4aab60 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mrsoundhar 0:559a8e4aab60 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mrsoundhar 0:559a8e4aab60 493
mrsoundhar 0:559a8e4aab60 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mrsoundhar 0:559a8e4aab60 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mrsoundhar 0:559a8e4aab60 496
mrsoundhar 0:559a8e4aab60 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mrsoundhar 0:559a8e4aab60 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
mrsoundhar 0:559a8e4aab60 499
mrsoundhar 0:559a8e4aab60 500 /* MPU Control Register */
mrsoundhar 0:559a8e4aab60 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mrsoundhar 0:559a8e4aab60 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mrsoundhar 0:559a8e4aab60 503
mrsoundhar 0:559a8e4aab60 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mrsoundhar 0:559a8e4aab60 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mrsoundhar 0:559a8e4aab60 506
mrsoundhar 0:559a8e4aab60 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mrsoundhar 0:559a8e4aab60 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
mrsoundhar 0:559a8e4aab60 509
mrsoundhar 0:559a8e4aab60 510 /* MPU Region Number Register */
mrsoundhar 0:559a8e4aab60 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mrsoundhar 0:559a8e4aab60 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
mrsoundhar 0:559a8e4aab60 513
mrsoundhar 0:559a8e4aab60 514 /* MPU Region Base Address Register */
mrsoundhar 0:559a8e4aab60 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
mrsoundhar 0:559a8e4aab60 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mrsoundhar 0:559a8e4aab60 517
mrsoundhar 0:559a8e4aab60 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mrsoundhar 0:559a8e4aab60 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mrsoundhar 0:559a8e4aab60 520
mrsoundhar 0:559a8e4aab60 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mrsoundhar 0:559a8e4aab60 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
mrsoundhar 0:559a8e4aab60 523
mrsoundhar 0:559a8e4aab60 524 /* MPU Region Attribute and Size Register */
mrsoundhar 0:559a8e4aab60 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mrsoundhar 0:559a8e4aab60 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mrsoundhar 0:559a8e4aab60 527
mrsoundhar 0:559a8e4aab60 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mrsoundhar 0:559a8e4aab60 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mrsoundhar 0:559a8e4aab60 530
mrsoundhar 0:559a8e4aab60 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mrsoundhar 0:559a8e4aab60 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mrsoundhar 0:559a8e4aab60 533
mrsoundhar 0:559a8e4aab60 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mrsoundhar 0:559a8e4aab60 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mrsoundhar 0:559a8e4aab60 536
mrsoundhar 0:559a8e4aab60 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mrsoundhar 0:559a8e4aab60 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mrsoundhar 0:559a8e4aab60 539
mrsoundhar 0:559a8e4aab60 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mrsoundhar 0:559a8e4aab60 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mrsoundhar 0:559a8e4aab60 542
mrsoundhar 0:559a8e4aab60 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mrsoundhar 0:559a8e4aab60 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mrsoundhar 0:559a8e4aab60 545
mrsoundhar 0:559a8e4aab60 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mrsoundhar 0:559a8e4aab60 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mrsoundhar 0:559a8e4aab60 548
mrsoundhar 0:559a8e4aab60 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mrsoundhar 0:559a8e4aab60 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mrsoundhar 0:559a8e4aab60 551
mrsoundhar 0:559a8e4aab60 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mrsoundhar 0:559a8e4aab60 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
mrsoundhar 0:559a8e4aab60 554
mrsoundhar 0:559a8e4aab60 555 /*@} end of group CMSIS_MPU */
mrsoundhar 0:559a8e4aab60 556 #endif
mrsoundhar 0:559a8e4aab60 557
mrsoundhar 0:559a8e4aab60 558
mrsoundhar 0:559a8e4aab60 559 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mrsoundhar 0:559a8e4aab60 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
mrsoundhar 0:559a8e4aab60 562 are only accessible over DAP and not via processor. Therefore
mrsoundhar 0:559a8e4aab60 563 they are not covered by the Cortex-M0 header file.
mrsoundhar 0:559a8e4aab60 564 @{
mrsoundhar 0:559a8e4aab60 565 */
mrsoundhar 0:559a8e4aab60 566 /*@} end of group CMSIS_CoreDebug */
mrsoundhar 0:559a8e4aab60 567
mrsoundhar 0:559a8e4aab60 568
mrsoundhar 0:559a8e4aab60 569 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 570 \defgroup CMSIS_core_base Core Definitions
mrsoundhar 0:559a8e4aab60 571 \brief Definitions for base addresses, unions, and structures.
mrsoundhar 0:559a8e4aab60 572 @{
mrsoundhar 0:559a8e4aab60 573 */
mrsoundhar 0:559a8e4aab60 574
mrsoundhar 0:559a8e4aab60 575 /* Memory mapping of Cortex-M0+ Hardware */
mrsoundhar 0:559a8e4aab60 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mrsoundhar 0:559a8e4aab60 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mrsoundhar 0:559a8e4aab60 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mrsoundhar 0:559a8e4aab60 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mrsoundhar 0:559a8e4aab60 580
mrsoundhar 0:559a8e4aab60 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mrsoundhar 0:559a8e4aab60 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mrsoundhar 0:559a8e4aab60 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mrsoundhar 0:559a8e4aab60 584
mrsoundhar 0:559a8e4aab60 585 #if (__MPU_PRESENT == 1)
mrsoundhar 0:559a8e4aab60 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mrsoundhar 0:559a8e4aab60 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mrsoundhar 0:559a8e4aab60 588 #endif
mrsoundhar 0:559a8e4aab60 589
mrsoundhar 0:559a8e4aab60 590 /*@} */
mrsoundhar 0:559a8e4aab60 591
mrsoundhar 0:559a8e4aab60 592
mrsoundhar 0:559a8e4aab60 593
mrsoundhar 0:559a8e4aab60 594 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 595 * Hardware Abstraction Layer
mrsoundhar 0:559a8e4aab60 596 Core Function Interface contains:
mrsoundhar 0:559a8e4aab60 597 - Core NVIC Functions
mrsoundhar 0:559a8e4aab60 598 - Core SysTick Functions
mrsoundhar 0:559a8e4aab60 599 - Core Register Access Functions
mrsoundhar 0:559a8e4aab60 600 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mrsoundhar 0:559a8e4aab60 602 */
mrsoundhar 0:559a8e4aab60 603
mrsoundhar 0:559a8e4aab60 604
mrsoundhar 0:559a8e4aab60 605
mrsoundhar 0:559a8e4aab60 606 /* ########################## NVIC functions #################################### */
mrsoundhar 0:559a8e4aab60 607 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:559a8e4aab60 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mrsoundhar 0:559a8e4aab60 609 \brief Functions that manage interrupts and exceptions via the NVIC.
mrsoundhar 0:559a8e4aab60 610 @{
mrsoundhar 0:559a8e4aab60 611 */
mrsoundhar 0:559a8e4aab60 612
mrsoundhar 0:559a8e4aab60 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mrsoundhar 0:559a8e4aab60 614 /* The following MACROS handle generation of the register offset and byte masks */
mrsoundhar 0:559a8e4aab60 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
mrsoundhar 0:559a8e4aab60 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
mrsoundhar 0:559a8e4aab60 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
mrsoundhar 0:559a8e4aab60 618
mrsoundhar 0:559a8e4aab60 619
mrsoundhar 0:559a8e4aab60 620 /** \brief Enable External Interrupt
mrsoundhar 0:559a8e4aab60 621
mrsoundhar 0:559a8e4aab60 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
mrsoundhar 0:559a8e4aab60 623
mrsoundhar 0:559a8e4aab60 624 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 625 */
mrsoundhar 0:559a8e4aab60 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 627 {
mrsoundhar 0:559a8e4aab60 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mrsoundhar 0:559a8e4aab60 629 }
mrsoundhar 0:559a8e4aab60 630
mrsoundhar 0:559a8e4aab60 631
mrsoundhar 0:559a8e4aab60 632 /** \brief Disable External Interrupt
mrsoundhar 0:559a8e4aab60 633
mrsoundhar 0:559a8e4aab60 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
mrsoundhar 0:559a8e4aab60 635
mrsoundhar 0:559a8e4aab60 636 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 637 */
mrsoundhar 0:559a8e4aab60 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 639 {
mrsoundhar 0:559a8e4aab60 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mrsoundhar 0:559a8e4aab60 641 }
mrsoundhar 0:559a8e4aab60 642
mrsoundhar 0:559a8e4aab60 643
mrsoundhar 0:559a8e4aab60 644 /** \brief Get Pending Interrupt
mrsoundhar 0:559a8e4aab60 645
mrsoundhar 0:559a8e4aab60 646 The function reads the pending register in the NVIC and returns the pending bit
mrsoundhar 0:559a8e4aab60 647 for the specified interrupt.
mrsoundhar 0:559a8e4aab60 648
mrsoundhar 0:559a8e4aab60 649 \param [in] IRQn Interrupt number.
mrsoundhar 0:559a8e4aab60 650
mrsoundhar 0:559a8e4aab60 651 \return 0 Interrupt status is not pending.
mrsoundhar 0:559a8e4aab60 652 \return 1 Interrupt status is pending.
mrsoundhar 0:559a8e4aab60 653 */
mrsoundhar 0:559a8e4aab60 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 655 {
mrsoundhar 0:559a8e4aab60 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
mrsoundhar 0:559a8e4aab60 657 }
mrsoundhar 0:559a8e4aab60 658
mrsoundhar 0:559a8e4aab60 659
mrsoundhar 0:559a8e4aab60 660 /** \brief Set Pending Interrupt
mrsoundhar 0:559a8e4aab60 661
mrsoundhar 0:559a8e4aab60 662 The function sets the pending bit of an external interrupt.
mrsoundhar 0:559a8e4aab60 663
mrsoundhar 0:559a8e4aab60 664 \param [in] IRQn Interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 665 */
mrsoundhar 0:559a8e4aab60 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 667 {
mrsoundhar 0:559a8e4aab60 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mrsoundhar 0:559a8e4aab60 669 }
mrsoundhar 0:559a8e4aab60 670
mrsoundhar 0:559a8e4aab60 671
mrsoundhar 0:559a8e4aab60 672 /** \brief Clear Pending Interrupt
mrsoundhar 0:559a8e4aab60 673
mrsoundhar 0:559a8e4aab60 674 The function clears the pending bit of an external interrupt.
mrsoundhar 0:559a8e4aab60 675
mrsoundhar 0:559a8e4aab60 676 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 677 */
mrsoundhar 0:559a8e4aab60 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 679 {
mrsoundhar 0:559a8e4aab60 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mrsoundhar 0:559a8e4aab60 681 }
mrsoundhar 0:559a8e4aab60 682
mrsoundhar 0:559a8e4aab60 683
mrsoundhar 0:559a8e4aab60 684 /** \brief Set Interrupt Priority
mrsoundhar 0:559a8e4aab60 685
mrsoundhar 0:559a8e4aab60 686 The function sets the priority of an interrupt.
mrsoundhar 0:559a8e4aab60 687
mrsoundhar 0:559a8e4aab60 688 \note The priority cannot be set for every core interrupt.
mrsoundhar 0:559a8e4aab60 689
mrsoundhar 0:559a8e4aab60 690 \param [in] IRQn Interrupt number.
mrsoundhar 0:559a8e4aab60 691 \param [in] priority Priority to set.
mrsoundhar 0:559a8e4aab60 692 */
mrsoundhar 0:559a8e4aab60 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mrsoundhar 0:559a8e4aab60 694 {
mrsoundhar 0:559a8e4aab60 695 if(IRQn < 0) {
mrsoundhar 0:559a8e4aab60 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mrsoundhar 0:559a8e4aab60 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mrsoundhar 0:559a8e4aab60 698 else {
mrsoundhar 0:559a8e4aab60 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mrsoundhar 0:559a8e4aab60 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mrsoundhar 0:559a8e4aab60 701 }
mrsoundhar 0:559a8e4aab60 702
mrsoundhar 0:559a8e4aab60 703
mrsoundhar 0:559a8e4aab60 704 /** \brief Get Interrupt Priority
mrsoundhar 0:559a8e4aab60 705
mrsoundhar 0:559a8e4aab60 706 The function reads the priority of an interrupt. The interrupt
mrsoundhar 0:559a8e4aab60 707 number can be positive to specify an external (device specific)
mrsoundhar 0:559a8e4aab60 708 interrupt, or negative to specify an internal (core) interrupt.
mrsoundhar 0:559a8e4aab60 709
mrsoundhar 0:559a8e4aab60 710
mrsoundhar 0:559a8e4aab60 711 \param [in] IRQn Interrupt number.
mrsoundhar 0:559a8e4aab60 712 \return Interrupt Priority. Value is aligned automatically to the implemented
mrsoundhar 0:559a8e4aab60 713 priority bits of the microcontroller.
mrsoundhar 0:559a8e4aab60 714 */
mrsoundhar 0:559a8e4aab60 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 716 {
mrsoundhar 0:559a8e4aab60 717
mrsoundhar 0:559a8e4aab60 718 if(IRQn < 0) {
mrsoundhar 0:559a8e4aab60 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
mrsoundhar 0:559a8e4aab60 720 else {
mrsoundhar 0:559a8e4aab60 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mrsoundhar 0:559a8e4aab60 722 }
mrsoundhar 0:559a8e4aab60 723
mrsoundhar 0:559a8e4aab60 724
mrsoundhar 0:559a8e4aab60 725 /** \brief System Reset
mrsoundhar 0:559a8e4aab60 726
mrsoundhar 0:559a8e4aab60 727 The function initiates a system reset request to reset the MCU.
mrsoundhar 0:559a8e4aab60 728 */
mrsoundhar 0:559a8e4aab60 729 __STATIC_INLINE void NVIC_SystemReset(void)
mrsoundhar 0:559a8e4aab60 730 {
mrsoundhar 0:559a8e4aab60 731 __DSB(); /* Ensure all outstanding memory accesses included
mrsoundhar 0:559a8e4aab60 732 buffered write are completed before reset */
mrsoundhar 0:559a8e4aab60 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mrsoundhar 0:559a8e4aab60 734 SCB_AIRCR_SYSRESETREQ_Msk);
mrsoundhar 0:559a8e4aab60 735 __DSB(); /* Ensure completion of memory access */
mrsoundhar 0:559a8e4aab60 736 while(1); /* wait until reset */
mrsoundhar 0:559a8e4aab60 737 }
mrsoundhar 0:559a8e4aab60 738
mrsoundhar 0:559a8e4aab60 739 /*@} end of CMSIS_Core_NVICFunctions */
mrsoundhar 0:559a8e4aab60 740
mrsoundhar 0:559a8e4aab60 741
mrsoundhar 0:559a8e4aab60 742
mrsoundhar 0:559a8e4aab60 743 /* ################################## SysTick function ############################################ */
mrsoundhar 0:559a8e4aab60 744 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:559a8e4aab60 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mrsoundhar 0:559a8e4aab60 746 \brief Functions that configure the System.
mrsoundhar 0:559a8e4aab60 747 @{
mrsoundhar 0:559a8e4aab60 748 */
mrsoundhar 0:559a8e4aab60 749
mrsoundhar 0:559a8e4aab60 750 #if (__Vendor_SysTickConfig == 0)
mrsoundhar 0:559a8e4aab60 751
mrsoundhar 0:559a8e4aab60 752 /** \brief System Tick Configuration
mrsoundhar 0:559a8e4aab60 753
mrsoundhar 0:559a8e4aab60 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mrsoundhar 0:559a8e4aab60 755 Counter is in free running mode to generate periodic interrupts.
mrsoundhar 0:559a8e4aab60 756
mrsoundhar 0:559a8e4aab60 757 \param [in] ticks Number of ticks between two interrupts.
mrsoundhar 0:559a8e4aab60 758
mrsoundhar 0:559a8e4aab60 759 \return 0 Function succeeded.
mrsoundhar 0:559a8e4aab60 760 \return 1 Function failed.
mrsoundhar 0:559a8e4aab60 761
mrsoundhar 0:559a8e4aab60 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mrsoundhar 0:559a8e4aab60 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mrsoundhar 0:559a8e4aab60 764 must contain a vendor-specific implementation of this function.
mrsoundhar 0:559a8e4aab60 765
mrsoundhar 0:559a8e4aab60 766 */
mrsoundhar 0:559a8e4aab60 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mrsoundhar 0:559a8e4aab60 768 {
mrsoundhar 0:559a8e4aab60 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mrsoundhar 0:559a8e4aab60 770
mrsoundhar 0:559a8e4aab60 771 SysTick->LOAD = ticks - 1; /* set reload register */
mrsoundhar 0:559a8e4aab60 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mrsoundhar 0:559a8e4aab60 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mrsoundhar 0:559a8e4aab60 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mrsoundhar 0:559a8e4aab60 775 SysTick_CTRL_TICKINT_Msk |
mrsoundhar 0:559a8e4aab60 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mrsoundhar 0:559a8e4aab60 777 return (0); /* Function successful */
mrsoundhar 0:559a8e4aab60 778 }
mrsoundhar 0:559a8e4aab60 779
mrsoundhar 0:559a8e4aab60 780 #endif
mrsoundhar 0:559a8e4aab60 781
mrsoundhar 0:559a8e4aab60 782 /*@} end of CMSIS_Core_SysTickFunctions */
mrsoundhar 0:559a8e4aab60 783
mrsoundhar 0:559a8e4aab60 784
mrsoundhar 0:559a8e4aab60 785
mrsoundhar 0:559a8e4aab60 786
mrsoundhar 0:559a8e4aab60 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
mrsoundhar 0:559a8e4aab60 788
mrsoundhar 0:559a8e4aab60 789 #endif /* __CMSIS_GENERIC */
mrsoundhar 0:559a8e4aab60 790
mrsoundhar 0:559a8e4aab60 791 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 792 }
mrsoundhar 0:559a8e4aab60 793 #endif