Sertel_Srinath Gopalan / TARGET_LPC1768i2c

myi2c test

core_cm0.h@0:559a8e4aab60, 2015-06-29 (annotated)

Committer:
mrsoundhar
Date:
Mon Jun 29 12:59:52 2015 +0000
Revision:
0:559a8e4aab60
i2c

Who changed what in which revision?

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mrsoundhar 0:559a8e4aab60 1 /**************************************************************************//**
mrsoundhar 0:559a8e4aab60 2 * @file core_cm0.h
mrsoundhar 0:559a8e4aab60 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
mrsoundhar 0:559a8e4aab60 4 * @version V3.20
mrsoundhar 0:559a8e4aab60 5 * @date 25. February 2013
mrsoundhar 0:559a8e4aab60 6 *
mrsoundhar 0:559a8e4aab60 7 * @note
mrsoundhar 0:559a8e4aab60 8 *
mrsoundhar 0:559a8e4aab60 9 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:559a8e4aab60 11
mrsoundhar 0:559a8e4aab60 12 All rights reserved.
mrsoundhar 0:559a8e4aab60 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:559a8e4aab60 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:559a8e4aab60 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:559a8e4aab60 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:559a8e4aab60 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:559a8e4aab60 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:559a8e4aab60 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:559a8e4aab60 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:559a8e4aab60 21 to endorse or promote products derived from this software without
mrsoundhar 0:559a8e4aab60 22 specific prior written permission.
mrsoundhar 0:559a8e4aab60 23 *
mrsoundhar 0:559a8e4aab60 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:559a8e4aab60 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:559a8e4aab60 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:559a8e4aab60 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:559a8e4aab60 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:559a8e4aab60 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:559a8e4aab60 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:559a8e4aab60 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:559a8e4aab60 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:559a8e4aab60 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:559a8e4aab60 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:559a8e4aab60 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 36
mrsoundhar 0:559a8e4aab60 37
mrsoundhar 0:559a8e4aab60 38 #if defined ( __ICCARM__ )
mrsoundhar 0:559a8e4aab60 39 #pragma system_include /* treat file as system include file for MISRA check */
mrsoundhar 0:559a8e4aab60 40 #endif
mrsoundhar 0:559a8e4aab60 41
mrsoundhar 0:559a8e4aab60 42 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 43 extern "C" {
mrsoundhar 0:559a8e4aab60 44 #endif
mrsoundhar 0:559a8e4aab60 45
mrsoundhar 0:559a8e4aab60 46 #ifndef __CORE_CM0_H_GENERIC
mrsoundhar 0:559a8e4aab60 47 #define __CORE_CM0_H_GENERIC
mrsoundhar 0:559a8e4aab60 48
mrsoundhar 0:559a8e4aab60 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mrsoundhar 0:559a8e4aab60 50 CMSIS violates the following MISRA-C:2004 rules:
mrsoundhar 0:559a8e4aab60 51
mrsoundhar 0:559a8e4aab60 52 \li Required Rule 8.5, object/function definition in header file.<br>
mrsoundhar 0:559a8e4aab60 53 Function definitions in header files are used to allow 'inlining'.
mrsoundhar 0:559a8e4aab60 54
mrsoundhar 0:559a8e4aab60 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mrsoundhar 0:559a8e4aab60 56 Unions are used for effective representation of core registers.
mrsoundhar 0:559a8e4aab60 57
mrsoundhar 0:559a8e4aab60 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mrsoundhar 0:559a8e4aab60 59 Function-like macros are used to allow more efficient code.
mrsoundhar 0:559a8e4aab60 60 */
mrsoundhar 0:559a8e4aab60 61
mrsoundhar 0:559a8e4aab60 62
mrsoundhar 0:559a8e4aab60 63 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 64 * CMSIS definitions
mrsoundhar 0:559a8e4aab60 65 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 66 /** \ingroup Cortex_M0
mrsoundhar 0:559a8e4aab60 67 @{
mrsoundhar 0:559a8e4aab60 68 */
mrsoundhar 0:559a8e4aab60 69
mrsoundhar 0:559a8e4aab60 70 /* CMSIS CM0 definitions */
mrsoundhar 0:559a8e4aab60 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
mrsoundhar 0:559a8e4aab60 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
mrsoundhar 0:559a8e4aab60 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
mrsoundhar 0:559a8e4aab60 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mrsoundhar 0:559a8e4aab60 75
mrsoundhar 0:559a8e4aab60 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
mrsoundhar 0:559a8e4aab60 77
mrsoundhar 0:559a8e4aab60 78
mrsoundhar 0:559a8e4aab60 79 #if defined ( __CC_ARM )
mrsoundhar 0:559a8e4aab60 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mrsoundhar 0:559a8e4aab60 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mrsoundhar 0:559a8e4aab60 82 #define __STATIC_INLINE static __inline
mrsoundhar 0:559a8e4aab60 83
mrsoundhar 0:559a8e4aab60 84 #elif defined ( __ICCARM__ )
mrsoundhar 0:559a8e4aab60 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mrsoundhar 0:559a8e4aab60 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mrsoundhar 0:559a8e4aab60 87 #define __STATIC_INLINE static inline
mrsoundhar 0:559a8e4aab60 88
mrsoundhar 0:559a8e4aab60 89 #elif defined ( __GNUC__ )
mrsoundhar 0:559a8e4aab60 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mrsoundhar 0:559a8e4aab60 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mrsoundhar 0:559a8e4aab60 92 #define __STATIC_INLINE static inline
mrsoundhar 0:559a8e4aab60 93
mrsoundhar 0:559a8e4aab60 94 #elif defined ( __TASKING__ )
mrsoundhar 0:559a8e4aab60 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mrsoundhar 0:559a8e4aab60 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mrsoundhar 0:559a8e4aab60 97 #define __STATIC_INLINE static inline
mrsoundhar 0:559a8e4aab60 98
mrsoundhar 0:559a8e4aab60 99 #endif
mrsoundhar 0:559a8e4aab60 100
mrsoundhar 0:559a8e4aab60 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
mrsoundhar 0:559a8e4aab60 102 */
mrsoundhar 0:559a8e4aab60 103 #define __FPU_USED 0
mrsoundhar 0:559a8e4aab60 104
mrsoundhar 0:559a8e4aab60 105 #if defined ( __CC_ARM )
mrsoundhar 0:559a8e4aab60 106 #if defined __TARGET_FPU_VFP
mrsoundhar 0:559a8e4aab60 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 108 #endif
mrsoundhar 0:559a8e4aab60 109
mrsoundhar 0:559a8e4aab60 110 #elif defined ( __ICCARM__ )
mrsoundhar 0:559a8e4aab60 111 #if defined __ARMVFP__
mrsoundhar 0:559a8e4aab60 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 113 #endif
mrsoundhar 0:559a8e4aab60 114
mrsoundhar 0:559a8e4aab60 115 #elif defined ( __GNUC__ )
mrsoundhar 0:559a8e4aab60 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mrsoundhar 0:559a8e4aab60 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 118 #endif
mrsoundhar 0:559a8e4aab60 119
mrsoundhar 0:559a8e4aab60 120 #elif defined ( __TASKING__ )
mrsoundhar 0:559a8e4aab60 121 #if defined __FPU_VFP__
mrsoundhar 0:559a8e4aab60 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mrsoundhar 0:559a8e4aab60 123 #endif
mrsoundhar 0:559a8e4aab60 124 #endif
mrsoundhar 0:559a8e4aab60 125
mrsoundhar 0:559a8e4aab60 126 #include <stdint.h> /* standard types definitions */
mrsoundhar 0:559a8e4aab60 127 #include <core_cmInstr.h> /* Core Instruction Access */
mrsoundhar 0:559a8e4aab60 128 #include <core_cmFunc.h> /* Core Function Access */
mrsoundhar 0:559a8e4aab60 129
mrsoundhar 0:559a8e4aab60 130 #endif /* __CORE_CM0_H_GENERIC */
mrsoundhar 0:559a8e4aab60 131
mrsoundhar 0:559a8e4aab60 132 #ifndef __CMSIS_GENERIC
mrsoundhar 0:559a8e4aab60 133
mrsoundhar 0:559a8e4aab60 134 #ifndef __CORE_CM0_H_DEPENDANT
mrsoundhar 0:559a8e4aab60 135 #define __CORE_CM0_H_DEPENDANT
mrsoundhar 0:559a8e4aab60 136
mrsoundhar 0:559a8e4aab60 137 /* check device defines and use defaults */
mrsoundhar 0:559a8e4aab60 138 #if defined __CHECK_DEVICE_DEFINES
mrsoundhar 0:559a8e4aab60 139 #ifndef __CM0_REV
mrsoundhar 0:559a8e4aab60 140 #define __CM0_REV 0x0000
mrsoundhar 0:559a8e4aab60 141 #warning "__CM0_REV not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 142 #endif
mrsoundhar 0:559a8e4aab60 143
mrsoundhar 0:559a8e4aab60 144 #ifndef __NVIC_PRIO_BITS
mrsoundhar 0:559a8e4aab60 145 #define __NVIC_PRIO_BITS 2
mrsoundhar 0:559a8e4aab60 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 147 #endif
mrsoundhar 0:559a8e4aab60 148
mrsoundhar 0:559a8e4aab60 149 #ifndef __Vendor_SysTickConfig
mrsoundhar 0:559a8e4aab60 150 #define __Vendor_SysTickConfig 0
mrsoundhar 0:559a8e4aab60 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mrsoundhar 0:559a8e4aab60 152 #endif
mrsoundhar 0:559a8e4aab60 153 #endif
mrsoundhar 0:559a8e4aab60 154
mrsoundhar 0:559a8e4aab60 155 /* IO definitions (access restrictions to peripheral registers) */
mrsoundhar 0:559a8e4aab60 156 /**
mrsoundhar 0:559a8e4aab60 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
mrsoundhar 0:559a8e4aab60 158
mrsoundhar 0:559a8e4aab60 159 <strong>IO Type Qualifiers</strong> are used
mrsoundhar 0:559a8e4aab60 160 \li to specify the access to peripheral variables.
mrsoundhar 0:559a8e4aab60 161 \li for automatic generation of peripheral register debug information.
mrsoundhar 0:559a8e4aab60 162 */
mrsoundhar 0:559a8e4aab60 163 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 164 #define __I volatile /*!< Defines 'read only' permissions */
mrsoundhar 0:559a8e4aab60 165 #else
mrsoundhar 0:559a8e4aab60 166 #define __I volatile const /*!< Defines 'read only' permissions */
mrsoundhar 0:559a8e4aab60 167 #endif
mrsoundhar 0:559a8e4aab60 168 #define __O volatile /*!< Defines 'write only' permissions */
mrsoundhar 0:559a8e4aab60 169 #define __IO volatile /*!< Defines 'read / write' permissions */
mrsoundhar 0:559a8e4aab60 170
mrsoundhar 0:559a8e4aab60 171 /*@} end of group Cortex_M0 */
mrsoundhar 0:559a8e4aab60 172
mrsoundhar 0:559a8e4aab60 173
mrsoundhar 0:559a8e4aab60 174
mrsoundhar 0:559a8e4aab60 175 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 176 * Register Abstraction
mrsoundhar 0:559a8e4aab60 177 Core Register contain:
mrsoundhar 0:559a8e4aab60 178 - Core Register
mrsoundhar 0:559a8e4aab60 179 - Core NVIC Register
mrsoundhar 0:559a8e4aab60 180 - Core SCB Register
mrsoundhar 0:559a8e4aab60 181 - Core SysTick Register
mrsoundhar 0:559a8e4aab60 182 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
mrsoundhar 0:559a8e4aab60 184 \brief Type definitions and defines for Cortex-M processor based devices.
mrsoundhar 0:559a8e4aab60 185 */
mrsoundhar 0:559a8e4aab60 186
mrsoundhar 0:559a8e4aab60 187 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 188 \defgroup CMSIS_CORE Status and Control Registers
mrsoundhar 0:559a8e4aab60 189 \brief Core Register type definitions.
mrsoundhar 0:559a8e4aab60 190 @{
mrsoundhar 0:559a8e4aab60 191 */
mrsoundhar 0:559a8e4aab60 192
mrsoundhar 0:559a8e4aab60 193 /** \brief Union type to access the Application Program Status Register (APSR).
mrsoundhar 0:559a8e4aab60 194 */
mrsoundhar 0:559a8e4aab60 195 typedef union
mrsoundhar 0:559a8e4aab60 196 {
mrsoundhar 0:559a8e4aab60 197 struct
mrsoundhar 0:559a8e4aab60 198 {
mrsoundhar 0:559a8e4aab60 199 #if (__CORTEX_M != 0x04)
mrsoundhar 0:559a8e4aab60 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mrsoundhar 0:559a8e4aab60 201 #else
mrsoundhar 0:559a8e4aab60 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mrsoundhar 0:559a8e4aab60 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mrsoundhar 0:559a8e4aab60 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mrsoundhar 0:559a8e4aab60 205 #endif
mrsoundhar 0:559a8e4aab60 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mrsoundhar 0:559a8e4aab60 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mrsoundhar 0:559a8e4aab60 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mrsoundhar 0:559a8e4aab60 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mrsoundhar 0:559a8e4aab60 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mrsoundhar 0:559a8e4aab60 211 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 212 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 213 } APSR_Type;
mrsoundhar 0:559a8e4aab60 214
mrsoundhar 0:559a8e4aab60 215
mrsoundhar 0:559a8e4aab60 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mrsoundhar 0:559a8e4aab60 217 */
mrsoundhar 0:559a8e4aab60 218 typedef union
mrsoundhar 0:559a8e4aab60 219 {
mrsoundhar 0:559a8e4aab60 220 struct
mrsoundhar 0:559a8e4aab60 221 {
mrsoundhar 0:559a8e4aab60 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mrsoundhar 0:559a8e4aab60 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mrsoundhar 0:559a8e4aab60 224 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 225 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 226 } IPSR_Type;
mrsoundhar 0:559a8e4aab60 227
mrsoundhar 0:559a8e4aab60 228
mrsoundhar 0:559a8e4aab60 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mrsoundhar 0:559a8e4aab60 230 */
mrsoundhar 0:559a8e4aab60 231 typedef union
mrsoundhar 0:559a8e4aab60 232 {
mrsoundhar 0:559a8e4aab60 233 struct
mrsoundhar 0:559a8e4aab60 234 {
mrsoundhar 0:559a8e4aab60 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mrsoundhar 0:559a8e4aab60 236 #if (__CORTEX_M != 0x04)
mrsoundhar 0:559a8e4aab60 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mrsoundhar 0:559a8e4aab60 238 #else
mrsoundhar 0:559a8e4aab60 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mrsoundhar 0:559a8e4aab60 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mrsoundhar 0:559a8e4aab60 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mrsoundhar 0:559a8e4aab60 242 #endif
mrsoundhar 0:559a8e4aab60 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mrsoundhar 0:559a8e4aab60 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mrsoundhar 0:559a8e4aab60 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mrsoundhar 0:559a8e4aab60 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mrsoundhar 0:559a8e4aab60 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mrsoundhar 0:559a8e4aab60 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mrsoundhar 0:559a8e4aab60 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mrsoundhar 0:559a8e4aab60 250 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 251 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 252 } xPSR_Type;
mrsoundhar 0:559a8e4aab60 253
mrsoundhar 0:559a8e4aab60 254
mrsoundhar 0:559a8e4aab60 255 /** \brief Union type to access the Control Registers (CONTROL).
mrsoundhar 0:559a8e4aab60 256 */
mrsoundhar 0:559a8e4aab60 257 typedef union
mrsoundhar 0:559a8e4aab60 258 {
mrsoundhar 0:559a8e4aab60 259 struct
mrsoundhar 0:559a8e4aab60 260 {
mrsoundhar 0:559a8e4aab60 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mrsoundhar 0:559a8e4aab60 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mrsoundhar 0:559a8e4aab60 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mrsoundhar 0:559a8e4aab60 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mrsoundhar 0:559a8e4aab60 265 } b; /*!< Structure used for bit access */
mrsoundhar 0:559a8e4aab60 266 uint32_t w; /*!< Type used for word access */
mrsoundhar 0:559a8e4aab60 267 } CONTROL_Type;
mrsoundhar 0:559a8e4aab60 268
mrsoundhar 0:559a8e4aab60 269 /*@} end of group CMSIS_CORE */
mrsoundhar 0:559a8e4aab60 270
mrsoundhar 0:559a8e4aab60 271
mrsoundhar 0:559a8e4aab60 272 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mrsoundhar 0:559a8e4aab60 274 \brief Type definitions for the NVIC Registers
mrsoundhar 0:559a8e4aab60 275 @{
mrsoundhar 0:559a8e4aab60 276 */
mrsoundhar 0:559a8e4aab60 277
mrsoundhar 0:559a8e4aab60 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mrsoundhar 0:559a8e4aab60 279 */
mrsoundhar 0:559a8e4aab60 280 typedef struct
mrsoundhar 0:559a8e4aab60 281 {
mrsoundhar 0:559a8e4aab60 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mrsoundhar 0:559a8e4aab60 283 uint32_t RESERVED0[31];
mrsoundhar 0:559a8e4aab60 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mrsoundhar 0:559a8e4aab60 285 uint32_t RSERVED1[31];
mrsoundhar 0:559a8e4aab60 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mrsoundhar 0:559a8e4aab60 287 uint32_t RESERVED2[31];
mrsoundhar 0:559a8e4aab60 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mrsoundhar 0:559a8e4aab60 289 uint32_t RESERVED3[31];
mrsoundhar 0:559a8e4aab60 290 uint32_t RESERVED4[64];
mrsoundhar 0:559a8e4aab60 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
mrsoundhar 0:559a8e4aab60 292 } NVIC_Type;
mrsoundhar 0:559a8e4aab60 293
mrsoundhar 0:559a8e4aab60 294 /*@} end of group CMSIS_NVIC */
mrsoundhar 0:559a8e4aab60 295
mrsoundhar 0:559a8e4aab60 296
mrsoundhar 0:559a8e4aab60 297 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 298 \defgroup CMSIS_SCB System Control Block (SCB)
mrsoundhar 0:559a8e4aab60 299 \brief Type definitions for the System Control Block Registers
mrsoundhar 0:559a8e4aab60 300 @{
mrsoundhar 0:559a8e4aab60 301 */
mrsoundhar 0:559a8e4aab60 302
mrsoundhar 0:559a8e4aab60 303 /** \brief Structure type to access the System Control Block (SCB).
mrsoundhar 0:559a8e4aab60 304 */
mrsoundhar 0:559a8e4aab60 305 typedef struct
mrsoundhar 0:559a8e4aab60 306 {
mrsoundhar 0:559a8e4aab60 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mrsoundhar 0:559a8e4aab60 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mrsoundhar 0:559a8e4aab60 309 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mrsoundhar 0:559a8e4aab60 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mrsoundhar 0:559a8e4aab60 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mrsoundhar 0:559a8e4aab60 313 uint32_t RESERVED1;
mrsoundhar 0:559a8e4aab60 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
mrsoundhar 0:559a8e4aab60 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mrsoundhar 0:559a8e4aab60 316 } SCB_Type;
mrsoundhar 0:559a8e4aab60 317
mrsoundhar 0:559a8e4aab60 318 /* SCB CPUID Register Definitions */
mrsoundhar 0:559a8e4aab60 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mrsoundhar 0:559a8e4aab60 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mrsoundhar 0:559a8e4aab60 321
mrsoundhar 0:559a8e4aab60 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mrsoundhar 0:559a8e4aab60 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mrsoundhar 0:559a8e4aab60 324
mrsoundhar 0:559a8e4aab60 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mrsoundhar 0:559a8e4aab60 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mrsoundhar 0:559a8e4aab60 327
mrsoundhar 0:559a8e4aab60 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mrsoundhar 0:559a8e4aab60 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mrsoundhar 0:559a8e4aab60 330
mrsoundhar 0:559a8e4aab60 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mrsoundhar 0:559a8e4aab60 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
mrsoundhar 0:559a8e4aab60 333
mrsoundhar 0:559a8e4aab60 334 /* SCB Interrupt Control State Register Definitions */
mrsoundhar 0:559a8e4aab60 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mrsoundhar 0:559a8e4aab60 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mrsoundhar 0:559a8e4aab60 337
mrsoundhar 0:559a8e4aab60 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mrsoundhar 0:559a8e4aab60 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mrsoundhar 0:559a8e4aab60 340
mrsoundhar 0:559a8e4aab60 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mrsoundhar 0:559a8e4aab60 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mrsoundhar 0:559a8e4aab60 343
mrsoundhar 0:559a8e4aab60 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mrsoundhar 0:559a8e4aab60 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mrsoundhar 0:559a8e4aab60 346
mrsoundhar 0:559a8e4aab60 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mrsoundhar 0:559a8e4aab60 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mrsoundhar 0:559a8e4aab60 349
mrsoundhar 0:559a8e4aab60 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mrsoundhar 0:559a8e4aab60 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mrsoundhar 0:559a8e4aab60 352
mrsoundhar 0:559a8e4aab60 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mrsoundhar 0:559a8e4aab60 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mrsoundhar 0:559a8e4aab60 355
mrsoundhar 0:559a8e4aab60 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mrsoundhar 0:559a8e4aab60 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mrsoundhar 0:559a8e4aab60 358
mrsoundhar 0:559a8e4aab60 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mrsoundhar 0:559a8e4aab60 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
mrsoundhar 0:559a8e4aab60 361
mrsoundhar 0:559a8e4aab60 362 /* SCB Application Interrupt and Reset Control Register Definitions */
mrsoundhar 0:559a8e4aab60 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mrsoundhar 0:559a8e4aab60 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mrsoundhar 0:559a8e4aab60 365
mrsoundhar 0:559a8e4aab60 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mrsoundhar 0:559a8e4aab60 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mrsoundhar 0:559a8e4aab60 368
mrsoundhar 0:559a8e4aab60 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mrsoundhar 0:559a8e4aab60 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mrsoundhar 0:559a8e4aab60 371
mrsoundhar 0:559a8e4aab60 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mrsoundhar 0:559a8e4aab60 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mrsoundhar 0:559a8e4aab60 374
mrsoundhar 0:559a8e4aab60 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mrsoundhar 0:559a8e4aab60 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mrsoundhar 0:559a8e4aab60 377
mrsoundhar 0:559a8e4aab60 378 /* SCB System Control Register Definitions */
mrsoundhar 0:559a8e4aab60 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mrsoundhar 0:559a8e4aab60 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mrsoundhar 0:559a8e4aab60 381
mrsoundhar 0:559a8e4aab60 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mrsoundhar 0:559a8e4aab60 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mrsoundhar 0:559a8e4aab60 384
mrsoundhar 0:559a8e4aab60 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mrsoundhar 0:559a8e4aab60 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mrsoundhar 0:559a8e4aab60 387
mrsoundhar 0:559a8e4aab60 388 /* SCB Configuration Control Register Definitions */
mrsoundhar 0:559a8e4aab60 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mrsoundhar 0:559a8e4aab60 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mrsoundhar 0:559a8e4aab60 391
mrsoundhar 0:559a8e4aab60 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mrsoundhar 0:559a8e4aab60 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mrsoundhar 0:559a8e4aab60 394
mrsoundhar 0:559a8e4aab60 395 /* SCB System Handler Control and State Register Definitions */
mrsoundhar 0:559a8e4aab60 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mrsoundhar 0:559a8e4aab60 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mrsoundhar 0:559a8e4aab60 398
mrsoundhar 0:559a8e4aab60 399 /*@} end of group CMSIS_SCB */
mrsoundhar 0:559a8e4aab60 400
mrsoundhar 0:559a8e4aab60 401
mrsoundhar 0:559a8e4aab60 402 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mrsoundhar 0:559a8e4aab60 404 \brief Type definitions for the System Timer Registers.
mrsoundhar 0:559a8e4aab60 405 @{
mrsoundhar 0:559a8e4aab60 406 */
mrsoundhar 0:559a8e4aab60 407
mrsoundhar 0:559a8e4aab60 408 /** \brief Structure type to access the System Timer (SysTick).
mrsoundhar 0:559a8e4aab60 409 */
mrsoundhar 0:559a8e4aab60 410 typedef struct
mrsoundhar 0:559a8e4aab60 411 {
mrsoundhar 0:559a8e4aab60 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mrsoundhar 0:559a8e4aab60 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mrsoundhar 0:559a8e4aab60 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mrsoundhar 0:559a8e4aab60 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mrsoundhar 0:559a8e4aab60 416 } SysTick_Type;
mrsoundhar 0:559a8e4aab60 417
mrsoundhar 0:559a8e4aab60 418 /* SysTick Control / Status Register Definitions */
mrsoundhar 0:559a8e4aab60 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mrsoundhar 0:559a8e4aab60 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mrsoundhar 0:559a8e4aab60 421
mrsoundhar 0:559a8e4aab60 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mrsoundhar 0:559a8e4aab60 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mrsoundhar 0:559a8e4aab60 424
mrsoundhar 0:559a8e4aab60 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mrsoundhar 0:559a8e4aab60 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mrsoundhar 0:559a8e4aab60 427
mrsoundhar 0:559a8e4aab60 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mrsoundhar 0:559a8e4aab60 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
mrsoundhar 0:559a8e4aab60 430
mrsoundhar 0:559a8e4aab60 431 /* SysTick Reload Register Definitions */
mrsoundhar 0:559a8e4aab60 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mrsoundhar 0:559a8e4aab60 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
mrsoundhar 0:559a8e4aab60 434
mrsoundhar 0:559a8e4aab60 435 /* SysTick Current Register Definitions */
mrsoundhar 0:559a8e4aab60 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mrsoundhar 0:559a8e4aab60 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
mrsoundhar 0:559a8e4aab60 438
mrsoundhar 0:559a8e4aab60 439 /* SysTick Calibration Register Definitions */
mrsoundhar 0:559a8e4aab60 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mrsoundhar 0:559a8e4aab60 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mrsoundhar 0:559a8e4aab60 442
mrsoundhar 0:559a8e4aab60 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mrsoundhar 0:559a8e4aab60 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mrsoundhar 0:559a8e4aab60 445
mrsoundhar 0:559a8e4aab60 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mrsoundhar 0:559a8e4aab60 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
mrsoundhar 0:559a8e4aab60 448
mrsoundhar 0:559a8e4aab60 449 /*@} end of group CMSIS_SysTick */
mrsoundhar 0:559a8e4aab60 450
mrsoundhar 0:559a8e4aab60 451
mrsoundhar 0:559a8e4aab60 452 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mrsoundhar 0:559a8e4aab60 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
mrsoundhar 0:559a8e4aab60 455 are only accessible over DAP and not via processor. Therefore
mrsoundhar 0:559a8e4aab60 456 they are not covered by the Cortex-M0 header file.
mrsoundhar 0:559a8e4aab60 457 @{
mrsoundhar 0:559a8e4aab60 458 */
mrsoundhar 0:559a8e4aab60 459 /*@} end of group CMSIS_CoreDebug */
mrsoundhar 0:559a8e4aab60 460
mrsoundhar 0:559a8e4aab60 461
mrsoundhar 0:559a8e4aab60 462 /** \ingroup CMSIS_core_register
mrsoundhar 0:559a8e4aab60 463 \defgroup CMSIS_core_base Core Definitions
mrsoundhar 0:559a8e4aab60 464 \brief Definitions for base addresses, unions, and structures.
mrsoundhar 0:559a8e4aab60 465 @{
mrsoundhar 0:559a8e4aab60 466 */
mrsoundhar 0:559a8e4aab60 467
mrsoundhar 0:559a8e4aab60 468 /* Memory mapping of Cortex-M0 Hardware */
mrsoundhar 0:559a8e4aab60 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mrsoundhar 0:559a8e4aab60 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mrsoundhar 0:559a8e4aab60 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mrsoundhar 0:559a8e4aab60 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mrsoundhar 0:559a8e4aab60 473
mrsoundhar 0:559a8e4aab60 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mrsoundhar 0:559a8e4aab60 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mrsoundhar 0:559a8e4aab60 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mrsoundhar 0:559a8e4aab60 477
mrsoundhar 0:559a8e4aab60 478
mrsoundhar 0:559a8e4aab60 479 /*@} */
mrsoundhar 0:559a8e4aab60 480
mrsoundhar 0:559a8e4aab60 481
mrsoundhar 0:559a8e4aab60 482
mrsoundhar 0:559a8e4aab60 483 /*******************************************************************************
mrsoundhar 0:559a8e4aab60 484 * Hardware Abstraction Layer
mrsoundhar 0:559a8e4aab60 485 Core Function Interface contains:
mrsoundhar 0:559a8e4aab60 486 - Core NVIC Functions
mrsoundhar 0:559a8e4aab60 487 - Core SysTick Functions
mrsoundhar 0:559a8e4aab60 488 - Core Register Access Functions
mrsoundhar 0:559a8e4aab60 489 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mrsoundhar 0:559a8e4aab60 491 */
mrsoundhar 0:559a8e4aab60 492
mrsoundhar 0:559a8e4aab60 493
mrsoundhar 0:559a8e4aab60 494
mrsoundhar 0:559a8e4aab60 495 /* ########################## NVIC functions #################################### */
mrsoundhar 0:559a8e4aab60 496 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:559a8e4aab60 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mrsoundhar 0:559a8e4aab60 498 \brief Functions that manage interrupts and exceptions via the NVIC.
mrsoundhar 0:559a8e4aab60 499 @{
mrsoundhar 0:559a8e4aab60 500 */
mrsoundhar 0:559a8e4aab60 501
mrsoundhar 0:559a8e4aab60 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
mrsoundhar 0:559a8e4aab60 503 /* The following MACROS handle generation of the register offset and byte masks */
mrsoundhar 0:559a8e4aab60 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
mrsoundhar 0:559a8e4aab60 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
mrsoundhar 0:559a8e4aab60 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
mrsoundhar 0:559a8e4aab60 507
mrsoundhar 0:559a8e4aab60 508
mrsoundhar 0:559a8e4aab60 509 /** \brief Enable External Interrupt
mrsoundhar 0:559a8e4aab60 510
mrsoundhar 0:559a8e4aab60 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
mrsoundhar 0:559a8e4aab60 512
mrsoundhar 0:559a8e4aab60 513 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 514 */
mrsoundhar 0:559a8e4aab60 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 516 {
mrsoundhar 0:559a8e4aab60 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mrsoundhar 0:559a8e4aab60 518 }
mrsoundhar 0:559a8e4aab60 519
mrsoundhar 0:559a8e4aab60 520
mrsoundhar 0:559a8e4aab60 521 /** \brief Disable External Interrupt
mrsoundhar 0:559a8e4aab60 522
mrsoundhar 0:559a8e4aab60 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
mrsoundhar 0:559a8e4aab60 524
mrsoundhar 0:559a8e4aab60 525 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 526 */
mrsoundhar 0:559a8e4aab60 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 528 {
mrsoundhar 0:559a8e4aab60 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mrsoundhar 0:559a8e4aab60 530 }
mrsoundhar 0:559a8e4aab60 531
mrsoundhar 0:559a8e4aab60 532
mrsoundhar 0:559a8e4aab60 533 /** \brief Get Pending Interrupt
mrsoundhar 0:559a8e4aab60 534
mrsoundhar 0:559a8e4aab60 535 The function reads the pending register in the NVIC and returns the pending bit
mrsoundhar 0:559a8e4aab60 536 for the specified interrupt.
mrsoundhar 0:559a8e4aab60 537
mrsoundhar 0:559a8e4aab60 538 \param [in] IRQn Interrupt number.
mrsoundhar 0:559a8e4aab60 539
mrsoundhar 0:559a8e4aab60 540 \return 0 Interrupt status is not pending.
mrsoundhar 0:559a8e4aab60 541 \return 1 Interrupt status is pending.
mrsoundhar 0:559a8e4aab60 542 */
mrsoundhar 0:559a8e4aab60 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 544 {
mrsoundhar 0:559a8e4aab60 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
mrsoundhar 0:559a8e4aab60 546 }
mrsoundhar 0:559a8e4aab60 547
mrsoundhar 0:559a8e4aab60 548
mrsoundhar 0:559a8e4aab60 549 /** \brief Set Pending Interrupt
mrsoundhar 0:559a8e4aab60 550
mrsoundhar 0:559a8e4aab60 551 The function sets the pending bit of an external interrupt.
mrsoundhar 0:559a8e4aab60 552
mrsoundhar 0:559a8e4aab60 553 \param [in] IRQn Interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 554 */
mrsoundhar 0:559a8e4aab60 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 556 {
mrsoundhar 0:559a8e4aab60 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
mrsoundhar 0:559a8e4aab60 558 }
mrsoundhar 0:559a8e4aab60 559
mrsoundhar 0:559a8e4aab60 560
mrsoundhar 0:559a8e4aab60 561 /** \brief Clear Pending Interrupt
mrsoundhar 0:559a8e4aab60 562
mrsoundhar 0:559a8e4aab60 563 The function clears the pending bit of an external interrupt.
mrsoundhar 0:559a8e4aab60 564
mrsoundhar 0:559a8e4aab60 565 \param [in] IRQn External interrupt number. Value cannot be negative.
mrsoundhar 0:559a8e4aab60 566 */
mrsoundhar 0:559a8e4aab60 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 568 {
mrsoundhar 0:559a8e4aab60 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
mrsoundhar 0:559a8e4aab60 570 }
mrsoundhar 0:559a8e4aab60 571
mrsoundhar 0:559a8e4aab60 572
mrsoundhar 0:559a8e4aab60 573 /** \brief Set Interrupt Priority
mrsoundhar 0:559a8e4aab60 574
mrsoundhar 0:559a8e4aab60 575 The function sets the priority of an interrupt.
mrsoundhar 0:559a8e4aab60 576
mrsoundhar 0:559a8e4aab60 577 \note The priority cannot be set for every core interrupt.
mrsoundhar 0:559a8e4aab60 578
mrsoundhar 0:559a8e4aab60 579 \param [in] IRQn Interrupt number.
mrsoundhar 0:559a8e4aab60 580 \param [in] priority Priority to set.
mrsoundhar 0:559a8e4aab60 581 */
mrsoundhar 0:559a8e4aab60 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mrsoundhar 0:559a8e4aab60 583 {
mrsoundhar 0:559a8e4aab60 584 if(IRQn < 0) {
mrsoundhar 0:559a8e4aab60 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mrsoundhar 0:559a8e4aab60 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mrsoundhar 0:559a8e4aab60 587 else {
mrsoundhar 0:559a8e4aab60 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
mrsoundhar 0:559a8e4aab60 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
mrsoundhar 0:559a8e4aab60 590 }
mrsoundhar 0:559a8e4aab60 591
mrsoundhar 0:559a8e4aab60 592
mrsoundhar 0:559a8e4aab60 593 /** \brief Get Interrupt Priority
mrsoundhar 0:559a8e4aab60 594
mrsoundhar 0:559a8e4aab60 595 The function reads the priority of an interrupt. The interrupt
mrsoundhar 0:559a8e4aab60 596 number can be positive to specify an external (device specific)
mrsoundhar 0:559a8e4aab60 597 interrupt, or negative to specify an internal (core) interrupt.
mrsoundhar 0:559a8e4aab60 598
mrsoundhar 0:559a8e4aab60 599
mrsoundhar 0:559a8e4aab60 600 \param [in] IRQn Interrupt number.
mrsoundhar 0:559a8e4aab60 601 \return Interrupt Priority. Value is aligned automatically to the implemented
mrsoundhar 0:559a8e4aab60 602 priority bits of the microcontroller.
mrsoundhar 0:559a8e4aab60 603 */
mrsoundhar 0:559a8e4aab60 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mrsoundhar 0:559a8e4aab60 605 {
mrsoundhar 0:559a8e4aab60 606
mrsoundhar 0:559a8e4aab60 607 if(IRQn < 0) {
mrsoundhar 0:559a8e4aab60 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
mrsoundhar 0:559a8e4aab60 609 else {
mrsoundhar 0:559a8e4aab60 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
mrsoundhar 0:559a8e4aab60 611 }
mrsoundhar 0:559a8e4aab60 612
mrsoundhar 0:559a8e4aab60 613
mrsoundhar 0:559a8e4aab60 614 /** \brief System Reset
mrsoundhar 0:559a8e4aab60 615
mrsoundhar 0:559a8e4aab60 616 The function initiates a system reset request to reset the MCU.
mrsoundhar 0:559a8e4aab60 617 */
mrsoundhar 0:559a8e4aab60 618 __STATIC_INLINE void NVIC_SystemReset(void)
mrsoundhar 0:559a8e4aab60 619 {
mrsoundhar 0:559a8e4aab60 620 __DSB(); /* Ensure all outstanding memory accesses included
mrsoundhar 0:559a8e4aab60 621 buffered write are completed before reset */
mrsoundhar 0:559a8e4aab60 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
mrsoundhar 0:559a8e4aab60 623 SCB_AIRCR_SYSRESETREQ_Msk);
mrsoundhar 0:559a8e4aab60 624 __DSB(); /* Ensure completion of memory access */
mrsoundhar 0:559a8e4aab60 625 while(1); /* wait until reset */
mrsoundhar 0:559a8e4aab60 626 }
mrsoundhar 0:559a8e4aab60 627
mrsoundhar 0:559a8e4aab60 628 /*@} end of CMSIS_Core_NVICFunctions */
mrsoundhar 0:559a8e4aab60 629
mrsoundhar 0:559a8e4aab60 630
mrsoundhar 0:559a8e4aab60 631
mrsoundhar 0:559a8e4aab60 632 /* ################################## SysTick function ############################################ */
mrsoundhar 0:559a8e4aab60 633 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:559a8e4aab60 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mrsoundhar 0:559a8e4aab60 635 \brief Functions that configure the System.
mrsoundhar 0:559a8e4aab60 636 @{
mrsoundhar 0:559a8e4aab60 637 */
mrsoundhar 0:559a8e4aab60 638
mrsoundhar 0:559a8e4aab60 639 #if (__Vendor_SysTickConfig == 0)
mrsoundhar 0:559a8e4aab60 640
mrsoundhar 0:559a8e4aab60 641 /** \brief System Tick Configuration
mrsoundhar 0:559a8e4aab60 642
mrsoundhar 0:559a8e4aab60 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mrsoundhar 0:559a8e4aab60 644 Counter is in free running mode to generate periodic interrupts.
mrsoundhar 0:559a8e4aab60 645
mrsoundhar 0:559a8e4aab60 646 \param [in] ticks Number of ticks between two interrupts.
mrsoundhar 0:559a8e4aab60 647
mrsoundhar 0:559a8e4aab60 648 \return 0 Function succeeded.
mrsoundhar 0:559a8e4aab60 649 \return 1 Function failed.
mrsoundhar 0:559a8e4aab60 650
mrsoundhar 0:559a8e4aab60 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mrsoundhar 0:559a8e4aab60 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mrsoundhar 0:559a8e4aab60 653 must contain a vendor-specific implementation of this function.
mrsoundhar 0:559a8e4aab60 654
mrsoundhar 0:559a8e4aab60 655 */
mrsoundhar 0:559a8e4aab60 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mrsoundhar 0:559a8e4aab60 657 {
mrsoundhar 0:559a8e4aab60 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
mrsoundhar 0:559a8e4aab60 659
mrsoundhar 0:559a8e4aab60 660 SysTick->LOAD = ticks - 1; /* set reload register */
mrsoundhar 0:559a8e4aab60 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
mrsoundhar 0:559a8e4aab60 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
mrsoundhar 0:559a8e4aab60 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mrsoundhar 0:559a8e4aab60 664 SysTick_CTRL_TICKINT_Msk |
mrsoundhar 0:559a8e4aab60 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mrsoundhar 0:559a8e4aab60 666 return (0); /* Function successful */
mrsoundhar 0:559a8e4aab60 667 }
mrsoundhar 0:559a8e4aab60 668
mrsoundhar 0:559a8e4aab60 669 #endif
mrsoundhar 0:559a8e4aab60 670
mrsoundhar 0:559a8e4aab60 671 /*@} end of CMSIS_Core_SysTickFunctions */
mrsoundhar 0:559a8e4aab60 672
mrsoundhar 0:559a8e4aab60 673
mrsoundhar 0:559a8e4aab60 674
mrsoundhar 0:559a8e4aab60 675
mrsoundhar 0:559a8e4aab60 676 #endif /* __CORE_CM0_H_DEPENDANT */
mrsoundhar 0:559a8e4aab60 677
mrsoundhar 0:559a8e4aab60 678 #endif /* __CMSIS_GENERIC */
mrsoundhar 0:559a8e4aab60 679
mrsoundhar 0:559a8e4aab60 680 #ifdef __cplusplus
mrsoundhar 0:559a8e4aab60 681 }
mrsoundhar 0:559a8e4aab60 682 #endif