Sertel_Srinath Gopalan / TARGET_LPC1768i2c

myi2c test

LPC17xx.h@0:559a8e4aab60, 2015-06-29 (annotated)

Committer:
mrsoundhar
Date:
Mon Jun 29 12:59:52 2015 +0000
Revision:
0:559a8e4aab60
i2c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mrsoundhar 0:559a8e4aab60 1 /**************************************************************************//**
mrsoundhar 0:559a8e4aab60 2 * @file LPC17xx.h
mrsoundhar 0:559a8e4aab60 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
mrsoundhar 0:559a8e4aab60 4 * NXP LPC17xx Device Series
mrsoundhar 0:559a8e4aab60 5 * @version: V1.09
mrsoundhar 0:559a8e4aab60 6 * @date: 17. March 2010
mrsoundhar 0:559a8e4aab60 7
mrsoundhar 0:559a8e4aab60 8 *
mrsoundhar 0:559a8e4aab60 9 * @note
mrsoundhar 0:559a8e4aab60 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
mrsoundhar 0:559a8e4aab60 11 *
mrsoundhar 0:559a8e4aab60 12 * @par
mrsoundhar 0:559a8e4aab60 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
mrsoundhar 0:559a8e4aab60 14 * processor based microcontrollers. This file can be freely distributed
mrsoundhar 0:559a8e4aab60 15 * within development tools that are supporting such ARM based processors.
mrsoundhar 0:559a8e4aab60 16 *
mrsoundhar 0:559a8e4aab60 17 * @par
mrsoundhar 0:559a8e4aab60 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mrsoundhar 0:559a8e4aab60 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mrsoundhar 0:559a8e4aab60 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mrsoundhar 0:559a8e4aab60 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mrsoundhar 0:559a8e4aab60 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mrsoundhar 0:559a8e4aab60 23 *
mrsoundhar 0:559a8e4aab60 24 ******************************************************************************/
mrsoundhar 0:559a8e4aab60 25
mrsoundhar 0:559a8e4aab60 26
mrsoundhar 0:559a8e4aab60 27 #ifndef __LPC17xx_H__
mrsoundhar 0:559a8e4aab60 28 #define __LPC17xx_H__
mrsoundhar 0:559a8e4aab60 29
mrsoundhar 0:559a8e4aab60 30 /*
mrsoundhar 0:559a8e4aab60 31 * ==========================================================================
mrsoundhar 0:559a8e4aab60 32 * ---------- Interrupt Number Definition -----------------------------------
mrsoundhar 0:559a8e4aab60 33 * ==========================================================================
mrsoundhar 0:559a8e4aab60 34 */
mrsoundhar 0:559a8e4aab60 35
mrsoundhar 0:559a8e4aab60 36 typedef enum IRQn
mrsoundhar 0:559a8e4aab60 37 {
mrsoundhar 0:559a8e4aab60 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
mrsoundhar 0:559a8e4aab60 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mrsoundhar 0:559a8e4aab60 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
mrsoundhar 0:559a8e4aab60 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
mrsoundhar 0:559a8e4aab60 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
mrsoundhar 0:559a8e4aab60 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
mrsoundhar 0:559a8e4aab60 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
mrsoundhar 0:559a8e4aab60 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
mrsoundhar 0:559a8e4aab60 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
mrsoundhar 0:559a8e4aab60 47
mrsoundhar 0:559a8e4aab60 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
mrsoundhar 0:559a8e4aab60 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
mrsoundhar 0:559a8e4aab60 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
mrsoundhar 0:559a8e4aab60 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
mrsoundhar 0:559a8e4aab60 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
mrsoundhar 0:559a8e4aab60 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
mrsoundhar 0:559a8e4aab60 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
mrsoundhar 0:559a8e4aab60 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
mrsoundhar 0:559a8e4aab60 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
mrsoundhar 0:559a8e4aab60 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
mrsoundhar 0:559a8e4aab60 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
mrsoundhar 0:559a8e4aab60 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
mrsoundhar 0:559a8e4aab60 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
mrsoundhar 0:559a8e4aab60 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
mrsoundhar 0:559a8e4aab60 62 SPI_IRQn = 13, /*!< SPI Interrupt */
mrsoundhar 0:559a8e4aab60 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
mrsoundhar 0:559a8e4aab60 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
mrsoundhar 0:559a8e4aab60 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
mrsoundhar 0:559a8e4aab60 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
mrsoundhar 0:559a8e4aab60 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
mrsoundhar 0:559a8e4aab60 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
mrsoundhar 0:559a8e4aab60 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
mrsoundhar 0:559a8e4aab60 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
mrsoundhar 0:559a8e4aab60 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
mrsoundhar 0:559a8e4aab60 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
mrsoundhar 0:559a8e4aab60 73 USB_IRQn = 24, /*!< USB Interrupt */
mrsoundhar 0:559a8e4aab60 74 CAN_IRQn = 25, /*!< CAN Interrupt */
mrsoundhar 0:559a8e4aab60 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
mrsoundhar 0:559a8e4aab60 76 I2S_IRQn = 27, /*!< I2S Interrupt */
mrsoundhar 0:559a8e4aab60 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
mrsoundhar 0:559a8e4aab60 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
mrsoundhar 0:559a8e4aab60 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
mrsoundhar 0:559a8e4aab60 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
mrsoundhar 0:559a8e4aab60 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
mrsoundhar 0:559a8e4aab60 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
mrsoundhar 0:559a8e4aab60 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
mrsoundhar 0:559a8e4aab60 84 } IRQn_Type;
mrsoundhar 0:559a8e4aab60 85
mrsoundhar 0:559a8e4aab60 86
mrsoundhar 0:559a8e4aab60 87 /*
mrsoundhar 0:559a8e4aab60 88 * ==========================================================================
mrsoundhar 0:559a8e4aab60 89 * ----------- Processor and Core Peripheral Section ------------------------
mrsoundhar 0:559a8e4aab60 90 * ==========================================================================
mrsoundhar 0:559a8e4aab60 91 */
mrsoundhar 0:559a8e4aab60 92
mrsoundhar 0:559a8e4aab60 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
mrsoundhar 0:559a8e4aab60 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
mrsoundhar 0:559a8e4aab60 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
mrsoundhar 0:559a8e4aab60 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mrsoundhar 0:559a8e4aab60 97
mrsoundhar 0:559a8e4aab60 98
mrsoundhar 0:559a8e4aab60 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
mrsoundhar 0:559a8e4aab60 100 #include "system_LPC17xx.h" /* System Header */
mrsoundhar 0:559a8e4aab60 101
mrsoundhar 0:559a8e4aab60 102
mrsoundhar 0:559a8e4aab60 103 /******************************************************************************/
mrsoundhar 0:559a8e4aab60 104 /* Device Specific Peripheral registers structures */
mrsoundhar 0:559a8e4aab60 105 /******************************************************************************/
mrsoundhar 0:559a8e4aab60 106
mrsoundhar 0:559a8e4aab60 107 #if defined ( __CC_ARM )
mrsoundhar 0:559a8e4aab60 108 #pragma anon_unions
mrsoundhar 0:559a8e4aab60 109 #endif
mrsoundhar 0:559a8e4aab60 110
mrsoundhar 0:559a8e4aab60 111 /*------------- System Control (SC) ------------------------------------------*/
mrsoundhar 0:559a8e4aab60 112 typedef struct
mrsoundhar 0:559a8e4aab60 113 {
mrsoundhar 0:559a8e4aab60 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
mrsoundhar 0:559a8e4aab60 115 uint32_t RESERVED0[31];
mrsoundhar 0:559a8e4aab60 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
mrsoundhar 0:559a8e4aab60 117 __IO uint32_t PLL0CFG;
mrsoundhar 0:559a8e4aab60 118 __I uint32_t PLL0STAT;
mrsoundhar 0:559a8e4aab60 119 __O uint32_t PLL0FEED;
mrsoundhar 0:559a8e4aab60 120 uint32_t RESERVED1[4];
mrsoundhar 0:559a8e4aab60 121 __IO uint32_t PLL1CON;
mrsoundhar 0:559a8e4aab60 122 __IO uint32_t PLL1CFG;
mrsoundhar 0:559a8e4aab60 123 __I uint32_t PLL1STAT;
mrsoundhar 0:559a8e4aab60 124 __O uint32_t PLL1FEED;
mrsoundhar 0:559a8e4aab60 125 uint32_t RESERVED2[4];
mrsoundhar 0:559a8e4aab60 126 __IO uint32_t PCON;
mrsoundhar 0:559a8e4aab60 127 __IO uint32_t PCONP;
mrsoundhar 0:559a8e4aab60 128 uint32_t RESERVED3[15];
mrsoundhar 0:559a8e4aab60 129 __IO uint32_t CCLKCFG;
mrsoundhar 0:559a8e4aab60 130 __IO uint32_t USBCLKCFG;
mrsoundhar 0:559a8e4aab60 131 __IO uint32_t CLKSRCSEL;
mrsoundhar 0:559a8e4aab60 132 __IO uint32_t CANSLEEPCLR;
mrsoundhar 0:559a8e4aab60 133 __IO uint32_t CANWAKEFLAGS;
mrsoundhar 0:559a8e4aab60 134 uint32_t RESERVED4[10];
mrsoundhar 0:559a8e4aab60 135 __IO uint32_t EXTINT; /* External Interrupts */
mrsoundhar 0:559a8e4aab60 136 uint32_t RESERVED5;
mrsoundhar 0:559a8e4aab60 137 __IO uint32_t EXTMODE;
mrsoundhar 0:559a8e4aab60 138 __IO uint32_t EXTPOLAR;
mrsoundhar 0:559a8e4aab60 139 uint32_t RESERVED6[12];
mrsoundhar 0:559a8e4aab60 140 __IO uint32_t RSID; /* Reset */
mrsoundhar 0:559a8e4aab60 141 uint32_t RESERVED7[7];
mrsoundhar 0:559a8e4aab60 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
mrsoundhar 0:559a8e4aab60 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
mrsoundhar 0:559a8e4aab60 144 __IO uint32_t PCLKSEL0;
mrsoundhar 0:559a8e4aab60 145 __IO uint32_t PCLKSEL1;
mrsoundhar 0:559a8e4aab60 146 uint32_t RESERVED8[4];
mrsoundhar 0:559a8e4aab60 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
mrsoundhar 0:559a8e4aab60 148 __IO uint32_t DMAREQSEL;
mrsoundhar 0:559a8e4aab60 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
mrsoundhar 0:559a8e4aab60 150 } LPC_SC_TypeDef;
mrsoundhar 0:559a8e4aab60 151
mrsoundhar 0:559a8e4aab60 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
mrsoundhar 0:559a8e4aab60 153 typedef struct
mrsoundhar 0:559a8e4aab60 154 {
mrsoundhar 0:559a8e4aab60 155 __IO uint32_t PINSEL0;
mrsoundhar 0:559a8e4aab60 156 __IO uint32_t PINSEL1;
mrsoundhar 0:559a8e4aab60 157 __IO uint32_t PINSEL2;
mrsoundhar 0:559a8e4aab60 158 __IO uint32_t PINSEL3;
mrsoundhar 0:559a8e4aab60 159 __IO uint32_t PINSEL4;
mrsoundhar 0:559a8e4aab60 160 __IO uint32_t PINSEL5;
mrsoundhar 0:559a8e4aab60 161 __IO uint32_t PINSEL6;
mrsoundhar 0:559a8e4aab60 162 __IO uint32_t PINSEL7;
mrsoundhar 0:559a8e4aab60 163 __IO uint32_t PINSEL8;
mrsoundhar 0:559a8e4aab60 164 __IO uint32_t PINSEL9;
mrsoundhar 0:559a8e4aab60 165 __IO uint32_t PINSEL10;
mrsoundhar 0:559a8e4aab60 166 uint32_t RESERVED0[5];
mrsoundhar 0:559a8e4aab60 167 __IO uint32_t PINMODE0;
mrsoundhar 0:559a8e4aab60 168 __IO uint32_t PINMODE1;
mrsoundhar 0:559a8e4aab60 169 __IO uint32_t PINMODE2;
mrsoundhar 0:559a8e4aab60 170 __IO uint32_t PINMODE3;
mrsoundhar 0:559a8e4aab60 171 __IO uint32_t PINMODE4;
mrsoundhar 0:559a8e4aab60 172 __IO uint32_t PINMODE5;
mrsoundhar 0:559a8e4aab60 173 __IO uint32_t PINMODE6;
mrsoundhar 0:559a8e4aab60 174 __IO uint32_t PINMODE7;
mrsoundhar 0:559a8e4aab60 175 __IO uint32_t PINMODE8;
mrsoundhar 0:559a8e4aab60 176 __IO uint32_t PINMODE9;
mrsoundhar 0:559a8e4aab60 177 __IO uint32_t PINMODE_OD0;
mrsoundhar 0:559a8e4aab60 178 __IO uint32_t PINMODE_OD1;
mrsoundhar 0:559a8e4aab60 179 __IO uint32_t PINMODE_OD2;
mrsoundhar 0:559a8e4aab60 180 __IO uint32_t PINMODE_OD3;
mrsoundhar 0:559a8e4aab60 181 __IO uint32_t PINMODE_OD4;
mrsoundhar 0:559a8e4aab60 182 __IO uint32_t I2CPADCFG;
mrsoundhar 0:559a8e4aab60 183 } LPC_PINCON_TypeDef;
mrsoundhar 0:559a8e4aab60 184
mrsoundhar 0:559a8e4aab60 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
mrsoundhar 0:559a8e4aab60 186 typedef struct
mrsoundhar 0:559a8e4aab60 187 {
mrsoundhar 0:559a8e4aab60 188 union {
mrsoundhar 0:559a8e4aab60 189 __IO uint32_t FIODIR;
mrsoundhar 0:559a8e4aab60 190 struct {
mrsoundhar 0:559a8e4aab60 191 __IO uint16_t FIODIRL;
mrsoundhar 0:559a8e4aab60 192 __IO uint16_t FIODIRH;
mrsoundhar 0:559a8e4aab60 193 };
mrsoundhar 0:559a8e4aab60 194 struct {
mrsoundhar 0:559a8e4aab60 195 __IO uint8_t FIODIR0;
mrsoundhar 0:559a8e4aab60 196 __IO uint8_t FIODIR1;
mrsoundhar 0:559a8e4aab60 197 __IO uint8_t FIODIR2;
mrsoundhar 0:559a8e4aab60 198 __IO uint8_t FIODIR3;
mrsoundhar 0:559a8e4aab60 199 };
mrsoundhar 0:559a8e4aab60 200 };
mrsoundhar 0:559a8e4aab60 201 uint32_t RESERVED0[3];
mrsoundhar 0:559a8e4aab60 202 union {
mrsoundhar 0:559a8e4aab60 203 __IO uint32_t FIOMASK;
mrsoundhar 0:559a8e4aab60 204 struct {
mrsoundhar 0:559a8e4aab60 205 __IO uint16_t FIOMASKL;
mrsoundhar 0:559a8e4aab60 206 __IO uint16_t FIOMASKH;
mrsoundhar 0:559a8e4aab60 207 };
mrsoundhar 0:559a8e4aab60 208 struct {
mrsoundhar 0:559a8e4aab60 209 __IO uint8_t FIOMASK0;
mrsoundhar 0:559a8e4aab60 210 __IO uint8_t FIOMASK1;
mrsoundhar 0:559a8e4aab60 211 __IO uint8_t FIOMASK2;
mrsoundhar 0:559a8e4aab60 212 __IO uint8_t FIOMASK3;
mrsoundhar 0:559a8e4aab60 213 };
mrsoundhar 0:559a8e4aab60 214 };
mrsoundhar 0:559a8e4aab60 215 union {
mrsoundhar 0:559a8e4aab60 216 __IO uint32_t FIOPIN;
mrsoundhar 0:559a8e4aab60 217 struct {
mrsoundhar 0:559a8e4aab60 218 __IO uint16_t FIOPINL;
mrsoundhar 0:559a8e4aab60 219 __IO uint16_t FIOPINH;
mrsoundhar 0:559a8e4aab60 220 };
mrsoundhar 0:559a8e4aab60 221 struct {
mrsoundhar 0:559a8e4aab60 222 __IO uint8_t FIOPIN0;
mrsoundhar 0:559a8e4aab60 223 __IO uint8_t FIOPIN1;
mrsoundhar 0:559a8e4aab60 224 __IO uint8_t FIOPIN2;
mrsoundhar 0:559a8e4aab60 225 __IO uint8_t FIOPIN3;
mrsoundhar 0:559a8e4aab60 226 };
mrsoundhar 0:559a8e4aab60 227 };
mrsoundhar 0:559a8e4aab60 228 union {
mrsoundhar 0:559a8e4aab60 229 __IO uint32_t FIOSET;
mrsoundhar 0:559a8e4aab60 230 struct {
mrsoundhar 0:559a8e4aab60 231 __IO uint16_t FIOSETL;
mrsoundhar 0:559a8e4aab60 232 __IO uint16_t FIOSETH;
mrsoundhar 0:559a8e4aab60 233 };
mrsoundhar 0:559a8e4aab60 234 struct {
mrsoundhar 0:559a8e4aab60 235 __IO uint8_t FIOSET0;
mrsoundhar 0:559a8e4aab60 236 __IO uint8_t FIOSET1;
mrsoundhar 0:559a8e4aab60 237 __IO uint8_t FIOSET2;
mrsoundhar 0:559a8e4aab60 238 __IO uint8_t FIOSET3;
mrsoundhar 0:559a8e4aab60 239 };
mrsoundhar 0:559a8e4aab60 240 };
mrsoundhar 0:559a8e4aab60 241 union {
mrsoundhar 0:559a8e4aab60 242 __O uint32_t FIOCLR;
mrsoundhar 0:559a8e4aab60 243 struct {
mrsoundhar 0:559a8e4aab60 244 __O uint16_t FIOCLRL;
mrsoundhar 0:559a8e4aab60 245 __O uint16_t FIOCLRH;
mrsoundhar 0:559a8e4aab60 246 };
mrsoundhar 0:559a8e4aab60 247 struct {
mrsoundhar 0:559a8e4aab60 248 __O uint8_t FIOCLR0;
mrsoundhar 0:559a8e4aab60 249 __O uint8_t FIOCLR1;
mrsoundhar 0:559a8e4aab60 250 __O uint8_t FIOCLR2;
mrsoundhar 0:559a8e4aab60 251 __O uint8_t FIOCLR3;
mrsoundhar 0:559a8e4aab60 252 };
mrsoundhar 0:559a8e4aab60 253 };
mrsoundhar 0:559a8e4aab60 254 } LPC_GPIO_TypeDef;
mrsoundhar 0:559a8e4aab60 255
mrsoundhar 0:559a8e4aab60 256 typedef struct
mrsoundhar 0:559a8e4aab60 257 {
mrsoundhar 0:559a8e4aab60 258 __I uint32_t IntStatus;
mrsoundhar 0:559a8e4aab60 259 __I uint32_t IO0IntStatR;
mrsoundhar 0:559a8e4aab60 260 __I uint32_t IO0IntStatF;
mrsoundhar 0:559a8e4aab60 261 __O uint32_t IO0IntClr;
mrsoundhar 0:559a8e4aab60 262 __IO uint32_t IO0IntEnR;
mrsoundhar 0:559a8e4aab60 263 __IO uint32_t IO0IntEnF;
mrsoundhar 0:559a8e4aab60 264 uint32_t RESERVED0[3];
mrsoundhar 0:559a8e4aab60 265 __I uint32_t IO2IntStatR;
mrsoundhar 0:559a8e4aab60 266 __I uint32_t IO2IntStatF;
mrsoundhar 0:559a8e4aab60 267 __O uint32_t IO2IntClr;
mrsoundhar 0:559a8e4aab60 268 __IO uint32_t IO2IntEnR;
mrsoundhar 0:559a8e4aab60 269 __IO uint32_t IO2IntEnF;
mrsoundhar 0:559a8e4aab60 270 } LPC_GPIOINT_TypeDef;
mrsoundhar 0:559a8e4aab60 271
mrsoundhar 0:559a8e4aab60 272 /*------------- Timer (TIM) --------------------------------------------------*/
mrsoundhar 0:559a8e4aab60 273 typedef struct
mrsoundhar 0:559a8e4aab60 274 {
mrsoundhar 0:559a8e4aab60 275 __IO uint32_t IR;
mrsoundhar 0:559a8e4aab60 276 __IO uint32_t TCR;
mrsoundhar 0:559a8e4aab60 277 __IO uint32_t TC;
mrsoundhar 0:559a8e4aab60 278 __IO uint32_t PR;
mrsoundhar 0:559a8e4aab60 279 __IO uint32_t PC;
mrsoundhar 0:559a8e4aab60 280 __IO uint32_t MCR;
mrsoundhar 0:559a8e4aab60 281 __IO uint32_t MR0;
mrsoundhar 0:559a8e4aab60 282 __IO uint32_t MR1;
mrsoundhar 0:559a8e4aab60 283 __IO uint32_t MR2;
mrsoundhar 0:559a8e4aab60 284 __IO uint32_t MR3;
mrsoundhar 0:559a8e4aab60 285 __IO uint32_t CCR;
mrsoundhar 0:559a8e4aab60 286 __I uint32_t CR0;
mrsoundhar 0:559a8e4aab60 287 __I uint32_t CR1;
mrsoundhar 0:559a8e4aab60 288 uint32_t RESERVED0[2];
mrsoundhar 0:559a8e4aab60 289 __IO uint32_t EMR;
mrsoundhar 0:559a8e4aab60 290 uint32_t RESERVED1[12];
mrsoundhar 0:559a8e4aab60 291 __IO uint32_t CTCR;
mrsoundhar 0:559a8e4aab60 292 } LPC_TIM_TypeDef;
mrsoundhar 0:559a8e4aab60 293
mrsoundhar 0:559a8e4aab60 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
mrsoundhar 0:559a8e4aab60 295 typedef struct
mrsoundhar 0:559a8e4aab60 296 {
mrsoundhar 0:559a8e4aab60 297 __IO uint32_t IR;
mrsoundhar 0:559a8e4aab60 298 __IO uint32_t TCR;
mrsoundhar 0:559a8e4aab60 299 __IO uint32_t TC;
mrsoundhar 0:559a8e4aab60 300 __IO uint32_t PR;
mrsoundhar 0:559a8e4aab60 301 __IO uint32_t PC;
mrsoundhar 0:559a8e4aab60 302 __IO uint32_t MCR;
mrsoundhar 0:559a8e4aab60 303 __IO uint32_t MR0;
mrsoundhar 0:559a8e4aab60 304 __IO uint32_t MR1;
mrsoundhar 0:559a8e4aab60 305 __IO uint32_t MR2;
mrsoundhar 0:559a8e4aab60 306 __IO uint32_t MR3;
mrsoundhar 0:559a8e4aab60 307 __IO uint32_t CCR;
mrsoundhar 0:559a8e4aab60 308 __I uint32_t CR0;
mrsoundhar 0:559a8e4aab60 309 __I uint32_t CR1;
mrsoundhar 0:559a8e4aab60 310 __I uint32_t CR2;
mrsoundhar 0:559a8e4aab60 311 __I uint32_t CR3;
mrsoundhar 0:559a8e4aab60 312 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 313 __IO uint32_t MR4;
mrsoundhar 0:559a8e4aab60 314 __IO uint32_t MR5;
mrsoundhar 0:559a8e4aab60 315 __IO uint32_t MR6;
mrsoundhar 0:559a8e4aab60 316 __IO uint32_t PCR;
mrsoundhar 0:559a8e4aab60 317 __IO uint32_t LER;
mrsoundhar 0:559a8e4aab60 318 uint32_t RESERVED1[7];
mrsoundhar 0:559a8e4aab60 319 __IO uint32_t CTCR;
mrsoundhar 0:559a8e4aab60 320 } LPC_PWM_TypeDef;
mrsoundhar 0:559a8e4aab60 321
mrsoundhar 0:559a8e4aab60 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
mrsoundhar 0:559a8e4aab60 323 typedef struct
mrsoundhar 0:559a8e4aab60 324 {
mrsoundhar 0:559a8e4aab60 325 union {
mrsoundhar 0:559a8e4aab60 326 __I uint8_t RBR;
mrsoundhar 0:559a8e4aab60 327 __O uint8_t THR;
mrsoundhar 0:559a8e4aab60 328 __IO uint8_t DLL;
mrsoundhar 0:559a8e4aab60 329 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 330 };
mrsoundhar 0:559a8e4aab60 331 union {
mrsoundhar 0:559a8e4aab60 332 __IO uint8_t DLM;
mrsoundhar 0:559a8e4aab60 333 __IO uint32_t IER;
mrsoundhar 0:559a8e4aab60 334 };
mrsoundhar 0:559a8e4aab60 335 union {
mrsoundhar 0:559a8e4aab60 336 __I uint32_t IIR;
mrsoundhar 0:559a8e4aab60 337 __O uint8_t FCR;
mrsoundhar 0:559a8e4aab60 338 };
mrsoundhar 0:559a8e4aab60 339 __IO uint8_t LCR;
mrsoundhar 0:559a8e4aab60 340 uint8_t RESERVED1[7];
mrsoundhar 0:559a8e4aab60 341 __I uint8_t LSR;
mrsoundhar 0:559a8e4aab60 342 uint8_t RESERVED2[7];
mrsoundhar 0:559a8e4aab60 343 __IO uint8_t SCR;
mrsoundhar 0:559a8e4aab60 344 uint8_t RESERVED3[3];
mrsoundhar 0:559a8e4aab60 345 __IO uint32_t ACR;
mrsoundhar 0:559a8e4aab60 346 __IO uint8_t ICR;
mrsoundhar 0:559a8e4aab60 347 uint8_t RESERVED4[3];
mrsoundhar 0:559a8e4aab60 348 __IO uint8_t FDR;
mrsoundhar 0:559a8e4aab60 349 uint8_t RESERVED5[7];
mrsoundhar 0:559a8e4aab60 350 __IO uint8_t TER;
mrsoundhar 0:559a8e4aab60 351 uint8_t RESERVED6[39];
mrsoundhar 0:559a8e4aab60 352 __IO uint32_t FIFOLVL;
mrsoundhar 0:559a8e4aab60 353 } LPC_UART_TypeDef;
mrsoundhar 0:559a8e4aab60 354
mrsoundhar 0:559a8e4aab60 355 typedef struct
mrsoundhar 0:559a8e4aab60 356 {
mrsoundhar 0:559a8e4aab60 357 union {
mrsoundhar 0:559a8e4aab60 358 __I uint8_t RBR;
mrsoundhar 0:559a8e4aab60 359 __O uint8_t THR;
mrsoundhar 0:559a8e4aab60 360 __IO uint8_t DLL;
mrsoundhar 0:559a8e4aab60 361 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 362 };
mrsoundhar 0:559a8e4aab60 363 union {
mrsoundhar 0:559a8e4aab60 364 __IO uint8_t DLM;
mrsoundhar 0:559a8e4aab60 365 __IO uint32_t IER;
mrsoundhar 0:559a8e4aab60 366 };
mrsoundhar 0:559a8e4aab60 367 union {
mrsoundhar 0:559a8e4aab60 368 __I uint32_t IIR;
mrsoundhar 0:559a8e4aab60 369 __O uint8_t FCR;
mrsoundhar 0:559a8e4aab60 370 };
mrsoundhar 0:559a8e4aab60 371 __IO uint8_t LCR;
mrsoundhar 0:559a8e4aab60 372 uint8_t RESERVED1[7];
mrsoundhar 0:559a8e4aab60 373 __I uint8_t LSR;
mrsoundhar 0:559a8e4aab60 374 uint8_t RESERVED2[7];
mrsoundhar 0:559a8e4aab60 375 __IO uint8_t SCR;
mrsoundhar 0:559a8e4aab60 376 uint8_t RESERVED3[3];
mrsoundhar 0:559a8e4aab60 377 __IO uint32_t ACR;
mrsoundhar 0:559a8e4aab60 378 __IO uint8_t ICR;
mrsoundhar 0:559a8e4aab60 379 uint8_t RESERVED4[3];
mrsoundhar 0:559a8e4aab60 380 __IO uint8_t FDR;
mrsoundhar 0:559a8e4aab60 381 uint8_t RESERVED5[7];
mrsoundhar 0:559a8e4aab60 382 __IO uint8_t TER;
mrsoundhar 0:559a8e4aab60 383 uint8_t RESERVED6[39];
mrsoundhar 0:559a8e4aab60 384 __IO uint32_t FIFOLVL;
mrsoundhar 0:559a8e4aab60 385 } LPC_UART0_TypeDef;
mrsoundhar 0:559a8e4aab60 386
mrsoundhar 0:559a8e4aab60 387 typedef struct
mrsoundhar 0:559a8e4aab60 388 {
mrsoundhar 0:559a8e4aab60 389 union {
mrsoundhar 0:559a8e4aab60 390 __I uint8_t RBR;
mrsoundhar 0:559a8e4aab60 391 __O uint8_t THR;
mrsoundhar 0:559a8e4aab60 392 __IO uint8_t DLL;
mrsoundhar 0:559a8e4aab60 393 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 394 };
mrsoundhar 0:559a8e4aab60 395 union {
mrsoundhar 0:559a8e4aab60 396 __IO uint8_t DLM;
mrsoundhar 0:559a8e4aab60 397 __IO uint32_t IER;
mrsoundhar 0:559a8e4aab60 398 };
mrsoundhar 0:559a8e4aab60 399 union {
mrsoundhar 0:559a8e4aab60 400 __I uint32_t IIR;
mrsoundhar 0:559a8e4aab60 401 __O uint8_t FCR;
mrsoundhar 0:559a8e4aab60 402 };
mrsoundhar 0:559a8e4aab60 403 __IO uint8_t LCR;
mrsoundhar 0:559a8e4aab60 404 uint8_t RESERVED1[3];
mrsoundhar 0:559a8e4aab60 405 __IO uint8_t MCR;
mrsoundhar 0:559a8e4aab60 406 uint8_t RESERVED2[3];
mrsoundhar 0:559a8e4aab60 407 __I uint8_t LSR;
mrsoundhar 0:559a8e4aab60 408 uint8_t RESERVED3[3];
mrsoundhar 0:559a8e4aab60 409 __I uint8_t MSR;
mrsoundhar 0:559a8e4aab60 410 uint8_t RESERVED4[3];
mrsoundhar 0:559a8e4aab60 411 __IO uint8_t SCR;
mrsoundhar 0:559a8e4aab60 412 uint8_t RESERVED5[3];
mrsoundhar 0:559a8e4aab60 413 __IO uint32_t ACR;
mrsoundhar 0:559a8e4aab60 414 uint32_t RESERVED6;
mrsoundhar 0:559a8e4aab60 415 __IO uint32_t FDR;
mrsoundhar 0:559a8e4aab60 416 uint32_t RESERVED7;
mrsoundhar 0:559a8e4aab60 417 __IO uint8_t TER;
mrsoundhar 0:559a8e4aab60 418 uint8_t RESERVED8[27];
mrsoundhar 0:559a8e4aab60 419 __IO uint8_t RS485CTRL;
mrsoundhar 0:559a8e4aab60 420 uint8_t RESERVED9[3];
mrsoundhar 0:559a8e4aab60 421 __IO uint8_t ADRMATCH;
mrsoundhar 0:559a8e4aab60 422 uint8_t RESERVED10[3];
mrsoundhar 0:559a8e4aab60 423 __IO uint8_t RS485DLY;
mrsoundhar 0:559a8e4aab60 424 uint8_t RESERVED11[3];
mrsoundhar 0:559a8e4aab60 425 __IO uint32_t FIFOLVL;
mrsoundhar 0:559a8e4aab60 426 } LPC_UART1_TypeDef;
mrsoundhar 0:559a8e4aab60 427
mrsoundhar 0:559a8e4aab60 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
mrsoundhar 0:559a8e4aab60 429 typedef struct
mrsoundhar 0:559a8e4aab60 430 {
mrsoundhar 0:559a8e4aab60 431 __IO uint32_t SPCR;
mrsoundhar 0:559a8e4aab60 432 __I uint32_t SPSR;
mrsoundhar 0:559a8e4aab60 433 __IO uint32_t SPDR;
mrsoundhar 0:559a8e4aab60 434 __IO uint32_t SPCCR;
mrsoundhar 0:559a8e4aab60 435 uint32_t RESERVED0[3];
mrsoundhar 0:559a8e4aab60 436 __IO uint32_t SPINT;
mrsoundhar 0:559a8e4aab60 437 } LPC_SPI_TypeDef;
mrsoundhar 0:559a8e4aab60 438
mrsoundhar 0:559a8e4aab60 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
mrsoundhar 0:559a8e4aab60 440 typedef struct
mrsoundhar 0:559a8e4aab60 441 {
mrsoundhar 0:559a8e4aab60 442 __IO uint32_t CR0;
mrsoundhar 0:559a8e4aab60 443 __IO uint32_t CR1;
mrsoundhar 0:559a8e4aab60 444 __IO uint32_t DR;
mrsoundhar 0:559a8e4aab60 445 __I uint32_t SR;
mrsoundhar 0:559a8e4aab60 446 __IO uint32_t CPSR;
mrsoundhar 0:559a8e4aab60 447 __IO uint32_t IMSC;
mrsoundhar 0:559a8e4aab60 448 __IO uint32_t RIS;
mrsoundhar 0:559a8e4aab60 449 __IO uint32_t MIS;
mrsoundhar 0:559a8e4aab60 450 __IO uint32_t ICR;
mrsoundhar 0:559a8e4aab60 451 __IO uint32_t DMACR;
mrsoundhar 0:559a8e4aab60 452 } LPC_SSP_TypeDef;
mrsoundhar 0:559a8e4aab60 453
mrsoundhar 0:559a8e4aab60 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
mrsoundhar 0:559a8e4aab60 455 typedef struct
mrsoundhar 0:559a8e4aab60 456 {
mrsoundhar 0:559a8e4aab60 457 __IO uint32_t I2CONSET;
mrsoundhar 0:559a8e4aab60 458 __I uint32_t I2STAT;
mrsoundhar 0:559a8e4aab60 459 __IO uint32_t I2DAT;
mrsoundhar 0:559a8e4aab60 460 __IO uint32_t I2ADR0;
mrsoundhar 0:559a8e4aab60 461 __IO uint32_t I2SCLH;
mrsoundhar 0:559a8e4aab60 462 __IO uint32_t I2SCLL;
mrsoundhar 0:559a8e4aab60 463 __O uint32_t I2CONCLR;
mrsoundhar 0:559a8e4aab60 464 __IO uint32_t MMCTRL;
mrsoundhar 0:559a8e4aab60 465 __IO uint32_t I2ADR1;
mrsoundhar 0:559a8e4aab60 466 __IO uint32_t I2ADR2;
mrsoundhar 0:559a8e4aab60 467 __IO uint32_t I2ADR3;
mrsoundhar 0:559a8e4aab60 468 __I uint32_t I2DATA_BUFFER;
mrsoundhar 0:559a8e4aab60 469 __IO uint32_t I2MASK0;
mrsoundhar 0:559a8e4aab60 470 __IO uint32_t I2MASK1;
mrsoundhar 0:559a8e4aab60 471 __IO uint32_t I2MASK2;
mrsoundhar 0:559a8e4aab60 472 __IO uint32_t I2MASK3;
mrsoundhar 0:559a8e4aab60 473 } LPC_I2C_TypeDef;
mrsoundhar 0:559a8e4aab60 474
mrsoundhar 0:559a8e4aab60 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
mrsoundhar 0:559a8e4aab60 476 typedef struct
mrsoundhar 0:559a8e4aab60 477 {
mrsoundhar 0:559a8e4aab60 478 __IO uint32_t I2SDAO;
mrsoundhar 0:559a8e4aab60 479 __IO uint32_t I2SDAI;
mrsoundhar 0:559a8e4aab60 480 __O uint32_t I2STXFIFO;
mrsoundhar 0:559a8e4aab60 481 __I uint32_t I2SRXFIFO;
mrsoundhar 0:559a8e4aab60 482 __I uint32_t I2SSTATE;
mrsoundhar 0:559a8e4aab60 483 __IO uint32_t I2SDMA1;
mrsoundhar 0:559a8e4aab60 484 __IO uint32_t I2SDMA2;
mrsoundhar 0:559a8e4aab60 485 __IO uint32_t I2SIRQ;
mrsoundhar 0:559a8e4aab60 486 __IO uint32_t I2STXRATE;
mrsoundhar 0:559a8e4aab60 487 __IO uint32_t I2SRXRATE;
mrsoundhar 0:559a8e4aab60 488 __IO uint32_t I2STXBITRATE;
mrsoundhar 0:559a8e4aab60 489 __IO uint32_t I2SRXBITRATE;
mrsoundhar 0:559a8e4aab60 490 __IO uint32_t I2STXMODE;
mrsoundhar 0:559a8e4aab60 491 __IO uint32_t I2SRXMODE;
mrsoundhar 0:559a8e4aab60 492 } LPC_I2S_TypeDef;
mrsoundhar 0:559a8e4aab60 493
mrsoundhar 0:559a8e4aab60 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
mrsoundhar 0:559a8e4aab60 495 typedef struct
mrsoundhar 0:559a8e4aab60 496 {
mrsoundhar 0:559a8e4aab60 497 __IO uint32_t RICOMPVAL;
mrsoundhar 0:559a8e4aab60 498 __IO uint32_t RIMASK;
mrsoundhar 0:559a8e4aab60 499 __IO uint8_t RICTRL;
mrsoundhar 0:559a8e4aab60 500 uint8_t RESERVED0[3];
mrsoundhar 0:559a8e4aab60 501 __IO uint32_t RICOUNTER;
mrsoundhar 0:559a8e4aab60 502 } LPC_RIT_TypeDef;
mrsoundhar 0:559a8e4aab60 503
mrsoundhar 0:559a8e4aab60 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
mrsoundhar 0:559a8e4aab60 505 typedef struct
mrsoundhar 0:559a8e4aab60 506 {
mrsoundhar 0:559a8e4aab60 507 __IO uint8_t ILR;
mrsoundhar 0:559a8e4aab60 508 uint8_t RESERVED0[7];
mrsoundhar 0:559a8e4aab60 509 __IO uint8_t CCR;
mrsoundhar 0:559a8e4aab60 510 uint8_t RESERVED1[3];
mrsoundhar 0:559a8e4aab60 511 __IO uint8_t CIIR;
mrsoundhar 0:559a8e4aab60 512 uint8_t RESERVED2[3];
mrsoundhar 0:559a8e4aab60 513 __IO uint8_t AMR;
mrsoundhar 0:559a8e4aab60 514 uint8_t RESERVED3[3];
mrsoundhar 0:559a8e4aab60 515 __I uint32_t CTIME0;
mrsoundhar 0:559a8e4aab60 516 __I uint32_t CTIME1;
mrsoundhar 0:559a8e4aab60 517 __I uint32_t CTIME2;
mrsoundhar 0:559a8e4aab60 518 __IO uint8_t SEC;
mrsoundhar 0:559a8e4aab60 519 uint8_t RESERVED4[3];
mrsoundhar 0:559a8e4aab60 520 __IO uint8_t MIN;
mrsoundhar 0:559a8e4aab60 521 uint8_t RESERVED5[3];
mrsoundhar 0:559a8e4aab60 522 __IO uint8_t HOUR;
mrsoundhar 0:559a8e4aab60 523 uint8_t RESERVED6[3];
mrsoundhar 0:559a8e4aab60 524 __IO uint8_t DOM;
mrsoundhar 0:559a8e4aab60 525 uint8_t RESERVED7[3];
mrsoundhar 0:559a8e4aab60 526 __IO uint8_t DOW;
mrsoundhar 0:559a8e4aab60 527 uint8_t RESERVED8[3];
mrsoundhar 0:559a8e4aab60 528 __IO uint16_t DOY;
mrsoundhar 0:559a8e4aab60 529 uint16_t RESERVED9;
mrsoundhar 0:559a8e4aab60 530 __IO uint8_t MONTH;
mrsoundhar 0:559a8e4aab60 531 uint8_t RESERVED10[3];
mrsoundhar 0:559a8e4aab60 532 __IO uint16_t YEAR;
mrsoundhar 0:559a8e4aab60 533 uint16_t RESERVED11;
mrsoundhar 0:559a8e4aab60 534 __IO uint32_t CALIBRATION;
mrsoundhar 0:559a8e4aab60 535 __IO uint32_t GPREG0;
mrsoundhar 0:559a8e4aab60 536 __IO uint32_t GPREG1;
mrsoundhar 0:559a8e4aab60 537 __IO uint32_t GPREG2;
mrsoundhar 0:559a8e4aab60 538 __IO uint32_t GPREG3;
mrsoundhar 0:559a8e4aab60 539 __IO uint32_t GPREG4;
mrsoundhar 0:559a8e4aab60 540 __IO uint8_t RTC_AUXEN;
mrsoundhar 0:559a8e4aab60 541 uint8_t RESERVED12[3];
mrsoundhar 0:559a8e4aab60 542 __IO uint8_t RTC_AUX;
mrsoundhar 0:559a8e4aab60 543 uint8_t RESERVED13[3];
mrsoundhar 0:559a8e4aab60 544 __IO uint8_t ALSEC;
mrsoundhar 0:559a8e4aab60 545 uint8_t RESERVED14[3];
mrsoundhar 0:559a8e4aab60 546 __IO uint8_t ALMIN;
mrsoundhar 0:559a8e4aab60 547 uint8_t RESERVED15[3];
mrsoundhar 0:559a8e4aab60 548 __IO uint8_t ALHOUR;
mrsoundhar 0:559a8e4aab60 549 uint8_t RESERVED16[3];
mrsoundhar 0:559a8e4aab60 550 __IO uint8_t ALDOM;
mrsoundhar 0:559a8e4aab60 551 uint8_t RESERVED17[3];
mrsoundhar 0:559a8e4aab60 552 __IO uint8_t ALDOW;
mrsoundhar 0:559a8e4aab60 553 uint8_t RESERVED18[3];
mrsoundhar 0:559a8e4aab60 554 __IO uint16_t ALDOY;
mrsoundhar 0:559a8e4aab60 555 uint16_t RESERVED19;
mrsoundhar 0:559a8e4aab60 556 __IO uint8_t ALMON;
mrsoundhar 0:559a8e4aab60 557 uint8_t RESERVED20[3];
mrsoundhar 0:559a8e4aab60 558 __IO uint16_t ALYEAR;
mrsoundhar 0:559a8e4aab60 559 uint16_t RESERVED21;
mrsoundhar 0:559a8e4aab60 560 } LPC_RTC_TypeDef;
mrsoundhar 0:559a8e4aab60 561
mrsoundhar 0:559a8e4aab60 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
mrsoundhar 0:559a8e4aab60 563 typedef struct
mrsoundhar 0:559a8e4aab60 564 {
mrsoundhar 0:559a8e4aab60 565 __IO uint8_t WDMOD;
mrsoundhar 0:559a8e4aab60 566 uint8_t RESERVED0[3];
mrsoundhar 0:559a8e4aab60 567 __IO uint32_t WDTC;
mrsoundhar 0:559a8e4aab60 568 __O uint8_t WDFEED;
mrsoundhar 0:559a8e4aab60 569 uint8_t RESERVED1[3];
mrsoundhar 0:559a8e4aab60 570 __I uint32_t WDTV;
mrsoundhar 0:559a8e4aab60 571 __IO uint32_t WDCLKSEL;
mrsoundhar 0:559a8e4aab60 572 } LPC_WDT_TypeDef;
mrsoundhar 0:559a8e4aab60 573
mrsoundhar 0:559a8e4aab60 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
mrsoundhar 0:559a8e4aab60 575 typedef struct
mrsoundhar 0:559a8e4aab60 576 {
mrsoundhar 0:559a8e4aab60 577 __IO uint32_t ADCR;
mrsoundhar 0:559a8e4aab60 578 __IO uint32_t ADGDR;
mrsoundhar 0:559a8e4aab60 579 uint32_t RESERVED0;
mrsoundhar 0:559a8e4aab60 580 __IO uint32_t ADINTEN;
mrsoundhar 0:559a8e4aab60 581 __I uint32_t ADDR0;
mrsoundhar 0:559a8e4aab60 582 __I uint32_t ADDR1;
mrsoundhar 0:559a8e4aab60 583 __I uint32_t ADDR2;
mrsoundhar 0:559a8e4aab60 584 __I uint32_t ADDR3;
mrsoundhar 0:559a8e4aab60 585 __I uint32_t ADDR4;
mrsoundhar 0:559a8e4aab60 586 __I uint32_t ADDR5;
mrsoundhar 0:559a8e4aab60 587 __I uint32_t ADDR6;
mrsoundhar 0:559a8e4aab60 588 __I uint32_t ADDR7;
mrsoundhar 0:559a8e4aab60 589 __I uint32_t ADSTAT;
mrsoundhar 0:559a8e4aab60 590 __IO uint32_t ADTRM;
mrsoundhar 0:559a8e4aab60 591 } LPC_ADC_TypeDef;
mrsoundhar 0:559a8e4aab60 592
mrsoundhar 0:559a8e4aab60 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
mrsoundhar 0:559a8e4aab60 594 typedef struct
mrsoundhar 0:559a8e4aab60 595 {
mrsoundhar 0:559a8e4aab60 596 __IO uint32_t DACR;
mrsoundhar 0:559a8e4aab60 597 __IO uint32_t DACCTRL;
mrsoundhar 0:559a8e4aab60 598 __IO uint16_t DACCNTVAL;
mrsoundhar 0:559a8e4aab60 599 } LPC_DAC_TypeDef;
mrsoundhar 0:559a8e4aab60 600
mrsoundhar 0:559a8e4aab60 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
mrsoundhar 0:559a8e4aab60 602 typedef struct
mrsoundhar 0:559a8e4aab60 603 {
mrsoundhar 0:559a8e4aab60 604 __I uint32_t MCCON;
mrsoundhar 0:559a8e4aab60 605 __O uint32_t MCCON_SET;
mrsoundhar 0:559a8e4aab60 606 __O uint32_t MCCON_CLR;
mrsoundhar 0:559a8e4aab60 607 __I uint32_t MCCAPCON;
mrsoundhar 0:559a8e4aab60 608 __O uint32_t MCCAPCON_SET;
mrsoundhar 0:559a8e4aab60 609 __O uint32_t MCCAPCON_CLR;
mrsoundhar 0:559a8e4aab60 610 __IO uint32_t MCTIM0;
mrsoundhar 0:559a8e4aab60 611 __IO uint32_t MCTIM1;
mrsoundhar 0:559a8e4aab60 612 __IO uint32_t MCTIM2;
mrsoundhar 0:559a8e4aab60 613 __IO uint32_t MCPER0;
mrsoundhar 0:559a8e4aab60 614 __IO uint32_t MCPER1;
mrsoundhar 0:559a8e4aab60 615 __IO uint32_t MCPER2;
mrsoundhar 0:559a8e4aab60 616 __IO uint32_t MCPW0;
mrsoundhar 0:559a8e4aab60 617 __IO uint32_t MCPW1;
mrsoundhar 0:559a8e4aab60 618 __IO uint32_t MCPW2;
mrsoundhar 0:559a8e4aab60 619 __IO uint32_t MCDEADTIME;
mrsoundhar 0:559a8e4aab60 620 __IO uint32_t MCCCP;
mrsoundhar 0:559a8e4aab60 621 __IO uint32_t MCCR0;
mrsoundhar 0:559a8e4aab60 622 __IO uint32_t MCCR1;
mrsoundhar 0:559a8e4aab60 623 __IO uint32_t MCCR2;
mrsoundhar 0:559a8e4aab60 624 __I uint32_t MCINTEN;
mrsoundhar 0:559a8e4aab60 625 __O uint32_t MCINTEN_SET;
mrsoundhar 0:559a8e4aab60 626 __O uint32_t MCINTEN_CLR;
mrsoundhar 0:559a8e4aab60 627 __I uint32_t MCCNTCON;
mrsoundhar 0:559a8e4aab60 628 __O uint32_t MCCNTCON_SET;
mrsoundhar 0:559a8e4aab60 629 __O uint32_t MCCNTCON_CLR;
mrsoundhar 0:559a8e4aab60 630 __I uint32_t MCINTFLAG;
mrsoundhar 0:559a8e4aab60 631 __O uint32_t MCINTFLAG_SET;
mrsoundhar 0:559a8e4aab60 632 __O uint32_t MCINTFLAG_CLR;
mrsoundhar 0:559a8e4aab60 633 __O uint32_t MCCAP_CLR;
mrsoundhar 0:559a8e4aab60 634 } LPC_MCPWM_TypeDef;
mrsoundhar 0:559a8e4aab60 635
mrsoundhar 0:559a8e4aab60 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
mrsoundhar 0:559a8e4aab60 637 typedef struct
mrsoundhar 0:559a8e4aab60 638 {
mrsoundhar 0:559a8e4aab60 639 __O uint32_t QEICON;
mrsoundhar 0:559a8e4aab60 640 __I uint32_t QEISTAT;
mrsoundhar 0:559a8e4aab60 641 __IO uint32_t QEICONF;
mrsoundhar 0:559a8e4aab60 642 __I uint32_t QEIPOS;
mrsoundhar 0:559a8e4aab60 643 __IO uint32_t QEIMAXPOS;
mrsoundhar 0:559a8e4aab60 644 __IO uint32_t CMPOS0;
mrsoundhar 0:559a8e4aab60 645 __IO uint32_t CMPOS1;
mrsoundhar 0:559a8e4aab60 646 __IO uint32_t CMPOS2;
mrsoundhar 0:559a8e4aab60 647 __I uint32_t INXCNT;
mrsoundhar 0:559a8e4aab60 648 __IO uint32_t INXCMP;
mrsoundhar 0:559a8e4aab60 649 __IO uint32_t QEILOAD;
mrsoundhar 0:559a8e4aab60 650 __I uint32_t QEITIME;
mrsoundhar 0:559a8e4aab60 651 __I uint32_t QEIVEL;
mrsoundhar 0:559a8e4aab60 652 __I uint32_t QEICAP;
mrsoundhar 0:559a8e4aab60 653 __IO uint32_t VELCOMP;
mrsoundhar 0:559a8e4aab60 654 __IO uint32_t FILTER;
mrsoundhar 0:559a8e4aab60 655 uint32_t RESERVED0[998];
mrsoundhar 0:559a8e4aab60 656 __O uint32_t QEIIEC;
mrsoundhar 0:559a8e4aab60 657 __O uint32_t QEIIES;
mrsoundhar 0:559a8e4aab60 658 __I uint32_t QEIINTSTAT;
mrsoundhar 0:559a8e4aab60 659 __I uint32_t QEIIE;
mrsoundhar 0:559a8e4aab60 660 __O uint32_t QEICLR;
mrsoundhar 0:559a8e4aab60 661 __O uint32_t QEISET;
mrsoundhar 0:559a8e4aab60 662 } LPC_QEI_TypeDef;
mrsoundhar 0:559a8e4aab60 663
mrsoundhar 0:559a8e4aab60 664 /*------------- Controller Area Network (CAN) --------------------------------*/
mrsoundhar 0:559a8e4aab60 665 typedef struct
mrsoundhar 0:559a8e4aab60 666 {
mrsoundhar 0:559a8e4aab60 667 __IO uint32_t mask[512]; /* ID Masks */
mrsoundhar 0:559a8e4aab60 668 } LPC_CANAF_RAM_TypeDef;
mrsoundhar 0:559a8e4aab60 669
mrsoundhar 0:559a8e4aab60 670 typedef struct /* Acceptance Filter Registers */
mrsoundhar 0:559a8e4aab60 671 {
mrsoundhar 0:559a8e4aab60 672 __IO uint32_t AFMR;
mrsoundhar 0:559a8e4aab60 673 __IO uint32_t SFF_sa;
mrsoundhar 0:559a8e4aab60 674 __IO uint32_t SFF_GRP_sa;
mrsoundhar 0:559a8e4aab60 675 __IO uint32_t EFF_sa;
mrsoundhar 0:559a8e4aab60 676 __IO uint32_t EFF_GRP_sa;
mrsoundhar 0:559a8e4aab60 677 __IO uint32_t ENDofTable;
mrsoundhar 0:559a8e4aab60 678 __I uint32_t LUTerrAd;
mrsoundhar 0:559a8e4aab60 679 __I uint32_t LUTerr;
mrsoundhar 0:559a8e4aab60 680 __IO uint32_t FCANIE;
mrsoundhar 0:559a8e4aab60 681 __IO uint32_t FCANIC0;
mrsoundhar 0:559a8e4aab60 682 __IO uint32_t FCANIC1;
mrsoundhar 0:559a8e4aab60 683 } LPC_CANAF_TypeDef;
mrsoundhar 0:559a8e4aab60 684
mrsoundhar 0:559a8e4aab60 685 typedef struct /* Central Registers */
mrsoundhar 0:559a8e4aab60 686 {
mrsoundhar 0:559a8e4aab60 687 __I uint32_t CANTxSR;
mrsoundhar 0:559a8e4aab60 688 __I uint32_t CANRxSR;
mrsoundhar 0:559a8e4aab60 689 __I uint32_t CANMSR;
mrsoundhar 0:559a8e4aab60 690 } LPC_CANCR_TypeDef;
mrsoundhar 0:559a8e4aab60 691
mrsoundhar 0:559a8e4aab60 692 typedef struct /* Controller Registers */
mrsoundhar 0:559a8e4aab60 693 {
mrsoundhar 0:559a8e4aab60 694 __IO uint32_t MOD;
mrsoundhar 0:559a8e4aab60 695 __O uint32_t CMR;
mrsoundhar 0:559a8e4aab60 696 __IO uint32_t GSR;
mrsoundhar 0:559a8e4aab60 697 __I uint32_t ICR;
mrsoundhar 0:559a8e4aab60 698 __IO uint32_t IER;
mrsoundhar 0:559a8e4aab60 699 __IO uint32_t BTR;
mrsoundhar 0:559a8e4aab60 700 __IO uint32_t EWL;
mrsoundhar 0:559a8e4aab60 701 __I uint32_t SR;
mrsoundhar 0:559a8e4aab60 702 __IO uint32_t RFS;
mrsoundhar 0:559a8e4aab60 703 __IO uint32_t RID;
mrsoundhar 0:559a8e4aab60 704 __IO uint32_t RDA;
mrsoundhar 0:559a8e4aab60 705 __IO uint32_t RDB;
mrsoundhar 0:559a8e4aab60 706 __IO uint32_t TFI1;
mrsoundhar 0:559a8e4aab60 707 __IO uint32_t TID1;
mrsoundhar 0:559a8e4aab60 708 __IO uint32_t TDA1;
mrsoundhar 0:559a8e4aab60 709 __IO uint32_t TDB1;
mrsoundhar 0:559a8e4aab60 710 __IO uint32_t TFI2;
mrsoundhar 0:559a8e4aab60 711 __IO uint32_t TID2;
mrsoundhar 0:559a8e4aab60 712 __IO uint32_t TDA2;
mrsoundhar 0:559a8e4aab60 713 __IO uint32_t TDB2;
mrsoundhar 0:559a8e4aab60 714 __IO uint32_t TFI3;
mrsoundhar 0:559a8e4aab60 715 __IO uint32_t TID3;
mrsoundhar 0:559a8e4aab60 716 __IO uint32_t TDA3;
mrsoundhar 0:559a8e4aab60 717 __IO uint32_t TDB3;
mrsoundhar 0:559a8e4aab60 718 } LPC_CAN_TypeDef;
mrsoundhar 0:559a8e4aab60 719
mrsoundhar 0:559a8e4aab60 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
mrsoundhar 0:559a8e4aab60 721 typedef struct /* Common Registers */
mrsoundhar 0:559a8e4aab60 722 {
mrsoundhar 0:559a8e4aab60 723 __I uint32_t DMACIntStat;
mrsoundhar 0:559a8e4aab60 724 __I uint32_t DMACIntTCStat;
mrsoundhar 0:559a8e4aab60 725 __O uint32_t DMACIntTCClear;
mrsoundhar 0:559a8e4aab60 726 __I uint32_t DMACIntErrStat;
mrsoundhar 0:559a8e4aab60 727 __O uint32_t DMACIntErrClr;
mrsoundhar 0:559a8e4aab60 728 __I uint32_t DMACRawIntTCStat;
mrsoundhar 0:559a8e4aab60 729 __I uint32_t DMACRawIntErrStat;
mrsoundhar 0:559a8e4aab60 730 __I uint32_t DMACEnbldChns;
mrsoundhar 0:559a8e4aab60 731 __IO uint32_t DMACSoftBReq;
mrsoundhar 0:559a8e4aab60 732 __IO uint32_t DMACSoftSReq;
mrsoundhar 0:559a8e4aab60 733 __IO uint32_t DMACSoftLBReq;
mrsoundhar 0:559a8e4aab60 734 __IO uint32_t DMACSoftLSReq;
mrsoundhar 0:559a8e4aab60 735 __IO uint32_t DMACConfig;
mrsoundhar 0:559a8e4aab60 736 __IO uint32_t DMACSync;
mrsoundhar 0:559a8e4aab60 737 } LPC_GPDMA_TypeDef;
mrsoundhar 0:559a8e4aab60 738
mrsoundhar 0:559a8e4aab60 739 typedef struct /* Channel Registers */
mrsoundhar 0:559a8e4aab60 740 {
mrsoundhar 0:559a8e4aab60 741 __IO uint32_t DMACCSrcAddr;
mrsoundhar 0:559a8e4aab60 742 __IO uint32_t DMACCDestAddr;
mrsoundhar 0:559a8e4aab60 743 __IO uint32_t DMACCLLI;
mrsoundhar 0:559a8e4aab60 744 __IO uint32_t DMACCControl;
mrsoundhar 0:559a8e4aab60 745 __IO uint32_t DMACCConfig;
mrsoundhar 0:559a8e4aab60 746 } LPC_GPDMACH_TypeDef;
mrsoundhar 0:559a8e4aab60 747
mrsoundhar 0:559a8e4aab60 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
mrsoundhar 0:559a8e4aab60 749 typedef struct
mrsoundhar 0:559a8e4aab60 750 {
mrsoundhar 0:559a8e4aab60 751 __I uint32_t HcRevision; /* USB Host Registers */
mrsoundhar 0:559a8e4aab60 752 __IO uint32_t HcControl;
mrsoundhar 0:559a8e4aab60 753 __IO uint32_t HcCommandStatus;
mrsoundhar 0:559a8e4aab60 754 __IO uint32_t HcInterruptStatus;
mrsoundhar 0:559a8e4aab60 755 __IO uint32_t HcInterruptEnable;
mrsoundhar 0:559a8e4aab60 756 __IO uint32_t HcInterruptDisable;
mrsoundhar 0:559a8e4aab60 757 __IO uint32_t HcHCCA;
mrsoundhar 0:559a8e4aab60 758 __I uint32_t HcPeriodCurrentED;
mrsoundhar 0:559a8e4aab60 759 __IO uint32_t HcControlHeadED;
mrsoundhar 0:559a8e4aab60 760 __IO uint32_t HcControlCurrentED;
mrsoundhar 0:559a8e4aab60 761 __IO uint32_t HcBulkHeadED;
mrsoundhar 0:559a8e4aab60 762 __IO uint32_t HcBulkCurrentED;
mrsoundhar 0:559a8e4aab60 763 __I uint32_t HcDoneHead;
mrsoundhar 0:559a8e4aab60 764 __IO uint32_t HcFmInterval;
mrsoundhar 0:559a8e4aab60 765 __I uint32_t HcFmRemaining;
mrsoundhar 0:559a8e4aab60 766 __I uint32_t HcFmNumber;
mrsoundhar 0:559a8e4aab60 767 __IO uint32_t HcPeriodicStart;
mrsoundhar 0:559a8e4aab60 768 __IO uint32_t HcLSTreshold;
mrsoundhar 0:559a8e4aab60 769 __IO uint32_t HcRhDescriptorA;
mrsoundhar 0:559a8e4aab60 770 __IO uint32_t HcRhDescriptorB;
mrsoundhar 0:559a8e4aab60 771 __IO uint32_t HcRhStatus;
mrsoundhar 0:559a8e4aab60 772 __IO uint32_t HcRhPortStatus1;
mrsoundhar 0:559a8e4aab60 773 __IO uint32_t HcRhPortStatus2;
mrsoundhar 0:559a8e4aab60 774 uint32_t RESERVED0[40];
mrsoundhar 0:559a8e4aab60 775 __I uint32_t Module_ID;
mrsoundhar 0:559a8e4aab60 776
mrsoundhar 0:559a8e4aab60 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
mrsoundhar 0:559a8e4aab60 778 __IO uint32_t OTGIntEn;
mrsoundhar 0:559a8e4aab60 779 __O uint32_t OTGIntSet;
mrsoundhar 0:559a8e4aab60 780 __O uint32_t OTGIntClr;
mrsoundhar 0:559a8e4aab60 781 __IO uint32_t OTGStCtrl;
mrsoundhar 0:559a8e4aab60 782 __IO uint32_t OTGTmr;
mrsoundhar 0:559a8e4aab60 783 uint32_t RESERVED1[58];
mrsoundhar 0:559a8e4aab60 784
mrsoundhar 0:559a8e4aab60 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
mrsoundhar 0:559a8e4aab60 786 __IO uint32_t USBDevIntEn;
mrsoundhar 0:559a8e4aab60 787 __O uint32_t USBDevIntClr;
mrsoundhar 0:559a8e4aab60 788 __O uint32_t USBDevIntSet;
mrsoundhar 0:559a8e4aab60 789
mrsoundhar 0:559a8e4aab60 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
mrsoundhar 0:559a8e4aab60 791 __I uint32_t USBCmdData;
mrsoundhar 0:559a8e4aab60 792
mrsoundhar 0:559a8e4aab60 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
mrsoundhar 0:559a8e4aab60 794 __O uint32_t USBTxData;
mrsoundhar 0:559a8e4aab60 795 __I uint32_t USBRxPLen;
mrsoundhar 0:559a8e4aab60 796 __O uint32_t USBTxPLen;
mrsoundhar 0:559a8e4aab60 797 __IO uint32_t USBCtrl;
mrsoundhar 0:559a8e4aab60 798 __O uint32_t USBDevIntPri;
mrsoundhar 0:559a8e4aab60 799
mrsoundhar 0:559a8e4aab60 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
mrsoundhar 0:559a8e4aab60 801 __IO uint32_t USBEpIntEn;
mrsoundhar 0:559a8e4aab60 802 __O uint32_t USBEpIntClr;
mrsoundhar 0:559a8e4aab60 803 __O uint32_t USBEpIntSet;
mrsoundhar 0:559a8e4aab60 804 __O uint32_t USBEpIntPri;
mrsoundhar 0:559a8e4aab60 805
mrsoundhar 0:559a8e4aab60 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
mrsoundhar 0:559a8e4aab60 807 __O uint32_t USBEpInd;
mrsoundhar 0:559a8e4aab60 808 __IO uint32_t USBMaxPSize;
mrsoundhar 0:559a8e4aab60 809
mrsoundhar 0:559a8e4aab60 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
mrsoundhar 0:559a8e4aab60 811 __O uint32_t USBDMARClr;
mrsoundhar 0:559a8e4aab60 812 __O uint32_t USBDMARSet;
mrsoundhar 0:559a8e4aab60 813 uint32_t RESERVED2[9];
mrsoundhar 0:559a8e4aab60 814 __IO uint32_t USBUDCAH;
mrsoundhar 0:559a8e4aab60 815 __I uint32_t USBEpDMASt;
mrsoundhar 0:559a8e4aab60 816 __O uint32_t USBEpDMAEn;
mrsoundhar 0:559a8e4aab60 817 __O uint32_t USBEpDMADis;
mrsoundhar 0:559a8e4aab60 818 __I uint32_t USBDMAIntSt;
mrsoundhar 0:559a8e4aab60 819 __IO uint32_t USBDMAIntEn;
mrsoundhar 0:559a8e4aab60 820 uint32_t RESERVED3[2];
mrsoundhar 0:559a8e4aab60 821 __I uint32_t USBEoTIntSt;
mrsoundhar 0:559a8e4aab60 822 __O uint32_t USBEoTIntClr;
mrsoundhar 0:559a8e4aab60 823 __O uint32_t USBEoTIntSet;
mrsoundhar 0:559a8e4aab60 824 __I uint32_t USBNDDRIntSt;
mrsoundhar 0:559a8e4aab60 825 __O uint32_t USBNDDRIntClr;
mrsoundhar 0:559a8e4aab60 826 __O uint32_t USBNDDRIntSet;
mrsoundhar 0:559a8e4aab60 827 __I uint32_t USBSysErrIntSt;
mrsoundhar 0:559a8e4aab60 828 __O uint32_t USBSysErrIntClr;
mrsoundhar 0:559a8e4aab60 829 __O uint32_t USBSysErrIntSet;
mrsoundhar 0:559a8e4aab60 830 uint32_t RESERVED4[15];
mrsoundhar 0:559a8e4aab60 831
mrsoundhar 0:559a8e4aab60 832 union {
mrsoundhar 0:559a8e4aab60 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
mrsoundhar 0:559a8e4aab60 834 __O uint32_t I2C_TX;
mrsoundhar 0:559a8e4aab60 835 };
mrsoundhar 0:559a8e4aab60 836 __I uint32_t I2C_STS;
mrsoundhar 0:559a8e4aab60 837 __IO uint32_t I2C_CTL;
mrsoundhar 0:559a8e4aab60 838 __IO uint32_t I2C_CLKHI;
mrsoundhar 0:559a8e4aab60 839 __O uint32_t I2C_CLKLO;
mrsoundhar 0:559a8e4aab60 840 uint32_t RESERVED5[824];
mrsoundhar 0:559a8e4aab60 841
mrsoundhar 0:559a8e4aab60 842 union {
mrsoundhar 0:559a8e4aab60 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
mrsoundhar 0:559a8e4aab60 844 __IO uint32_t OTGClkCtrl;
mrsoundhar 0:559a8e4aab60 845 };
mrsoundhar 0:559a8e4aab60 846 union {
mrsoundhar 0:559a8e4aab60 847 __I uint32_t USBClkSt;
mrsoundhar 0:559a8e4aab60 848 __I uint32_t OTGClkSt;
mrsoundhar 0:559a8e4aab60 849 };
mrsoundhar 0:559a8e4aab60 850 } LPC_USB_TypeDef;
mrsoundhar 0:559a8e4aab60 851
mrsoundhar 0:559a8e4aab60 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
mrsoundhar 0:559a8e4aab60 853 typedef struct
mrsoundhar 0:559a8e4aab60 854 {
mrsoundhar 0:559a8e4aab60 855 __IO uint32_t MAC1; /* MAC Registers */
mrsoundhar 0:559a8e4aab60 856 __IO uint32_t MAC2;
mrsoundhar 0:559a8e4aab60 857 __IO uint32_t IPGT;
mrsoundhar 0:559a8e4aab60 858 __IO uint32_t IPGR;
mrsoundhar 0:559a8e4aab60 859 __IO uint32_t CLRT;
mrsoundhar 0:559a8e4aab60 860 __IO uint32_t MAXF;
mrsoundhar 0:559a8e4aab60 861 __IO uint32_t SUPP;
mrsoundhar 0:559a8e4aab60 862 __IO uint32_t TEST;
mrsoundhar 0:559a8e4aab60 863 __IO uint32_t MCFG;
mrsoundhar 0:559a8e4aab60 864 __IO uint32_t MCMD;
mrsoundhar 0:559a8e4aab60 865 __IO uint32_t MADR;
mrsoundhar 0:559a8e4aab60 866 __O uint32_t MWTD;
mrsoundhar 0:559a8e4aab60 867 __I uint32_t MRDD;
mrsoundhar 0:559a8e4aab60 868 __I uint32_t MIND;
mrsoundhar 0:559a8e4aab60 869 uint32_t RESERVED0[2];
mrsoundhar 0:559a8e4aab60 870 __IO uint32_t SA0;
mrsoundhar 0:559a8e4aab60 871 __IO uint32_t SA1;
mrsoundhar 0:559a8e4aab60 872 __IO uint32_t SA2;
mrsoundhar 0:559a8e4aab60 873 uint32_t RESERVED1[45];
mrsoundhar 0:559a8e4aab60 874 __IO uint32_t Command; /* Control Registers */
mrsoundhar 0:559a8e4aab60 875 __I uint32_t Status;
mrsoundhar 0:559a8e4aab60 876 __IO uint32_t RxDescriptor;
mrsoundhar 0:559a8e4aab60 877 __IO uint32_t RxStatus;
mrsoundhar 0:559a8e4aab60 878 __IO uint32_t RxDescriptorNumber;
mrsoundhar 0:559a8e4aab60 879 __I uint32_t RxProduceIndex;
mrsoundhar 0:559a8e4aab60 880 __IO uint32_t RxConsumeIndex;
mrsoundhar 0:559a8e4aab60 881 __IO uint32_t TxDescriptor;
mrsoundhar 0:559a8e4aab60 882 __IO uint32_t TxStatus;
mrsoundhar 0:559a8e4aab60 883 __IO uint32_t TxDescriptorNumber;
mrsoundhar 0:559a8e4aab60 884 __IO uint32_t TxProduceIndex;
mrsoundhar 0:559a8e4aab60 885 __I uint32_t TxConsumeIndex;
mrsoundhar 0:559a8e4aab60 886 uint32_t RESERVED2[10];
mrsoundhar 0:559a8e4aab60 887 __I uint32_t TSV0;
mrsoundhar 0:559a8e4aab60 888 __I uint32_t TSV1;
mrsoundhar 0:559a8e4aab60 889 __I uint32_t RSV;
mrsoundhar 0:559a8e4aab60 890 uint32_t RESERVED3[3];
mrsoundhar 0:559a8e4aab60 891 __IO uint32_t FlowControlCounter;
mrsoundhar 0:559a8e4aab60 892 __I uint32_t FlowControlStatus;
mrsoundhar 0:559a8e4aab60 893 uint32_t RESERVED4[34];
mrsoundhar 0:559a8e4aab60 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
mrsoundhar 0:559a8e4aab60 895 __IO uint32_t RxFilterWoLStatus;
mrsoundhar 0:559a8e4aab60 896 __IO uint32_t RxFilterWoLClear;
mrsoundhar 0:559a8e4aab60 897 uint32_t RESERVED5;
mrsoundhar 0:559a8e4aab60 898 __IO uint32_t HashFilterL;
mrsoundhar 0:559a8e4aab60 899 __IO uint32_t HashFilterH;
mrsoundhar 0:559a8e4aab60 900 uint32_t RESERVED6[882];
mrsoundhar 0:559a8e4aab60 901 __I uint32_t IntStatus; /* Module Control Registers */
mrsoundhar 0:559a8e4aab60 902 __IO uint32_t IntEnable;
mrsoundhar 0:559a8e4aab60 903 __O uint32_t IntClear;
mrsoundhar 0:559a8e4aab60 904 __O uint32_t IntSet;
mrsoundhar 0:559a8e4aab60 905 uint32_t RESERVED7;
mrsoundhar 0:559a8e4aab60 906 __IO uint32_t PowerDown;
mrsoundhar 0:559a8e4aab60 907 uint32_t RESERVED8;
mrsoundhar 0:559a8e4aab60 908 __IO uint32_t Module_ID;
mrsoundhar 0:559a8e4aab60 909 } LPC_EMAC_TypeDef;
mrsoundhar 0:559a8e4aab60 910
mrsoundhar 0:559a8e4aab60 911 #if defined ( __CC_ARM )
mrsoundhar 0:559a8e4aab60 912 #pragma no_anon_unions
mrsoundhar 0:559a8e4aab60 913 #endif
mrsoundhar 0:559a8e4aab60 914
mrsoundhar 0:559a8e4aab60 915
mrsoundhar 0:559a8e4aab60 916 /******************************************************************************/
mrsoundhar 0:559a8e4aab60 917 /* Peripheral memory map */
mrsoundhar 0:559a8e4aab60 918 /******************************************************************************/
mrsoundhar 0:559a8e4aab60 919 /* Base addresses */
mrsoundhar 0:559a8e4aab60 920 #define LPC_FLASH_BASE (0x00000000UL)
mrsoundhar 0:559a8e4aab60 921 #define LPC_RAM_BASE (0x10000000UL)
mrsoundhar 0:559a8e4aab60 922 #define LPC_GPIO_BASE (0x2009C000UL)
mrsoundhar 0:559a8e4aab60 923 #define LPC_APB0_BASE (0x40000000UL)
mrsoundhar 0:559a8e4aab60 924 #define LPC_APB1_BASE (0x40080000UL)
mrsoundhar 0:559a8e4aab60 925 #define LPC_AHB_BASE (0x50000000UL)
mrsoundhar 0:559a8e4aab60 926 #define LPC_CM3_BASE (0xE0000000UL)
mrsoundhar 0:559a8e4aab60 927
mrsoundhar 0:559a8e4aab60 928 /* APB0 peripherals */
mrsoundhar 0:559a8e4aab60 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
mrsoundhar 0:559a8e4aab60 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
mrsoundhar 0:559a8e4aab60 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
mrsoundhar 0:559a8e4aab60 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
mrsoundhar 0:559a8e4aab60 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
mrsoundhar 0:559a8e4aab60 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
mrsoundhar 0:559a8e4aab60 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
mrsoundhar 0:559a8e4aab60 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
mrsoundhar 0:559a8e4aab60 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
mrsoundhar 0:559a8e4aab60 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
mrsoundhar 0:559a8e4aab60 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
mrsoundhar 0:559a8e4aab60 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
mrsoundhar 0:559a8e4aab60 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
mrsoundhar 0:559a8e4aab60 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
mrsoundhar 0:559a8e4aab60 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
mrsoundhar 0:559a8e4aab60 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
mrsoundhar 0:559a8e4aab60 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
mrsoundhar 0:559a8e4aab60 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
mrsoundhar 0:559a8e4aab60 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
mrsoundhar 0:559a8e4aab60 948
mrsoundhar 0:559a8e4aab60 949 /* APB1 peripherals */
mrsoundhar 0:559a8e4aab60 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
mrsoundhar 0:559a8e4aab60 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
mrsoundhar 0:559a8e4aab60 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
mrsoundhar 0:559a8e4aab60 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
mrsoundhar 0:559a8e4aab60 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
mrsoundhar 0:559a8e4aab60 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
mrsoundhar 0:559a8e4aab60 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
mrsoundhar 0:559a8e4aab60 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
mrsoundhar 0:559a8e4aab60 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
mrsoundhar 0:559a8e4aab60 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
mrsoundhar 0:559a8e4aab60 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
mrsoundhar 0:559a8e4aab60 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
mrsoundhar 0:559a8e4aab60 962
mrsoundhar 0:559a8e4aab60 963 /* AHB peripherals */
mrsoundhar 0:559a8e4aab60 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
mrsoundhar 0:559a8e4aab60 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
mrsoundhar 0:559a8e4aab60 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
mrsoundhar 0:559a8e4aab60 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
mrsoundhar 0:559a8e4aab60 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
mrsoundhar 0:559a8e4aab60 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
mrsoundhar 0:559a8e4aab60 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
mrsoundhar 0:559a8e4aab60 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
mrsoundhar 0:559a8e4aab60 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
mrsoundhar 0:559a8e4aab60 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
mrsoundhar 0:559a8e4aab60 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
mrsoundhar 0:559a8e4aab60 975
mrsoundhar 0:559a8e4aab60 976 /* GPIOs */
mrsoundhar 0:559a8e4aab60 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
mrsoundhar 0:559a8e4aab60 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
mrsoundhar 0:559a8e4aab60 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
mrsoundhar 0:559a8e4aab60 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
mrsoundhar 0:559a8e4aab60 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
mrsoundhar 0:559a8e4aab60 982
mrsoundhar 0:559a8e4aab60 983
mrsoundhar 0:559a8e4aab60 984 /******************************************************************************/
mrsoundhar 0:559a8e4aab60 985 /* Peripheral declaration */
mrsoundhar 0:559a8e4aab60 986 /******************************************************************************/
mrsoundhar 0:559a8e4aab60 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
mrsoundhar 0:559a8e4aab60 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
mrsoundhar 0:559a8e4aab60 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
mrsoundhar 0:559a8e4aab60 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
mrsoundhar 0:559a8e4aab60 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
mrsoundhar 0:559a8e4aab60 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
mrsoundhar 0:559a8e4aab60 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
mrsoundhar 0:559a8e4aab60 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
mrsoundhar 0:559a8e4aab60 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
mrsoundhar 0:559a8e4aab60 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
mrsoundhar 0:559a8e4aab60 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
mrsoundhar 0:559a8e4aab60 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
mrsoundhar 0:559a8e4aab60 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
mrsoundhar 0:559a8e4aab60 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
mrsoundhar 0:559a8e4aab60 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
mrsoundhar 0:559a8e4aab60 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
mrsoundhar 0:559a8e4aab60 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
mrsoundhar 0:559a8e4aab60 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
mrsoundhar 0:559a8e4aab60 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
mrsoundhar 0:559a8e4aab60 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
mrsoundhar 0:559a8e4aab60 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
mrsoundhar 0:559a8e4aab60 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
mrsoundhar 0:559a8e4aab60 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
mrsoundhar 0:559a8e4aab60 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
mrsoundhar 0:559a8e4aab60 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
mrsoundhar 0:559a8e4aab60 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
mrsoundhar 0:559a8e4aab60 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
mrsoundhar 0:559a8e4aab60 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
mrsoundhar 0:559a8e4aab60 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
mrsoundhar 0:559a8e4aab60 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
mrsoundhar 0:559a8e4aab60 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
mrsoundhar 0:559a8e4aab60 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
mrsoundhar 0:559a8e4aab60 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
mrsoundhar 0:559a8e4aab60 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
mrsoundhar 0:559a8e4aab60 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
mrsoundhar 0:559a8e4aab60 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
mrsoundhar 0:559a8e4aab60 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
mrsoundhar 0:559a8e4aab60 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
mrsoundhar 0:559a8e4aab60 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
mrsoundhar 0:559a8e4aab60 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
mrsoundhar 0:559a8e4aab60 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
mrsoundhar 0:559a8e4aab60 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
mrsoundhar 0:559a8e4aab60 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
mrsoundhar 0:559a8e4aab60 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
mrsoundhar 0:559a8e4aab60 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
mrsoundhar 0:559a8e4aab60 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
mrsoundhar 0:559a8e4aab60 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
mrsoundhar 0:559a8e4aab60 1034
mrsoundhar 0:559a8e4aab60 1035 #endif // __LPC17xx_H__