Sertel_Srinath Gopalan / TARGET_LPC1768_N

LPC1768

core_cmFunc.h@0:ae306d3f6076, 2014-11-19 (annotated)

Committer:
mrsoundhar
Date:
Wed Nov 19 05:50:22 2014 +0000
Revision:
0:ae306d3f6076
publish

Who changed what in which revision?

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mrsoundhar 0:ae306d3f6076 1 /**************************************************************************//**
mrsoundhar 0:ae306d3f6076 2 * @file core_cmFunc.h
mrsoundhar 0:ae306d3f6076 3 * @brief CMSIS Cortex-M Core Function Access Header File
mrsoundhar 0:ae306d3f6076 4 * @version V3.20
mrsoundhar 0:ae306d3f6076 5 * @date 25. February 2013
mrsoundhar 0:ae306d3f6076 6 *
mrsoundhar 0:ae306d3f6076 7 * @note
mrsoundhar 0:ae306d3f6076 8 *
mrsoundhar 0:ae306d3f6076 9 ******************************************************************************/
mrsoundhar 0:ae306d3f6076 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mrsoundhar 0:ae306d3f6076 11
mrsoundhar 0:ae306d3f6076 12 All rights reserved.
mrsoundhar 0:ae306d3f6076 13 Redistribution and use in source and binary forms, with or without
mrsoundhar 0:ae306d3f6076 14 modification, are permitted provided that the following conditions are met:
mrsoundhar 0:ae306d3f6076 15 - Redistributions of source code must retain the above copyright
mrsoundhar 0:ae306d3f6076 16 notice, this list of conditions and the following disclaimer.
mrsoundhar 0:ae306d3f6076 17 - Redistributions in binary form must reproduce the above copyright
mrsoundhar 0:ae306d3f6076 18 notice, this list of conditions and the following disclaimer in the
mrsoundhar 0:ae306d3f6076 19 documentation and/or other materials provided with the distribution.
mrsoundhar 0:ae306d3f6076 20 - Neither the name of ARM nor the names of its contributors may be used
mrsoundhar 0:ae306d3f6076 21 to endorse or promote products derived from this software without
mrsoundhar 0:ae306d3f6076 22 specific prior written permission.
mrsoundhar 0:ae306d3f6076 23 *
mrsoundhar 0:ae306d3f6076 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mrsoundhar 0:ae306d3f6076 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mrsoundhar 0:ae306d3f6076 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mrsoundhar 0:ae306d3f6076 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mrsoundhar 0:ae306d3f6076 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mrsoundhar 0:ae306d3f6076 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mrsoundhar 0:ae306d3f6076 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mrsoundhar 0:ae306d3f6076 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mrsoundhar 0:ae306d3f6076 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mrsoundhar 0:ae306d3f6076 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mrsoundhar 0:ae306d3f6076 34 POSSIBILITY OF SUCH DAMAGE.
mrsoundhar 0:ae306d3f6076 35 ---------------------------------------------------------------------------*/
mrsoundhar 0:ae306d3f6076 36
mrsoundhar 0:ae306d3f6076 37
mrsoundhar 0:ae306d3f6076 38 #ifndef __CORE_CMFUNC_H
mrsoundhar 0:ae306d3f6076 39 #define __CORE_CMFUNC_H
mrsoundhar 0:ae306d3f6076 40
mrsoundhar 0:ae306d3f6076 41
mrsoundhar 0:ae306d3f6076 42 /* ########################### Core Function Access ########################### */
mrsoundhar 0:ae306d3f6076 43 /** \ingroup CMSIS_Core_FunctionInterface
mrsoundhar 0:ae306d3f6076 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mrsoundhar 0:ae306d3f6076 45 @{
mrsoundhar 0:ae306d3f6076 46 */
mrsoundhar 0:ae306d3f6076 47
mrsoundhar 0:ae306d3f6076 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mrsoundhar 0:ae306d3f6076 49 /* ARM armcc specific functions */
mrsoundhar 0:ae306d3f6076 50
mrsoundhar 0:ae306d3f6076 51 #if (__ARMCC_VERSION < 400677)
mrsoundhar 0:ae306d3f6076 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mrsoundhar 0:ae306d3f6076 53 #endif
mrsoundhar 0:ae306d3f6076 54
mrsoundhar 0:ae306d3f6076 55 /* intrinsic void __enable_irq(); */
mrsoundhar 0:ae306d3f6076 56 /* intrinsic void __disable_irq(); */
mrsoundhar 0:ae306d3f6076 57
mrsoundhar 0:ae306d3f6076 58 /** \brief Get Control Register
mrsoundhar 0:ae306d3f6076 59
mrsoundhar 0:ae306d3f6076 60 This function returns the content of the Control Register.
mrsoundhar 0:ae306d3f6076 61
mrsoundhar 0:ae306d3f6076 62 \return Control Register value
mrsoundhar 0:ae306d3f6076 63 */
mrsoundhar 0:ae306d3f6076 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
mrsoundhar 0:ae306d3f6076 65 {
mrsoundhar 0:ae306d3f6076 66 register uint32_t __regControl __ASM("control");
mrsoundhar 0:ae306d3f6076 67 return(__regControl);
mrsoundhar 0:ae306d3f6076 68 }
mrsoundhar 0:ae306d3f6076 69
mrsoundhar 0:ae306d3f6076 70
mrsoundhar 0:ae306d3f6076 71 /** \brief Set Control Register
mrsoundhar 0:ae306d3f6076 72
mrsoundhar 0:ae306d3f6076 73 This function writes the given value to the Control Register.
mrsoundhar 0:ae306d3f6076 74
mrsoundhar 0:ae306d3f6076 75 \param [in] control Control Register value to set
mrsoundhar 0:ae306d3f6076 76 */
mrsoundhar 0:ae306d3f6076 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
mrsoundhar 0:ae306d3f6076 78 {
mrsoundhar 0:ae306d3f6076 79 register uint32_t __regControl __ASM("control");
mrsoundhar 0:ae306d3f6076 80 __regControl = control;
mrsoundhar 0:ae306d3f6076 81 }
mrsoundhar 0:ae306d3f6076 82
mrsoundhar 0:ae306d3f6076 83
mrsoundhar 0:ae306d3f6076 84 /** \brief Get IPSR Register
mrsoundhar 0:ae306d3f6076 85
mrsoundhar 0:ae306d3f6076 86 This function returns the content of the IPSR Register.
mrsoundhar 0:ae306d3f6076 87
mrsoundhar 0:ae306d3f6076 88 \return IPSR Register value
mrsoundhar 0:ae306d3f6076 89 */
mrsoundhar 0:ae306d3f6076 90 __STATIC_INLINE uint32_t __get_IPSR(void)
mrsoundhar 0:ae306d3f6076 91 {
mrsoundhar 0:ae306d3f6076 92 register uint32_t __regIPSR __ASM("ipsr");
mrsoundhar 0:ae306d3f6076 93 return(__regIPSR);
mrsoundhar 0:ae306d3f6076 94 }
mrsoundhar 0:ae306d3f6076 95
mrsoundhar 0:ae306d3f6076 96
mrsoundhar 0:ae306d3f6076 97 /** \brief Get APSR Register
mrsoundhar 0:ae306d3f6076 98
mrsoundhar 0:ae306d3f6076 99 This function returns the content of the APSR Register.
mrsoundhar 0:ae306d3f6076 100
mrsoundhar 0:ae306d3f6076 101 \return APSR Register value
mrsoundhar 0:ae306d3f6076 102 */
mrsoundhar 0:ae306d3f6076 103 __STATIC_INLINE uint32_t __get_APSR(void)
mrsoundhar 0:ae306d3f6076 104 {
mrsoundhar 0:ae306d3f6076 105 register uint32_t __regAPSR __ASM("apsr");
mrsoundhar 0:ae306d3f6076 106 return(__regAPSR);
mrsoundhar 0:ae306d3f6076 107 }
mrsoundhar 0:ae306d3f6076 108
mrsoundhar 0:ae306d3f6076 109
mrsoundhar 0:ae306d3f6076 110 /** \brief Get xPSR Register
mrsoundhar 0:ae306d3f6076 111
mrsoundhar 0:ae306d3f6076 112 This function returns the content of the xPSR Register.
mrsoundhar 0:ae306d3f6076 113
mrsoundhar 0:ae306d3f6076 114 \return xPSR Register value
mrsoundhar 0:ae306d3f6076 115 */
mrsoundhar 0:ae306d3f6076 116 __STATIC_INLINE uint32_t __get_xPSR(void)
mrsoundhar 0:ae306d3f6076 117 {
mrsoundhar 0:ae306d3f6076 118 register uint32_t __regXPSR __ASM("xpsr");
mrsoundhar 0:ae306d3f6076 119 return(__regXPSR);
mrsoundhar 0:ae306d3f6076 120 }
mrsoundhar 0:ae306d3f6076 121
mrsoundhar 0:ae306d3f6076 122
mrsoundhar 0:ae306d3f6076 123 /** \brief Get Process Stack Pointer
mrsoundhar 0:ae306d3f6076 124
mrsoundhar 0:ae306d3f6076 125 This function returns the current value of the Process Stack Pointer (PSP).
mrsoundhar 0:ae306d3f6076 126
mrsoundhar 0:ae306d3f6076 127 \return PSP Register value
mrsoundhar 0:ae306d3f6076 128 */
mrsoundhar 0:ae306d3f6076 129 __STATIC_INLINE uint32_t __get_PSP(void)
mrsoundhar 0:ae306d3f6076 130 {
mrsoundhar 0:ae306d3f6076 131 register uint32_t __regProcessStackPointer __ASM("psp");
mrsoundhar 0:ae306d3f6076 132 return(__regProcessStackPointer);
mrsoundhar 0:ae306d3f6076 133 }
mrsoundhar 0:ae306d3f6076 134
mrsoundhar 0:ae306d3f6076 135
mrsoundhar 0:ae306d3f6076 136 /** \brief Set Process Stack Pointer
mrsoundhar 0:ae306d3f6076 137
mrsoundhar 0:ae306d3f6076 138 This function assigns the given value to the Process Stack Pointer (PSP).
mrsoundhar 0:ae306d3f6076 139
mrsoundhar 0:ae306d3f6076 140 \param [in] topOfProcStack Process Stack Pointer value to set
mrsoundhar 0:ae306d3f6076 141 */
mrsoundhar 0:ae306d3f6076 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mrsoundhar 0:ae306d3f6076 143 {
mrsoundhar 0:ae306d3f6076 144 register uint32_t __regProcessStackPointer __ASM("psp");
mrsoundhar 0:ae306d3f6076 145 __regProcessStackPointer = topOfProcStack;
mrsoundhar 0:ae306d3f6076 146 }
mrsoundhar 0:ae306d3f6076 147
mrsoundhar 0:ae306d3f6076 148
mrsoundhar 0:ae306d3f6076 149 /** \brief Get Main Stack Pointer
mrsoundhar 0:ae306d3f6076 150
mrsoundhar 0:ae306d3f6076 151 This function returns the current value of the Main Stack Pointer (MSP).
mrsoundhar 0:ae306d3f6076 152
mrsoundhar 0:ae306d3f6076 153 \return MSP Register value
mrsoundhar 0:ae306d3f6076 154 */
mrsoundhar 0:ae306d3f6076 155 __STATIC_INLINE uint32_t __get_MSP(void)
mrsoundhar 0:ae306d3f6076 156 {
mrsoundhar 0:ae306d3f6076 157 register uint32_t __regMainStackPointer __ASM("msp");
mrsoundhar 0:ae306d3f6076 158 return(__regMainStackPointer);
mrsoundhar 0:ae306d3f6076 159 }
mrsoundhar 0:ae306d3f6076 160
mrsoundhar 0:ae306d3f6076 161
mrsoundhar 0:ae306d3f6076 162 /** \brief Set Main Stack Pointer
mrsoundhar 0:ae306d3f6076 163
mrsoundhar 0:ae306d3f6076 164 This function assigns the given value to the Main Stack Pointer (MSP).
mrsoundhar 0:ae306d3f6076 165
mrsoundhar 0:ae306d3f6076 166 \param [in] topOfMainStack Main Stack Pointer value to set
mrsoundhar 0:ae306d3f6076 167 */
mrsoundhar 0:ae306d3f6076 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mrsoundhar 0:ae306d3f6076 169 {
mrsoundhar 0:ae306d3f6076 170 register uint32_t __regMainStackPointer __ASM("msp");
mrsoundhar 0:ae306d3f6076 171 __regMainStackPointer = topOfMainStack;
mrsoundhar 0:ae306d3f6076 172 }
mrsoundhar 0:ae306d3f6076 173
mrsoundhar 0:ae306d3f6076 174
mrsoundhar 0:ae306d3f6076 175 /** \brief Get Priority Mask
mrsoundhar 0:ae306d3f6076 176
mrsoundhar 0:ae306d3f6076 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
mrsoundhar 0:ae306d3f6076 178
mrsoundhar 0:ae306d3f6076 179 \return Priority Mask value
mrsoundhar 0:ae306d3f6076 180 */
mrsoundhar 0:ae306d3f6076 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
mrsoundhar 0:ae306d3f6076 182 {
mrsoundhar 0:ae306d3f6076 183 register uint32_t __regPriMask __ASM("primask");
mrsoundhar 0:ae306d3f6076 184 return(__regPriMask);
mrsoundhar 0:ae306d3f6076 185 }
mrsoundhar 0:ae306d3f6076 186
mrsoundhar 0:ae306d3f6076 187
mrsoundhar 0:ae306d3f6076 188 /** \brief Set Priority Mask
mrsoundhar 0:ae306d3f6076 189
mrsoundhar 0:ae306d3f6076 190 This function assigns the given value to the Priority Mask Register.
mrsoundhar 0:ae306d3f6076 191
mrsoundhar 0:ae306d3f6076 192 \param [in] priMask Priority Mask
mrsoundhar 0:ae306d3f6076 193 */
mrsoundhar 0:ae306d3f6076 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mrsoundhar 0:ae306d3f6076 195 {
mrsoundhar 0:ae306d3f6076 196 register uint32_t __regPriMask __ASM("primask");
mrsoundhar 0:ae306d3f6076 197 __regPriMask = (priMask);
mrsoundhar 0:ae306d3f6076 198 }
mrsoundhar 0:ae306d3f6076 199
mrsoundhar 0:ae306d3f6076 200
mrsoundhar 0:ae306d3f6076 201 #if (__CORTEX_M >= 0x03)
mrsoundhar 0:ae306d3f6076 202
mrsoundhar 0:ae306d3f6076 203 /** \brief Enable FIQ
mrsoundhar 0:ae306d3f6076 204
mrsoundhar 0:ae306d3f6076 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mrsoundhar 0:ae306d3f6076 206 Can only be executed in Privileged modes.
mrsoundhar 0:ae306d3f6076 207 */
mrsoundhar 0:ae306d3f6076 208 #define __enable_fault_irq __enable_fiq
mrsoundhar 0:ae306d3f6076 209
mrsoundhar 0:ae306d3f6076 210
mrsoundhar 0:ae306d3f6076 211 /** \brief Disable FIQ
mrsoundhar 0:ae306d3f6076 212
mrsoundhar 0:ae306d3f6076 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mrsoundhar 0:ae306d3f6076 214 Can only be executed in Privileged modes.
mrsoundhar 0:ae306d3f6076 215 */
mrsoundhar 0:ae306d3f6076 216 #define __disable_fault_irq __disable_fiq
mrsoundhar 0:ae306d3f6076 217
mrsoundhar 0:ae306d3f6076 218
mrsoundhar 0:ae306d3f6076 219 /** \brief Get Base Priority
mrsoundhar 0:ae306d3f6076 220
mrsoundhar 0:ae306d3f6076 221 This function returns the current value of the Base Priority register.
mrsoundhar 0:ae306d3f6076 222
mrsoundhar 0:ae306d3f6076 223 \return Base Priority register value
mrsoundhar 0:ae306d3f6076 224 */
mrsoundhar 0:ae306d3f6076 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
mrsoundhar 0:ae306d3f6076 226 {
mrsoundhar 0:ae306d3f6076 227 register uint32_t __regBasePri __ASM("basepri");
mrsoundhar 0:ae306d3f6076 228 return(__regBasePri);
mrsoundhar 0:ae306d3f6076 229 }
mrsoundhar 0:ae306d3f6076 230
mrsoundhar 0:ae306d3f6076 231
mrsoundhar 0:ae306d3f6076 232 /** \brief Set Base Priority
mrsoundhar 0:ae306d3f6076 233
mrsoundhar 0:ae306d3f6076 234 This function assigns the given value to the Base Priority register.
mrsoundhar 0:ae306d3f6076 235
mrsoundhar 0:ae306d3f6076 236 \param [in] basePri Base Priority value to set
mrsoundhar 0:ae306d3f6076 237 */
mrsoundhar 0:ae306d3f6076 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
mrsoundhar 0:ae306d3f6076 239 {
mrsoundhar 0:ae306d3f6076 240 register uint32_t __regBasePri __ASM("basepri");
mrsoundhar 0:ae306d3f6076 241 __regBasePri = (basePri & 0xff);
mrsoundhar 0:ae306d3f6076 242 }
mrsoundhar 0:ae306d3f6076 243
mrsoundhar 0:ae306d3f6076 244
mrsoundhar 0:ae306d3f6076 245 /** \brief Get Fault Mask
mrsoundhar 0:ae306d3f6076 246
mrsoundhar 0:ae306d3f6076 247 This function returns the current value of the Fault Mask register.
mrsoundhar 0:ae306d3f6076 248
mrsoundhar 0:ae306d3f6076 249 \return Fault Mask register value
mrsoundhar 0:ae306d3f6076 250 */
mrsoundhar 0:ae306d3f6076 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mrsoundhar 0:ae306d3f6076 252 {
mrsoundhar 0:ae306d3f6076 253 register uint32_t __regFaultMask __ASM("faultmask");
mrsoundhar 0:ae306d3f6076 254 return(__regFaultMask);
mrsoundhar 0:ae306d3f6076 255 }
mrsoundhar 0:ae306d3f6076 256
mrsoundhar 0:ae306d3f6076 257
mrsoundhar 0:ae306d3f6076 258 /** \brief Set Fault Mask
mrsoundhar 0:ae306d3f6076 259
mrsoundhar 0:ae306d3f6076 260 This function assigns the given value to the Fault Mask register.
mrsoundhar 0:ae306d3f6076 261
mrsoundhar 0:ae306d3f6076 262 \param [in] faultMask Fault Mask value to set
mrsoundhar 0:ae306d3f6076 263 */
mrsoundhar 0:ae306d3f6076 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mrsoundhar 0:ae306d3f6076 265 {
mrsoundhar 0:ae306d3f6076 266 register uint32_t __regFaultMask __ASM("faultmask");
mrsoundhar 0:ae306d3f6076 267 __regFaultMask = (faultMask & (uint32_t)1);
mrsoundhar 0:ae306d3f6076 268 }
mrsoundhar 0:ae306d3f6076 269
mrsoundhar 0:ae306d3f6076 270 #endif /* (__CORTEX_M >= 0x03) */
mrsoundhar 0:ae306d3f6076 271
mrsoundhar 0:ae306d3f6076 272
mrsoundhar 0:ae306d3f6076 273 #if (__CORTEX_M == 0x04)
mrsoundhar 0:ae306d3f6076 274
mrsoundhar 0:ae306d3f6076 275 /** \brief Get FPSCR
mrsoundhar 0:ae306d3f6076 276
mrsoundhar 0:ae306d3f6076 277 This function returns the current value of the Floating Point Status/Control register.
mrsoundhar 0:ae306d3f6076 278
mrsoundhar 0:ae306d3f6076 279 \return Floating Point Status/Control register value
mrsoundhar 0:ae306d3f6076 280 */
mrsoundhar 0:ae306d3f6076 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
mrsoundhar 0:ae306d3f6076 282 {
mrsoundhar 0:ae306d3f6076 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mrsoundhar 0:ae306d3f6076 284 register uint32_t __regfpscr __ASM("fpscr");
mrsoundhar 0:ae306d3f6076 285 return(__regfpscr);
mrsoundhar 0:ae306d3f6076 286 #else
mrsoundhar 0:ae306d3f6076 287 return(0);
mrsoundhar 0:ae306d3f6076 288 #endif
mrsoundhar 0:ae306d3f6076 289 }
mrsoundhar 0:ae306d3f6076 290
mrsoundhar 0:ae306d3f6076 291
mrsoundhar 0:ae306d3f6076 292 /** \brief Set FPSCR
mrsoundhar 0:ae306d3f6076 293
mrsoundhar 0:ae306d3f6076 294 This function assigns the given value to the Floating Point Status/Control register.
mrsoundhar 0:ae306d3f6076 295
mrsoundhar 0:ae306d3f6076 296 \param [in] fpscr Floating Point Status/Control value to set
mrsoundhar 0:ae306d3f6076 297 */
mrsoundhar 0:ae306d3f6076 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mrsoundhar 0:ae306d3f6076 299 {
mrsoundhar 0:ae306d3f6076 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mrsoundhar 0:ae306d3f6076 301 register uint32_t __regfpscr __ASM("fpscr");
mrsoundhar 0:ae306d3f6076 302 __regfpscr = (fpscr);
mrsoundhar 0:ae306d3f6076 303 #endif
mrsoundhar 0:ae306d3f6076 304 }
mrsoundhar 0:ae306d3f6076 305
mrsoundhar 0:ae306d3f6076 306 #endif /* (__CORTEX_M == 0x04) */
mrsoundhar 0:ae306d3f6076 307
mrsoundhar 0:ae306d3f6076 308
mrsoundhar 0:ae306d3f6076 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mrsoundhar 0:ae306d3f6076 310 /* IAR iccarm specific functions */
mrsoundhar 0:ae306d3f6076 311
mrsoundhar 0:ae306d3f6076 312 #include <cmsis_iar.h>
mrsoundhar 0:ae306d3f6076 313
mrsoundhar 0:ae306d3f6076 314
mrsoundhar 0:ae306d3f6076 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mrsoundhar 0:ae306d3f6076 316 /* TI CCS specific functions */
mrsoundhar 0:ae306d3f6076 317
mrsoundhar 0:ae306d3f6076 318 #include <cmsis_ccs.h>
mrsoundhar 0:ae306d3f6076 319
mrsoundhar 0:ae306d3f6076 320
mrsoundhar 0:ae306d3f6076 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mrsoundhar 0:ae306d3f6076 322 /* GNU gcc specific functions */
mrsoundhar 0:ae306d3f6076 323
mrsoundhar 0:ae306d3f6076 324 /** \brief Enable IRQ Interrupts
mrsoundhar 0:ae306d3f6076 325
mrsoundhar 0:ae306d3f6076 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
mrsoundhar 0:ae306d3f6076 327 Can only be executed in Privileged modes.
mrsoundhar 0:ae306d3f6076 328 */
mrsoundhar 0:ae306d3f6076 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mrsoundhar 0:ae306d3f6076 330 {
mrsoundhar 0:ae306d3f6076 331 __ASM volatile ("cpsie i" : : : "memory");
mrsoundhar 0:ae306d3f6076 332 }
mrsoundhar 0:ae306d3f6076 333
mrsoundhar 0:ae306d3f6076 334
mrsoundhar 0:ae306d3f6076 335 /** \brief Disable IRQ Interrupts
mrsoundhar 0:ae306d3f6076 336
mrsoundhar 0:ae306d3f6076 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mrsoundhar 0:ae306d3f6076 338 Can only be executed in Privileged modes.
mrsoundhar 0:ae306d3f6076 339 */
mrsoundhar 0:ae306d3f6076 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
mrsoundhar 0:ae306d3f6076 341 {
mrsoundhar 0:ae306d3f6076 342 __ASM volatile ("cpsid i" : : : "memory");
mrsoundhar 0:ae306d3f6076 343 }
mrsoundhar 0:ae306d3f6076 344
mrsoundhar 0:ae306d3f6076 345
mrsoundhar 0:ae306d3f6076 346 /** \brief Get Control Register
mrsoundhar 0:ae306d3f6076 347
mrsoundhar 0:ae306d3f6076 348 This function returns the content of the Control Register.
mrsoundhar 0:ae306d3f6076 349
mrsoundhar 0:ae306d3f6076 350 \return Control Register value
mrsoundhar 0:ae306d3f6076 351 */
mrsoundhar 0:ae306d3f6076 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
mrsoundhar 0:ae306d3f6076 353 {
mrsoundhar 0:ae306d3f6076 354 uint32_t result;
mrsoundhar 0:ae306d3f6076 355
mrsoundhar 0:ae306d3f6076 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 357 return(result);
mrsoundhar 0:ae306d3f6076 358 }
mrsoundhar 0:ae306d3f6076 359
mrsoundhar 0:ae306d3f6076 360
mrsoundhar 0:ae306d3f6076 361 /** \brief Set Control Register
mrsoundhar 0:ae306d3f6076 362
mrsoundhar 0:ae306d3f6076 363 This function writes the given value to the Control Register.
mrsoundhar 0:ae306d3f6076 364
mrsoundhar 0:ae306d3f6076 365 \param [in] control Control Register value to set
mrsoundhar 0:ae306d3f6076 366 */
mrsoundhar 0:ae306d3f6076 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
mrsoundhar 0:ae306d3f6076 368 {
mrsoundhar 0:ae306d3f6076 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
mrsoundhar 0:ae306d3f6076 370 }
mrsoundhar 0:ae306d3f6076 371
mrsoundhar 0:ae306d3f6076 372
mrsoundhar 0:ae306d3f6076 373 /** \brief Get IPSR Register
mrsoundhar 0:ae306d3f6076 374
mrsoundhar 0:ae306d3f6076 375 This function returns the content of the IPSR Register.
mrsoundhar 0:ae306d3f6076 376
mrsoundhar 0:ae306d3f6076 377 \return IPSR Register value
mrsoundhar 0:ae306d3f6076 378 */
mrsoundhar 0:ae306d3f6076 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
mrsoundhar 0:ae306d3f6076 380 {
mrsoundhar 0:ae306d3f6076 381 uint32_t result;
mrsoundhar 0:ae306d3f6076 382
mrsoundhar 0:ae306d3f6076 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 384 return(result);
mrsoundhar 0:ae306d3f6076 385 }
mrsoundhar 0:ae306d3f6076 386
mrsoundhar 0:ae306d3f6076 387
mrsoundhar 0:ae306d3f6076 388 /** \brief Get APSR Register
mrsoundhar 0:ae306d3f6076 389
mrsoundhar 0:ae306d3f6076 390 This function returns the content of the APSR Register.
mrsoundhar 0:ae306d3f6076 391
mrsoundhar 0:ae306d3f6076 392 \return APSR Register value
mrsoundhar 0:ae306d3f6076 393 */
mrsoundhar 0:ae306d3f6076 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mrsoundhar 0:ae306d3f6076 395 {
mrsoundhar 0:ae306d3f6076 396 uint32_t result;
mrsoundhar 0:ae306d3f6076 397
mrsoundhar 0:ae306d3f6076 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 399 return(result);
mrsoundhar 0:ae306d3f6076 400 }
mrsoundhar 0:ae306d3f6076 401
mrsoundhar 0:ae306d3f6076 402
mrsoundhar 0:ae306d3f6076 403 /** \brief Get xPSR Register
mrsoundhar 0:ae306d3f6076 404
mrsoundhar 0:ae306d3f6076 405 This function returns the content of the xPSR Register.
mrsoundhar 0:ae306d3f6076 406
mrsoundhar 0:ae306d3f6076 407 \return xPSR Register value
mrsoundhar 0:ae306d3f6076 408 */
mrsoundhar 0:ae306d3f6076 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
mrsoundhar 0:ae306d3f6076 410 {
mrsoundhar 0:ae306d3f6076 411 uint32_t result;
mrsoundhar 0:ae306d3f6076 412
mrsoundhar 0:ae306d3f6076 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 414 return(result);
mrsoundhar 0:ae306d3f6076 415 }
mrsoundhar 0:ae306d3f6076 416
mrsoundhar 0:ae306d3f6076 417
mrsoundhar 0:ae306d3f6076 418 /** \brief Get Process Stack Pointer
mrsoundhar 0:ae306d3f6076 419
mrsoundhar 0:ae306d3f6076 420 This function returns the current value of the Process Stack Pointer (PSP).
mrsoundhar 0:ae306d3f6076 421
mrsoundhar 0:ae306d3f6076 422 \return PSP Register value
mrsoundhar 0:ae306d3f6076 423 */
mrsoundhar 0:ae306d3f6076 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
mrsoundhar 0:ae306d3f6076 425 {
mrsoundhar 0:ae306d3f6076 426 register uint32_t result;
mrsoundhar 0:ae306d3f6076 427
mrsoundhar 0:ae306d3f6076 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 429 return(result);
mrsoundhar 0:ae306d3f6076 430 }
mrsoundhar 0:ae306d3f6076 431
mrsoundhar 0:ae306d3f6076 432
mrsoundhar 0:ae306d3f6076 433 /** \brief Set Process Stack Pointer
mrsoundhar 0:ae306d3f6076 434
mrsoundhar 0:ae306d3f6076 435 This function assigns the given value to the Process Stack Pointer (PSP).
mrsoundhar 0:ae306d3f6076 436
mrsoundhar 0:ae306d3f6076 437 \param [in] topOfProcStack Process Stack Pointer value to set
mrsoundhar 0:ae306d3f6076 438 */
mrsoundhar 0:ae306d3f6076 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mrsoundhar 0:ae306d3f6076 440 {
mrsoundhar 0:ae306d3f6076 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
mrsoundhar 0:ae306d3f6076 442 }
mrsoundhar 0:ae306d3f6076 443
mrsoundhar 0:ae306d3f6076 444
mrsoundhar 0:ae306d3f6076 445 /** \brief Get Main Stack Pointer
mrsoundhar 0:ae306d3f6076 446
mrsoundhar 0:ae306d3f6076 447 This function returns the current value of the Main Stack Pointer (MSP).
mrsoundhar 0:ae306d3f6076 448
mrsoundhar 0:ae306d3f6076 449 \return MSP Register value
mrsoundhar 0:ae306d3f6076 450 */
mrsoundhar 0:ae306d3f6076 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
mrsoundhar 0:ae306d3f6076 452 {
mrsoundhar 0:ae306d3f6076 453 register uint32_t result;
mrsoundhar 0:ae306d3f6076 454
mrsoundhar 0:ae306d3f6076 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 456 return(result);
mrsoundhar 0:ae306d3f6076 457 }
mrsoundhar 0:ae306d3f6076 458
mrsoundhar 0:ae306d3f6076 459
mrsoundhar 0:ae306d3f6076 460 /** \brief Set Main Stack Pointer
mrsoundhar 0:ae306d3f6076 461
mrsoundhar 0:ae306d3f6076 462 This function assigns the given value to the Main Stack Pointer (MSP).
mrsoundhar 0:ae306d3f6076 463
mrsoundhar 0:ae306d3f6076 464 \param [in] topOfMainStack Main Stack Pointer value to set
mrsoundhar 0:ae306d3f6076 465 */
mrsoundhar 0:ae306d3f6076 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mrsoundhar 0:ae306d3f6076 467 {
mrsoundhar 0:ae306d3f6076 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
mrsoundhar 0:ae306d3f6076 469 }
mrsoundhar 0:ae306d3f6076 470
mrsoundhar 0:ae306d3f6076 471
mrsoundhar 0:ae306d3f6076 472 /** \brief Get Priority Mask
mrsoundhar 0:ae306d3f6076 473
mrsoundhar 0:ae306d3f6076 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
mrsoundhar 0:ae306d3f6076 475
mrsoundhar 0:ae306d3f6076 476 \return Priority Mask value
mrsoundhar 0:ae306d3f6076 477 */
mrsoundhar 0:ae306d3f6076 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
mrsoundhar 0:ae306d3f6076 479 {
mrsoundhar 0:ae306d3f6076 480 uint32_t result;
mrsoundhar 0:ae306d3f6076 481
mrsoundhar 0:ae306d3f6076 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 483 return(result);
mrsoundhar 0:ae306d3f6076 484 }
mrsoundhar 0:ae306d3f6076 485
mrsoundhar 0:ae306d3f6076 486
mrsoundhar 0:ae306d3f6076 487 /** \brief Set Priority Mask
mrsoundhar 0:ae306d3f6076 488
mrsoundhar 0:ae306d3f6076 489 This function assigns the given value to the Priority Mask Register.
mrsoundhar 0:ae306d3f6076 490
mrsoundhar 0:ae306d3f6076 491 \param [in] priMask Priority Mask
mrsoundhar 0:ae306d3f6076 492 */
mrsoundhar 0:ae306d3f6076 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mrsoundhar 0:ae306d3f6076 494 {
mrsoundhar 0:ae306d3f6076 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
mrsoundhar 0:ae306d3f6076 496 }
mrsoundhar 0:ae306d3f6076 497
mrsoundhar 0:ae306d3f6076 498
mrsoundhar 0:ae306d3f6076 499 #if (__CORTEX_M >= 0x03)
mrsoundhar 0:ae306d3f6076 500
mrsoundhar 0:ae306d3f6076 501 /** \brief Enable FIQ
mrsoundhar 0:ae306d3f6076 502
mrsoundhar 0:ae306d3f6076 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mrsoundhar 0:ae306d3f6076 504 Can only be executed in Privileged modes.
mrsoundhar 0:ae306d3f6076 505 */
mrsoundhar 0:ae306d3f6076 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
mrsoundhar 0:ae306d3f6076 507 {
mrsoundhar 0:ae306d3f6076 508 __ASM volatile ("cpsie f" : : : "memory");
mrsoundhar 0:ae306d3f6076 509 }
mrsoundhar 0:ae306d3f6076 510
mrsoundhar 0:ae306d3f6076 511
mrsoundhar 0:ae306d3f6076 512 /** \brief Disable FIQ
mrsoundhar 0:ae306d3f6076 513
mrsoundhar 0:ae306d3f6076 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mrsoundhar 0:ae306d3f6076 515 Can only be executed in Privileged modes.
mrsoundhar 0:ae306d3f6076 516 */
mrsoundhar 0:ae306d3f6076 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
mrsoundhar 0:ae306d3f6076 518 {
mrsoundhar 0:ae306d3f6076 519 __ASM volatile ("cpsid f" : : : "memory");
mrsoundhar 0:ae306d3f6076 520 }
mrsoundhar 0:ae306d3f6076 521
mrsoundhar 0:ae306d3f6076 522
mrsoundhar 0:ae306d3f6076 523 /** \brief Get Base Priority
mrsoundhar 0:ae306d3f6076 524
mrsoundhar 0:ae306d3f6076 525 This function returns the current value of the Base Priority register.
mrsoundhar 0:ae306d3f6076 526
mrsoundhar 0:ae306d3f6076 527 \return Base Priority register value
mrsoundhar 0:ae306d3f6076 528 */
mrsoundhar 0:ae306d3f6076 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
mrsoundhar 0:ae306d3f6076 530 {
mrsoundhar 0:ae306d3f6076 531 uint32_t result;
mrsoundhar 0:ae306d3f6076 532
mrsoundhar 0:ae306d3f6076 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 534 return(result);
mrsoundhar 0:ae306d3f6076 535 }
mrsoundhar 0:ae306d3f6076 536
mrsoundhar 0:ae306d3f6076 537
mrsoundhar 0:ae306d3f6076 538 /** \brief Set Base Priority
mrsoundhar 0:ae306d3f6076 539
mrsoundhar 0:ae306d3f6076 540 This function assigns the given value to the Base Priority register.
mrsoundhar 0:ae306d3f6076 541
mrsoundhar 0:ae306d3f6076 542 \param [in] basePri Base Priority value to set
mrsoundhar 0:ae306d3f6076 543 */
mrsoundhar 0:ae306d3f6076 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
mrsoundhar 0:ae306d3f6076 545 {
mrsoundhar 0:ae306d3f6076 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
mrsoundhar 0:ae306d3f6076 547 }
mrsoundhar 0:ae306d3f6076 548
mrsoundhar 0:ae306d3f6076 549
mrsoundhar 0:ae306d3f6076 550 /** \brief Get Fault Mask
mrsoundhar 0:ae306d3f6076 551
mrsoundhar 0:ae306d3f6076 552 This function returns the current value of the Fault Mask register.
mrsoundhar 0:ae306d3f6076 553
mrsoundhar 0:ae306d3f6076 554 \return Fault Mask register value
mrsoundhar 0:ae306d3f6076 555 */
mrsoundhar 0:ae306d3f6076 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mrsoundhar 0:ae306d3f6076 557 {
mrsoundhar 0:ae306d3f6076 558 uint32_t result;
mrsoundhar 0:ae306d3f6076 559
mrsoundhar 0:ae306d3f6076 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 561 return(result);
mrsoundhar 0:ae306d3f6076 562 }
mrsoundhar 0:ae306d3f6076 563
mrsoundhar 0:ae306d3f6076 564
mrsoundhar 0:ae306d3f6076 565 /** \brief Set Fault Mask
mrsoundhar 0:ae306d3f6076 566
mrsoundhar 0:ae306d3f6076 567 This function assigns the given value to the Fault Mask register.
mrsoundhar 0:ae306d3f6076 568
mrsoundhar 0:ae306d3f6076 569 \param [in] faultMask Fault Mask value to set
mrsoundhar 0:ae306d3f6076 570 */
mrsoundhar 0:ae306d3f6076 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mrsoundhar 0:ae306d3f6076 572 {
mrsoundhar 0:ae306d3f6076 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
mrsoundhar 0:ae306d3f6076 574 }
mrsoundhar 0:ae306d3f6076 575
mrsoundhar 0:ae306d3f6076 576 #endif /* (__CORTEX_M >= 0x03) */
mrsoundhar 0:ae306d3f6076 577
mrsoundhar 0:ae306d3f6076 578
mrsoundhar 0:ae306d3f6076 579 #if (__CORTEX_M == 0x04)
mrsoundhar 0:ae306d3f6076 580
mrsoundhar 0:ae306d3f6076 581 /** \brief Get FPSCR
mrsoundhar 0:ae306d3f6076 582
mrsoundhar 0:ae306d3f6076 583 This function returns the current value of the Floating Point Status/Control register.
mrsoundhar 0:ae306d3f6076 584
mrsoundhar 0:ae306d3f6076 585 \return Floating Point Status/Control register value
mrsoundhar 0:ae306d3f6076 586 */
mrsoundhar 0:ae306d3f6076 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mrsoundhar 0:ae306d3f6076 588 {
mrsoundhar 0:ae306d3f6076 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mrsoundhar 0:ae306d3f6076 590 uint32_t result;
mrsoundhar 0:ae306d3f6076 591
mrsoundhar 0:ae306d3f6076 592 /* Empty asm statement works as a scheduling barrier */
mrsoundhar 0:ae306d3f6076 593 __ASM volatile ("");
mrsoundhar 0:ae306d3f6076 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
mrsoundhar 0:ae306d3f6076 595 __ASM volatile ("");
mrsoundhar 0:ae306d3f6076 596 return(result);
mrsoundhar 0:ae306d3f6076 597 #else
mrsoundhar 0:ae306d3f6076 598 return(0);
mrsoundhar 0:ae306d3f6076 599 #endif
mrsoundhar 0:ae306d3f6076 600 }
mrsoundhar 0:ae306d3f6076 601
mrsoundhar 0:ae306d3f6076 602
mrsoundhar 0:ae306d3f6076 603 /** \brief Set FPSCR
mrsoundhar 0:ae306d3f6076 604
mrsoundhar 0:ae306d3f6076 605 This function assigns the given value to the Floating Point Status/Control register.
mrsoundhar 0:ae306d3f6076 606
mrsoundhar 0:ae306d3f6076 607 \param [in] fpscr Floating Point Status/Control value to set
mrsoundhar 0:ae306d3f6076 608 */
mrsoundhar 0:ae306d3f6076 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mrsoundhar 0:ae306d3f6076 610 {
mrsoundhar 0:ae306d3f6076 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mrsoundhar 0:ae306d3f6076 612 /* Empty asm statement works as a scheduling barrier */
mrsoundhar 0:ae306d3f6076 613 __ASM volatile ("");
mrsoundhar 0:ae306d3f6076 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
mrsoundhar 0:ae306d3f6076 615 __ASM volatile ("");
mrsoundhar 0:ae306d3f6076 616 #endif
mrsoundhar 0:ae306d3f6076 617 }
mrsoundhar 0:ae306d3f6076 618
mrsoundhar 0:ae306d3f6076 619 #endif /* (__CORTEX_M == 0x04) */
mrsoundhar 0:ae306d3f6076 620
mrsoundhar 0:ae306d3f6076 621
mrsoundhar 0:ae306d3f6076 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mrsoundhar 0:ae306d3f6076 623 /* TASKING carm specific functions */
mrsoundhar 0:ae306d3f6076 624
mrsoundhar 0:ae306d3f6076 625 /*
mrsoundhar 0:ae306d3f6076 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
mrsoundhar 0:ae306d3f6076 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
mrsoundhar 0:ae306d3f6076 628 * Including the CMSIS ones.
mrsoundhar 0:ae306d3f6076 629 */
mrsoundhar 0:ae306d3f6076 630
mrsoundhar 0:ae306d3f6076 631 #endif
mrsoundhar 0:ae306d3f6076 632
mrsoundhar 0:ae306d3f6076 633 /*@} end of CMSIS_Core_RegAccFunctions */
mrsoundhar 0:ae306d3f6076 634
mrsoundhar 0:ae306d3f6076 635
mrsoundhar 0:ae306d3f6076 636 #endif /* __CORE_CMFUNC_H */