fuyuno sakura / Mbed 2 deprecated OV7670_with_AL422B_QVGA_LCD_test

Dependencies:   mbed

ov7670reg.h@1:509676f3be32, 2012-02-17 (annotated)

Committer:
mio
Date:
Fri Feb 17 15:06:15 2012 +0000
Revision:
1:509676f3be32
Parent:
0:f3f80a0695ff 
Hflip Vflip init param support.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:f3f80a0695ff 1 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
mio 0:f3f80a0695ff 2 #define REG_BLUE 0x01 /* blue gain */
mio 0:f3f80a0695ff 3 #define REG_RED 0x02 /* red gain */
mio 0:f3f80a0695ff 4 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
mio 0:f3f80a0695ff 5 #define REG_COM1 0x04 /* Control 1 */
mio 0:f3f80a0695ff 6 #define COM1_CCIR656 0x40 /* CCIR656 enable */
mio 0:f3f80a0695ff 7 #define REG_BAVE 0x05 /* U/B Average level */
mio 0:f3f80a0695ff 8 #define REG_GbAVE 0x06 /* Y/Gb Average level */
mio 0:f3f80a0695ff 9 #define REG_AECHH 0x07 /* AEC MS 5 bits */
mio 0:f3f80a0695ff 10 #define REG_RAVE 0x08 /* V/R Average level */
mio 0:f3f80a0695ff 11 #define REG_COM2 0x09 /* Control 2 */
mio 0:f3f80a0695ff 12 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
mio 0:f3f80a0695ff 13 #define REG_PID 0x0a /* Product ID MSB */
mio 0:f3f80a0695ff 14 #define REG_VER 0x0b /* Product ID LSB */
mio 0:f3f80a0695ff 15 #define REG_COM3 0x0c /* Control 3 */
mio 0:f3f80a0695ff 16 #define COM3_SWAP 0x40 /* Byte swap */
mio 0:f3f80a0695ff 17 #define COM3_SCALEEN 0x08 /* Enable scaling */
mio 0:f3f80a0695ff 18 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
mio 0:f3f80a0695ff 19 #define REG_COM4 0x0d /* Control 4 */
mio 0:f3f80a0695ff 20 #define REG_COM5 0x0e /* All "reserved" */
mio 0:f3f80a0695ff 21 #define REG_COM6 0x0f /* Control 6 */
mio 0:f3f80a0695ff 22 #define REG_AECH 0x10 /* More bits of AEC value */
mio 0:f3f80a0695ff 23 #define REG_CLKRC 0x11 /* Clocl control */
mio 0:f3f80a0695ff 24 #define CLK_EXT 0x40 /* Use external clock directly */
mio 0:f3f80a0695ff 25 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
mio 0:f3f80a0695ff 26 #define REG_COM7 0x12 /* Control 7 */
mio 0:f3f80a0695ff 27 #define COM7_RESET 0x80 /* Register reset */
mio 0:f3f80a0695ff 28 #define COM7_FMT_MASK 0x38
mio 0:f3f80a0695ff 29 #define COM7_FMT_VGA 0x00
mio 0:f3f80a0695ff 30 #define COM7_FMT_CIF 0x20 /* CIF format */
mio 0:f3f80a0695ff 31 #define COM7_FMT_QVGA 0x10 /* QVGA format */
mio 0:f3f80a0695ff 32 #define COM7_FMT_QCIF 0x08 /* QCIF format */
mio 0:f3f80a0695ff 33 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
mio 0:f3f80a0695ff 34 #define COM7_YUV 0x00 /* YUV */
mio 0:f3f80a0695ff 35 #define COM7_BAYER 0x01 /* Bayer format */
mio 0:f3f80a0695ff 36 #define COM7_PBAYER 0x05 /* "Processed bayer" */
mio 0:f3f80a0695ff 37 #define REG_COM8 0x13 /* Control 8 */
mio 0:f3f80a0695ff 38 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
mio 0:f3f80a0695ff 39 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
mio 0:f3f80a0695ff 40 #define COM8_BFILT 0x20 /* Band filter enable */
mio 0:f3f80a0695ff 41 #define COM8_AGC 0x04 /* Auto gain enable */
mio 0:f3f80a0695ff 42 #define COM8_AWB 0x02 /* White balance enable */
mio 0:f3f80a0695ff 43 #define COM8_AEC 0x01 /* Auto exposure enable */
mio 0:f3f80a0695ff 44 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
mio 0:f3f80a0695ff 45 #define REG_COM10 0x15 /* Control 10 */
mio 0:f3f80a0695ff 46 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
mio 0:f3f80a0695ff 47 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
mio 0:f3f80a0695ff 48 #define COM10_HREF_REV 0x08 /* Reverse HREF */
mio 0:f3f80a0695ff 49 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
mio 0:f3f80a0695ff 50 #define COM10_VS_NEG 0x02 /* VSYNC negative */
mio 0:f3f80a0695ff 51 #define COM10_HS_NEG 0x01 /* HSYNC negative */
mio 0:f3f80a0695ff 52 #define REG_HSTART 0x17 /* Horiz start high bits */
mio 0:f3f80a0695ff 53 #define REG_HSTOP 0x18 /* Horiz stop high bits */
mio 0:f3f80a0695ff 54 #define REG_VSTART 0x19 /* Vert start high bits */
mio 0:f3f80a0695ff 55 #define REG_VSTOP 0x1a /* Vert stop high bits */
mio 0:f3f80a0695ff 56 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
mio 0:f3f80a0695ff 57 #define REG_MIDH 0x1c /* Manuf. ID high */
mio 0:f3f80a0695ff 58 #define REG_MIDL 0x1d /* Manuf. ID low */
mio 0:f3f80a0695ff 59 #define REG_MVFP 0x1e /* Mirror / vflip */
mio 0:f3f80a0695ff 60 #define MVFP_MIRROR 0x20 /* Mirror image */
mio 0:f3f80a0695ff 61 #define MVFP_FLIP 0x10 /* Vertical flip */
mio 0:f3f80a0695ff 62 #define REG_AEW 0x24 /* AGC upper limit */
mio 0:f3f80a0695ff 63 #define REG_AEB 0x25 /* AGC lower limit */
mio 0:f3f80a0695ff 64 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
mio 0:f3f80a0695ff 65 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
mio 0:f3f80a0695ff 66 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
mio 0:f3f80a0695ff 67 #define REG_HREF 0x32 /* HREF pieces */
mio 0:f3f80a0695ff 68 #define REG_TSLB 0x3a /* lots of stuff */
mio 0:f3f80a0695ff 69 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
mio 0:f3f80a0695ff 70 #define REG_COM11 0x3b /* Control 11 */
mio 0:f3f80a0695ff 71 #define COM11_NIGHT 0x80 /* NIght mode enable */
mio 0:f3f80a0695ff 72 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
mio 0:f3f80a0695ff 73 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
mio 0:f3f80a0695ff 74 #define COM11_50HZ 0x08 /* Manual 50Hz select */
mio 0:f3f80a0695ff 75 #define COM11_EXP 0x02
mio 0:f3f80a0695ff 76 #define REG_COM12 0x3c /* Control 12 */
mio 0:f3f80a0695ff 77 #define COM12_HREF 0x80 /* HREF always */
mio 0:f3f80a0695ff 78 #define REG_COM13 0x3d /* Control 13 */
mio 0:f3f80a0695ff 79 #define COM13_GAMMA 0x80 /* Gamma enable */
mio 0:f3f80a0695ff 80 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
mio 0:f3f80a0695ff 81 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
mio 0:f3f80a0695ff 82 #define REG_COM14 0x3e /* Control 14 */
mio 0:f3f80a0695ff 83 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
mio 0:f3f80a0695ff 84 #define REG_EDGE 0x3f /* Edge enhancement factor */
mio 0:f3f80a0695ff 85 #define REG_COM15 0x40 /* Control 15 */
mio 0:f3f80a0695ff 86 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
mio 0:f3f80a0695ff 87 #define COM15_R01FE 0x80 /* 01 to FE */
mio 0:f3f80a0695ff 88 #define COM15_R00FF 0xc0 /* 00 to FF */
mio 0:f3f80a0695ff 89 #define COM15_RGB565 0x10 /* RGB565 output */
mio 0:f3f80a0695ff 90 #define COM15_RGB555 0x30 /* RGB555 output */
mio 0:f3f80a0695ff 91 #define REG_COM16 0x41 /* Control 16 */
mio 0:f3f80a0695ff 92 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
mio 0:f3f80a0695ff 93 #define REG_COM17 0x42 /* Control 17 */
mio 0:f3f80a0695ff 94 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
mio 0:f3f80a0695ff 95 #define COM17_CBAR 0x08 /* DSP Color bar */
mio 0:f3f80a0695ff 96 #define REG_CMATRIX_BASE 0x4f
mio 0:f3f80a0695ff 97 #define CMATRIX_LEN 6
mio 0:f3f80a0695ff 98 #define REG_CMATRIX_SIGN 0x58
mio 0:f3f80a0695ff 99 #define REG_BRIGHT 0x55 /* Brightness */
mio 0:f3f80a0695ff 100 #define REG_CONTRAS 0x56 /* Contrast control */
mio 0:f3f80a0695ff 101 #define REG_GFIX 0x69 /* Fix gain control */
mio 0:f3f80a0695ff 102 #define REG_REG76 0x76 /* OV's name */
mio 0:f3f80a0695ff 103 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
mio 0:f3f80a0695ff 104 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
mio 0:f3f80a0695ff 105 #define REG_RGB444 0x8c /* RGB 444 control */
mio 0:f3f80a0695ff 106 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
mio 0:f3f80a0695ff 107 #define R444_RGBX 0x01 /* Empty nibble at end */
mio 0:f3f80a0695ff 108 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
mio 0:f3f80a0695ff 109 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
mio 0:f3f80a0695ff 110 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
mio 0:f3f80a0695ff 111 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
mio 0:f3f80a0695ff 112 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
mio 0:f3f80a0695ff 113 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
mio 0:f3f80a0695ff 114 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
mio 0:f3f80a0695ff 115 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
mio 0:f3f80a0695ff 116 #define REG_BD60MAX 0xab /* 60hz banding step limit */