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Diff: LPC1768/core_cmFunc.h
- Revision:
- 46:890817bdcffb
- Parent:
- 40:976df7c37ad5
--- a/LPC1768/core_cmFunc.h Thu Nov 22 16:04:31 2012 +0000 +++ b/LPC1768/core_cmFunc.h Mon Nov 26 10:13:56 2012 +0000 @@ -1,16 +1,16 @@ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V3.00 - * @date 09. December 2011 + * @version V3.02 + * @date 24. May 2012 * * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * Copyright (C) 2009-2012 ARM Limited. All rights reserved. * * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. * * @par * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED @@ -26,7 +26,7 @@ /* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface +/** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ @@ -47,7 +47,7 @@ \return Control Register value */ -static __INLINE uint32_t __get_CONTROL(void) +__STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); @@ -60,7 +60,7 @@ \param [in] control Control Register value to set */ -static __INLINE void __set_CONTROL(uint32_t control) +__STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; @@ -73,7 +73,7 @@ \return IPSR Register value */ -static __INLINE uint32_t __get_IPSR(void) +__STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); @@ -86,7 +86,7 @@ \return APSR Register value */ -static __INLINE uint32_t __get_APSR(void) +__STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); @@ -99,7 +99,7 @@ \return xPSR Register value */ -static __INLINE uint32_t __get_xPSR(void) +__STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); @@ -112,7 +112,7 @@ \return PSP Register value */ -static __INLINE uint32_t __get_PSP(void) +__STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); @@ -125,7 +125,7 @@ \param [in] topOfProcStack Process Stack Pointer value to set */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; @@ -138,7 +138,7 @@ \return MSP Register value */ -static __INLINE uint32_t __get_MSP(void) +__STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); @@ -151,7 +151,7 @@ \param [in] topOfMainStack Main Stack Pointer value to set */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; @@ -164,7 +164,7 @@ \return Priority Mask value */ -static __INLINE uint32_t __get_PRIMASK(void) +__STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); @@ -177,12 +177,12 @@ \param [in] priMask Priority Mask */ -static __INLINE void __set_PRIMASK(uint32_t priMask) +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } - + #if (__CORTEX_M >= 0x03) @@ -208,7 +208,7 @@ \return Base Priority register value */ -static __INLINE uint32_t __get_BASEPRI(void) +__STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); @@ -221,12 +221,12 @@ \param [in] basePri Base Priority value to set */ -static __INLINE void __set_BASEPRI(uint32_t basePri) +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } - + /** \brief Get Fault Mask @@ -234,7 +234,7 @@ \return Fault Mask register value */ -static __INLINE uint32_t __get_FAULTMASK(void) +__STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); @@ -247,7 +247,7 @@ \param [in] faultMask Fault Mask value to set */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1); @@ -264,7 +264,7 @@ \return Floating Point Status/Control register value */ -static __INLINE uint32_t __get_FPSCR(void) +__STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); @@ -281,7 +281,7 @@ \param [in] fpscr Floating Point Status/Control value to set */ -static __INLINE void __set_FPSCR(uint32_t fpscr) +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); @@ -297,6 +297,13 @@ #include <cmsis_iar.h> + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include <cmsis_ccs.h> + + #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ @@ -305,9 +312,9 @@ This function enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) { - __ASM volatile ("cpsie i"); + __ASM volatile ("cpsie i" : : : "memory"); } @@ -316,9 +323,9 @@ This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) { - __ASM volatile ("cpsid i"); + __ASM volatile ("cpsid i" : : : "memory"); } @@ -328,7 +335,7 @@ \return Control Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; @@ -343,7 +350,7 @@ \param [in] control Control Register value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) ); } @@ -355,7 +362,7 @@ \return IPSR Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; @@ -370,7 +377,7 @@ \return APSR Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; @@ -385,7 +392,7 @@ \return xPSR Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; @@ -400,14 +407,14 @@ \return PSP Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); return(result); } - + /** \brief Set Process Stack Pointer @@ -415,7 +422,7 @@ \param [in] topOfProcStack Process Stack Pointer value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); } @@ -427,14 +434,14 @@ \return MSP Register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); return(result); } - + /** \brief Set Main Stack Pointer @@ -442,7 +449,7 @@ \param [in] topOfMainStack Main Stack Pointer value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); } @@ -454,7 +461,7 @@ \return Priority Mask value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; @@ -469,11 +476,11 @@ \param [in] priMask Priority Mask */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); } - + #if (__CORTEX_M >= 0x03) @@ -482,9 +489,9 @@ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) { - __ASM volatile ("cpsie f"); + __ASM volatile ("cpsie f" : : : "memory"); } @@ -493,9 +500,9 @@ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) { - __ASM volatile ("cpsid f"); + __ASM volatile ("cpsid f" : : : "memory"); } @@ -505,10 +512,10 @@ \return Base Priority register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; - + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } @@ -520,7 +527,7 @@ \param [in] basePri Base Priority value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile ("MSR basepri, %0" : : "r" (value) ); } @@ -532,10 +539,10 @@ \return Fault Mask register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; - + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } @@ -547,7 +554,7 @@ \param [in] faultMask Fault Mask value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); } @@ -563,7 +570,7 @@ \return Floating Point Status/Control register value */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) uint32_t result; @@ -582,7 +589,7 @@ \param [in] fpscr Floating Point Status/Control value to set */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );