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TARGET_NUCLEO_F030R8/stm32f0xx_rcc.h@80:8e73be2a2ac1, 2014-02-21 (annotated)
- Committer:
- emilmont
- Date:
- Fri Feb 21 12:21:39 2014 +0000
- Revision:
- 80:8e73be2a2ac1
- Parent:
- 77:869cf507173a
- Child:
- 81:7d30d6019079
First alpha release for the NRF51822 target (to be tested in the online IDE)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 77:869cf507173a | 1 | /** |
| emilmont | 77:869cf507173a | 2 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 3 | * @file stm32f0xx_rcc.h |
| emilmont | 77:869cf507173a | 4 | * @author MCD Application Team |
| emilmont | 77:869cf507173a | 5 | * @version V1.3.0 |
| emilmont | 77:869cf507173a | 6 | * @date 16-January-2014 |
| emilmont | 77:869cf507173a | 7 | * @brief This file contains all the functions prototypes for the RCC |
| emilmont | 77:869cf507173a | 8 | * firmware library. |
| emilmont | 77:869cf507173a | 9 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 10 | * @attention |
| emilmont | 77:869cf507173a | 11 | * |
| emilmont | 77:869cf507173a | 12 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
| emilmont | 77:869cf507173a | 13 | * |
| emilmont | 77:869cf507173a | 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
| emilmont | 77:869cf507173a | 15 | * You may not use this file except in compliance with the License. |
| emilmont | 77:869cf507173a | 16 | * You may obtain a copy of the License at: |
| emilmont | 77:869cf507173a | 17 | * |
| emilmont | 77:869cf507173a | 18 | * http://www.st.com/software_license_agreement_liberty_v2 |
| emilmont | 77:869cf507173a | 19 | * |
| emilmont | 77:869cf507173a | 20 | * Unless required by applicable law or agreed to in writing, software |
| emilmont | 77:869cf507173a | 21 | * distributed under the License is distributed on an "AS IS" BASIS, |
| emilmont | 77:869cf507173a | 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| emilmont | 77:869cf507173a | 23 | * See the License for the specific language governing permissions and |
| emilmont | 77:869cf507173a | 24 | * limitations under the License. |
| emilmont | 77:869cf507173a | 25 | * |
| emilmont | 77:869cf507173a | 26 | ****************************************************************************** |
| emilmont | 77:869cf507173a | 27 | */ |
| emilmont | 77:869cf507173a | 28 | |
| emilmont | 77:869cf507173a | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| emilmont | 77:869cf507173a | 30 | #ifndef __STM32F0XX_RCC_H |
| emilmont | 77:869cf507173a | 31 | #define __STM32F0XX_RCC_H |
| emilmont | 77:869cf507173a | 32 | |
| emilmont | 77:869cf507173a | 33 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 34 | extern "C" { |
| emilmont | 77:869cf507173a | 35 | #endif |
| emilmont | 77:869cf507173a | 36 | |
| emilmont | 77:869cf507173a | 37 | /* Includes ------------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 38 | #include "stm32f0xx.h" |
| emilmont | 77:869cf507173a | 39 | |
| emilmont | 77:869cf507173a | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
| emilmont | 77:869cf507173a | 41 | * @{ |
| emilmont | 77:869cf507173a | 42 | */ |
| emilmont | 77:869cf507173a | 43 | |
| emilmont | 77:869cf507173a | 44 | /** @addtogroup RCC |
| emilmont | 77:869cf507173a | 45 | * @{ |
| emilmont | 77:869cf507173a | 46 | */ |
| emilmont | 77:869cf507173a | 47 | |
| emilmont | 77:869cf507173a | 48 | /* Exported types ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 49 | |
| emilmont | 77:869cf507173a | 50 | typedef struct |
| emilmont | 77:869cf507173a | 51 | { |
| emilmont | 77:869cf507173a | 52 | uint32_t SYSCLK_Frequency; |
| emilmont | 77:869cf507173a | 53 | uint32_t HCLK_Frequency; |
| emilmont | 77:869cf507173a | 54 | uint32_t PCLK_Frequency; |
| emilmont | 77:869cf507173a | 55 | uint32_t ADCCLK_Frequency; |
| emilmont | 77:869cf507173a | 56 | uint32_t CECCLK_Frequency; |
| emilmont | 77:869cf507173a | 57 | uint32_t I2C1CLK_Frequency; |
| emilmont | 77:869cf507173a | 58 | uint32_t USART1CLK_Frequency; |
| emilmont | 77:869cf507173a | 59 | uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 60 | uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 61 | }RCC_ClocksTypeDef; |
| emilmont | 77:869cf507173a | 62 | |
| emilmont | 77:869cf507173a | 63 | /* Exported constants --------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 64 | |
| emilmont | 77:869cf507173a | 65 | /** @defgroup RCC_Exported_Constants |
| emilmont | 77:869cf507173a | 66 | * @{ |
| emilmont | 77:869cf507173a | 67 | */ |
| emilmont | 77:869cf507173a | 68 | |
| emilmont | 77:869cf507173a | 69 | /** @defgroup RCC_HSE_configuration |
| emilmont | 77:869cf507173a | 70 | * @{ |
| emilmont | 77:869cf507173a | 71 | */ |
| emilmont | 77:869cf507173a | 72 | |
| emilmont | 77:869cf507173a | 73 | #define RCC_HSE_OFF ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 74 | #define RCC_HSE_ON ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 75 | #define RCC_HSE_Bypass ((uint8_t)0x05) |
| emilmont | 77:869cf507173a | 76 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| emilmont | 77:869cf507173a | 77 | ((HSE) == RCC_HSE_Bypass)) |
| emilmont | 77:869cf507173a | 78 | |
| emilmont | 77:869cf507173a | 79 | /** |
| emilmont | 77:869cf507173a | 80 | * @} |
| emilmont | 77:869cf507173a | 81 | */ |
| emilmont | 77:869cf507173a | 82 | |
| emilmont | 77:869cf507173a | 83 | /** @defgroup RCC_PLL_Clock_Source |
| emilmont | 77:869cf507173a | 84 | * @{ |
| emilmont | 77:869cf507173a | 85 | */ |
| emilmont | 77:869cf507173a | 86 | |
| emilmont | 77:869cf507173a | 87 | #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 |
| emilmont | 77:869cf507173a | 88 | #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */ |
| emilmont | 77:869cf507173a | 89 | #define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 90 | #define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 91 | #define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 92 | |
| emilmont | 77:869cf507173a | 93 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
| emilmont | 77:869cf507173a | 94 | ((SOURCE) == RCC_PLLSource_HSI48) || \ |
| emilmont | 77:869cf507173a | 95 | ((SOURCE) == RCC_PLLSource_HSI) || \ |
| emilmont | 77:869cf507173a | 96 | ((SOURCE) == RCC_PLLSource_HSE) || \ |
| emilmont | 77:869cf507173a | 97 | ((SOURCE) == RCC_PLLSource_PREDIV1)) |
| emilmont | 77:869cf507173a | 98 | /** |
| emilmont | 77:869cf507173a | 99 | * @} |
| emilmont | 77:869cf507173a | 100 | */ |
| emilmont | 77:869cf507173a | 101 | |
| emilmont | 77:869cf507173a | 102 | /** @defgroup RCC_PLL_Multiplication_Factor |
| emilmont | 77:869cf507173a | 103 | * @{ |
| emilmont | 77:869cf507173a | 104 | */ |
| emilmont | 77:869cf507173a | 105 | |
| emilmont | 77:869cf507173a | 106 | #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 |
| emilmont | 77:869cf507173a | 107 | #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 |
| emilmont | 77:869cf507173a | 108 | #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 |
| emilmont | 77:869cf507173a | 109 | #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 |
| emilmont | 77:869cf507173a | 110 | #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 |
| emilmont | 77:869cf507173a | 111 | #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 |
| emilmont | 77:869cf507173a | 112 | #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 |
| emilmont | 77:869cf507173a | 113 | #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 |
| emilmont | 77:869cf507173a | 114 | #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 |
| emilmont | 77:869cf507173a | 115 | #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 |
| emilmont | 77:869cf507173a | 116 | #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 |
| emilmont | 77:869cf507173a | 117 | #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 |
| emilmont | 77:869cf507173a | 118 | #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 |
| emilmont | 77:869cf507173a | 119 | #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 |
| emilmont | 77:869cf507173a | 120 | #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 |
| emilmont | 77:869cf507173a | 121 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ |
| emilmont | 77:869cf507173a | 122 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
| emilmont | 77:869cf507173a | 123 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
| emilmont | 77:869cf507173a | 124 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
| emilmont | 77:869cf507173a | 125 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ |
| emilmont | 77:869cf507173a | 126 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ |
| emilmont | 77:869cf507173a | 127 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ |
| emilmont | 77:869cf507173a | 128 | ((MUL) == RCC_PLLMul_16)) |
| emilmont | 77:869cf507173a | 129 | /** |
| emilmont | 77:869cf507173a | 130 | * @} |
| emilmont | 77:869cf507173a | 131 | */ |
| emilmont | 77:869cf507173a | 132 | |
| emilmont | 77:869cf507173a | 133 | /** @defgroup RCC_PREDIV1_division_factor |
| emilmont | 77:869cf507173a | 134 | * @{ |
| emilmont | 77:869cf507173a | 135 | */ |
| emilmont | 77:869cf507173a | 136 | #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 |
| emilmont | 77:869cf507173a | 137 | #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 |
| emilmont | 77:869cf507173a | 138 | #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 |
| emilmont | 77:869cf507173a | 139 | #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 |
| emilmont | 77:869cf507173a | 140 | #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 |
| emilmont | 77:869cf507173a | 141 | #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 |
| emilmont | 77:869cf507173a | 142 | #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 |
| emilmont | 77:869cf507173a | 143 | #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 |
| emilmont | 77:869cf507173a | 144 | #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 |
| emilmont | 77:869cf507173a | 145 | #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 |
| emilmont | 77:869cf507173a | 146 | #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 |
| emilmont | 77:869cf507173a | 147 | #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 |
| emilmont | 77:869cf507173a | 148 | #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 |
| emilmont | 77:869cf507173a | 149 | #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 |
| emilmont | 77:869cf507173a | 150 | #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 |
| emilmont | 77:869cf507173a | 151 | #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 |
| emilmont | 77:869cf507173a | 152 | |
| emilmont | 77:869cf507173a | 153 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ |
| emilmont | 77:869cf507173a | 154 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ |
| emilmont | 77:869cf507173a | 155 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ |
| emilmont | 77:869cf507173a | 156 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ |
| emilmont | 77:869cf507173a | 157 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ |
| emilmont | 77:869cf507173a | 158 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ |
| emilmont | 77:869cf507173a | 159 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ |
| emilmont | 77:869cf507173a | 160 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) |
| emilmont | 77:869cf507173a | 161 | /** |
| emilmont | 77:869cf507173a | 162 | * @} |
| emilmont | 77:869cf507173a | 163 | */ |
| emilmont | 77:869cf507173a | 164 | |
| emilmont | 77:869cf507173a | 165 | /** @defgroup RCC_System_Clock_Source |
| emilmont | 77:869cf507173a | 166 | * @{ |
| emilmont | 77:869cf507173a | 167 | */ |
| emilmont | 77:869cf507173a | 168 | |
| emilmont | 77:869cf507173a | 169 | #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI |
| emilmont | 77:869cf507173a | 170 | #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE |
| emilmont | 77:869cf507173a | 171 | #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL |
| emilmont | 77:869cf507173a | 172 | #define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 173 | |
| emilmont | 77:869cf507173a | 174 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
| emilmont | 77:869cf507173a | 175 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
| emilmont | 77:869cf507173a | 176 | ((SOURCE) == RCC_SYSCLKSource_HSI48) || \ |
| emilmont | 77:869cf507173a | 177 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
| emilmont | 77:869cf507173a | 178 | /** |
| emilmont | 77:869cf507173a | 179 | * @} |
| emilmont | 77:869cf507173a | 180 | */ |
| emilmont | 77:869cf507173a | 181 | |
| emilmont | 77:869cf507173a | 182 | /** @defgroup RCC_AHB_Clock_Source |
| emilmont | 77:869cf507173a | 183 | * @{ |
| emilmont | 77:869cf507173a | 184 | */ |
| emilmont | 77:869cf507173a | 185 | |
| emilmont | 77:869cf507173a | 186 | #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 |
| emilmont | 77:869cf507173a | 187 | #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 |
| emilmont | 77:869cf507173a | 188 | #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 |
| emilmont | 77:869cf507173a | 189 | #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 |
| emilmont | 77:869cf507173a | 190 | #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 |
| emilmont | 77:869cf507173a | 191 | #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 |
| emilmont | 77:869cf507173a | 192 | #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 |
| emilmont | 77:869cf507173a | 193 | #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 |
| emilmont | 77:869cf507173a | 194 | #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 |
| emilmont | 77:869cf507173a | 195 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
| emilmont | 77:869cf507173a | 196 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
| emilmont | 77:869cf507173a | 197 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
| emilmont | 77:869cf507173a | 198 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
| emilmont | 77:869cf507173a | 199 | ((HCLK) == RCC_SYSCLK_Div512)) |
| emilmont | 77:869cf507173a | 200 | /** |
| emilmont | 77:869cf507173a | 201 | * @} |
| emilmont | 77:869cf507173a | 202 | */ |
| emilmont | 77:869cf507173a | 203 | |
| emilmont | 77:869cf507173a | 204 | /** @defgroup RCC_APB_Clock_Source |
| emilmont | 77:869cf507173a | 205 | * @{ |
| emilmont | 77:869cf507173a | 206 | */ |
| emilmont | 77:869cf507173a | 207 | |
| emilmont | 77:869cf507173a | 208 | #define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 |
| emilmont | 77:869cf507173a | 209 | #define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 |
| emilmont | 77:869cf507173a | 210 | #define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 |
| emilmont | 77:869cf507173a | 211 | #define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 |
| emilmont | 77:869cf507173a | 212 | #define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 |
| emilmont | 77:869cf507173a | 213 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
| emilmont | 77:869cf507173a | 214 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
| emilmont | 77:869cf507173a | 215 | ((PCLK) == RCC_HCLK_Div16)) |
| emilmont | 77:869cf507173a | 216 | /** |
| emilmont | 77:869cf507173a | 217 | * @} |
| emilmont | 77:869cf507173a | 218 | */ |
| emilmont | 77:869cf507173a | 219 | |
| emilmont | 77:869cf507173a | 220 | /** @defgroup RCC_ADC_clock_source |
| emilmont | 77:869cf507173a | 221 | * @{ |
| emilmont | 77:869cf507173a | 222 | */ |
| emilmont | 77:869cf507173a | 223 | /* These defines are obsolete and kept for legacy purpose only. |
| emilmont | 77:869cf507173a | 224 | Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ |
| emilmont | 77:869cf507173a | 225 | #define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 226 | #define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) |
| emilmont | 77:869cf507173a | 227 | #define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) |
| emilmont | 77:869cf507173a | 228 | |
| emilmont | 77:869cf507173a | 229 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ |
| emilmont | 77:869cf507173a | 230 | ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) |
| emilmont | 77:869cf507173a | 231 | |
| emilmont | 77:869cf507173a | 232 | /** |
| emilmont | 77:869cf507173a | 233 | * @} |
| emilmont | 77:869cf507173a | 234 | */ |
| emilmont | 77:869cf507173a | 235 | |
| emilmont | 77:869cf507173a | 236 | /** @defgroup RCC_CEC_clock_source |
| emilmont | 77:869cf507173a | 237 | * @{ |
| emilmont | 77:869cf507173a | 238 | */ |
| emilmont | 77:869cf507173a | 239 | |
| emilmont | 77:869cf507173a | 240 | #define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 241 | #define RCC_CECCLK_LSE RCC_CFGR3_CECSW |
| emilmont | 77:869cf507173a | 242 | |
| emilmont | 77:869cf507173a | 243 | #define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE)) |
| emilmont | 77:869cf507173a | 244 | |
| emilmont | 77:869cf507173a | 245 | /** |
| emilmont | 77:869cf507173a | 246 | * @} |
| emilmont | 77:869cf507173a | 247 | */ |
| emilmont | 77:869cf507173a | 248 | |
| emilmont | 77:869cf507173a | 249 | /** @defgroup RCC_I2C_clock_source |
| emilmont | 77:869cf507173a | 250 | * @{ |
| emilmont | 77:869cf507173a | 251 | */ |
| emilmont | 77:869cf507173a | 252 | |
| emilmont | 77:869cf507173a | 253 | #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 254 | #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW |
| emilmont | 77:869cf507173a | 255 | |
| emilmont | 77:869cf507173a | 256 | #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) |
| emilmont | 77:869cf507173a | 257 | |
| emilmont | 77:869cf507173a | 258 | /** |
| emilmont | 77:869cf507173a | 259 | * @} |
| emilmont | 77:869cf507173a | 260 | */ |
| emilmont | 77:869cf507173a | 261 | |
| emilmont | 77:869cf507173a | 262 | /** @defgroup RCC_USB_clock_source |
| emilmont | 77:869cf507173a | 263 | * @brief Applicable only for STM32F072 devices |
| emilmont | 77:869cf507173a | 264 | * @{ |
| emilmont | 77:869cf507173a | 265 | */ |
| emilmont | 77:869cf507173a | 266 | |
| emilmont | 77:869cf507173a | 267 | #define RCC_USBCLK_HSI48 ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 268 | #define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW |
| emilmont | 77:869cf507173a | 269 | |
| emilmont | 77:869cf507173a | 270 | #define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK)) |
| emilmont | 77:869cf507173a | 271 | |
| emilmont | 77:869cf507173a | 272 | /** |
| emilmont | 77:869cf507173a | 273 | * @} |
| emilmont | 77:869cf507173a | 274 | */ |
| emilmont | 77:869cf507173a | 275 | |
| emilmont | 77:869cf507173a | 276 | /** @defgroup RCC_USART_clock_source |
| emilmont | 77:869cf507173a | 277 | * @{ |
| emilmont | 77:869cf507173a | 278 | */ |
| emilmont | 77:869cf507173a | 279 | |
| emilmont | 77:869cf507173a | 280 | #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) |
| emilmont | 77:869cf507173a | 281 | #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) |
| emilmont | 77:869cf507173a | 282 | #define RCC_USART1CLK_LSE ((uint32_t)0x10000002) |
| emilmont | 77:869cf507173a | 283 | #define RCC_USART1CLK_HSI ((uint32_t)0x10000003) |
| emilmont | 77:869cf507173a | 284 | |
| emilmont | 77:869cf507173a | 285 | #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 286 | #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 287 | #define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 288 | #define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 289 | |
| emilmont | 77:869cf507173a | 290 | #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \ |
| emilmont | 77:869cf507173a | 291 | ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ |
| emilmont | 77:869cf507173a | 292 | ((USARTCLK) == RCC_USART1CLK_LSE) || \ |
| emilmont | 77:869cf507173a | 293 | ((USARTCLK) == RCC_USART1CLK_HSI) || \ |
| emilmont | 77:869cf507173a | 294 | ((USARTCLK) == RCC_USART2CLK_PCLK) || \ |
| emilmont | 77:869cf507173a | 295 | ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ |
| emilmont | 77:869cf507173a | 296 | ((USARTCLK) == RCC_USART2CLK_LSE) || \ |
| emilmont | 77:869cf507173a | 297 | ((USARTCLK) == RCC_USART2CLK_HSI)) |
| emilmont | 77:869cf507173a | 298 | |
| emilmont | 77:869cf507173a | 299 | /** |
| emilmont | 77:869cf507173a | 300 | * @} |
| emilmont | 77:869cf507173a | 301 | */ |
| emilmont | 77:869cf507173a | 302 | |
| emilmont | 77:869cf507173a | 303 | /** @defgroup RCC_Interrupt_Source |
| emilmont | 77:869cf507173a | 304 | * @{ |
| emilmont | 77:869cf507173a | 305 | */ |
| emilmont | 77:869cf507173a | 306 | |
| emilmont | 77:869cf507173a | 307 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 308 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
| emilmont | 77:869cf507173a | 309 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
| emilmont | 77:869cf507173a | 310 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
| emilmont | 77:869cf507173a | 311 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
| emilmont | 77:869cf507173a | 312 | #define RCC_IT_HSI14RDY ((uint8_t)0x20) |
| emilmont | 77:869cf507173a | 313 | #define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 314 | #define RCC_IT_CSS ((uint8_t)0x80) |
| emilmont | 77:869cf507173a | 315 | |
| emilmont | 77:869cf507173a | 316 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) |
| emilmont | 77:869cf507173a | 317 | |
| emilmont | 77:869cf507173a | 318 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| emilmont | 77:869cf507173a | 319 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| emilmont | 77:869cf507173a | 320 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ |
| emilmont | 77:869cf507173a | 321 | ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY)) |
| emilmont | 77:869cf507173a | 322 | |
| emilmont | 77:869cf507173a | 323 | #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) |
| emilmont | 77:869cf507173a | 324 | |
| emilmont | 77:869cf507173a | 325 | /** |
| emilmont | 77:869cf507173a | 326 | * @} |
| emilmont | 77:869cf507173a | 327 | */ |
| emilmont | 77:869cf507173a | 328 | |
| emilmont | 77:869cf507173a | 329 | /** @defgroup RCC_LSE_Configuration |
| emilmont | 77:869cf507173a | 330 | * @{ |
| emilmont | 77:869cf507173a | 331 | */ |
| emilmont | 77:869cf507173a | 332 | |
| emilmont | 77:869cf507173a | 333 | #define RCC_LSE_OFF ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 334 | #define RCC_LSE_ON RCC_BDCR_LSEON |
| emilmont | 77:869cf507173a | 335 | #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) |
| emilmont | 77:869cf507173a | 336 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| emilmont | 77:869cf507173a | 337 | ((LSE) == RCC_LSE_Bypass)) |
| emilmont | 77:869cf507173a | 338 | /** |
| emilmont | 77:869cf507173a | 339 | * @} |
| emilmont | 77:869cf507173a | 340 | */ |
| emilmont | 77:869cf507173a | 341 | |
| emilmont | 77:869cf507173a | 342 | /** @defgroup RCC_RTC_Clock_Source |
| emilmont | 77:869cf507173a | 343 | * @{ |
| emilmont | 77:869cf507173a | 344 | */ |
| emilmont | 77:869cf507173a | 345 | |
| emilmont | 77:869cf507173a | 346 | #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE |
| emilmont | 77:869cf507173a | 347 | #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI |
| emilmont | 77:869cf507173a | 348 | #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE |
| emilmont | 77:869cf507173a | 349 | |
| emilmont | 77:869cf507173a | 350 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
| emilmont | 77:869cf507173a | 351 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
| emilmont | 77:869cf507173a | 352 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) |
| emilmont | 77:869cf507173a | 353 | /** |
| emilmont | 77:869cf507173a | 354 | * @} |
| emilmont | 77:869cf507173a | 355 | */ |
| emilmont | 77:869cf507173a | 356 | |
| emilmont | 77:869cf507173a | 357 | /** @defgroup RCC_LSE_Drive_Configuration |
| emilmont | 77:869cf507173a | 358 | * @{ |
| emilmont | 77:869cf507173a | 359 | */ |
| emilmont | 77:869cf507173a | 360 | |
| emilmont | 77:869cf507173a | 361 | #define RCC_LSEDrive_Low ((uint32_t)0x00000000) |
| emilmont | 77:869cf507173a | 362 | #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 |
| emilmont | 77:869cf507173a | 363 | #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 |
| emilmont | 77:869cf507173a | 364 | #define RCC_LSEDrive_High RCC_BDCR_LSEDRV |
| emilmont | 77:869cf507173a | 365 | #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ |
| emilmont | 77:869cf507173a | 366 | ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) |
| emilmont | 77:869cf507173a | 367 | /** |
| emilmont | 77:869cf507173a | 368 | * @} |
| emilmont | 77:869cf507173a | 369 | */ |
| emilmont | 77:869cf507173a | 370 | |
| emilmont | 77:869cf507173a | 371 | /** @defgroup RCC_AHB_Peripherals |
| emilmont | 77:869cf507173a | 372 | * @{ |
| emilmont | 77:869cf507173a | 373 | */ |
| emilmont | 77:869cf507173a | 374 | |
| emilmont | 77:869cf507173a | 375 | #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN |
| emilmont | 77:869cf507173a | 376 | #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN |
| emilmont | 77:869cf507173a | 377 | #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN |
| emilmont | 77:869cf507173a | 378 | #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN |
| emilmont | 77:869cf507173a | 379 | #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 380 | #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN |
| emilmont | 77:869cf507173a | 381 | #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN |
| emilmont | 77:869cf507173a | 382 | #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN |
| emilmont | 77:869cf507173a | 383 | #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN |
| emilmont | 77:869cf507173a | 384 | #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN |
| emilmont | 77:869cf507173a | 385 | #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN |
| emilmont | 77:869cf507173a | 386 | |
| emilmont | 77:869cf507173a | 387 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFAA) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 388 | #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFFF) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 389 | |
| emilmont | 77:869cf507173a | 390 | /** |
| emilmont | 77:869cf507173a | 391 | * @} |
| emilmont | 77:869cf507173a | 392 | */ |
| emilmont | 77:869cf507173a | 393 | |
| emilmont | 77:869cf507173a | 394 | /** @defgroup RCC_APB2_Peripherals |
| emilmont | 77:869cf507173a | 395 | * @{ |
| emilmont | 77:869cf507173a | 396 | */ |
| emilmont | 77:869cf507173a | 397 | |
| emilmont | 77:869cf507173a | 398 | #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN |
| emilmont | 77:869cf507173a | 399 | #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN |
| emilmont | 77:869cf507173a | 400 | #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN |
| emilmont | 77:869cf507173a | 401 | #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN |
| emilmont | 77:869cf507173a | 402 | #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN |
| emilmont | 77:869cf507173a | 403 | #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN |
| emilmont | 77:869cf507173a | 404 | #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN |
| emilmont | 77:869cf507173a | 405 | #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN |
| emilmont | 77:869cf507173a | 406 | #define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN |
| emilmont | 77:869cf507173a | 407 | |
| emilmont | 77:869cf507173a | 408 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 409 | |
| emilmont | 77:869cf507173a | 410 | /** |
| emilmont | 77:869cf507173a | 411 | * @} |
| emilmont | 77:869cf507173a | 412 | */ |
| emilmont | 77:869cf507173a | 413 | |
| emilmont | 77:869cf507173a | 414 | /** @defgroup RCC_APB1_Peripherals |
| emilmont | 77:869cf507173a | 415 | * @{ |
| emilmont | 77:869cf507173a | 416 | */ |
| emilmont | 77:869cf507173a | 417 | |
| emilmont | 77:869cf507173a | 418 | #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051 and STM32F072 devices */ |
| emilmont | 77:869cf507173a | 419 | #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN |
| emilmont | 77:869cf507173a | 420 | #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN |
| emilmont | 77:869cf507173a | 421 | #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 422 | #define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN |
| emilmont | 77:869cf507173a | 423 | #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN |
| emilmont | 77:869cf507173a | 424 | #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN |
| emilmont | 77:869cf507173a | 425 | #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN |
| emilmont | 77:869cf507173a | 426 | #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 427 | #define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 428 | #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN |
| emilmont | 77:869cf507173a | 429 | #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN |
| emilmont | 77:869cf507173a | 430 | #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */ |
| emilmont | 77:869cf507173a | 431 | #define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072 and STM32F042 devices */ |
| emilmont | 77:869cf507173a | 432 | #define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072 and STM32F042 devices*/ |
| emilmont | 77:869cf507173a | 433 | #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN |
| emilmont | 77:869cf507173a | 434 | #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051 and STM32F072 devices */ |
| emilmont | 77:869cf507173a | 435 | #define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042 and STM32F072 devices */ |
| emilmont | 77:869cf507173a | 436 | |
| emilmont | 77:869cf507173a | 437 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8511B6CC) == 0x00) && ((PERIPH) != 0x00)) |
| emilmont | 77:869cf507173a | 438 | /** |
| emilmont | 77:869cf507173a | 439 | * @} |
| emilmont | 77:869cf507173a | 440 | */ |
| emilmont | 77:869cf507173a | 441 | |
| emilmont | 77:869cf507173a | 442 | /** @defgroup RCC_MCO_Clock_Source |
| emilmont | 77:869cf507173a | 443 | * @{ |
| emilmont | 77:869cf507173a | 444 | */ |
| emilmont | 77:869cf507173a | 445 | |
| emilmont | 77:869cf507173a | 446 | #define RCC_MCOSource_NoClock ((uint8_t)0x00) |
| emilmont | 77:869cf507173a | 447 | #define RCC_MCOSource_HSI14 ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 448 | #define RCC_MCOSource_LSI ((uint8_t)0x02) |
| emilmont | 77:869cf507173a | 449 | #define RCC_MCOSource_LSE ((uint8_t)0x03) |
| emilmont | 77:869cf507173a | 450 | #define RCC_MCOSource_SYSCLK ((uint8_t)0x04) |
| emilmont | 77:869cf507173a | 451 | #define RCC_MCOSource_HSI ((uint8_t)0x05) |
| emilmont | 77:869cf507173a | 452 | #define RCC_MCOSource_HSE ((uint8_t)0x06) |
| emilmont | 77:869cf507173a | 453 | #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) |
| emilmont | 77:869cf507173a | 454 | #define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 455 | #define RCC_MCOSource_PLLCLK ((uint8_t)0x87) |
| emilmont | 77:869cf507173a | 456 | |
| emilmont | 77:869cf507173a | 457 | #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ |
| emilmont | 77:869cf507173a | 458 | ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ |
| emilmont | 77:869cf507173a | 459 | ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ |
| emilmont | 77:869cf507173a | 460 | ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \ |
| emilmont | 77:869cf507173a | 461 | ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE)) |
| emilmont | 77:869cf507173a | 462 | /** |
| emilmont | 77:869cf507173a | 463 | * @} |
| emilmont | 77:869cf507173a | 464 | */ |
| emilmont | 77:869cf507173a | 465 | |
| emilmont | 77:869cf507173a | 466 | /** @defgroup RCC_MCOPrescaler |
| emilmont | 77:869cf507173a | 467 | * @{ |
| emilmont | 77:869cf507173a | 468 | */ |
| emilmont | 77:869cf507173a | 469 | #if !defined (STM32F051) |
| emilmont | 77:869cf507173a | 470 | #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 |
| emilmont | 77:869cf507173a | 471 | #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 |
| emilmont | 77:869cf507173a | 472 | #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 |
| emilmont | 77:869cf507173a | 473 | #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 |
| emilmont | 77:869cf507173a | 474 | #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 |
| emilmont | 77:869cf507173a | 475 | #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 |
| emilmont | 77:869cf507173a | 476 | #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 |
| emilmont | 77:869cf507173a | 477 | #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 |
| emilmont | 77:869cf507173a | 478 | |
| emilmont | 77:869cf507173a | 479 | #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ |
| emilmont | 77:869cf507173a | 480 | ((PRESCALER) == RCC_MCOPrescaler_2) || \ |
| emilmont | 77:869cf507173a | 481 | ((PRESCALER) == RCC_MCOPrescaler_4) || \ |
| emilmont | 77:869cf507173a | 482 | ((PRESCALER) == RCC_MCOPrescaler_8) || \ |
| emilmont | 77:869cf507173a | 483 | ((PRESCALER) == RCC_MCOPrescaler_16) || \ |
| emilmont | 77:869cf507173a | 484 | ((PRESCALER) == RCC_MCOPrescaler_32) || \ |
| emilmont | 77:869cf507173a | 485 | ((PRESCALER) == RCC_MCOPrescaler_64) || \ |
| emilmont | 77:869cf507173a | 486 | ((PRESCALER) == RCC_MCOPrescaler_128)) |
| emilmont | 77:869cf507173a | 487 | #endif /* STM32F051 */ |
| emilmont | 77:869cf507173a | 488 | /** |
| emilmont | 77:869cf507173a | 489 | * @} |
| emilmont | 77:869cf507173a | 490 | */ |
| emilmont | 77:869cf507173a | 491 | |
| emilmont | 77:869cf507173a | 492 | /** @defgroup RCC_Flag |
| emilmont | 77:869cf507173a | 493 | * @{ |
| emilmont | 77:869cf507173a | 494 | */ |
| emilmont | 77:869cf507173a | 495 | #define RCC_FLAG_HSIRDY ((uint8_t)0x01) |
| emilmont | 77:869cf507173a | 496 | #define RCC_FLAG_HSERDY ((uint8_t)0x11) |
| emilmont | 77:869cf507173a | 497 | #define RCC_FLAG_PLLRDY ((uint8_t)0x19) |
| emilmont | 77:869cf507173a | 498 | #define RCC_FLAG_LSERDY ((uint8_t)0x21) |
| emilmont | 77:869cf507173a | 499 | #define RCC_FLAG_LSIRDY ((uint8_t)0x41) |
| emilmont | 77:869cf507173a | 500 | #define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) |
| emilmont | 77:869cf507173a | 501 | #define RCC_FLAG_OBLRST ((uint8_t)0x59) |
| emilmont | 77:869cf507173a | 502 | #define RCC_FLAG_PINRST ((uint8_t)0x5A) |
| emilmont | 77:869cf507173a | 503 | #define RCC_FLAG_PORRST ((uint8_t)0x5B) |
| emilmont | 77:869cf507173a | 504 | #define RCC_FLAG_SFTRST ((uint8_t)0x5C) |
| emilmont | 77:869cf507173a | 505 | #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) |
| emilmont | 77:869cf507173a | 506 | #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) |
| emilmont | 77:869cf507173a | 507 | #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) |
| emilmont | 77:869cf507173a | 508 | #define RCC_FLAG_HSI14RDY ((uint8_t)0x61) |
| emilmont | 77:869cf507173a | 509 | #define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 510 | |
| emilmont | 77:869cf507173a | 511 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| emilmont | 77:869cf507173a | 512 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| emilmont | 77:869cf507173a | 513 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ |
| emilmont | 77:869cf507173a | 514 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ |
| emilmont | 77:869cf507173a | 515 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \ |
| emilmont | 77:869cf507173a | 516 | ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \ |
| emilmont | 77:869cf507173a | 517 | ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \ |
| emilmont | 77:869cf507173a | 518 | ((FLAG) == RCC_FLAG_V18PWRRSTF)) |
| emilmont | 77:869cf507173a | 519 | |
| emilmont | 77:869cf507173a | 520 | #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| emilmont | 77:869cf507173a | 521 | #define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| emilmont | 77:869cf507173a | 522 | |
| emilmont | 77:869cf507173a | 523 | /** |
| emilmont | 77:869cf507173a | 524 | * @} |
| emilmont | 77:869cf507173a | 525 | */ |
| emilmont | 77:869cf507173a | 526 | |
| emilmont | 77:869cf507173a | 527 | /** |
| emilmont | 77:869cf507173a | 528 | * @} |
| emilmont | 77:869cf507173a | 529 | */ |
| emilmont | 77:869cf507173a | 530 | |
| emilmont | 77:869cf507173a | 531 | /* Exported macro ------------------------------------------------------------*/ |
| emilmont | 77:869cf507173a | 532 | /* Exported functions ------------------------------------------------------- */ |
| emilmont | 77:869cf507173a | 533 | |
| emilmont | 77:869cf507173a | 534 | /* Function used to set the RCC clock configuration to the default reset state */ |
| emilmont | 77:869cf507173a | 535 | void RCC_DeInit(void); |
| emilmont | 77:869cf507173a | 536 | |
| emilmont | 77:869cf507173a | 537 | /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ |
| emilmont | 77:869cf507173a | 538 | void RCC_HSEConfig(uint8_t RCC_HSE); |
| emilmont | 77:869cf507173a | 539 | ErrorStatus RCC_WaitForHSEStartUp(void); |
| emilmont | 77:869cf507173a | 540 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
| emilmont | 77:869cf507173a | 541 | void RCC_HSICmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 542 | void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); |
| emilmont | 77:869cf507173a | 543 | void RCC_HSI14Cmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 544 | void RCC_HSI14ADCRequestCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 545 | void RCC_LSEConfig(uint32_t RCC_LSE); |
| emilmont | 77:869cf507173a | 546 | void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); |
| emilmont | 77:869cf507173a | 547 | void RCC_LSICmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 548 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); |
| emilmont | 77:869cf507173a | 549 | void RCC_PLLCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 550 | void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 551 | uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */ |
| emilmont | 77:869cf507173a | 552 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); |
| emilmont | 77:869cf507173a | 553 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 554 | #ifdef STM32F051 |
| emilmont | 77:869cf507173a | 555 | void RCC_MCOConfig(uint8_t RCC_MCOSource); |
| emilmont | 77:869cf507173a | 556 | #else |
| emilmont | 77:869cf507173a | 557 | void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); |
| emilmont | 77:869cf507173a | 558 | #endif /* STM32F051 */ |
| emilmont | 77:869cf507173a | 559 | |
| emilmont | 77:869cf507173a | 560 | /* System, AHB and APB busses clocks configuration functions ******************/ |
| emilmont | 77:869cf507173a | 561 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
| emilmont | 77:869cf507173a | 562 | uint8_t RCC_GetSYSCLKSource(void); |
| emilmont | 77:869cf507173a | 563 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
| emilmont | 77:869cf507173a | 564 | void RCC_PCLKConfig(uint32_t RCC_HCLK); |
| emilmont | 77:869cf507173a | 565 | void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete. |
| emilmont | 77:869cf507173a | 566 | For proper ADC clock selection, refer to |
| emilmont | 77:869cf507173a | 567 | ADC_ClockModeConfig() in the ADC driver */ |
| emilmont | 77:869cf507173a | 568 | void RCC_CECCLKConfig(uint32_t RCC_CECCLK); |
| emilmont | 77:869cf507173a | 569 | void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); |
| emilmont | 77:869cf507173a | 570 | void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); |
| emilmont | 77:869cf507173a | 571 | void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */ |
| emilmont | 77:869cf507173a | 572 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
| emilmont | 77:869cf507173a | 573 | |
| emilmont | 77:869cf507173a | 574 | /* Peripheral clocks configuration functions **********************************/ |
| emilmont | 77:869cf507173a | 575 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
| emilmont | 77:869cf507173a | 576 | void RCC_RTCCLKCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 577 | void RCC_BackupResetCmd(FunctionalState NewState); |
| emilmont | 77:869cf507173a | 578 | |
| emilmont | 77:869cf507173a | 579 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 580 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 581 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 582 | |
| emilmont | 77:869cf507173a | 583 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 584 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 585 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 586 | |
| emilmont | 77:869cf507173a | 587 | /* Interrupts and flags management functions **********************************/ |
| emilmont | 77:869cf507173a | 588 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
| emilmont | 77:869cf507173a | 589 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
| emilmont | 77:869cf507173a | 590 | void RCC_ClearFlag(void); |
| emilmont | 77:869cf507173a | 591 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
| emilmont | 77:869cf507173a | 592 | void RCC_ClearITPendingBit(uint8_t RCC_IT); |
| emilmont | 77:869cf507173a | 593 | |
| emilmont | 77:869cf507173a | 594 | #ifdef __cplusplus |
| emilmont | 77:869cf507173a | 595 | } |
| emilmont | 77:869cf507173a | 596 | #endif |
| emilmont | 77:869cf507173a | 597 | |
| emilmont | 77:869cf507173a | 598 | #endif /* __STM32F0XX_RCC_H */ |
| emilmont | 77:869cf507173a | 599 | |
| emilmont | 77:869cf507173a | 600 | /** |
| emilmont | 77:869cf507173a | 601 | * @} |
| emilmont | 77:869cf507173a | 602 | */ |
| emilmont | 77:869cf507173a | 603 | |
| emilmont | 77:869cf507173a | 604 | /** |
| emilmont | 77:869cf507173a | 605 | * @} |
| emilmont | 77:869cf507173a | 606 | */ |
| emilmont | 77:869cf507173a | 607 | |
| emilmont | 77:869cf507173a | 608 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
