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TARGET_NRF51822/core_cmFunc.h@80:8e73be2a2ac1, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 12:21:39 2014 +0000
Revision:
80:8e73be2a2ac1
Child:
110:165afa46840b
First alpha release for the NRF51822 target (to be tested in the online IDE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cmFunc.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 80:8e73be2a2ac1 4 * @version V3.20
emilmont 80:8e73be2a2ac1 5 * @date 25. February 2013
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
emilmont 80:8e73be2a2ac1 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #ifndef __CORE_CMFUNC_H
emilmont 80:8e73be2a2ac1 39 #define __CORE_CMFUNC_H
emilmont 80:8e73be2a2ac1 40
emilmont 80:8e73be2a2ac1 41
emilmont 80:8e73be2a2ac1 42 /* ########################### Core Function Access ########################### */
emilmont 80:8e73be2a2ac1 43 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 80:8e73be2a2ac1 45 @{
emilmont 80:8e73be2a2ac1 46 */
emilmont 80:8e73be2a2ac1 47
emilmont 80:8e73be2a2ac1 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 80:8e73be2a2ac1 49 /* ARM armcc specific functions */
emilmont 80:8e73be2a2ac1 50
emilmont 80:8e73be2a2ac1 51 #if (__ARMCC_VERSION < 400677)
emilmont 80:8e73be2a2ac1 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 80:8e73be2a2ac1 53 #endif
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55 /* intrinsic void __enable_irq(); */
emilmont 80:8e73be2a2ac1 56 /* intrinsic void __disable_irq(); */
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 /** \brief Get Control Register
emilmont 80:8e73be2a2ac1 59
emilmont 80:8e73be2a2ac1 60 This function returns the content of the Control Register.
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62 \return Control Register value
emilmont 80:8e73be2a2ac1 63 */
emilmont 80:8e73be2a2ac1 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 80:8e73be2a2ac1 65 {
emilmont 80:8e73be2a2ac1 66 register uint32_t __regControl __ASM("control");
emilmont 80:8e73be2a2ac1 67 return(__regControl);
emilmont 80:8e73be2a2ac1 68 }
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70
emilmont 80:8e73be2a2ac1 71 /** \brief Set Control Register
emilmont 80:8e73be2a2ac1 72
emilmont 80:8e73be2a2ac1 73 This function writes the given value to the Control Register.
emilmont 80:8e73be2a2ac1 74
emilmont 80:8e73be2a2ac1 75 \param [in] control Control Register value to set
emilmont 80:8e73be2a2ac1 76 */
emilmont 80:8e73be2a2ac1 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 80:8e73be2a2ac1 78 {
emilmont 80:8e73be2a2ac1 79 register uint32_t __regControl __ASM("control");
emilmont 80:8e73be2a2ac1 80 __regControl = control;
emilmont 80:8e73be2a2ac1 81 }
emilmont 80:8e73be2a2ac1 82
emilmont 80:8e73be2a2ac1 83
emilmont 80:8e73be2a2ac1 84 /** \brief Get IPSR Register
emilmont 80:8e73be2a2ac1 85
emilmont 80:8e73be2a2ac1 86 This function returns the content of the IPSR Register.
emilmont 80:8e73be2a2ac1 87
emilmont 80:8e73be2a2ac1 88 \return IPSR Register value
emilmont 80:8e73be2a2ac1 89 */
emilmont 80:8e73be2a2ac1 90 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 80:8e73be2a2ac1 91 {
emilmont 80:8e73be2a2ac1 92 register uint32_t __regIPSR __ASM("ipsr");
emilmont 80:8e73be2a2ac1 93 return(__regIPSR);
emilmont 80:8e73be2a2ac1 94 }
emilmont 80:8e73be2a2ac1 95
emilmont 80:8e73be2a2ac1 96
emilmont 80:8e73be2a2ac1 97 /** \brief Get APSR Register
emilmont 80:8e73be2a2ac1 98
emilmont 80:8e73be2a2ac1 99 This function returns the content of the APSR Register.
emilmont 80:8e73be2a2ac1 100
emilmont 80:8e73be2a2ac1 101 \return APSR Register value
emilmont 80:8e73be2a2ac1 102 */
emilmont 80:8e73be2a2ac1 103 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 80:8e73be2a2ac1 104 {
emilmont 80:8e73be2a2ac1 105 register uint32_t __regAPSR __ASM("apsr");
emilmont 80:8e73be2a2ac1 106 return(__regAPSR);
emilmont 80:8e73be2a2ac1 107 }
emilmont 80:8e73be2a2ac1 108
emilmont 80:8e73be2a2ac1 109
emilmont 80:8e73be2a2ac1 110 /** \brief Get xPSR Register
emilmont 80:8e73be2a2ac1 111
emilmont 80:8e73be2a2ac1 112 This function returns the content of the xPSR Register.
emilmont 80:8e73be2a2ac1 113
emilmont 80:8e73be2a2ac1 114 \return xPSR Register value
emilmont 80:8e73be2a2ac1 115 */
emilmont 80:8e73be2a2ac1 116 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 80:8e73be2a2ac1 117 {
emilmont 80:8e73be2a2ac1 118 register uint32_t __regXPSR __ASM("xpsr");
emilmont 80:8e73be2a2ac1 119 return(__regXPSR);
emilmont 80:8e73be2a2ac1 120 }
emilmont 80:8e73be2a2ac1 121
emilmont 80:8e73be2a2ac1 122
emilmont 80:8e73be2a2ac1 123 /** \brief Get Process Stack Pointer
emilmont 80:8e73be2a2ac1 124
emilmont 80:8e73be2a2ac1 125 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 80:8e73be2a2ac1 126
emilmont 80:8e73be2a2ac1 127 \return PSP Register value
emilmont 80:8e73be2a2ac1 128 */
emilmont 80:8e73be2a2ac1 129 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 80:8e73be2a2ac1 130 {
emilmont 80:8e73be2a2ac1 131 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 80:8e73be2a2ac1 132 return(__regProcessStackPointer);
emilmont 80:8e73be2a2ac1 133 }
emilmont 80:8e73be2a2ac1 134
emilmont 80:8e73be2a2ac1 135
emilmont 80:8e73be2a2ac1 136 /** \brief Set Process Stack Pointer
emilmont 80:8e73be2a2ac1 137
emilmont 80:8e73be2a2ac1 138 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 80:8e73be2a2ac1 139
emilmont 80:8e73be2a2ac1 140 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 80:8e73be2a2ac1 141 */
emilmont 80:8e73be2a2ac1 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 80:8e73be2a2ac1 143 {
emilmont 80:8e73be2a2ac1 144 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 80:8e73be2a2ac1 145 __regProcessStackPointer = topOfProcStack;
emilmont 80:8e73be2a2ac1 146 }
emilmont 80:8e73be2a2ac1 147
emilmont 80:8e73be2a2ac1 148
emilmont 80:8e73be2a2ac1 149 /** \brief Get Main Stack Pointer
emilmont 80:8e73be2a2ac1 150
emilmont 80:8e73be2a2ac1 151 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 80:8e73be2a2ac1 152
emilmont 80:8e73be2a2ac1 153 \return MSP Register value
emilmont 80:8e73be2a2ac1 154 */
emilmont 80:8e73be2a2ac1 155 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 80:8e73be2a2ac1 156 {
emilmont 80:8e73be2a2ac1 157 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 80:8e73be2a2ac1 158 return(__regMainStackPointer);
emilmont 80:8e73be2a2ac1 159 }
emilmont 80:8e73be2a2ac1 160
emilmont 80:8e73be2a2ac1 161
emilmont 80:8e73be2a2ac1 162 /** \brief Set Main Stack Pointer
emilmont 80:8e73be2a2ac1 163
emilmont 80:8e73be2a2ac1 164 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 80:8e73be2a2ac1 165
emilmont 80:8e73be2a2ac1 166 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 80:8e73be2a2ac1 167 */
emilmont 80:8e73be2a2ac1 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 80:8e73be2a2ac1 169 {
emilmont 80:8e73be2a2ac1 170 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 80:8e73be2a2ac1 171 __regMainStackPointer = topOfMainStack;
emilmont 80:8e73be2a2ac1 172 }
emilmont 80:8e73be2a2ac1 173
emilmont 80:8e73be2a2ac1 174
emilmont 80:8e73be2a2ac1 175 /** \brief Get Priority Mask
emilmont 80:8e73be2a2ac1 176
emilmont 80:8e73be2a2ac1 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 80:8e73be2a2ac1 178
emilmont 80:8e73be2a2ac1 179 \return Priority Mask value
emilmont 80:8e73be2a2ac1 180 */
emilmont 80:8e73be2a2ac1 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 80:8e73be2a2ac1 182 {
emilmont 80:8e73be2a2ac1 183 register uint32_t __regPriMask __ASM("primask");
emilmont 80:8e73be2a2ac1 184 return(__regPriMask);
emilmont 80:8e73be2a2ac1 185 }
emilmont 80:8e73be2a2ac1 186
emilmont 80:8e73be2a2ac1 187
emilmont 80:8e73be2a2ac1 188 /** \brief Set Priority Mask
emilmont 80:8e73be2a2ac1 189
emilmont 80:8e73be2a2ac1 190 This function assigns the given value to the Priority Mask Register.
emilmont 80:8e73be2a2ac1 191
emilmont 80:8e73be2a2ac1 192 \param [in] priMask Priority Mask
emilmont 80:8e73be2a2ac1 193 */
emilmont 80:8e73be2a2ac1 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 80:8e73be2a2ac1 195 {
emilmont 80:8e73be2a2ac1 196 register uint32_t __regPriMask __ASM("primask");
emilmont 80:8e73be2a2ac1 197 __regPriMask = (priMask);
emilmont 80:8e73be2a2ac1 198 }
emilmont 80:8e73be2a2ac1 199
emilmont 80:8e73be2a2ac1 200
emilmont 80:8e73be2a2ac1 201 #if (__CORTEX_M >= 0x03)
emilmont 80:8e73be2a2ac1 202
emilmont 80:8e73be2a2ac1 203 /** \brief Enable FIQ
emilmont 80:8e73be2a2ac1 204
emilmont 80:8e73be2a2ac1 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 80:8e73be2a2ac1 206 Can only be executed in Privileged modes.
emilmont 80:8e73be2a2ac1 207 */
emilmont 80:8e73be2a2ac1 208 #define __enable_fault_irq __enable_fiq
emilmont 80:8e73be2a2ac1 209
emilmont 80:8e73be2a2ac1 210
emilmont 80:8e73be2a2ac1 211 /** \brief Disable FIQ
emilmont 80:8e73be2a2ac1 212
emilmont 80:8e73be2a2ac1 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 80:8e73be2a2ac1 214 Can only be executed in Privileged modes.
emilmont 80:8e73be2a2ac1 215 */
emilmont 80:8e73be2a2ac1 216 #define __disable_fault_irq __disable_fiq
emilmont 80:8e73be2a2ac1 217
emilmont 80:8e73be2a2ac1 218
emilmont 80:8e73be2a2ac1 219 /** \brief Get Base Priority
emilmont 80:8e73be2a2ac1 220
emilmont 80:8e73be2a2ac1 221 This function returns the current value of the Base Priority register.
emilmont 80:8e73be2a2ac1 222
emilmont 80:8e73be2a2ac1 223 \return Base Priority register value
emilmont 80:8e73be2a2ac1 224 */
emilmont 80:8e73be2a2ac1 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 80:8e73be2a2ac1 226 {
emilmont 80:8e73be2a2ac1 227 register uint32_t __regBasePri __ASM("basepri");
emilmont 80:8e73be2a2ac1 228 return(__regBasePri);
emilmont 80:8e73be2a2ac1 229 }
emilmont 80:8e73be2a2ac1 230
emilmont 80:8e73be2a2ac1 231
emilmont 80:8e73be2a2ac1 232 /** \brief Set Base Priority
emilmont 80:8e73be2a2ac1 233
emilmont 80:8e73be2a2ac1 234 This function assigns the given value to the Base Priority register.
emilmont 80:8e73be2a2ac1 235
emilmont 80:8e73be2a2ac1 236 \param [in] basePri Base Priority value to set
emilmont 80:8e73be2a2ac1 237 */
emilmont 80:8e73be2a2ac1 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 80:8e73be2a2ac1 239 {
emilmont 80:8e73be2a2ac1 240 register uint32_t __regBasePri __ASM("basepri");
emilmont 80:8e73be2a2ac1 241 __regBasePri = (basePri & 0xff);
emilmont 80:8e73be2a2ac1 242 }
emilmont 80:8e73be2a2ac1 243
emilmont 80:8e73be2a2ac1 244
emilmont 80:8e73be2a2ac1 245 /** \brief Get Fault Mask
emilmont 80:8e73be2a2ac1 246
emilmont 80:8e73be2a2ac1 247 This function returns the current value of the Fault Mask register.
emilmont 80:8e73be2a2ac1 248
emilmont 80:8e73be2a2ac1 249 \return Fault Mask register value
emilmont 80:8e73be2a2ac1 250 */
emilmont 80:8e73be2a2ac1 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 80:8e73be2a2ac1 252 {
emilmont 80:8e73be2a2ac1 253 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 80:8e73be2a2ac1 254 return(__regFaultMask);
emilmont 80:8e73be2a2ac1 255 }
emilmont 80:8e73be2a2ac1 256
emilmont 80:8e73be2a2ac1 257
emilmont 80:8e73be2a2ac1 258 /** \brief Set Fault Mask
emilmont 80:8e73be2a2ac1 259
emilmont 80:8e73be2a2ac1 260 This function assigns the given value to the Fault Mask register.
emilmont 80:8e73be2a2ac1 261
emilmont 80:8e73be2a2ac1 262 \param [in] faultMask Fault Mask value to set
emilmont 80:8e73be2a2ac1 263 */
emilmont 80:8e73be2a2ac1 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 80:8e73be2a2ac1 265 {
emilmont 80:8e73be2a2ac1 266 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 80:8e73be2a2ac1 267 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 80:8e73be2a2ac1 268 }
emilmont 80:8e73be2a2ac1 269
emilmont 80:8e73be2a2ac1 270 #endif /* (__CORTEX_M >= 0x03) */
emilmont 80:8e73be2a2ac1 271
emilmont 80:8e73be2a2ac1 272
emilmont 80:8e73be2a2ac1 273 #if (__CORTEX_M == 0x04)
emilmont 80:8e73be2a2ac1 274
emilmont 80:8e73be2a2ac1 275 /** \brief Get FPSCR
emilmont 80:8e73be2a2ac1 276
emilmont 80:8e73be2a2ac1 277 This function returns the current value of the Floating Point Status/Control register.
emilmont 80:8e73be2a2ac1 278
emilmont 80:8e73be2a2ac1 279 \return Floating Point Status/Control register value
emilmont 80:8e73be2a2ac1 280 */
emilmont 80:8e73be2a2ac1 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 80:8e73be2a2ac1 282 {
emilmont 80:8e73be2a2ac1 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 80:8e73be2a2ac1 284 register uint32_t __regfpscr __ASM("fpscr");
emilmont 80:8e73be2a2ac1 285 return(__regfpscr);
emilmont 80:8e73be2a2ac1 286 #else
emilmont 80:8e73be2a2ac1 287 return(0);
emilmont 80:8e73be2a2ac1 288 #endif
emilmont 80:8e73be2a2ac1 289 }
emilmont 80:8e73be2a2ac1 290
emilmont 80:8e73be2a2ac1 291
emilmont 80:8e73be2a2ac1 292 /** \brief Set FPSCR
emilmont 80:8e73be2a2ac1 293
emilmont 80:8e73be2a2ac1 294 This function assigns the given value to the Floating Point Status/Control register.
emilmont 80:8e73be2a2ac1 295
emilmont 80:8e73be2a2ac1 296 \param [in] fpscr Floating Point Status/Control value to set
emilmont 80:8e73be2a2ac1 297 */
emilmont 80:8e73be2a2ac1 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 80:8e73be2a2ac1 299 {
emilmont 80:8e73be2a2ac1 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 80:8e73be2a2ac1 301 register uint32_t __regfpscr __ASM("fpscr");
emilmont 80:8e73be2a2ac1 302 __regfpscr = (fpscr);
emilmont 80:8e73be2a2ac1 303 #endif
emilmont 80:8e73be2a2ac1 304 }
emilmont 80:8e73be2a2ac1 305
emilmont 80:8e73be2a2ac1 306 #endif /* (__CORTEX_M == 0x04) */
emilmont 80:8e73be2a2ac1 307
emilmont 80:8e73be2a2ac1 308
emilmont 80:8e73be2a2ac1 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 80:8e73be2a2ac1 310 /* IAR iccarm specific functions */
emilmont 80:8e73be2a2ac1 311
emilmont 80:8e73be2a2ac1 312 #include <cmsis_iar.h>
emilmont 80:8e73be2a2ac1 313
emilmont 80:8e73be2a2ac1 314
emilmont 80:8e73be2a2ac1 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 80:8e73be2a2ac1 316 /* TI CCS specific functions */
emilmont 80:8e73be2a2ac1 317
emilmont 80:8e73be2a2ac1 318 #include <cmsis_ccs.h>
emilmont 80:8e73be2a2ac1 319
emilmont 80:8e73be2a2ac1 320
emilmont 80:8e73be2a2ac1 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 80:8e73be2a2ac1 322 /* GNU gcc specific functions */
emilmont 80:8e73be2a2ac1 323
emilmont 80:8e73be2a2ac1 324 /** \brief Enable IRQ Interrupts
emilmont 80:8e73be2a2ac1 325
emilmont 80:8e73be2a2ac1 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 80:8e73be2a2ac1 327 Can only be executed in Privileged modes.
emilmont 80:8e73be2a2ac1 328 */
emilmont 80:8e73be2a2ac1 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 80:8e73be2a2ac1 330 {
emilmont 80:8e73be2a2ac1 331 __ASM volatile ("cpsie i" : : : "memory");
emilmont 80:8e73be2a2ac1 332 }
emilmont 80:8e73be2a2ac1 333
emilmont 80:8e73be2a2ac1 334
emilmont 80:8e73be2a2ac1 335 /** \brief Disable IRQ Interrupts
emilmont 80:8e73be2a2ac1 336
emilmont 80:8e73be2a2ac1 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 80:8e73be2a2ac1 338 Can only be executed in Privileged modes.
emilmont 80:8e73be2a2ac1 339 */
emilmont 80:8e73be2a2ac1 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 80:8e73be2a2ac1 341 {
emilmont 80:8e73be2a2ac1 342 __ASM volatile ("cpsid i" : : : "memory");
emilmont 80:8e73be2a2ac1 343 }
emilmont 80:8e73be2a2ac1 344
emilmont 80:8e73be2a2ac1 345
emilmont 80:8e73be2a2ac1 346 /** \brief Get Control Register
emilmont 80:8e73be2a2ac1 347
emilmont 80:8e73be2a2ac1 348 This function returns the content of the Control Register.
emilmont 80:8e73be2a2ac1 349
emilmont 80:8e73be2a2ac1 350 \return Control Register value
emilmont 80:8e73be2a2ac1 351 */
emilmont 80:8e73be2a2ac1 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 80:8e73be2a2ac1 353 {
emilmont 80:8e73be2a2ac1 354 uint32_t result;
emilmont 80:8e73be2a2ac1 355
emilmont 80:8e73be2a2ac1 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 80:8e73be2a2ac1 357 return(result);
emilmont 80:8e73be2a2ac1 358 }
emilmont 80:8e73be2a2ac1 359
emilmont 80:8e73be2a2ac1 360
emilmont 80:8e73be2a2ac1 361 /** \brief Set Control Register
emilmont 80:8e73be2a2ac1 362
emilmont 80:8e73be2a2ac1 363 This function writes the given value to the Control Register.
emilmont 80:8e73be2a2ac1 364
emilmont 80:8e73be2a2ac1 365 \param [in] control Control Register value to set
emilmont 80:8e73be2a2ac1 366 */
emilmont 80:8e73be2a2ac1 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 80:8e73be2a2ac1 368 {
emilmont 80:8e73be2a2ac1 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
emilmont 80:8e73be2a2ac1 370 }
emilmont 80:8e73be2a2ac1 371
emilmont 80:8e73be2a2ac1 372
emilmont 80:8e73be2a2ac1 373 /** \brief Get IPSR Register
emilmont 80:8e73be2a2ac1 374
emilmont 80:8e73be2a2ac1 375 This function returns the content of the IPSR Register.
emilmont 80:8e73be2a2ac1 376
emilmont 80:8e73be2a2ac1 377 \return IPSR Register value
emilmont 80:8e73be2a2ac1 378 */
emilmont 80:8e73be2a2ac1 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 80:8e73be2a2ac1 380 {
emilmont 80:8e73be2a2ac1 381 uint32_t result;
emilmont 80:8e73be2a2ac1 382
emilmont 80:8e73be2a2ac1 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 80:8e73be2a2ac1 384 return(result);
emilmont 80:8e73be2a2ac1 385 }
emilmont 80:8e73be2a2ac1 386
emilmont 80:8e73be2a2ac1 387
emilmont 80:8e73be2a2ac1 388 /** \brief Get APSR Register
emilmont 80:8e73be2a2ac1 389
emilmont 80:8e73be2a2ac1 390 This function returns the content of the APSR Register.
emilmont 80:8e73be2a2ac1 391
emilmont 80:8e73be2a2ac1 392 \return APSR Register value
emilmont 80:8e73be2a2ac1 393 */
emilmont 80:8e73be2a2ac1 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 80:8e73be2a2ac1 395 {
emilmont 80:8e73be2a2ac1 396 uint32_t result;
emilmont 80:8e73be2a2ac1 397
emilmont 80:8e73be2a2ac1 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 80:8e73be2a2ac1 399 return(result);
emilmont 80:8e73be2a2ac1 400 }
emilmont 80:8e73be2a2ac1 401
emilmont 80:8e73be2a2ac1 402
emilmont 80:8e73be2a2ac1 403 /** \brief Get xPSR Register
emilmont 80:8e73be2a2ac1 404
emilmont 80:8e73be2a2ac1 405 This function returns the content of the xPSR Register.
emilmont 80:8e73be2a2ac1 406
emilmont 80:8e73be2a2ac1 407 \return xPSR Register value
emilmont 80:8e73be2a2ac1 408 */
emilmont 80:8e73be2a2ac1 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 80:8e73be2a2ac1 410 {
emilmont 80:8e73be2a2ac1 411 uint32_t result;
emilmont 80:8e73be2a2ac1 412
emilmont 80:8e73be2a2ac1 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 80:8e73be2a2ac1 414 return(result);
emilmont 80:8e73be2a2ac1 415 }
emilmont 80:8e73be2a2ac1 416
emilmont 80:8e73be2a2ac1 417
emilmont 80:8e73be2a2ac1 418 /** \brief Get Process Stack Pointer
emilmont 80:8e73be2a2ac1 419
emilmont 80:8e73be2a2ac1 420 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 80:8e73be2a2ac1 421
emilmont 80:8e73be2a2ac1 422 \return PSP Register value
emilmont 80:8e73be2a2ac1 423 */
emilmont 80:8e73be2a2ac1 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 80:8e73be2a2ac1 425 {
emilmont 80:8e73be2a2ac1 426 register uint32_t result;
emilmont 80:8e73be2a2ac1 427
emilmont 80:8e73be2a2ac1 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 80:8e73be2a2ac1 429 return(result);
emilmont 80:8e73be2a2ac1 430 }
emilmont 80:8e73be2a2ac1 431
emilmont 80:8e73be2a2ac1 432
emilmont 80:8e73be2a2ac1 433 /** \brief Set Process Stack Pointer
emilmont 80:8e73be2a2ac1 434
emilmont 80:8e73be2a2ac1 435 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 80:8e73be2a2ac1 436
emilmont 80:8e73be2a2ac1 437 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 80:8e73be2a2ac1 438 */
emilmont 80:8e73be2a2ac1 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 80:8e73be2a2ac1 440 {
emilmont 80:8e73be2a2ac1 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
emilmont 80:8e73be2a2ac1 442 }
emilmont 80:8e73be2a2ac1 443
emilmont 80:8e73be2a2ac1 444
emilmont 80:8e73be2a2ac1 445 /** \brief Get Main Stack Pointer
emilmont 80:8e73be2a2ac1 446
emilmont 80:8e73be2a2ac1 447 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 80:8e73be2a2ac1 448
emilmont 80:8e73be2a2ac1 449 \return MSP Register value
emilmont 80:8e73be2a2ac1 450 */
emilmont 80:8e73be2a2ac1 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 80:8e73be2a2ac1 452 {
emilmont 80:8e73be2a2ac1 453 register uint32_t result;
emilmont 80:8e73be2a2ac1 454
emilmont 80:8e73be2a2ac1 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 80:8e73be2a2ac1 456 return(result);
emilmont 80:8e73be2a2ac1 457 }
emilmont 80:8e73be2a2ac1 458
emilmont 80:8e73be2a2ac1 459
emilmont 80:8e73be2a2ac1 460 /** \brief Set Main Stack Pointer
emilmont 80:8e73be2a2ac1 461
emilmont 80:8e73be2a2ac1 462 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 80:8e73be2a2ac1 463
emilmont 80:8e73be2a2ac1 464 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 80:8e73be2a2ac1 465 */
emilmont 80:8e73be2a2ac1 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 80:8e73be2a2ac1 467 {
emilmont 80:8e73be2a2ac1 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
emilmont 80:8e73be2a2ac1 469 }
emilmont 80:8e73be2a2ac1 470
emilmont 80:8e73be2a2ac1 471
emilmont 80:8e73be2a2ac1 472 /** \brief Get Priority Mask
emilmont 80:8e73be2a2ac1 473
emilmont 80:8e73be2a2ac1 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 80:8e73be2a2ac1 475
emilmont 80:8e73be2a2ac1 476 \return Priority Mask value
emilmont 80:8e73be2a2ac1 477 */
emilmont 80:8e73be2a2ac1 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 80:8e73be2a2ac1 479 {
emilmont 80:8e73be2a2ac1 480 uint32_t result;
emilmont 80:8e73be2a2ac1 481
emilmont 80:8e73be2a2ac1 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 80:8e73be2a2ac1 483 return(result);
emilmont 80:8e73be2a2ac1 484 }
emilmont 80:8e73be2a2ac1 485
emilmont 80:8e73be2a2ac1 486
emilmont 80:8e73be2a2ac1 487 /** \brief Set Priority Mask
emilmont 80:8e73be2a2ac1 488
emilmont 80:8e73be2a2ac1 489 This function assigns the given value to the Priority Mask Register.
emilmont 80:8e73be2a2ac1 490
emilmont 80:8e73be2a2ac1 491 \param [in] priMask Priority Mask
emilmont 80:8e73be2a2ac1 492 */
emilmont 80:8e73be2a2ac1 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 80:8e73be2a2ac1 494 {
emilmont 80:8e73be2a2ac1 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
emilmont 80:8e73be2a2ac1 496 }
emilmont 80:8e73be2a2ac1 497
emilmont 80:8e73be2a2ac1 498
emilmont 80:8e73be2a2ac1 499 #if (__CORTEX_M >= 0x03)
emilmont 80:8e73be2a2ac1 500
emilmont 80:8e73be2a2ac1 501 /** \brief Enable FIQ
emilmont 80:8e73be2a2ac1 502
emilmont 80:8e73be2a2ac1 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 80:8e73be2a2ac1 504 Can only be executed in Privileged modes.
emilmont 80:8e73be2a2ac1 505 */
emilmont 80:8e73be2a2ac1 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 80:8e73be2a2ac1 507 {
emilmont 80:8e73be2a2ac1 508 __ASM volatile ("cpsie f" : : : "memory");
emilmont 80:8e73be2a2ac1 509 }
emilmont 80:8e73be2a2ac1 510
emilmont 80:8e73be2a2ac1 511
emilmont 80:8e73be2a2ac1 512 /** \brief Disable FIQ
emilmont 80:8e73be2a2ac1 513
emilmont 80:8e73be2a2ac1 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 80:8e73be2a2ac1 515 Can only be executed in Privileged modes.
emilmont 80:8e73be2a2ac1 516 */
emilmont 80:8e73be2a2ac1 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 80:8e73be2a2ac1 518 {
emilmont 80:8e73be2a2ac1 519 __ASM volatile ("cpsid f" : : : "memory");
emilmont 80:8e73be2a2ac1 520 }
emilmont 80:8e73be2a2ac1 521
emilmont 80:8e73be2a2ac1 522
emilmont 80:8e73be2a2ac1 523 /** \brief Get Base Priority
emilmont 80:8e73be2a2ac1 524
emilmont 80:8e73be2a2ac1 525 This function returns the current value of the Base Priority register.
emilmont 80:8e73be2a2ac1 526
emilmont 80:8e73be2a2ac1 527 \return Base Priority register value
emilmont 80:8e73be2a2ac1 528 */
emilmont 80:8e73be2a2ac1 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 80:8e73be2a2ac1 530 {
emilmont 80:8e73be2a2ac1 531 uint32_t result;
emilmont 80:8e73be2a2ac1 532
emilmont 80:8e73be2a2ac1 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 80:8e73be2a2ac1 534 return(result);
emilmont 80:8e73be2a2ac1 535 }
emilmont 80:8e73be2a2ac1 536
emilmont 80:8e73be2a2ac1 537
emilmont 80:8e73be2a2ac1 538 /** \brief Set Base Priority
emilmont 80:8e73be2a2ac1 539
emilmont 80:8e73be2a2ac1 540 This function assigns the given value to the Base Priority register.
emilmont 80:8e73be2a2ac1 541
emilmont 80:8e73be2a2ac1 542 \param [in] basePri Base Priority value to set
emilmont 80:8e73be2a2ac1 543 */
emilmont 80:8e73be2a2ac1 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 80:8e73be2a2ac1 545 {
emilmont 80:8e73be2a2ac1 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
emilmont 80:8e73be2a2ac1 547 }
emilmont 80:8e73be2a2ac1 548
emilmont 80:8e73be2a2ac1 549
emilmont 80:8e73be2a2ac1 550 /** \brief Get Fault Mask
emilmont 80:8e73be2a2ac1 551
emilmont 80:8e73be2a2ac1 552 This function returns the current value of the Fault Mask register.
emilmont 80:8e73be2a2ac1 553
emilmont 80:8e73be2a2ac1 554 \return Fault Mask register value
emilmont 80:8e73be2a2ac1 555 */
emilmont 80:8e73be2a2ac1 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 80:8e73be2a2ac1 557 {
emilmont 80:8e73be2a2ac1 558 uint32_t result;
emilmont 80:8e73be2a2ac1 559
emilmont 80:8e73be2a2ac1 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 80:8e73be2a2ac1 561 return(result);
emilmont 80:8e73be2a2ac1 562 }
emilmont 80:8e73be2a2ac1 563
emilmont 80:8e73be2a2ac1 564
emilmont 80:8e73be2a2ac1 565 /** \brief Set Fault Mask
emilmont 80:8e73be2a2ac1 566
emilmont 80:8e73be2a2ac1 567 This function assigns the given value to the Fault Mask register.
emilmont 80:8e73be2a2ac1 568
emilmont 80:8e73be2a2ac1 569 \param [in] faultMask Fault Mask value to set
emilmont 80:8e73be2a2ac1 570 */
emilmont 80:8e73be2a2ac1 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 80:8e73be2a2ac1 572 {
emilmont 80:8e73be2a2ac1 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
emilmont 80:8e73be2a2ac1 574 }
emilmont 80:8e73be2a2ac1 575
emilmont 80:8e73be2a2ac1 576 #endif /* (__CORTEX_M >= 0x03) */
emilmont 80:8e73be2a2ac1 577
emilmont 80:8e73be2a2ac1 578
emilmont 80:8e73be2a2ac1 579 #if (__CORTEX_M == 0x04)
emilmont 80:8e73be2a2ac1 580
emilmont 80:8e73be2a2ac1 581 /** \brief Get FPSCR
emilmont 80:8e73be2a2ac1 582
emilmont 80:8e73be2a2ac1 583 This function returns the current value of the Floating Point Status/Control register.
emilmont 80:8e73be2a2ac1 584
emilmont 80:8e73be2a2ac1 585 \return Floating Point Status/Control register value
emilmont 80:8e73be2a2ac1 586 */
emilmont 80:8e73be2a2ac1 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 80:8e73be2a2ac1 588 {
emilmont 80:8e73be2a2ac1 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 80:8e73be2a2ac1 590 uint32_t result;
emilmont 80:8e73be2a2ac1 591
emilmont 80:8e73be2a2ac1 592 /* Empty asm statement works as a scheduling barrier */
emilmont 80:8e73be2a2ac1 593 __ASM volatile ("");
emilmont 80:8e73be2a2ac1 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 80:8e73be2a2ac1 595 __ASM volatile ("");
emilmont 80:8e73be2a2ac1 596 return(result);
emilmont 80:8e73be2a2ac1 597 #else
emilmont 80:8e73be2a2ac1 598 return(0);
emilmont 80:8e73be2a2ac1 599 #endif
emilmont 80:8e73be2a2ac1 600 }
emilmont 80:8e73be2a2ac1 601
emilmont 80:8e73be2a2ac1 602
emilmont 80:8e73be2a2ac1 603 /** \brief Set FPSCR
emilmont 80:8e73be2a2ac1 604
emilmont 80:8e73be2a2ac1 605 This function assigns the given value to the Floating Point Status/Control register.
emilmont 80:8e73be2a2ac1 606
emilmont 80:8e73be2a2ac1 607 \param [in] fpscr Floating Point Status/Control value to set
emilmont 80:8e73be2a2ac1 608 */
emilmont 80:8e73be2a2ac1 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 80:8e73be2a2ac1 610 {
emilmont 80:8e73be2a2ac1 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 80:8e73be2a2ac1 612 /* Empty asm statement works as a scheduling barrier */
emilmont 80:8e73be2a2ac1 613 __ASM volatile ("");
emilmont 80:8e73be2a2ac1 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
emilmont 80:8e73be2a2ac1 615 __ASM volatile ("");
emilmont 80:8e73be2a2ac1 616 #endif
emilmont 80:8e73be2a2ac1 617 }
emilmont 80:8e73be2a2ac1 618
emilmont 80:8e73be2a2ac1 619 #endif /* (__CORTEX_M == 0x04) */
emilmont 80:8e73be2a2ac1 620
emilmont 80:8e73be2a2ac1 621
emilmont 80:8e73be2a2ac1 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 80:8e73be2a2ac1 623 /* TASKING carm specific functions */
emilmont 80:8e73be2a2ac1 624
emilmont 80:8e73be2a2ac1 625 /*
emilmont 80:8e73be2a2ac1 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 80:8e73be2a2ac1 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 80:8e73be2a2ac1 628 * Including the CMSIS ones.
emilmont 80:8e73be2a2ac1 629 */
emilmont 80:8e73be2a2ac1 630
emilmont 80:8e73be2a2ac1 631 #endif
emilmont 80:8e73be2a2ac1 632
emilmont 80:8e73be2a2ac1 633 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 80:8e73be2a2ac1 634
emilmont 80:8e73be2a2ac1 635
emilmont 80:8e73be2a2ac1 636 #endif /* __CORE_CMFUNC_H */