mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF51822/core_cm3.h@80:8e73be2a2ac1, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 12:21:39 2014 +0000
Revision:
80:8e73be2a2ac1
Child:
110:165afa46840b
First alpha release for the NRF51822 target (to be tested in the online IDE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cm3.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
emilmont 80:8e73be2a2ac1 4 * @version V3.20
emilmont 80:8e73be2a2ac1 5 * @date 25. February 2013
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
emilmont 80:8e73be2a2ac1 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #if defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 80:8e73be2a2ac1 40 #endif
emilmont 80:8e73be2a2ac1 41
emilmont 80:8e73be2a2ac1 42 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 43 extern "C" {
emilmont 80:8e73be2a2ac1 44 #endif
emilmont 80:8e73be2a2ac1 45
emilmont 80:8e73be2a2ac1 46 #ifndef __CORE_CM3_H_GENERIC
emilmont 80:8e73be2a2ac1 47 #define __CORE_CM3_H_GENERIC
emilmont 80:8e73be2a2ac1 48
emilmont 80:8e73be2a2ac1 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 80:8e73be2a2ac1 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 80:8e73be2a2ac1 51
emilmont 80:8e73be2a2ac1 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 80:8e73be2a2ac1 53 Function definitions in header files are used to allow 'inlining'.
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 80:8e73be2a2ac1 56 Unions are used for effective representation of core registers.
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 80:8e73be2a2ac1 59 Function-like macros are used to allow more efficient code.
emilmont 80:8e73be2a2ac1 60 */
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62
emilmont 80:8e73be2a2ac1 63 /*******************************************************************************
emilmont 80:8e73be2a2ac1 64 * CMSIS definitions
emilmont 80:8e73be2a2ac1 65 ******************************************************************************/
emilmont 80:8e73be2a2ac1 66 /** \ingroup Cortex_M3
emilmont 80:8e73be2a2ac1 67 @{
emilmont 80:8e73be2a2ac1 68 */
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70 /* CMSIS CM3 definitions */
emilmont 80:8e73be2a2ac1 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 80:8e73be2a2ac1 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
emilmont 80:8e73be2a2ac1 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
emilmont 80:8e73be2a2ac1 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 80:8e73be2a2ac1 75
emilmont 80:8e73be2a2ac1 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
emilmont 80:8e73be2a2ac1 77
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 82 #define __STATIC_INLINE static __inline
emilmont 80:8e73be2a2ac1 83
emilmont 80:8e73be2a2ac1 84 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 80:8e73be2a2ac1 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 80:8e73be2a2ac1 87 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 88
emilmont 80:8e73be2a2ac1 89 #elif defined ( __TMS470__ )
emilmont 80:8e73be2a2ac1 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 80:8e73be2a2ac1 91 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 92
emilmont 80:8e73be2a2ac1 93 #elif defined ( __GNUC__ )
emilmont 80:8e73be2a2ac1 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 80:8e73be2a2ac1 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 80:8e73be2a2ac1 96 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 97
emilmont 80:8e73be2a2ac1 98 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 101 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 102
emilmont 80:8e73be2a2ac1 103 #endif
emilmont 80:8e73be2a2ac1 104
emilmont 80:8e73be2a2ac1 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 80:8e73be2a2ac1 106 */
emilmont 80:8e73be2a2ac1 107 #define __FPU_USED 0
emilmont 80:8e73be2a2ac1 108
emilmont 80:8e73be2a2ac1 109 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 110 #if defined __TARGET_FPU_VFP
emilmont 80:8e73be2a2ac1 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 112 #endif
emilmont 80:8e73be2a2ac1 113
emilmont 80:8e73be2a2ac1 114 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 115 #if defined __ARMVFP__
emilmont 80:8e73be2a2ac1 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 117 #endif
emilmont 80:8e73be2a2ac1 118
emilmont 80:8e73be2a2ac1 119 #elif defined ( __TMS470__ )
emilmont 80:8e73be2a2ac1 120 #if defined __TI__VFP_SUPPORT____
emilmont 80:8e73be2a2ac1 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 122 #endif
emilmont 80:8e73be2a2ac1 123
emilmont 80:8e73be2a2ac1 124 #elif defined ( __GNUC__ )
emilmont 80:8e73be2a2ac1 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 80:8e73be2a2ac1 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 127 #endif
emilmont 80:8e73be2a2ac1 128
emilmont 80:8e73be2a2ac1 129 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 130 #if defined __FPU_VFP__
emilmont 80:8e73be2a2ac1 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 132 #endif
emilmont 80:8e73be2a2ac1 133 #endif
emilmont 80:8e73be2a2ac1 134
emilmont 80:8e73be2a2ac1 135 #include <stdint.h> /* standard types definitions */
emilmont 80:8e73be2a2ac1 136 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 80:8e73be2a2ac1 137 #include <core_cmFunc.h> /* Core Function Access */
emilmont 80:8e73be2a2ac1 138
emilmont 80:8e73be2a2ac1 139 #endif /* __CORE_CM3_H_GENERIC */
emilmont 80:8e73be2a2ac1 140
emilmont 80:8e73be2a2ac1 141 #ifndef __CMSIS_GENERIC
emilmont 80:8e73be2a2ac1 142
emilmont 80:8e73be2a2ac1 143 #ifndef __CORE_CM3_H_DEPENDANT
emilmont 80:8e73be2a2ac1 144 #define __CORE_CM3_H_DEPENDANT
emilmont 80:8e73be2a2ac1 145
emilmont 80:8e73be2a2ac1 146 /* check device defines and use defaults */
emilmont 80:8e73be2a2ac1 147 #if defined __CHECK_DEVICE_DEFINES
emilmont 80:8e73be2a2ac1 148 #ifndef __CM3_REV
emilmont 80:8e73be2a2ac1 149 #define __CM3_REV 0x0200
emilmont 80:8e73be2a2ac1 150 #warning "__CM3_REV not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 151 #endif
emilmont 80:8e73be2a2ac1 152
emilmont 80:8e73be2a2ac1 153 #ifndef __MPU_PRESENT
emilmont 80:8e73be2a2ac1 154 #define __MPU_PRESENT 0
emilmont 80:8e73be2a2ac1 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 156 #endif
emilmont 80:8e73be2a2ac1 157
emilmont 80:8e73be2a2ac1 158 #ifndef __NVIC_PRIO_BITS
emilmont 80:8e73be2a2ac1 159 #define __NVIC_PRIO_BITS 4
emilmont 80:8e73be2a2ac1 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 161 #endif
emilmont 80:8e73be2a2ac1 162
emilmont 80:8e73be2a2ac1 163 #ifndef __Vendor_SysTickConfig
emilmont 80:8e73be2a2ac1 164 #define __Vendor_SysTickConfig 0
emilmont 80:8e73be2a2ac1 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 166 #endif
emilmont 80:8e73be2a2ac1 167 #endif
emilmont 80:8e73be2a2ac1 168
emilmont 80:8e73be2a2ac1 169 /* IO definitions (access restrictions to peripheral registers) */
emilmont 80:8e73be2a2ac1 170 /**
emilmont 80:8e73be2a2ac1 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 80:8e73be2a2ac1 172
emilmont 80:8e73be2a2ac1 173 <strong>IO Type Qualifiers</strong> are used
emilmont 80:8e73be2a2ac1 174 \li to specify the access to peripheral variables.
emilmont 80:8e73be2a2ac1 175 \li for automatic generation of peripheral register debug information.
emilmont 80:8e73be2a2ac1 176 */
emilmont 80:8e73be2a2ac1 177 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 178 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 179 #else
emilmont 80:8e73be2a2ac1 180 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 181 #endif
emilmont 80:8e73be2a2ac1 182 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 80:8e73be2a2ac1 183 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 80:8e73be2a2ac1 184
emilmont 80:8e73be2a2ac1 185 /*@} end of group Cortex_M3 */
emilmont 80:8e73be2a2ac1 186
emilmont 80:8e73be2a2ac1 187
emilmont 80:8e73be2a2ac1 188
emilmont 80:8e73be2a2ac1 189 /*******************************************************************************
emilmont 80:8e73be2a2ac1 190 * Register Abstraction
emilmont 80:8e73be2a2ac1 191 Core Register contain:
emilmont 80:8e73be2a2ac1 192 - Core Register
emilmont 80:8e73be2a2ac1 193 - Core NVIC Register
emilmont 80:8e73be2a2ac1 194 - Core SCB Register
emilmont 80:8e73be2a2ac1 195 - Core SysTick Register
emilmont 80:8e73be2a2ac1 196 - Core Debug Register
emilmont 80:8e73be2a2ac1 197 - Core MPU Register
emilmont 80:8e73be2a2ac1 198 ******************************************************************************/
emilmont 80:8e73be2a2ac1 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 80:8e73be2a2ac1 200 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 80:8e73be2a2ac1 201 */
emilmont 80:8e73be2a2ac1 202
emilmont 80:8e73be2a2ac1 203 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 204 \defgroup CMSIS_CORE Status and Control Registers
emilmont 80:8e73be2a2ac1 205 \brief Core Register type definitions.
emilmont 80:8e73be2a2ac1 206 @{
emilmont 80:8e73be2a2ac1 207 */
emilmont 80:8e73be2a2ac1 208
emilmont 80:8e73be2a2ac1 209 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 80:8e73be2a2ac1 210 */
emilmont 80:8e73be2a2ac1 211 typedef union
emilmont 80:8e73be2a2ac1 212 {
emilmont 80:8e73be2a2ac1 213 struct
emilmont 80:8e73be2a2ac1 214 {
emilmont 80:8e73be2a2ac1 215 #if (__CORTEX_M != 0x04)
emilmont 80:8e73be2a2ac1 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 80:8e73be2a2ac1 217 #else
emilmont 80:8e73be2a2ac1 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 80:8e73be2a2ac1 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 80:8e73be2a2ac1 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 80:8e73be2a2ac1 221 #endif
emilmont 80:8e73be2a2ac1 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 80:8e73be2a2ac1 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 227 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 228 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 229 } APSR_Type;
emilmont 80:8e73be2a2ac1 230
emilmont 80:8e73be2a2ac1 231
emilmont 80:8e73be2a2ac1 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 80:8e73be2a2ac1 233 */
emilmont 80:8e73be2a2ac1 234 typedef union
emilmont 80:8e73be2a2ac1 235 {
emilmont 80:8e73be2a2ac1 236 struct
emilmont 80:8e73be2a2ac1 237 {
emilmont 80:8e73be2a2ac1 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 80:8e73be2a2ac1 240 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 241 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 242 } IPSR_Type;
emilmont 80:8e73be2a2ac1 243
emilmont 80:8e73be2a2ac1 244
emilmont 80:8e73be2a2ac1 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 80:8e73be2a2ac1 246 */
emilmont 80:8e73be2a2ac1 247 typedef union
emilmont 80:8e73be2a2ac1 248 {
emilmont 80:8e73be2a2ac1 249 struct
emilmont 80:8e73be2a2ac1 250 {
emilmont 80:8e73be2a2ac1 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 252 #if (__CORTEX_M != 0x04)
emilmont 80:8e73be2a2ac1 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 80:8e73be2a2ac1 254 #else
emilmont 80:8e73be2a2ac1 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 80:8e73be2a2ac1 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 80:8e73be2a2ac1 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 80:8e73be2a2ac1 258 #endif
emilmont 80:8e73be2a2ac1 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 80:8e73be2a2ac1 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 80:8e73be2a2ac1 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 80:8e73be2a2ac1 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 266 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 267 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 268 } xPSR_Type;
emilmont 80:8e73be2a2ac1 269
emilmont 80:8e73be2a2ac1 270
emilmont 80:8e73be2a2ac1 271 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 80:8e73be2a2ac1 272 */
emilmont 80:8e73be2a2ac1 273 typedef union
emilmont 80:8e73be2a2ac1 274 {
emilmont 80:8e73be2a2ac1 275 struct
emilmont 80:8e73be2a2ac1 276 {
emilmont 80:8e73be2a2ac1 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 80:8e73be2a2ac1 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 80:8e73be2a2ac1 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 80:8e73be2a2ac1 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 80:8e73be2a2ac1 281 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 282 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 283 } CONTROL_Type;
emilmont 80:8e73be2a2ac1 284
emilmont 80:8e73be2a2ac1 285 /*@} end of group CMSIS_CORE */
emilmont 80:8e73be2a2ac1 286
emilmont 80:8e73be2a2ac1 287
emilmont 80:8e73be2a2ac1 288 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 80:8e73be2a2ac1 290 \brief Type definitions for the NVIC Registers
emilmont 80:8e73be2a2ac1 291 @{
emilmont 80:8e73be2a2ac1 292 */
emilmont 80:8e73be2a2ac1 293
emilmont 80:8e73be2a2ac1 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 80:8e73be2a2ac1 295 */
emilmont 80:8e73be2a2ac1 296 typedef struct
emilmont 80:8e73be2a2ac1 297 {
emilmont 80:8e73be2a2ac1 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 80:8e73be2a2ac1 299 uint32_t RESERVED0[24];
emilmont 80:8e73be2a2ac1 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 80:8e73be2a2ac1 301 uint32_t RSERVED1[24];
emilmont 80:8e73be2a2ac1 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 80:8e73be2a2ac1 303 uint32_t RESERVED2[24];
emilmont 80:8e73be2a2ac1 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 80:8e73be2a2ac1 305 uint32_t RESERVED3[24];
emilmont 80:8e73be2a2ac1 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
emilmont 80:8e73be2a2ac1 307 uint32_t RESERVED4[56];
emilmont 80:8e73be2a2ac1 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
emilmont 80:8e73be2a2ac1 309 uint32_t RESERVED5[644];
emilmont 80:8e73be2a2ac1 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
emilmont 80:8e73be2a2ac1 311 } NVIC_Type;
emilmont 80:8e73be2a2ac1 312
emilmont 80:8e73be2a2ac1 313 /* Software Triggered Interrupt Register Definitions */
emilmont 80:8e73be2a2ac1 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
emilmont 80:8e73be2a2ac1 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
emilmont 80:8e73be2a2ac1 316
emilmont 80:8e73be2a2ac1 317 /*@} end of group CMSIS_NVIC */
emilmont 80:8e73be2a2ac1 318
emilmont 80:8e73be2a2ac1 319
emilmont 80:8e73be2a2ac1 320 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 321 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 80:8e73be2a2ac1 322 \brief Type definitions for the System Control Block Registers
emilmont 80:8e73be2a2ac1 323 @{
emilmont 80:8e73be2a2ac1 324 */
emilmont 80:8e73be2a2ac1 325
emilmont 80:8e73be2a2ac1 326 /** \brief Structure type to access the System Control Block (SCB).
emilmont 80:8e73be2a2ac1 327 */
emilmont 80:8e73be2a2ac1 328 typedef struct
emilmont 80:8e73be2a2ac1 329 {
emilmont 80:8e73be2a2ac1 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 80:8e73be2a2ac1 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 80:8e73be2a2ac1 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 80:8e73be2a2ac1 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 80:8e73be2a2ac1 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 80:8e73be2a2ac1 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 80:8e73be2a2ac1 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
emilmont 80:8e73be2a2ac1 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 80:8e73be2a2ac1 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
emilmont 80:8e73be2a2ac1 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
emilmont 80:8e73be2a2ac1 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
emilmont 80:8e73be2a2ac1 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
emilmont 80:8e73be2a2ac1 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
emilmont 80:8e73be2a2ac1 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
emilmont 80:8e73be2a2ac1 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
emilmont 80:8e73be2a2ac1 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
emilmont 80:8e73be2a2ac1 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
emilmont 80:8e73be2a2ac1 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
emilmont 80:8e73be2a2ac1 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
emilmont 80:8e73be2a2ac1 349 uint32_t RESERVED0[5];
emilmont 80:8e73be2a2ac1 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
emilmont 80:8e73be2a2ac1 351 } SCB_Type;
emilmont 80:8e73be2a2ac1 352
emilmont 80:8e73be2a2ac1 353 /* SCB CPUID Register Definitions */
emilmont 80:8e73be2a2ac1 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 80:8e73be2a2ac1 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 80:8e73be2a2ac1 356
emilmont 80:8e73be2a2ac1 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 80:8e73be2a2ac1 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 80:8e73be2a2ac1 359
emilmont 80:8e73be2a2ac1 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 80:8e73be2a2ac1 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 80:8e73be2a2ac1 362
emilmont 80:8e73be2a2ac1 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 80:8e73be2a2ac1 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 80:8e73be2a2ac1 365
emilmont 80:8e73be2a2ac1 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 80:8e73be2a2ac1 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 80:8e73be2a2ac1 368
emilmont 80:8e73be2a2ac1 369 /* SCB Interrupt Control State Register Definitions */
emilmont 80:8e73be2a2ac1 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 80:8e73be2a2ac1 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 80:8e73be2a2ac1 372
emilmont 80:8e73be2a2ac1 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 80:8e73be2a2ac1 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 80:8e73be2a2ac1 375
emilmont 80:8e73be2a2ac1 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 80:8e73be2a2ac1 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 80:8e73be2a2ac1 378
emilmont 80:8e73be2a2ac1 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 80:8e73be2a2ac1 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 80:8e73be2a2ac1 381
emilmont 80:8e73be2a2ac1 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 80:8e73be2a2ac1 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 80:8e73be2a2ac1 384
emilmont 80:8e73be2a2ac1 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 80:8e73be2a2ac1 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 80:8e73be2a2ac1 387
emilmont 80:8e73be2a2ac1 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 80:8e73be2a2ac1 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 80:8e73be2a2ac1 390
emilmont 80:8e73be2a2ac1 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 80:8e73be2a2ac1 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 80:8e73be2a2ac1 393
emilmont 80:8e73be2a2ac1 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
emilmont 80:8e73be2a2ac1 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
emilmont 80:8e73be2a2ac1 396
emilmont 80:8e73be2a2ac1 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 80:8e73be2a2ac1 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 80:8e73be2a2ac1 399
emilmont 80:8e73be2a2ac1 400 /* SCB Vector Table Offset Register Definitions */
emilmont 80:8e73be2a2ac1 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
emilmont 80:8e73be2a2ac1 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
emilmont 80:8e73be2a2ac1 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
emilmont 80:8e73be2a2ac1 404
emilmont 80:8e73be2a2ac1 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 80:8e73be2a2ac1 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 80:8e73be2a2ac1 407 #else
emilmont 80:8e73be2a2ac1 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 80:8e73be2a2ac1 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 80:8e73be2a2ac1 410 #endif
emilmont 80:8e73be2a2ac1 411
emilmont 80:8e73be2a2ac1 412 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 80:8e73be2a2ac1 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 80:8e73be2a2ac1 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 80:8e73be2a2ac1 415
emilmont 80:8e73be2a2ac1 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 80:8e73be2a2ac1 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 80:8e73be2a2ac1 418
emilmont 80:8e73be2a2ac1 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 80:8e73be2a2ac1 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 80:8e73be2a2ac1 421
emilmont 80:8e73be2a2ac1 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
emilmont 80:8e73be2a2ac1 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
emilmont 80:8e73be2a2ac1 424
emilmont 80:8e73be2a2ac1 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 80:8e73be2a2ac1 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 80:8e73be2a2ac1 427
emilmont 80:8e73be2a2ac1 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 80:8e73be2a2ac1 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 80:8e73be2a2ac1 430
emilmont 80:8e73be2a2ac1 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
emilmont 80:8e73be2a2ac1 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
emilmont 80:8e73be2a2ac1 433
emilmont 80:8e73be2a2ac1 434 /* SCB System Control Register Definitions */
emilmont 80:8e73be2a2ac1 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 80:8e73be2a2ac1 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 80:8e73be2a2ac1 437
emilmont 80:8e73be2a2ac1 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 80:8e73be2a2ac1 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 80:8e73be2a2ac1 440
emilmont 80:8e73be2a2ac1 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 80:8e73be2a2ac1 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 80:8e73be2a2ac1 443
emilmont 80:8e73be2a2ac1 444 /* SCB Configuration Control Register Definitions */
emilmont 80:8e73be2a2ac1 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 80:8e73be2a2ac1 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 80:8e73be2a2ac1 447
emilmont 80:8e73be2a2ac1 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
emilmont 80:8e73be2a2ac1 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
emilmont 80:8e73be2a2ac1 450
emilmont 80:8e73be2a2ac1 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
emilmont 80:8e73be2a2ac1 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
emilmont 80:8e73be2a2ac1 453
emilmont 80:8e73be2a2ac1 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 80:8e73be2a2ac1 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 80:8e73be2a2ac1 456
emilmont 80:8e73be2a2ac1 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
emilmont 80:8e73be2a2ac1 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
emilmont 80:8e73be2a2ac1 459
emilmont 80:8e73be2a2ac1 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
emilmont 80:8e73be2a2ac1 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
emilmont 80:8e73be2a2ac1 462
emilmont 80:8e73be2a2ac1 463 /* SCB System Handler Control and State Register Definitions */
emilmont 80:8e73be2a2ac1 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
emilmont 80:8e73be2a2ac1 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
emilmont 80:8e73be2a2ac1 466
emilmont 80:8e73be2a2ac1 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
emilmont 80:8e73be2a2ac1 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
emilmont 80:8e73be2a2ac1 469
emilmont 80:8e73be2a2ac1 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
emilmont 80:8e73be2a2ac1 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
emilmont 80:8e73be2a2ac1 472
emilmont 80:8e73be2a2ac1 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 80:8e73be2a2ac1 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 80:8e73be2a2ac1 475
emilmont 80:8e73be2a2ac1 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
emilmont 80:8e73be2a2ac1 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
emilmont 80:8e73be2a2ac1 478
emilmont 80:8e73be2a2ac1 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
emilmont 80:8e73be2a2ac1 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
emilmont 80:8e73be2a2ac1 481
emilmont 80:8e73be2a2ac1 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
emilmont 80:8e73be2a2ac1 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
emilmont 80:8e73be2a2ac1 484
emilmont 80:8e73be2a2ac1 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
emilmont 80:8e73be2a2ac1 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
emilmont 80:8e73be2a2ac1 487
emilmont 80:8e73be2a2ac1 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
emilmont 80:8e73be2a2ac1 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
emilmont 80:8e73be2a2ac1 490
emilmont 80:8e73be2a2ac1 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
emilmont 80:8e73be2a2ac1 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
emilmont 80:8e73be2a2ac1 493
emilmont 80:8e73be2a2ac1 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
emilmont 80:8e73be2a2ac1 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
emilmont 80:8e73be2a2ac1 496
emilmont 80:8e73be2a2ac1 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
emilmont 80:8e73be2a2ac1 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
emilmont 80:8e73be2a2ac1 499
emilmont 80:8e73be2a2ac1 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
emilmont 80:8e73be2a2ac1 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
emilmont 80:8e73be2a2ac1 502
emilmont 80:8e73be2a2ac1 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
emilmont 80:8e73be2a2ac1 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
emilmont 80:8e73be2a2ac1 505
emilmont 80:8e73be2a2ac1 506 /* SCB Configurable Fault Status Registers Definitions */
emilmont 80:8e73be2a2ac1 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
emilmont 80:8e73be2a2ac1 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
emilmont 80:8e73be2a2ac1 509
emilmont 80:8e73be2a2ac1 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
emilmont 80:8e73be2a2ac1 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
emilmont 80:8e73be2a2ac1 512
emilmont 80:8e73be2a2ac1 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
emilmont 80:8e73be2a2ac1 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
emilmont 80:8e73be2a2ac1 515
emilmont 80:8e73be2a2ac1 516 /* SCB Hard Fault Status Registers Definitions */
emilmont 80:8e73be2a2ac1 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
emilmont 80:8e73be2a2ac1 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
emilmont 80:8e73be2a2ac1 519
emilmont 80:8e73be2a2ac1 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
emilmont 80:8e73be2a2ac1 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
emilmont 80:8e73be2a2ac1 522
emilmont 80:8e73be2a2ac1 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
emilmont 80:8e73be2a2ac1 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
emilmont 80:8e73be2a2ac1 525
emilmont 80:8e73be2a2ac1 526 /* SCB Debug Fault Status Register Definitions */
emilmont 80:8e73be2a2ac1 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
emilmont 80:8e73be2a2ac1 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
emilmont 80:8e73be2a2ac1 529
emilmont 80:8e73be2a2ac1 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
emilmont 80:8e73be2a2ac1 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
emilmont 80:8e73be2a2ac1 532
emilmont 80:8e73be2a2ac1 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
emilmont 80:8e73be2a2ac1 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
emilmont 80:8e73be2a2ac1 535
emilmont 80:8e73be2a2ac1 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
emilmont 80:8e73be2a2ac1 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
emilmont 80:8e73be2a2ac1 538
emilmont 80:8e73be2a2ac1 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
emilmont 80:8e73be2a2ac1 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
emilmont 80:8e73be2a2ac1 541
emilmont 80:8e73be2a2ac1 542 /*@} end of group CMSIS_SCB */
emilmont 80:8e73be2a2ac1 543
emilmont 80:8e73be2a2ac1 544
emilmont 80:8e73be2a2ac1 545 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont 80:8e73be2a2ac1 547 \brief Type definitions for the System Control and ID Register not in the SCB
emilmont 80:8e73be2a2ac1 548 @{
emilmont 80:8e73be2a2ac1 549 */
emilmont 80:8e73be2a2ac1 550
emilmont 80:8e73be2a2ac1 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont 80:8e73be2a2ac1 552 */
emilmont 80:8e73be2a2ac1 553 typedef struct
emilmont 80:8e73be2a2ac1 554 {
emilmont 80:8e73be2a2ac1 555 uint32_t RESERVED0[1];
emilmont 80:8e73be2a2ac1 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
emilmont 80:8e73be2a2ac1 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont 80:8e73be2a2ac1 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
emilmont 80:8e73be2a2ac1 559 #else
emilmont 80:8e73be2a2ac1 560 uint32_t RESERVED1[1];
emilmont 80:8e73be2a2ac1 561 #endif
emilmont 80:8e73be2a2ac1 562 } SCnSCB_Type;
emilmont 80:8e73be2a2ac1 563
emilmont 80:8e73be2a2ac1 564 /* Interrupt Controller Type Register Definitions */
emilmont 80:8e73be2a2ac1 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
emilmont 80:8e73be2a2ac1 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
emilmont 80:8e73be2a2ac1 567
emilmont 80:8e73be2a2ac1 568 /* Auxiliary Control Register Definitions */
emilmont 80:8e73be2a2ac1 569
emilmont 80:8e73be2a2ac1 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
emilmont 80:8e73be2a2ac1 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
emilmont 80:8e73be2a2ac1 572
emilmont 80:8e73be2a2ac1 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
emilmont 80:8e73be2a2ac1 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
emilmont 80:8e73be2a2ac1 575
emilmont 80:8e73be2a2ac1 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
emilmont 80:8e73be2a2ac1 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
emilmont 80:8e73be2a2ac1 578
emilmont 80:8e73be2a2ac1 579 /*@} end of group CMSIS_SCnotSCB */
emilmont 80:8e73be2a2ac1 580
emilmont 80:8e73be2a2ac1 581
emilmont 80:8e73be2a2ac1 582 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 80:8e73be2a2ac1 584 \brief Type definitions for the System Timer Registers.
emilmont 80:8e73be2a2ac1 585 @{
emilmont 80:8e73be2a2ac1 586 */
emilmont 80:8e73be2a2ac1 587
emilmont 80:8e73be2a2ac1 588 /** \brief Structure type to access the System Timer (SysTick).
emilmont 80:8e73be2a2ac1 589 */
emilmont 80:8e73be2a2ac1 590 typedef struct
emilmont 80:8e73be2a2ac1 591 {
emilmont 80:8e73be2a2ac1 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 80:8e73be2a2ac1 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 80:8e73be2a2ac1 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 80:8e73be2a2ac1 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 80:8e73be2a2ac1 596 } SysTick_Type;
emilmont 80:8e73be2a2ac1 597
emilmont 80:8e73be2a2ac1 598 /* SysTick Control / Status Register Definitions */
emilmont 80:8e73be2a2ac1 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 80:8e73be2a2ac1 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 80:8e73be2a2ac1 601
emilmont 80:8e73be2a2ac1 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 80:8e73be2a2ac1 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 80:8e73be2a2ac1 604
emilmont 80:8e73be2a2ac1 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 80:8e73be2a2ac1 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 80:8e73be2a2ac1 607
emilmont 80:8e73be2a2ac1 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 80:8e73be2a2ac1 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 610
emilmont 80:8e73be2a2ac1 611 /* SysTick Reload Register Definitions */
emilmont 80:8e73be2a2ac1 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 80:8e73be2a2ac1 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 80:8e73be2a2ac1 614
emilmont 80:8e73be2a2ac1 615 /* SysTick Current Register Definitions */
emilmont 80:8e73be2a2ac1 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 80:8e73be2a2ac1 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 80:8e73be2a2ac1 618
emilmont 80:8e73be2a2ac1 619 /* SysTick Calibration Register Definitions */
emilmont 80:8e73be2a2ac1 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 80:8e73be2a2ac1 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 80:8e73be2a2ac1 622
emilmont 80:8e73be2a2ac1 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 80:8e73be2a2ac1 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 80:8e73be2a2ac1 625
emilmont 80:8e73be2a2ac1 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 80:8e73be2a2ac1 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 80:8e73be2a2ac1 628
emilmont 80:8e73be2a2ac1 629 /*@} end of group CMSIS_SysTick */
emilmont 80:8e73be2a2ac1 630
emilmont 80:8e73be2a2ac1 631
emilmont 80:8e73be2a2ac1 632 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont 80:8e73be2a2ac1 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont 80:8e73be2a2ac1 635 @{
emilmont 80:8e73be2a2ac1 636 */
emilmont 80:8e73be2a2ac1 637
emilmont 80:8e73be2a2ac1 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont 80:8e73be2a2ac1 639 */
emilmont 80:8e73be2a2ac1 640 typedef struct
emilmont 80:8e73be2a2ac1 641 {
emilmont 80:8e73be2a2ac1 642 __O union
emilmont 80:8e73be2a2ac1 643 {
emilmont 80:8e73be2a2ac1 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
emilmont 80:8e73be2a2ac1 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
emilmont 80:8e73be2a2ac1 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
emilmont 80:8e73be2a2ac1 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
emilmont 80:8e73be2a2ac1 648 uint32_t RESERVED0[864];
emilmont 80:8e73be2a2ac1 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
emilmont 80:8e73be2a2ac1 650 uint32_t RESERVED1[15];
emilmont 80:8e73be2a2ac1 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
emilmont 80:8e73be2a2ac1 652 uint32_t RESERVED2[15];
emilmont 80:8e73be2a2ac1 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
emilmont 80:8e73be2a2ac1 654 uint32_t RESERVED3[29];
emilmont 80:8e73be2a2ac1 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
emilmont 80:8e73be2a2ac1 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
emilmont 80:8e73be2a2ac1 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
emilmont 80:8e73be2a2ac1 658 uint32_t RESERVED4[43];
emilmont 80:8e73be2a2ac1 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
emilmont 80:8e73be2a2ac1 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
emilmont 80:8e73be2a2ac1 661 uint32_t RESERVED5[6];
emilmont 80:8e73be2a2ac1 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
emilmont 80:8e73be2a2ac1 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
emilmont 80:8e73be2a2ac1 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
emilmont 80:8e73be2a2ac1 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
emilmont 80:8e73be2a2ac1 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
emilmont 80:8e73be2a2ac1 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
emilmont 80:8e73be2a2ac1 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
emilmont 80:8e73be2a2ac1 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
emilmont 80:8e73be2a2ac1 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
emilmont 80:8e73be2a2ac1 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
emilmont 80:8e73be2a2ac1 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
emilmont 80:8e73be2a2ac1 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
emilmont 80:8e73be2a2ac1 674 } ITM_Type;
emilmont 80:8e73be2a2ac1 675
emilmont 80:8e73be2a2ac1 676 /* ITM Trace Privilege Register Definitions */
emilmont 80:8e73be2a2ac1 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
emilmont 80:8e73be2a2ac1 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
emilmont 80:8e73be2a2ac1 679
emilmont 80:8e73be2a2ac1 680 /* ITM Trace Control Register Definitions */
emilmont 80:8e73be2a2ac1 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
emilmont 80:8e73be2a2ac1 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
emilmont 80:8e73be2a2ac1 683
emilmont 80:8e73be2a2ac1 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
emilmont 80:8e73be2a2ac1 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
emilmont 80:8e73be2a2ac1 686
emilmont 80:8e73be2a2ac1 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
emilmont 80:8e73be2a2ac1 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
emilmont 80:8e73be2a2ac1 689
emilmont 80:8e73be2a2ac1 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
emilmont 80:8e73be2a2ac1 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
emilmont 80:8e73be2a2ac1 692
emilmont 80:8e73be2a2ac1 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
emilmont 80:8e73be2a2ac1 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
emilmont 80:8e73be2a2ac1 695
emilmont 80:8e73be2a2ac1 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
emilmont 80:8e73be2a2ac1 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
emilmont 80:8e73be2a2ac1 698
emilmont 80:8e73be2a2ac1 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
emilmont 80:8e73be2a2ac1 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
emilmont 80:8e73be2a2ac1 701
emilmont 80:8e73be2a2ac1 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
emilmont 80:8e73be2a2ac1 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
emilmont 80:8e73be2a2ac1 704
emilmont 80:8e73be2a2ac1 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
emilmont 80:8e73be2a2ac1 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
emilmont 80:8e73be2a2ac1 707
emilmont 80:8e73be2a2ac1 708 /* ITM Integration Write Register Definitions */
emilmont 80:8e73be2a2ac1 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
emilmont 80:8e73be2a2ac1 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
emilmont 80:8e73be2a2ac1 711
emilmont 80:8e73be2a2ac1 712 /* ITM Integration Read Register Definitions */
emilmont 80:8e73be2a2ac1 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
emilmont 80:8e73be2a2ac1 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
emilmont 80:8e73be2a2ac1 715
emilmont 80:8e73be2a2ac1 716 /* ITM Integration Mode Control Register Definitions */
emilmont 80:8e73be2a2ac1 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
emilmont 80:8e73be2a2ac1 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
emilmont 80:8e73be2a2ac1 719
emilmont 80:8e73be2a2ac1 720 /* ITM Lock Status Register Definitions */
emilmont 80:8e73be2a2ac1 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
emilmont 80:8e73be2a2ac1 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
emilmont 80:8e73be2a2ac1 723
emilmont 80:8e73be2a2ac1 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
emilmont 80:8e73be2a2ac1 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
emilmont 80:8e73be2a2ac1 726
emilmont 80:8e73be2a2ac1 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
emilmont 80:8e73be2a2ac1 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
emilmont 80:8e73be2a2ac1 729
emilmont 80:8e73be2a2ac1 730 /*@}*/ /* end of group CMSIS_ITM */
emilmont 80:8e73be2a2ac1 731
emilmont 80:8e73be2a2ac1 732
emilmont 80:8e73be2a2ac1 733 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
emilmont 80:8e73be2a2ac1 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
emilmont 80:8e73be2a2ac1 736 @{
emilmont 80:8e73be2a2ac1 737 */
emilmont 80:8e73be2a2ac1 738
emilmont 80:8e73be2a2ac1 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
emilmont 80:8e73be2a2ac1 740 */
emilmont 80:8e73be2a2ac1 741 typedef struct
emilmont 80:8e73be2a2ac1 742 {
emilmont 80:8e73be2a2ac1 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
emilmont 80:8e73be2a2ac1 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
emilmont 80:8e73be2a2ac1 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
emilmont 80:8e73be2a2ac1 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
emilmont 80:8e73be2a2ac1 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
emilmont 80:8e73be2a2ac1 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
emilmont 80:8e73be2a2ac1 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
emilmont 80:8e73be2a2ac1 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
emilmont 80:8e73be2a2ac1 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
emilmont 80:8e73be2a2ac1 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
emilmont 80:8e73be2a2ac1 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
emilmont 80:8e73be2a2ac1 754 uint32_t RESERVED0[1];
emilmont 80:8e73be2a2ac1 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
emilmont 80:8e73be2a2ac1 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
emilmont 80:8e73be2a2ac1 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
emilmont 80:8e73be2a2ac1 758 uint32_t RESERVED1[1];
emilmont 80:8e73be2a2ac1 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
emilmont 80:8e73be2a2ac1 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
emilmont 80:8e73be2a2ac1 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
emilmont 80:8e73be2a2ac1 762 uint32_t RESERVED2[1];
emilmont 80:8e73be2a2ac1 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
emilmont 80:8e73be2a2ac1 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
emilmont 80:8e73be2a2ac1 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
emilmont 80:8e73be2a2ac1 766 } DWT_Type;
emilmont 80:8e73be2a2ac1 767
emilmont 80:8e73be2a2ac1 768 /* DWT Control Register Definitions */
emilmont 80:8e73be2a2ac1 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
emilmont 80:8e73be2a2ac1 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
emilmont 80:8e73be2a2ac1 771
emilmont 80:8e73be2a2ac1 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
emilmont 80:8e73be2a2ac1 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
emilmont 80:8e73be2a2ac1 774
emilmont 80:8e73be2a2ac1 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
emilmont 80:8e73be2a2ac1 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
emilmont 80:8e73be2a2ac1 777
emilmont 80:8e73be2a2ac1 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
emilmont 80:8e73be2a2ac1 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
emilmont 80:8e73be2a2ac1 780
emilmont 80:8e73be2a2ac1 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
emilmont 80:8e73be2a2ac1 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
emilmont 80:8e73be2a2ac1 783
emilmont 80:8e73be2a2ac1 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
emilmont 80:8e73be2a2ac1 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
emilmont 80:8e73be2a2ac1 786
emilmont 80:8e73be2a2ac1 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
emilmont 80:8e73be2a2ac1 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
emilmont 80:8e73be2a2ac1 789
emilmont 80:8e73be2a2ac1 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
emilmont 80:8e73be2a2ac1 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
emilmont 80:8e73be2a2ac1 792
emilmont 80:8e73be2a2ac1 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
emilmont 80:8e73be2a2ac1 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
emilmont 80:8e73be2a2ac1 795
emilmont 80:8e73be2a2ac1 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
emilmont 80:8e73be2a2ac1 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
emilmont 80:8e73be2a2ac1 798
emilmont 80:8e73be2a2ac1 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
emilmont 80:8e73be2a2ac1 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
emilmont 80:8e73be2a2ac1 801
emilmont 80:8e73be2a2ac1 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
emilmont 80:8e73be2a2ac1 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
emilmont 80:8e73be2a2ac1 804
emilmont 80:8e73be2a2ac1 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
emilmont 80:8e73be2a2ac1 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
emilmont 80:8e73be2a2ac1 807
emilmont 80:8e73be2a2ac1 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
emilmont 80:8e73be2a2ac1 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
emilmont 80:8e73be2a2ac1 810
emilmont 80:8e73be2a2ac1 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
emilmont 80:8e73be2a2ac1 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
emilmont 80:8e73be2a2ac1 813
emilmont 80:8e73be2a2ac1 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
emilmont 80:8e73be2a2ac1 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
emilmont 80:8e73be2a2ac1 816
emilmont 80:8e73be2a2ac1 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
emilmont 80:8e73be2a2ac1 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
emilmont 80:8e73be2a2ac1 819
emilmont 80:8e73be2a2ac1 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
emilmont 80:8e73be2a2ac1 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
emilmont 80:8e73be2a2ac1 822
emilmont 80:8e73be2a2ac1 823 /* DWT CPI Count Register Definitions */
emilmont 80:8e73be2a2ac1 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
emilmont 80:8e73be2a2ac1 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
emilmont 80:8e73be2a2ac1 826
emilmont 80:8e73be2a2ac1 827 /* DWT Exception Overhead Count Register Definitions */
emilmont 80:8e73be2a2ac1 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
emilmont 80:8e73be2a2ac1 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
emilmont 80:8e73be2a2ac1 830
emilmont 80:8e73be2a2ac1 831 /* DWT Sleep Count Register Definitions */
emilmont 80:8e73be2a2ac1 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
emilmont 80:8e73be2a2ac1 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
emilmont 80:8e73be2a2ac1 834
emilmont 80:8e73be2a2ac1 835 /* DWT LSU Count Register Definitions */
emilmont 80:8e73be2a2ac1 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
emilmont 80:8e73be2a2ac1 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
emilmont 80:8e73be2a2ac1 838
emilmont 80:8e73be2a2ac1 839 /* DWT Folded-instruction Count Register Definitions */
emilmont 80:8e73be2a2ac1 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
emilmont 80:8e73be2a2ac1 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
emilmont 80:8e73be2a2ac1 842
emilmont 80:8e73be2a2ac1 843 /* DWT Comparator Mask Register Definitions */
emilmont 80:8e73be2a2ac1 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
emilmont 80:8e73be2a2ac1 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
emilmont 80:8e73be2a2ac1 846
emilmont 80:8e73be2a2ac1 847 /* DWT Comparator Function Register Definitions */
emilmont 80:8e73be2a2ac1 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
emilmont 80:8e73be2a2ac1 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
emilmont 80:8e73be2a2ac1 850
emilmont 80:8e73be2a2ac1 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
emilmont 80:8e73be2a2ac1 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
emilmont 80:8e73be2a2ac1 853
emilmont 80:8e73be2a2ac1 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
emilmont 80:8e73be2a2ac1 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
emilmont 80:8e73be2a2ac1 856
emilmont 80:8e73be2a2ac1 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
emilmont 80:8e73be2a2ac1 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
emilmont 80:8e73be2a2ac1 859
emilmont 80:8e73be2a2ac1 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
emilmont 80:8e73be2a2ac1 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
emilmont 80:8e73be2a2ac1 862
emilmont 80:8e73be2a2ac1 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
emilmont 80:8e73be2a2ac1 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
emilmont 80:8e73be2a2ac1 865
emilmont 80:8e73be2a2ac1 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
emilmont 80:8e73be2a2ac1 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
emilmont 80:8e73be2a2ac1 868
emilmont 80:8e73be2a2ac1 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
emilmont 80:8e73be2a2ac1 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
emilmont 80:8e73be2a2ac1 871
emilmont 80:8e73be2a2ac1 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
emilmont 80:8e73be2a2ac1 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
emilmont 80:8e73be2a2ac1 874
emilmont 80:8e73be2a2ac1 875 /*@}*/ /* end of group CMSIS_DWT */
emilmont 80:8e73be2a2ac1 876
emilmont 80:8e73be2a2ac1 877
emilmont 80:8e73be2a2ac1 878 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
emilmont 80:8e73be2a2ac1 880 \brief Type definitions for the Trace Port Interface (TPI)
emilmont 80:8e73be2a2ac1 881 @{
emilmont 80:8e73be2a2ac1 882 */
emilmont 80:8e73be2a2ac1 883
emilmont 80:8e73be2a2ac1 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
emilmont 80:8e73be2a2ac1 885 */
emilmont 80:8e73be2a2ac1 886 typedef struct
emilmont 80:8e73be2a2ac1 887 {
emilmont 80:8e73be2a2ac1 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
emilmont 80:8e73be2a2ac1 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
emilmont 80:8e73be2a2ac1 890 uint32_t RESERVED0[2];
emilmont 80:8e73be2a2ac1 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
emilmont 80:8e73be2a2ac1 892 uint32_t RESERVED1[55];
emilmont 80:8e73be2a2ac1 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
emilmont 80:8e73be2a2ac1 894 uint32_t RESERVED2[131];
emilmont 80:8e73be2a2ac1 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
emilmont 80:8e73be2a2ac1 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
emilmont 80:8e73be2a2ac1 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
emilmont 80:8e73be2a2ac1 898 uint32_t RESERVED3[759];
emilmont 80:8e73be2a2ac1 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
emilmont 80:8e73be2a2ac1 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
emilmont 80:8e73be2a2ac1 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
emilmont 80:8e73be2a2ac1 902 uint32_t RESERVED4[1];
emilmont 80:8e73be2a2ac1 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
emilmont 80:8e73be2a2ac1 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
emilmont 80:8e73be2a2ac1 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
emilmont 80:8e73be2a2ac1 906 uint32_t RESERVED5[39];
emilmont 80:8e73be2a2ac1 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
emilmont 80:8e73be2a2ac1 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
emilmont 80:8e73be2a2ac1 909 uint32_t RESERVED7[8];
emilmont 80:8e73be2a2ac1 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
emilmont 80:8e73be2a2ac1 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
emilmont 80:8e73be2a2ac1 912 } TPI_Type;
emilmont 80:8e73be2a2ac1 913
emilmont 80:8e73be2a2ac1 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
emilmont 80:8e73be2a2ac1 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
emilmont 80:8e73be2a2ac1 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
emilmont 80:8e73be2a2ac1 917
emilmont 80:8e73be2a2ac1 918 /* TPI Selected Pin Protocol Register Definitions */
emilmont 80:8e73be2a2ac1 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
emilmont 80:8e73be2a2ac1 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
emilmont 80:8e73be2a2ac1 921
emilmont 80:8e73be2a2ac1 922 /* TPI Formatter and Flush Status Register Definitions */
emilmont 80:8e73be2a2ac1 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
emilmont 80:8e73be2a2ac1 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
emilmont 80:8e73be2a2ac1 925
emilmont 80:8e73be2a2ac1 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
emilmont 80:8e73be2a2ac1 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
emilmont 80:8e73be2a2ac1 928
emilmont 80:8e73be2a2ac1 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
emilmont 80:8e73be2a2ac1 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
emilmont 80:8e73be2a2ac1 931
emilmont 80:8e73be2a2ac1 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
emilmont 80:8e73be2a2ac1 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
emilmont 80:8e73be2a2ac1 934
emilmont 80:8e73be2a2ac1 935 /* TPI Formatter and Flush Control Register Definitions */
emilmont 80:8e73be2a2ac1 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
emilmont 80:8e73be2a2ac1 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
emilmont 80:8e73be2a2ac1 938
emilmont 80:8e73be2a2ac1 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
emilmont 80:8e73be2a2ac1 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
emilmont 80:8e73be2a2ac1 941
emilmont 80:8e73be2a2ac1 942 /* TPI TRIGGER Register Definitions */
emilmont 80:8e73be2a2ac1 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
emilmont 80:8e73be2a2ac1 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
emilmont 80:8e73be2a2ac1 945
emilmont 80:8e73be2a2ac1 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
emilmont 80:8e73be2a2ac1 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
emilmont 80:8e73be2a2ac1 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
emilmont 80:8e73be2a2ac1 949
emilmont 80:8e73be2a2ac1 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
emilmont 80:8e73be2a2ac1 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
emilmont 80:8e73be2a2ac1 952
emilmont 80:8e73be2a2ac1 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
emilmont 80:8e73be2a2ac1 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
emilmont 80:8e73be2a2ac1 955
emilmont 80:8e73be2a2ac1 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
emilmont 80:8e73be2a2ac1 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
emilmont 80:8e73be2a2ac1 958
emilmont 80:8e73be2a2ac1 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
emilmont 80:8e73be2a2ac1 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
emilmont 80:8e73be2a2ac1 961
emilmont 80:8e73be2a2ac1 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
emilmont 80:8e73be2a2ac1 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
emilmont 80:8e73be2a2ac1 964
emilmont 80:8e73be2a2ac1 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
emilmont 80:8e73be2a2ac1 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
emilmont 80:8e73be2a2ac1 967
emilmont 80:8e73be2a2ac1 968 /* TPI ITATBCTR2 Register Definitions */
emilmont 80:8e73be2a2ac1 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
emilmont 80:8e73be2a2ac1 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
emilmont 80:8e73be2a2ac1 971
emilmont 80:8e73be2a2ac1 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
emilmont 80:8e73be2a2ac1 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
emilmont 80:8e73be2a2ac1 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
emilmont 80:8e73be2a2ac1 975
emilmont 80:8e73be2a2ac1 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
emilmont 80:8e73be2a2ac1 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
emilmont 80:8e73be2a2ac1 978
emilmont 80:8e73be2a2ac1 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
emilmont 80:8e73be2a2ac1 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
emilmont 80:8e73be2a2ac1 981
emilmont 80:8e73be2a2ac1 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
emilmont 80:8e73be2a2ac1 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
emilmont 80:8e73be2a2ac1 984
emilmont 80:8e73be2a2ac1 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
emilmont 80:8e73be2a2ac1 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
emilmont 80:8e73be2a2ac1 987
emilmont 80:8e73be2a2ac1 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
emilmont 80:8e73be2a2ac1 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
emilmont 80:8e73be2a2ac1 990
emilmont 80:8e73be2a2ac1 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
emilmont 80:8e73be2a2ac1 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
emilmont 80:8e73be2a2ac1 993
emilmont 80:8e73be2a2ac1 994 /* TPI ITATBCTR0 Register Definitions */
emilmont 80:8e73be2a2ac1 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
emilmont 80:8e73be2a2ac1 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
emilmont 80:8e73be2a2ac1 997
emilmont 80:8e73be2a2ac1 998 /* TPI Integration Mode Control Register Definitions */
emilmont 80:8e73be2a2ac1 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
emilmont 80:8e73be2a2ac1 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
emilmont 80:8e73be2a2ac1 1001
emilmont 80:8e73be2a2ac1 1002 /* TPI DEVID Register Definitions */
emilmont 80:8e73be2a2ac1 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
emilmont 80:8e73be2a2ac1 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
emilmont 80:8e73be2a2ac1 1005
emilmont 80:8e73be2a2ac1 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
emilmont 80:8e73be2a2ac1 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
emilmont 80:8e73be2a2ac1 1008
emilmont 80:8e73be2a2ac1 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
emilmont 80:8e73be2a2ac1 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
emilmont 80:8e73be2a2ac1 1011
emilmont 80:8e73be2a2ac1 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
emilmont 80:8e73be2a2ac1 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
emilmont 80:8e73be2a2ac1 1014
emilmont 80:8e73be2a2ac1 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
emilmont 80:8e73be2a2ac1 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
emilmont 80:8e73be2a2ac1 1017
emilmont 80:8e73be2a2ac1 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
emilmont 80:8e73be2a2ac1 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
emilmont 80:8e73be2a2ac1 1020
emilmont 80:8e73be2a2ac1 1021 /* TPI DEVTYPE Register Definitions */
emilmont 80:8e73be2a2ac1 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
emilmont 80:8e73be2a2ac1 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
emilmont 80:8e73be2a2ac1 1024
emilmont 80:8e73be2a2ac1 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
emilmont 80:8e73be2a2ac1 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
emilmont 80:8e73be2a2ac1 1027
emilmont 80:8e73be2a2ac1 1028 /*@}*/ /* end of group CMSIS_TPI */
emilmont 80:8e73be2a2ac1 1029
emilmont 80:8e73be2a2ac1 1030
emilmont 80:8e73be2a2ac1 1031 #if (__MPU_PRESENT == 1)
emilmont 80:8e73be2a2ac1 1032 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 80:8e73be2a2ac1 1034 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 80:8e73be2a2ac1 1035 @{
emilmont 80:8e73be2a2ac1 1036 */
emilmont 80:8e73be2a2ac1 1037
emilmont 80:8e73be2a2ac1 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 80:8e73be2a2ac1 1039 */
emilmont 80:8e73be2a2ac1 1040 typedef struct
emilmont 80:8e73be2a2ac1 1041 {
emilmont 80:8e73be2a2ac1 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 80:8e73be2a2ac1 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 80:8e73be2a2ac1 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 80:8e73be2a2ac1 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 80:8e73be2a2ac1 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
emilmont 80:8e73be2a2ac1 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
emilmont 80:8e73be2a2ac1 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
emilmont 80:8e73be2a2ac1 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 1053 } MPU_Type;
emilmont 80:8e73be2a2ac1 1054
emilmont 80:8e73be2a2ac1 1055 /* MPU Type Register */
emilmont 80:8e73be2a2ac1 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 80:8e73be2a2ac1 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 80:8e73be2a2ac1 1058
emilmont 80:8e73be2a2ac1 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 80:8e73be2a2ac1 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 80:8e73be2a2ac1 1061
emilmont 80:8e73be2a2ac1 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
emilmont 80:8e73be2a2ac1 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
emilmont 80:8e73be2a2ac1 1064
emilmont 80:8e73be2a2ac1 1065 /* MPU Control Register */
emilmont 80:8e73be2a2ac1 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 80:8e73be2a2ac1 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 80:8e73be2a2ac1 1068
emilmont 80:8e73be2a2ac1 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 80:8e73be2a2ac1 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 80:8e73be2a2ac1 1071
emilmont 80:8e73be2a2ac1 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
emilmont 80:8e73be2a2ac1 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 1074
emilmont 80:8e73be2a2ac1 1075 /* MPU Region Number Register */
emilmont 80:8e73be2a2ac1 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
emilmont 80:8e73be2a2ac1 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
emilmont 80:8e73be2a2ac1 1078
emilmont 80:8e73be2a2ac1 1079 /* MPU Region Base Address Register */
emilmont 80:8e73be2a2ac1 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
emilmont 80:8e73be2a2ac1 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 80:8e73be2a2ac1 1082
emilmont 80:8e73be2a2ac1 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 80:8e73be2a2ac1 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 80:8e73be2a2ac1 1085
emilmont 80:8e73be2a2ac1 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
emilmont 80:8e73be2a2ac1 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
emilmont 80:8e73be2a2ac1 1088
emilmont 80:8e73be2a2ac1 1089 /* MPU Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 80:8e73be2a2ac1 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 80:8e73be2a2ac1 1092
emilmont 80:8e73be2a2ac1 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 80:8e73be2a2ac1 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 80:8e73be2a2ac1 1095
emilmont 80:8e73be2a2ac1 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 80:8e73be2a2ac1 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 80:8e73be2a2ac1 1098
emilmont 80:8e73be2a2ac1 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 80:8e73be2a2ac1 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 80:8e73be2a2ac1 1101
emilmont 80:8e73be2a2ac1 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 80:8e73be2a2ac1 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 80:8e73be2a2ac1 1104
emilmont 80:8e73be2a2ac1 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 80:8e73be2a2ac1 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 80:8e73be2a2ac1 1107
emilmont 80:8e73be2a2ac1 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 80:8e73be2a2ac1 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 80:8e73be2a2ac1 1110
emilmont 80:8e73be2a2ac1 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 80:8e73be2a2ac1 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 80:8e73be2a2ac1 1113
emilmont 80:8e73be2a2ac1 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 80:8e73be2a2ac1 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 80:8e73be2a2ac1 1116
emilmont 80:8e73be2a2ac1 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
emilmont 80:8e73be2a2ac1 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 80:8e73be2a2ac1 1119
emilmont 80:8e73be2a2ac1 1120 /*@} end of group CMSIS_MPU */
emilmont 80:8e73be2a2ac1 1121 #endif
emilmont 80:8e73be2a2ac1 1122
emilmont 80:8e73be2a2ac1 1123
emilmont 80:8e73be2a2ac1 1124 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 80:8e73be2a2ac1 1126 \brief Type definitions for the Core Debug Registers
emilmont 80:8e73be2a2ac1 1127 @{
emilmont 80:8e73be2a2ac1 1128 */
emilmont 80:8e73be2a2ac1 1129
emilmont 80:8e73be2a2ac1 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont 80:8e73be2a2ac1 1131 */
emilmont 80:8e73be2a2ac1 1132 typedef struct
emilmont 80:8e73be2a2ac1 1133 {
emilmont 80:8e73be2a2ac1 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
emilmont 80:8e73be2a2ac1 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
emilmont 80:8e73be2a2ac1 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
emilmont 80:8e73be2a2ac1 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
emilmont 80:8e73be2a2ac1 1138 } CoreDebug_Type;
emilmont 80:8e73be2a2ac1 1139
emilmont 80:8e73be2a2ac1 1140 /* Debug Halting Control and Status Register */
emilmont 80:8e73be2a2ac1 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
emilmont 80:8e73be2a2ac1 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
emilmont 80:8e73be2a2ac1 1143
emilmont 80:8e73be2a2ac1 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
emilmont 80:8e73be2a2ac1 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
emilmont 80:8e73be2a2ac1 1146
emilmont 80:8e73be2a2ac1 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
emilmont 80:8e73be2a2ac1 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
emilmont 80:8e73be2a2ac1 1149
emilmont 80:8e73be2a2ac1 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
emilmont 80:8e73be2a2ac1 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
emilmont 80:8e73be2a2ac1 1152
emilmont 80:8e73be2a2ac1 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
emilmont 80:8e73be2a2ac1 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
emilmont 80:8e73be2a2ac1 1155
emilmont 80:8e73be2a2ac1 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
emilmont 80:8e73be2a2ac1 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
emilmont 80:8e73be2a2ac1 1158
emilmont 80:8e73be2a2ac1 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
emilmont 80:8e73be2a2ac1 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
emilmont 80:8e73be2a2ac1 1161
emilmont 80:8e73be2a2ac1 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
emilmont 80:8e73be2a2ac1 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
emilmont 80:8e73be2a2ac1 1164
emilmont 80:8e73be2a2ac1 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
emilmont 80:8e73be2a2ac1 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
emilmont 80:8e73be2a2ac1 1167
emilmont 80:8e73be2a2ac1 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
emilmont 80:8e73be2a2ac1 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
emilmont 80:8e73be2a2ac1 1170
emilmont 80:8e73be2a2ac1 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
emilmont 80:8e73be2a2ac1 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
emilmont 80:8e73be2a2ac1 1173
emilmont 80:8e73be2a2ac1 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
emilmont 80:8e73be2a2ac1 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
emilmont 80:8e73be2a2ac1 1176
emilmont 80:8e73be2a2ac1 1177 /* Debug Core Register Selector Register */
emilmont 80:8e73be2a2ac1 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
emilmont 80:8e73be2a2ac1 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
emilmont 80:8e73be2a2ac1 1180
emilmont 80:8e73be2a2ac1 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
emilmont 80:8e73be2a2ac1 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
emilmont 80:8e73be2a2ac1 1183
emilmont 80:8e73be2a2ac1 1184 /* Debug Exception and Monitor Control Register */
emilmont 80:8e73be2a2ac1 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
emilmont 80:8e73be2a2ac1 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
emilmont 80:8e73be2a2ac1 1187
emilmont 80:8e73be2a2ac1 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
emilmont 80:8e73be2a2ac1 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
emilmont 80:8e73be2a2ac1 1190
emilmont 80:8e73be2a2ac1 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
emilmont 80:8e73be2a2ac1 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
emilmont 80:8e73be2a2ac1 1193
emilmont 80:8e73be2a2ac1 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
emilmont 80:8e73be2a2ac1 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
emilmont 80:8e73be2a2ac1 1196
emilmont 80:8e73be2a2ac1 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
emilmont 80:8e73be2a2ac1 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
emilmont 80:8e73be2a2ac1 1199
emilmont 80:8e73be2a2ac1 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
emilmont 80:8e73be2a2ac1 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
emilmont 80:8e73be2a2ac1 1202
emilmont 80:8e73be2a2ac1 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
emilmont 80:8e73be2a2ac1 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
emilmont 80:8e73be2a2ac1 1205
emilmont 80:8e73be2a2ac1 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
emilmont 80:8e73be2a2ac1 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
emilmont 80:8e73be2a2ac1 1208
emilmont 80:8e73be2a2ac1 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
emilmont 80:8e73be2a2ac1 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
emilmont 80:8e73be2a2ac1 1211
emilmont 80:8e73be2a2ac1 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
emilmont 80:8e73be2a2ac1 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
emilmont 80:8e73be2a2ac1 1214
emilmont 80:8e73be2a2ac1 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
emilmont 80:8e73be2a2ac1 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
emilmont 80:8e73be2a2ac1 1217
emilmont 80:8e73be2a2ac1 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
emilmont 80:8e73be2a2ac1 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
emilmont 80:8e73be2a2ac1 1220
emilmont 80:8e73be2a2ac1 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
emilmont 80:8e73be2a2ac1 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
emilmont 80:8e73be2a2ac1 1223
emilmont 80:8e73be2a2ac1 1224 /*@} end of group CMSIS_CoreDebug */
emilmont 80:8e73be2a2ac1 1225
emilmont 80:8e73be2a2ac1 1226
emilmont 80:8e73be2a2ac1 1227 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 1228 \defgroup CMSIS_core_base Core Definitions
emilmont 80:8e73be2a2ac1 1229 \brief Definitions for base addresses, unions, and structures.
emilmont 80:8e73be2a2ac1 1230 @{
emilmont 80:8e73be2a2ac1 1231 */
emilmont 80:8e73be2a2ac1 1232
emilmont 80:8e73be2a2ac1 1233 /* Memory mapping of Cortex-M3 Hardware */
emilmont 80:8e73be2a2ac1 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 80:8e73be2a2ac1 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
emilmont 80:8e73be2a2ac1 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
emilmont 80:8e73be2a2ac1 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
emilmont 80:8e73be2a2ac1 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
emilmont 80:8e73be2a2ac1 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 80:8e73be2a2ac1 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 80:8e73be2a2ac1 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 80:8e73be2a2ac1 1242
emilmont 80:8e73be2a2ac1 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
emilmont 80:8e73be2a2ac1 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 80:8e73be2a2ac1 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 80:8e73be2a2ac1 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 80:8e73be2a2ac1 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
emilmont 80:8e73be2a2ac1 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
emilmont 80:8e73be2a2ac1 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
emilmont 80:8e73be2a2ac1 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
emilmont 80:8e73be2a2ac1 1251
emilmont 80:8e73be2a2ac1 1252 #if (__MPU_PRESENT == 1)
emilmont 80:8e73be2a2ac1 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 80:8e73be2a2ac1 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 80:8e73be2a2ac1 1255 #endif
emilmont 80:8e73be2a2ac1 1256
emilmont 80:8e73be2a2ac1 1257 /*@} */
emilmont 80:8e73be2a2ac1 1258
emilmont 80:8e73be2a2ac1 1259
emilmont 80:8e73be2a2ac1 1260
emilmont 80:8e73be2a2ac1 1261 /*******************************************************************************
emilmont 80:8e73be2a2ac1 1262 * Hardware Abstraction Layer
emilmont 80:8e73be2a2ac1 1263 Core Function Interface contains:
emilmont 80:8e73be2a2ac1 1264 - Core NVIC Functions
emilmont 80:8e73be2a2ac1 1265 - Core SysTick Functions
emilmont 80:8e73be2a2ac1 1266 - Core Debug Functions
emilmont 80:8e73be2a2ac1 1267 - Core Register Access Functions
emilmont 80:8e73be2a2ac1 1268 ******************************************************************************/
emilmont 80:8e73be2a2ac1 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 80:8e73be2a2ac1 1270 */
emilmont 80:8e73be2a2ac1 1271
emilmont 80:8e73be2a2ac1 1272
emilmont 80:8e73be2a2ac1 1273
emilmont 80:8e73be2a2ac1 1274 /* ########################## NVIC functions #################################### */
emilmont 80:8e73be2a2ac1 1275 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 80:8e73be2a2ac1 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 80:8e73be2a2ac1 1278 @{
emilmont 80:8e73be2a2ac1 1279 */
emilmont 80:8e73be2a2ac1 1280
emilmont 80:8e73be2a2ac1 1281 /** \brief Set Priority Grouping
emilmont 80:8e73be2a2ac1 1282
emilmont 80:8e73be2a2ac1 1283 The function sets the priority grouping field using the required unlock sequence.
emilmont 80:8e73be2a2ac1 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont 80:8e73be2a2ac1 1285 Only values from 0..7 are used.
emilmont 80:8e73be2a2ac1 1286 In case of a conflict between priority grouping and available
emilmont 80:8e73be2a2ac1 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont 80:8e73be2a2ac1 1288
emilmont 80:8e73be2a2ac1 1289 \param [in] PriorityGroup Priority grouping field.
emilmont 80:8e73be2a2ac1 1290 */
emilmont 80:8e73be2a2ac1 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont 80:8e73be2a2ac1 1292 {
emilmont 80:8e73be2a2ac1 1293 uint32_t reg_value;
emilmont 80:8e73be2a2ac1 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
emilmont 80:8e73be2a2ac1 1295
emilmont 80:8e73be2a2ac1 1296 reg_value = SCB->AIRCR; /* read old register configuration */
emilmont 80:8e73be2a2ac1 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
emilmont 80:8e73be2a2ac1 1298 reg_value = (reg_value |
emilmont 80:8e73be2a2ac1 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 80:8e73be2a2ac1 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
emilmont 80:8e73be2a2ac1 1301 SCB->AIRCR = reg_value;
emilmont 80:8e73be2a2ac1 1302 }
emilmont 80:8e73be2a2ac1 1303
emilmont 80:8e73be2a2ac1 1304
emilmont 80:8e73be2a2ac1 1305 /** \brief Get Priority Grouping
emilmont 80:8e73be2a2ac1 1306
emilmont 80:8e73be2a2ac1 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont 80:8e73be2a2ac1 1308
emilmont 80:8e73be2a2ac1 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont 80:8e73be2a2ac1 1310 */
emilmont 80:8e73be2a2ac1 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont 80:8e73be2a2ac1 1312 {
emilmont 80:8e73be2a2ac1 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
emilmont 80:8e73be2a2ac1 1314 }
emilmont 80:8e73be2a2ac1 1315
emilmont 80:8e73be2a2ac1 1316
emilmont 80:8e73be2a2ac1 1317 /** \brief Enable External Interrupt
emilmont 80:8e73be2a2ac1 1318
emilmont 80:8e73be2a2ac1 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 1320
emilmont 80:8e73be2a2ac1 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 1322 */
emilmont 80:8e73be2a2ac1 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1324 {
emilmont 80:8e73be2a2ac1 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
emilmont 80:8e73be2a2ac1 1326 }
emilmont 80:8e73be2a2ac1 1327
emilmont 80:8e73be2a2ac1 1328
emilmont 80:8e73be2a2ac1 1329 /** \brief Disable External Interrupt
emilmont 80:8e73be2a2ac1 1330
emilmont 80:8e73be2a2ac1 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 1332
emilmont 80:8e73be2a2ac1 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 1334 */
emilmont 80:8e73be2a2ac1 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1336 {
emilmont 80:8e73be2a2ac1 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
emilmont 80:8e73be2a2ac1 1338 }
emilmont 80:8e73be2a2ac1 1339
emilmont 80:8e73be2a2ac1 1340
emilmont 80:8e73be2a2ac1 1341 /** \brief Get Pending Interrupt
emilmont 80:8e73be2a2ac1 1342
emilmont 80:8e73be2a2ac1 1343 The function reads the pending register in the NVIC and returns the pending bit
emilmont 80:8e73be2a2ac1 1344 for the specified interrupt.
emilmont 80:8e73be2a2ac1 1345
emilmont 80:8e73be2a2ac1 1346 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 1347
emilmont 80:8e73be2a2ac1 1348 \return 0 Interrupt status is not pending.
emilmont 80:8e73be2a2ac1 1349 \return 1 Interrupt status is pending.
emilmont 80:8e73be2a2ac1 1350 */
emilmont 80:8e73be2a2ac1 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1352 {
emilmont 80:8e73be2a2ac1 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
emilmont 80:8e73be2a2ac1 1354 }
emilmont 80:8e73be2a2ac1 1355
emilmont 80:8e73be2a2ac1 1356
emilmont 80:8e73be2a2ac1 1357 /** \brief Set Pending Interrupt
emilmont 80:8e73be2a2ac1 1358
emilmont 80:8e73be2a2ac1 1359 The function sets the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 1360
emilmont 80:8e73be2a2ac1 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 1362 */
emilmont 80:8e73be2a2ac1 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1364 {
emilmont 80:8e73be2a2ac1 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
emilmont 80:8e73be2a2ac1 1366 }
emilmont 80:8e73be2a2ac1 1367
emilmont 80:8e73be2a2ac1 1368
emilmont 80:8e73be2a2ac1 1369 /** \brief Clear Pending Interrupt
emilmont 80:8e73be2a2ac1 1370
emilmont 80:8e73be2a2ac1 1371 The function clears the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 1372
emilmont 80:8e73be2a2ac1 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 1374 */
emilmont 80:8e73be2a2ac1 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1376 {
emilmont 80:8e73be2a2ac1 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 80:8e73be2a2ac1 1378 }
emilmont 80:8e73be2a2ac1 1379
emilmont 80:8e73be2a2ac1 1380
emilmont 80:8e73be2a2ac1 1381 /** \brief Get Active Interrupt
emilmont 80:8e73be2a2ac1 1382
emilmont 80:8e73be2a2ac1 1383 The function reads the active register in NVIC and returns the active bit.
emilmont 80:8e73be2a2ac1 1384
emilmont 80:8e73be2a2ac1 1385 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 1386
emilmont 80:8e73be2a2ac1 1387 \return 0 Interrupt status is not active.
emilmont 80:8e73be2a2ac1 1388 \return 1 Interrupt status is active.
emilmont 80:8e73be2a2ac1 1389 */
emilmont 80:8e73be2a2ac1 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1391 {
emilmont 80:8e73be2a2ac1 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
emilmont 80:8e73be2a2ac1 1393 }
emilmont 80:8e73be2a2ac1 1394
emilmont 80:8e73be2a2ac1 1395
emilmont 80:8e73be2a2ac1 1396 /** \brief Set Interrupt Priority
emilmont 80:8e73be2a2ac1 1397
emilmont 80:8e73be2a2ac1 1398 The function sets the priority of an interrupt.
emilmont 80:8e73be2a2ac1 1399
emilmont 80:8e73be2a2ac1 1400 \note The priority cannot be set for every core interrupt.
emilmont 80:8e73be2a2ac1 1401
emilmont 80:8e73be2a2ac1 1402 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 1403 \param [in] priority Priority to set.
emilmont 80:8e73be2a2ac1 1404 */
emilmont 80:8e73be2a2ac1 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 80:8e73be2a2ac1 1406 {
emilmont 80:8e73be2a2ac1 1407 if(IRQn < 0) {
emilmont 80:8e73be2a2ac1 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
emilmont 80:8e73be2a2ac1 1409 else {
emilmont 80:8e73be2a2ac1 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
emilmont 80:8e73be2a2ac1 1411 }
emilmont 80:8e73be2a2ac1 1412
emilmont 80:8e73be2a2ac1 1413
emilmont 80:8e73be2a2ac1 1414 /** \brief Get Interrupt Priority
emilmont 80:8e73be2a2ac1 1415
emilmont 80:8e73be2a2ac1 1416 The function reads the priority of an interrupt. The interrupt
emilmont 80:8e73be2a2ac1 1417 number can be positive to specify an external (device specific)
emilmont 80:8e73be2a2ac1 1418 interrupt, or negative to specify an internal (core) interrupt.
emilmont 80:8e73be2a2ac1 1419
emilmont 80:8e73be2a2ac1 1420
emilmont 80:8e73be2a2ac1 1421 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 80:8e73be2a2ac1 1423 priority bits of the microcontroller.
emilmont 80:8e73be2a2ac1 1424 */
emilmont 80:8e73be2a2ac1 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 1426 {
emilmont 80:8e73be2a2ac1 1427
emilmont 80:8e73be2a2ac1 1428 if(IRQn < 0) {
emilmont 80:8e73be2a2ac1 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
emilmont 80:8e73be2a2ac1 1430 else {
emilmont 80:8e73be2a2ac1 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 80:8e73be2a2ac1 1432 }
emilmont 80:8e73be2a2ac1 1433
emilmont 80:8e73be2a2ac1 1434
emilmont 80:8e73be2a2ac1 1435 /** \brief Encode Priority
emilmont 80:8e73be2a2ac1 1436
emilmont 80:8e73be2a2ac1 1437 The function encodes the priority for an interrupt with the given priority group,
emilmont 80:8e73be2a2ac1 1438 preemptive priority value, and subpriority value.
emilmont 80:8e73be2a2ac1 1439 In case of a conflict between priority grouping and available
emilmont 80:8e73be2a2ac1 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
emilmont 80:8e73be2a2ac1 1441
emilmont 80:8e73be2a2ac1 1442 \param [in] PriorityGroup Used priority group.
emilmont 80:8e73be2a2ac1 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont 80:8e73be2a2ac1 1444 \param [in] SubPriority Subpriority value (starting from 0).
emilmont 80:8e73be2a2ac1 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont 80:8e73be2a2ac1 1446 */
emilmont 80:8e73be2a2ac1 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont 80:8e73be2a2ac1 1448 {
emilmont 80:8e73be2a2ac1 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont 80:8e73be2a2ac1 1450 uint32_t PreemptPriorityBits;
emilmont 80:8e73be2a2ac1 1451 uint32_t SubPriorityBits;
emilmont 80:8e73be2a2ac1 1452
emilmont 80:8e73be2a2ac1 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont 80:8e73be2a2ac1 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont 80:8e73be2a2ac1 1455
emilmont 80:8e73be2a2ac1 1456 return (
emilmont 80:8e73be2a2ac1 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
emilmont 80:8e73be2a2ac1 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
emilmont 80:8e73be2a2ac1 1459 );
emilmont 80:8e73be2a2ac1 1460 }
emilmont 80:8e73be2a2ac1 1461
emilmont 80:8e73be2a2ac1 1462
emilmont 80:8e73be2a2ac1 1463 /** \brief Decode Priority
emilmont 80:8e73be2a2ac1 1464
emilmont 80:8e73be2a2ac1 1465 The function decodes an interrupt priority value with a given priority group to
emilmont 80:8e73be2a2ac1 1466 preemptive priority value and subpriority value.
emilmont 80:8e73be2a2ac1 1467 In case of a conflict between priority grouping and available
emilmont 80:8e73be2a2ac1 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont 80:8e73be2a2ac1 1469
emilmont 80:8e73be2a2ac1 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont 80:8e73be2a2ac1 1471 \param [in] PriorityGroup Used priority group.
emilmont 80:8e73be2a2ac1 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont 80:8e73be2a2ac1 1473 \param [out] pSubPriority Subpriority value (starting from 0).
emilmont 80:8e73be2a2ac1 1474 */
emilmont 80:8e73be2a2ac1 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont 80:8e73be2a2ac1 1476 {
emilmont 80:8e73be2a2ac1 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont 80:8e73be2a2ac1 1478 uint32_t PreemptPriorityBits;
emilmont 80:8e73be2a2ac1 1479 uint32_t SubPriorityBits;
emilmont 80:8e73be2a2ac1 1480
emilmont 80:8e73be2a2ac1 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont 80:8e73be2a2ac1 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont 80:8e73be2a2ac1 1483
emilmont 80:8e73be2a2ac1 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
emilmont 80:8e73be2a2ac1 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
emilmont 80:8e73be2a2ac1 1486 }
emilmont 80:8e73be2a2ac1 1487
emilmont 80:8e73be2a2ac1 1488
emilmont 80:8e73be2a2ac1 1489 /** \brief System Reset
emilmont 80:8e73be2a2ac1 1490
emilmont 80:8e73be2a2ac1 1491 The function initiates a system reset request to reset the MCU.
emilmont 80:8e73be2a2ac1 1492 */
emilmont 80:8e73be2a2ac1 1493 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 80:8e73be2a2ac1 1494 {
emilmont 80:8e73be2a2ac1 1495 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 80:8e73be2a2ac1 1496 buffered write are completed before reset */
emilmont 80:8e73be2a2ac1 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 80:8e73be2a2ac1 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
emilmont 80:8e73be2a2ac1 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
emilmont 80:8e73be2a2ac1 1500 __DSB(); /* Ensure completion of memory access */
emilmont 80:8e73be2a2ac1 1501 while(1); /* wait until reset */
emilmont 80:8e73be2a2ac1 1502 }
emilmont 80:8e73be2a2ac1 1503
emilmont 80:8e73be2a2ac1 1504 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 80:8e73be2a2ac1 1505
emilmont 80:8e73be2a2ac1 1506
emilmont 80:8e73be2a2ac1 1507
emilmont 80:8e73be2a2ac1 1508 /* ################################## SysTick function ############################################ */
emilmont 80:8e73be2a2ac1 1509 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 80:8e73be2a2ac1 1511 \brief Functions that configure the System.
emilmont 80:8e73be2a2ac1 1512 @{
emilmont 80:8e73be2a2ac1 1513 */
emilmont 80:8e73be2a2ac1 1514
emilmont 80:8e73be2a2ac1 1515 #if (__Vendor_SysTickConfig == 0)
emilmont 80:8e73be2a2ac1 1516
emilmont 80:8e73be2a2ac1 1517 /** \brief System Tick Configuration
emilmont 80:8e73be2a2ac1 1518
emilmont 80:8e73be2a2ac1 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 80:8e73be2a2ac1 1520 Counter is in free running mode to generate periodic interrupts.
emilmont 80:8e73be2a2ac1 1521
emilmont 80:8e73be2a2ac1 1522 \param [in] ticks Number of ticks between two interrupts.
emilmont 80:8e73be2a2ac1 1523
emilmont 80:8e73be2a2ac1 1524 \return 0 Function succeeded.
emilmont 80:8e73be2a2ac1 1525 \return 1 Function failed.
emilmont 80:8e73be2a2ac1 1526
emilmont 80:8e73be2a2ac1 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 80:8e73be2a2ac1 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 80:8e73be2a2ac1 1529 must contain a vendor-specific implementation of this function.
emilmont 80:8e73be2a2ac1 1530
emilmont 80:8e73be2a2ac1 1531 */
emilmont 80:8e73be2a2ac1 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 80:8e73be2a2ac1 1533 {
emilmont 80:8e73be2a2ac1 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 80:8e73be2a2ac1 1535
emilmont 80:8e73be2a2ac1 1536 SysTick->LOAD = ticks - 1; /* set reload register */
emilmont 80:8e73be2a2ac1 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 80:8e73be2a2ac1 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 80:8e73be2a2ac1 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 80:8e73be2a2ac1 1540 SysTick_CTRL_TICKINT_Msk |
emilmont 80:8e73be2a2ac1 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 80:8e73be2a2ac1 1542 return (0); /* Function successful */
emilmont 80:8e73be2a2ac1 1543 }
emilmont 80:8e73be2a2ac1 1544
emilmont 80:8e73be2a2ac1 1545 #endif
emilmont 80:8e73be2a2ac1 1546
emilmont 80:8e73be2a2ac1 1547 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 80:8e73be2a2ac1 1548
emilmont 80:8e73be2a2ac1 1549
emilmont 80:8e73be2a2ac1 1550
emilmont 80:8e73be2a2ac1 1551 /* ##################################### Debug In/Output function ########################################### */
emilmont 80:8e73be2a2ac1 1552 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont 80:8e73be2a2ac1 1554 \brief Functions that access the ITM debug interface.
emilmont 80:8e73be2a2ac1 1555 @{
emilmont 80:8e73be2a2ac1 1556 */
emilmont 80:8e73be2a2ac1 1557
emilmont 80:8e73be2a2ac1 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
emilmont 80:8e73be2a2ac1 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
emilmont 80:8e73be2a2ac1 1560
emilmont 80:8e73be2a2ac1 1561
emilmont 80:8e73be2a2ac1 1562 /** \brief ITM Send Character
emilmont 80:8e73be2a2ac1 1563
emilmont 80:8e73be2a2ac1 1564 The function transmits a character via the ITM channel 0, and
emilmont 80:8e73be2a2ac1 1565 \li Just returns when no debugger is connected that has booked the output.
emilmont 80:8e73be2a2ac1 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont 80:8e73be2a2ac1 1567
emilmont 80:8e73be2a2ac1 1568 \param [in] ch Character to transmit.
emilmont 80:8e73be2a2ac1 1569
emilmont 80:8e73be2a2ac1 1570 \returns Character to transmit.
emilmont 80:8e73be2a2ac1 1571 */
emilmont 80:8e73be2a2ac1 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont 80:8e73be2a2ac1 1573 {
emilmont 80:8e73be2a2ac1 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
emilmont 80:8e73be2a2ac1 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
emilmont 80:8e73be2a2ac1 1576 {
emilmont 80:8e73be2a2ac1 1577 while (ITM->PORT[0].u32 == 0);
emilmont 80:8e73be2a2ac1 1578 ITM->PORT[0].u8 = (uint8_t) ch;
emilmont 80:8e73be2a2ac1 1579 }
emilmont 80:8e73be2a2ac1 1580 return (ch);
emilmont 80:8e73be2a2ac1 1581 }
emilmont 80:8e73be2a2ac1 1582
emilmont 80:8e73be2a2ac1 1583
emilmont 80:8e73be2a2ac1 1584 /** \brief ITM Receive Character
emilmont 80:8e73be2a2ac1 1585
emilmont 80:8e73be2a2ac1 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont 80:8e73be2a2ac1 1587
emilmont 80:8e73be2a2ac1 1588 \return Received character.
emilmont 80:8e73be2a2ac1 1589 \return -1 No character pending.
emilmont 80:8e73be2a2ac1 1590 */
emilmont 80:8e73be2a2ac1 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
emilmont 80:8e73be2a2ac1 1592 int32_t ch = -1; /* no character available */
emilmont 80:8e73be2a2ac1 1593
emilmont 80:8e73be2a2ac1 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont 80:8e73be2a2ac1 1595 ch = ITM_RxBuffer;
emilmont 80:8e73be2a2ac1 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont 80:8e73be2a2ac1 1597 }
emilmont 80:8e73be2a2ac1 1598
emilmont 80:8e73be2a2ac1 1599 return (ch);
emilmont 80:8e73be2a2ac1 1600 }
emilmont 80:8e73be2a2ac1 1601
emilmont 80:8e73be2a2ac1 1602
emilmont 80:8e73be2a2ac1 1603 /** \brief ITM Check Character
emilmont 80:8e73be2a2ac1 1604
emilmont 80:8e73be2a2ac1 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont 80:8e73be2a2ac1 1606
emilmont 80:8e73be2a2ac1 1607 \return 0 No character available.
emilmont 80:8e73be2a2ac1 1608 \return 1 Character available.
emilmont 80:8e73be2a2ac1 1609 */
emilmont 80:8e73be2a2ac1 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
emilmont 80:8e73be2a2ac1 1611
emilmont 80:8e73be2a2ac1 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont 80:8e73be2a2ac1 1613 return (0); /* no character available */
emilmont 80:8e73be2a2ac1 1614 } else {
emilmont 80:8e73be2a2ac1 1615 return (1); /* character available */
emilmont 80:8e73be2a2ac1 1616 }
emilmont 80:8e73be2a2ac1 1617 }
emilmont 80:8e73be2a2ac1 1618
emilmont 80:8e73be2a2ac1 1619 /*@} end of CMSIS_core_DebugFunctions */
emilmont 80:8e73be2a2ac1 1620
emilmont 80:8e73be2a2ac1 1621 #endif /* __CORE_CM3_H_DEPENDANT */
emilmont 80:8e73be2a2ac1 1622
emilmont 80:8e73be2a2ac1 1623 #endif /* __CMSIS_GENERIC */
emilmont 80:8e73be2a2ac1 1624
emilmont 80:8e73be2a2ac1 1625 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 1626 }
emilmont 80:8e73be2a2ac1 1627 #endif