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TARGET_NRF51822/core_cm0plus.h@80:8e73be2a2ac1, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 12:21:39 2014 +0000
Revision:
80:8e73be2a2ac1
Child:
110:165afa46840b
First alpha release for the NRF51822 target (to be tested in the online IDE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cm0plus.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
emilmont 80:8e73be2a2ac1 4 * @version V3.20
emilmont 80:8e73be2a2ac1 5 * @date 25. February 2013
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
emilmont 80:8e73be2a2ac1 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #if defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 80:8e73be2a2ac1 40 #endif
emilmont 80:8e73be2a2ac1 41
emilmont 80:8e73be2a2ac1 42 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 43 extern "C" {
emilmont 80:8e73be2a2ac1 44 #endif
emilmont 80:8e73be2a2ac1 45
emilmont 80:8e73be2a2ac1 46 #ifndef __CORE_CM0PLUS_H_GENERIC
emilmont 80:8e73be2a2ac1 47 #define __CORE_CM0PLUS_H_GENERIC
emilmont 80:8e73be2a2ac1 48
emilmont 80:8e73be2a2ac1 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 80:8e73be2a2ac1 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 80:8e73be2a2ac1 51
emilmont 80:8e73be2a2ac1 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 80:8e73be2a2ac1 53 Function definitions in header files are used to allow 'inlining'.
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 80:8e73be2a2ac1 56 Unions are used for effective representation of core registers.
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 80:8e73be2a2ac1 59 Function-like macros are used to allow more efficient code.
emilmont 80:8e73be2a2ac1 60 */
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62
emilmont 80:8e73be2a2ac1 63 /*******************************************************************************
emilmont 80:8e73be2a2ac1 64 * CMSIS definitions
emilmont 80:8e73be2a2ac1 65 ******************************************************************************/
emilmont 80:8e73be2a2ac1 66 /** \ingroup Cortex-M0+
emilmont 80:8e73be2a2ac1 67 @{
emilmont 80:8e73be2a2ac1 68 */
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70 /* CMSIS CM0P definitions */
emilmont 80:8e73be2a2ac1 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 80:8e73be2a2ac1 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
emilmont 80:8e73be2a2ac1 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
emilmont 80:8e73be2a2ac1 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 80:8e73be2a2ac1 75
emilmont 80:8e73be2a2ac1 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 80:8e73be2a2ac1 77
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 82 #define __STATIC_INLINE static __inline
emilmont 80:8e73be2a2ac1 83
emilmont 80:8e73be2a2ac1 84 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 80:8e73be2a2ac1 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 80:8e73be2a2ac1 87 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 88
emilmont 80:8e73be2a2ac1 89 #elif defined ( __GNUC__ )
emilmont 80:8e73be2a2ac1 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 80:8e73be2a2ac1 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 80:8e73be2a2ac1 92 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 93
emilmont 80:8e73be2a2ac1 94 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 97 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 98
emilmont 80:8e73be2a2ac1 99 #endif
emilmont 80:8e73be2a2ac1 100
emilmont 80:8e73be2a2ac1 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 80:8e73be2a2ac1 102 */
emilmont 80:8e73be2a2ac1 103 #define __FPU_USED 0
emilmont 80:8e73be2a2ac1 104
emilmont 80:8e73be2a2ac1 105 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 106 #if defined __TARGET_FPU_VFP
emilmont 80:8e73be2a2ac1 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 108 #endif
emilmont 80:8e73be2a2ac1 109
emilmont 80:8e73be2a2ac1 110 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 111 #if defined __ARMVFP__
emilmont 80:8e73be2a2ac1 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 113 #endif
emilmont 80:8e73be2a2ac1 114
emilmont 80:8e73be2a2ac1 115 #elif defined ( __GNUC__ )
emilmont 80:8e73be2a2ac1 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 80:8e73be2a2ac1 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 118 #endif
emilmont 80:8e73be2a2ac1 119
emilmont 80:8e73be2a2ac1 120 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 121 #if defined __FPU_VFP__
emilmont 80:8e73be2a2ac1 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 123 #endif
emilmont 80:8e73be2a2ac1 124 #endif
emilmont 80:8e73be2a2ac1 125
emilmont 80:8e73be2a2ac1 126 #include <stdint.h> /* standard types definitions */
emilmont 80:8e73be2a2ac1 127 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 80:8e73be2a2ac1 128 #include <core_cmFunc.h> /* Core Function Access */
emilmont 80:8e73be2a2ac1 129
emilmont 80:8e73be2a2ac1 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
emilmont 80:8e73be2a2ac1 131
emilmont 80:8e73be2a2ac1 132 #ifndef __CMSIS_GENERIC
emilmont 80:8e73be2a2ac1 133
emilmont 80:8e73be2a2ac1 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
emilmont 80:8e73be2a2ac1 135 #define __CORE_CM0PLUS_H_DEPENDANT
emilmont 80:8e73be2a2ac1 136
emilmont 80:8e73be2a2ac1 137 /* check device defines and use defaults */
emilmont 80:8e73be2a2ac1 138 #if defined __CHECK_DEVICE_DEFINES
emilmont 80:8e73be2a2ac1 139 #ifndef __CM0PLUS_REV
emilmont 80:8e73be2a2ac1 140 #define __CM0PLUS_REV 0x0000
emilmont 80:8e73be2a2ac1 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 142 #endif
emilmont 80:8e73be2a2ac1 143
emilmont 80:8e73be2a2ac1 144 #ifndef __MPU_PRESENT
emilmont 80:8e73be2a2ac1 145 #define __MPU_PRESENT 0
emilmont 80:8e73be2a2ac1 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 147 #endif
emilmont 80:8e73be2a2ac1 148
emilmont 80:8e73be2a2ac1 149 #ifndef __VTOR_PRESENT
emilmont 80:8e73be2a2ac1 150 #define __VTOR_PRESENT 0
emilmont 80:8e73be2a2ac1 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 152 #endif
emilmont 80:8e73be2a2ac1 153
emilmont 80:8e73be2a2ac1 154 #ifndef __NVIC_PRIO_BITS
emilmont 80:8e73be2a2ac1 155 #define __NVIC_PRIO_BITS 2
emilmont 80:8e73be2a2ac1 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 157 #endif
emilmont 80:8e73be2a2ac1 158
emilmont 80:8e73be2a2ac1 159 #ifndef __Vendor_SysTickConfig
emilmont 80:8e73be2a2ac1 160 #define __Vendor_SysTickConfig 0
emilmont 80:8e73be2a2ac1 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 162 #endif
emilmont 80:8e73be2a2ac1 163 #endif
emilmont 80:8e73be2a2ac1 164
emilmont 80:8e73be2a2ac1 165 /* IO definitions (access restrictions to peripheral registers) */
emilmont 80:8e73be2a2ac1 166 /**
emilmont 80:8e73be2a2ac1 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 80:8e73be2a2ac1 168
emilmont 80:8e73be2a2ac1 169 <strong>IO Type Qualifiers</strong> are used
emilmont 80:8e73be2a2ac1 170 \li to specify the access to peripheral variables.
emilmont 80:8e73be2a2ac1 171 \li for automatic generation of peripheral register debug information.
emilmont 80:8e73be2a2ac1 172 */
emilmont 80:8e73be2a2ac1 173 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 174 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 175 #else
emilmont 80:8e73be2a2ac1 176 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 177 #endif
emilmont 80:8e73be2a2ac1 178 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 80:8e73be2a2ac1 179 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 80:8e73be2a2ac1 180
emilmont 80:8e73be2a2ac1 181 /*@} end of group Cortex-M0+ */
emilmont 80:8e73be2a2ac1 182
emilmont 80:8e73be2a2ac1 183
emilmont 80:8e73be2a2ac1 184
emilmont 80:8e73be2a2ac1 185 /*******************************************************************************
emilmont 80:8e73be2a2ac1 186 * Register Abstraction
emilmont 80:8e73be2a2ac1 187 Core Register contain:
emilmont 80:8e73be2a2ac1 188 - Core Register
emilmont 80:8e73be2a2ac1 189 - Core NVIC Register
emilmont 80:8e73be2a2ac1 190 - Core SCB Register
emilmont 80:8e73be2a2ac1 191 - Core SysTick Register
emilmont 80:8e73be2a2ac1 192 - Core MPU Register
emilmont 80:8e73be2a2ac1 193 ******************************************************************************/
emilmont 80:8e73be2a2ac1 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 80:8e73be2a2ac1 195 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 80:8e73be2a2ac1 196 */
emilmont 80:8e73be2a2ac1 197
emilmont 80:8e73be2a2ac1 198 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 199 \defgroup CMSIS_CORE Status and Control Registers
emilmont 80:8e73be2a2ac1 200 \brief Core Register type definitions.
emilmont 80:8e73be2a2ac1 201 @{
emilmont 80:8e73be2a2ac1 202 */
emilmont 80:8e73be2a2ac1 203
emilmont 80:8e73be2a2ac1 204 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 80:8e73be2a2ac1 205 */
emilmont 80:8e73be2a2ac1 206 typedef union
emilmont 80:8e73be2a2ac1 207 {
emilmont 80:8e73be2a2ac1 208 struct
emilmont 80:8e73be2a2ac1 209 {
emilmont 80:8e73be2a2ac1 210 #if (__CORTEX_M != 0x04)
emilmont 80:8e73be2a2ac1 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 80:8e73be2a2ac1 212 #else
emilmont 80:8e73be2a2ac1 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 80:8e73be2a2ac1 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 80:8e73be2a2ac1 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 80:8e73be2a2ac1 216 #endif
emilmont 80:8e73be2a2ac1 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 80:8e73be2a2ac1 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 222 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 223 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 224 } APSR_Type;
emilmont 80:8e73be2a2ac1 225
emilmont 80:8e73be2a2ac1 226
emilmont 80:8e73be2a2ac1 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 80:8e73be2a2ac1 228 */
emilmont 80:8e73be2a2ac1 229 typedef union
emilmont 80:8e73be2a2ac1 230 {
emilmont 80:8e73be2a2ac1 231 struct
emilmont 80:8e73be2a2ac1 232 {
emilmont 80:8e73be2a2ac1 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 80:8e73be2a2ac1 235 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 236 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 237 } IPSR_Type;
emilmont 80:8e73be2a2ac1 238
emilmont 80:8e73be2a2ac1 239
emilmont 80:8e73be2a2ac1 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 80:8e73be2a2ac1 241 */
emilmont 80:8e73be2a2ac1 242 typedef union
emilmont 80:8e73be2a2ac1 243 {
emilmont 80:8e73be2a2ac1 244 struct
emilmont 80:8e73be2a2ac1 245 {
emilmont 80:8e73be2a2ac1 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 247 #if (__CORTEX_M != 0x04)
emilmont 80:8e73be2a2ac1 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 80:8e73be2a2ac1 249 #else
emilmont 80:8e73be2a2ac1 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 80:8e73be2a2ac1 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 80:8e73be2a2ac1 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 80:8e73be2a2ac1 253 #endif
emilmont 80:8e73be2a2ac1 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 80:8e73be2a2ac1 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 80:8e73be2a2ac1 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 80:8e73be2a2ac1 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 261 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 262 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 263 } xPSR_Type;
emilmont 80:8e73be2a2ac1 264
emilmont 80:8e73be2a2ac1 265
emilmont 80:8e73be2a2ac1 266 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 80:8e73be2a2ac1 267 */
emilmont 80:8e73be2a2ac1 268 typedef union
emilmont 80:8e73be2a2ac1 269 {
emilmont 80:8e73be2a2ac1 270 struct
emilmont 80:8e73be2a2ac1 271 {
emilmont 80:8e73be2a2ac1 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 80:8e73be2a2ac1 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 80:8e73be2a2ac1 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 80:8e73be2a2ac1 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 80:8e73be2a2ac1 276 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 277 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 278 } CONTROL_Type;
emilmont 80:8e73be2a2ac1 279
emilmont 80:8e73be2a2ac1 280 /*@} end of group CMSIS_CORE */
emilmont 80:8e73be2a2ac1 281
emilmont 80:8e73be2a2ac1 282
emilmont 80:8e73be2a2ac1 283 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 80:8e73be2a2ac1 285 \brief Type definitions for the NVIC Registers
emilmont 80:8e73be2a2ac1 286 @{
emilmont 80:8e73be2a2ac1 287 */
emilmont 80:8e73be2a2ac1 288
emilmont 80:8e73be2a2ac1 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 80:8e73be2a2ac1 290 */
emilmont 80:8e73be2a2ac1 291 typedef struct
emilmont 80:8e73be2a2ac1 292 {
emilmont 80:8e73be2a2ac1 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 80:8e73be2a2ac1 294 uint32_t RESERVED0[31];
emilmont 80:8e73be2a2ac1 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 80:8e73be2a2ac1 296 uint32_t RSERVED1[31];
emilmont 80:8e73be2a2ac1 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 80:8e73be2a2ac1 298 uint32_t RESERVED2[31];
emilmont 80:8e73be2a2ac1 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 80:8e73be2a2ac1 300 uint32_t RESERVED3[31];
emilmont 80:8e73be2a2ac1 301 uint32_t RESERVED4[64];
emilmont 80:8e73be2a2ac1 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 80:8e73be2a2ac1 303 } NVIC_Type;
emilmont 80:8e73be2a2ac1 304
emilmont 80:8e73be2a2ac1 305 /*@} end of group CMSIS_NVIC */
emilmont 80:8e73be2a2ac1 306
emilmont 80:8e73be2a2ac1 307
emilmont 80:8e73be2a2ac1 308 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 309 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 80:8e73be2a2ac1 310 \brief Type definitions for the System Control Block Registers
emilmont 80:8e73be2a2ac1 311 @{
emilmont 80:8e73be2a2ac1 312 */
emilmont 80:8e73be2a2ac1 313
emilmont 80:8e73be2a2ac1 314 /** \brief Structure type to access the System Control Block (SCB).
emilmont 80:8e73be2a2ac1 315 */
emilmont 80:8e73be2a2ac1 316 typedef struct
emilmont 80:8e73be2a2ac1 317 {
emilmont 80:8e73be2a2ac1 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 80:8e73be2a2ac1 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 80:8e73be2a2ac1 320 #if (__VTOR_PRESENT == 1)
emilmont 80:8e73be2a2ac1 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 80:8e73be2a2ac1 322 #else
emilmont 80:8e73be2a2ac1 323 uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 324 #endif
emilmont 80:8e73be2a2ac1 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 80:8e73be2a2ac1 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 80:8e73be2a2ac1 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 80:8e73be2a2ac1 328 uint32_t RESERVED1;
emilmont 80:8e73be2a2ac1 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 80:8e73be2a2ac1 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 80:8e73be2a2ac1 331 } SCB_Type;
emilmont 80:8e73be2a2ac1 332
emilmont 80:8e73be2a2ac1 333 /* SCB CPUID Register Definitions */
emilmont 80:8e73be2a2ac1 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 80:8e73be2a2ac1 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 80:8e73be2a2ac1 336
emilmont 80:8e73be2a2ac1 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 80:8e73be2a2ac1 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 80:8e73be2a2ac1 339
emilmont 80:8e73be2a2ac1 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 80:8e73be2a2ac1 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 80:8e73be2a2ac1 342
emilmont 80:8e73be2a2ac1 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 80:8e73be2a2ac1 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 80:8e73be2a2ac1 345
emilmont 80:8e73be2a2ac1 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 80:8e73be2a2ac1 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 80:8e73be2a2ac1 348
emilmont 80:8e73be2a2ac1 349 /* SCB Interrupt Control State Register Definitions */
emilmont 80:8e73be2a2ac1 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 80:8e73be2a2ac1 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 80:8e73be2a2ac1 352
emilmont 80:8e73be2a2ac1 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 80:8e73be2a2ac1 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 80:8e73be2a2ac1 355
emilmont 80:8e73be2a2ac1 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 80:8e73be2a2ac1 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 80:8e73be2a2ac1 358
emilmont 80:8e73be2a2ac1 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 80:8e73be2a2ac1 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 80:8e73be2a2ac1 361
emilmont 80:8e73be2a2ac1 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 80:8e73be2a2ac1 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 80:8e73be2a2ac1 364
emilmont 80:8e73be2a2ac1 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 80:8e73be2a2ac1 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 80:8e73be2a2ac1 367
emilmont 80:8e73be2a2ac1 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 80:8e73be2a2ac1 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 80:8e73be2a2ac1 370
emilmont 80:8e73be2a2ac1 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 80:8e73be2a2ac1 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 80:8e73be2a2ac1 373
emilmont 80:8e73be2a2ac1 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 80:8e73be2a2ac1 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 80:8e73be2a2ac1 376
emilmont 80:8e73be2a2ac1 377 #if (__VTOR_PRESENT == 1)
emilmont 80:8e73be2a2ac1 378 /* SCB Interrupt Control State Register Definitions */
emilmont 80:8e73be2a2ac1 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
emilmont 80:8e73be2a2ac1 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 80:8e73be2a2ac1 381 #endif
emilmont 80:8e73be2a2ac1 382
emilmont 80:8e73be2a2ac1 383 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 80:8e73be2a2ac1 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 80:8e73be2a2ac1 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 80:8e73be2a2ac1 386
emilmont 80:8e73be2a2ac1 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 80:8e73be2a2ac1 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 80:8e73be2a2ac1 389
emilmont 80:8e73be2a2ac1 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 80:8e73be2a2ac1 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 80:8e73be2a2ac1 392
emilmont 80:8e73be2a2ac1 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 80:8e73be2a2ac1 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 80:8e73be2a2ac1 395
emilmont 80:8e73be2a2ac1 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 80:8e73be2a2ac1 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 80:8e73be2a2ac1 398
emilmont 80:8e73be2a2ac1 399 /* SCB System Control Register Definitions */
emilmont 80:8e73be2a2ac1 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 80:8e73be2a2ac1 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 80:8e73be2a2ac1 402
emilmont 80:8e73be2a2ac1 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 80:8e73be2a2ac1 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 80:8e73be2a2ac1 405
emilmont 80:8e73be2a2ac1 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 80:8e73be2a2ac1 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 80:8e73be2a2ac1 408
emilmont 80:8e73be2a2ac1 409 /* SCB Configuration Control Register Definitions */
emilmont 80:8e73be2a2ac1 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 80:8e73be2a2ac1 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 80:8e73be2a2ac1 412
emilmont 80:8e73be2a2ac1 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 80:8e73be2a2ac1 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 80:8e73be2a2ac1 415
emilmont 80:8e73be2a2ac1 416 /* SCB System Handler Control and State Register Definitions */
emilmont 80:8e73be2a2ac1 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 80:8e73be2a2ac1 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 80:8e73be2a2ac1 419
emilmont 80:8e73be2a2ac1 420 /*@} end of group CMSIS_SCB */
emilmont 80:8e73be2a2ac1 421
emilmont 80:8e73be2a2ac1 422
emilmont 80:8e73be2a2ac1 423 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 80:8e73be2a2ac1 425 \brief Type definitions for the System Timer Registers.
emilmont 80:8e73be2a2ac1 426 @{
emilmont 80:8e73be2a2ac1 427 */
emilmont 80:8e73be2a2ac1 428
emilmont 80:8e73be2a2ac1 429 /** \brief Structure type to access the System Timer (SysTick).
emilmont 80:8e73be2a2ac1 430 */
emilmont 80:8e73be2a2ac1 431 typedef struct
emilmont 80:8e73be2a2ac1 432 {
emilmont 80:8e73be2a2ac1 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 80:8e73be2a2ac1 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 80:8e73be2a2ac1 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 80:8e73be2a2ac1 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 80:8e73be2a2ac1 437 } SysTick_Type;
emilmont 80:8e73be2a2ac1 438
emilmont 80:8e73be2a2ac1 439 /* SysTick Control / Status Register Definitions */
emilmont 80:8e73be2a2ac1 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 80:8e73be2a2ac1 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 80:8e73be2a2ac1 442
emilmont 80:8e73be2a2ac1 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 80:8e73be2a2ac1 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 80:8e73be2a2ac1 445
emilmont 80:8e73be2a2ac1 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 80:8e73be2a2ac1 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 80:8e73be2a2ac1 448
emilmont 80:8e73be2a2ac1 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 80:8e73be2a2ac1 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 451
emilmont 80:8e73be2a2ac1 452 /* SysTick Reload Register Definitions */
emilmont 80:8e73be2a2ac1 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 80:8e73be2a2ac1 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 80:8e73be2a2ac1 455
emilmont 80:8e73be2a2ac1 456 /* SysTick Current Register Definitions */
emilmont 80:8e73be2a2ac1 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 80:8e73be2a2ac1 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 80:8e73be2a2ac1 459
emilmont 80:8e73be2a2ac1 460 /* SysTick Calibration Register Definitions */
emilmont 80:8e73be2a2ac1 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 80:8e73be2a2ac1 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 80:8e73be2a2ac1 463
emilmont 80:8e73be2a2ac1 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 80:8e73be2a2ac1 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 80:8e73be2a2ac1 466
emilmont 80:8e73be2a2ac1 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 80:8e73be2a2ac1 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 80:8e73be2a2ac1 469
emilmont 80:8e73be2a2ac1 470 /*@} end of group CMSIS_SysTick */
emilmont 80:8e73be2a2ac1 471
emilmont 80:8e73be2a2ac1 472 #if (__MPU_PRESENT == 1)
emilmont 80:8e73be2a2ac1 473 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 80:8e73be2a2ac1 475 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 80:8e73be2a2ac1 476 @{
emilmont 80:8e73be2a2ac1 477 */
emilmont 80:8e73be2a2ac1 478
emilmont 80:8e73be2a2ac1 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 80:8e73be2a2ac1 480 */
emilmont 80:8e73be2a2ac1 481 typedef struct
emilmont 80:8e73be2a2ac1 482 {
emilmont 80:8e73be2a2ac1 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 80:8e73be2a2ac1 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 80:8e73be2a2ac1 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 80:8e73be2a2ac1 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 80:8e73be2a2ac1 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 488 } MPU_Type;
emilmont 80:8e73be2a2ac1 489
emilmont 80:8e73be2a2ac1 490 /* MPU Type Register */
emilmont 80:8e73be2a2ac1 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 80:8e73be2a2ac1 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 80:8e73be2a2ac1 493
emilmont 80:8e73be2a2ac1 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 80:8e73be2a2ac1 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 80:8e73be2a2ac1 496
emilmont 80:8e73be2a2ac1 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
emilmont 80:8e73be2a2ac1 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
emilmont 80:8e73be2a2ac1 499
emilmont 80:8e73be2a2ac1 500 /* MPU Control Register */
emilmont 80:8e73be2a2ac1 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 80:8e73be2a2ac1 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 80:8e73be2a2ac1 503
emilmont 80:8e73be2a2ac1 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 80:8e73be2a2ac1 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 80:8e73be2a2ac1 506
emilmont 80:8e73be2a2ac1 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
emilmont 80:8e73be2a2ac1 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 509
emilmont 80:8e73be2a2ac1 510 /* MPU Region Number Register */
emilmont 80:8e73be2a2ac1 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
emilmont 80:8e73be2a2ac1 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
emilmont 80:8e73be2a2ac1 513
emilmont 80:8e73be2a2ac1 514 /* MPU Region Base Address Register */
emilmont 80:8e73be2a2ac1 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
emilmont 80:8e73be2a2ac1 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 80:8e73be2a2ac1 517
emilmont 80:8e73be2a2ac1 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 80:8e73be2a2ac1 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 80:8e73be2a2ac1 520
emilmont 80:8e73be2a2ac1 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
emilmont 80:8e73be2a2ac1 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
emilmont 80:8e73be2a2ac1 523
emilmont 80:8e73be2a2ac1 524 /* MPU Region Attribute and Size Register */
emilmont 80:8e73be2a2ac1 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 80:8e73be2a2ac1 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 80:8e73be2a2ac1 527
emilmont 80:8e73be2a2ac1 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 80:8e73be2a2ac1 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 80:8e73be2a2ac1 530
emilmont 80:8e73be2a2ac1 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 80:8e73be2a2ac1 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 80:8e73be2a2ac1 533
emilmont 80:8e73be2a2ac1 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 80:8e73be2a2ac1 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 80:8e73be2a2ac1 536
emilmont 80:8e73be2a2ac1 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 80:8e73be2a2ac1 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 80:8e73be2a2ac1 539
emilmont 80:8e73be2a2ac1 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 80:8e73be2a2ac1 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 80:8e73be2a2ac1 542
emilmont 80:8e73be2a2ac1 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 80:8e73be2a2ac1 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 80:8e73be2a2ac1 545
emilmont 80:8e73be2a2ac1 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 80:8e73be2a2ac1 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 80:8e73be2a2ac1 548
emilmont 80:8e73be2a2ac1 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 80:8e73be2a2ac1 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 80:8e73be2a2ac1 551
emilmont 80:8e73be2a2ac1 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
emilmont 80:8e73be2a2ac1 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 80:8e73be2a2ac1 554
emilmont 80:8e73be2a2ac1 555 /*@} end of group CMSIS_MPU */
emilmont 80:8e73be2a2ac1 556 #endif
emilmont 80:8e73be2a2ac1 557
emilmont 80:8e73be2a2ac1 558
emilmont 80:8e73be2a2ac1 559 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 80:8e73be2a2ac1 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 80:8e73be2a2ac1 562 are only accessible over DAP and not via processor. Therefore
emilmont 80:8e73be2a2ac1 563 they are not covered by the Cortex-M0 header file.
emilmont 80:8e73be2a2ac1 564 @{
emilmont 80:8e73be2a2ac1 565 */
emilmont 80:8e73be2a2ac1 566 /*@} end of group CMSIS_CoreDebug */
emilmont 80:8e73be2a2ac1 567
emilmont 80:8e73be2a2ac1 568
emilmont 80:8e73be2a2ac1 569 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 570 \defgroup CMSIS_core_base Core Definitions
emilmont 80:8e73be2a2ac1 571 \brief Definitions for base addresses, unions, and structures.
emilmont 80:8e73be2a2ac1 572 @{
emilmont 80:8e73be2a2ac1 573 */
emilmont 80:8e73be2a2ac1 574
emilmont 80:8e73be2a2ac1 575 /* Memory mapping of Cortex-M0+ Hardware */
emilmont 80:8e73be2a2ac1 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 80:8e73be2a2ac1 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 80:8e73be2a2ac1 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 80:8e73be2a2ac1 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 80:8e73be2a2ac1 580
emilmont 80:8e73be2a2ac1 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 80:8e73be2a2ac1 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 80:8e73be2a2ac1 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 80:8e73be2a2ac1 584
emilmont 80:8e73be2a2ac1 585 #if (__MPU_PRESENT == 1)
emilmont 80:8e73be2a2ac1 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 80:8e73be2a2ac1 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 80:8e73be2a2ac1 588 #endif
emilmont 80:8e73be2a2ac1 589
emilmont 80:8e73be2a2ac1 590 /*@} */
emilmont 80:8e73be2a2ac1 591
emilmont 80:8e73be2a2ac1 592
emilmont 80:8e73be2a2ac1 593
emilmont 80:8e73be2a2ac1 594 /*******************************************************************************
emilmont 80:8e73be2a2ac1 595 * Hardware Abstraction Layer
emilmont 80:8e73be2a2ac1 596 Core Function Interface contains:
emilmont 80:8e73be2a2ac1 597 - Core NVIC Functions
emilmont 80:8e73be2a2ac1 598 - Core SysTick Functions
emilmont 80:8e73be2a2ac1 599 - Core Register Access Functions
emilmont 80:8e73be2a2ac1 600 ******************************************************************************/
emilmont 80:8e73be2a2ac1 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 80:8e73be2a2ac1 602 */
emilmont 80:8e73be2a2ac1 603
emilmont 80:8e73be2a2ac1 604
emilmont 80:8e73be2a2ac1 605
emilmont 80:8e73be2a2ac1 606 /* ########################## NVIC functions #################################### */
emilmont 80:8e73be2a2ac1 607 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 80:8e73be2a2ac1 609 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 80:8e73be2a2ac1 610 @{
emilmont 80:8e73be2a2ac1 611 */
emilmont 80:8e73be2a2ac1 612
emilmont 80:8e73be2a2ac1 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 80:8e73be2a2ac1 614 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 80:8e73be2a2ac1 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 80:8e73be2a2ac1 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 80:8e73be2a2ac1 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 80:8e73be2a2ac1 618
emilmont 80:8e73be2a2ac1 619
emilmont 80:8e73be2a2ac1 620 /** \brief Enable External Interrupt
emilmont 80:8e73be2a2ac1 621
emilmont 80:8e73be2a2ac1 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 623
emilmont 80:8e73be2a2ac1 624 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 625 */
emilmont 80:8e73be2a2ac1 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 627 {
emilmont 80:8e73be2a2ac1 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 80:8e73be2a2ac1 629 }
emilmont 80:8e73be2a2ac1 630
emilmont 80:8e73be2a2ac1 631
emilmont 80:8e73be2a2ac1 632 /** \brief Disable External Interrupt
emilmont 80:8e73be2a2ac1 633
emilmont 80:8e73be2a2ac1 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 635
emilmont 80:8e73be2a2ac1 636 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 637 */
emilmont 80:8e73be2a2ac1 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 639 {
emilmont 80:8e73be2a2ac1 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 80:8e73be2a2ac1 641 }
emilmont 80:8e73be2a2ac1 642
emilmont 80:8e73be2a2ac1 643
emilmont 80:8e73be2a2ac1 644 /** \brief Get Pending Interrupt
emilmont 80:8e73be2a2ac1 645
emilmont 80:8e73be2a2ac1 646 The function reads the pending register in the NVIC and returns the pending bit
emilmont 80:8e73be2a2ac1 647 for the specified interrupt.
emilmont 80:8e73be2a2ac1 648
emilmont 80:8e73be2a2ac1 649 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 650
emilmont 80:8e73be2a2ac1 651 \return 0 Interrupt status is not pending.
emilmont 80:8e73be2a2ac1 652 \return 1 Interrupt status is pending.
emilmont 80:8e73be2a2ac1 653 */
emilmont 80:8e73be2a2ac1 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 655 {
emilmont 80:8e73be2a2ac1 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 80:8e73be2a2ac1 657 }
emilmont 80:8e73be2a2ac1 658
emilmont 80:8e73be2a2ac1 659
emilmont 80:8e73be2a2ac1 660 /** \brief Set Pending Interrupt
emilmont 80:8e73be2a2ac1 661
emilmont 80:8e73be2a2ac1 662 The function sets the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 663
emilmont 80:8e73be2a2ac1 664 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 665 */
emilmont 80:8e73be2a2ac1 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 667 {
emilmont 80:8e73be2a2ac1 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 80:8e73be2a2ac1 669 }
emilmont 80:8e73be2a2ac1 670
emilmont 80:8e73be2a2ac1 671
emilmont 80:8e73be2a2ac1 672 /** \brief Clear Pending Interrupt
emilmont 80:8e73be2a2ac1 673
emilmont 80:8e73be2a2ac1 674 The function clears the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 675
emilmont 80:8e73be2a2ac1 676 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 677 */
emilmont 80:8e73be2a2ac1 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 679 {
emilmont 80:8e73be2a2ac1 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 80:8e73be2a2ac1 681 }
emilmont 80:8e73be2a2ac1 682
emilmont 80:8e73be2a2ac1 683
emilmont 80:8e73be2a2ac1 684 /** \brief Set Interrupt Priority
emilmont 80:8e73be2a2ac1 685
emilmont 80:8e73be2a2ac1 686 The function sets the priority of an interrupt.
emilmont 80:8e73be2a2ac1 687
emilmont 80:8e73be2a2ac1 688 \note The priority cannot be set for every core interrupt.
emilmont 80:8e73be2a2ac1 689
emilmont 80:8e73be2a2ac1 690 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 691 \param [in] priority Priority to set.
emilmont 80:8e73be2a2ac1 692 */
emilmont 80:8e73be2a2ac1 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 80:8e73be2a2ac1 694 {
emilmont 80:8e73be2a2ac1 695 if(IRQn < 0) {
emilmont 80:8e73be2a2ac1 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 80:8e73be2a2ac1 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 80:8e73be2a2ac1 698 else {
emilmont 80:8e73be2a2ac1 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 80:8e73be2a2ac1 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 80:8e73be2a2ac1 701 }
emilmont 80:8e73be2a2ac1 702
emilmont 80:8e73be2a2ac1 703
emilmont 80:8e73be2a2ac1 704 /** \brief Get Interrupt Priority
emilmont 80:8e73be2a2ac1 705
emilmont 80:8e73be2a2ac1 706 The function reads the priority of an interrupt. The interrupt
emilmont 80:8e73be2a2ac1 707 number can be positive to specify an external (device specific)
emilmont 80:8e73be2a2ac1 708 interrupt, or negative to specify an internal (core) interrupt.
emilmont 80:8e73be2a2ac1 709
emilmont 80:8e73be2a2ac1 710
emilmont 80:8e73be2a2ac1 711 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 712 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 80:8e73be2a2ac1 713 priority bits of the microcontroller.
emilmont 80:8e73be2a2ac1 714 */
emilmont 80:8e73be2a2ac1 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 716 {
emilmont 80:8e73be2a2ac1 717
emilmont 80:8e73be2a2ac1 718 if(IRQn < 0) {
emilmont 80:8e73be2a2ac1 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 80:8e73be2a2ac1 720 else {
emilmont 80:8e73be2a2ac1 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 80:8e73be2a2ac1 722 }
emilmont 80:8e73be2a2ac1 723
emilmont 80:8e73be2a2ac1 724
emilmont 80:8e73be2a2ac1 725 /** \brief System Reset
emilmont 80:8e73be2a2ac1 726
emilmont 80:8e73be2a2ac1 727 The function initiates a system reset request to reset the MCU.
emilmont 80:8e73be2a2ac1 728 */
emilmont 80:8e73be2a2ac1 729 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 80:8e73be2a2ac1 730 {
emilmont 80:8e73be2a2ac1 731 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 80:8e73be2a2ac1 732 buffered write are completed before reset */
emilmont 80:8e73be2a2ac1 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 80:8e73be2a2ac1 734 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 80:8e73be2a2ac1 735 __DSB(); /* Ensure completion of memory access */
emilmont 80:8e73be2a2ac1 736 while(1); /* wait until reset */
emilmont 80:8e73be2a2ac1 737 }
emilmont 80:8e73be2a2ac1 738
emilmont 80:8e73be2a2ac1 739 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 80:8e73be2a2ac1 740
emilmont 80:8e73be2a2ac1 741
emilmont 80:8e73be2a2ac1 742
emilmont 80:8e73be2a2ac1 743 /* ################################## SysTick function ############################################ */
emilmont 80:8e73be2a2ac1 744 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 80:8e73be2a2ac1 746 \brief Functions that configure the System.
emilmont 80:8e73be2a2ac1 747 @{
emilmont 80:8e73be2a2ac1 748 */
emilmont 80:8e73be2a2ac1 749
emilmont 80:8e73be2a2ac1 750 #if (__Vendor_SysTickConfig == 0)
emilmont 80:8e73be2a2ac1 751
emilmont 80:8e73be2a2ac1 752 /** \brief System Tick Configuration
emilmont 80:8e73be2a2ac1 753
emilmont 80:8e73be2a2ac1 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 80:8e73be2a2ac1 755 Counter is in free running mode to generate periodic interrupts.
emilmont 80:8e73be2a2ac1 756
emilmont 80:8e73be2a2ac1 757 \param [in] ticks Number of ticks between two interrupts.
emilmont 80:8e73be2a2ac1 758
emilmont 80:8e73be2a2ac1 759 \return 0 Function succeeded.
emilmont 80:8e73be2a2ac1 760 \return 1 Function failed.
emilmont 80:8e73be2a2ac1 761
emilmont 80:8e73be2a2ac1 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 80:8e73be2a2ac1 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 80:8e73be2a2ac1 764 must contain a vendor-specific implementation of this function.
emilmont 80:8e73be2a2ac1 765
emilmont 80:8e73be2a2ac1 766 */
emilmont 80:8e73be2a2ac1 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 80:8e73be2a2ac1 768 {
emilmont 80:8e73be2a2ac1 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 80:8e73be2a2ac1 770
emilmont 80:8e73be2a2ac1 771 SysTick->LOAD = ticks - 1; /* set reload register */
emilmont 80:8e73be2a2ac1 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 80:8e73be2a2ac1 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 80:8e73be2a2ac1 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 80:8e73be2a2ac1 775 SysTick_CTRL_TICKINT_Msk |
emilmont 80:8e73be2a2ac1 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 80:8e73be2a2ac1 777 return (0); /* Function successful */
emilmont 80:8e73be2a2ac1 778 }
emilmont 80:8e73be2a2ac1 779
emilmont 80:8e73be2a2ac1 780 #endif
emilmont 80:8e73be2a2ac1 781
emilmont 80:8e73be2a2ac1 782 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 80:8e73be2a2ac1 783
emilmont 80:8e73be2a2ac1 784
emilmont 80:8e73be2a2ac1 785
emilmont 80:8e73be2a2ac1 786
emilmont 80:8e73be2a2ac1 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
emilmont 80:8e73be2a2ac1 788
emilmont 80:8e73be2a2ac1 789 #endif /* __CMSIS_GENERIC */
emilmont 80:8e73be2a2ac1 790
emilmont 80:8e73be2a2ac1 791 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 792 }
emilmont 80:8e73be2a2ac1 793 #endif