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TARGET_KL46Z/clk_freqs.h@80:8e73be2a2ac1, 2014-02-21 (annotated)

Committer:
emilmont
Date:
Fri Feb 21 12:21:39 2014 +0000
Revision:
80:8e73be2a2ac1
Parent:
77:869cf507173a 
First alpha release for the NRF51822 target (to be tested in the online IDE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /* mbed Microcontroller Library
emilmont 77:869cf507173a 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 77:869cf507173a 3 *
emilmont 77:869cf507173a 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 77:869cf507173a 5 * you may not use this file except in compliance with the License.
emilmont 77:869cf507173a 6 * You may obtain a copy of the License at
emilmont 77:869cf507173a 7 *
emilmont 77:869cf507173a 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 77:869cf507173a 9 *
emilmont 77:869cf507173a 10 * Unless required by applicable law or agreed to in writing, software
emilmont 77:869cf507173a 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 77:869cf507173a 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 77:869cf507173a 13 * See the License for the specific language governing permissions and
emilmont 77:869cf507173a 14 * limitations under the License.
emilmont 77:869cf507173a 15 */
emilmont 77:869cf507173a 16 #ifndef MBED_CLK_FREQS_H
emilmont 77:869cf507173a 17 #define MBED_CLK_FREQS_H
emilmont 77:869cf507173a 18
emilmont 77:869cf507173a 19 #ifdef __cplusplus
emilmont 77:869cf507173a 20 extern "C" {
emilmont 77:869cf507173a 21 #endif
emilmont 77:869cf507173a 22
emilmont 77:869cf507173a 23 #include "PeripheralPins.h"
emilmont 77:869cf507173a 24
emilmont 77:869cf507173a 25 //Get the peripheral bus clock frequency
emilmont 77:869cf507173a 26 static inline uint32_t bus_frequency(void) {
emilmont 77:869cf507173a 27 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
emilmont 77:869cf507173a 28 }
emilmont 77:869cf507173a 29
emilmont 77:869cf507173a 30 //Get external oscillator (crystal) frequency
emilmont 77:869cf507173a 31 static uint32_t extosc_frequency(void) {
emilmont 77:869cf507173a 32 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
emilmont 77:869cf507173a 33
emilmont 77:869cf507173a 34 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
emilmont 77:869cf507173a 35 return MCGClock;
emilmont 77:869cf507173a 36
emilmont 77:869cf507173a 37 uint32_t divider, multiplier;
emilmont 77:869cf507173a 38 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
emilmont 77:869cf507173a 39 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
emilmont 77:869cf507173a 40 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
emilmont 77:869cf507173a 41 #endif
emilmont 77:869cf507173a 42 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
emilmont 77:869cf507173a 43 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
emilmont 77:869cf507173a 44 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
emilmont 77:869cf507173a 45 divider <<= 5u;
emilmont 77:869cf507173a 46 /* Select correct multiplier to calculate the MCG output clock */
emilmont 77:869cf507173a 47 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
emilmont 77:869cf507173a 48 case 0x0u:
emilmont 77:869cf507173a 49 multiplier = 640u;
emilmont 77:869cf507173a 50 break;
emilmont 77:869cf507173a 51 case 0x20u:
emilmont 77:869cf507173a 52 multiplier = 1280u;
emilmont 77:869cf507173a 53 break;
emilmont 77:869cf507173a 54 case 0x40u:
emilmont 77:869cf507173a 55 multiplier = 1920u;
emilmont 77:869cf507173a 56 break;
emilmont 77:869cf507173a 57 case 0x60u:
emilmont 77:869cf507173a 58 multiplier = 2560u;
emilmont 77:869cf507173a 59 break;
emilmont 77:869cf507173a 60 case 0x80u:
emilmont 77:869cf507173a 61 multiplier = 732u;
emilmont 77:869cf507173a 62 break;
emilmont 77:869cf507173a 63 case 0xA0u:
emilmont 77:869cf507173a 64 multiplier = 1464u;
emilmont 77:869cf507173a 65 break;
emilmont 77:869cf507173a 66 case 0xC0u:
emilmont 77:869cf507173a 67 multiplier = 2197u;
emilmont 77:869cf507173a 68 break;
emilmont 77:869cf507173a 69 case 0xE0u:
emilmont 77:869cf507173a 70 default:
emilmont 77:869cf507173a 71 multiplier = 2929u;
emilmont 77:869cf507173a 72 break;
emilmont 77:869cf507173a 73 }
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 return MCGClock * divider / multiplier;
emilmont 77:869cf507173a 76 }
emilmont 77:869cf507173a 77 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 77:869cf507173a 78 } else { //PLL is selected
emilmont 77:869cf507173a 79 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
emilmont 77:869cf507173a 80 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
emilmont 77:869cf507173a 81 return MCGClock * divider / multiplier;
emilmont 77:869cf507173a 82 }
emilmont 77:869cf507173a 83 }
emilmont 77:869cf507173a 84 #endif
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 //In all other cases either there is no crystal or we cannot determine it
emilmont 77:869cf507173a 87 //For example when the FLL is running on the internal reference, and there is also an
emilmont 77:869cf507173a 88 //external crystal. However these are unlikely situations
emilmont 77:869cf507173a 89 return 0;
emilmont 77:869cf507173a 90 }
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
emilmont 77:869cf507173a 93 static uint32_t mcgpllfll_frequency(void) {
emilmont 77:869cf507173a 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
emilmont 77:869cf507173a 95 return 0;
emilmont 77:869cf507173a 96
emilmont 77:869cf507173a 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
emilmont 77:869cf507173a 98 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 77:869cf507173a 99 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
emilmont 77:869cf507173a 100 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
emilmont 77:869cf507173a 101 #endif
emilmont 77:869cf507173a 102 return MCGClock;
emilmont 77:869cf507173a 103 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 77:869cf507173a 104 } else { //PLL is selected
emilmont 77:869cf507173a 105 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
emilmont 77:869cf507173a 106 return (MCGClock >> 1);
emilmont 77:869cf507173a 107 }
emilmont 77:869cf507173a 108 #endif
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
emilmont 77:869cf507173a 111 //for the peripherals, this is however an unlikely setup
emilmont 77:869cf507173a 112 }
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 #ifdef __cplusplus
emilmont 77:869cf507173a 115 }
emilmont 77:869cf507173a 116 #endif
emilmont 77:869cf507173a 117
emilmont 77:869cf507173a 118 #endif