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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
emilmont
Date:
Tue Nov 29 14:59:27 2011 +0000
Revision:
27:7110ebee3484
New Libraries 11.11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file LPC17xx.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
emilmont 27:7110ebee3484 4 * NXP LPC17xx Device Series
emilmont 27:7110ebee3484 5 * @version: V1.09
emilmont 27:7110ebee3484 6 * @date: 17. March 2010
emilmont 27:7110ebee3484 7
emilmont 27:7110ebee3484 8 *
emilmont 27:7110ebee3484 9 * @note
emilmont 27:7110ebee3484 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 11 *
emilmont 27:7110ebee3484 12 * @par
emilmont 27:7110ebee3484 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 27:7110ebee3484 14 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 15 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 16 *
emilmont 27:7110ebee3484 17 * @par
emilmont 27:7110ebee3484 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 23 *
emilmont 27:7110ebee3484 24 ******************************************************************************/
emilmont 27:7110ebee3484 25
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27 #ifndef __LPC17xx_H__
emilmont 27:7110ebee3484 28 #define __LPC17xx_H__
emilmont 27:7110ebee3484 29
emilmont 27:7110ebee3484 30 /*
emilmont 27:7110ebee3484 31 * ==========================================================================
emilmont 27:7110ebee3484 32 * ---------- Interrupt Number Definition -----------------------------------
emilmont 27:7110ebee3484 33 * ==========================================================================
emilmont 27:7110ebee3484 34 */
emilmont 27:7110ebee3484 35
emilmont 27:7110ebee3484 36 typedef enum IRQn
emilmont 27:7110ebee3484 37 {
emilmont 27:7110ebee3484 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
emilmont 27:7110ebee3484 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
emilmont 27:7110ebee3484 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
emilmont 27:7110ebee3484 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
emilmont 27:7110ebee3484 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
emilmont 27:7110ebee3484 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
emilmont 27:7110ebee3484 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
emilmont 27:7110ebee3484 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
emilmont 27:7110ebee3484 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
emilmont 27:7110ebee3484 47
emilmont 27:7110ebee3484 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
emilmont 27:7110ebee3484 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
emilmont 27:7110ebee3484 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
emilmont 27:7110ebee3484 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
emilmont 27:7110ebee3484 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
emilmont 27:7110ebee3484 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
emilmont 27:7110ebee3484 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
emilmont 27:7110ebee3484 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
emilmont 27:7110ebee3484 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
emilmont 27:7110ebee3484 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
emilmont 27:7110ebee3484 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
emilmont 27:7110ebee3484 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
emilmont 27:7110ebee3484 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
emilmont 27:7110ebee3484 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
emilmont 27:7110ebee3484 62 SPI_IRQn = 13, /*!< SPI Interrupt */
emilmont 27:7110ebee3484 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
emilmont 27:7110ebee3484 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
emilmont 27:7110ebee3484 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
emilmont 27:7110ebee3484 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
emilmont 27:7110ebee3484 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
emilmont 27:7110ebee3484 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
emilmont 27:7110ebee3484 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
emilmont 27:7110ebee3484 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
emilmont 27:7110ebee3484 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
emilmont 27:7110ebee3484 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
emilmont 27:7110ebee3484 73 USB_IRQn = 24, /*!< USB Interrupt */
emilmont 27:7110ebee3484 74 CAN_IRQn = 25, /*!< CAN Interrupt */
emilmont 27:7110ebee3484 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
emilmont 27:7110ebee3484 76 I2S_IRQn = 27, /*!< I2S Interrupt */
emilmont 27:7110ebee3484 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
emilmont 27:7110ebee3484 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
emilmont 27:7110ebee3484 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
emilmont 27:7110ebee3484 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
emilmont 27:7110ebee3484 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
emilmont 27:7110ebee3484 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
emilmont 27:7110ebee3484 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
emilmont 27:7110ebee3484 84 } IRQn_Type;
emilmont 27:7110ebee3484 85
emilmont 27:7110ebee3484 86
emilmont 27:7110ebee3484 87 /*
emilmont 27:7110ebee3484 88 * ==========================================================================
emilmont 27:7110ebee3484 89 * ----------- Processor and Core Peripheral Section ------------------------
emilmont 27:7110ebee3484 90 * ==========================================================================
emilmont 27:7110ebee3484 91 */
emilmont 27:7110ebee3484 92
emilmont 27:7110ebee3484 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
emilmont 27:7110ebee3484 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
emilmont 27:7110ebee3484 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
emilmont 27:7110ebee3484 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 27:7110ebee3484 97
emilmont 27:7110ebee3484 98
emilmont 27:7110ebee3484 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
emilmont 27:7110ebee3484 100 #include "system_LPC17xx.h" /* System Header */
emilmont 27:7110ebee3484 101
emilmont 27:7110ebee3484 102
emilmont 27:7110ebee3484 103 /******************************************************************************/
emilmont 27:7110ebee3484 104 /* Device Specific Peripheral registers structures */
emilmont 27:7110ebee3484 105 /******************************************************************************/
emilmont 27:7110ebee3484 106
emilmont 27:7110ebee3484 107 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 108 #pragma anon_unions
emilmont 27:7110ebee3484 109 #endif
emilmont 27:7110ebee3484 110
emilmont 27:7110ebee3484 111 /*------------- System Control (SC) ------------------------------------------*/
emilmont 27:7110ebee3484 112 typedef struct
emilmont 27:7110ebee3484 113 {
emilmont 27:7110ebee3484 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
emilmont 27:7110ebee3484 115 uint32_t RESERVED0[31];
emilmont 27:7110ebee3484 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
emilmont 27:7110ebee3484 117 __IO uint32_t PLL0CFG;
emilmont 27:7110ebee3484 118 __I uint32_t PLL0STAT;
emilmont 27:7110ebee3484 119 __O uint32_t PLL0FEED;
emilmont 27:7110ebee3484 120 uint32_t RESERVED1[4];
emilmont 27:7110ebee3484 121 __IO uint32_t PLL1CON;
emilmont 27:7110ebee3484 122 __IO uint32_t PLL1CFG;
emilmont 27:7110ebee3484 123 __I uint32_t PLL1STAT;
emilmont 27:7110ebee3484 124 __O uint32_t PLL1FEED;
emilmont 27:7110ebee3484 125 uint32_t RESERVED2[4];
emilmont 27:7110ebee3484 126 __IO uint32_t PCON;
emilmont 27:7110ebee3484 127 __IO uint32_t PCONP;
emilmont 27:7110ebee3484 128 uint32_t RESERVED3[15];
emilmont 27:7110ebee3484 129 __IO uint32_t CCLKCFG;
emilmont 27:7110ebee3484 130 __IO uint32_t USBCLKCFG;
emilmont 27:7110ebee3484 131 __IO uint32_t CLKSRCSEL;
emilmont 27:7110ebee3484 132 __IO uint32_t CANSLEEPCLR;
emilmont 27:7110ebee3484 133 __IO uint32_t CANWAKEFLAGS;
emilmont 27:7110ebee3484 134 uint32_t RESERVED4[10];
emilmont 27:7110ebee3484 135 __IO uint32_t EXTINT; /* External Interrupts */
emilmont 27:7110ebee3484 136 uint32_t RESERVED5;
emilmont 27:7110ebee3484 137 __IO uint32_t EXTMODE;
emilmont 27:7110ebee3484 138 __IO uint32_t EXTPOLAR;
emilmont 27:7110ebee3484 139 uint32_t RESERVED6[12];
emilmont 27:7110ebee3484 140 __IO uint32_t RSID; /* Reset */
emilmont 27:7110ebee3484 141 uint32_t RESERVED7[7];
emilmont 27:7110ebee3484 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
emilmont 27:7110ebee3484 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
emilmont 27:7110ebee3484 144 __IO uint32_t PCLKSEL0;
emilmont 27:7110ebee3484 145 __IO uint32_t PCLKSEL1;
emilmont 27:7110ebee3484 146 uint32_t RESERVED8[4];
emilmont 27:7110ebee3484 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
emilmont 27:7110ebee3484 148 __IO uint32_t DMAREQSEL;
emilmont 27:7110ebee3484 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
emilmont 27:7110ebee3484 150 } LPC_SC_TypeDef;
emilmont 27:7110ebee3484 151
emilmont 27:7110ebee3484 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
emilmont 27:7110ebee3484 153 typedef struct
emilmont 27:7110ebee3484 154 {
emilmont 27:7110ebee3484 155 __IO uint32_t PINSEL0;
emilmont 27:7110ebee3484 156 __IO uint32_t PINSEL1;
emilmont 27:7110ebee3484 157 __IO uint32_t PINSEL2;
emilmont 27:7110ebee3484 158 __IO uint32_t PINSEL3;
emilmont 27:7110ebee3484 159 __IO uint32_t PINSEL4;
emilmont 27:7110ebee3484 160 __IO uint32_t PINSEL5;
emilmont 27:7110ebee3484 161 __IO uint32_t PINSEL6;
emilmont 27:7110ebee3484 162 __IO uint32_t PINSEL7;
emilmont 27:7110ebee3484 163 __IO uint32_t PINSEL8;
emilmont 27:7110ebee3484 164 __IO uint32_t PINSEL9;
emilmont 27:7110ebee3484 165 __IO uint32_t PINSEL10;
emilmont 27:7110ebee3484 166 uint32_t RESERVED0[5];
emilmont 27:7110ebee3484 167 __IO uint32_t PINMODE0;
emilmont 27:7110ebee3484 168 __IO uint32_t PINMODE1;
emilmont 27:7110ebee3484 169 __IO uint32_t PINMODE2;
emilmont 27:7110ebee3484 170 __IO uint32_t PINMODE3;
emilmont 27:7110ebee3484 171 __IO uint32_t PINMODE4;
emilmont 27:7110ebee3484 172 __IO uint32_t PINMODE5;
emilmont 27:7110ebee3484 173 __IO uint32_t PINMODE6;
emilmont 27:7110ebee3484 174 __IO uint32_t PINMODE7;
emilmont 27:7110ebee3484 175 __IO uint32_t PINMODE8;
emilmont 27:7110ebee3484 176 __IO uint32_t PINMODE9;
emilmont 27:7110ebee3484 177 __IO uint32_t PINMODE_OD0;
emilmont 27:7110ebee3484 178 __IO uint32_t PINMODE_OD1;
emilmont 27:7110ebee3484 179 __IO uint32_t PINMODE_OD2;
emilmont 27:7110ebee3484 180 __IO uint32_t PINMODE_OD3;
emilmont 27:7110ebee3484 181 __IO uint32_t PINMODE_OD4;
emilmont 27:7110ebee3484 182 __IO uint32_t I2CPADCFG;
emilmont 27:7110ebee3484 183 } LPC_PINCON_TypeDef;
emilmont 27:7110ebee3484 184
emilmont 27:7110ebee3484 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
emilmont 27:7110ebee3484 186 typedef struct
emilmont 27:7110ebee3484 187 {
emilmont 27:7110ebee3484 188 union {
emilmont 27:7110ebee3484 189 __IO uint32_t FIODIR;
emilmont 27:7110ebee3484 190 struct {
emilmont 27:7110ebee3484 191 __IO uint16_t FIODIRL;
emilmont 27:7110ebee3484 192 __IO uint16_t FIODIRH;
emilmont 27:7110ebee3484 193 };
emilmont 27:7110ebee3484 194 struct {
emilmont 27:7110ebee3484 195 __IO uint8_t FIODIR0;
emilmont 27:7110ebee3484 196 __IO uint8_t FIODIR1;
emilmont 27:7110ebee3484 197 __IO uint8_t FIODIR2;
emilmont 27:7110ebee3484 198 __IO uint8_t FIODIR3;
emilmont 27:7110ebee3484 199 };
emilmont 27:7110ebee3484 200 };
emilmont 27:7110ebee3484 201 uint32_t RESERVED0[3];
emilmont 27:7110ebee3484 202 union {
emilmont 27:7110ebee3484 203 __IO uint32_t FIOMASK;
emilmont 27:7110ebee3484 204 struct {
emilmont 27:7110ebee3484 205 __IO uint16_t FIOMASKL;
emilmont 27:7110ebee3484 206 __IO uint16_t FIOMASKH;
emilmont 27:7110ebee3484 207 };
emilmont 27:7110ebee3484 208 struct {
emilmont 27:7110ebee3484 209 __IO uint8_t FIOMASK0;
emilmont 27:7110ebee3484 210 __IO uint8_t FIOMASK1;
emilmont 27:7110ebee3484 211 __IO uint8_t FIOMASK2;
emilmont 27:7110ebee3484 212 __IO uint8_t FIOMASK3;
emilmont 27:7110ebee3484 213 };
emilmont 27:7110ebee3484 214 };
emilmont 27:7110ebee3484 215 union {
emilmont 27:7110ebee3484 216 __IO uint32_t FIOPIN;
emilmont 27:7110ebee3484 217 struct {
emilmont 27:7110ebee3484 218 __IO uint16_t FIOPINL;
emilmont 27:7110ebee3484 219 __IO uint16_t FIOPINH;
emilmont 27:7110ebee3484 220 };
emilmont 27:7110ebee3484 221 struct {
emilmont 27:7110ebee3484 222 __IO uint8_t FIOPIN0;
emilmont 27:7110ebee3484 223 __IO uint8_t FIOPIN1;
emilmont 27:7110ebee3484 224 __IO uint8_t FIOPIN2;
emilmont 27:7110ebee3484 225 __IO uint8_t FIOPIN3;
emilmont 27:7110ebee3484 226 };
emilmont 27:7110ebee3484 227 };
emilmont 27:7110ebee3484 228 union {
emilmont 27:7110ebee3484 229 __IO uint32_t FIOSET;
emilmont 27:7110ebee3484 230 struct {
emilmont 27:7110ebee3484 231 __IO uint16_t FIOSETL;
emilmont 27:7110ebee3484 232 __IO uint16_t FIOSETH;
emilmont 27:7110ebee3484 233 };
emilmont 27:7110ebee3484 234 struct {
emilmont 27:7110ebee3484 235 __IO uint8_t FIOSET0;
emilmont 27:7110ebee3484 236 __IO uint8_t FIOSET1;
emilmont 27:7110ebee3484 237 __IO uint8_t FIOSET2;
emilmont 27:7110ebee3484 238 __IO uint8_t FIOSET3;
emilmont 27:7110ebee3484 239 };
emilmont 27:7110ebee3484 240 };
emilmont 27:7110ebee3484 241 union {
emilmont 27:7110ebee3484 242 __O uint32_t FIOCLR;
emilmont 27:7110ebee3484 243 struct {
emilmont 27:7110ebee3484 244 __O uint16_t FIOCLRL;
emilmont 27:7110ebee3484 245 __O uint16_t FIOCLRH;
emilmont 27:7110ebee3484 246 };
emilmont 27:7110ebee3484 247 struct {
emilmont 27:7110ebee3484 248 __O uint8_t FIOCLR0;
emilmont 27:7110ebee3484 249 __O uint8_t FIOCLR1;
emilmont 27:7110ebee3484 250 __O uint8_t FIOCLR2;
emilmont 27:7110ebee3484 251 __O uint8_t FIOCLR3;
emilmont 27:7110ebee3484 252 };
emilmont 27:7110ebee3484 253 };
emilmont 27:7110ebee3484 254 } LPC_GPIO_TypeDef;
emilmont 27:7110ebee3484 255
emilmont 27:7110ebee3484 256 typedef struct
emilmont 27:7110ebee3484 257 {
emilmont 27:7110ebee3484 258 __I uint32_t IntStatus;
emilmont 27:7110ebee3484 259 __I uint32_t IO0IntStatR;
emilmont 27:7110ebee3484 260 __I uint32_t IO0IntStatF;
emilmont 27:7110ebee3484 261 __O uint32_t IO0IntClr;
emilmont 27:7110ebee3484 262 __IO uint32_t IO0IntEnR;
emilmont 27:7110ebee3484 263 __IO uint32_t IO0IntEnF;
emilmont 27:7110ebee3484 264 uint32_t RESERVED0[3];
emilmont 27:7110ebee3484 265 __I uint32_t IO2IntStatR;
emilmont 27:7110ebee3484 266 __I uint32_t IO2IntStatF;
emilmont 27:7110ebee3484 267 __O uint32_t IO2IntClr;
emilmont 27:7110ebee3484 268 __IO uint32_t IO2IntEnR;
emilmont 27:7110ebee3484 269 __IO uint32_t IO2IntEnF;
emilmont 27:7110ebee3484 270 } LPC_GPIOINT_TypeDef;
emilmont 27:7110ebee3484 271
emilmont 27:7110ebee3484 272 /*------------- Timer (TIM) --------------------------------------------------*/
emilmont 27:7110ebee3484 273 typedef struct
emilmont 27:7110ebee3484 274 {
emilmont 27:7110ebee3484 275 __IO uint32_t IR;
emilmont 27:7110ebee3484 276 __IO uint32_t TCR;
emilmont 27:7110ebee3484 277 __IO uint32_t TC;
emilmont 27:7110ebee3484 278 __IO uint32_t PR;
emilmont 27:7110ebee3484 279 __IO uint32_t PC;
emilmont 27:7110ebee3484 280 __IO uint32_t MCR;
emilmont 27:7110ebee3484 281 __IO uint32_t MR0;
emilmont 27:7110ebee3484 282 __IO uint32_t MR1;
emilmont 27:7110ebee3484 283 __IO uint32_t MR2;
emilmont 27:7110ebee3484 284 __IO uint32_t MR3;
emilmont 27:7110ebee3484 285 __IO uint32_t CCR;
emilmont 27:7110ebee3484 286 __I uint32_t CR0;
emilmont 27:7110ebee3484 287 __I uint32_t CR1;
emilmont 27:7110ebee3484 288 uint32_t RESERVED0[2];
emilmont 27:7110ebee3484 289 __IO uint32_t EMR;
emilmont 27:7110ebee3484 290 uint32_t RESERVED1[12];
emilmont 27:7110ebee3484 291 __IO uint32_t CTCR;
emilmont 27:7110ebee3484 292 } LPC_TIM_TypeDef;
emilmont 27:7110ebee3484 293
emilmont 27:7110ebee3484 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
emilmont 27:7110ebee3484 295 typedef struct
emilmont 27:7110ebee3484 296 {
emilmont 27:7110ebee3484 297 __IO uint32_t IR;
emilmont 27:7110ebee3484 298 __IO uint32_t TCR;
emilmont 27:7110ebee3484 299 __IO uint32_t TC;
emilmont 27:7110ebee3484 300 __IO uint32_t PR;
emilmont 27:7110ebee3484 301 __IO uint32_t PC;
emilmont 27:7110ebee3484 302 __IO uint32_t MCR;
emilmont 27:7110ebee3484 303 __IO uint32_t MR0;
emilmont 27:7110ebee3484 304 __IO uint32_t MR1;
emilmont 27:7110ebee3484 305 __IO uint32_t MR2;
emilmont 27:7110ebee3484 306 __IO uint32_t MR3;
emilmont 27:7110ebee3484 307 __IO uint32_t CCR;
emilmont 27:7110ebee3484 308 __I uint32_t CR0;
emilmont 27:7110ebee3484 309 __I uint32_t CR1;
emilmont 27:7110ebee3484 310 __I uint32_t CR2;
emilmont 27:7110ebee3484 311 __I uint32_t CR3;
emilmont 27:7110ebee3484 312 uint32_t RESERVED0;
emilmont 27:7110ebee3484 313 __IO uint32_t MR4;
emilmont 27:7110ebee3484 314 __IO uint32_t MR5;
emilmont 27:7110ebee3484 315 __IO uint32_t MR6;
emilmont 27:7110ebee3484 316 __IO uint32_t PCR;
emilmont 27:7110ebee3484 317 __IO uint32_t LER;
emilmont 27:7110ebee3484 318 uint32_t RESERVED1[7];
emilmont 27:7110ebee3484 319 __IO uint32_t CTCR;
emilmont 27:7110ebee3484 320 } LPC_PWM_TypeDef;
emilmont 27:7110ebee3484 321
emilmont 27:7110ebee3484 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
emilmont 27:7110ebee3484 323 typedef struct
emilmont 27:7110ebee3484 324 {
emilmont 27:7110ebee3484 325 union {
emilmont 27:7110ebee3484 326 __I uint8_t RBR;
emilmont 27:7110ebee3484 327 __O uint8_t THR;
emilmont 27:7110ebee3484 328 __IO uint8_t DLL;
emilmont 27:7110ebee3484 329 uint32_t RESERVED0;
emilmont 27:7110ebee3484 330 };
emilmont 27:7110ebee3484 331 union {
emilmont 27:7110ebee3484 332 __IO uint8_t DLM;
emilmont 27:7110ebee3484 333 __IO uint32_t IER;
emilmont 27:7110ebee3484 334 };
emilmont 27:7110ebee3484 335 union {
emilmont 27:7110ebee3484 336 __I uint32_t IIR;
emilmont 27:7110ebee3484 337 __O uint8_t FCR;
emilmont 27:7110ebee3484 338 };
emilmont 27:7110ebee3484 339 __IO uint8_t LCR;
emilmont 27:7110ebee3484 340 uint8_t RESERVED1[7];
emilmont 27:7110ebee3484 341 __I uint8_t LSR;
emilmont 27:7110ebee3484 342 uint8_t RESERVED2[7];
emilmont 27:7110ebee3484 343 __IO uint8_t SCR;
emilmont 27:7110ebee3484 344 uint8_t RESERVED3[3];
emilmont 27:7110ebee3484 345 __IO uint32_t ACR;
emilmont 27:7110ebee3484 346 __IO uint8_t ICR;
emilmont 27:7110ebee3484 347 uint8_t RESERVED4[3];
emilmont 27:7110ebee3484 348 __IO uint8_t FDR;
emilmont 27:7110ebee3484 349 uint8_t RESERVED5[7];
emilmont 27:7110ebee3484 350 __IO uint8_t TER;
emilmont 27:7110ebee3484 351 uint8_t RESERVED6[39];
emilmont 27:7110ebee3484 352 __IO uint32_t FIFOLVL;
emilmont 27:7110ebee3484 353 } LPC_UART_TypeDef;
emilmont 27:7110ebee3484 354
emilmont 27:7110ebee3484 355 typedef struct
emilmont 27:7110ebee3484 356 {
emilmont 27:7110ebee3484 357 union {
emilmont 27:7110ebee3484 358 __I uint8_t RBR;
emilmont 27:7110ebee3484 359 __O uint8_t THR;
emilmont 27:7110ebee3484 360 __IO uint8_t DLL;
emilmont 27:7110ebee3484 361 uint32_t RESERVED0;
emilmont 27:7110ebee3484 362 };
emilmont 27:7110ebee3484 363 union {
emilmont 27:7110ebee3484 364 __IO uint8_t DLM;
emilmont 27:7110ebee3484 365 __IO uint32_t IER;
emilmont 27:7110ebee3484 366 };
emilmont 27:7110ebee3484 367 union {
emilmont 27:7110ebee3484 368 __I uint32_t IIR;
emilmont 27:7110ebee3484 369 __O uint8_t FCR;
emilmont 27:7110ebee3484 370 };
emilmont 27:7110ebee3484 371 __IO uint8_t LCR;
emilmont 27:7110ebee3484 372 uint8_t RESERVED1[7];
emilmont 27:7110ebee3484 373 __I uint8_t LSR;
emilmont 27:7110ebee3484 374 uint8_t RESERVED2[7];
emilmont 27:7110ebee3484 375 __IO uint8_t SCR;
emilmont 27:7110ebee3484 376 uint8_t RESERVED3[3];
emilmont 27:7110ebee3484 377 __IO uint32_t ACR;
emilmont 27:7110ebee3484 378 __IO uint8_t ICR;
emilmont 27:7110ebee3484 379 uint8_t RESERVED4[3];
emilmont 27:7110ebee3484 380 __IO uint8_t FDR;
emilmont 27:7110ebee3484 381 uint8_t RESERVED5[7];
emilmont 27:7110ebee3484 382 __IO uint8_t TER;
emilmont 27:7110ebee3484 383 uint8_t RESERVED6[39];
emilmont 27:7110ebee3484 384 __IO uint32_t FIFOLVL;
emilmont 27:7110ebee3484 385 } LPC_UART0_TypeDef;
emilmont 27:7110ebee3484 386
emilmont 27:7110ebee3484 387 typedef struct
emilmont 27:7110ebee3484 388 {
emilmont 27:7110ebee3484 389 union {
emilmont 27:7110ebee3484 390 __I uint8_t RBR;
emilmont 27:7110ebee3484 391 __O uint8_t THR;
emilmont 27:7110ebee3484 392 __IO uint8_t DLL;
emilmont 27:7110ebee3484 393 uint32_t RESERVED0;
emilmont 27:7110ebee3484 394 };
emilmont 27:7110ebee3484 395 union {
emilmont 27:7110ebee3484 396 __IO uint8_t DLM;
emilmont 27:7110ebee3484 397 __IO uint32_t IER;
emilmont 27:7110ebee3484 398 };
emilmont 27:7110ebee3484 399 union {
emilmont 27:7110ebee3484 400 __I uint32_t IIR;
emilmont 27:7110ebee3484 401 __O uint8_t FCR;
emilmont 27:7110ebee3484 402 };
emilmont 27:7110ebee3484 403 __IO uint8_t LCR;
emilmont 27:7110ebee3484 404 uint8_t RESERVED1[3];
emilmont 27:7110ebee3484 405 __IO uint8_t MCR;
emilmont 27:7110ebee3484 406 uint8_t RESERVED2[3];
emilmont 27:7110ebee3484 407 __I uint8_t LSR;
emilmont 27:7110ebee3484 408 uint8_t RESERVED3[3];
emilmont 27:7110ebee3484 409 __I uint8_t MSR;
emilmont 27:7110ebee3484 410 uint8_t RESERVED4[3];
emilmont 27:7110ebee3484 411 __IO uint8_t SCR;
emilmont 27:7110ebee3484 412 uint8_t RESERVED5[3];
emilmont 27:7110ebee3484 413 __IO uint32_t ACR;
emilmont 27:7110ebee3484 414 uint32_t RESERVED6;
emilmont 27:7110ebee3484 415 __IO uint32_t FDR;
emilmont 27:7110ebee3484 416 uint32_t RESERVED7;
emilmont 27:7110ebee3484 417 __IO uint8_t TER;
emilmont 27:7110ebee3484 418 uint8_t RESERVED8[27];
emilmont 27:7110ebee3484 419 __IO uint8_t RS485CTRL;
emilmont 27:7110ebee3484 420 uint8_t RESERVED9[3];
emilmont 27:7110ebee3484 421 __IO uint8_t ADRMATCH;
emilmont 27:7110ebee3484 422 uint8_t RESERVED10[3];
emilmont 27:7110ebee3484 423 __IO uint8_t RS485DLY;
emilmont 27:7110ebee3484 424 uint8_t RESERVED11[3];
emilmont 27:7110ebee3484 425 __IO uint32_t FIFOLVL;
emilmont 27:7110ebee3484 426 } LPC_UART1_TypeDef;
emilmont 27:7110ebee3484 427
emilmont 27:7110ebee3484 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
emilmont 27:7110ebee3484 429 typedef struct
emilmont 27:7110ebee3484 430 {
emilmont 27:7110ebee3484 431 __IO uint32_t SPCR;
emilmont 27:7110ebee3484 432 __I uint32_t SPSR;
emilmont 27:7110ebee3484 433 __IO uint32_t SPDR;
emilmont 27:7110ebee3484 434 __IO uint32_t SPCCR;
emilmont 27:7110ebee3484 435 uint32_t RESERVED0[3];
emilmont 27:7110ebee3484 436 __IO uint32_t SPINT;
emilmont 27:7110ebee3484 437 } LPC_SPI_TypeDef;
emilmont 27:7110ebee3484 438
emilmont 27:7110ebee3484 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
emilmont 27:7110ebee3484 440 typedef struct
emilmont 27:7110ebee3484 441 {
emilmont 27:7110ebee3484 442 __IO uint32_t CR0;
emilmont 27:7110ebee3484 443 __IO uint32_t CR1;
emilmont 27:7110ebee3484 444 __IO uint32_t DR;
emilmont 27:7110ebee3484 445 __I uint32_t SR;
emilmont 27:7110ebee3484 446 __IO uint32_t CPSR;
emilmont 27:7110ebee3484 447 __IO uint32_t IMSC;
emilmont 27:7110ebee3484 448 __IO uint32_t RIS;
emilmont 27:7110ebee3484 449 __IO uint32_t MIS;
emilmont 27:7110ebee3484 450 __IO uint32_t ICR;
emilmont 27:7110ebee3484 451 __IO uint32_t DMACR;
emilmont 27:7110ebee3484 452 } LPC_SSP_TypeDef;
emilmont 27:7110ebee3484 453
emilmont 27:7110ebee3484 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
emilmont 27:7110ebee3484 455 typedef struct
emilmont 27:7110ebee3484 456 {
emilmont 27:7110ebee3484 457 __IO uint32_t I2CONSET;
emilmont 27:7110ebee3484 458 __I uint32_t I2STAT;
emilmont 27:7110ebee3484 459 __IO uint32_t I2DAT;
emilmont 27:7110ebee3484 460 __IO uint32_t I2ADR0;
emilmont 27:7110ebee3484 461 __IO uint32_t I2SCLH;
emilmont 27:7110ebee3484 462 __IO uint32_t I2SCLL;
emilmont 27:7110ebee3484 463 __O uint32_t I2CONCLR;
emilmont 27:7110ebee3484 464 __IO uint32_t MMCTRL;
emilmont 27:7110ebee3484 465 __IO uint32_t I2ADR1;
emilmont 27:7110ebee3484 466 __IO uint32_t I2ADR2;
emilmont 27:7110ebee3484 467 __IO uint32_t I2ADR3;
emilmont 27:7110ebee3484 468 __I uint32_t I2DATA_BUFFER;
emilmont 27:7110ebee3484 469 __IO uint32_t I2MASK0;
emilmont 27:7110ebee3484 470 __IO uint32_t I2MASK1;
emilmont 27:7110ebee3484 471 __IO uint32_t I2MASK2;
emilmont 27:7110ebee3484 472 __IO uint32_t I2MASK3;
emilmont 27:7110ebee3484 473 } LPC_I2C_TypeDef;
emilmont 27:7110ebee3484 474
emilmont 27:7110ebee3484 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
emilmont 27:7110ebee3484 476 typedef struct
emilmont 27:7110ebee3484 477 {
emilmont 27:7110ebee3484 478 __IO uint32_t I2SDAO;
emilmont 27:7110ebee3484 479 __IO uint32_t I2SDAI;
emilmont 27:7110ebee3484 480 __O uint32_t I2STXFIFO;
emilmont 27:7110ebee3484 481 __I uint32_t I2SRXFIFO;
emilmont 27:7110ebee3484 482 __I uint32_t I2SSTATE;
emilmont 27:7110ebee3484 483 __IO uint32_t I2SDMA1;
emilmont 27:7110ebee3484 484 __IO uint32_t I2SDMA2;
emilmont 27:7110ebee3484 485 __IO uint32_t I2SIRQ;
emilmont 27:7110ebee3484 486 __IO uint32_t I2STXRATE;
emilmont 27:7110ebee3484 487 __IO uint32_t I2SRXRATE;
emilmont 27:7110ebee3484 488 __IO uint32_t I2STXBITRATE;
emilmont 27:7110ebee3484 489 __IO uint32_t I2SRXBITRATE;
emilmont 27:7110ebee3484 490 __IO uint32_t I2STXMODE;
emilmont 27:7110ebee3484 491 __IO uint32_t I2SRXMODE;
emilmont 27:7110ebee3484 492 } LPC_I2S_TypeDef;
emilmont 27:7110ebee3484 493
emilmont 27:7110ebee3484 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
emilmont 27:7110ebee3484 495 typedef struct
emilmont 27:7110ebee3484 496 {
emilmont 27:7110ebee3484 497 __IO uint32_t RICOMPVAL;
emilmont 27:7110ebee3484 498 __IO uint32_t RIMASK;
emilmont 27:7110ebee3484 499 __IO uint8_t RICTRL;
emilmont 27:7110ebee3484 500 uint8_t RESERVED0[3];
emilmont 27:7110ebee3484 501 __IO uint32_t RICOUNTER;
emilmont 27:7110ebee3484 502 } LPC_RIT_TypeDef;
emilmont 27:7110ebee3484 503
emilmont 27:7110ebee3484 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
emilmont 27:7110ebee3484 505 typedef struct
emilmont 27:7110ebee3484 506 {
emilmont 27:7110ebee3484 507 __IO uint8_t ILR;
emilmont 27:7110ebee3484 508 uint8_t RESERVED0[7];
emilmont 27:7110ebee3484 509 __IO uint8_t CCR;
emilmont 27:7110ebee3484 510 uint8_t RESERVED1[3];
emilmont 27:7110ebee3484 511 __IO uint8_t CIIR;
emilmont 27:7110ebee3484 512 uint8_t RESERVED2[3];
emilmont 27:7110ebee3484 513 __IO uint8_t AMR;
emilmont 27:7110ebee3484 514 uint8_t RESERVED3[3];
emilmont 27:7110ebee3484 515 __I uint32_t CTIME0;
emilmont 27:7110ebee3484 516 __I uint32_t CTIME1;
emilmont 27:7110ebee3484 517 __I uint32_t CTIME2;
emilmont 27:7110ebee3484 518 __IO uint8_t SEC;
emilmont 27:7110ebee3484 519 uint8_t RESERVED4[3];
emilmont 27:7110ebee3484 520 __IO uint8_t MIN;
emilmont 27:7110ebee3484 521 uint8_t RESERVED5[3];
emilmont 27:7110ebee3484 522 __IO uint8_t HOUR;
emilmont 27:7110ebee3484 523 uint8_t RESERVED6[3];
emilmont 27:7110ebee3484 524 __IO uint8_t DOM;
emilmont 27:7110ebee3484 525 uint8_t RESERVED7[3];
emilmont 27:7110ebee3484 526 __IO uint8_t DOW;
emilmont 27:7110ebee3484 527 uint8_t RESERVED8[3];
emilmont 27:7110ebee3484 528 __IO uint16_t DOY;
emilmont 27:7110ebee3484 529 uint16_t RESERVED9;
emilmont 27:7110ebee3484 530 __IO uint8_t MONTH;
emilmont 27:7110ebee3484 531 uint8_t RESERVED10[3];
emilmont 27:7110ebee3484 532 __IO uint16_t YEAR;
emilmont 27:7110ebee3484 533 uint16_t RESERVED11;
emilmont 27:7110ebee3484 534 __IO uint32_t CALIBRATION;
emilmont 27:7110ebee3484 535 __IO uint32_t GPREG0;
emilmont 27:7110ebee3484 536 __IO uint32_t GPREG1;
emilmont 27:7110ebee3484 537 __IO uint32_t GPREG2;
emilmont 27:7110ebee3484 538 __IO uint32_t GPREG3;
emilmont 27:7110ebee3484 539 __IO uint32_t GPREG4;
emilmont 27:7110ebee3484 540 __IO uint8_t RTC_AUXEN;
emilmont 27:7110ebee3484 541 uint8_t RESERVED12[3];
emilmont 27:7110ebee3484 542 __IO uint8_t RTC_AUX;
emilmont 27:7110ebee3484 543 uint8_t RESERVED13[3];
emilmont 27:7110ebee3484 544 __IO uint8_t ALSEC;
emilmont 27:7110ebee3484 545 uint8_t RESERVED14[3];
emilmont 27:7110ebee3484 546 __IO uint8_t ALMIN;
emilmont 27:7110ebee3484 547 uint8_t RESERVED15[3];
emilmont 27:7110ebee3484 548 __IO uint8_t ALHOUR;
emilmont 27:7110ebee3484 549 uint8_t RESERVED16[3];
emilmont 27:7110ebee3484 550 __IO uint8_t ALDOM;
emilmont 27:7110ebee3484 551 uint8_t RESERVED17[3];
emilmont 27:7110ebee3484 552 __IO uint8_t ALDOW;
emilmont 27:7110ebee3484 553 uint8_t RESERVED18[3];
emilmont 27:7110ebee3484 554 __IO uint16_t ALDOY;
emilmont 27:7110ebee3484 555 uint16_t RESERVED19;
emilmont 27:7110ebee3484 556 __IO uint8_t ALMON;
emilmont 27:7110ebee3484 557 uint8_t RESERVED20[3];
emilmont 27:7110ebee3484 558 __IO uint16_t ALYEAR;
emilmont 27:7110ebee3484 559 uint16_t RESERVED21;
emilmont 27:7110ebee3484 560 } LPC_RTC_TypeDef;
emilmont 27:7110ebee3484 561
emilmont 27:7110ebee3484 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
emilmont 27:7110ebee3484 563 typedef struct
emilmont 27:7110ebee3484 564 {
emilmont 27:7110ebee3484 565 __IO uint8_t WDMOD;
emilmont 27:7110ebee3484 566 uint8_t RESERVED0[3];
emilmont 27:7110ebee3484 567 __IO uint32_t WDTC;
emilmont 27:7110ebee3484 568 __O uint8_t WDFEED;
emilmont 27:7110ebee3484 569 uint8_t RESERVED1[3];
emilmont 27:7110ebee3484 570 __I uint32_t WDTV;
emilmont 27:7110ebee3484 571 __IO uint32_t WDCLKSEL;
emilmont 27:7110ebee3484 572 } LPC_WDT_TypeDef;
emilmont 27:7110ebee3484 573
emilmont 27:7110ebee3484 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
emilmont 27:7110ebee3484 575 typedef struct
emilmont 27:7110ebee3484 576 {
emilmont 27:7110ebee3484 577 __IO uint32_t ADCR;
emilmont 27:7110ebee3484 578 __IO uint32_t ADGDR;
emilmont 27:7110ebee3484 579 uint32_t RESERVED0;
emilmont 27:7110ebee3484 580 __IO uint32_t ADINTEN;
emilmont 27:7110ebee3484 581 __I uint32_t ADDR0;
emilmont 27:7110ebee3484 582 __I uint32_t ADDR1;
emilmont 27:7110ebee3484 583 __I uint32_t ADDR2;
emilmont 27:7110ebee3484 584 __I uint32_t ADDR3;
emilmont 27:7110ebee3484 585 __I uint32_t ADDR4;
emilmont 27:7110ebee3484 586 __I uint32_t ADDR5;
emilmont 27:7110ebee3484 587 __I uint32_t ADDR6;
emilmont 27:7110ebee3484 588 __I uint32_t ADDR7;
emilmont 27:7110ebee3484 589 __I uint32_t ADSTAT;
emilmont 27:7110ebee3484 590 __IO uint32_t ADTRM;
emilmont 27:7110ebee3484 591 } LPC_ADC_TypeDef;
emilmont 27:7110ebee3484 592
emilmont 27:7110ebee3484 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
emilmont 27:7110ebee3484 594 typedef struct
emilmont 27:7110ebee3484 595 {
emilmont 27:7110ebee3484 596 __IO uint32_t DACR;
emilmont 27:7110ebee3484 597 __IO uint32_t DACCTRL;
emilmont 27:7110ebee3484 598 __IO uint16_t DACCNTVAL;
emilmont 27:7110ebee3484 599 } LPC_DAC_TypeDef;
emilmont 27:7110ebee3484 600
emilmont 27:7110ebee3484 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
emilmont 27:7110ebee3484 602 typedef struct
emilmont 27:7110ebee3484 603 {
emilmont 27:7110ebee3484 604 __I uint32_t MCCON;
emilmont 27:7110ebee3484 605 __O uint32_t MCCON_SET;
emilmont 27:7110ebee3484 606 __O uint32_t MCCON_CLR;
emilmont 27:7110ebee3484 607 __I uint32_t MCCAPCON;
emilmont 27:7110ebee3484 608 __O uint32_t MCCAPCON_SET;
emilmont 27:7110ebee3484 609 __O uint32_t MCCAPCON_CLR;
emilmont 27:7110ebee3484 610 __IO uint32_t MCTIM0;
emilmont 27:7110ebee3484 611 __IO uint32_t MCTIM1;
emilmont 27:7110ebee3484 612 __IO uint32_t MCTIM2;
emilmont 27:7110ebee3484 613 __IO uint32_t MCPER0;
emilmont 27:7110ebee3484 614 __IO uint32_t MCPER1;
emilmont 27:7110ebee3484 615 __IO uint32_t MCPER2;
emilmont 27:7110ebee3484 616 __IO uint32_t MCPW0;
emilmont 27:7110ebee3484 617 __IO uint32_t MCPW1;
emilmont 27:7110ebee3484 618 __IO uint32_t MCPW2;
emilmont 27:7110ebee3484 619 __IO uint32_t MCDEADTIME;
emilmont 27:7110ebee3484 620 __IO uint32_t MCCCP;
emilmont 27:7110ebee3484 621 __IO uint32_t MCCR0;
emilmont 27:7110ebee3484 622 __IO uint32_t MCCR1;
emilmont 27:7110ebee3484 623 __IO uint32_t MCCR2;
emilmont 27:7110ebee3484 624 __I uint32_t MCINTEN;
emilmont 27:7110ebee3484 625 __O uint32_t MCINTEN_SET;
emilmont 27:7110ebee3484 626 __O uint32_t MCINTEN_CLR;
emilmont 27:7110ebee3484 627 __I uint32_t MCCNTCON;
emilmont 27:7110ebee3484 628 __O uint32_t MCCNTCON_SET;
emilmont 27:7110ebee3484 629 __O uint32_t MCCNTCON_CLR;
emilmont 27:7110ebee3484 630 __I uint32_t MCINTFLAG;
emilmont 27:7110ebee3484 631 __O uint32_t MCINTFLAG_SET;
emilmont 27:7110ebee3484 632 __O uint32_t MCINTFLAG_CLR;
emilmont 27:7110ebee3484 633 __O uint32_t MCCAP_CLR;
emilmont 27:7110ebee3484 634 } LPC_MCPWM_TypeDef;
emilmont 27:7110ebee3484 635
emilmont 27:7110ebee3484 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
emilmont 27:7110ebee3484 637 typedef struct
emilmont 27:7110ebee3484 638 {
emilmont 27:7110ebee3484 639 __O uint32_t QEICON;
emilmont 27:7110ebee3484 640 __I uint32_t QEISTAT;
emilmont 27:7110ebee3484 641 __IO uint32_t QEICONF;
emilmont 27:7110ebee3484 642 __I uint32_t QEIPOS;
emilmont 27:7110ebee3484 643 __IO uint32_t QEIMAXPOS;
emilmont 27:7110ebee3484 644 __IO uint32_t CMPOS0;
emilmont 27:7110ebee3484 645 __IO uint32_t CMPOS1;
emilmont 27:7110ebee3484 646 __IO uint32_t CMPOS2;
emilmont 27:7110ebee3484 647 __I uint32_t INXCNT;
emilmont 27:7110ebee3484 648 __IO uint32_t INXCMP;
emilmont 27:7110ebee3484 649 __IO uint32_t QEILOAD;
emilmont 27:7110ebee3484 650 __I uint32_t QEITIME;
emilmont 27:7110ebee3484 651 __I uint32_t QEIVEL;
emilmont 27:7110ebee3484 652 __I uint32_t QEICAP;
emilmont 27:7110ebee3484 653 __IO uint32_t VELCOMP;
emilmont 27:7110ebee3484 654 __IO uint32_t FILTER;
emilmont 27:7110ebee3484 655 uint32_t RESERVED0[998];
emilmont 27:7110ebee3484 656 __O uint32_t QEIIEC;
emilmont 27:7110ebee3484 657 __O uint32_t QEIIES;
emilmont 27:7110ebee3484 658 __I uint32_t QEIINTSTAT;
emilmont 27:7110ebee3484 659 __I uint32_t QEIIE;
emilmont 27:7110ebee3484 660 __O uint32_t QEICLR;
emilmont 27:7110ebee3484 661 __O uint32_t QEISET;
emilmont 27:7110ebee3484 662 } LPC_QEI_TypeDef;
emilmont 27:7110ebee3484 663
emilmont 27:7110ebee3484 664 /*------------- Controller Area Network (CAN) --------------------------------*/
emilmont 27:7110ebee3484 665 typedef struct
emilmont 27:7110ebee3484 666 {
emilmont 27:7110ebee3484 667 __IO uint32_t mask[512]; /* ID Masks */
emilmont 27:7110ebee3484 668 } LPC_CANAF_RAM_TypeDef;
emilmont 27:7110ebee3484 669
emilmont 27:7110ebee3484 670 typedef struct /* Acceptance Filter Registers */
emilmont 27:7110ebee3484 671 {
emilmont 27:7110ebee3484 672 __IO uint32_t AFMR;
emilmont 27:7110ebee3484 673 __IO uint32_t SFF_sa;
emilmont 27:7110ebee3484 674 __IO uint32_t SFF_GRP_sa;
emilmont 27:7110ebee3484 675 __IO uint32_t EFF_sa;
emilmont 27:7110ebee3484 676 __IO uint32_t EFF_GRP_sa;
emilmont 27:7110ebee3484 677 __IO uint32_t ENDofTable;
emilmont 27:7110ebee3484 678 __I uint32_t LUTerrAd;
emilmont 27:7110ebee3484 679 __I uint32_t LUTerr;
emilmont 27:7110ebee3484 680 __IO uint32_t FCANIE;
emilmont 27:7110ebee3484 681 __IO uint32_t FCANIC0;
emilmont 27:7110ebee3484 682 __IO uint32_t FCANIC1;
emilmont 27:7110ebee3484 683 } LPC_CANAF_TypeDef;
emilmont 27:7110ebee3484 684
emilmont 27:7110ebee3484 685 typedef struct /* Central Registers */
emilmont 27:7110ebee3484 686 {
emilmont 27:7110ebee3484 687 __I uint32_t CANTxSR;
emilmont 27:7110ebee3484 688 __I uint32_t CANRxSR;
emilmont 27:7110ebee3484 689 __I uint32_t CANMSR;
emilmont 27:7110ebee3484 690 } LPC_CANCR_TypeDef;
emilmont 27:7110ebee3484 691
emilmont 27:7110ebee3484 692 typedef struct /* Controller Registers */
emilmont 27:7110ebee3484 693 {
emilmont 27:7110ebee3484 694 __IO uint32_t MOD;
emilmont 27:7110ebee3484 695 __O uint32_t CMR;
emilmont 27:7110ebee3484 696 __IO uint32_t GSR;
emilmont 27:7110ebee3484 697 __I uint32_t ICR;
emilmont 27:7110ebee3484 698 __IO uint32_t IER;
emilmont 27:7110ebee3484 699 __IO uint32_t BTR;
emilmont 27:7110ebee3484 700 __IO uint32_t EWL;
emilmont 27:7110ebee3484 701 __I uint32_t SR;
emilmont 27:7110ebee3484 702 __IO uint32_t RFS;
emilmont 27:7110ebee3484 703 __IO uint32_t RID;
emilmont 27:7110ebee3484 704 __IO uint32_t RDA;
emilmont 27:7110ebee3484 705 __IO uint32_t RDB;
emilmont 27:7110ebee3484 706 __IO uint32_t TFI1;
emilmont 27:7110ebee3484 707 __IO uint32_t TID1;
emilmont 27:7110ebee3484 708 __IO uint32_t TDA1;
emilmont 27:7110ebee3484 709 __IO uint32_t TDB1;
emilmont 27:7110ebee3484 710 __IO uint32_t TFI2;
emilmont 27:7110ebee3484 711 __IO uint32_t TID2;
emilmont 27:7110ebee3484 712 __IO uint32_t TDA2;
emilmont 27:7110ebee3484 713 __IO uint32_t TDB2;
emilmont 27:7110ebee3484 714 __IO uint32_t TFI3;
emilmont 27:7110ebee3484 715 __IO uint32_t TID3;
emilmont 27:7110ebee3484 716 __IO uint32_t TDA3;
emilmont 27:7110ebee3484 717 __IO uint32_t TDB3;
emilmont 27:7110ebee3484 718 } LPC_CAN_TypeDef;
emilmont 27:7110ebee3484 719
emilmont 27:7110ebee3484 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
emilmont 27:7110ebee3484 721 typedef struct /* Common Registers */
emilmont 27:7110ebee3484 722 {
emilmont 27:7110ebee3484 723 __I uint32_t DMACIntStat;
emilmont 27:7110ebee3484 724 __I uint32_t DMACIntTCStat;
emilmont 27:7110ebee3484 725 __O uint32_t DMACIntTCClear;
emilmont 27:7110ebee3484 726 __I uint32_t DMACIntErrStat;
emilmont 27:7110ebee3484 727 __O uint32_t DMACIntErrClr;
emilmont 27:7110ebee3484 728 __I uint32_t DMACRawIntTCStat;
emilmont 27:7110ebee3484 729 __I uint32_t DMACRawIntErrStat;
emilmont 27:7110ebee3484 730 __I uint32_t DMACEnbldChns;
emilmont 27:7110ebee3484 731 __IO uint32_t DMACSoftBReq;
emilmont 27:7110ebee3484 732 __IO uint32_t DMACSoftSReq;
emilmont 27:7110ebee3484 733 __IO uint32_t DMACSoftLBReq;
emilmont 27:7110ebee3484 734 __IO uint32_t DMACSoftLSReq;
emilmont 27:7110ebee3484 735 __IO uint32_t DMACConfig;
emilmont 27:7110ebee3484 736 __IO uint32_t DMACSync;
emilmont 27:7110ebee3484 737 } LPC_GPDMA_TypeDef;
emilmont 27:7110ebee3484 738
emilmont 27:7110ebee3484 739 typedef struct /* Channel Registers */
emilmont 27:7110ebee3484 740 {
emilmont 27:7110ebee3484 741 __IO uint32_t DMACCSrcAddr;
emilmont 27:7110ebee3484 742 __IO uint32_t DMACCDestAddr;
emilmont 27:7110ebee3484 743 __IO uint32_t DMACCLLI;
emilmont 27:7110ebee3484 744 __IO uint32_t DMACCControl;
emilmont 27:7110ebee3484 745 __IO uint32_t DMACCConfig;
emilmont 27:7110ebee3484 746 } LPC_GPDMACH_TypeDef;
emilmont 27:7110ebee3484 747
emilmont 27:7110ebee3484 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
emilmont 27:7110ebee3484 749 typedef struct
emilmont 27:7110ebee3484 750 {
emilmont 27:7110ebee3484 751 __I uint32_t HcRevision; /* USB Host Registers */
emilmont 27:7110ebee3484 752 __IO uint32_t HcControl;
emilmont 27:7110ebee3484 753 __IO uint32_t HcCommandStatus;
emilmont 27:7110ebee3484 754 __IO uint32_t HcInterruptStatus;
emilmont 27:7110ebee3484 755 __IO uint32_t HcInterruptEnable;
emilmont 27:7110ebee3484 756 __IO uint32_t HcInterruptDisable;
emilmont 27:7110ebee3484 757 __IO uint32_t HcHCCA;
emilmont 27:7110ebee3484 758 __I uint32_t HcPeriodCurrentED;
emilmont 27:7110ebee3484 759 __IO uint32_t HcControlHeadED;
emilmont 27:7110ebee3484 760 __IO uint32_t HcControlCurrentED;
emilmont 27:7110ebee3484 761 __IO uint32_t HcBulkHeadED;
emilmont 27:7110ebee3484 762 __IO uint32_t HcBulkCurrentED;
emilmont 27:7110ebee3484 763 __I uint32_t HcDoneHead;
emilmont 27:7110ebee3484 764 __IO uint32_t HcFmInterval;
emilmont 27:7110ebee3484 765 __I uint32_t HcFmRemaining;
emilmont 27:7110ebee3484 766 __I uint32_t HcFmNumber;
emilmont 27:7110ebee3484 767 __IO uint32_t HcPeriodicStart;
emilmont 27:7110ebee3484 768 __IO uint32_t HcLSTreshold;
emilmont 27:7110ebee3484 769 __IO uint32_t HcRhDescriptorA;
emilmont 27:7110ebee3484 770 __IO uint32_t HcRhDescriptorB;
emilmont 27:7110ebee3484 771 __IO uint32_t HcRhStatus;
emilmont 27:7110ebee3484 772 __IO uint32_t HcRhPortStatus1;
emilmont 27:7110ebee3484 773 __IO uint32_t HcRhPortStatus2;
emilmont 27:7110ebee3484 774 uint32_t RESERVED0[40];
emilmont 27:7110ebee3484 775 __I uint32_t Module_ID;
emilmont 27:7110ebee3484 776
emilmont 27:7110ebee3484 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
emilmont 27:7110ebee3484 778 __IO uint32_t OTGIntEn;
emilmont 27:7110ebee3484 779 __O uint32_t OTGIntSet;
emilmont 27:7110ebee3484 780 __O uint32_t OTGIntClr;
emilmont 27:7110ebee3484 781 __IO uint32_t OTGStCtrl;
emilmont 27:7110ebee3484 782 __IO uint32_t OTGTmr;
emilmont 27:7110ebee3484 783 uint32_t RESERVED1[58];
emilmont 27:7110ebee3484 784
emilmont 27:7110ebee3484 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
emilmont 27:7110ebee3484 786 __IO uint32_t USBDevIntEn;
emilmont 27:7110ebee3484 787 __O uint32_t USBDevIntClr;
emilmont 27:7110ebee3484 788 __O uint32_t USBDevIntSet;
emilmont 27:7110ebee3484 789
emilmont 27:7110ebee3484 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
emilmont 27:7110ebee3484 791 __I uint32_t USBCmdData;
emilmont 27:7110ebee3484 792
emilmont 27:7110ebee3484 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
emilmont 27:7110ebee3484 794 __O uint32_t USBTxData;
emilmont 27:7110ebee3484 795 __I uint32_t USBRxPLen;
emilmont 27:7110ebee3484 796 __O uint32_t USBTxPLen;
emilmont 27:7110ebee3484 797 __IO uint32_t USBCtrl;
emilmont 27:7110ebee3484 798 __O uint32_t USBDevIntPri;
emilmont 27:7110ebee3484 799
emilmont 27:7110ebee3484 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
emilmont 27:7110ebee3484 801 __IO uint32_t USBEpIntEn;
emilmont 27:7110ebee3484 802 __O uint32_t USBEpIntClr;
emilmont 27:7110ebee3484 803 __O uint32_t USBEpIntSet;
emilmont 27:7110ebee3484 804 __O uint32_t USBEpIntPri;
emilmont 27:7110ebee3484 805
emilmont 27:7110ebee3484 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
emilmont 27:7110ebee3484 807 __O uint32_t USBEpInd;
emilmont 27:7110ebee3484 808 __IO uint32_t USBMaxPSize;
emilmont 27:7110ebee3484 809
emilmont 27:7110ebee3484 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
emilmont 27:7110ebee3484 811 __O uint32_t USBDMARClr;
emilmont 27:7110ebee3484 812 __O uint32_t USBDMARSet;
emilmont 27:7110ebee3484 813 uint32_t RESERVED2[9];
emilmont 27:7110ebee3484 814 __IO uint32_t USBUDCAH;
emilmont 27:7110ebee3484 815 __I uint32_t USBEpDMASt;
emilmont 27:7110ebee3484 816 __O uint32_t USBEpDMAEn;
emilmont 27:7110ebee3484 817 __O uint32_t USBEpDMADis;
emilmont 27:7110ebee3484 818 __I uint32_t USBDMAIntSt;
emilmont 27:7110ebee3484 819 __IO uint32_t USBDMAIntEn;
emilmont 27:7110ebee3484 820 uint32_t RESERVED3[2];
emilmont 27:7110ebee3484 821 __I uint32_t USBEoTIntSt;
emilmont 27:7110ebee3484 822 __O uint32_t USBEoTIntClr;
emilmont 27:7110ebee3484 823 __O uint32_t USBEoTIntSet;
emilmont 27:7110ebee3484 824 __I uint32_t USBNDDRIntSt;
emilmont 27:7110ebee3484 825 __O uint32_t USBNDDRIntClr;
emilmont 27:7110ebee3484 826 __O uint32_t USBNDDRIntSet;
emilmont 27:7110ebee3484 827 __I uint32_t USBSysErrIntSt;
emilmont 27:7110ebee3484 828 __O uint32_t USBSysErrIntClr;
emilmont 27:7110ebee3484 829 __O uint32_t USBSysErrIntSet;
emilmont 27:7110ebee3484 830 uint32_t RESERVED4[15];
emilmont 27:7110ebee3484 831
emilmont 27:7110ebee3484 832 union {
emilmont 27:7110ebee3484 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
emilmont 27:7110ebee3484 834 __O uint32_t I2C_TX;
emilmont 27:7110ebee3484 835 };
emilmont 27:7110ebee3484 836 __I uint32_t I2C_STS;
emilmont 27:7110ebee3484 837 __IO uint32_t I2C_CTL;
emilmont 27:7110ebee3484 838 __IO uint32_t I2C_CLKHI;
emilmont 27:7110ebee3484 839 __O uint32_t I2C_CLKLO;
emilmont 27:7110ebee3484 840 uint32_t RESERVED5[824];
emilmont 27:7110ebee3484 841
emilmont 27:7110ebee3484 842 union {
emilmont 27:7110ebee3484 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
emilmont 27:7110ebee3484 844 __IO uint32_t OTGClkCtrl;
emilmont 27:7110ebee3484 845 };
emilmont 27:7110ebee3484 846 union {
emilmont 27:7110ebee3484 847 __I uint32_t USBClkSt;
emilmont 27:7110ebee3484 848 __I uint32_t OTGClkSt;
emilmont 27:7110ebee3484 849 };
emilmont 27:7110ebee3484 850 } LPC_USB_TypeDef;
emilmont 27:7110ebee3484 851
emilmont 27:7110ebee3484 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
emilmont 27:7110ebee3484 853 typedef struct
emilmont 27:7110ebee3484 854 {
emilmont 27:7110ebee3484 855 __IO uint32_t MAC1; /* MAC Registers */
emilmont 27:7110ebee3484 856 __IO uint32_t MAC2;
emilmont 27:7110ebee3484 857 __IO uint32_t IPGT;
emilmont 27:7110ebee3484 858 __IO uint32_t IPGR;
emilmont 27:7110ebee3484 859 __IO uint32_t CLRT;
emilmont 27:7110ebee3484 860 __IO uint32_t MAXF;
emilmont 27:7110ebee3484 861 __IO uint32_t SUPP;
emilmont 27:7110ebee3484 862 __IO uint32_t TEST;
emilmont 27:7110ebee3484 863 __IO uint32_t MCFG;
emilmont 27:7110ebee3484 864 __IO uint32_t MCMD;
emilmont 27:7110ebee3484 865 __IO uint32_t MADR;
emilmont 27:7110ebee3484 866 __O uint32_t MWTD;
emilmont 27:7110ebee3484 867 __I uint32_t MRDD;
emilmont 27:7110ebee3484 868 __I uint32_t MIND;
emilmont 27:7110ebee3484 869 uint32_t RESERVED0[2];
emilmont 27:7110ebee3484 870 __IO uint32_t SA0;
emilmont 27:7110ebee3484 871 __IO uint32_t SA1;
emilmont 27:7110ebee3484 872 __IO uint32_t SA2;
emilmont 27:7110ebee3484 873 uint32_t RESERVED1[45];
emilmont 27:7110ebee3484 874 __IO uint32_t Command; /* Control Registers */
emilmont 27:7110ebee3484 875 __I uint32_t Status;
emilmont 27:7110ebee3484 876 __IO uint32_t RxDescriptor;
emilmont 27:7110ebee3484 877 __IO uint32_t RxStatus;
emilmont 27:7110ebee3484 878 __IO uint32_t RxDescriptorNumber;
emilmont 27:7110ebee3484 879 __I uint32_t RxProduceIndex;
emilmont 27:7110ebee3484 880 __IO uint32_t RxConsumeIndex;
emilmont 27:7110ebee3484 881 __IO uint32_t TxDescriptor;
emilmont 27:7110ebee3484 882 __IO uint32_t TxStatus;
emilmont 27:7110ebee3484 883 __IO uint32_t TxDescriptorNumber;
emilmont 27:7110ebee3484 884 __IO uint32_t TxProduceIndex;
emilmont 27:7110ebee3484 885 __I uint32_t TxConsumeIndex;
emilmont 27:7110ebee3484 886 uint32_t RESERVED2[10];
emilmont 27:7110ebee3484 887 __I uint32_t TSV0;
emilmont 27:7110ebee3484 888 __I uint32_t TSV1;
emilmont 27:7110ebee3484 889 __I uint32_t RSV;
emilmont 27:7110ebee3484 890 uint32_t RESERVED3[3];
emilmont 27:7110ebee3484 891 __IO uint32_t FlowControlCounter;
emilmont 27:7110ebee3484 892 __I uint32_t FlowControlStatus;
emilmont 27:7110ebee3484 893 uint32_t RESERVED4[34];
emilmont 27:7110ebee3484 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
emilmont 27:7110ebee3484 895 __IO uint32_t RxFilterWoLStatus;
emilmont 27:7110ebee3484 896 __IO uint32_t RxFilterWoLClear;
emilmont 27:7110ebee3484 897 uint32_t RESERVED5;
emilmont 27:7110ebee3484 898 __IO uint32_t HashFilterL;
emilmont 27:7110ebee3484 899 __IO uint32_t HashFilterH;
emilmont 27:7110ebee3484 900 uint32_t RESERVED6[882];
emilmont 27:7110ebee3484 901 __I uint32_t IntStatus; /* Module Control Registers */
emilmont 27:7110ebee3484 902 __IO uint32_t IntEnable;
emilmont 27:7110ebee3484 903 __O uint32_t IntClear;
emilmont 27:7110ebee3484 904 __O uint32_t IntSet;
emilmont 27:7110ebee3484 905 uint32_t RESERVED7;
emilmont 27:7110ebee3484 906 __IO uint32_t PowerDown;
emilmont 27:7110ebee3484 907 uint32_t RESERVED8;
emilmont 27:7110ebee3484 908 __IO uint32_t Module_ID;
emilmont 27:7110ebee3484 909 } LPC_EMAC_TypeDef;
emilmont 27:7110ebee3484 910
emilmont 27:7110ebee3484 911 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 912 #pragma no_anon_unions
emilmont 27:7110ebee3484 913 #endif
emilmont 27:7110ebee3484 914
emilmont 27:7110ebee3484 915
emilmont 27:7110ebee3484 916 /******************************************************************************/
emilmont 27:7110ebee3484 917 /* Peripheral memory map */
emilmont 27:7110ebee3484 918 /******************************************************************************/
emilmont 27:7110ebee3484 919 /* Base addresses */
emilmont 27:7110ebee3484 920 #define LPC_FLASH_BASE (0x00000000UL)
emilmont 27:7110ebee3484 921 #define LPC_RAM_BASE (0x10000000UL)
emilmont 27:7110ebee3484 922 #define LPC_GPIO_BASE (0x2009C000UL)
emilmont 27:7110ebee3484 923 #define LPC_APB0_BASE (0x40000000UL)
emilmont 27:7110ebee3484 924 #define LPC_APB1_BASE (0x40080000UL)
emilmont 27:7110ebee3484 925 #define LPC_AHB_BASE (0x50000000UL)
emilmont 27:7110ebee3484 926 #define LPC_CM3_BASE (0xE0000000UL)
emilmont 27:7110ebee3484 927
emilmont 27:7110ebee3484 928 /* APB0 peripherals */
emilmont 27:7110ebee3484 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
emilmont 27:7110ebee3484 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
emilmont 27:7110ebee3484 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
emilmont 27:7110ebee3484 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
emilmont 27:7110ebee3484 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
emilmont 27:7110ebee3484 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
emilmont 27:7110ebee3484 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
emilmont 27:7110ebee3484 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
emilmont 27:7110ebee3484 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
emilmont 27:7110ebee3484 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
emilmont 27:7110ebee3484 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
emilmont 27:7110ebee3484 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
emilmont 27:7110ebee3484 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
emilmont 27:7110ebee3484 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
emilmont 27:7110ebee3484 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
emilmont 27:7110ebee3484 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
emilmont 27:7110ebee3484 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
emilmont 27:7110ebee3484 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
emilmont 27:7110ebee3484 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
emilmont 27:7110ebee3484 948
emilmont 27:7110ebee3484 949 /* APB1 peripherals */
emilmont 27:7110ebee3484 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
emilmont 27:7110ebee3484 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
emilmont 27:7110ebee3484 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
emilmont 27:7110ebee3484 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
emilmont 27:7110ebee3484 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
emilmont 27:7110ebee3484 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
emilmont 27:7110ebee3484 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
emilmont 27:7110ebee3484 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
emilmont 27:7110ebee3484 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
emilmont 27:7110ebee3484 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
emilmont 27:7110ebee3484 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
emilmont 27:7110ebee3484 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
emilmont 27:7110ebee3484 962
emilmont 27:7110ebee3484 963 /* AHB peripherals */
emilmont 27:7110ebee3484 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
emilmont 27:7110ebee3484 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
emilmont 27:7110ebee3484 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
emilmont 27:7110ebee3484 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
emilmont 27:7110ebee3484 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
emilmont 27:7110ebee3484 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
emilmont 27:7110ebee3484 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
emilmont 27:7110ebee3484 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
emilmont 27:7110ebee3484 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
emilmont 27:7110ebee3484 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
emilmont 27:7110ebee3484 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
emilmont 27:7110ebee3484 975
emilmont 27:7110ebee3484 976 /* GPIOs */
emilmont 27:7110ebee3484 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
emilmont 27:7110ebee3484 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
emilmont 27:7110ebee3484 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
emilmont 27:7110ebee3484 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
emilmont 27:7110ebee3484 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
emilmont 27:7110ebee3484 982
emilmont 27:7110ebee3484 983
emilmont 27:7110ebee3484 984 /******************************************************************************/
emilmont 27:7110ebee3484 985 /* Peripheral declaration */
emilmont 27:7110ebee3484 986 /******************************************************************************/
emilmont 27:7110ebee3484 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
emilmont 27:7110ebee3484 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
emilmont 27:7110ebee3484 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
emilmont 27:7110ebee3484 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
emilmont 27:7110ebee3484 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
emilmont 27:7110ebee3484 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
emilmont 27:7110ebee3484 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
emilmont 27:7110ebee3484 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
emilmont 27:7110ebee3484 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
emilmont 27:7110ebee3484 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
emilmont 27:7110ebee3484 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
emilmont 27:7110ebee3484 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
emilmont 27:7110ebee3484 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
emilmont 27:7110ebee3484 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
emilmont 27:7110ebee3484 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
emilmont 27:7110ebee3484 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
emilmont 27:7110ebee3484 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
emilmont 27:7110ebee3484 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
emilmont 27:7110ebee3484 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
emilmont 27:7110ebee3484 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
emilmont 27:7110ebee3484 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
emilmont 27:7110ebee3484 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
emilmont 27:7110ebee3484 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
emilmont 27:7110ebee3484 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
emilmont 27:7110ebee3484 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
emilmont 27:7110ebee3484 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
emilmont 27:7110ebee3484 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
emilmont 27:7110ebee3484 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
emilmont 27:7110ebee3484 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
emilmont 27:7110ebee3484 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
emilmont 27:7110ebee3484 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
emilmont 27:7110ebee3484 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
emilmont 27:7110ebee3484 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
emilmont 27:7110ebee3484 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
emilmont 27:7110ebee3484 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
emilmont 27:7110ebee3484 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
emilmont 27:7110ebee3484 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
emilmont 27:7110ebee3484 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
emilmont 27:7110ebee3484 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
emilmont 27:7110ebee3484 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
emilmont 27:7110ebee3484 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
emilmont 27:7110ebee3484 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
emilmont 27:7110ebee3484 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
emilmont 27:7110ebee3484 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
emilmont 27:7110ebee3484 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
emilmont 27:7110ebee3484 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
emilmont 27:7110ebee3484 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
emilmont 27:7110ebee3484 1034
emilmont 27:7110ebee3484 1035 #endif // __LPC17xx_H__