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TARGET_VK_RZ_A1H/TOOLCHAIN_GCC_ARM/mtu2_iobitmask.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 161:aa5281ff4a02 | 1 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 2 | * DISCLAIMER |
| AnnaBridge | 161:aa5281ff4a02 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| AnnaBridge | 161:aa5281ff4a02 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| AnnaBridge | 161:aa5281ff4a02 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| AnnaBridge | 161:aa5281ff4a02 | 6 | * all applicable laws, including copyright laws. |
| AnnaBridge | 161:aa5281ff4a02 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| AnnaBridge | 161:aa5281ff4a02 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| AnnaBridge | 161:aa5281ff4a02 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| AnnaBridge | 161:aa5281ff4a02 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| AnnaBridge | 161:aa5281ff4a02 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| AnnaBridge | 161:aa5281ff4a02 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| AnnaBridge | 161:aa5281ff4a02 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| AnnaBridge | 161:aa5281ff4a02 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| AnnaBridge | 161:aa5281ff4a02 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| AnnaBridge | 161:aa5281ff4a02 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| AnnaBridge | 161:aa5281ff4a02 | 17 | * and to discontinue the availability of this software. By using this software, |
| AnnaBridge | 161:aa5281ff4a02 | 18 | * you agree to the additional terms and conditions found by accessing the |
| AnnaBridge | 161:aa5281ff4a02 | 19 | * following link: |
| AnnaBridge | 161:aa5281ff4a02 | 20 | * http://www.renesas.com/disclaimer |
| AnnaBridge | 161:aa5281ff4a02 | 21 | * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. |
| AnnaBridge | 161:aa5281ff4a02 | 22 | *******************************************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 23 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 24 | * File Name : mtu2_iobitmask.h |
| AnnaBridge | 161:aa5281ff4a02 | 25 | * $Rev: 1138 $ |
| AnnaBridge | 161:aa5281ff4a02 | 26 | * $Date:: 2014-08-08 11:03:56 +0900#$ |
| AnnaBridge | 161:aa5281ff4a02 | 27 | * Description : MTU2 register define header |
| AnnaBridge | 161:aa5281ff4a02 | 28 | *******************************************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 29 | #ifndef MTU2_IOBITMASK_H |
| AnnaBridge | 161:aa5281ff4a02 | 30 | #define MTU2_IOBITMASK_H |
| AnnaBridge | 161:aa5281ff4a02 | 31 | |
| AnnaBridge | 161:aa5281ff4a02 | 32 | |
| AnnaBridge | 161:aa5281ff4a02 | 33 | /* ==== Mask values for IO registers ==== */ |
| AnnaBridge | 161:aa5281ff4a02 | 34 | #define MTU2_TCR_n_TPSC (0x07u) |
| AnnaBridge | 161:aa5281ff4a02 | 35 | #define MTU2_TCR_n_CKEG (0x18u) |
| AnnaBridge | 161:aa5281ff4a02 | 36 | #define MTU2_TCR_n_CCLR (0xE0u) |
| AnnaBridge | 161:aa5281ff4a02 | 37 | |
| AnnaBridge | 161:aa5281ff4a02 | 38 | #define MTU2_TMDR_n_MD (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 39 | |
| AnnaBridge | 161:aa5281ff4a02 | 40 | #define MTU2_TIOR_2_IOA (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 41 | #define MTU2_TIOR_2_IOB (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 42 | |
| AnnaBridge | 161:aa5281ff4a02 | 43 | #define MTU2_TIER_n_TGIEA (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 44 | #define MTU2_TIER_n_TGIEB (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 45 | #define MTU2_TIER_n_TCIEV (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 46 | #define MTU2_TIER_2_TCIEU (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 47 | #define MTU2_TIER_n_TTGE (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 48 | |
| AnnaBridge | 161:aa5281ff4a02 | 49 | #define MTU2_TSR_n_TGFA (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 50 | #define MTU2_TSR_n_TGFB (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 51 | #define MTU2_TSR_n_TCFV (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 52 | #define MTU2_TSR_2_TCFU (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 53 | #define MTU2_TSR_2_TCFD (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 54 | |
| AnnaBridge | 161:aa5281ff4a02 | 55 | #define MTU2_TCNT_n_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 56 | |
| AnnaBridge | 161:aa5281ff4a02 | 57 | #define MTU2_TGRA_n_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 58 | |
| AnnaBridge | 161:aa5281ff4a02 | 59 | #define MTU2_TGRB_n_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 60 | |
| AnnaBridge | 161:aa5281ff4a02 | 61 | #define MTU2_TMDR_3_BFA (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 62 | #define MTU2_TMDR_3_BFB (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 63 | |
| AnnaBridge | 161:aa5281ff4a02 | 64 | #define MTU2_TMDR_4_BFA (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 65 | #define MTU2_TMDR_4_BFB (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 66 | |
| AnnaBridge | 161:aa5281ff4a02 | 67 | #define MTU2_TIORH_3_IOA (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 68 | #define MTU2_TIORH_3_IOB (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 69 | |
| AnnaBridge | 161:aa5281ff4a02 | 70 | #define MTU2_TIORL_3_IOC (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 71 | #define MTU2_TIORL_3_IOD (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 72 | |
| AnnaBridge | 161:aa5281ff4a02 | 73 | #define MTU2_TIORH_4_IOA (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 74 | #define MTU2_TIORH_4_IOB (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 75 | |
| AnnaBridge | 161:aa5281ff4a02 | 76 | #define MTU2_TIORL_4_IOC (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 77 | #define MTU2_TIORL_4_IOD (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 78 | |
| AnnaBridge | 161:aa5281ff4a02 | 79 | #define MTU2_TIER_3_TGIEC (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 80 | #define MTU2_TIER_3_TGIED (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 81 | |
| AnnaBridge | 161:aa5281ff4a02 | 82 | #define MTU2_TIER_4_TGIEC (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 83 | #define MTU2_TIER_4_TGIED (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 84 | #define MTU2_TIER_4_TTGE2 (0x40u) |
| AnnaBridge | 161:aa5281ff4a02 | 85 | |
| AnnaBridge | 161:aa5281ff4a02 | 86 | #define MTU2_TOER_OE3B (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 87 | #define MTU2_TOER_OE4A (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 88 | #define MTU2_TOER_OE4B (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 89 | #define MTU2_TOER_OE3D (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 90 | #define MTU2_TOER_OE4C (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 91 | #define MTU2_TOER_OE4D (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 92 | |
| AnnaBridge | 161:aa5281ff4a02 | 93 | #define MTU2_TGCR_UF (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 94 | #define MTU2_TGCR_VF (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 95 | #define MTU2_TGCR_WF (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 96 | #define MTU2_TGCR_FB (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 97 | #define MTU2_TGCR_P (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 98 | #define MTU2_TGCR_N (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 99 | #define MTU2_TGCR_BDC (0x40u) |
| AnnaBridge | 161:aa5281ff4a02 | 100 | |
| AnnaBridge | 161:aa5281ff4a02 | 101 | #define MTU2_TOCR1_OLSP (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 102 | #define MTU2_TOCR1_OLSN (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 103 | #define MTU2_TOCR1_TOCS (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 104 | #define MTU2_TOCR1_TOCL (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 105 | #define MTU2_TOCR1_PSYE (0x40u) |
| AnnaBridge | 161:aa5281ff4a02 | 106 | |
| AnnaBridge | 161:aa5281ff4a02 | 107 | #define MTU2_TOCR2_OLS1P (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 108 | #define MTU2_TOCR2_OLS1N (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 109 | #define MTU2_TOCR2_OLS2P (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 110 | #define MTU2_TOCR2_OLS2N (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 111 | #define MTU2_TOCR2_OLS3P (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 112 | #define MTU2_TOCR2_OLS3N (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 113 | #define MTU2_TOCR2_BF (0xC0u) |
| AnnaBridge | 161:aa5281ff4a02 | 114 | |
| AnnaBridge | 161:aa5281ff4a02 | 115 | #define MTU2_TCDR_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 116 | |
| AnnaBridge | 161:aa5281ff4a02 | 117 | #define MTU2_TDDR_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 118 | |
| AnnaBridge | 161:aa5281ff4a02 | 119 | #define MTU2_TCNTS_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 120 | |
| AnnaBridge | 161:aa5281ff4a02 | 121 | #define MTU2_TCBR_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 122 | |
| AnnaBridge | 161:aa5281ff4a02 | 123 | #define MTU2_TGRC_3_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 124 | |
| AnnaBridge | 161:aa5281ff4a02 | 125 | #define MTU2_TGRD_3_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 126 | |
| AnnaBridge | 161:aa5281ff4a02 | 127 | #define MTU2_TGRC_4_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 128 | |
| AnnaBridge | 161:aa5281ff4a02 | 129 | #define MTU2_TGRD_4_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 130 | |
| AnnaBridge | 161:aa5281ff4a02 | 131 | #define MTU2_TSR_3_TGFC (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 132 | #define MTU2_TSR_3_TGFD (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 133 | #define MTU2_TSR_3_TCFD (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 134 | |
| AnnaBridge | 161:aa5281ff4a02 | 135 | #define MTU2_TSR_4_TGFC (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 136 | #define MTU2_TSR_4_TGFD (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 137 | #define MTU2_TSR_4_TCFD (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 138 | |
| AnnaBridge | 161:aa5281ff4a02 | 139 | #define MTU2_TITCR_4VCOR (0x07u) |
| AnnaBridge | 161:aa5281ff4a02 | 140 | #define MTU2_TITCR_T4VEN (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 141 | #define MTU2_TITCR_3ACOR (0x70u) |
| AnnaBridge | 161:aa5281ff4a02 | 142 | #define MTU2_TITCR_T3AEN (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 143 | |
| AnnaBridge | 161:aa5281ff4a02 | 144 | #define MTU2_TITCNT_4VCNT (0x07u) |
| AnnaBridge | 161:aa5281ff4a02 | 145 | #define MTU2_TITCNT_3ACNT (0x70u) |
| AnnaBridge | 161:aa5281ff4a02 | 146 | |
| AnnaBridge | 161:aa5281ff4a02 | 147 | #define MTU2_TBTER_BTE (0x03u) |
| AnnaBridge | 161:aa5281ff4a02 | 148 | |
| AnnaBridge | 161:aa5281ff4a02 | 149 | #define MTU2_TDER_TDER (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 150 | |
| AnnaBridge | 161:aa5281ff4a02 | 151 | #define MTU2_TOLBR_OLS1P (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 152 | #define MTU2_TOLBR_OLS1N (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 153 | #define MTU2_TOLBR_OLS2P (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 154 | #define MTU2_TOLBR_OLS2N (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 155 | #define MTU2_TOLBR_OLS3P (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 156 | #define MTU2_TOLBR_OLS3N (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 157 | |
| AnnaBridge | 161:aa5281ff4a02 | 158 | #define MTU2_TBTM_3_TTSA (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 159 | #define MTU2_TBTM_3_TTSB (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 160 | |
| AnnaBridge | 161:aa5281ff4a02 | 161 | #define MTU2_TBTM_4_TTSA (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 162 | #define MTU2_TBTM_4_TTSB (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 163 | |
| AnnaBridge | 161:aa5281ff4a02 | 164 | #define MTU2_TADCR_ITB4VE (0x0001u) |
| AnnaBridge | 161:aa5281ff4a02 | 165 | #define MTU2_TADCR_ITB3AE (0x0002u) |
| AnnaBridge | 161:aa5281ff4a02 | 166 | #define MTU2_TADCR_ITA4VE (0x0004u) |
| AnnaBridge | 161:aa5281ff4a02 | 167 | #define MTU2_TADCR_ITA3AE (0x0008u) |
| AnnaBridge | 161:aa5281ff4a02 | 168 | #define MTU2_TADCR_DT4BE (0x0010u) |
| AnnaBridge | 161:aa5281ff4a02 | 169 | #define MTU2_TADCR_UT4BE (0x0020u) |
| AnnaBridge | 161:aa5281ff4a02 | 170 | #define MTU2_TADCR_DT4AE (0x0040u) |
| AnnaBridge | 161:aa5281ff4a02 | 171 | #define MTU2_TADCR_UT4AE (0x0080u) |
| AnnaBridge | 161:aa5281ff4a02 | 172 | #define MTU2_TADCR_BF (0xC000u) |
| AnnaBridge | 161:aa5281ff4a02 | 173 | |
| AnnaBridge | 161:aa5281ff4a02 | 174 | #define MTU2_TADCORA_4_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 175 | |
| AnnaBridge | 161:aa5281ff4a02 | 176 | #define MTU2_TADCORB_4_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 177 | |
| AnnaBridge | 161:aa5281ff4a02 | 178 | #define MTU2_TADCOBRA_4_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 179 | |
| AnnaBridge | 161:aa5281ff4a02 | 180 | #define MTU2_TADCOBRB_4_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 181 | |
| AnnaBridge | 161:aa5281ff4a02 | 182 | #define MTU2_TWCR_WRE (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 183 | #define MTU2_TWCR_CCE (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 184 | |
| AnnaBridge | 161:aa5281ff4a02 | 185 | #define MTU2_TSTR_CST0 (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 186 | #define MTU2_TSTR_CST1 (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 187 | #define MTU2_TSTR_CST2 (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 188 | #define MTU2_TSTR_CST3 (0x40u) |
| AnnaBridge | 161:aa5281ff4a02 | 189 | #define MTU2_TSTR_CST4 (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 190 | |
| AnnaBridge | 161:aa5281ff4a02 | 191 | #define MTU2_TSYR_SYNC0 (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 192 | #define MTU2_TSYR_SYNC1 (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 193 | #define MTU2_TSYR_SYNC2 (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 194 | #define MTU2_TSYR_SYNC3 (0x40u) |
| AnnaBridge | 161:aa5281ff4a02 | 195 | #define MTU2_TSYR_SYNC4 (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 196 | |
| AnnaBridge | 161:aa5281ff4a02 | 197 | #define MTU2_TRWER_RWE (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 198 | |
| AnnaBridge | 161:aa5281ff4a02 | 199 | #define MTU2_TMDR_0_BFA (0x10u) |
| AnnaBridge | 161:aa5281ff4a02 | 200 | #define MTU2_TMDR_0_BFB (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 201 | #define MTU2_TMDR_0_BFE (0x40u) |
| AnnaBridge | 161:aa5281ff4a02 | 202 | |
| AnnaBridge | 161:aa5281ff4a02 | 203 | #define MTU2_TIORH_0_IOA (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 204 | #define MTU2_TIORH_0_IOB (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 205 | |
| AnnaBridge | 161:aa5281ff4a02 | 206 | #define MTU2_TIORL_0_IOC (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 207 | #define MTU2_TIORL_0_IOD (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 208 | |
| AnnaBridge | 161:aa5281ff4a02 | 209 | #define MTU2_TIER_0_TGIEC (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 210 | #define MTU2_TIER_0_TGIED (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 211 | |
| AnnaBridge | 161:aa5281ff4a02 | 212 | #define MTU2_TSR_0_TGFC (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 213 | #define MTU2_TSR_0_TGFD (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 214 | |
| AnnaBridge | 161:aa5281ff4a02 | 215 | #define MTU2_TGRC_0_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 216 | |
| AnnaBridge | 161:aa5281ff4a02 | 217 | #define MTU2_TGRD_0_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 218 | |
| AnnaBridge | 161:aa5281ff4a02 | 219 | #define MTU2_TGRE_0_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 220 | |
| AnnaBridge | 161:aa5281ff4a02 | 221 | #define MTU2_TGRF_0_D (0xFFFFu) |
| AnnaBridge | 161:aa5281ff4a02 | 222 | |
| AnnaBridge | 161:aa5281ff4a02 | 223 | #define MTU2_TIER2_0_TGIEE (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 224 | #define MTU2_TIER2_0_TGIEF (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 225 | |
| AnnaBridge | 161:aa5281ff4a02 | 226 | #define MTU2_TSR2_0_TGFE (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 227 | #define MTU2_TSR2_0_TGFF (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 228 | |
| AnnaBridge | 161:aa5281ff4a02 | 229 | #define MTU2_TBTM_0_TTSA (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 230 | #define MTU2_TBTM_0_TTSB (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 231 | #define MTU2_TBTM_0_TTSE (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 232 | |
| AnnaBridge | 161:aa5281ff4a02 | 233 | #define MTU2_TIOR_1_IOA (0x0Fu) |
| AnnaBridge | 161:aa5281ff4a02 | 234 | #define MTU2_TIOR_1_IOB (0xF0u) |
| AnnaBridge | 161:aa5281ff4a02 | 235 | |
| AnnaBridge | 161:aa5281ff4a02 | 236 | #define MTU2_TIER_1_TCIEU (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 237 | |
| AnnaBridge | 161:aa5281ff4a02 | 238 | #define MTU2_TSR_1_TCFU (0x20u) |
| AnnaBridge | 161:aa5281ff4a02 | 239 | #define MTU2_TSR_1_TCFD (0x80u) |
| AnnaBridge | 161:aa5281ff4a02 | 240 | |
| AnnaBridge | 161:aa5281ff4a02 | 241 | #define MTU2_TICCR_I1AE (0x01u) |
| AnnaBridge | 161:aa5281ff4a02 | 242 | #define MTU2_TICCR_I1BE (0x02u) |
| AnnaBridge | 161:aa5281ff4a02 | 243 | #define MTU2_TICCR_I2AE (0x04u) |
| AnnaBridge | 161:aa5281ff4a02 | 244 | #define MTU2_TICCR_I2BE (0x08u) |
| AnnaBridge | 161:aa5281ff4a02 | 245 | |
| AnnaBridge | 161:aa5281ff4a02 | 246 | |
| AnnaBridge | 161:aa5281ff4a02 | 247 | /* ==== Shift values for IO registers ==== */ |
| AnnaBridge | 161:aa5281ff4a02 | 248 | #define MTU2_TCR_n_TPSC_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 249 | #define MTU2_TCR_n_CKEG_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 250 | #define MTU2_TCR_n_CCLR_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 251 | |
| AnnaBridge | 161:aa5281ff4a02 | 252 | #define MTU2_TMDR_n_MD_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 253 | |
| AnnaBridge | 161:aa5281ff4a02 | 254 | #define MTU2_TIOR_2_IOA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 255 | #define MTU2_TIOR_2_IOB_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 256 | |
| AnnaBridge | 161:aa5281ff4a02 | 257 | #define MTU2_TIER_n_TGIEA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 258 | #define MTU2_TIER_n_TGIEB_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 259 | #define MTU2_TIER_n_TCIEV_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 260 | #define MTU2_TIER_2_TCIEU_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 261 | #define MTU2_TIER_n_TTGE_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 262 | |
| AnnaBridge | 161:aa5281ff4a02 | 263 | #define MTU2_TSR_n_TGFA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 264 | #define MTU2_TSR_n_TGFB_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 265 | #define MTU2_TSR_n_TCFV_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 266 | #define MTU2_TSR_2_TCFU_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 267 | #define MTU2_TSR_2_TCFD_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 268 | |
| AnnaBridge | 161:aa5281ff4a02 | 269 | #define MTU2_TCNT_n_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 270 | |
| AnnaBridge | 161:aa5281ff4a02 | 271 | #define MTU2_TGRA_n_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 272 | |
| AnnaBridge | 161:aa5281ff4a02 | 273 | #define MTU2_TGRB_n_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 274 | |
| AnnaBridge | 161:aa5281ff4a02 | 275 | #define MTU2_TMDR_3_BFA_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 276 | #define MTU2_TMDR_3_BFB_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 277 | |
| AnnaBridge | 161:aa5281ff4a02 | 278 | #define MTU2_TMDR_4_BFA_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 279 | #define MTU2_TMDR_4_BFB_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 280 | |
| AnnaBridge | 161:aa5281ff4a02 | 281 | #define MTU2_TIORH_3_IOA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 282 | #define MTU2_TIORH_3_IOB_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 283 | |
| AnnaBridge | 161:aa5281ff4a02 | 284 | #define MTU2_TIORL_3_IOC_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 285 | #define MTU2_TIORL_3_IOD_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 286 | |
| AnnaBridge | 161:aa5281ff4a02 | 287 | #define MTU2_TIORH_4_IOA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 288 | #define MTU2_TIORH_4_IOB_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 289 | |
| AnnaBridge | 161:aa5281ff4a02 | 290 | #define MTU2_TIORL_4_IOC_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 291 | #define MTU2_TIORL_4_IOD_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 292 | |
| AnnaBridge | 161:aa5281ff4a02 | 293 | #define MTU2_TIER_3_TGIEC_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 294 | #define MTU2_TIER_3_TGIED_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 295 | |
| AnnaBridge | 161:aa5281ff4a02 | 296 | #define MTU2_TIER_4_TGIEC_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 297 | #define MTU2_TIER_4_TGIED_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 298 | #define MTU2_TIER_4_TTGE2_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 299 | |
| AnnaBridge | 161:aa5281ff4a02 | 300 | #define MTU2_TOER_OE3B_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 301 | #define MTU2_TOER_OE4A_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 302 | #define MTU2_TOER_OE4B_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 303 | #define MTU2_TOER_OE3D_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 304 | #define MTU2_TOER_OE4C_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 305 | #define MTU2_TOER_OE4D_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 306 | |
| AnnaBridge | 161:aa5281ff4a02 | 307 | #define MTU2_TGCR_UF_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 308 | #define MTU2_TGCR_VF_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 309 | #define MTU2_TGCR_WF_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 310 | #define MTU2_TGCR_FB_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 311 | #define MTU2_TGCR_P_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 312 | #define MTU2_TGCR_N_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 313 | #define MTU2_TGCR_BDC_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 314 | |
| AnnaBridge | 161:aa5281ff4a02 | 315 | #define MTU2_TOCR1_OLSP_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 316 | #define MTU2_TOCR1_OLSN_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 317 | #define MTU2_TOCR1_TOCS_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 318 | #define MTU2_TOCR1_TOCL_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 319 | #define MTU2_TOCR1_PSYE_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 320 | |
| AnnaBridge | 161:aa5281ff4a02 | 321 | #define MTU2_TOCR2_OLS1P_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 322 | #define MTU2_TOCR2_OLS1N_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 323 | #define MTU2_TOCR2_OLS2P_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 324 | #define MTU2_TOCR2_OLS2N_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 325 | #define MTU2_TOCR2_OLS3P_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 326 | #define MTU2_TOCR2_OLS3N_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 327 | #define MTU2_TOCR2_BF_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 328 | |
| AnnaBridge | 161:aa5281ff4a02 | 329 | #define MTU2_TCDR_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 330 | |
| AnnaBridge | 161:aa5281ff4a02 | 331 | #define MTU2_TDDR_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 332 | |
| AnnaBridge | 161:aa5281ff4a02 | 333 | #define MTU2_TCNTS_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 334 | |
| AnnaBridge | 161:aa5281ff4a02 | 335 | #define MTU2_TCBR_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 336 | |
| AnnaBridge | 161:aa5281ff4a02 | 337 | #define MTU2_TGRC_3_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 338 | |
| AnnaBridge | 161:aa5281ff4a02 | 339 | #define MTU2_TGRD_3_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 340 | |
| AnnaBridge | 161:aa5281ff4a02 | 341 | #define MTU2_TGRC_4_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 342 | |
| AnnaBridge | 161:aa5281ff4a02 | 343 | #define MTU2_TGRD_4_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 344 | |
| AnnaBridge | 161:aa5281ff4a02 | 345 | #define MTU2_TSR_3_TGFC_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 346 | #define MTU2_TSR_3_TGFD_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 347 | #define MTU2_TSR_3_TCFD_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 348 | |
| AnnaBridge | 161:aa5281ff4a02 | 349 | #define MTU2_TSR_4_TGFC_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 350 | #define MTU2_TSR_4_TGFD_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 351 | #define MTU2_TSR_4_TCFD_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 352 | |
| AnnaBridge | 161:aa5281ff4a02 | 353 | #define MTU2_TITCR_4VCOR_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 354 | #define MTU2_TITCR_T4VEN_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 355 | #define MTU2_TITCR_3ACOR_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 356 | #define MTU2_TITCR_T3AEN_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 357 | |
| AnnaBridge | 161:aa5281ff4a02 | 358 | #define MTU2_TITCNT_4VCNT_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 359 | #define MTU2_TITCNT_3ACNT_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 360 | |
| AnnaBridge | 161:aa5281ff4a02 | 361 | #define MTU2_TBTER_BTE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 362 | |
| AnnaBridge | 161:aa5281ff4a02 | 363 | #define MTU2_TDER_TDER_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 364 | |
| AnnaBridge | 161:aa5281ff4a02 | 365 | #define MTU2_TOLBR_OLS1P_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 366 | #define MTU2_TOLBR_OLS1N_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 367 | #define MTU2_TOLBR_OLS2P_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 368 | #define MTU2_TOLBR_OLS2N_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 369 | #define MTU2_TOLBR_OLS3P_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 370 | #define MTU2_TOLBR_OLS3N_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 371 | |
| AnnaBridge | 161:aa5281ff4a02 | 372 | #define MTU2_TBTM_3_TTSA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 373 | #define MTU2_TBTM_3_TTSB_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 374 | |
| AnnaBridge | 161:aa5281ff4a02 | 375 | #define MTU2_TBTM_4_TTSA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 376 | #define MTU2_TBTM_4_TTSB_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 377 | |
| AnnaBridge | 161:aa5281ff4a02 | 378 | #define MTU2_TADCR_ITB4VE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 379 | #define MTU2_TADCR_ITB3AE_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 380 | #define MTU2_TADCR_ITA4VE_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 381 | #define MTU2_TADCR_ITA3AE_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 382 | #define MTU2_TADCR_DT4BE_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 383 | #define MTU2_TADCR_UT4BE_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 384 | #define MTU2_TADCR_DT4AE_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 385 | #define MTU2_TADCR_UT4AE_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 386 | #define MTU2_TADCR_BF_SHIFT (14u) |
| AnnaBridge | 161:aa5281ff4a02 | 387 | |
| AnnaBridge | 161:aa5281ff4a02 | 388 | #define MTU2_TADCORA_4_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 389 | |
| AnnaBridge | 161:aa5281ff4a02 | 390 | #define MTU2_TADCORB_4_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 391 | |
| AnnaBridge | 161:aa5281ff4a02 | 392 | #define MTU2_TADCOBRA_4_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 393 | |
| AnnaBridge | 161:aa5281ff4a02 | 394 | #define MTU2_TADCOBRB_4_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 395 | |
| AnnaBridge | 161:aa5281ff4a02 | 396 | #define MTU2_TWCR_WRE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 397 | #define MTU2_TWCR_CCE_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 398 | |
| AnnaBridge | 161:aa5281ff4a02 | 399 | #define MTU2_TSTR_CST0_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 400 | #define MTU2_TSTR_CST1_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 401 | #define MTU2_TSTR_CST2_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 402 | #define MTU2_TSTR_CST3_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 403 | #define MTU2_TSTR_CST4_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 404 | |
| AnnaBridge | 161:aa5281ff4a02 | 405 | #define MTU2_TSYR_SYNC0_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 406 | #define MTU2_TSYR_SYNC1_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 407 | #define MTU2_TSYR_SYNC2_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 408 | #define MTU2_TSYR_SYNC3_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 409 | #define MTU2_TSYR_SYNC4_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 410 | |
| AnnaBridge | 161:aa5281ff4a02 | 411 | #define MTU2_TRWER_RWE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 412 | |
| AnnaBridge | 161:aa5281ff4a02 | 413 | #define MTU2_TMDR_0_BFA_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 414 | #define MTU2_TMDR_0_BFB_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 415 | #define MTU2_TMDR_0_BFE_SHIFT (6u) |
| AnnaBridge | 161:aa5281ff4a02 | 416 | |
| AnnaBridge | 161:aa5281ff4a02 | 417 | #define MTU2_TIORH_0_IOA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 418 | #define MTU2_TIORH_0_IOB_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 419 | |
| AnnaBridge | 161:aa5281ff4a02 | 420 | #define MTU2_TIORL_0_IOC_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 421 | #define MTU2_TIORL_0_IOD_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 422 | |
| AnnaBridge | 161:aa5281ff4a02 | 423 | #define MTU2_TIER_0_TGIEC_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 424 | #define MTU2_TIER_0_TGIED_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 425 | |
| AnnaBridge | 161:aa5281ff4a02 | 426 | #define MTU2_TSR_0_TGFC_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 427 | #define MTU2_TSR_0_TGFD_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 428 | |
| AnnaBridge | 161:aa5281ff4a02 | 429 | #define MTU2_TGRC_0_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 430 | |
| AnnaBridge | 161:aa5281ff4a02 | 431 | #define MTU2_TGRD_0_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 432 | |
| AnnaBridge | 161:aa5281ff4a02 | 433 | #define MTU2_TGRE_0_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 434 | |
| AnnaBridge | 161:aa5281ff4a02 | 435 | #define MTU2_TGRF_0_D_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 436 | |
| AnnaBridge | 161:aa5281ff4a02 | 437 | #define MTU2_TIER2_0_TGIEE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 438 | #define MTU2_TIER2_0_TGIEF_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 439 | |
| AnnaBridge | 161:aa5281ff4a02 | 440 | #define MTU2_TSR2_0_TGFE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 441 | #define MTU2_TSR2_0_TGFF_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 442 | |
| AnnaBridge | 161:aa5281ff4a02 | 443 | #define MTU2_TBTM_0_TTSA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 444 | #define MTU2_TBTM_0_TTSB_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 445 | #define MTU2_TBTM_0_TTSE_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 446 | |
| AnnaBridge | 161:aa5281ff4a02 | 447 | #define MTU2_TIOR_1_IOA_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 448 | #define MTU2_TIOR_1_IOB_SHIFT (4u) |
| AnnaBridge | 161:aa5281ff4a02 | 449 | |
| AnnaBridge | 161:aa5281ff4a02 | 450 | #define MTU2_TIER_1_TCIEU_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 451 | |
| AnnaBridge | 161:aa5281ff4a02 | 452 | #define MTU2_TSR_1_TCFU_SHIFT (5u) |
| AnnaBridge | 161:aa5281ff4a02 | 453 | #define MTU2_TSR_1_TCFD_SHIFT (7u) |
| AnnaBridge | 161:aa5281ff4a02 | 454 | |
| AnnaBridge | 161:aa5281ff4a02 | 455 | #define MTU2_TICCR_I1AE_SHIFT (0u) |
| AnnaBridge | 161:aa5281ff4a02 | 456 | #define MTU2_TICCR_I1BE_SHIFT (1u) |
| AnnaBridge | 161:aa5281ff4a02 | 457 | #define MTU2_TICCR_I2AE_SHIFT (2u) |
| AnnaBridge | 161:aa5281ff4a02 | 458 | #define MTU2_TICCR_I2BE_SHIFT (3u) |
| AnnaBridge | 161:aa5281ff4a02 | 459 | |
| AnnaBridge | 161:aa5281ff4a02 | 460 | |
| AnnaBridge | 161:aa5281ff4a02 | 461 | #endif /* MTU2_IOBITMASK_H */ |
| AnnaBridge | 161:aa5281ff4a02 | 462 | /* End of File */ |
