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TARGET_TB_SENSE_12/TOOLCHAIN_ARM_STD/efr32mg12p_dmareq.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file efr32mg12p_dmareq.h
Anna Bridge 142:4eea097334d6 3 * @brief EFR32MG12P_DMAREQ register and bit field definitions
Anna Bridge 142:4eea097334d6 4 * @version 5.1.2
Anna Bridge 142:4eea097334d6 5 ******************************************************************************
Anna Bridge 142:4eea097334d6 6 * @section License
Anna Bridge 142:4eea097334d6 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 8 ******************************************************************************
Anna Bridge 142:4eea097334d6 9 *
Anna Bridge 142:4eea097334d6 10 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 11 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 12 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 13 *
Anna Bridge 142:4eea097334d6 14 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 15 * claim that you wrote the original software.@n
Anna Bridge 142:4eea097334d6 16 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 17 * misrepresented as being the original software.@n
Anna Bridge 142:4eea097334d6 18 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 19 *
Anna Bridge 142:4eea097334d6 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
Anna Bridge 142:4eea097334d6 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
Anna Bridge 142:4eea097334d6 22 * providing the Software "AS IS", with no express or implied warranties of any
Anna Bridge 142:4eea097334d6 23 * kind, including, but not limited to, any implied warranties of
Anna Bridge 142:4eea097334d6 24 * merchantability or fitness for any particular purpose or warranties against
Anna Bridge 142:4eea097334d6 25 * infringement of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 26 *
Anna Bridge 142:4eea097334d6 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
Anna Bridge 142:4eea097334d6 28 * incidental, or special damages, or any other relief, or for any claim by
Anna Bridge 142:4eea097334d6 29 * any third party, arising from your use of this Software.
Anna Bridge 142:4eea097334d6 30 *
Anna Bridge 142:4eea097334d6 31 *****************************************************************************/
Anna Bridge 142:4eea097334d6 32 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 33 * @addtogroup Parts
Anna Bridge 142:4eea097334d6 34 * @{
Anna Bridge 142:4eea097334d6 35 ******************************************************************************/
Anna Bridge 142:4eea097334d6 36
Anna Bridge 142:4eea097334d6 37 /**************************************************************************//**
Anna Bridge 142:4eea097334d6 38 * @defgroup EFR32MG12P_DMAREQ_BitFields
Anna Bridge 142:4eea097334d6 39 * @{
Anna Bridge 142:4eea097334d6 40 *****************************************************************************/
Anna Bridge 142:4eea097334d6 41 #define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
Anna Bridge 142:4eea097334d6 42 #define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
Anna Bridge 142:4eea097334d6 43 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
Anna Bridge 142:4eea097334d6 44 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
Anna Bridge 142:4eea097334d6 45 #define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
Anna Bridge 142:4eea097334d6 46 #define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
Anna Bridge 142:4eea097334d6 47 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
Anna Bridge 142:4eea097334d6 48 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
Anna Bridge 142:4eea097334d6 49 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
Anna Bridge 142:4eea097334d6 50 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
Anna Bridge 142:4eea097334d6 51 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
Anna Bridge 142:4eea097334d6 52 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
Anna Bridge 142:4eea097334d6 53 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
Anna Bridge 142:4eea097334d6 54 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
Anna Bridge 142:4eea097334d6 55 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
Anna Bridge 142:4eea097334d6 56 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
Anna Bridge 142:4eea097334d6 57 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
Anna Bridge 142:4eea097334d6 58 #define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */
Anna Bridge 142:4eea097334d6 59 #define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */
Anna Bridge 142:4eea097334d6 60 #define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */
Anna Bridge 142:4eea097334d6 61 #define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */
Anna Bridge 142:4eea097334d6 62 #define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */
Anna Bridge 142:4eea097334d6 63 #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
Anna Bridge 142:4eea097334d6 64 #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
Anna Bridge 142:4eea097334d6 65 #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
Anna Bridge 142:4eea097334d6 66 #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
Anna Bridge 142:4eea097334d6 67 #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
Anna Bridge 142:4eea097334d6 68 #define DMAREQ_I2C1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
Anna Bridge 142:4eea097334d6 69 #define DMAREQ_I2C1_TXBL ((21 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
Anna Bridge 142:4eea097334d6 70 #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
Anna Bridge 142:4eea097334d6 71 #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
Anna Bridge 142:4eea097334d6 72 #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
Anna Bridge 142:4eea097334d6 73 #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
Anna Bridge 142:4eea097334d6 74 #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
Anna Bridge 142:4eea097334d6 75 #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
Anna Bridge 142:4eea097334d6 76 #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
Anna Bridge 142:4eea097334d6 77 #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
Anna Bridge 142:4eea097334d6 78 #define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
Anna Bridge 142:4eea097334d6 79 #define DMAREQ_WTIMER0_UFOF ((26 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
Anna Bridge 142:4eea097334d6 80 #define DMAREQ_WTIMER0_CC0 ((26 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
Anna Bridge 142:4eea097334d6 81 #define DMAREQ_WTIMER0_CC1 ((26 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
Anna Bridge 142:4eea097334d6 82 #define DMAREQ_WTIMER0_CC2 ((26 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
Anna Bridge 142:4eea097334d6 83 #define DMAREQ_WTIMER1_UFOF ((27 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */
Anna Bridge 142:4eea097334d6 84 #define DMAREQ_WTIMER1_CC0 ((27 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */
Anna Bridge 142:4eea097334d6 85 #define DMAREQ_WTIMER1_CC1 ((27 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */
Anna Bridge 142:4eea097334d6 86 #define DMAREQ_WTIMER1_CC2 ((27 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */
Anna Bridge 142:4eea097334d6 87 #define DMAREQ_WTIMER1_CC3 ((27 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */
Anna Bridge 142:4eea097334d6 88 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
Anna Bridge 142:4eea097334d6 89 #define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
Anna Bridge 142:4eea097334d6 90 #define DMAREQ_CRYPTO_DATA0WR DMAREQ_CRYPTO0_DATA0WR /**< Alias for DMAREQ_CRYPTO0_DATA0WR */
Anna Bridge 142:4eea097334d6 91 #define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
Anna Bridge 142:4eea097334d6 92 #define DMAREQ_CRYPTO_DATA0XWR DMAREQ_CRYPTO0_DATA0XWR /**< Alias for DMAREQ_CRYPTO0_DATA0XWR */
Anna Bridge 142:4eea097334d6 93 #define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
Anna Bridge 142:4eea097334d6 94 #define DMAREQ_CRYPTO_DATA0RD DMAREQ_CRYPTO0_DATA0RD /**< Alias for DMAREQ_CRYPTO0_DATA0RD */
Anna Bridge 142:4eea097334d6 95 #define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
Anna Bridge 142:4eea097334d6 96 #define DMAREQ_CRYPTO_DATA1WR DMAREQ_CRYPTO0_DATA1WR /**< Alias for DMAREQ_CRYPTO0_DATA1WR */
Anna Bridge 142:4eea097334d6 97 #define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
Anna Bridge 142:4eea097334d6 98 #define DMAREQ_CRYPTO_DATA1RD DMAREQ_CRYPTO0_DATA1RD /**< Alias for DMAREQ_CRYPTO0_DATA1RD */
Anna Bridge 142:4eea097334d6 99 #define DMAREQ_CSEN_DATA ((50 << 16) + 0) /**< DMA channel select for CSEN_DATA */
Anna Bridge 142:4eea097334d6 100 #define DMAREQ_CSEN_BSLN ((50 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
Anna Bridge 142:4eea097334d6 101 #define DMAREQ_LESENSE_BUFDATAV ((51 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
Anna Bridge 142:4eea097334d6 102 #define DMAREQ_CRYPTO1_DATA0WR ((52 << 16) + 0) /**< DMA channel select for CRYPTO1_DATA0WR */
Anna Bridge 142:4eea097334d6 103 #define DMAREQ_CRYPTO1_DATA0XWR ((52 << 16) + 1) /**< DMA channel select for CRYPTO1_DATA0XWR */
Anna Bridge 142:4eea097334d6 104 #define DMAREQ_CRYPTO1_DATA0RD ((52 << 16) + 2) /**< DMA channel select for CRYPTO1_DATA0RD */
Anna Bridge 142:4eea097334d6 105 #define DMAREQ_CRYPTO1_DATA1WR ((52 << 16) + 3) /**< DMA channel select for CRYPTO1_DATA1WR */
Anna Bridge 142:4eea097334d6 106 #define DMAREQ_CRYPTO1_DATA1RD ((52 << 16) + 4) /**< DMA channel select for CRYPTO1_DATA1RD */
Anna Bridge 142:4eea097334d6 107
Anna Bridge 142:4eea097334d6 108 /** @} End of group EFR32MG12P_DMAREQ */
Anna Bridge 142:4eea097334d6 109 /** @} End of group Parts */
Anna Bridge 142:4eea097334d6 110