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TARGET_TB_SENSE_12/TOOLCHAIN_ARM_STD/efr32mg12p_devinfo.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg12p_devinfo.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG12P_DEVINFO register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG12P_DEVINFO |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 40 | |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ |
| Anna Bridge |
142:4eea097334d6 | 44 | uint32_t RESERVED0[7]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IM uint32_t EXTINFO; /**< External Component description */ |
| Anna Bridge |
142:4eea097334d6 | 46 | uint32_t RESERVED1[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IM uint32_t EUI48H; /**< OUI */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IM uint32_t CUSTOMINFO; /**< Custom information */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ |
| Anna Bridge |
142:4eea097334d6 | 51 | uint32_t RESERVED2[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IM uint32_t PART; /**< Part description */ |
| Anna Bridge |
142:4eea097334d6 | 56 | __IM uint32_t DEVINFOREV; /**< Device information page revision */ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ |
| Anna Bridge |
142:4eea097334d6 | 58 | uint32_t RESERVED3[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 59 | __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 60 | __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ |
| Anna Bridge |
142:4eea097334d6 | 61 | __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ |
| Anna Bridge |
142:4eea097334d6 | 62 | __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ |
| Anna Bridge |
142:4eea097334d6 | 63 | uint32_t RESERVED4[4]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 64 | __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 65 | uint32_t RESERVED5[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 66 | __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 67 | uint32_t RESERVED6[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 68 | __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 69 | __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 70 | __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 71 | uint32_t RESERVED7[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 72 | __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 73 | __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 74 | __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 75 | uint32_t RESERVED8[11]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 76 | __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 77 | uint32_t RESERVED9[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 78 | __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 79 | uint32_t RESERVED10[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 80 | __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 81 | __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 82 | __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 83 | uint32_t RESERVED11[1]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 84 | __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 85 | __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 86 | __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ |
| Anna Bridge |
142:4eea097334d6 | 87 | uint32_t RESERVED12[11]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 88 | __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 89 | __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ |
| Anna Bridge |
142:4eea097334d6 | 90 | __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ |
| Anna Bridge |
142:4eea097334d6 | 91 | uint32_t RESERVED13[3]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 92 | __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 93 | __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ |
| Anna Bridge |
142:4eea097334d6 | 94 | uint32_t RESERVED14[2]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 95 | __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 96 | __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 97 | __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ |
| Anna Bridge |
142:4eea097334d6 | 98 | __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ |
| Anna Bridge |
142:4eea097334d6 | 99 | __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ |
| Anna Bridge |
142:4eea097334d6 | 100 | __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ |
| Anna Bridge |
142:4eea097334d6 | 101 | __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ |
| Anna Bridge |
142:4eea097334d6 | 102 | __IM uint32_t VDAC0MAINCAL; /**< VDAC0 Cals for Main Path */ |
| Anna Bridge |
142:4eea097334d6 | 103 | __IM uint32_t VDAC0ALTCAL; /**< VDAC0 Cals for Alternate Path */ |
| Anna Bridge |
142:4eea097334d6 | 104 | __IM uint32_t VDAC0CH1CAL; /**< VDAC0 CH1 Error Cal */ |
| Anna Bridge |
142:4eea097334d6 | 105 | __IM uint32_t OPA0CAL0; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 106 | __IM uint32_t OPA0CAL1; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 107 | __IM uint32_t OPA0CAL2; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 108 | __IM uint32_t OPA0CAL3; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 109 | __IM uint32_t OPA1CAL0; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 110 | __IM uint32_t OPA1CAL1; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 111 | __IM uint32_t OPA1CAL2; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 112 | __IM uint32_t OPA1CAL3; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 113 | __IM uint32_t OPA2CAL0; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 114 | __IM uint32_t OPA2CAL1; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 115 | __IM uint32_t OPA2CAL2; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 116 | __IM uint32_t OPA2CAL3; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ |
| Anna Bridge |
142:4eea097334d6 | 117 | __IM uint32_t CSENGAINCAL; /**< Cap Sense Gain Adjustment */ |
| Anna Bridge |
142:4eea097334d6 | 118 | uint32_t RESERVED15[3]; /**< Reserved for future use **/ |
| Anna Bridge |
142:4eea097334d6 | 119 | __IM uint32_t OPA0CAL4; /**< OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 120 | __IM uint32_t OPA0CAL5; /**< OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 121 | __IM uint32_t OPA0CAL6; /**< OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 122 | __IM uint32_t OPA0CAL7; /**< OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 123 | __IM uint32_t OPA1CAL4; /**< OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 124 | __IM uint32_t OPA1CAL5; /**< OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 125 | __IM uint32_t OPA1CAL6; /**< OPA1 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 126 | __IM uint32_t OPA1CAL7; /**< OPA1 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 127 | __IM uint32_t OPA2CAL4; /**< OPA2 Calibration Register for DRIVESTRENGTH 0, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 128 | __IM uint32_t OPA2CAL5; /**< OPA2 Calibration Register for DRIVESTRENGTH 1, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 129 | __IM uint32_t OPA2CAL6; /**< OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 130 | __IM uint32_t OPA2CAL7; /**< OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ |
| Anna Bridge |
142:4eea097334d6 | 131 | } DEVINFO_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 132 | |
| Anna Bridge |
142:4eea097334d6 | 133 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 134 | * @defgroup EFR32MG12P_DEVINFO_BitFields |
| Anna Bridge |
142:4eea097334d6 | 135 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 136 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 137 | |
| Anna Bridge |
142:4eea097334d6 | 138 | /* Bit fields for DEVINFO CAL */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ |
| Anna Bridge |
142:4eea097334d6 | 144 | |
| Anna Bridge |
142:4eea097334d6 | 145 | /* Bit fields for DEVINFO EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _DEVINFO_EXTINFO_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _DEVINFO_EXTINFO_TYPE_SHIFT 0 /**< Shift value for TYPE */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _DEVINFO_EXTINFO_TYPE_MASK 0xFFUL /**< Bit mask for TYPE */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define _DEVINFO_EXTINFO_TYPE_IS25LQ040B 0x00000001UL /**< Mode IS25LQ040B for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define _DEVINFO_EXTINFO_TYPE_AT25S041 0x00000002UL /**< Mode AT25S041 for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define _DEVINFO_EXTINFO_TYPE_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define DEVINFO_EXTINFO_TYPE_IS25LQ040B (_DEVINFO_EXTINFO_TYPE_IS25LQ040B << 0) /**< Shifted mode IS25LQ040B for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define DEVINFO_EXTINFO_TYPE_AT25S041 (_DEVINFO_EXTINFO_TYPE_AT25S041 << 0) /**< Shifted mode AT25S041 for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define DEVINFO_EXTINFO_TYPE_NONE (_DEVINFO_EXTINFO_TYPE_NONE << 0) /**< Shifted mode NONE for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define _DEVINFO_EXTINFO_CONNECTION_SHIFT 8 /**< Shift value for CONNECTION */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define _DEVINFO_EXTINFO_CONNECTION_MASK 0xFF00UL /**< Bit mask for CONNECTION */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define _DEVINFO_EXTINFO_CONNECTION_SPI 0x00000001UL /**< Mode SPI for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 158 | #define _DEVINFO_EXTINFO_CONNECTION_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 159 | #define DEVINFO_EXTINFO_CONNECTION_SPI (_DEVINFO_EXTINFO_CONNECTION_SPI << 8) /**< Shifted mode SPI for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define DEVINFO_EXTINFO_CONNECTION_NONE (_DEVINFO_EXTINFO_CONNECTION_NONE << 8) /**< Shifted mode NONE for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _DEVINFO_EXTINFO_REV_SHIFT 16 /**< Shift value for REV */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _DEVINFO_EXTINFO_REV_MASK 0xFF0000UL /**< Bit mask for REV */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _DEVINFO_EXTINFO_REV_REV1 0x00000001UL /**< Mode REV1 for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define _DEVINFO_EXTINFO_REV_NONE 0x000000FFUL /**< Mode NONE for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define DEVINFO_EXTINFO_REV_REV1 (_DEVINFO_EXTINFO_REV_REV1 << 16) /**< Shifted mode REV1 for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 166 | #define DEVINFO_EXTINFO_REV_NONE (_DEVINFO_EXTINFO_REV_NONE << 16) /**< Shifted mode NONE for DEVINFO_EXTINFO */ |
| Anna Bridge |
142:4eea097334d6 | 167 | |
| Anna Bridge |
142:4eea097334d6 | 168 | /* Bit fields for DEVINFO EUI48L */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ |
| Anna Bridge |
142:4eea097334d6 | 174 | |
| Anna Bridge |
142:4eea097334d6 | 175 | /* Bit fields for DEVINFO EUI48H */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ |
| Anna Bridge |
142:4eea097334d6 | 179 | |
| Anna Bridge |
142:4eea097334d6 | 180 | /* Bit fields for DEVINFO CUSTOMINFO */ |
| Anna Bridge |
142:4eea097334d6 | 181 | #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ |
| Anna Bridge |
142:4eea097334d6 | 182 | #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ |
| Anna Bridge |
142:4eea097334d6 | 183 | #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ |
| Anna Bridge |
142:4eea097334d6 | 184 | |
| Anna Bridge |
142:4eea097334d6 | 185 | /* Bit fields for DEVINFO MEMINFO */ |
| Anna Bridge |
142:4eea097334d6 | 186 | #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ |
| Anna Bridge |
142:4eea097334d6 | 187 | #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ |
| Anna Bridge |
142:4eea097334d6 | 188 | #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ |
| Anna Bridge |
142:4eea097334d6 | 189 | #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ |
| Anna Bridge |
142:4eea097334d6 | 190 | #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ |
| Anna Bridge |
142:4eea097334d6 | 191 | #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 192 | #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 193 | #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 194 | #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 195 | #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 196 | #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 197 | #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ |
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142:4eea097334d6 | 198 | #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ |
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142:4eea097334d6 | 199 | #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 200 | #define _DEVINFO_MEMINFO_PKGTYPE_BGA 0x0000004CUL /**< Mode BGA for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 201 | #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 202 | #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 203 | #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 204 | #define DEVINFO_MEMINFO_PKGTYPE_BGA (_DEVINFO_MEMINFO_PKGTYPE_BGA << 8) /**< Shifted mode BGA for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 205 | #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 206 | #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ |
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142:4eea097334d6 | 207 | #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ |
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142:4eea097334d6 | 208 | #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ |
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142:4eea097334d6 | 209 | #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ |
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142:4eea097334d6 | 210 | #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ |
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142:4eea097334d6 | 211 | |
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142:4eea097334d6 | 212 | /* Bit fields for DEVINFO UNIQUEL */ |
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142:4eea097334d6 | 213 | #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ |
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142:4eea097334d6 | 214 | #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ |
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142:4eea097334d6 | 215 | #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ |
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142:4eea097334d6 | 216 | |
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142:4eea097334d6 | 217 | /* Bit fields for DEVINFO UNIQUEH */ |
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142:4eea097334d6 | 218 | #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ |
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142:4eea097334d6 | 219 | #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ |
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142:4eea097334d6 | 220 | #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ |
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142:4eea097334d6 | 221 | |
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142:4eea097334d6 | 222 | /* Bit fields for DEVINFO MSIZE */ |
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142:4eea097334d6 | 223 | #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ |
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142:4eea097334d6 | 224 | #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ |
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142:4eea097334d6 | 225 | #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ |
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142:4eea097334d6 | 226 | #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ |
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142:4eea097334d6 | 227 | #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ |
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142:4eea097334d6 | 228 | |
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142:4eea097334d6 | 229 | /* Bit fields for DEVINFO PART */ |
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142:4eea097334d6 | 230 | #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ |
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142:4eea097334d6 | 231 | #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ |
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142:4eea097334d6 | 232 | #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ |
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142:4eea097334d6 | 233 | #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ |
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142:4eea097334d6 | 234 | #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ |
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142:4eea097334d6 | 235 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ |
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142:4eea097334d6 | 236 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 237 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ |
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142:4eea097334d6 | 238 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ |
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142:4eea097334d6 | 239 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 240 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ |
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142:4eea097334d6 | 241 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ |
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142:4eea097334d6 | 242 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 243 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ |
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142:4eea097334d6 | 244 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ |
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142:4eea097334d6 | 245 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */ |
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142:4eea097334d6 | 246 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 247 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ |
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142:4eea097334d6 | 248 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ |
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142:4eea097334d6 | 249 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 250 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ |
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142:4eea097334d6 | 251 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ |
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142:4eea097334d6 | 252 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 253 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ |
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142:4eea097334d6 | 254 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ |
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142:4eea097334d6 | 255 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 256 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ |
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142:4eea097334d6 | 257 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ |
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142:4eea097334d6 | 258 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 259 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ |
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142:4eea097334d6 | 260 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ |
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142:4eea097334d6 | 261 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 262 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ |
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142:4eea097334d6 | 263 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ |
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142:4eea097334d6 | 264 | #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ |
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142:4eea097334d6 | 265 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ |
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142:4eea097334d6 | 266 | #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ |
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142:4eea097334d6 | 267 | #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ |
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142:4eea097334d6 | 268 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ |
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142:4eea097334d6 | 269 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ |
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142:4eea097334d6 | 270 | #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ |
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142:4eea097334d6 | 271 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ |
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142:4eea097334d6 | 272 | #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ |
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142:4eea097334d6 | 273 | #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ |
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142:4eea097334d6 | 274 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ |
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142:4eea097334d6 | 275 | #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ |
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142:4eea097334d6 | 276 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ |
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142:4eea097334d6 | 277 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 278 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 279 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 280 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 281 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 282 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 283 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ |
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142:4eea097334d6 | 284 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ |
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142:4eea097334d6 | 285 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ |
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142:4eea097334d6 | 286 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ |
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142:4eea097334d6 | 287 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 288 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ |
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142:4eea097334d6 | 289 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ |
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142:4eea097334d6 | 290 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 291 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ |
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142:4eea097334d6 | 292 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ |
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142:4eea097334d6 | 293 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 294 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ |
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142:4eea097334d6 | 295 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ |
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142:4eea097334d6 | 296 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */ |
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142:4eea097334d6 | 297 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 298 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ |
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142:4eea097334d6 | 299 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ |
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142:4eea097334d6 | 300 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 301 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ |
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142:4eea097334d6 | 302 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ |
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142:4eea097334d6 | 303 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 304 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ |
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142:4eea097334d6 | 305 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ |
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142:4eea097334d6 | 306 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 307 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ |
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142:4eea097334d6 | 308 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ |
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142:4eea097334d6 | 309 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 310 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ |
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142:4eea097334d6 | 311 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ |
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142:4eea097334d6 | 312 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 313 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ |
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142:4eea097334d6 | 314 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ |
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142:4eea097334d6 | 315 | #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ |
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142:4eea097334d6 | 316 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ |
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142:4eea097334d6 | 317 | #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ |
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142:4eea097334d6 | 318 | #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ |
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142:4eea097334d6 | 319 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ |
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142:4eea097334d6 | 320 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ |
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142:4eea097334d6 | 321 | #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ |
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142:4eea097334d6 | 322 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ |
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142:4eea097334d6 | 323 | #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ |
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142:4eea097334d6 | 324 | #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ |
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142:4eea097334d6 | 325 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ |
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142:4eea097334d6 | 326 | #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ |
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142:4eea097334d6 | 327 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ |
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142:4eea097334d6 | 328 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 329 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ |
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142:4eea097334d6 | 330 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 331 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ |
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142:4eea097334d6 | 332 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 333 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */ |
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142:4eea097334d6 | 334 | #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ |
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142:4eea097334d6 | 335 | #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ |
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142:4eea097334d6 | 336 | #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ |
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142:4eea097334d6 | 337 | #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ |
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142:4eea097334d6 | 338 | #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ |
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142:4eea097334d6 | 339 | |
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142:4eea097334d6 | 340 | /* Bit fields for DEVINFO DEVINFOREV */ |
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142:4eea097334d6 | 341 | #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ |
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142:4eea097334d6 | 342 | #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ |
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142:4eea097334d6 | 343 | #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ |
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142:4eea097334d6 | 344 | |
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142:4eea097334d6 | 345 | /* Bit fields for DEVINFO EMUTEMP */ |
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142:4eea097334d6 | 346 | #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ |
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142:4eea097334d6 | 347 | #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ |
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142:4eea097334d6 | 348 | #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ |
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142:4eea097334d6 | 349 | |
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142:4eea097334d6 | 350 | /* Bit fields for DEVINFO ADC0CAL0 */ |
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142:4eea097334d6 | 351 | #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ |
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142:4eea097334d6 | 352 | #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ |
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142:4eea097334d6 | 353 | #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ |
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142:4eea097334d6 | 354 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ |
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142:4eea097334d6 | 355 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ |
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142:4eea097334d6 | 356 | #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ |
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142:4eea097334d6 | 357 | #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ |
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142:4eea097334d6 | 358 | #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ |
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142:4eea097334d6 | 359 | #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ |
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142:4eea097334d6 | 360 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ |
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142:4eea097334d6 | 361 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ |
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142:4eea097334d6 | 362 | #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ |
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142:4eea097334d6 | 363 | #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ |
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142:4eea097334d6 | 364 | |
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142:4eea097334d6 | 365 | /* Bit fields for DEVINFO ADC0CAL1 */ |
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142:4eea097334d6 | 366 | #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ |
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142:4eea097334d6 | 367 | #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ |
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142:4eea097334d6 | 368 | #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ |
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142:4eea097334d6 | 369 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ |
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142:4eea097334d6 | 370 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ |
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142:4eea097334d6 | 371 | #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ |
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142:4eea097334d6 | 372 | #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ |
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142:4eea097334d6 | 373 | #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ |
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142:4eea097334d6 | 374 | #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ |
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142:4eea097334d6 | 375 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ |
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142:4eea097334d6 | 376 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ |
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142:4eea097334d6 | 377 | #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ |
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142:4eea097334d6 | 378 | #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ |
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142:4eea097334d6 | 379 | |
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142:4eea097334d6 | 380 | /* Bit fields for DEVINFO ADC0CAL2 */ |
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142:4eea097334d6 | 381 | #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ |
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142:4eea097334d6 | 382 | #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ |
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142:4eea097334d6 | 383 | #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ |
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142:4eea097334d6 | 384 | #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ |
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142:4eea097334d6 | 385 | #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ |
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142:4eea097334d6 | 386 | |
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142:4eea097334d6 | 387 | /* Bit fields for DEVINFO ADC0CAL3 */ |
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142:4eea097334d6 | 388 | #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ |
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142:4eea097334d6 | 389 | #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ |
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142:4eea097334d6 | 390 | #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ |
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142:4eea097334d6 | 391 | |
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142:4eea097334d6 | 392 | /* Bit fields for DEVINFO HFRCOCAL0 */ |
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142:4eea097334d6 | 393 | #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ |
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142:4eea097334d6 | 394 | #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
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142:4eea097334d6 | 395 | #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
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142:4eea097334d6 | 396 | #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
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142:4eea097334d6 | 397 | #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
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142:4eea097334d6 | 398 | #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
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142:4eea097334d6 | 399 | #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
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142:4eea097334d6 | 400 | #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
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142:4eea097334d6 | 401 | #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
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142:4eea097334d6 | 402 | #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
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142:4eea097334d6 | 403 | #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
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142:4eea097334d6 | 404 | #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 405 | #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
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142:4eea097334d6 | 406 | #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
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142:4eea097334d6 | 407 | #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
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142:4eea097334d6 | 408 | #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
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142:4eea097334d6 | 409 | #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
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142:4eea097334d6 | 410 | |
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142:4eea097334d6 | 411 | /* Bit fields for DEVINFO HFRCOCAL3 */ |
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142:4eea097334d6 | 412 | #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ |
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142:4eea097334d6 | 413 | #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 414 | #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 415 | #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 416 | #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 417 | #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 418 | #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
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142:4eea097334d6 | 419 | #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 420 | #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 421 | #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 422 | #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 423 | #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 424 | #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 425 | #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 426 | #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
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142:4eea097334d6 | 427 | #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
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142:4eea097334d6 | 428 | #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
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142:4eea097334d6 | 429 | |
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142:4eea097334d6 | 430 | /* Bit fields for DEVINFO HFRCOCAL6 */ |
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142:4eea097334d6 | 431 | #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ |
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142:4eea097334d6 | 432 | #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 433 | #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 434 | #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 435 | #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 436 | #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 437 | #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 438 | #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 439 | #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 440 | #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 441 | #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 442 | #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 443 | #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 444 | #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 445 | #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 446 | #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 447 | #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
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142:4eea097334d6 | 448 | |
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142:4eea097334d6 | 449 | /* Bit fields for DEVINFO HFRCOCAL7 */ |
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142:4eea097334d6 | 450 | #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 451 | #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 452 | #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 453 | #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 454 | #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 455 | #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 456 | #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 457 | #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 458 | #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 459 | #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 460 | #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 461 | #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 462 | #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 463 | #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 464 | #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 465 | #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 466 | #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
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142:4eea097334d6 | 467 | |
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142:4eea097334d6 | 468 | /* Bit fields for DEVINFO HFRCOCAL8 */ |
| Anna Bridge |
142:4eea097334d6 | 469 | #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ |
| Anna Bridge |
142:4eea097334d6 | 470 | #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 471 | #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 472 | #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 473 | #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 474 | #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 475 | #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 476 | #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 477 | #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 478 | #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 479 | #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 480 | #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 481 | #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 482 | #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 483 | #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 484 | #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 485 | #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 486 | |
| Anna Bridge |
142:4eea097334d6 | 487 | /* Bit fields for DEVINFO HFRCOCAL10 */ |
| Anna Bridge |
142:4eea097334d6 | 488 | #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ |
| Anna Bridge |
142:4eea097334d6 | 489 | #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 490 | #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 491 | #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 492 | #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 493 | #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 494 | #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 495 | #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 496 | #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 497 | #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 498 | #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 499 | #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 500 | #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 501 | #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 502 | #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 503 | #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 504 | #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 505 | |
| Anna Bridge |
142:4eea097334d6 | 506 | /* Bit fields for DEVINFO HFRCOCAL11 */ |
| Anna Bridge |
142:4eea097334d6 | 507 | #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ |
| Anna Bridge |
142:4eea097334d6 | 508 | #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 509 | #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 510 | #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 511 | #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 512 | #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 513 | #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 514 | #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 515 | #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 516 | #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 517 | #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 518 | #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 519 | #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 520 | #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 521 | #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 522 | #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 523 | #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 524 | |
| Anna Bridge |
142:4eea097334d6 | 525 | /* Bit fields for DEVINFO HFRCOCAL12 */ |
| Anna Bridge |
142:4eea097334d6 | 526 | #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ |
| Anna Bridge |
142:4eea097334d6 | 527 | #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 528 | #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 529 | #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 530 | #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 531 | #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 532 | #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 533 | #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 534 | #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 535 | #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 536 | #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 537 | #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 538 | #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 539 | #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 540 | #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 541 | #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 542 | #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 543 | |
| Anna Bridge |
142:4eea097334d6 | 544 | /* Bit fields for DEVINFO AUXHFRCOCAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 545 | #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 546 | #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 547 | #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 548 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 549 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 550 | #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 551 | #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 552 | #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 553 | #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 554 | #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 555 | #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 556 | #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 557 | #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 558 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 559 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 560 | #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 561 | #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 562 | |
| Anna Bridge |
142:4eea097334d6 | 563 | /* Bit fields for DEVINFO AUXHFRCOCAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 564 | #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 565 | #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 566 | #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 567 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 568 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 569 | #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 570 | #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 571 | #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 572 | #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 573 | #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 574 | #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 575 | #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 576 | #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 577 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 578 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 579 | #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 580 | #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 581 | |
| Anna Bridge |
142:4eea097334d6 | 582 | /* Bit fields for DEVINFO AUXHFRCOCAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 583 | #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 584 | #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 585 | #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 586 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 587 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 588 | #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 589 | #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 590 | #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 591 | #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 592 | #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 593 | #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 594 | #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 595 | #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 596 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 597 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 598 | #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 599 | #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 600 | |
| Anna Bridge |
142:4eea097334d6 | 601 | /* Bit fields for DEVINFO AUXHFRCOCAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 602 | #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 603 | #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 604 | #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 605 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 606 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 607 | #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 608 | #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 609 | #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 610 | #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 611 | #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 612 | #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 613 | #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 614 | #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 615 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 616 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 617 | #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 618 | #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 619 | |
| Anna Bridge |
142:4eea097334d6 | 620 | /* Bit fields for DEVINFO AUXHFRCOCAL8 */ |
| Anna Bridge |
142:4eea097334d6 | 621 | #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ |
| Anna Bridge |
142:4eea097334d6 | 622 | #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 623 | #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 624 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 625 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 626 | #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 627 | #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 628 | #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 629 | #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 630 | #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 631 | #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 632 | #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 633 | #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 634 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 635 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 636 | #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 637 | #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 638 | |
| Anna Bridge |
142:4eea097334d6 | 639 | /* Bit fields for DEVINFO AUXHFRCOCAL10 */ |
| Anna Bridge |
142:4eea097334d6 | 640 | #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ |
| Anna Bridge |
142:4eea097334d6 | 641 | #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 642 | #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 643 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 644 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 645 | #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 646 | #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 647 | #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 648 | #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 649 | #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 650 | #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 651 | #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 652 | #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 653 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 654 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 655 | #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 656 | #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
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142:4eea097334d6 | 657 | |
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142:4eea097334d6 | 658 | /* Bit fields for DEVINFO AUXHFRCOCAL11 */ |
| Anna Bridge |
142:4eea097334d6 | 659 | #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ |
| Anna Bridge |
142:4eea097334d6 | 660 | #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 661 | #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
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142:4eea097334d6 | 662 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 663 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
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142:4eea097334d6 | 664 | #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
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142:4eea097334d6 | 665 | #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 666 | #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 667 | #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 668 | #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
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142:4eea097334d6 | 669 | #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 670 | #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 671 | #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 672 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 673 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 674 | #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 675 | #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
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142:4eea097334d6 | 676 | |
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142:4eea097334d6 | 677 | /* Bit fields for DEVINFO AUXHFRCOCAL12 */ |
| Anna Bridge |
142:4eea097334d6 | 678 | #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ |
| Anna Bridge |
142:4eea097334d6 | 679 | #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 680 | #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 681 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 682 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| Anna Bridge |
142:4eea097334d6 | 683 | #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 684 | #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| Anna Bridge |
142:4eea097334d6 | 685 | #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 686 | #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| Anna Bridge |
142:4eea097334d6 | 687 | #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 688 | #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| Anna Bridge |
142:4eea097334d6 | 689 | #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 690 | #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| Anna Bridge |
142:4eea097334d6 | 691 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 692 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| Anna Bridge |
142:4eea097334d6 | 693 | #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 694 | #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| Anna Bridge |
142:4eea097334d6 | 695 | |
| Anna Bridge |
142:4eea097334d6 | 696 | /* Bit fields for DEVINFO VMONCAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 697 | #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 698 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 699 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 700 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 701 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 702 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 703 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 704 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 705 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 706 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 707 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 708 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 709 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 710 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 711 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 712 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 713 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 714 | |
| Anna Bridge |
142:4eea097334d6 | 715 | /* Bit fields for DEVINFO VMONCAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 716 | #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 717 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 718 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 719 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 720 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 721 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 722 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 723 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 724 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 725 | #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 726 | #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 727 | #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 728 | #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 729 | #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 730 | #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 731 | #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 732 | #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 733 | |
| Anna Bridge |
142:4eea097334d6 | 734 | /* Bit fields for DEVINFO VMONCAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 735 | #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 736 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 737 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 738 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 739 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 740 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 741 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 742 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 743 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 744 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 745 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 746 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 747 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 748 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 749 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ |
| Anna Bridge |
142:4eea097334d6 | 750 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 751 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ |
| Anna Bridge |
142:4eea097334d6 | 752 | |
| Anna Bridge |
142:4eea097334d6 | 753 | /* Bit fields for DEVINFO IDAC0CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 754 | #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 755 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 756 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 757 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 758 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 759 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 760 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 761 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 762 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 763 | |
| Anna Bridge |
142:4eea097334d6 | 764 | /* Bit fields for DEVINFO IDAC0CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 765 | #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 766 | #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 767 | #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 768 | #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 769 | #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 770 | #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 771 | #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 772 | #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 773 | #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ |
| Anna Bridge |
142:4eea097334d6 | 774 | |
| Anna Bridge |
142:4eea097334d6 | 775 | /* Bit fields for DEVINFO DCDCLNVCTRL0 */ |
| Anna Bridge |
142:4eea097334d6 | 776 | #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ |
| Anna Bridge |
142:4eea097334d6 | 777 | #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ |
| Anna Bridge |
142:4eea097334d6 | 778 | #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ |
| Anna Bridge |
142:4eea097334d6 | 779 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ |
| Anna Bridge |
142:4eea097334d6 | 780 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ |
| Anna Bridge |
142:4eea097334d6 | 781 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ |
| Anna Bridge |
142:4eea097334d6 | 782 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ |
| Anna Bridge |
142:4eea097334d6 | 783 | #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ |
| Anna Bridge |
142:4eea097334d6 | 784 | #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ |
| Anna Bridge |
142:4eea097334d6 | 785 | |
| Anna Bridge |
142:4eea097334d6 | 786 | /* Bit fields for DEVINFO DCDCLPVCTRL0 */ |
| Anna Bridge |
142:4eea097334d6 | 787 | #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ |
| Anna Bridge |
142:4eea097334d6 | 788 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 789 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 790 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 791 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 792 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 793 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 794 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 795 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 796 | |
| Anna Bridge |
142:4eea097334d6 | 797 | /* Bit fields for DEVINFO DCDCLPVCTRL1 */ |
| Anna Bridge |
142:4eea097334d6 | 798 | #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ |
| Anna Bridge |
142:4eea097334d6 | 799 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 800 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 801 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 802 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 803 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 804 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 805 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 806 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 807 | |
| Anna Bridge |
142:4eea097334d6 | 808 | /* Bit fields for DEVINFO DCDCLPVCTRL2 */ |
| Anna Bridge |
142:4eea097334d6 | 809 | #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ |
| Anna Bridge |
142:4eea097334d6 | 810 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 811 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 812 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 813 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 814 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 815 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 816 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 817 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 818 | |
| Anna Bridge |
142:4eea097334d6 | 819 | /* Bit fields for DEVINFO DCDCLPVCTRL3 */ |
| Anna Bridge |
142:4eea097334d6 | 820 | #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ |
| Anna Bridge |
142:4eea097334d6 | 821 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 822 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 823 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 824 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 825 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 826 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 827 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 828 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 829 | |
| Anna Bridge |
142:4eea097334d6 | 830 | /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 831 | #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ |
| Anna Bridge |
142:4eea097334d6 | 832 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ |
| Anna Bridge |
142:4eea097334d6 | 833 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ |
| Anna Bridge |
142:4eea097334d6 | 834 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ |
| Anna Bridge |
142:4eea097334d6 | 835 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ |
| Anna Bridge |
142:4eea097334d6 | 836 | |
| Anna Bridge |
142:4eea097334d6 | 837 | /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 838 | #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ |
| Anna Bridge |
142:4eea097334d6 | 839 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 840 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ |
| Anna Bridge |
142:4eea097334d6 | 841 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 842 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ |
| Anna Bridge |
142:4eea097334d6 | 843 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 844 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ |
| Anna Bridge |
142:4eea097334d6 | 845 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 846 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ |
| Anna Bridge |
142:4eea097334d6 | 847 | |
| Anna Bridge |
142:4eea097334d6 | 848 | /* Bit fields for DEVINFO VDAC0MAINCAL */ |
| Anna Bridge |
142:4eea097334d6 | 849 | #define _DEVINFO_VDAC0MAINCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0MAINCAL */ |
| Anna Bridge |
142:4eea097334d6 | 850 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LN */ |
| Anna Bridge |
142:4eea097334d6 | 851 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25LN_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LN */ |
| Anna Bridge |
142:4eea097334d6 | 852 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LN */ |
| Anna Bridge |
142:4eea097334d6 | 853 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5LN_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LN */ |
| Anna Bridge |
142:4eea097334d6 | 854 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_SHIFT 12 /**< Shift value for GAINERRTRIM1V25 */ |
| Anna Bridge |
142:4eea097334d6 | 855 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM1V25_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25 */ |
| Anna Bridge |
142:4eea097334d6 | 856 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_SHIFT 18 /**< Shift value for GAINERRTRIM2V5 */ |
| Anna Bridge |
142:4eea097334d6 | 857 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIM2V5_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5 */ |
| Anna Bridge |
142:4eea097334d6 | 858 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPIN */ |
| Anna Bridge |
142:4eea097334d6 | 859 | #define _DEVINFO_VDAC0MAINCAL_GAINERRTRIMVDDANAEXTPIN_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPIN */ |
| Anna Bridge |
142:4eea097334d6 | 860 | |
| Anna Bridge |
142:4eea097334d6 | 861 | /* Bit fields for DEVINFO VDAC0ALTCAL */ |
| Anna Bridge |
142:4eea097334d6 | 862 | #define _DEVINFO_VDAC0ALTCAL_MASK 0x3FFFFFFFUL /**< Mask for DEVINFO_VDAC0ALTCAL */ |
| Anna Bridge |
142:4eea097334d6 | 863 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_SHIFT 0 /**< Shift value for GAINERRTRIM1V25LNALT */ |
| Anna Bridge |
142:4eea097334d6 | 864 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25LNALT_MASK 0x3FUL /**< Bit mask for GAINERRTRIM1V25LNALT */ |
| Anna Bridge |
142:4eea097334d6 | 865 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_SHIFT 6 /**< Shift value for GAINERRTRIM2V5LNALT */ |
| Anna Bridge |
142:4eea097334d6 | 866 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5LNALT_MASK 0xFC0UL /**< Bit mask for GAINERRTRIM2V5LNALT */ |
| Anna Bridge |
142:4eea097334d6 | 867 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_SHIFT 12 /**< Shift value for GAINERRTRIM1V25ALT */ |
| Anna Bridge |
142:4eea097334d6 | 868 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM1V25ALT_MASK 0x3F000UL /**< Bit mask for GAINERRTRIM1V25ALT */ |
| Anna Bridge |
142:4eea097334d6 | 869 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_SHIFT 18 /**< Shift value for GAINERRTRIM2V5ALT */ |
| Anna Bridge |
142:4eea097334d6 | 870 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIM2V5ALT_MASK 0xFC0000UL /**< Bit mask for GAINERRTRIM2V5ALT */ |
| Anna Bridge |
142:4eea097334d6 | 871 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_SHIFT 24 /**< Shift value for GAINERRTRIMVDDANAEXTPINALT */ |
| Anna Bridge |
142:4eea097334d6 | 872 | #define _DEVINFO_VDAC0ALTCAL_GAINERRTRIMVDDANAEXTPINALT_MASK 0x3F000000UL /**< Bit mask for GAINERRTRIMVDDANAEXTPINALT */ |
| Anna Bridge |
142:4eea097334d6 | 873 | |
| Anna Bridge |
142:4eea097334d6 | 874 | /* Bit fields for DEVINFO VDAC0CH1CAL */ |
| Anna Bridge |
142:4eea097334d6 | 875 | #define _DEVINFO_VDAC0CH1CAL_MASK 0x00000FF7UL /**< Mask for DEVINFO_VDAC0CH1CAL */ |
| Anna Bridge |
142:4eea097334d6 | 876 | #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_SHIFT 0 /**< Shift value for OFFSETTRIM */ |
| Anna Bridge |
142:4eea097334d6 | 877 | #define _DEVINFO_VDAC0CH1CAL_OFFSETTRIM_MASK 0x7UL /**< Bit mask for OFFSETTRIM */ |
| Anna Bridge |
142:4eea097334d6 | 878 | #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_SHIFT 4 /**< Shift value for GAINERRTRIMCH1A */ |
| Anna Bridge |
142:4eea097334d6 | 879 | #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1A_MASK 0xF0UL /**< Bit mask for GAINERRTRIMCH1A */ |
| Anna Bridge |
142:4eea097334d6 | 880 | #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_SHIFT 8 /**< Shift value for GAINERRTRIMCH1B */ |
| Anna Bridge |
142:4eea097334d6 | 881 | #define _DEVINFO_VDAC0CH1CAL_GAINERRTRIMCH1B_MASK 0xF00UL /**< Bit mask for GAINERRTRIMCH1B */ |
| Anna Bridge |
142:4eea097334d6 | 882 | |
| Anna Bridge |
142:4eea097334d6 | 883 | /* Bit fields for DEVINFO OPA0CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 884 | #define _DEVINFO_OPA0CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 885 | #define _DEVINFO_OPA0CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 886 | #define _DEVINFO_OPA0CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 887 | #define _DEVINFO_OPA0CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 888 | #define _DEVINFO_OPA0CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 889 | #define _DEVINFO_OPA0CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 890 | #define _DEVINFO_OPA0CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 891 | #define _DEVINFO_OPA0CAL0_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 892 | #define _DEVINFO_OPA0CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 893 | #define _DEVINFO_OPA0CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 894 | #define _DEVINFO_OPA0CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 895 | #define _DEVINFO_OPA0CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 896 | #define _DEVINFO_OPA0CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 897 | #define _DEVINFO_OPA0CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 898 | #define _DEVINFO_OPA0CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 899 | |
| Anna Bridge |
142:4eea097334d6 | 900 | /* Bit fields for DEVINFO OPA0CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 901 | #define _DEVINFO_OPA0CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 902 | #define _DEVINFO_OPA0CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 903 | #define _DEVINFO_OPA0CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 904 | #define _DEVINFO_OPA0CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 905 | #define _DEVINFO_OPA0CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 906 | #define _DEVINFO_OPA0CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 907 | #define _DEVINFO_OPA0CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 908 | #define _DEVINFO_OPA0CAL1_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 909 | #define _DEVINFO_OPA0CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 910 | #define _DEVINFO_OPA0CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 911 | #define _DEVINFO_OPA0CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 912 | #define _DEVINFO_OPA0CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 913 | #define _DEVINFO_OPA0CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 914 | #define _DEVINFO_OPA0CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 915 | #define _DEVINFO_OPA0CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 916 | |
| Anna Bridge |
142:4eea097334d6 | 917 | /* Bit fields for DEVINFO OPA0CAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 918 | #define _DEVINFO_OPA0CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 919 | #define _DEVINFO_OPA0CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 920 | #define _DEVINFO_OPA0CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 921 | #define _DEVINFO_OPA0CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 922 | #define _DEVINFO_OPA0CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 923 | #define _DEVINFO_OPA0CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 924 | #define _DEVINFO_OPA0CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 925 | #define _DEVINFO_OPA0CAL2_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 926 | #define _DEVINFO_OPA0CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 927 | #define _DEVINFO_OPA0CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 928 | #define _DEVINFO_OPA0CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 929 | #define _DEVINFO_OPA0CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 930 | #define _DEVINFO_OPA0CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 931 | #define _DEVINFO_OPA0CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 932 | #define _DEVINFO_OPA0CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 933 | |
| Anna Bridge |
142:4eea097334d6 | 934 | /* Bit fields for DEVINFO OPA0CAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 935 | #define _DEVINFO_OPA0CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 936 | #define _DEVINFO_OPA0CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 937 | #define _DEVINFO_OPA0CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 938 | #define _DEVINFO_OPA0CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 939 | #define _DEVINFO_OPA0CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 940 | #define _DEVINFO_OPA0CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 941 | #define _DEVINFO_OPA0CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 942 | #define _DEVINFO_OPA0CAL3_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 943 | #define _DEVINFO_OPA0CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 944 | #define _DEVINFO_OPA0CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 945 | #define _DEVINFO_OPA0CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 946 | #define _DEVINFO_OPA0CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 947 | #define _DEVINFO_OPA0CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 948 | #define _DEVINFO_OPA0CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 949 | #define _DEVINFO_OPA0CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 950 | |
| Anna Bridge |
142:4eea097334d6 | 951 | /* Bit fields for DEVINFO OPA1CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 952 | #define _DEVINFO_OPA1CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 953 | #define _DEVINFO_OPA1CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 954 | #define _DEVINFO_OPA1CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 955 | #define _DEVINFO_OPA1CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 956 | #define _DEVINFO_OPA1CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 957 | #define _DEVINFO_OPA1CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 958 | #define _DEVINFO_OPA1CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 959 | #define _DEVINFO_OPA1CAL0_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 960 | #define _DEVINFO_OPA1CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 961 | #define _DEVINFO_OPA1CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 962 | #define _DEVINFO_OPA1CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 963 | #define _DEVINFO_OPA1CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 964 | #define _DEVINFO_OPA1CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 965 | #define _DEVINFO_OPA1CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 966 | #define _DEVINFO_OPA1CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 967 | |
| Anna Bridge |
142:4eea097334d6 | 968 | /* Bit fields for DEVINFO OPA1CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 969 | #define _DEVINFO_OPA1CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 970 | #define _DEVINFO_OPA1CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 971 | #define _DEVINFO_OPA1CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 972 | #define _DEVINFO_OPA1CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 973 | #define _DEVINFO_OPA1CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 974 | #define _DEVINFO_OPA1CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 975 | #define _DEVINFO_OPA1CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 976 | #define _DEVINFO_OPA1CAL1_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 977 | #define _DEVINFO_OPA1CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 978 | #define _DEVINFO_OPA1CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 979 | #define _DEVINFO_OPA1CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 980 | #define _DEVINFO_OPA1CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 981 | #define _DEVINFO_OPA1CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 982 | #define _DEVINFO_OPA1CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 983 | #define _DEVINFO_OPA1CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 984 | |
| Anna Bridge |
142:4eea097334d6 | 985 | /* Bit fields for DEVINFO OPA1CAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 986 | #define _DEVINFO_OPA1CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 987 | #define _DEVINFO_OPA1CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 988 | #define _DEVINFO_OPA1CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 989 | #define _DEVINFO_OPA1CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 990 | #define _DEVINFO_OPA1CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 991 | #define _DEVINFO_OPA1CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 992 | #define _DEVINFO_OPA1CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 993 | #define _DEVINFO_OPA1CAL2_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 994 | #define _DEVINFO_OPA1CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 995 | #define _DEVINFO_OPA1CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 996 | #define _DEVINFO_OPA1CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 997 | #define _DEVINFO_OPA1CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 998 | #define _DEVINFO_OPA1CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 999 | #define _DEVINFO_OPA1CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1000 | #define _DEVINFO_OPA1CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1001 | |
| Anna Bridge |
142:4eea097334d6 | 1002 | /* Bit fields for DEVINFO OPA1CAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 1003 | #define _DEVINFO_OPA1CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 1004 | #define _DEVINFO_OPA1CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1005 | #define _DEVINFO_OPA1CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1006 | #define _DEVINFO_OPA1CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1007 | #define _DEVINFO_OPA1CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1008 | #define _DEVINFO_OPA1CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1009 | #define _DEVINFO_OPA1CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1010 | #define _DEVINFO_OPA1CAL3_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1011 | #define _DEVINFO_OPA1CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1012 | #define _DEVINFO_OPA1CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1013 | #define _DEVINFO_OPA1CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1014 | #define _DEVINFO_OPA1CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1015 | #define _DEVINFO_OPA1CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1016 | #define _DEVINFO_OPA1CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1017 | #define _DEVINFO_OPA1CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1018 | |
| Anna Bridge |
142:4eea097334d6 | 1019 | /* Bit fields for DEVINFO OPA2CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 1020 | #define _DEVINFO_OPA2CAL0_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL0 */ |
| Anna Bridge |
142:4eea097334d6 | 1021 | #define _DEVINFO_OPA2CAL0_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1022 | #define _DEVINFO_OPA2CAL0_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1023 | #define _DEVINFO_OPA2CAL0_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1024 | #define _DEVINFO_OPA2CAL0_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1025 | #define _DEVINFO_OPA2CAL0_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1026 | #define _DEVINFO_OPA2CAL0_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1027 | #define _DEVINFO_OPA2CAL0_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1028 | #define _DEVINFO_OPA2CAL0_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1029 | #define _DEVINFO_OPA2CAL0_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1030 | #define _DEVINFO_OPA2CAL0_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1031 | #define _DEVINFO_OPA2CAL0_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1032 | #define _DEVINFO_OPA2CAL0_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1033 | #define _DEVINFO_OPA2CAL0_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1034 | #define _DEVINFO_OPA2CAL0_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1035 | |
| Anna Bridge |
142:4eea097334d6 | 1036 | /* Bit fields for DEVINFO OPA2CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 1037 | #define _DEVINFO_OPA2CAL1_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL1 */ |
| Anna Bridge |
142:4eea097334d6 | 1038 | #define _DEVINFO_OPA2CAL1_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1039 | #define _DEVINFO_OPA2CAL1_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1040 | #define _DEVINFO_OPA2CAL1_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1041 | #define _DEVINFO_OPA2CAL1_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1042 | #define _DEVINFO_OPA2CAL1_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1043 | #define _DEVINFO_OPA2CAL1_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1044 | #define _DEVINFO_OPA2CAL1_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1045 | #define _DEVINFO_OPA2CAL1_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1046 | #define _DEVINFO_OPA2CAL1_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1047 | #define _DEVINFO_OPA2CAL1_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1048 | #define _DEVINFO_OPA2CAL1_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1049 | #define _DEVINFO_OPA2CAL1_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1050 | #define _DEVINFO_OPA2CAL1_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1051 | #define _DEVINFO_OPA2CAL1_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1052 | |
| Anna Bridge |
142:4eea097334d6 | 1053 | /* Bit fields for DEVINFO OPA2CAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 1054 | #define _DEVINFO_OPA2CAL2_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL2 */ |
| Anna Bridge |
142:4eea097334d6 | 1055 | #define _DEVINFO_OPA2CAL2_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1056 | #define _DEVINFO_OPA2CAL2_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1057 | #define _DEVINFO_OPA2CAL2_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1058 | #define _DEVINFO_OPA2CAL2_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1059 | #define _DEVINFO_OPA2CAL2_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1060 | #define _DEVINFO_OPA2CAL2_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1061 | #define _DEVINFO_OPA2CAL2_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1062 | #define _DEVINFO_OPA2CAL2_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1063 | #define _DEVINFO_OPA2CAL2_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1064 | #define _DEVINFO_OPA2CAL2_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1065 | #define _DEVINFO_OPA2CAL2_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1066 | #define _DEVINFO_OPA2CAL2_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1067 | #define _DEVINFO_OPA2CAL2_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1068 | #define _DEVINFO_OPA2CAL2_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1069 | |
| Anna Bridge |
142:4eea097334d6 | 1070 | /* Bit fields for DEVINFO OPA2CAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 1071 | #define _DEVINFO_OPA2CAL3_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL3 */ |
| Anna Bridge |
142:4eea097334d6 | 1072 | #define _DEVINFO_OPA2CAL3_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1073 | #define _DEVINFO_OPA2CAL3_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1074 | #define _DEVINFO_OPA2CAL3_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1075 | #define _DEVINFO_OPA2CAL3_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1076 | #define _DEVINFO_OPA2CAL3_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1077 | #define _DEVINFO_OPA2CAL3_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1078 | #define _DEVINFO_OPA2CAL3_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1079 | #define _DEVINFO_OPA2CAL3_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1080 | #define _DEVINFO_OPA2CAL3_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1081 | #define _DEVINFO_OPA2CAL3_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1082 | #define _DEVINFO_OPA2CAL3_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1083 | #define _DEVINFO_OPA2CAL3_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1084 | #define _DEVINFO_OPA2CAL3_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1085 | #define _DEVINFO_OPA2CAL3_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1086 | |
| Anna Bridge |
142:4eea097334d6 | 1087 | /* Bit fields for DEVINFO CSENGAINCAL */ |
| Anna Bridge |
142:4eea097334d6 | 1088 | #define _DEVINFO_CSENGAINCAL_MASK 0x000000FFUL /**< Mask for DEVINFO_CSENGAINCAL */ |
| Anna Bridge |
142:4eea097334d6 | 1089 | #define _DEVINFO_CSENGAINCAL_GAINCAL_SHIFT 0 /**< Shift value for GAINCAL */ |
| Anna Bridge |
142:4eea097334d6 | 1090 | #define _DEVINFO_CSENGAINCAL_GAINCAL_MASK 0xFFUL /**< Bit mask for GAINCAL */ |
| Anna Bridge |
142:4eea097334d6 | 1091 | |
| Anna Bridge |
142:4eea097334d6 | 1092 | /* Bit fields for DEVINFO OPA0CAL4 */ |
| Anna Bridge |
142:4eea097334d6 | 1093 | #define _DEVINFO_OPA0CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL4 */ |
| Anna Bridge |
142:4eea097334d6 | 1094 | #define _DEVINFO_OPA0CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1095 | #define _DEVINFO_OPA0CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1096 | #define _DEVINFO_OPA0CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1097 | #define _DEVINFO_OPA0CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1098 | #define _DEVINFO_OPA0CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1099 | #define _DEVINFO_OPA0CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1100 | #define _DEVINFO_OPA0CAL4_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1101 | #define _DEVINFO_OPA0CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1102 | #define _DEVINFO_OPA0CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1103 | #define _DEVINFO_OPA0CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1104 | #define _DEVINFO_OPA0CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1105 | #define _DEVINFO_OPA0CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1106 | #define _DEVINFO_OPA0CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1107 | #define _DEVINFO_OPA0CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1108 | |
| Anna Bridge |
142:4eea097334d6 | 1109 | /* Bit fields for DEVINFO OPA0CAL5 */ |
| Anna Bridge |
142:4eea097334d6 | 1110 | #define _DEVINFO_OPA0CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL5 */ |
| Anna Bridge |
142:4eea097334d6 | 1111 | #define _DEVINFO_OPA0CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1112 | #define _DEVINFO_OPA0CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1113 | #define _DEVINFO_OPA0CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1114 | #define _DEVINFO_OPA0CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1115 | #define _DEVINFO_OPA0CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1116 | #define _DEVINFO_OPA0CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1117 | #define _DEVINFO_OPA0CAL5_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1118 | #define _DEVINFO_OPA0CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1119 | #define _DEVINFO_OPA0CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1120 | #define _DEVINFO_OPA0CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1121 | #define _DEVINFO_OPA0CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1122 | #define _DEVINFO_OPA0CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1123 | #define _DEVINFO_OPA0CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1124 | #define _DEVINFO_OPA0CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1125 | |
| Anna Bridge |
142:4eea097334d6 | 1126 | /* Bit fields for DEVINFO OPA0CAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 1127 | #define _DEVINFO_OPA0CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 1128 | #define _DEVINFO_OPA0CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1129 | #define _DEVINFO_OPA0CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1130 | #define _DEVINFO_OPA0CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1131 | #define _DEVINFO_OPA0CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1132 | #define _DEVINFO_OPA0CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1133 | #define _DEVINFO_OPA0CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1134 | #define _DEVINFO_OPA0CAL6_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1135 | #define _DEVINFO_OPA0CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1136 | #define _DEVINFO_OPA0CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1137 | #define _DEVINFO_OPA0CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1138 | #define _DEVINFO_OPA0CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1139 | #define _DEVINFO_OPA0CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1140 | #define _DEVINFO_OPA0CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1141 | #define _DEVINFO_OPA0CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1142 | |
| Anna Bridge |
142:4eea097334d6 | 1143 | /* Bit fields for DEVINFO OPA0CAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 1144 | #define _DEVINFO_OPA0CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA0CAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 1145 | #define _DEVINFO_OPA0CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1146 | #define _DEVINFO_OPA0CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1147 | #define _DEVINFO_OPA0CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1148 | #define _DEVINFO_OPA0CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1149 | #define _DEVINFO_OPA0CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1150 | #define _DEVINFO_OPA0CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1151 | #define _DEVINFO_OPA0CAL7_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1152 | #define _DEVINFO_OPA0CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1153 | #define _DEVINFO_OPA0CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1154 | #define _DEVINFO_OPA0CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1155 | #define _DEVINFO_OPA0CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1156 | #define _DEVINFO_OPA0CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1157 | #define _DEVINFO_OPA0CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1158 | #define _DEVINFO_OPA0CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1159 | |
| Anna Bridge |
142:4eea097334d6 | 1160 | /* Bit fields for DEVINFO OPA1CAL4 */ |
| Anna Bridge |
142:4eea097334d6 | 1161 | #define _DEVINFO_OPA1CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL4 */ |
| Anna Bridge |
142:4eea097334d6 | 1162 | #define _DEVINFO_OPA1CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1163 | #define _DEVINFO_OPA1CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1164 | #define _DEVINFO_OPA1CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1165 | #define _DEVINFO_OPA1CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1166 | #define _DEVINFO_OPA1CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1167 | #define _DEVINFO_OPA1CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1168 | #define _DEVINFO_OPA1CAL4_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1169 | #define _DEVINFO_OPA1CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1170 | #define _DEVINFO_OPA1CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1171 | #define _DEVINFO_OPA1CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1172 | #define _DEVINFO_OPA1CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1173 | #define _DEVINFO_OPA1CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1174 | #define _DEVINFO_OPA1CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1175 | #define _DEVINFO_OPA1CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1176 | |
| Anna Bridge |
142:4eea097334d6 | 1177 | /* Bit fields for DEVINFO OPA1CAL5 */ |
| Anna Bridge |
142:4eea097334d6 | 1178 | #define _DEVINFO_OPA1CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL5 */ |
| Anna Bridge |
142:4eea097334d6 | 1179 | #define _DEVINFO_OPA1CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1180 | #define _DEVINFO_OPA1CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1181 | #define _DEVINFO_OPA1CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1182 | #define _DEVINFO_OPA1CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1183 | #define _DEVINFO_OPA1CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1184 | #define _DEVINFO_OPA1CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1185 | #define _DEVINFO_OPA1CAL5_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1186 | #define _DEVINFO_OPA1CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1187 | #define _DEVINFO_OPA1CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1188 | #define _DEVINFO_OPA1CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1189 | #define _DEVINFO_OPA1CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1190 | #define _DEVINFO_OPA1CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1191 | #define _DEVINFO_OPA1CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1192 | #define _DEVINFO_OPA1CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1193 | |
| Anna Bridge |
142:4eea097334d6 | 1194 | /* Bit fields for DEVINFO OPA1CAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 1195 | #define _DEVINFO_OPA1CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 1196 | #define _DEVINFO_OPA1CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1197 | #define _DEVINFO_OPA1CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1198 | #define _DEVINFO_OPA1CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1199 | #define _DEVINFO_OPA1CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1200 | #define _DEVINFO_OPA1CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1201 | #define _DEVINFO_OPA1CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1202 | #define _DEVINFO_OPA1CAL6_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1203 | #define _DEVINFO_OPA1CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1204 | #define _DEVINFO_OPA1CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1205 | #define _DEVINFO_OPA1CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1206 | #define _DEVINFO_OPA1CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1207 | #define _DEVINFO_OPA1CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1208 | #define _DEVINFO_OPA1CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1209 | #define _DEVINFO_OPA1CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1210 | |
| Anna Bridge |
142:4eea097334d6 | 1211 | /* Bit fields for DEVINFO OPA1CAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 1212 | #define _DEVINFO_OPA1CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA1CAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 1213 | #define _DEVINFO_OPA1CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1214 | #define _DEVINFO_OPA1CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1215 | #define _DEVINFO_OPA1CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1216 | #define _DEVINFO_OPA1CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1217 | #define _DEVINFO_OPA1CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1218 | #define _DEVINFO_OPA1CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1219 | #define _DEVINFO_OPA1CAL7_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1220 | #define _DEVINFO_OPA1CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1221 | #define _DEVINFO_OPA1CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1222 | #define _DEVINFO_OPA1CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1223 | #define _DEVINFO_OPA1CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1224 | #define _DEVINFO_OPA1CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1225 | #define _DEVINFO_OPA1CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1226 | #define _DEVINFO_OPA1CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1227 | |
| Anna Bridge |
142:4eea097334d6 | 1228 | /* Bit fields for DEVINFO OPA2CAL4 */ |
| Anna Bridge |
142:4eea097334d6 | 1229 | #define _DEVINFO_OPA2CAL4_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL4 */ |
| Anna Bridge |
142:4eea097334d6 | 1230 | #define _DEVINFO_OPA2CAL4_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1231 | #define _DEVINFO_OPA2CAL4_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1232 | #define _DEVINFO_OPA2CAL4_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1233 | #define _DEVINFO_OPA2CAL4_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1234 | #define _DEVINFO_OPA2CAL4_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1235 | #define _DEVINFO_OPA2CAL4_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1236 | #define _DEVINFO_OPA2CAL4_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1237 | #define _DEVINFO_OPA2CAL4_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1238 | #define _DEVINFO_OPA2CAL4_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1239 | #define _DEVINFO_OPA2CAL4_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1240 | #define _DEVINFO_OPA2CAL4_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1241 | #define _DEVINFO_OPA2CAL4_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1242 | #define _DEVINFO_OPA2CAL4_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1243 | #define _DEVINFO_OPA2CAL4_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1244 | |
| Anna Bridge |
142:4eea097334d6 | 1245 | /* Bit fields for DEVINFO OPA2CAL5 */ |
| Anna Bridge |
142:4eea097334d6 | 1246 | #define _DEVINFO_OPA2CAL5_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL5 */ |
| Anna Bridge |
142:4eea097334d6 | 1247 | #define _DEVINFO_OPA2CAL5_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1248 | #define _DEVINFO_OPA2CAL5_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1249 | #define _DEVINFO_OPA2CAL5_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1250 | #define _DEVINFO_OPA2CAL5_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1251 | #define _DEVINFO_OPA2CAL5_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1252 | #define _DEVINFO_OPA2CAL5_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1253 | #define _DEVINFO_OPA2CAL5_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1254 | #define _DEVINFO_OPA2CAL5_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1255 | #define _DEVINFO_OPA2CAL5_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1256 | #define _DEVINFO_OPA2CAL5_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1257 | #define _DEVINFO_OPA2CAL5_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1258 | #define _DEVINFO_OPA2CAL5_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1259 | #define _DEVINFO_OPA2CAL5_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1260 | #define _DEVINFO_OPA2CAL5_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1261 | |
| Anna Bridge |
142:4eea097334d6 | 1262 | /* Bit fields for DEVINFO OPA2CAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 1263 | #define _DEVINFO_OPA2CAL6_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL6 */ |
| Anna Bridge |
142:4eea097334d6 | 1264 | #define _DEVINFO_OPA2CAL6_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1265 | #define _DEVINFO_OPA2CAL6_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1266 | #define _DEVINFO_OPA2CAL6_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1267 | #define _DEVINFO_OPA2CAL6_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1268 | #define _DEVINFO_OPA2CAL6_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1269 | #define _DEVINFO_OPA2CAL6_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1270 | #define _DEVINFO_OPA2CAL6_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1271 | #define _DEVINFO_OPA2CAL6_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1272 | #define _DEVINFO_OPA2CAL6_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1273 | #define _DEVINFO_OPA2CAL6_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1274 | #define _DEVINFO_OPA2CAL6_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1275 | #define _DEVINFO_OPA2CAL6_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1276 | #define _DEVINFO_OPA2CAL6_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1277 | #define _DEVINFO_OPA2CAL6_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1278 | |
| Anna Bridge |
142:4eea097334d6 | 1279 | /* Bit fields for DEVINFO OPA2CAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 1280 | #define _DEVINFO_OPA2CAL7_MASK 0x7DF6EDEFUL /**< Mask for DEVINFO_OPA2CAL7 */ |
| Anna Bridge |
142:4eea097334d6 | 1281 | #define _DEVINFO_OPA2CAL7_CM1_SHIFT 0 /**< Shift value for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1282 | #define _DEVINFO_OPA2CAL7_CM1_MASK 0xFUL /**< Bit mask for CM1 */ |
| Anna Bridge |
142:4eea097334d6 | 1283 | #define _DEVINFO_OPA2CAL7_CM2_SHIFT 5 /**< Shift value for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1284 | #define _DEVINFO_OPA2CAL7_CM2_MASK 0x1E0UL /**< Bit mask for CM2 */ |
| Anna Bridge |
142:4eea097334d6 | 1285 | #define _DEVINFO_OPA2CAL7_CM3_SHIFT 10 /**< Shift value for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1286 | #define _DEVINFO_OPA2CAL7_CM3_MASK 0xC00UL /**< Bit mask for CM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1287 | #define _DEVINFO_OPA2CAL7_GM_SHIFT 13 /**< Shift value for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1288 | #define _DEVINFO_OPA2CAL7_GM_MASK 0xE000UL /**< Bit mask for GM */ |
| Anna Bridge |
142:4eea097334d6 | 1289 | #define _DEVINFO_OPA2CAL7_GM3_SHIFT 17 /**< Shift value for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1290 | #define _DEVINFO_OPA2CAL7_GM3_MASK 0x60000UL /**< Bit mask for GM3 */ |
| Anna Bridge |
142:4eea097334d6 | 1291 | #define _DEVINFO_OPA2CAL7_OFFSETP_SHIFT 20 /**< Shift value for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1292 | #define _DEVINFO_OPA2CAL7_OFFSETP_MASK 0x1F00000UL /**< Bit mask for OFFSETP */ |
| Anna Bridge |
142:4eea097334d6 | 1293 | #define _DEVINFO_OPA2CAL7_OFFSETN_SHIFT 26 /**< Shift value for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1294 | #define _DEVINFO_OPA2CAL7_OFFSETN_MASK 0x7C000000UL /**< Bit mask for OFFSETN */ |
| Anna Bridge |
142:4eea097334d6 | 1295 | |
| Anna Bridge |
142:4eea097334d6 | 1296 | /** @} End of group EFR32MG12P_DEVINFO */ |
| Anna Bridge |
142:4eea097334d6 | 1297 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 1298 |
