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TARGET_TB_SENSE_1/TOOLCHAIN_ARM_STD/efr32mg1p_rtcc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
142:4eea097334d6 | 1 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 2 | * @file efr32mg1p_rtcc.h |
| Anna Bridge |
142:4eea097334d6 | 3 | * @brief EFR32MG1P_RTCC register and bit field definitions |
| Anna Bridge |
142:4eea097334d6 | 4 | * @version 5.1.2 |
| Anna Bridge |
142:4eea097334d6 | 5 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 6 | * @section License |
| Anna Bridge |
142:4eea097334d6 | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| Anna Bridge |
142:4eea097334d6 | 8 | ****************************************************************************** |
| Anna Bridge |
142:4eea097334d6 | 9 | * |
| Anna Bridge |
142:4eea097334d6 | 10 | * Permission is granted to anyone to use this software for any purpose, |
| Anna Bridge |
142:4eea097334d6 | 11 | * including commercial applications, and to alter it and redistribute it |
| Anna Bridge |
142:4eea097334d6 | 12 | * freely, subject to the following restrictions: |
| Anna Bridge |
142:4eea097334d6 | 13 | * |
| Anna Bridge |
142:4eea097334d6 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| Anna Bridge |
142:4eea097334d6 | 15 | * claim that you wrote the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| Anna Bridge |
142:4eea097334d6 | 17 | * misrepresented as being the original software.@n |
| Anna Bridge |
142:4eea097334d6 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| Anna Bridge |
142:4eea097334d6 | 19 | * |
| Anna Bridge |
142:4eea097334d6 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| Anna Bridge |
142:4eea097334d6 | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| Anna Bridge |
142:4eea097334d6 | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| Anna Bridge |
142:4eea097334d6 | 23 | * kind, including, but not limited to, any implied warranties of |
| Anna Bridge |
142:4eea097334d6 | 24 | * merchantability or fitness for any particular purpose or warranties against |
| Anna Bridge |
142:4eea097334d6 | 25 | * infringement of any proprietary rights of a third party. |
| Anna Bridge |
142:4eea097334d6 | 26 | * |
| Anna Bridge |
142:4eea097334d6 | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| Anna Bridge |
142:4eea097334d6 | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| Anna Bridge |
142:4eea097334d6 | 29 | * any third party, arising from your use of this Software. |
| Anna Bridge |
142:4eea097334d6 | 30 | * |
| Anna Bridge |
142:4eea097334d6 | 31 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 32 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 33 | * @addtogroup Parts |
| Anna Bridge |
142:4eea097334d6 | 34 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 35 | ******************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 36 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 37 | * @defgroup EFR32MG1P_RTCC |
| Anna Bridge |
142:4eea097334d6 | 38 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 39 | * @brief EFR32MG1P_RTCC Register Declaration |
| Anna Bridge |
142:4eea097334d6 | 40 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 41 | typedef struct |
| Anna Bridge |
142:4eea097334d6 | 42 | { |
| Anna Bridge |
142:4eea097334d6 | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| Anna Bridge |
142:4eea097334d6 | 44 | __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ |
| Anna Bridge |
142:4eea097334d6 | 45 | __IOM uint32_t CNT; /**< Counter Value Register */ |
| Anna Bridge |
142:4eea097334d6 | 46 | __IM uint32_t COMBCNT; /**< Combined Pre-Counter and Counter Value Register */ |
| Anna Bridge |
142:4eea097334d6 | 47 | __IOM uint32_t TIME; /**< Time of day register */ |
| Anna Bridge |
142:4eea097334d6 | 48 | __IOM uint32_t DATE; /**< Date register */ |
| Anna Bridge |
142:4eea097334d6 | 49 | __IM uint32_t IF; /**< RTCC Interrupt Flags */ |
| Anna Bridge |
142:4eea097334d6 | 50 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| Anna Bridge |
142:4eea097334d6 | 51 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| Anna Bridge |
142:4eea097334d6 | 52 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| Anna Bridge |
142:4eea097334d6 | 53 | __IM uint32_t STATUS; /**< Status register */ |
| Anna Bridge |
142:4eea097334d6 | 54 | __IOM uint32_t CMD; /**< Command Register */ |
| Anna Bridge |
142:4eea097334d6 | 55 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| Anna Bridge |
142:4eea097334d6 | 56 | __IOM uint32_t POWERDOWN; /**< Retention RAM power-down register */ |
| Anna Bridge |
142:4eea097334d6 | 57 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
| Anna Bridge |
142:4eea097334d6 | 58 | __IOM uint32_t EM4WUEN; /**< Wake Up Enable */ |
| Anna Bridge |
142:4eea097334d6 | 59 | |
| Anna Bridge |
142:4eea097334d6 | 60 | RTCC_CC_TypeDef CC[3]; /**< Capture/Compare Channel */ |
| Anna Bridge |
142:4eea097334d6 | 61 | |
| Anna Bridge |
142:4eea097334d6 | 62 | uint32_t RESERVED0[37]; /**< Reserved registers */ |
| Anna Bridge |
142:4eea097334d6 | 63 | RTCC_RET_TypeDef RET[32]; /**< RetentionReg */ |
| Anna Bridge |
142:4eea097334d6 | 64 | } RTCC_TypeDef; /** @} */ |
| Anna Bridge |
142:4eea097334d6 | 65 | |
| Anna Bridge |
142:4eea097334d6 | 66 | /**************************************************************************//** |
| Anna Bridge |
142:4eea097334d6 | 67 | * @defgroup EFR32MG1P_RTCC_BitFields |
| Anna Bridge |
142:4eea097334d6 | 68 | * @{ |
| Anna Bridge |
142:4eea097334d6 | 69 | *****************************************************************************/ |
| Anna Bridge |
142:4eea097334d6 | 70 | |
| Anna Bridge |
142:4eea097334d6 | 71 | /* Bit fields for RTCC CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 72 | #define _RTCC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 73 | #define _RTCC_CTRL_MASK 0x00039F35UL /**< Mask for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 74 | #define RTCC_CTRL_ENABLE (0x1UL << 0) /**< RTCC Enable */ |
| Anna Bridge |
142:4eea097334d6 | 75 | #define _RTCC_CTRL_ENABLE_SHIFT 0 /**< Shift value for RTCC_ENABLE */ |
| Anna Bridge |
142:4eea097334d6 | 76 | #define _RTCC_CTRL_ENABLE_MASK 0x1UL /**< Bit mask for RTCC_ENABLE */ |
| Anna Bridge |
142:4eea097334d6 | 77 | #define _RTCC_CTRL_ENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 78 | #define RTCC_CTRL_ENABLE_DEFAULT (_RTCC_CTRL_ENABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 79 | #define RTCC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ |
| Anna Bridge |
142:4eea097334d6 | 80 | #define _RTCC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for RTCC_DEBUGRUN */ |
| Anna Bridge |
142:4eea097334d6 | 81 | #define _RTCC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for RTCC_DEBUGRUN */ |
| Anna Bridge |
142:4eea097334d6 | 82 | #define _RTCC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 83 | #define RTCC_CTRL_DEBUGRUN_DEFAULT (_RTCC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 84 | #define RTCC_CTRL_PRECCV0TOP (0x1UL << 4) /**< Pre-counter CCV0 top value enable. */ |
| Anna Bridge |
142:4eea097334d6 | 85 | #define _RTCC_CTRL_PRECCV0TOP_SHIFT 4 /**< Shift value for RTCC_PRECCV0TOP */ |
| Anna Bridge |
142:4eea097334d6 | 86 | #define _RTCC_CTRL_PRECCV0TOP_MASK 0x10UL /**< Bit mask for RTCC_PRECCV0TOP */ |
| Anna Bridge |
142:4eea097334d6 | 87 | #define _RTCC_CTRL_PRECCV0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 88 | #define RTCC_CTRL_PRECCV0TOP_DEFAULT (_RTCC_CTRL_PRECCV0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 89 | #define RTCC_CTRL_CCV1TOP (0x1UL << 5) /**< CCV1 top value enable */ |
| Anna Bridge |
142:4eea097334d6 | 90 | #define _RTCC_CTRL_CCV1TOP_SHIFT 5 /**< Shift value for RTCC_CCV1TOP */ |
| Anna Bridge |
142:4eea097334d6 | 91 | #define _RTCC_CTRL_CCV1TOP_MASK 0x20UL /**< Bit mask for RTCC_CCV1TOP */ |
| Anna Bridge |
142:4eea097334d6 | 92 | #define _RTCC_CTRL_CCV1TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 93 | #define RTCC_CTRL_CCV1TOP_DEFAULT (_RTCC_CTRL_CCV1TOP_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 94 | #define _RTCC_CTRL_CNTPRESC_SHIFT 8 /**< Shift value for RTCC_CNTPRESC */ |
| Anna Bridge |
142:4eea097334d6 | 95 | #define _RTCC_CTRL_CNTPRESC_MASK 0xF00UL /**< Bit mask for RTCC_CNTPRESC */ |
| Anna Bridge |
142:4eea097334d6 | 96 | #define _RTCC_CTRL_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 97 | #define _RTCC_CTRL_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 98 | #define _RTCC_CTRL_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 99 | #define _RTCC_CTRL_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 100 | #define _RTCC_CTRL_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 101 | #define _RTCC_CTRL_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 102 | #define _RTCC_CTRL_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 103 | #define _RTCC_CTRL_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 104 | #define _RTCC_CTRL_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 105 | #define _RTCC_CTRL_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 106 | #define _RTCC_CTRL_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 107 | #define _RTCC_CTRL_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 108 | #define _RTCC_CTRL_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 109 | #define _RTCC_CTRL_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 110 | #define _RTCC_CTRL_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 111 | #define _RTCC_CTRL_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 112 | #define _RTCC_CTRL_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 113 | #define RTCC_CTRL_CNTPRESC_DEFAULT (_RTCC_CTRL_CNTPRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 114 | #define RTCC_CTRL_CNTPRESC_DIV1 (_RTCC_CTRL_CNTPRESC_DIV1 << 8) /**< Shifted mode DIV1 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 115 | #define RTCC_CTRL_CNTPRESC_DIV2 (_RTCC_CTRL_CNTPRESC_DIV2 << 8) /**< Shifted mode DIV2 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 116 | #define RTCC_CTRL_CNTPRESC_DIV4 (_RTCC_CTRL_CNTPRESC_DIV4 << 8) /**< Shifted mode DIV4 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 117 | #define RTCC_CTRL_CNTPRESC_DIV8 (_RTCC_CTRL_CNTPRESC_DIV8 << 8) /**< Shifted mode DIV8 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 118 | #define RTCC_CTRL_CNTPRESC_DIV16 (_RTCC_CTRL_CNTPRESC_DIV16 << 8) /**< Shifted mode DIV16 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 119 | #define RTCC_CTRL_CNTPRESC_DIV32 (_RTCC_CTRL_CNTPRESC_DIV32 << 8) /**< Shifted mode DIV32 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 120 | #define RTCC_CTRL_CNTPRESC_DIV64 (_RTCC_CTRL_CNTPRESC_DIV64 << 8) /**< Shifted mode DIV64 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 121 | #define RTCC_CTRL_CNTPRESC_DIV128 (_RTCC_CTRL_CNTPRESC_DIV128 << 8) /**< Shifted mode DIV128 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 122 | #define RTCC_CTRL_CNTPRESC_DIV256 (_RTCC_CTRL_CNTPRESC_DIV256 << 8) /**< Shifted mode DIV256 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 123 | #define RTCC_CTRL_CNTPRESC_DIV512 (_RTCC_CTRL_CNTPRESC_DIV512 << 8) /**< Shifted mode DIV512 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 124 | #define RTCC_CTRL_CNTPRESC_DIV1024 (_RTCC_CTRL_CNTPRESC_DIV1024 << 8) /**< Shifted mode DIV1024 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 125 | #define RTCC_CTRL_CNTPRESC_DIV2048 (_RTCC_CTRL_CNTPRESC_DIV2048 << 8) /**< Shifted mode DIV2048 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 126 | #define RTCC_CTRL_CNTPRESC_DIV4096 (_RTCC_CTRL_CNTPRESC_DIV4096 << 8) /**< Shifted mode DIV4096 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 127 | #define RTCC_CTRL_CNTPRESC_DIV8192 (_RTCC_CTRL_CNTPRESC_DIV8192 << 8) /**< Shifted mode DIV8192 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 128 | #define RTCC_CTRL_CNTPRESC_DIV16384 (_RTCC_CTRL_CNTPRESC_DIV16384 << 8) /**< Shifted mode DIV16384 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 129 | #define RTCC_CTRL_CNTPRESC_DIV32768 (_RTCC_CTRL_CNTPRESC_DIV32768 << 8) /**< Shifted mode DIV32768 for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 130 | #define RTCC_CTRL_CNTTICK (0x1UL << 12) /**< Counter prescaler mode. */ |
| Anna Bridge |
142:4eea097334d6 | 131 | #define _RTCC_CTRL_CNTTICK_SHIFT 12 /**< Shift value for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 132 | #define _RTCC_CTRL_CNTTICK_MASK 0x1000UL /**< Bit mask for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 133 | #define _RTCC_CTRL_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 134 | #define _RTCC_CTRL_CNTTICK_PRESC 0x00000000UL /**< Mode PRESC for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 135 | #define _RTCC_CTRL_CNTTICK_CCV0MATCH 0x00000001UL /**< Mode CCV0MATCH for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 136 | #define RTCC_CTRL_CNTTICK_DEFAULT (_RTCC_CTRL_CNTTICK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 137 | #define RTCC_CTRL_CNTTICK_PRESC (_RTCC_CTRL_CNTTICK_PRESC << 12) /**< Shifted mode PRESC for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 138 | #define RTCC_CTRL_CNTTICK_CCV0MATCH (_RTCC_CTRL_CNTTICK_CCV0MATCH << 12) /**< Shifted mode CCV0MATCH for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 139 | #define RTCC_CTRL_OSCFDETEN (0x1UL << 15) /**< Oscillator failure detection enable */ |
| Anna Bridge |
142:4eea097334d6 | 140 | #define _RTCC_CTRL_OSCFDETEN_SHIFT 15 /**< Shift value for RTCC_OSCFDETEN */ |
| Anna Bridge |
142:4eea097334d6 | 141 | #define _RTCC_CTRL_OSCFDETEN_MASK 0x8000UL /**< Bit mask for RTCC_OSCFDETEN */ |
| Anna Bridge |
142:4eea097334d6 | 142 | #define _RTCC_CTRL_OSCFDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 143 | #define RTCC_CTRL_OSCFDETEN_DEFAULT (_RTCC_CTRL_OSCFDETEN_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 144 | #define RTCC_CTRL_CNTMODE (0x1UL << 16) /**< Main counter mode */ |
| Anna Bridge |
142:4eea097334d6 | 145 | #define _RTCC_CTRL_CNTMODE_SHIFT 16 /**< Shift value for RTCC_CNTMODE */ |
| Anna Bridge |
142:4eea097334d6 | 146 | #define _RTCC_CTRL_CNTMODE_MASK 0x10000UL /**< Bit mask for RTCC_CNTMODE */ |
| Anna Bridge |
142:4eea097334d6 | 147 | #define _RTCC_CTRL_CNTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 148 | #define _RTCC_CTRL_CNTMODE_NORMAL 0x00000000UL /**< Mode NORMAL for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 149 | #define _RTCC_CTRL_CNTMODE_CALENDAR 0x00000001UL /**< Mode CALENDAR for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 150 | #define RTCC_CTRL_CNTMODE_DEFAULT (_RTCC_CTRL_CNTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 151 | #define RTCC_CTRL_CNTMODE_NORMAL (_RTCC_CTRL_CNTMODE_NORMAL << 16) /**< Shifted mode NORMAL for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 152 | #define RTCC_CTRL_CNTMODE_CALENDAR (_RTCC_CTRL_CNTMODE_CALENDAR << 16) /**< Shifted mode CALENDAR for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 153 | #define RTCC_CTRL_LYEARCORRDIS (0x1UL << 17) /**< Leap year correction disabled. */ |
| Anna Bridge |
142:4eea097334d6 | 154 | #define _RTCC_CTRL_LYEARCORRDIS_SHIFT 17 /**< Shift value for RTCC_LYEARCORRDIS */ |
| Anna Bridge |
142:4eea097334d6 | 155 | #define _RTCC_CTRL_LYEARCORRDIS_MASK 0x20000UL /**< Bit mask for RTCC_LYEARCORRDIS */ |
| Anna Bridge |
142:4eea097334d6 | 156 | #define _RTCC_CTRL_LYEARCORRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 157 | #define RTCC_CTRL_LYEARCORRDIS_DEFAULT (_RTCC_CTRL_LYEARCORRDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 158 | |
| Anna Bridge |
142:4eea097334d6 | 159 | /* Bit fields for RTCC PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 160 | #define _RTCC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 161 | #define _RTCC_PRECNT_MASK 0x00007FFFUL /**< Mask for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 162 | #define _RTCC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 163 | #define _RTCC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 164 | #define _RTCC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 165 | #define RTCC_PRECNT_PRECNT_DEFAULT (_RTCC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 166 | |
| Anna Bridge |
142:4eea097334d6 | 167 | /* Bit fields for RTCC CNT */ |
| Anna Bridge |
142:4eea097334d6 | 168 | #define _RTCC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_CNT */ |
| Anna Bridge |
142:4eea097334d6 | 169 | #define _RTCC_CNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CNT */ |
| Anna Bridge |
142:4eea097334d6 | 170 | #define _RTCC_CNT_CNT_SHIFT 0 /**< Shift value for RTCC_CNT */ |
| Anna Bridge |
142:4eea097334d6 | 171 | #define _RTCC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for RTCC_CNT */ |
| Anna Bridge |
142:4eea097334d6 | 172 | #define _RTCC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CNT */ |
| Anna Bridge |
142:4eea097334d6 | 173 | #define RTCC_CNT_CNT_DEFAULT (_RTCC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CNT */ |
| Anna Bridge |
142:4eea097334d6 | 174 | |
| Anna Bridge |
142:4eea097334d6 | 175 | /* Bit fields for RTCC COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 176 | #define _RTCC_COMBCNT_RESETVALUE 0x00000000UL /**< Default value for RTCC_COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 177 | #define _RTCC_COMBCNT_MASK 0xFFFFFFFFUL /**< Mask for RTCC_COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 178 | #define _RTCC_COMBCNT_PRECNT_SHIFT 0 /**< Shift value for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 179 | #define _RTCC_COMBCNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for RTCC_PRECNT */ |
| Anna Bridge |
142:4eea097334d6 | 180 | #define _RTCC_COMBCNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 181 | #define RTCC_COMBCNT_PRECNT_DEFAULT (_RTCC_COMBCNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 182 | #define _RTCC_COMBCNT_CNTLSB_SHIFT 15 /**< Shift value for RTCC_CNTLSB */ |
| Anna Bridge |
142:4eea097334d6 | 183 | #define _RTCC_COMBCNT_CNTLSB_MASK 0xFFFF8000UL /**< Bit mask for RTCC_CNTLSB */ |
| Anna Bridge |
142:4eea097334d6 | 184 | #define _RTCC_COMBCNT_CNTLSB_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 185 | #define RTCC_COMBCNT_CNTLSB_DEFAULT (_RTCC_COMBCNT_CNTLSB_DEFAULT << 15) /**< Shifted mode DEFAULT for RTCC_COMBCNT */ |
| Anna Bridge |
142:4eea097334d6 | 186 | |
| Anna Bridge |
142:4eea097334d6 | 187 | /* Bit fields for RTCC TIME */ |
| Anna Bridge |
142:4eea097334d6 | 188 | #define _RTCC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 189 | #define _RTCC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 190 | #define _RTCC_TIME_SECU_SHIFT 0 /**< Shift value for RTCC_SECU */ |
| Anna Bridge |
142:4eea097334d6 | 191 | #define _RTCC_TIME_SECU_MASK 0xFUL /**< Bit mask for RTCC_SECU */ |
| Anna Bridge |
142:4eea097334d6 | 192 | #define _RTCC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 193 | #define RTCC_TIME_SECU_DEFAULT (_RTCC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 194 | #define _RTCC_TIME_SECT_SHIFT 4 /**< Shift value for RTCC_SECT */ |
| Anna Bridge |
142:4eea097334d6 | 195 | #define _RTCC_TIME_SECT_MASK 0x70UL /**< Bit mask for RTCC_SECT */ |
| Anna Bridge |
142:4eea097334d6 | 196 | #define _RTCC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 197 | #define RTCC_TIME_SECT_DEFAULT (_RTCC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 198 | #define _RTCC_TIME_MINU_SHIFT 8 /**< Shift value for RTCC_MINU */ |
| Anna Bridge |
142:4eea097334d6 | 199 | #define _RTCC_TIME_MINU_MASK 0xF00UL /**< Bit mask for RTCC_MINU */ |
| Anna Bridge |
142:4eea097334d6 | 200 | #define _RTCC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 201 | #define RTCC_TIME_MINU_DEFAULT (_RTCC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 202 | #define _RTCC_TIME_MINT_SHIFT 12 /**< Shift value for RTCC_MINT */ |
| Anna Bridge |
142:4eea097334d6 | 203 | #define _RTCC_TIME_MINT_MASK 0x7000UL /**< Bit mask for RTCC_MINT */ |
| Anna Bridge |
142:4eea097334d6 | 204 | #define _RTCC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 205 | #define RTCC_TIME_MINT_DEFAULT (_RTCC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 206 | #define _RTCC_TIME_HOURU_SHIFT 16 /**< Shift value for RTCC_HOURU */ |
| Anna Bridge |
142:4eea097334d6 | 207 | #define _RTCC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for RTCC_HOURU */ |
| Anna Bridge |
142:4eea097334d6 | 208 | #define _RTCC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 209 | #define RTCC_TIME_HOURU_DEFAULT (_RTCC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 210 | #define _RTCC_TIME_HOURT_SHIFT 20 /**< Shift value for RTCC_HOURT */ |
| Anna Bridge |
142:4eea097334d6 | 211 | #define _RTCC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for RTCC_HOURT */ |
| Anna Bridge |
142:4eea097334d6 | 212 | #define _RTCC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 213 | #define RTCC_TIME_HOURT_DEFAULT (_RTCC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 214 | |
| Anna Bridge |
142:4eea097334d6 | 215 | /* Bit fields for RTCC DATE */ |
| Anna Bridge |
142:4eea097334d6 | 216 | #define _RTCC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 217 | #define _RTCC_DATE_MASK 0x07FF1F3FUL /**< Mask for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 218 | #define _RTCC_DATE_DAYOMU_SHIFT 0 /**< Shift value for RTCC_DAYOMU */ |
| Anna Bridge |
142:4eea097334d6 | 219 | #define _RTCC_DATE_DAYOMU_MASK 0xFUL /**< Bit mask for RTCC_DAYOMU */ |
| Anna Bridge |
142:4eea097334d6 | 220 | #define _RTCC_DATE_DAYOMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 221 | #define RTCC_DATE_DAYOMU_DEFAULT (_RTCC_DATE_DAYOMU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 222 | #define _RTCC_DATE_DAYOMT_SHIFT 4 /**< Shift value for RTCC_DAYOMT */ |
| Anna Bridge |
142:4eea097334d6 | 223 | #define _RTCC_DATE_DAYOMT_MASK 0x30UL /**< Bit mask for RTCC_DAYOMT */ |
| Anna Bridge |
142:4eea097334d6 | 224 | #define _RTCC_DATE_DAYOMT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 225 | #define RTCC_DATE_DAYOMT_DEFAULT (_RTCC_DATE_DAYOMT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 226 | #define _RTCC_DATE_MONTHU_SHIFT 8 /**< Shift value for RTCC_MONTHU */ |
| Anna Bridge |
142:4eea097334d6 | 227 | #define _RTCC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for RTCC_MONTHU */ |
| Anna Bridge |
142:4eea097334d6 | 228 | #define _RTCC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 229 | #define RTCC_DATE_MONTHU_DEFAULT (_RTCC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 230 | #define RTCC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ |
| Anna Bridge |
142:4eea097334d6 | 231 | #define _RTCC_DATE_MONTHT_SHIFT 12 /**< Shift value for RTCC_MONTHT */ |
| Anna Bridge |
142:4eea097334d6 | 232 | #define _RTCC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for RTCC_MONTHT */ |
| Anna Bridge |
142:4eea097334d6 | 233 | #define _RTCC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 234 | #define RTCC_DATE_MONTHT_DEFAULT (_RTCC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 235 | #define _RTCC_DATE_YEARU_SHIFT 16 /**< Shift value for RTCC_YEARU */ |
| Anna Bridge |
142:4eea097334d6 | 236 | #define _RTCC_DATE_YEARU_MASK 0xF0000UL /**< Bit mask for RTCC_YEARU */ |
| Anna Bridge |
142:4eea097334d6 | 237 | #define _RTCC_DATE_YEARU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 238 | #define RTCC_DATE_YEARU_DEFAULT (_RTCC_DATE_YEARU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 239 | #define _RTCC_DATE_YEART_SHIFT 20 /**< Shift value for RTCC_YEART */ |
| Anna Bridge |
142:4eea097334d6 | 240 | #define _RTCC_DATE_YEART_MASK 0xF00000UL /**< Bit mask for RTCC_YEART */ |
| Anna Bridge |
142:4eea097334d6 | 241 | #define _RTCC_DATE_YEART_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 242 | #define RTCC_DATE_YEART_DEFAULT (_RTCC_DATE_YEART_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 243 | #define _RTCC_DATE_DAYOW_SHIFT 24 /**< Shift value for RTCC_DAYOW */ |
| Anna Bridge |
142:4eea097334d6 | 244 | #define _RTCC_DATE_DAYOW_MASK 0x7000000UL /**< Bit mask for RTCC_DAYOW */ |
| Anna Bridge |
142:4eea097334d6 | 245 | #define _RTCC_DATE_DAYOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 246 | #define RTCC_DATE_DAYOW_DEFAULT (_RTCC_DATE_DAYOW_DEFAULT << 24) /**< Shifted mode DEFAULT for RTCC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 247 | |
| Anna Bridge |
142:4eea097334d6 | 248 | /* Bit fields for RTCC IF */ |
| Anna Bridge |
142:4eea097334d6 | 249 | #define _RTCC_IF_RESETVALUE 0x00000000UL /**< Default value for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 250 | #define _RTCC_IF_MASK 0x000007FFUL /**< Mask for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 251 | #define RTCC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 252 | #define _RTCC_IF_OF_SHIFT 0 /**< Shift value for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 253 | #define _RTCC_IF_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 254 | #define _RTCC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 255 | #define RTCC_IF_OF_DEFAULT (_RTCC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 256 | #define RTCC_IF_CC0 (0x1UL << 1) /**< Channel 0 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 257 | #define _RTCC_IF_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 258 | #define _RTCC_IF_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 259 | #define _RTCC_IF_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 260 | #define RTCC_IF_CC0_DEFAULT (_RTCC_IF_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 261 | #define RTCC_IF_CC1 (0x1UL << 2) /**< Channel 1 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 262 | #define _RTCC_IF_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 263 | #define _RTCC_IF_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 264 | #define _RTCC_IF_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 265 | #define RTCC_IF_CC1_DEFAULT (_RTCC_IF_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 266 | #define RTCC_IF_CC2 (0x1UL << 3) /**< Channel 2 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 267 | #define _RTCC_IF_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 268 | #define _RTCC_IF_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 269 | #define _RTCC_IF_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 270 | #define RTCC_IF_CC2_DEFAULT (_RTCC_IF_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 271 | #define RTCC_IF_OSCFAIL (0x1UL << 4) /**< Oscillator failure Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 272 | #define _RTCC_IF_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 273 | #define _RTCC_IF_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 274 | #define _RTCC_IF_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 275 | #define RTCC_IF_OSCFAIL_DEFAULT (_RTCC_IF_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 276 | #define RTCC_IF_CNTTICK (0x1UL << 5) /**< Main counter tick */ |
| Anna Bridge |
142:4eea097334d6 | 277 | #define _RTCC_IF_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 278 | #define _RTCC_IF_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 279 | #define _RTCC_IF_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 280 | #define RTCC_IF_CNTTICK_DEFAULT (_RTCC_IF_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 281 | #define RTCC_IF_MINTICK (0x1UL << 6) /**< Minute tick */ |
| Anna Bridge |
142:4eea097334d6 | 282 | #define _RTCC_IF_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 283 | #define _RTCC_IF_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 284 | #define _RTCC_IF_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 285 | #define RTCC_IF_MINTICK_DEFAULT (_RTCC_IF_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 286 | #define RTCC_IF_HOURTICK (0x1UL << 7) /**< Hour tick */ |
| Anna Bridge |
142:4eea097334d6 | 287 | #define _RTCC_IF_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 288 | #define _RTCC_IF_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 289 | #define _RTCC_IF_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 290 | #define RTCC_IF_HOURTICK_DEFAULT (_RTCC_IF_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 291 | #define RTCC_IF_DAYTICK (0x1UL << 8) /**< Day tick */ |
| Anna Bridge |
142:4eea097334d6 | 292 | #define _RTCC_IF_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 293 | #define _RTCC_IF_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 294 | #define _RTCC_IF_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 295 | #define RTCC_IF_DAYTICK_DEFAULT (_RTCC_IF_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 296 | #define RTCC_IF_DAYOWOF (0x1UL << 9) /**< Day of week overflow */ |
| Anna Bridge |
142:4eea097334d6 | 297 | #define _RTCC_IF_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 298 | #define _RTCC_IF_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 299 | #define _RTCC_IF_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 300 | #define RTCC_IF_DAYOWOF_DEFAULT (_RTCC_IF_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 301 | #define RTCC_IF_MONTHTICK (0x1UL << 10) /**< Month tick */ |
| Anna Bridge |
142:4eea097334d6 | 302 | #define _RTCC_IF_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 303 | #define _RTCC_IF_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 304 | #define _RTCC_IF_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 305 | #define RTCC_IF_MONTHTICK_DEFAULT (_RTCC_IF_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IF */ |
| Anna Bridge |
142:4eea097334d6 | 306 | |
| Anna Bridge |
142:4eea097334d6 | 307 | /* Bit fields for RTCC IFS */ |
| Anna Bridge |
142:4eea097334d6 | 308 | #define _RTCC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 309 | #define _RTCC_IFS_MASK 0x000007FFUL /**< Mask for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 310 | #define RTCC_IFS_OF (0x1UL << 0) /**< Set OF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 311 | #define _RTCC_IFS_OF_SHIFT 0 /**< Shift value for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 312 | #define _RTCC_IFS_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 313 | #define _RTCC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 314 | #define RTCC_IFS_OF_DEFAULT (_RTCC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 315 | #define RTCC_IFS_CC0 (0x1UL << 1) /**< Set CC0 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 316 | #define _RTCC_IFS_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 317 | #define _RTCC_IFS_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 318 | #define _RTCC_IFS_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 319 | #define RTCC_IFS_CC0_DEFAULT (_RTCC_IFS_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 320 | #define RTCC_IFS_CC1 (0x1UL << 2) /**< Set CC1 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 321 | #define _RTCC_IFS_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 322 | #define _RTCC_IFS_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 323 | #define _RTCC_IFS_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 324 | #define RTCC_IFS_CC1_DEFAULT (_RTCC_IFS_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 325 | #define RTCC_IFS_CC2 (0x1UL << 3) /**< Set CC2 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 326 | #define _RTCC_IFS_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 327 | #define _RTCC_IFS_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 328 | #define _RTCC_IFS_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 329 | #define RTCC_IFS_CC2_DEFAULT (_RTCC_IFS_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 330 | #define RTCC_IFS_OSCFAIL (0x1UL << 4) /**< Set OSCFAIL Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 331 | #define _RTCC_IFS_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 332 | #define _RTCC_IFS_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 333 | #define _RTCC_IFS_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 334 | #define RTCC_IFS_OSCFAIL_DEFAULT (_RTCC_IFS_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 335 | #define RTCC_IFS_CNTTICK (0x1UL << 5) /**< Set CNTTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 336 | #define _RTCC_IFS_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 337 | #define _RTCC_IFS_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 338 | #define _RTCC_IFS_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 339 | #define RTCC_IFS_CNTTICK_DEFAULT (_RTCC_IFS_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 340 | #define RTCC_IFS_MINTICK (0x1UL << 6) /**< Set MINTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 341 | #define _RTCC_IFS_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 342 | #define _RTCC_IFS_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 343 | #define _RTCC_IFS_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 344 | #define RTCC_IFS_MINTICK_DEFAULT (_RTCC_IFS_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 345 | #define RTCC_IFS_HOURTICK (0x1UL << 7) /**< Set HOURTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 346 | #define _RTCC_IFS_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 347 | #define _RTCC_IFS_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 348 | #define _RTCC_IFS_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 349 | #define RTCC_IFS_HOURTICK_DEFAULT (_RTCC_IFS_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 350 | #define RTCC_IFS_DAYTICK (0x1UL << 8) /**< Set DAYTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 351 | #define _RTCC_IFS_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 352 | #define _RTCC_IFS_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 353 | #define _RTCC_IFS_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 354 | #define RTCC_IFS_DAYTICK_DEFAULT (_RTCC_IFS_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 355 | #define RTCC_IFS_DAYOWOF (0x1UL << 9) /**< Set DAYOWOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 356 | #define _RTCC_IFS_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 357 | #define _RTCC_IFS_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 358 | #define _RTCC_IFS_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 359 | #define RTCC_IFS_DAYOWOF_DEFAULT (_RTCC_IFS_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 360 | #define RTCC_IFS_MONTHTICK (0x1UL << 10) /**< Set MONTHTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 361 | #define _RTCC_IFS_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 362 | #define _RTCC_IFS_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 363 | #define _RTCC_IFS_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 364 | #define RTCC_IFS_MONTHTICK_DEFAULT (_RTCC_IFS_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFS */ |
| Anna Bridge |
142:4eea097334d6 | 365 | |
| Anna Bridge |
142:4eea097334d6 | 366 | /* Bit fields for RTCC IFC */ |
| Anna Bridge |
142:4eea097334d6 | 367 | #define _RTCC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 368 | #define _RTCC_IFC_MASK 0x000007FFUL /**< Mask for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 369 | #define RTCC_IFC_OF (0x1UL << 0) /**< Clear OF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 370 | #define _RTCC_IFC_OF_SHIFT 0 /**< Shift value for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 371 | #define _RTCC_IFC_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 372 | #define _RTCC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 373 | #define RTCC_IFC_OF_DEFAULT (_RTCC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 374 | #define RTCC_IFC_CC0 (0x1UL << 1) /**< Clear CC0 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 375 | #define _RTCC_IFC_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 376 | #define _RTCC_IFC_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 377 | #define _RTCC_IFC_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 378 | #define RTCC_IFC_CC0_DEFAULT (_RTCC_IFC_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 379 | #define RTCC_IFC_CC1 (0x1UL << 2) /**< Clear CC1 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 380 | #define _RTCC_IFC_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 381 | #define _RTCC_IFC_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 382 | #define _RTCC_IFC_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 383 | #define RTCC_IFC_CC1_DEFAULT (_RTCC_IFC_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 384 | #define RTCC_IFC_CC2 (0x1UL << 3) /**< Clear CC2 Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 385 | #define _RTCC_IFC_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 386 | #define _RTCC_IFC_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 387 | #define _RTCC_IFC_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 388 | #define RTCC_IFC_CC2_DEFAULT (_RTCC_IFC_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 389 | #define RTCC_IFC_OSCFAIL (0x1UL << 4) /**< Clear OSCFAIL Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 390 | #define _RTCC_IFC_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 391 | #define _RTCC_IFC_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 392 | #define _RTCC_IFC_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 393 | #define RTCC_IFC_OSCFAIL_DEFAULT (_RTCC_IFC_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 394 | #define RTCC_IFC_CNTTICK (0x1UL << 5) /**< Clear CNTTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 395 | #define _RTCC_IFC_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 396 | #define _RTCC_IFC_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 397 | #define _RTCC_IFC_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 398 | #define RTCC_IFC_CNTTICK_DEFAULT (_RTCC_IFC_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 399 | #define RTCC_IFC_MINTICK (0x1UL << 6) /**< Clear MINTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 400 | #define _RTCC_IFC_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 401 | #define _RTCC_IFC_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 402 | #define _RTCC_IFC_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 403 | #define RTCC_IFC_MINTICK_DEFAULT (_RTCC_IFC_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 404 | #define RTCC_IFC_HOURTICK (0x1UL << 7) /**< Clear HOURTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 405 | #define _RTCC_IFC_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 406 | #define _RTCC_IFC_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 407 | #define _RTCC_IFC_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 408 | #define RTCC_IFC_HOURTICK_DEFAULT (_RTCC_IFC_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 409 | #define RTCC_IFC_DAYTICK (0x1UL << 8) /**< Clear DAYTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 410 | #define _RTCC_IFC_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 411 | #define _RTCC_IFC_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 412 | #define _RTCC_IFC_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 413 | #define RTCC_IFC_DAYTICK_DEFAULT (_RTCC_IFC_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 414 | #define RTCC_IFC_DAYOWOF (0x1UL << 9) /**< Clear DAYOWOF Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 415 | #define _RTCC_IFC_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 416 | #define _RTCC_IFC_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 417 | #define _RTCC_IFC_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 418 | #define RTCC_IFC_DAYOWOF_DEFAULT (_RTCC_IFC_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 419 | #define RTCC_IFC_MONTHTICK (0x1UL << 10) /**< Clear MONTHTICK Interrupt Flag */ |
| Anna Bridge |
142:4eea097334d6 | 420 | #define _RTCC_IFC_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 421 | #define _RTCC_IFC_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 422 | #define _RTCC_IFC_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 423 | #define RTCC_IFC_MONTHTICK_DEFAULT (_RTCC_IFC_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IFC */ |
| Anna Bridge |
142:4eea097334d6 | 424 | |
| Anna Bridge |
142:4eea097334d6 | 425 | /* Bit fields for RTCC IEN */ |
| Anna Bridge |
142:4eea097334d6 | 426 | #define _RTCC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 427 | #define _RTCC_IEN_MASK 0x000007FFUL /**< Mask for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 428 | #define RTCC_IEN_OF (0x1UL << 0) /**< OF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 429 | #define _RTCC_IEN_OF_SHIFT 0 /**< Shift value for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 430 | #define _RTCC_IEN_OF_MASK 0x1UL /**< Bit mask for RTCC_OF */ |
| Anna Bridge |
142:4eea097334d6 | 431 | #define _RTCC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 432 | #define RTCC_IEN_OF_DEFAULT (_RTCC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 433 | #define RTCC_IEN_CC0 (0x1UL << 1) /**< CC0 Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 434 | #define _RTCC_IEN_CC0_SHIFT 1 /**< Shift value for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 435 | #define _RTCC_IEN_CC0_MASK 0x2UL /**< Bit mask for RTCC_CC0 */ |
| Anna Bridge |
142:4eea097334d6 | 436 | #define _RTCC_IEN_CC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 437 | #define RTCC_IEN_CC0_DEFAULT (_RTCC_IEN_CC0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 438 | #define RTCC_IEN_CC1 (0x1UL << 2) /**< CC1 Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 439 | #define _RTCC_IEN_CC1_SHIFT 2 /**< Shift value for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 440 | #define _RTCC_IEN_CC1_MASK 0x4UL /**< Bit mask for RTCC_CC1 */ |
| Anna Bridge |
142:4eea097334d6 | 441 | #define _RTCC_IEN_CC1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 442 | #define RTCC_IEN_CC1_DEFAULT (_RTCC_IEN_CC1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 443 | #define RTCC_IEN_CC2 (0x1UL << 3) /**< CC2 Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 444 | #define _RTCC_IEN_CC2_SHIFT 3 /**< Shift value for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 445 | #define _RTCC_IEN_CC2_MASK 0x8UL /**< Bit mask for RTCC_CC2 */ |
| Anna Bridge |
142:4eea097334d6 | 446 | #define _RTCC_IEN_CC2_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 447 | #define RTCC_IEN_CC2_DEFAULT (_RTCC_IEN_CC2_DEFAULT << 3) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 448 | #define RTCC_IEN_OSCFAIL (0x1UL << 4) /**< OSCFAIL Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 449 | #define _RTCC_IEN_OSCFAIL_SHIFT 4 /**< Shift value for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 450 | #define _RTCC_IEN_OSCFAIL_MASK 0x10UL /**< Bit mask for RTCC_OSCFAIL */ |
| Anna Bridge |
142:4eea097334d6 | 451 | #define _RTCC_IEN_OSCFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 452 | #define RTCC_IEN_OSCFAIL_DEFAULT (_RTCC_IEN_OSCFAIL_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 453 | #define RTCC_IEN_CNTTICK (0x1UL << 5) /**< CNTTICK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 454 | #define _RTCC_IEN_CNTTICK_SHIFT 5 /**< Shift value for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 455 | #define _RTCC_IEN_CNTTICK_MASK 0x20UL /**< Bit mask for RTCC_CNTTICK */ |
| Anna Bridge |
142:4eea097334d6 | 456 | #define _RTCC_IEN_CNTTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 457 | #define RTCC_IEN_CNTTICK_DEFAULT (_RTCC_IEN_CNTTICK_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 458 | #define RTCC_IEN_MINTICK (0x1UL << 6) /**< MINTICK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 459 | #define _RTCC_IEN_MINTICK_SHIFT 6 /**< Shift value for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 460 | #define _RTCC_IEN_MINTICK_MASK 0x40UL /**< Bit mask for RTCC_MINTICK */ |
| Anna Bridge |
142:4eea097334d6 | 461 | #define _RTCC_IEN_MINTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 462 | #define RTCC_IEN_MINTICK_DEFAULT (_RTCC_IEN_MINTICK_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 463 | #define RTCC_IEN_HOURTICK (0x1UL << 7) /**< HOURTICK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 464 | #define _RTCC_IEN_HOURTICK_SHIFT 7 /**< Shift value for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 465 | #define _RTCC_IEN_HOURTICK_MASK 0x80UL /**< Bit mask for RTCC_HOURTICK */ |
| Anna Bridge |
142:4eea097334d6 | 466 | #define _RTCC_IEN_HOURTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 467 | #define RTCC_IEN_HOURTICK_DEFAULT (_RTCC_IEN_HOURTICK_DEFAULT << 7) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 468 | #define RTCC_IEN_DAYTICK (0x1UL << 8) /**< DAYTICK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 469 | #define _RTCC_IEN_DAYTICK_SHIFT 8 /**< Shift value for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 470 | #define _RTCC_IEN_DAYTICK_MASK 0x100UL /**< Bit mask for RTCC_DAYTICK */ |
| Anna Bridge |
142:4eea097334d6 | 471 | #define _RTCC_IEN_DAYTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 472 | #define RTCC_IEN_DAYTICK_DEFAULT (_RTCC_IEN_DAYTICK_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 473 | #define RTCC_IEN_DAYOWOF (0x1UL << 9) /**< DAYOWOF Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 474 | #define _RTCC_IEN_DAYOWOF_SHIFT 9 /**< Shift value for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 475 | #define _RTCC_IEN_DAYOWOF_MASK 0x200UL /**< Bit mask for RTCC_DAYOWOF */ |
| Anna Bridge |
142:4eea097334d6 | 476 | #define _RTCC_IEN_DAYOWOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 477 | #define RTCC_IEN_DAYOWOF_DEFAULT (_RTCC_IEN_DAYOWOF_DEFAULT << 9) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 478 | #define RTCC_IEN_MONTHTICK (0x1UL << 10) /**< MONTHTICK Interrupt Enable */ |
| Anna Bridge |
142:4eea097334d6 | 479 | #define _RTCC_IEN_MONTHTICK_SHIFT 10 /**< Shift value for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 480 | #define _RTCC_IEN_MONTHTICK_MASK 0x400UL /**< Bit mask for RTCC_MONTHTICK */ |
| Anna Bridge |
142:4eea097334d6 | 481 | #define _RTCC_IEN_MONTHTICK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 482 | #define RTCC_IEN_MONTHTICK_DEFAULT (_RTCC_IEN_MONTHTICK_DEFAULT << 10) /**< Shifted mode DEFAULT for RTCC_IEN */ |
| Anna Bridge |
142:4eea097334d6 | 483 | |
| Anna Bridge |
142:4eea097334d6 | 484 | /* Bit fields for RTCC STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 485 | #define _RTCC_STATUS_RESETVALUE 0x00000000UL /**< Default value for RTCC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 486 | #define _RTCC_STATUS_MASK 0x00000000UL /**< Mask for RTCC_STATUS */ |
| Anna Bridge |
142:4eea097334d6 | 487 | |
| Anna Bridge |
142:4eea097334d6 | 488 | /* Bit fields for RTCC CMD */ |
| Anna Bridge |
142:4eea097334d6 | 489 | #define _RTCC_CMD_RESETVALUE 0x00000000UL /**< Default value for RTCC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 490 | #define _RTCC_CMD_MASK 0x00000001UL /**< Mask for RTCC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 491 | #define RTCC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear RTCC_STATUS register. */ |
| Anna Bridge |
142:4eea097334d6 | 492 | #define _RTCC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for RTCC_CLRSTATUS */ |
| Anna Bridge |
142:4eea097334d6 | 493 | #define _RTCC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for RTCC_CLRSTATUS */ |
| Anna Bridge |
142:4eea097334d6 | 494 | #define _RTCC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 495 | #define RTCC_CMD_CLRSTATUS_DEFAULT (_RTCC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 496 | |
| Anna Bridge |
142:4eea097334d6 | 497 | /* Bit fields for RTCC SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 498 | #define _RTCC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTCC_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 499 | #define _RTCC_SYNCBUSY_MASK 0x00000020UL /**< Mask for RTCC_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 500 | #define RTCC_SYNCBUSY_CMD (0x1UL << 5) /**< CMD Register Busy */ |
| Anna Bridge |
142:4eea097334d6 | 501 | #define _RTCC_SYNCBUSY_CMD_SHIFT 5 /**< Shift value for RTCC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 502 | #define _RTCC_SYNCBUSY_CMD_MASK 0x20UL /**< Bit mask for RTCC_CMD */ |
| Anna Bridge |
142:4eea097334d6 | 503 | #define _RTCC_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 504 | #define RTCC_SYNCBUSY_CMD_DEFAULT (_RTCC_SYNCBUSY_CMD_DEFAULT << 5) /**< Shifted mode DEFAULT for RTCC_SYNCBUSY */ |
| Anna Bridge |
142:4eea097334d6 | 505 | |
| Anna Bridge |
142:4eea097334d6 | 506 | /* Bit fields for RTCC POWERDOWN */ |
| Anna Bridge |
142:4eea097334d6 | 507 | #define _RTCC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for RTCC_POWERDOWN */ |
| Anna Bridge |
142:4eea097334d6 | 508 | #define _RTCC_POWERDOWN_MASK 0x00000001UL /**< Mask for RTCC_POWERDOWN */ |
| Anna Bridge |
142:4eea097334d6 | 509 | #define RTCC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */ |
| Anna Bridge |
142:4eea097334d6 | 510 | #define _RTCC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for RTCC_RAM */ |
| Anna Bridge |
142:4eea097334d6 | 511 | #define _RTCC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for RTCC_RAM */ |
| Anna Bridge |
142:4eea097334d6 | 512 | #define _RTCC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_POWERDOWN */ |
| Anna Bridge |
142:4eea097334d6 | 513 | #define RTCC_POWERDOWN_RAM_DEFAULT (_RTCC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_POWERDOWN */ |
| Anna Bridge |
142:4eea097334d6 | 514 | |
| Anna Bridge |
142:4eea097334d6 | 515 | /* Bit fields for RTCC LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 516 | #define _RTCC_LOCK_RESETVALUE 0x00000000UL /**< Default value for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 517 | #define _RTCC_LOCK_MASK 0x0000FFFFUL /**< Mask for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 518 | #define _RTCC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RTCC_LOCKKEY */ |
| Anna Bridge |
142:4eea097334d6 | 519 | #define _RTCC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RTCC_LOCKKEY */ |
| Anna Bridge |
142:4eea097334d6 | 520 | #define _RTCC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 521 | #define _RTCC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 522 | #define _RTCC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 523 | #define _RTCC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 524 | #define _RTCC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 525 | #define RTCC_LOCK_LOCKKEY_DEFAULT (_RTCC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 526 | #define RTCC_LOCK_LOCKKEY_LOCK (_RTCC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 527 | #define RTCC_LOCK_LOCKKEY_UNLOCKED (_RTCC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 528 | #define RTCC_LOCK_LOCKKEY_LOCKED (_RTCC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 529 | #define RTCC_LOCK_LOCKKEY_UNLOCK (_RTCC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RTCC_LOCK */ |
| Anna Bridge |
142:4eea097334d6 | 530 | |
| Anna Bridge |
142:4eea097334d6 | 531 | /* Bit fields for RTCC EM4WUEN */ |
| Anna Bridge |
142:4eea097334d6 | 532 | #define _RTCC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for RTCC_EM4WUEN */ |
| Anna Bridge |
142:4eea097334d6 | 533 | #define _RTCC_EM4WUEN_MASK 0x00000001UL /**< Mask for RTCC_EM4WUEN */ |
| Anna Bridge |
142:4eea097334d6 | 534 | #define RTCC_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up enable */ |
| Anna Bridge |
142:4eea097334d6 | 535 | #define _RTCC_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for RTCC_EM4WU */ |
| Anna Bridge |
142:4eea097334d6 | 536 | #define _RTCC_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for RTCC_EM4WU */ |
| Anna Bridge |
142:4eea097334d6 | 537 | #define _RTCC_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_EM4WUEN */ |
| Anna Bridge |
142:4eea097334d6 | 538 | #define RTCC_EM4WUEN_EM4WU_DEFAULT (_RTCC_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_EM4WUEN */ |
| Anna Bridge |
142:4eea097334d6 | 539 | |
| Anna Bridge |
142:4eea097334d6 | 540 | /* Bit fields for RTCC CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 541 | #define _RTCC_CC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 542 | #define _RTCC_CC_CTRL_MASK 0x0003FBFFUL /**< Mask for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 543 | #define _RTCC_CC_CTRL_MODE_SHIFT 0 /**< Shift value for CC_MODE */ |
| Anna Bridge |
142:4eea097334d6 | 544 | #define _RTCC_CC_CTRL_MODE_MASK 0x3UL /**< Bit mask for CC_MODE */ |
| Anna Bridge |
142:4eea097334d6 | 545 | #define _RTCC_CC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 546 | #define _RTCC_CC_CTRL_MODE_OFF 0x00000000UL /**< Mode OFF for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 547 | #define _RTCC_CC_CTRL_MODE_INPUTCAPTURE 0x00000001UL /**< Mode INPUTCAPTURE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 548 | #define _RTCC_CC_CTRL_MODE_OUTPUTCOMPARE 0x00000002UL /**< Mode OUTPUTCOMPARE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 549 | #define RTCC_CC_CTRL_MODE_DEFAULT (_RTCC_CC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 550 | #define RTCC_CC_CTRL_MODE_OFF (_RTCC_CC_CTRL_MODE_OFF << 0) /**< Shifted mode OFF for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 551 | #define RTCC_CC_CTRL_MODE_INPUTCAPTURE (_RTCC_CC_CTRL_MODE_INPUTCAPTURE << 0) /**< Shifted mode INPUTCAPTURE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 552 | #define RTCC_CC_CTRL_MODE_OUTPUTCOMPARE (_RTCC_CC_CTRL_MODE_OUTPUTCOMPARE << 0) /**< Shifted mode OUTPUTCOMPARE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 553 | #define _RTCC_CC_CTRL_CMOA_SHIFT 2 /**< Shift value for CC_CMOA */ |
| Anna Bridge |
142:4eea097334d6 | 554 | #define _RTCC_CC_CTRL_CMOA_MASK 0xCUL /**< Bit mask for CC_CMOA */ |
| Anna Bridge |
142:4eea097334d6 | 555 | #define _RTCC_CC_CTRL_CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 556 | #define _RTCC_CC_CTRL_CMOA_PULSE 0x00000000UL /**< Mode PULSE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 557 | #define _RTCC_CC_CTRL_CMOA_TOGGLE 0x00000001UL /**< Mode TOGGLE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 558 | #define _RTCC_CC_CTRL_CMOA_CLEAR 0x00000002UL /**< Mode CLEAR for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 559 | #define _RTCC_CC_CTRL_CMOA_SET 0x00000003UL /**< Mode SET for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 560 | #define RTCC_CC_CTRL_CMOA_DEFAULT (_RTCC_CC_CTRL_CMOA_DEFAULT << 2) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 561 | #define RTCC_CC_CTRL_CMOA_PULSE (_RTCC_CC_CTRL_CMOA_PULSE << 2) /**< Shifted mode PULSE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 562 | #define RTCC_CC_CTRL_CMOA_TOGGLE (_RTCC_CC_CTRL_CMOA_TOGGLE << 2) /**< Shifted mode TOGGLE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 563 | #define RTCC_CC_CTRL_CMOA_CLEAR (_RTCC_CC_CTRL_CMOA_CLEAR << 2) /**< Shifted mode CLEAR for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 564 | #define RTCC_CC_CTRL_CMOA_SET (_RTCC_CC_CTRL_CMOA_SET << 2) /**< Shifted mode SET for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 565 | #define _RTCC_CC_CTRL_ICEDGE_SHIFT 4 /**< Shift value for CC_ICEDGE */ |
| Anna Bridge |
142:4eea097334d6 | 566 | #define _RTCC_CC_CTRL_ICEDGE_MASK 0x30UL /**< Bit mask for CC_ICEDGE */ |
| Anna Bridge |
142:4eea097334d6 | 567 | #define _RTCC_CC_CTRL_ICEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 568 | #define _RTCC_CC_CTRL_ICEDGE_RISING 0x00000000UL /**< Mode RISING for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 569 | #define _RTCC_CC_CTRL_ICEDGE_FALLING 0x00000001UL /**< Mode FALLING for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 570 | #define _RTCC_CC_CTRL_ICEDGE_BOTH 0x00000002UL /**< Mode BOTH for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 571 | #define _RTCC_CC_CTRL_ICEDGE_NONE 0x00000003UL /**< Mode NONE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 572 | #define RTCC_CC_CTRL_ICEDGE_DEFAULT (_RTCC_CC_CTRL_ICEDGE_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 573 | #define RTCC_CC_CTRL_ICEDGE_RISING (_RTCC_CC_CTRL_ICEDGE_RISING << 4) /**< Shifted mode RISING for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 574 | #define RTCC_CC_CTRL_ICEDGE_FALLING (_RTCC_CC_CTRL_ICEDGE_FALLING << 4) /**< Shifted mode FALLING for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 575 | #define RTCC_CC_CTRL_ICEDGE_BOTH (_RTCC_CC_CTRL_ICEDGE_BOTH << 4) /**< Shifted mode BOTH for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 576 | #define RTCC_CC_CTRL_ICEDGE_NONE (_RTCC_CC_CTRL_ICEDGE_NONE << 4) /**< Shifted mode NONE for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 577 | #define _RTCC_CC_CTRL_PRSSEL_SHIFT 6 /**< Shift value for CC_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 578 | #define _RTCC_CC_CTRL_PRSSEL_MASK 0x3C0UL /**< Bit mask for CC_PRSSEL */ |
| Anna Bridge |
142:4eea097334d6 | 579 | #define _RTCC_CC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 580 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 581 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 582 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 583 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 584 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 585 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 586 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 587 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 588 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 589 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 590 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 591 | #define _RTCC_CC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 592 | #define RTCC_CC_CTRL_PRSSEL_DEFAULT (_RTCC_CC_CTRL_PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 593 | #define RTCC_CC_CTRL_PRSSEL_PRSCH0 (_RTCC_CC_CTRL_PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 594 | #define RTCC_CC_CTRL_PRSSEL_PRSCH1 (_RTCC_CC_CTRL_PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 595 | #define RTCC_CC_CTRL_PRSSEL_PRSCH2 (_RTCC_CC_CTRL_PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 596 | #define RTCC_CC_CTRL_PRSSEL_PRSCH3 (_RTCC_CC_CTRL_PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 597 | #define RTCC_CC_CTRL_PRSSEL_PRSCH4 (_RTCC_CC_CTRL_PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 598 | #define RTCC_CC_CTRL_PRSSEL_PRSCH5 (_RTCC_CC_CTRL_PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 599 | #define RTCC_CC_CTRL_PRSSEL_PRSCH6 (_RTCC_CC_CTRL_PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 600 | #define RTCC_CC_CTRL_PRSSEL_PRSCH7 (_RTCC_CC_CTRL_PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 601 | #define RTCC_CC_CTRL_PRSSEL_PRSCH8 (_RTCC_CC_CTRL_PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 602 | #define RTCC_CC_CTRL_PRSSEL_PRSCH9 (_RTCC_CC_CTRL_PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 603 | #define RTCC_CC_CTRL_PRSSEL_PRSCH10 (_RTCC_CC_CTRL_PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 604 | #define RTCC_CC_CTRL_PRSSEL_PRSCH11 (_RTCC_CC_CTRL_PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 605 | #define RTCC_CC_CTRL_COMPBASE (0x1UL << 11) /**< Capture compare channel comparison base. */ |
| Anna Bridge |
142:4eea097334d6 | 606 | #define _RTCC_CC_CTRL_COMPBASE_SHIFT 11 /**< Shift value for CC_COMPBASE */ |
| Anna Bridge |
142:4eea097334d6 | 607 | #define _RTCC_CC_CTRL_COMPBASE_MASK 0x800UL /**< Bit mask for CC_COMPBASE */ |
| Anna Bridge |
142:4eea097334d6 | 608 | #define _RTCC_CC_CTRL_COMPBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 609 | #define _RTCC_CC_CTRL_COMPBASE_CNT 0x00000000UL /**< Mode CNT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 610 | #define _RTCC_CC_CTRL_COMPBASE_PRECNT 0x00000001UL /**< Mode PRECNT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 611 | #define RTCC_CC_CTRL_COMPBASE_DEFAULT (_RTCC_CC_CTRL_COMPBASE_DEFAULT << 11) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 612 | #define RTCC_CC_CTRL_COMPBASE_CNT (_RTCC_CC_CTRL_COMPBASE_CNT << 11) /**< Shifted mode CNT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 613 | #define RTCC_CC_CTRL_COMPBASE_PRECNT (_RTCC_CC_CTRL_COMPBASE_PRECNT << 11) /**< Shifted mode PRECNT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 614 | #define _RTCC_CC_CTRL_COMPMASK_SHIFT 12 /**< Shift value for CC_COMPMASK */ |
| Anna Bridge |
142:4eea097334d6 | 615 | #define _RTCC_CC_CTRL_COMPMASK_MASK 0x1F000UL /**< Bit mask for CC_COMPMASK */ |
| Anna Bridge |
142:4eea097334d6 | 616 | #define _RTCC_CC_CTRL_COMPMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 617 | #define RTCC_CC_CTRL_COMPMASK_DEFAULT (_RTCC_CC_CTRL_COMPMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 618 | #define RTCC_CC_CTRL_DAYCC (0x1UL << 17) /**< Day Capture/Compare selection */ |
| Anna Bridge |
142:4eea097334d6 | 619 | #define _RTCC_CC_CTRL_DAYCC_SHIFT 17 /**< Shift value for CC_DAYCC */ |
| Anna Bridge |
142:4eea097334d6 | 620 | #define _RTCC_CC_CTRL_DAYCC_MASK 0x20000UL /**< Bit mask for CC_DAYCC */ |
| Anna Bridge |
142:4eea097334d6 | 621 | #define _RTCC_CC_CTRL_DAYCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 622 | #define _RTCC_CC_CTRL_DAYCC_MONTH 0x00000000UL /**< Mode MONTH for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 623 | #define _RTCC_CC_CTRL_DAYCC_WEEK 0x00000001UL /**< Mode WEEK for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 624 | #define RTCC_CC_CTRL_DAYCC_DEFAULT (_RTCC_CC_CTRL_DAYCC_DEFAULT << 17) /**< Shifted mode DEFAULT for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 625 | #define RTCC_CC_CTRL_DAYCC_MONTH (_RTCC_CC_CTRL_DAYCC_MONTH << 17) /**< Shifted mode MONTH for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 626 | #define RTCC_CC_CTRL_DAYCC_WEEK (_RTCC_CC_CTRL_DAYCC_WEEK << 17) /**< Shifted mode WEEK for RTCC_CC_CTRL */ |
| Anna Bridge |
142:4eea097334d6 | 627 | |
| Anna Bridge |
142:4eea097334d6 | 628 | /* Bit fields for RTCC CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 629 | #define _RTCC_CC_CCV_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 630 | #define _RTCC_CC_CCV_MASK 0xFFFFFFFFUL /**< Mask for RTCC_CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 631 | #define _RTCC_CC_CCV_CCV_SHIFT 0 /**< Shift value for CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 632 | #define _RTCC_CC_CCV_CCV_MASK 0xFFFFFFFFUL /**< Bit mask for CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 633 | #define _RTCC_CC_CCV_CCV_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 634 | #define RTCC_CC_CCV_CCV_DEFAULT (_RTCC_CC_CCV_CCV_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_CCV */ |
| Anna Bridge |
142:4eea097334d6 | 635 | |
| Anna Bridge |
142:4eea097334d6 | 636 | /* Bit fields for RTCC CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 637 | #define _RTCC_CC_TIME_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 638 | #define _RTCC_CC_TIME_MASK 0x003F7F7FUL /**< Mask for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 639 | #define _RTCC_CC_TIME_SECU_SHIFT 0 /**< Shift value for CC_SECU */ |
| Anna Bridge |
142:4eea097334d6 | 640 | #define _RTCC_CC_TIME_SECU_MASK 0xFUL /**< Bit mask for CC_SECU */ |
| Anna Bridge |
142:4eea097334d6 | 641 | #define _RTCC_CC_TIME_SECU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 642 | #define RTCC_CC_TIME_SECU_DEFAULT (_RTCC_CC_TIME_SECU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 643 | #define _RTCC_CC_TIME_SECT_SHIFT 4 /**< Shift value for CC_SECT */ |
| Anna Bridge |
142:4eea097334d6 | 644 | #define _RTCC_CC_TIME_SECT_MASK 0x70UL /**< Bit mask for CC_SECT */ |
| Anna Bridge |
142:4eea097334d6 | 645 | #define _RTCC_CC_TIME_SECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 646 | #define RTCC_CC_TIME_SECT_DEFAULT (_RTCC_CC_TIME_SECT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 647 | #define _RTCC_CC_TIME_MINU_SHIFT 8 /**< Shift value for CC_MINU */ |
| Anna Bridge |
142:4eea097334d6 | 648 | #define _RTCC_CC_TIME_MINU_MASK 0xF00UL /**< Bit mask for CC_MINU */ |
| Anna Bridge |
142:4eea097334d6 | 649 | #define _RTCC_CC_TIME_MINU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 650 | #define RTCC_CC_TIME_MINU_DEFAULT (_RTCC_CC_TIME_MINU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 651 | #define _RTCC_CC_TIME_MINT_SHIFT 12 /**< Shift value for CC_MINT */ |
| Anna Bridge |
142:4eea097334d6 | 652 | #define _RTCC_CC_TIME_MINT_MASK 0x7000UL /**< Bit mask for CC_MINT */ |
| Anna Bridge |
142:4eea097334d6 | 653 | #define _RTCC_CC_TIME_MINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 654 | #define RTCC_CC_TIME_MINT_DEFAULT (_RTCC_CC_TIME_MINT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 655 | #define _RTCC_CC_TIME_HOURU_SHIFT 16 /**< Shift value for CC_HOURU */ |
| Anna Bridge |
142:4eea097334d6 | 656 | #define _RTCC_CC_TIME_HOURU_MASK 0xF0000UL /**< Bit mask for CC_HOURU */ |
| Anna Bridge |
142:4eea097334d6 | 657 | #define _RTCC_CC_TIME_HOURU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 658 | #define RTCC_CC_TIME_HOURU_DEFAULT (_RTCC_CC_TIME_HOURU_DEFAULT << 16) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 659 | #define _RTCC_CC_TIME_HOURT_SHIFT 20 /**< Shift value for CC_HOURT */ |
| Anna Bridge |
142:4eea097334d6 | 660 | #define _RTCC_CC_TIME_HOURT_MASK 0x300000UL /**< Bit mask for CC_HOURT */ |
| Anna Bridge |
142:4eea097334d6 | 661 | #define _RTCC_CC_TIME_HOURT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 662 | #define RTCC_CC_TIME_HOURT_DEFAULT (_RTCC_CC_TIME_HOURT_DEFAULT << 20) /**< Shifted mode DEFAULT for RTCC_CC_TIME */ |
| Anna Bridge |
142:4eea097334d6 | 663 | |
| Anna Bridge |
142:4eea097334d6 | 664 | /* Bit fields for RTCC CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 665 | #define _RTCC_CC_DATE_RESETVALUE 0x00000000UL /**< Default value for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 666 | #define _RTCC_CC_DATE_MASK 0x00001F3FUL /**< Mask for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 667 | #define _RTCC_CC_DATE_DAYU_SHIFT 0 /**< Shift value for CC_DAYU */ |
| Anna Bridge |
142:4eea097334d6 | 668 | #define _RTCC_CC_DATE_DAYU_MASK 0xFUL /**< Bit mask for CC_DAYU */ |
| Anna Bridge |
142:4eea097334d6 | 669 | #define _RTCC_CC_DATE_DAYU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 670 | #define RTCC_CC_DATE_DAYU_DEFAULT (_RTCC_CC_DATE_DAYU_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 671 | #define _RTCC_CC_DATE_DAYT_SHIFT 4 /**< Shift value for CC_DAYT */ |
| Anna Bridge |
142:4eea097334d6 | 672 | #define _RTCC_CC_DATE_DAYT_MASK 0x30UL /**< Bit mask for CC_DAYT */ |
| Anna Bridge |
142:4eea097334d6 | 673 | #define _RTCC_CC_DATE_DAYT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 674 | #define RTCC_CC_DATE_DAYT_DEFAULT (_RTCC_CC_DATE_DAYT_DEFAULT << 4) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 675 | #define _RTCC_CC_DATE_MONTHU_SHIFT 8 /**< Shift value for CC_MONTHU */ |
| Anna Bridge |
142:4eea097334d6 | 676 | #define _RTCC_CC_DATE_MONTHU_MASK 0xF00UL /**< Bit mask for CC_MONTHU */ |
| Anna Bridge |
142:4eea097334d6 | 677 | #define _RTCC_CC_DATE_MONTHU_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 678 | #define RTCC_CC_DATE_MONTHU_DEFAULT (_RTCC_CC_DATE_MONTHU_DEFAULT << 8) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 679 | #define RTCC_CC_DATE_MONTHT (0x1UL << 12) /**< Month, tens. */ |
| Anna Bridge |
142:4eea097334d6 | 680 | #define _RTCC_CC_DATE_MONTHT_SHIFT 12 /**< Shift value for CC_MONTHT */ |
| Anna Bridge |
142:4eea097334d6 | 681 | #define _RTCC_CC_DATE_MONTHT_MASK 0x1000UL /**< Bit mask for CC_MONTHT */ |
| Anna Bridge |
142:4eea097334d6 | 682 | #define _RTCC_CC_DATE_MONTHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 683 | #define RTCC_CC_DATE_MONTHT_DEFAULT (_RTCC_CC_DATE_MONTHT_DEFAULT << 12) /**< Shifted mode DEFAULT for RTCC_CC_DATE */ |
| Anna Bridge |
142:4eea097334d6 | 684 | |
| Anna Bridge |
142:4eea097334d6 | 685 | /* Bit fields for RTCC RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 686 | #define _RTCC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for RTCC_RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 687 | #define _RTCC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for RTCC_RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 688 | #define _RTCC_RET_REG_REG_SHIFT 0 /**< Shift value for RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 689 | #define _RTCC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 690 | #define _RTCC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTCC_RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 691 | #define RTCC_RET_REG_REG_DEFAULT (_RTCC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for RTCC_RET_REG */ |
| Anna Bridge |
142:4eea097334d6 | 692 | |
| Anna Bridge |
142:4eea097334d6 | 693 | /** @} End of group EFR32MG1P_RTCC */ |
| Anna Bridge |
142:4eea097334d6 | 694 | /** @} End of group Parts */ |
| Anna Bridge |
142:4eea097334d6 | 695 |
