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TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/comp_pm.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Component description for PM |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_PM_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_PM_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | /** SOFTWARE API DEFINITION FOR PM */ |
AnnaBridge | 171:3a7713b1edbc | 52 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 53 | /** \addtogroup SAMD21_PM Power Manager */ |
AnnaBridge | 171:3a7713b1edbc | 54 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | #define PM_U2206 |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REV_PM 0x211 |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 61 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 62 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 63 | } PM_CTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 64 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 65 | |
AnnaBridge | 171:3a7713b1edbc | 66 | #define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define PM_CTRL_RESETVALUE 0x00ul /**< \brief (PM_CTRL reset_value) Control */ |
AnnaBridge | 171:3a7713b1edbc | 68 | |
AnnaBridge | 171:3a7713b1edbc | 69 | #define PM_CTRL_MASK 0x00ul /**< \brief (PM_CTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 73 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 74 | struct { |
AnnaBridge | 171:3a7713b1edbc | 75 | uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 76 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 77 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 78 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 79 | } PM_SLEEP_Type; |
AnnaBridge | 171:3a7713b1edbc | 80 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | #define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define PM_SLEEP_RESETVALUE 0x00ul /**< \brief (PM_SLEEP reset_value) Sleep Mode */ |
AnnaBridge | 171:3a7713b1edbc | 84 | |
AnnaBridge | 171:3a7713b1edbc | 85 | #define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define PM_SLEEP_IDLE_Msk (0x3ul << PM_SLEEP_IDLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 87 | #define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 88 | #define PM_SLEEP_IDLE_CPU_Val 0x0ul /**< \brief (PM_SLEEP) The CPU clock domain is stopped */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define PM_SLEEP_IDLE_AHB_Val 0x1ul /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define PM_SLEEP_IDLE_APB_Val 0x2ul /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 92 | #define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 93 | #define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 94 | #define PM_SLEEP_MASK 0x03ul /**< \brief (PM_SLEEP) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 95 | |
AnnaBridge | 171:3a7713b1edbc | 96 | /* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 98 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 99 | struct { |
AnnaBridge | 171:3a7713b1edbc | 100 | uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */ |
AnnaBridge | 171:3a7713b1edbc | 101 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 102 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 103 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 104 | } PM_EXTCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 105 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 106 | |
AnnaBridge | 171:3a7713b1edbc | 107 | #define PM_EXTCTRL_OFFSET 0x02 /**< \brief (PM_EXTCTRL offset) External Reset Controller */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define PM_EXTCTRL_RESETVALUE 0x00ul /**< \brief (PM_EXTCTRL reset_value) External Reset Controller */ |
AnnaBridge | 171:3a7713b1edbc | 109 | |
AnnaBridge | 171:3a7713b1edbc | 110 | #define PM_EXTCTRL_SETDIS_Pos 0 /**< \brief (PM_EXTCTRL) External Reset Disable */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define PM_EXTCTRL_SETDIS (0x1ul << PM_EXTCTRL_SETDIS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 112 | #define PM_EXTCTRL_MASK 0x01ul /**< \brief (PM_EXTCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */ |
AnnaBridge | 171:3a7713b1edbc | 115 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 116 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 117 | struct { |
AnnaBridge | 171:3a7713b1edbc | 118 | uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 119 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 120 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 121 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 122 | } PM_CPUSEL_Type; |
AnnaBridge | 171:3a7713b1edbc | 123 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | #define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define PM_CPUSEL_RESETVALUE 0x00ul /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 127 | |
AnnaBridge | 171:3a7713b1edbc | 128 | #define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define PM_CPUSEL_CPUDIV_Msk (0x7ul << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 130 | #define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 131 | #define PM_CPUSEL_CPUDIV_DIV1_Val 0x0ul /**< \brief (PM_CPUSEL) Divide by 1 */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define PM_CPUSEL_CPUDIV_DIV2_Val 0x1ul /**< \brief (PM_CPUSEL) Divide by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define PM_CPUSEL_CPUDIV_DIV4_Val 0x2ul /**< \brief (PM_CPUSEL) Divide by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define PM_CPUSEL_CPUDIV_DIV8_Val 0x3ul /**< \brief (PM_CPUSEL) Divide by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define PM_CPUSEL_CPUDIV_DIV16_Val 0x4ul /**< \brief (PM_CPUSEL) Divide by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define PM_CPUSEL_CPUDIV_DIV32_Val 0x5ul /**< \brief (PM_CPUSEL) Divide by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define PM_CPUSEL_CPUDIV_DIV64_Val 0x6ul /**< \brief (PM_CPUSEL) Divide by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define PM_CPUSEL_CPUDIV_DIV128_Val 0x7ul /**< \brief (PM_CPUSEL) Divide by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 140 | #define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 141 | #define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 142 | #define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 143 | #define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 144 | #define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 145 | #define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 146 | #define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 147 | #define PM_CPUSEL_MASK 0x07ul /**< \brief (PM_CPUSEL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 148 | |
AnnaBridge | 171:3a7713b1edbc | 149 | /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 151 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 152 | struct { |
AnnaBridge | 171:3a7713b1edbc | 153 | uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 154 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 155 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 156 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 157 | } PM_APBASEL_Type; |
AnnaBridge | 171:3a7713b1edbc | 158 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 159 | |
AnnaBridge | 171:3a7713b1edbc | 160 | #define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define PM_APBASEL_RESETVALUE 0x00ul /**< \brief (PM_APBASEL reset_value) APBA Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 162 | |
AnnaBridge | 171:3a7713b1edbc | 163 | #define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 164 | #define PM_APBASEL_APBADIV_Msk (0x7ul << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 165 | #define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 166 | #define PM_APBASEL_APBADIV_DIV1_Val 0x0ul /**< \brief (PM_APBASEL) Divide by 1 */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define PM_APBASEL_APBADIV_DIV2_Val 0x1ul /**< \brief (PM_APBASEL) Divide by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define PM_APBASEL_APBADIV_DIV4_Val 0x2ul /**< \brief (PM_APBASEL) Divide by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define PM_APBASEL_APBADIV_DIV8_Val 0x3ul /**< \brief (PM_APBASEL) Divide by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define PM_APBASEL_APBADIV_DIV16_Val 0x4ul /**< \brief (PM_APBASEL) Divide by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define PM_APBASEL_APBADIV_DIV32_Val 0x5ul /**< \brief (PM_APBASEL) Divide by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 172 | #define PM_APBASEL_APBADIV_DIV64_Val 0x6ul /**< \brief (PM_APBASEL) Divide by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define PM_APBASEL_APBADIV_DIV128_Val 0x7ul /**< \brief (PM_APBASEL) Divide by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 174 | #define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 175 | #define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 176 | #define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 177 | #define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 178 | #define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 179 | #define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 180 | #define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 181 | #define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 182 | #define PM_APBASEL_MASK 0x07ul /**< \brief (PM_APBASEL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 183 | |
AnnaBridge | 171:3a7713b1edbc | 184 | /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 186 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 187 | struct { |
AnnaBridge | 171:3a7713b1edbc | 188 | uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 189 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 190 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 191 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 192 | } PM_APBBSEL_Type; |
AnnaBridge | 171:3a7713b1edbc | 193 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 194 | |
AnnaBridge | 171:3a7713b1edbc | 195 | #define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define PM_APBBSEL_RESETVALUE 0x00ul /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 197 | |
AnnaBridge | 171:3a7713b1edbc | 198 | #define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define PM_APBBSEL_APBBDIV_Msk (0x7ul << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 200 | #define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 201 | #define PM_APBBSEL_APBBDIV_DIV1_Val 0x0ul /**< \brief (PM_APBBSEL) Divide by 1 */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define PM_APBBSEL_APBBDIV_DIV2_Val 0x1ul /**< \brief (PM_APBBSEL) Divide by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define PM_APBBSEL_APBBDIV_DIV4_Val 0x2ul /**< \brief (PM_APBBSEL) Divide by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define PM_APBBSEL_APBBDIV_DIV8_Val 0x3ul /**< \brief (PM_APBBSEL) Divide by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define PM_APBBSEL_APBBDIV_DIV16_Val 0x4ul /**< \brief (PM_APBBSEL) Divide by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define PM_APBBSEL_APBBDIV_DIV32_Val 0x5ul /**< \brief (PM_APBBSEL) Divide by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define PM_APBBSEL_APBBDIV_DIV64_Val 0x6ul /**< \brief (PM_APBBSEL) Divide by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define PM_APBBSEL_APBBDIV_DIV128_Val 0x7ul /**< \brief (PM_APBBSEL) Divide by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 210 | #define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 211 | #define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 212 | #define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 213 | #define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 214 | #define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 215 | #define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 216 | #define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 217 | #define PM_APBBSEL_MASK 0x07ul /**< \brief (PM_APBBSEL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 221 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 222 | struct { |
AnnaBridge | 171:3a7713b1edbc | 223 | uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 224 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 225 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 226 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 227 | } PM_APBCSEL_Type; |
AnnaBridge | 171:3a7713b1edbc | 228 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 229 | |
AnnaBridge | 171:3a7713b1edbc | 230 | #define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define PM_APBCSEL_RESETVALUE 0x00ul /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 232 | |
AnnaBridge | 171:3a7713b1edbc | 233 | #define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define PM_APBCSEL_APBCDIV_Msk (0x7ul << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 235 | #define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 236 | #define PM_APBCSEL_APBCDIV_DIV1_Val 0x0ul /**< \brief (PM_APBCSEL) Divide by 1 */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define PM_APBCSEL_APBCDIV_DIV2_Val 0x1ul /**< \brief (PM_APBCSEL) Divide by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define PM_APBCSEL_APBCDIV_DIV4_Val 0x2ul /**< \brief (PM_APBCSEL) Divide by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define PM_APBCSEL_APBCDIV_DIV8_Val 0x3ul /**< \brief (PM_APBCSEL) Divide by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define PM_APBCSEL_APBCDIV_DIV16_Val 0x4ul /**< \brief (PM_APBCSEL) Divide by 16 */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define PM_APBCSEL_APBCDIV_DIV32_Val 0x5ul /**< \brief (PM_APBCSEL) Divide by 32 */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define PM_APBCSEL_APBCDIV_DIV64_Val 0x6ul /**< \brief (PM_APBCSEL) Divide by 64 */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define PM_APBCSEL_APBCDIV_DIV128_Val 0x7ul /**< \brief (PM_APBCSEL) Divide by 128 */ |
AnnaBridge | 171:3a7713b1edbc | 244 | #define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 245 | #define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 246 | #define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 247 | #define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 248 | #define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 249 | #define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 250 | #define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 251 | #define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 252 | #define PM_APBCSEL_MASK 0x07ul /**< \brief (PM_APBCSEL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 253 | |
AnnaBridge | 171:3a7713b1edbc | 254 | /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 256 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 257 | struct { |
AnnaBridge | 171:3a7713b1edbc | 258 | uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 259 | uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 260 | uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 261 | uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 262 | uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 263 | uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 264 | uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 265 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 266 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 267 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 268 | } PM_AHBMASK_Type; |
AnnaBridge | 171:3a7713b1edbc | 269 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 270 | |
AnnaBridge | 171:3a7713b1edbc | 271 | #define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define PM_AHBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_AHBMASK reset_value) AHB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 273 | |
AnnaBridge | 171:3a7713b1edbc | 274 | #define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define PM_AHBMASK_HPB0 (0x1ul << PM_AHBMASK_HPB0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 276 | #define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define PM_AHBMASK_HPB1 (0x1ul << PM_AHBMASK_HPB1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 278 | #define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define PM_AHBMASK_HPB2 (0x1ul << PM_AHBMASK_HPB2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 280 | #define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define PM_AHBMASK_DSU (0x1ul << PM_AHBMASK_DSU_Pos) |
AnnaBridge | 171:3a7713b1edbc | 282 | #define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define PM_AHBMASK_NVMCTRL (0x1ul << PM_AHBMASK_NVMCTRL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 284 | #define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define PM_AHBMASK_DMAC (0x1ul << PM_AHBMASK_DMAC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 286 | #define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define PM_AHBMASK_USB (0x1ul << PM_AHBMASK_USB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 288 | #define PM_AHBMASK_MASK 0x0000007Ful /**< \brief (PM_AHBMASK) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 289 | |
AnnaBridge | 171:3a7713b1edbc | 290 | /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 292 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 293 | struct { |
AnnaBridge | 171:3a7713b1edbc | 294 | uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 295 | uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 296 | uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 297 | uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 298 | uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 299 | uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 300 | uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 301 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 302 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 303 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 304 | } PM_APBAMASK_Type; |
AnnaBridge | 171:3a7713b1edbc | 305 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 306 | |
AnnaBridge | 171:3a7713b1edbc | 307 | #define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define PM_APBAMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBAMASK reset_value) APBA Mask */ |
AnnaBridge | 171:3a7713b1edbc | 309 | |
AnnaBridge | 171:3a7713b1edbc | 310 | #define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 311 | #define PM_APBAMASK_PAC0 (0x1ul << PM_APBAMASK_PAC0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 312 | #define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #define PM_APBAMASK_PM (0x1ul << PM_APBAMASK_PM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 314 | #define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 315 | #define PM_APBAMASK_SYSCTRL (0x1ul << PM_APBAMASK_SYSCTRL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 316 | #define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define PM_APBAMASK_GCLK (0x1ul << PM_APBAMASK_GCLK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 318 | #define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define PM_APBAMASK_WDT (0x1ul << PM_APBAMASK_WDT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 320 | #define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define PM_APBAMASK_RTC (0x1ul << PM_APBAMASK_RTC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 322 | #define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 323 | #define PM_APBAMASK_EIC (0x1ul << PM_APBAMASK_EIC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 324 | #define PM_APBAMASK_MASK 0x0000007Ful /**< \brief (PM_APBAMASK) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 325 | |
AnnaBridge | 171:3a7713b1edbc | 326 | /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */ |
AnnaBridge | 171:3a7713b1edbc | 327 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 328 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 329 | struct { |
AnnaBridge | 171:3a7713b1edbc | 330 | uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 331 | uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 332 | uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 333 | uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 334 | uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 335 | uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 336 | uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 337 | uint32_t :25; /*!< bit: 7..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 338 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 339 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 340 | } PM_APBBMASK_Type; |
AnnaBridge | 171:3a7713b1edbc | 341 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 342 | |
AnnaBridge | 171:3a7713b1edbc | 343 | #define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define PM_APBBMASK_RESETVALUE 0x0000007Ful /**< \brief (PM_APBBMASK reset_value) APBB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 345 | |
AnnaBridge | 171:3a7713b1edbc | 346 | #define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 347 | #define PM_APBBMASK_PAC1 (0x1ul << PM_APBBMASK_PAC1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 348 | #define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 349 | #define PM_APBBMASK_DSU (0x1ul << PM_APBBMASK_DSU_Pos) |
AnnaBridge | 171:3a7713b1edbc | 350 | #define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #define PM_APBBMASK_NVMCTRL (0x1ul << PM_APBBMASK_NVMCTRL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 352 | #define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 353 | #define PM_APBBMASK_PORT (0x1ul << PM_APBBMASK_PORT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 354 | #define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define PM_APBBMASK_DMAC (0x1ul << PM_APBBMASK_DMAC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 356 | #define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 357 | #define PM_APBBMASK_USB (0x1ul << PM_APBBMASK_USB_Pos) |
AnnaBridge | 171:3a7713b1edbc | 358 | #define PM_APBBMASK_HMATRIX_Pos 6 /**< \brief (PM_APBBMASK) HMATRIX APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define PM_APBBMASK_HMATRIX (0x1ul << PM_APBBMASK_HMATRIX_Pos) |
AnnaBridge | 171:3a7713b1edbc | 360 | #define PM_APBBMASK_MASK 0x0000007Ful /**< \brief (PM_APBBMASK) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 361 | |
AnnaBridge | 171:3a7713b1edbc | 362 | /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 364 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 365 | struct { |
AnnaBridge | 171:3a7713b1edbc | 366 | uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 367 | uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 368 | uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 369 | uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 370 | uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 371 | uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 372 | uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 373 | uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 374 | uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 375 | uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 376 | uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 377 | uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 378 | uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 379 | uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 380 | uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 381 | uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 382 | uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 383 | uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 384 | uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 385 | uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 386 | uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 387 | uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 388 | uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 389 | uint32_t :9; /*!< bit: 23..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 390 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 391 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 392 | } PM_APBCMASK_Type; |
AnnaBridge | 171:3a7713b1edbc | 393 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 394 | |
AnnaBridge | 171:3a7713b1edbc | 395 | #define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */ |
AnnaBridge | 171:3a7713b1edbc | 396 | #define PM_APBCMASK_RESETVALUE 0x00010000ul /**< \brief (PM_APBCMASK reset_value) APBC Mask */ |
AnnaBridge | 171:3a7713b1edbc | 397 | |
AnnaBridge | 171:3a7713b1edbc | 398 | #define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define PM_APBCMASK_PAC2 (0x1ul << PM_APBCMASK_PAC2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 400 | #define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 401 | #define PM_APBCMASK_EVSYS (0x1ul << PM_APBCMASK_EVSYS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 402 | #define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 403 | #define PM_APBCMASK_SERCOM0 (0x1ul << PM_APBCMASK_SERCOM0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 404 | #define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define PM_APBCMASK_SERCOM1 (0x1ul << PM_APBCMASK_SERCOM1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 406 | #define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 407 | #define PM_APBCMASK_SERCOM2 (0x1ul << PM_APBCMASK_SERCOM2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 408 | #define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 409 | #define PM_APBCMASK_SERCOM3 (0x1ul << PM_APBCMASK_SERCOM3_Pos) |
AnnaBridge | 171:3a7713b1edbc | 410 | #define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 411 | #define PM_APBCMASK_SERCOM4 (0x1ul << PM_APBCMASK_SERCOM4_Pos) |
AnnaBridge | 171:3a7713b1edbc | 412 | #define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define PM_APBCMASK_SERCOM5 (0x1ul << PM_APBCMASK_SERCOM5_Pos) |
AnnaBridge | 171:3a7713b1edbc | 414 | #define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 415 | #define PM_APBCMASK_TCC0 (0x1ul << PM_APBCMASK_TCC0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 416 | #define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 417 | #define PM_APBCMASK_TCC1 (0x1ul << PM_APBCMASK_TCC1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 418 | #define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define PM_APBCMASK_TCC2 (0x1ul << PM_APBCMASK_TCC2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 420 | #define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 421 | #define PM_APBCMASK_TC3 (0x1ul << PM_APBCMASK_TC3_Pos) |
AnnaBridge | 171:3a7713b1edbc | 422 | #define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 423 | #define PM_APBCMASK_TC4 (0x1ul << PM_APBCMASK_TC4_Pos) |
AnnaBridge | 171:3a7713b1edbc | 424 | #define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 425 | #define PM_APBCMASK_TC5 (0x1ul << PM_APBCMASK_TC5_Pos) |
AnnaBridge | 171:3a7713b1edbc | 426 | #define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 427 | #define PM_APBCMASK_TC6 (0x1ul << PM_APBCMASK_TC6_Pos) |
AnnaBridge | 171:3a7713b1edbc | 428 | #define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 429 | #define PM_APBCMASK_TC7 (0x1ul << PM_APBCMASK_TC7_Pos) |
AnnaBridge | 171:3a7713b1edbc | 430 | #define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 431 | #define PM_APBCMASK_ADC (0x1ul << PM_APBCMASK_ADC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 432 | #define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define PM_APBCMASK_AC (0x1ul << PM_APBCMASK_AC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 434 | #define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 435 | #define PM_APBCMASK_DAC (0x1ul << PM_APBCMASK_DAC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 436 | #define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 437 | #define PM_APBCMASK_PTC (0x1ul << PM_APBCMASK_PTC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 438 | #define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 439 | #define PM_APBCMASK_I2S (0x1ul << PM_APBCMASK_I2S_Pos) |
AnnaBridge | 171:3a7713b1edbc | 440 | #define PM_APBCMASK_AC1_Pos 21 /**< \brief (PM_APBCMASK) AC1 APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define PM_APBCMASK_AC1 (0x1ul << PM_APBCMASK_AC1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 442 | #define PM_APBCMASK_LINCTRL_Pos 22 /**< \brief (PM_APBCMASK) LINCTRL APB Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define PM_APBCMASK_LINCTRL (0x1ul << PM_APBCMASK_LINCTRL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 444 | #define PM_APBCMASK_MASK 0x007FFFFFul /**< \brief (PM_APBCMASK) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 445 | |
AnnaBridge | 171:3a7713b1edbc | 446 | /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 447 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 448 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 449 | struct { |
AnnaBridge | 171:3a7713b1edbc | 450 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 451 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 452 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 453 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 454 | } PM_INTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 455 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 456 | |
AnnaBridge | 171:3a7713b1edbc | 457 | #define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 458 | #define PM_INTENCLR_RESETVALUE 0x00ul /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 459 | |
AnnaBridge | 171:3a7713b1edbc | 460 | #define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 461 | #define PM_INTENCLR_CKRDY (0x1ul << PM_INTENCLR_CKRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 462 | #define PM_INTENCLR_MASK 0x01ul /**< \brief (PM_INTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 463 | |
AnnaBridge | 171:3a7713b1edbc | 464 | /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 465 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 466 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 467 | struct { |
AnnaBridge | 171:3a7713b1edbc | 468 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 469 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 470 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 471 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 472 | } PM_INTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 473 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 474 | |
AnnaBridge | 171:3a7713b1edbc | 475 | #define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 476 | #define PM_INTENSET_RESETVALUE 0x00ul /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 477 | |
AnnaBridge | 171:3a7713b1edbc | 478 | #define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define PM_INTENSET_CKRDY (0x1ul << PM_INTENSET_CKRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 480 | #define PM_INTENSET_MASK 0x01ul /**< \brief (PM_INTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 481 | |
AnnaBridge | 171:3a7713b1edbc | 482 | /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 483 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 484 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 485 | struct { |
AnnaBridge | 171:3a7713b1edbc | 486 | uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ |
AnnaBridge | 171:3a7713b1edbc | 487 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 488 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 489 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 490 | } PM_INTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 491 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 492 | |
AnnaBridge | 171:3a7713b1edbc | 493 | #define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 494 | #define PM_INTFLAG_RESETVALUE 0x00ul /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 495 | |
AnnaBridge | 171:3a7713b1edbc | 496 | #define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */ |
AnnaBridge | 171:3a7713b1edbc | 497 | #define PM_INTFLAG_CKRDY (0x1ul << PM_INTFLAG_CKRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 498 | #define PM_INTFLAG_MASK 0x01ul /**< \brief (PM_INTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 499 | |
AnnaBridge | 171:3a7713b1edbc | 500 | /* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 502 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 503 | struct { |
AnnaBridge | 171:3a7713b1edbc | 504 | uint8_t POR:1; /*!< bit: 0 Power On Reset */ |
AnnaBridge | 171:3a7713b1edbc | 505 | uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */ |
AnnaBridge | 171:3a7713b1edbc | 506 | uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */ |
AnnaBridge | 171:3a7713b1edbc | 507 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 508 | uint8_t EXT:1; /*!< bit: 4 External Reset */ |
AnnaBridge | 171:3a7713b1edbc | 509 | uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */ |
AnnaBridge | 171:3a7713b1edbc | 510 | uint8_t SYST:1; /*!< bit: 6 System Reset Request */ |
AnnaBridge | 171:3a7713b1edbc | 511 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 512 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 513 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 514 | } PM_RCAUSE_Type; |
AnnaBridge | 171:3a7713b1edbc | 515 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 516 | |
AnnaBridge | 171:3a7713b1edbc | 517 | #define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define PM_RCAUSE_RESETVALUE 0x01ul /**< \brief (PM_RCAUSE reset_value) Reset Cause */ |
AnnaBridge | 171:3a7713b1edbc | 519 | |
AnnaBridge | 171:3a7713b1edbc | 520 | #define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */ |
AnnaBridge | 171:3a7713b1edbc | 521 | #define PM_RCAUSE_POR (0x1ul << PM_RCAUSE_POR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 522 | #define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */ |
AnnaBridge | 171:3a7713b1edbc | 523 | #define PM_RCAUSE_BOD12 (0x1ul << PM_RCAUSE_BOD12_Pos) |
AnnaBridge | 171:3a7713b1edbc | 524 | #define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */ |
AnnaBridge | 171:3a7713b1edbc | 525 | #define PM_RCAUSE_BOD33 (0x1ul << PM_RCAUSE_BOD33_Pos) |
AnnaBridge | 171:3a7713b1edbc | 526 | #define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */ |
AnnaBridge | 171:3a7713b1edbc | 527 | #define PM_RCAUSE_EXT (0x1ul << PM_RCAUSE_EXT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 528 | #define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define PM_RCAUSE_WDT (0x1ul << PM_RCAUSE_WDT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 530 | #define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define PM_RCAUSE_SYST (0x1ul << PM_RCAUSE_SYST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 532 | #define PM_RCAUSE_MASK 0x77ul /**< \brief (PM_RCAUSE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 533 | |
AnnaBridge | 171:3a7713b1edbc | 534 | /** \brief PM hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 535 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 536 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 537 | __IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ |
AnnaBridge | 171:3a7713b1edbc | 538 | __IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */ |
AnnaBridge | 171:3a7713b1edbc | 539 | __IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */ |
AnnaBridge | 171:3a7713b1edbc | 540 | RoReg8 Reserved1[0x5]; |
AnnaBridge | 171:3a7713b1edbc | 541 | __IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 542 | __IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 543 | __IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 544 | __IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */ |
AnnaBridge | 171:3a7713b1edbc | 545 | RoReg8 Reserved2[0x8]; |
AnnaBridge | 171:3a7713b1edbc | 546 | __IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 547 | __IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */ |
AnnaBridge | 171:3a7713b1edbc | 548 | __IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */ |
AnnaBridge | 171:3a7713b1edbc | 549 | __IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */ |
AnnaBridge | 171:3a7713b1edbc | 550 | RoReg8 Reserved3[0x10]; |
AnnaBridge | 171:3a7713b1edbc | 551 | __IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 552 | __IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 553 | __IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 554 | RoReg8 Reserved4[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 555 | __I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */ |
AnnaBridge | 171:3a7713b1edbc | 556 | } Pm; |
AnnaBridge | 171:3a7713b1edbc | 557 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 558 | |
AnnaBridge | 171:3a7713b1edbc | 559 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 560 | |
AnnaBridge | 171:3a7713b1edbc | 561 | #endif /* _SAMD21_PM_COMPONENT_ */ |