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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_ll_sdmmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_ll_sdmmc.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of low layer SDMMC HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 12 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 14 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 17 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 19 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 20 * without specific prior written permission.
AnnaBridge 172:65be27845400 21 *
AnnaBridge 172:65be27845400 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 32 *
AnnaBridge 172:65be27845400 33 ******************************************************************************
AnnaBridge 172:65be27845400 34 */
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 37 #ifndef __STM32L4xx_LL_SDMMC_H
AnnaBridge 172:65be27845400 38 #define __STM32L4xx_LL_SDMMC_H
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 #ifdef __cplusplus
AnnaBridge 172:65be27845400 41 extern "C" {
AnnaBridge 172:65be27845400 42 #endif
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 #if defined(SDMMC1)
AnnaBridge 172:65be27845400 45
AnnaBridge 172:65be27845400 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 47 #include "stm32l4xx_hal_def.h"
AnnaBridge 172:65be27845400 48
AnnaBridge 172:65be27845400 49 /** @addtogroup STM32L4xx_Driver
AnnaBridge 172:65be27845400 50 * @{
AnnaBridge 172:65be27845400 51 */
AnnaBridge 172:65be27845400 52
AnnaBridge 172:65be27845400 53 /** @addtogroup SDMMC_LL
AnnaBridge 172:65be27845400 54 * @{
AnnaBridge 172:65be27845400 55 */
AnnaBridge 172:65be27845400 56
AnnaBridge 172:65be27845400 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
AnnaBridge 172:65be27845400 59 * @{
AnnaBridge 172:65be27845400 60 */
AnnaBridge 172:65be27845400 61
AnnaBridge 172:65be27845400 62 /**
AnnaBridge 172:65be27845400 63 * @brief SDMMC Configuration Structure definition
AnnaBridge 172:65be27845400 64 */
AnnaBridge 172:65be27845400 65 typedef struct
AnnaBridge 172:65be27845400 66 {
AnnaBridge 172:65be27845400 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge 172:65be27845400 68 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
AnnaBridge 172:65be27845400 69
AnnaBridge 172:65be27845400 70 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 71 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
AnnaBridge 172:65be27845400 72 enabled or disabled.
AnnaBridge 172:65be27845400 73 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
AnnaBridge 172:65be27845400 74 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge 172:65be27845400 75
AnnaBridge 172:65be27845400 76 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
AnnaBridge 172:65be27845400 77 disabled when the bus is idle.
AnnaBridge 172:65be27845400 78 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
AnnaBridge 172:65be27845400 79
AnnaBridge 172:65be27845400 80 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
AnnaBridge 172:65be27845400 81 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
AnnaBridge 172:65be27845400 82
AnnaBridge 172:65be27845400 83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
AnnaBridge 172:65be27845400 84 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
AnnaBridge 172:65be27845400 85
AnnaBridge 172:65be27845400 86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
AnnaBridge 172:65be27845400 87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge 172:65be27845400 88
AnnaBridge 172:65be27845400 89 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 90 uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled.
AnnaBridge 172:65be27845400 91 This parameter can be a value of @ref SDMMC_LL_Transceiver */
AnnaBridge 172:65be27845400 92 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 93
AnnaBridge 172:65be27845400 94 }SDMMC_InitTypeDef;
AnnaBridge 172:65be27845400 95
AnnaBridge 172:65be27845400 96
AnnaBridge 172:65be27845400 97 /**
AnnaBridge 172:65be27845400 98 * @brief SDMMC Command Control structure
AnnaBridge 172:65be27845400 99 */
AnnaBridge 172:65be27845400 100 typedef struct
AnnaBridge 172:65be27845400 101 {
AnnaBridge 172:65be27845400 102 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
AnnaBridge 172:65be27845400 103 to a card as part of a command message. If a command
AnnaBridge 172:65be27845400 104 contains an argument, it must be loaded into this register
AnnaBridge 172:65be27845400 105 before writing the command to the command register. */
AnnaBridge 172:65be27845400 106
AnnaBridge 172:65be27845400 107 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
AnnaBridge 172:65be27845400 108 Max_Data = 64 */
AnnaBridge 172:65be27845400 109
AnnaBridge 172:65be27845400 110 uint32_t Response; /*!< Specifies the SDMMC response type.
AnnaBridge 172:65be27845400 111 This parameter can be a value of @ref SDMMC_LL_Response_Type */
AnnaBridge 172:65be27845400 112
AnnaBridge 172:65be27845400 113 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
AnnaBridge 172:65be27845400 114 enabled or disabled.
AnnaBridge 172:65be27845400 115 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
AnnaBridge 172:65be27845400 116
AnnaBridge 172:65be27845400 117 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
AnnaBridge 172:65be27845400 118 is enabled or disabled.
AnnaBridge 172:65be27845400 119 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
AnnaBridge 172:65be27845400 120 }SDMMC_CmdInitTypeDef;
AnnaBridge 172:65be27845400 121
AnnaBridge 172:65be27845400 122
AnnaBridge 172:65be27845400 123 /**
AnnaBridge 172:65be27845400 124 * @brief SDMMC Data Control structure
AnnaBridge 172:65be27845400 125 */
AnnaBridge 172:65be27845400 126 typedef struct
AnnaBridge 172:65be27845400 127 {
AnnaBridge 172:65be27845400 128 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
AnnaBridge 172:65be27845400 129
AnnaBridge 172:65be27845400 130 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
AnnaBridge 172:65be27845400 131
AnnaBridge 172:65be27845400 132 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
AnnaBridge 172:65be27845400 133 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
AnnaBridge 172:65be27845400 134
AnnaBridge 172:65be27845400 135 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
AnnaBridge 172:65be27845400 136 is a read or write.
AnnaBridge 172:65be27845400 137 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
AnnaBridge 172:65be27845400 138
AnnaBridge 172:65be27845400 139 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
AnnaBridge 172:65be27845400 140 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
AnnaBridge 172:65be27845400 141
AnnaBridge 172:65be27845400 142 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
AnnaBridge 172:65be27845400 143 is enabled or disabled.
AnnaBridge 172:65be27845400 144 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
AnnaBridge 172:65be27845400 145 }SDMMC_DataInitTypeDef;
AnnaBridge 172:65be27845400 146
AnnaBridge 172:65be27845400 147 /**
AnnaBridge 172:65be27845400 148 * @}
AnnaBridge 172:65be27845400 149 */
AnnaBridge 172:65be27845400 150
AnnaBridge 172:65be27845400 151 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 152 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
AnnaBridge 172:65be27845400 153 * @{
AnnaBridge 172:65be27845400 154 */
AnnaBridge 172:65be27845400 155 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
AnnaBridge 172:65be27845400 156 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
AnnaBridge 172:65be27845400 157 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
AnnaBridge 172:65be27845400 158 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
AnnaBridge 172:65be27845400 159 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
AnnaBridge 172:65be27845400 160 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
AnnaBridge 172:65be27845400 161 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
AnnaBridge 172:65be27845400 162 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
AnnaBridge 172:65be27845400 163 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
AnnaBridge 172:65be27845400 164 number of transferred bytes does not match the block length */
AnnaBridge 172:65be27845400 165 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
AnnaBridge 172:65be27845400 166 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
AnnaBridge 172:65be27845400 167 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
AnnaBridge 172:65be27845400 168 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
AnnaBridge 172:65be27845400 169 command or if there was an attempt to access a locked card */
AnnaBridge 172:65be27845400 170 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
AnnaBridge 172:65be27845400 171 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
AnnaBridge 172:65be27845400 172 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
AnnaBridge 172:65be27845400 173 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
AnnaBridge 172:65be27845400 174 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
AnnaBridge 172:65be27845400 175 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
AnnaBridge 172:65be27845400 176 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
AnnaBridge 172:65be27845400 177 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
AnnaBridge 172:65be27845400 178 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
AnnaBridge 172:65be27845400 179 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
AnnaBridge 172:65be27845400 180 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
AnnaBridge 172:65be27845400 181 of erase sequence command was received */
AnnaBridge 172:65be27845400 182 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
AnnaBridge 172:65be27845400 183 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
AnnaBridge 172:65be27845400 184 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
AnnaBridge 172:65be27845400 185 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
AnnaBridge 172:65be27845400 186 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
AnnaBridge 172:65be27845400 187 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
AnnaBridge 172:65be27845400 188 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
AnnaBridge 172:65be27845400 189 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
AnnaBridge 172:65be27845400 190 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
AnnaBridge 172:65be27845400 191
AnnaBridge 172:65be27845400 192 /**
AnnaBridge 172:65be27845400 193 * @brief SDMMC Commands Index
AnnaBridge 172:65be27845400 194 */
AnnaBridge 172:65be27845400 195 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
AnnaBridge 172:65be27845400 196 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
AnnaBridge 172:65be27845400 197 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
AnnaBridge 172:65be27845400 198 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
AnnaBridge 172:65be27845400 199 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
AnnaBridge 172:65be27845400 200 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
AnnaBridge 172:65be27845400 201 operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge 172:65be27845400 202 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
AnnaBridge 172:65be27845400 203 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
AnnaBridge 172:65be27845400 204 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
AnnaBridge 172:65be27845400 205 and asks the card whether card supports voltage. */
AnnaBridge 172:65be27845400 206 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
AnnaBridge 172:65be27845400 207 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
AnnaBridge 172:65be27845400 208 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 209 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */
AnnaBridge 172:65be27845400 210 #else
AnnaBridge 172:65be27845400 211 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
AnnaBridge 172:65be27845400 212 #endif
AnnaBridge 172:65be27845400 213 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
AnnaBridge 172:65be27845400 214 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
AnnaBridge 172:65be27845400 215 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
AnnaBridge 172:65be27845400 216 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
AnnaBridge 172:65be27845400 217 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
AnnaBridge 172:65be27845400 218 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
AnnaBridge 172:65be27845400 219 for SDHS and SDXC. */
AnnaBridge 172:65be27845400 220 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge 172:65be27845400 221 fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge 172:65be27845400 222 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
AnnaBridge 172:65be27845400 223 STOP_TRANSMISSION command. */
AnnaBridge 172:65be27845400 224 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
AnnaBridge 172:65be27845400 225 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
AnnaBridge 172:65be27845400 226 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
AnnaBridge 172:65be27845400 227 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
AnnaBridge 172:65be27845400 228 fixed 512 bytes in case of SDHC and SDXC. */
AnnaBridge 172:65be27845400 229 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
AnnaBridge 172:65be27845400 230 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
AnnaBridge 172:65be27845400 231 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
AnnaBridge 172:65be27845400 232 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
AnnaBridge 172:65be27845400 233 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
AnnaBridge 172:65be27845400 234 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
AnnaBridge 172:65be27845400 235 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
AnnaBridge 172:65be27845400 236 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
AnnaBridge 172:65be27845400 237 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
AnnaBridge 172:65be27845400 238 system set by switch function command (CMD6). */
AnnaBridge 172:65be27845400 239 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
AnnaBridge 172:65be27845400 240 Reserved for each command system set by switch function command (CMD6). */
AnnaBridge 172:65be27845400 241 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
AnnaBridge 172:65be27845400 242 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
AnnaBridge 172:65be27845400 243 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
AnnaBridge 172:65be27845400 244 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
AnnaBridge 172:65be27845400 245 the SET_BLOCK_LEN command. */
AnnaBridge 172:65be27845400 246 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
AnnaBridge 172:65be27845400 247 than a standard command. */
AnnaBridge 172:65be27845400 248 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
AnnaBridge 172:65be27845400 249 for general purpose/application specific commands. */
AnnaBridge 172:65be27845400 250 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
AnnaBridge 172:65be27845400 251
AnnaBridge 172:65be27845400 252 /**
AnnaBridge 172:65be27845400 253 * @brief Following commands are SD Card Specific commands.
AnnaBridge 172:65be27845400 254 * SDMMC_APP_CMD should be sent before sending these commands.
AnnaBridge 172:65be27845400 255 */
AnnaBridge 172:65be27845400 256 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
AnnaBridge 172:65be27845400 257 widths are given in SCR register. */
AnnaBridge 172:65be27845400 258 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
AnnaBridge 172:65be27845400 259 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
AnnaBridge 172:65be27845400 260 32bit+CRC data block. */
AnnaBridge 172:65be27845400 261 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
AnnaBridge 172:65be27845400 262 send its operating condition register (OCR) content in the response on the CMD line. */
AnnaBridge 172:65be27845400 263 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
AnnaBridge 172:65be27845400 264 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
AnnaBridge 172:65be27845400 265 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
AnnaBridge 172:65be27845400 266 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
AnnaBridge 172:65be27845400 267
AnnaBridge 172:65be27845400 268 /**
AnnaBridge 172:65be27845400 269 * @brief Following commands are SD Card Specific security commands.
AnnaBridge 172:65be27845400 270 * SDMMC_CMD_APP_CMD should be sent before sending these commands.
AnnaBridge 172:65be27845400 271 */
AnnaBridge 172:65be27845400 272 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
AnnaBridge 172:65be27845400 273 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
AnnaBridge 172:65be27845400 274 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
AnnaBridge 172:65be27845400 275 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
AnnaBridge 172:65be27845400 276 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
AnnaBridge 172:65be27845400 277 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
AnnaBridge 172:65be27845400 278 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
AnnaBridge 172:65be27845400 279 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
AnnaBridge 172:65be27845400 280 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
AnnaBridge 172:65be27845400 281 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
AnnaBridge 172:65be27845400 282 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
AnnaBridge 172:65be27845400 283
AnnaBridge 172:65be27845400 284 /**
AnnaBridge 172:65be27845400 285 * @brief Masks for errors Card Status R1 (OCR Register)
AnnaBridge 172:65be27845400 286 */
AnnaBridge 172:65be27845400 287 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
AnnaBridge 172:65be27845400 288 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
AnnaBridge 172:65be27845400 289 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
AnnaBridge 172:65be27845400 290 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
AnnaBridge 172:65be27845400 291 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
AnnaBridge 172:65be27845400 292 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
AnnaBridge 172:65be27845400 293 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
AnnaBridge 172:65be27845400 294 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
AnnaBridge 172:65be27845400 295 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
AnnaBridge 172:65be27845400 296 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
AnnaBridge 172:65be27845400 297 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
AnnaBridge 172:65be27845400 298 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
AnnaBridge 172:65be27845400 299 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
AnnaBridge 172:65be27845400 300 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
AnnaBridge 172:65be27845400 301 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
AnnaBridge 172:65be27845400 302 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
AnnaBridge 172:65be27845400 303 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
AnnaBridge 172:65be27845400 304 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
AnnaBridge 172:65be27845400 305 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
AnnaBridge 172:65be27845400 306 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
AnnaBridge 172:65be27845400 307
AnnaBridge 172:65be27845400 308 /**
AnnaBridge 172:65be27845400 309 * @brief Masks for R6 Response
AnnaBridge 172:65be27845400 310 */
AnnaBridge 172:65be27845400 311 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
AnnaBridge 172:65be27845400 312 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
AnnaBridge 172:65be27845400 313 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
AnnaBridge 172:65be27845400 314
AnnaBridge 172:65be27845400 315 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
AnnaBridge 172:65be27845400 316 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
AnnaBridge 172:65be27845400 317 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 318 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
AnnaBridge 172:65be27845400 319 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 320 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U)
AnnaBridge 172:65be27845400 321 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U)
AnnaBridge 172:65be27845400 322 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U)
AnnaBridge 172:65be27845400 323 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 324
AnnaBridge 172:65be27845400 325 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge 172:65be27845400 326
AnnaBridge 172:65be27845400 327 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
AnnaBridge 172:65be27845400 328
AnnaBridge 172:65be27845400 329 #define SDMMC_ALLZERO ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 330
AnnaBridge 172:65be27845400 331 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
AnnaBridge 172:65be27845400 332 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
AnnaBridge 172:65be27845400 333 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
AnnaBridge 172:65be27845400 334
AnnaBridge 172:65be27845400 335 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
AnnaBridge 172:65be27845400 336
AnnaBridge 172:65be27845400 337 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
AnnaBridge 172:65be27845400 338 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
AnnaBridge 172:65be27845400 339 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
AnnaBridge 172:65be27845400 340 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
AnnaBridge 172:65be27845400 341 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
AnnaBridge 172:65be27845400 342
AnnaBridge 172:65be27845400 343 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
AnnaBridge 172:65be27845400 344 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
AnnaBridge 172:65be27845400 345
AnnaBridge 172:65be27845400 346 /**
AnnaBridge 172:65be27845400 347 * @brief Command Class supported
AnnaBridge 172:65be27845400 348 */
AnnaBridge 172:65be27845400 349 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
AnnaBridge 172:65be27845400 350
AnnaBridge 172:65be27845400 351 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
AnnaBridge 172:65be27845400 352 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
AnnaBridge 172:65be27845400 353 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */
AnnaBridge 172:65be27845400 354
AnnaBridge 172:65be27845400 355 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
AnnaBridge 172:65be27845400 356 * @{
AnnaBridge 172:65be27845400 357 */
AnnaBridge 172:65be27845400 358 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 359 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
AnnaBridge 172:65be27845400 360
AnnaBridge 172:65be27845400 361 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
AnnaBridge 172:65be27845400 362 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
AnnaBridge 172:65be27845400 363 /**
AnnaBridge 172:65be27845400 364 * @}
AnnaBridge 172:65be27845400 365 */
AnnaBridge 172:65be27845400 366
AnnaBridge 172:65be27845400 367 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 368 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
AnnaBridge 172:65be27845400 369 * @{
AnnaBridge 172:65be27845400 370 */
AnnaBridge 172:65be27845400 371 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 372 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
AnnaBridge 172:65be27845400 373
AnnaBridge 172:65be27845400 374 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
AnnaBridge 172:65be27845400 375 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
AnnaBridge 172:65be27845400 376 /**
AnnaBridge 172:65be27845400 377 * @}
AnnaBridge 172:65be27845400 378 */
AnnaBridge 172:65be27845400 379 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 380
AnnaBridge 172:65be27845400 381 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
AnnaBridge 172:65be27845400 382 * @{
AnnaBridge 172:65be27845400 383 */
AnnaBridge 172:65be27845400 384 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 385 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
AnnaBridge 172:65be27845400 386
AnnaBridge 172:65be27845400 387 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
AnnaBridge 172:65be27845400 388 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
AnnaBridge 172:65be27845400 389 /**
AnnaBridge 172:65be27845400 390 * @}
AnnaBridge 172:65be27845400 391 */
AnnaBridge 172:65be27845400 392
AnnaBridge 172:65be27845400 393 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
AnnaBridge 172:65be27845400 394 * @{
AnnaBridge 172:65be27845400 395 */
AnnaBridge 172:65be27845400 396 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 397 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
AnnaBridge 172:65be27845400 398 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
AnnaBridge 172:65be27845400 399
AnnaBridge 172:65be27845400 400 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
AnnaBridge 172:65be27845400 401 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
AnnaBridge 172:65be27845400 402 ((WIDE) == SDMMC_BUS_WIDE_8B))
AnnaBridge 172:65be27845400 403 /**
AnnaBridge 172:65be27845400 404 * @}
AnnaBridge 172:65be27845400 405 */
AnnaBridge 172:65be27845400 406
AnnaBridge 172:65be27845400 407 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
AnnaBridge 172:65be27845400 408 * @{
AnnaBridge 172:65be27845400 409 */
AnnaBridge 172:65be27845400 410 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 411 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
AnnaBridge 172:65be27845400 412
AnnaBridge 172:65be27845400 413 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
AnnaBridge 172:65be27845400 414 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
AnnaBridge 172:65be27845400 415 /**
AnnaBridge 172:65be27845400 416 * @}
AnnaBridge 172:65be27845400 417 */
AnnaBridge 172:65be27845400 418
AnnaBridge 172:65be27845400 419 /** @defgroup SDMMC_LL_Clock_Division Clock Division
AnnaBridge 172:65be27845400 420 * @{
AnnaBridge 172:65be27845400 421 */
AnnaBridge 172:65be27845400 422 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 423 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */
AnnaBridge 172:65be27845400 424 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400)
AnnaBridge 172:65be27845400 425 #else
AnnaBridge 172:65be27845400 426 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
AnnaBridge 172:65be27845400 427 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 428 /**
AnnaBridge 172:65be27845400 429 * @}
AnnaBridge 172:65be27845400 430 */
AnnaBridge 172:65be27845400 431
AnnaBridge 172:65be27845400 432
AnnaBridge 172:65be27845400 433 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 434 /** @defgroup SDMMC_LL_Transceiver Transceiver
AnnaBridge 172:65be27845400 435 * @{
AnnaBridge 172:65be27845400 436 */
AnnaBridge 172:65be27845400 437 #define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 438 #define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U)
AnnaBridge 172:65be27845400 439
AnnaBridge 172:65be27845400 440 #define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \
AnnaBridge 172:65be27845400 441 ((MODE) == SDMMC_TRANSCEIVER_ENABLE))
AnnaBridge 172:65be27845400 442 /**
AnnaBridge 172:65be27845400 443 * @}
AnnaBridge 172:65be27845400 444 */
AnnaBridge 172:65be27845400 445 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 446
AnnaBridge 172:65be27845400 447 /** @defgroup SDMMC_LL_Command_Index Command Index
AnnaBridge 172:65be27845400 448 * @{
AnnaBridge 172:65be27845400 449 */
AnnaBridge 172:65be27845400 450 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
AnnaBridge 172:65be27845400 451 /**
AnnaBridge 172:65be27845400 452 * @}
AnnaBridge 172:65be27845400 453 */
AnnaBridge 172:65be27845400 454
AnnaBridge 172:65be27845400 455 /** @defgroup SDMMC_LL_Response_Type Response Type
AnnaBridge 172:65be27845400 456 * @{
AnnaBridge 172:65be27845400 457 */
AnnaBridge 172:65be27845400 458 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 459 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
AnnaBridge 172:65be27845400 460 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
AnnaBridge 172:65be27845400 461
AnnaBridge 172:65be27845400 462 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
AnnaBridge 172:65be27845400 463 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
AnnaBridge 172:65be27845400 464 ((RESPONSE) == SDMMC_RESPONSE_LONG))
AnnaBridge 172:65be27845400 465 /**
AnnaBridge 172:65be27845400 466 * @}
AnnaBridge 172:65be27845400 467 */
AnnaBridge 172:65be27845400 468
AnnaBridge 172:65be27845400 469 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
AnnaBridge 172:65be27845400 470 * @{
AnnaBridge 172:65be27845400 471 */
AnnaBridge 172:65be27845400 472 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 473 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
AnnaBridge 172:65be27845400 474 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
AnnaBridge 172:65be27845400 475
AnnaBridge 172:65be27845400 476 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
AnnaBridge 172:65be27845400 477 ((WAIT) == SDMMC_WAIT_IT) || \
AnnaBridge 172:65be27845400 478 ((WAIT) == SDMMC_WAIT_PEND))
AnnaBridge 172:65be27845400 479 /**
AnnaBridge 172:65be27845400 480 * @}
AnnaBridge 172:65be27845400 481 */
AnnaBridge 172:65be27845400 482
AnnaBridge 172:65be27845400 483 /** @defgroup SDMMC_LL_CPSM_State CPSM State
AnnaBridge 172:65be27845400 484 * @{
AnnaBridge 172:65be27845400 485 */
AnnaBridge 172:65be27845400 486 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 487 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
AnnaBridge 172:65be27845400 488
AnnaBridge 172:65be27845400 489 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
AnnaBridge 172:65be27845400 490 ((CPSM) == SDMMC_CPSM_ENABLE))
AnnaBridge 172:65be27845400 491 /**
AnnaBridge 172:65be27845400 492 * @}
AnnaBridge 172:65be27845400 493 */
AnnaBridge 172:65be27845400 494
AnnaBridge 172:65be27845400 495 /** @defgroup SDMMC_LL_Response_Registers Response Register
AnnaBridge 172:65be27845400 496 * @{
AnnaBridge 172:65be27845400 497 */
AnnaBridge 172:65be27845400 498 #define SDMMC_RESP1 ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 499 #define SDMMC_RESP2 ((uint32_t)0x00000004U)
AnnaBridge 172:65be27845400 500 #define SDMMC_RESP3 ((uint32_t)0x00000008U)
AnnaBridge 172:65be27845400 501 #define SDMMC_RESP4 ((uint32_t)0x0000000CU)
AnnaBridge 172:65be27845400 502
AnnaBridge 172:65be27845400 503 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
AnnaBridge 172:65be27845400 504 ((RESP) == SDMMC_RESP2) || \
AnnaBridge 172:65be27845400 505 ((RESP) == SDMMC_RESP3) || \
AnnaBridge 172:65be27845400 506 ((RESP) == SDMMC_RESP4))
AnnaBridge 172:65be27845400 507
AnnaBridge 172:65be27845400 508 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 509 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode
AnnaBridge 172:65be27845400 510 * @{
AnnaBridge 172:65be27845400 511 */
AnnaBridge 172:65be27845400 512 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000)
AnnaBridge 172:65be27845400 513 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN)
AnnaBridge 172:65be27845400 514 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)
AnnaBridge 172:65be27845400 515 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)
AnnaBridge 172:65be27845400 516
AnnaBridge 172:65be27845400 517 /**
AnnaBridge 172:65be27845400 518 * @}
AnnaBridge 172:65be27845400 519 */
AnnaBridge 172:65be27845400 520 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 521 /**
AnnaBridge 172:65be27845400 522 * @}
AnnaBridge 172:65be27845400 523 */
AnnaBridge 172:65be27845400 524
AnnaBridge 172:65be27845400 525 /** @defgroup SDMMC_LL_Data_Length Data Lenght
AnnaBridge 172:65be27845400 526 * @{
AnnaBridge 172:65be27845400 527 */
AnnaBridge 172:65be27845400 528 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
AnnaBridge 172:65be27845400 529 /**
AnnaBridge 172:65be27845400 530 * @}
AnnaBridge 172:65be27845400 531 */
AnnaBridge 172:65be27845400 532
AnnaBridge 172:65be27845400 533 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
AnnaBridge 172:65be27845400 534 * @{
AnnaBridge 172:65be27845400 535 */
AnnaBridge 172:65be27845400 536 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 537 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
AnnaBridge 172:65be27845400 538 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
AnnaBridge 172:65be27845400 539 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
AnnaBridge 172:65be27845400 540 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
AnnaBridge 172:65be27845400 541 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge 172:65be27845400 542 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge 172:65be27845400 543 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
AnnaBridge 172:65be27845400 544 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
AnnaBridge 172:65be27845400 545 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge 172:65be27845400 546 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge 172:65be27845400 547 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge 172:65be27845400 548 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge 172:65be27845400 549 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge 172:65be27845400 550 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
AnnaBridge 172:65be27845400 551
AnnaBridge 172:65be27845400 552 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
AnnaBridge 172:65be27845400 553 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
AnnaBridge 172:65be27845400 554 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
AnnaBridge 172:65be27845400 555 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
AnnaBridge 172:65be27845400 556 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
AnnaBridge 172:65be27845400 557 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
AnnaBridge 172:65be27845400 558 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
AnnaBridge 172:65be27845400 559 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
AnnaBridge 172:65be27845400 560 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
AnnaBridge 172:65be27845400 561 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
AnnaBridge 172:65be27845400 562 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
AnnaBridge 172:65be27845400 563 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
AnnaBridge 172:65be27845400 564 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
AnnaBridge 172:65be27845400 565 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
AnnaBridge 172:65be27845400 566 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
AnnaBridge 172:65be27845400 567 /**
AnnaBridge 172:65be27845400 568 * @}
AnnaBridge 172:65be27845400 569 */
AnnaBridge 172:65be27845400 570
AnnaBridge 172:65be27845400 571 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
AnnaBridge 172:65be27845400 572 * @{
AnnaBridge 172:65be27845400 573 */
AnnaBridge 172:65be27845400 574 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 575 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
AnnaBridge 172:65be27845400 576
AnnaBridge 172:65be27845400 577 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
AnnaBridge 172:65be27845400 578 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
AnnaBridge 172:65be27845400 579 /**
AnnaBridge 172:65be27845400 580 * @}
AnnaBridge 172:65be27845400 581 */
AnnaBridge 172:65be27845400 582
AnnaBridge 172:65be27845400 583 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
AnnaBridge 172:65be27845400 584 * @{
AnnaBridge 172:65be27845400 585 */
AnnaBridge 172:65be27845400 586 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 587 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 588 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1
AnnaBridge 172:65be27845400 589 #else
AnnaBridge 172:65be27845400 590 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
AnnaBridge 172:65be27845400 591 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 592
AnnaBridge 172:65be27845400 593 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
AnnaBridge 172:65be27845400 594 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
AnnaBridge 172:65be27845400 595 /**
AnnaBridge 172:65be27845400 596 * @}
AnnaBridge 172:65be27845400 597 */
AnnaBridge 172:65be27845400 598
AnnaBridge 172:65be27845400 599 /** @defgroup SDMMC_LL_DPSM_State DPSM State
AnnaBridge 172:65be27845400 600 * @{
AnnaBridge 172:65be27845400 601 */
AnnaBridge 172:65be27845400 602 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 603 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
AnnaBridge 172:65be27845400 604
AnnaBridge 172:65be27845400 605 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
AnnaBridge 172:65be27845400 606 ((DPSM) == SDMMC_DPSM_ENABLE))
AnnaBridge 172:65be27845400 607 /**
AnnaBridge 172:65be27845400 608 * @}
AnnaBridge 172:65be27845400 609 */
AnnaBridge 172:65be27845400 610
AnnaBridge 172:65be27845400 611 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
AnnaBridge 172:65be27845400 612 * @{
AnnaBridge 172:65be27845400 613 */
AnnaBridge 172:65be27845400 614 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 615 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
AnnaBridge 172:65be27845400 616
AnnaBridge 172:65be27845400 617 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
AnnaBridge 172:65be27845400 618 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
AnnaBridge 172:65be27845400 619 /**
AnnaBridge 172:65be27845400 620 * @}
AnnaBridge 172:65be27845400 621 */
AnnaBridge 172:65be27845400 622
AnnaBridge 172:65be27845400 623 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
AnnaBridge 172:65be27845400 624 * @{
AnnaBridge 172:65be27845400 625 */
AnnaBridge 172:65be27845400 626 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE
AnnaBridge 172:65be27845400 627 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE
AnnaBridge 172:65be27845400 628 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE
AnnaBridge 172:65be27845400 629 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE
AnnaBridge 172:65be27845400 630 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE
AnnaBridge 172:65be27845400 631 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE
AnnaBridge 172:65be27845400 632 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE
AnnaBridge 172:65be27845400 633 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE
AnnaBridge 172:65be27845400 634 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE
AnnaBridge 172:65be27845400 635 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE
AnnaBridge 172:65be27845400 636 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE
AnnaBridge 172:65be27845400 637 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE
AnnaBridge 172:65be27845400 638 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE
AnnaBridge 172:65be27845400 639 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE
AnnaBridge 172:65be27845400 640 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE
AnnaBridge 172:65be27845400 641 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 642 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE
AnnaBridge 172:65be27845400 643 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE
AnnaBridge 172:65be27845400 644 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE
AnnaBridge 172:65be27845400 645 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE
AnnaBridge 172:65be27845400 646 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE
AnnaBridge 172:65be27845400 647 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE
AnnaBridge 172:65be27845400 648 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE
AnnaBridge 172:65be27845400 649 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE
AnnaBridge 172:65be27845400 650 #else
AnnaBridge 172:65be27845400 651 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE
AnnaBridge 172:65be27845400 652 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE
AnnaBridge 172:65be27845400 653 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE
AnnaBridge 172:65be27845400 654 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE
AnnaBridge 172:65be27845400 655 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE
AnnaBridge 172:65be27845400 656 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE
AnnaBridge 172:65be27845400 657 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE
AnnaBridge 172:65be27845400 658 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 659 /**
AnnaBridge 172:65be27845400 660 * @}
AnnaBridge 172:65be27845400 661 */
AnnaBridge 172:65be27845400 662
AnnaBridge 172:65be27845400 663 /** @defgroup SDMMC_LL_Flags Flags
AnnaBridge 172:65be27845400 664 * @{
AnnaBridge 172:65be27845400 665 */
AnnaBridge 172:65be27845400 666 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
AnnaBridge 172:65be27845400 667 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
AnnaBridge 172:65be27845400 668 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
AnnaBridge 172:65be27845400 669 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
AnnaBridge 172:65be27845400 670 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
AnnaBridge 172:65be27845400 671 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
AnnaBridge 172:65be27845400 672 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
AnnaBridge 172:65be27845400 673 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
AnnaBridge 172:65be27845400 674 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
AnnaBridge 172:65be27845400 675 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
AnnaBridge 172:65be27845400 676 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
AnnaBridge 172:65be27845400 677 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
AnnaBridge 172:65be27845400 678 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
AnnaBridge 172:65be27845400 679 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
AnnaBridge 172:65be27845400 680 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
AnnaBridge 172:65be27845400 681 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
AnnaBridge 172:65be27845400 682 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
AnnaBridge 172:65be27845400 683 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 684 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD
AnnaBridge 172:65be27845400 685 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT
AnnaBridge 172:65be27845400 686 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT
AnnaBridge 172:65be27845400 687 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT
AnnaBridge 172:65be27845400 688 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0
AnnaBridge 172:65be27845400 689 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END
AnnaBridge 172:65be27845400 690 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL
AnnaBridge 172:65be27845400 691 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT
AnnaBridge 172:65be27845400 692 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND
AnnaBridge 172:65be27845400 693 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP
AnnaBridge 172:65be27845400 694 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE
AnnaBridge 172:65be27845400 695 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC
AnnaBridge 172:65be27845400 696 #else
AnnaBridge 172:65be27845400 697 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
AnnaBridge 172:65be27845400 698 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
AnnaBridge 172:65be27845400 699 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
AnnaBridge 172:65be27845400 700 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
AnnaBridge 172:65be27845400 701 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
AnnaBridge 172:65be27845400 702 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 703
AnnaBridge 172:65be27845400 704 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 705 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
AnnaBridge 172:65be27845400 706 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
AnnaBridge 172:65be27845400 707 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
AnnaBridge 172:65be27845400 708 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\
AnnaBridge 172:65be27845400 709 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\
AnnaBridge 172:65be27845400 710 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\
AnnaBridge 172:65be27845400 711 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC))
AnnaBridge 172:65be27845400 712
AnnaBridge 172:65be27845400 713 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
AnnaBridge 172:65be27845400 714 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END))
AnnaBridge 172:65be27845400 715
AnnaBridge 172:65be27845400 716 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
AnnaBridge 172:65be27845400 717 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\
AnnaBridge 172:65be27845400 718 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\
AnnaBridge 172:65be27845400 719 SDMMC_FLAG_IDMABTC))
AnnaBridge 172:65be27845400 720
AnnaBridge 172:65be27845400 721 #else
AnnaBridge 172:65be27845400 722 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
AnnaBridge 172:65be27845400 723 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
AnnaBridge 172:65be27845400 724 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
AnnaBridge 172:65be27845400 725 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT))
AnnaBridge 172:65be27845400 726
AnnaBridge 172:65be27845400 727 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\
AnnaBridge 172:65be27845400 728 SDMMC_FLAG_CMDSENT))
AnnaBridge 172:65be27845400 729
AnnaBridge 172:65be27845400 730 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\
AnnaBridge 172:65be27845400 731 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND))
AnnaBridge 172:65be27845400 732 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 733
AnnaBridge 172:65be27845400 734 /**
AnnaBridge 172:65be27845400 735 * @}
AnnaBridge 172:65be27845400 736 */
AnnaBridge 172:65be27845400 737
AnnaBridge 172:65be27845400 738 /**
AnnaBridge 172:65be27845400 739 * @}
AnnaBridge 172:65be27845400 740 */
AnnaBridge 172:65be27845400 741
AnnaBridge 172:65be27845400 742 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 743 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
AnnaBridge 172:65be27845400 744 * @{
AnnaBridge 172:65be27845400 745 */
AnnaBridge 172:65be27845400 746
AnnaBridge 172:65be27845400 747 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
AnnaBridge 172:65be27845400 748 * @brief SDMMC_LL registers bit address in the alias region
AnnaBridge 172:65be27845400 749 * @{
AnnaBridge 172:65be27845400 750 */
AnnaBridge 172:65be27845400 751 /* ---------------------- SDMMC registers bit mask --------------------------- */
AnnaBridge 172:65be27845400 752 /* --- CLKCR Register ---*/
AnnaBridge 172:65be27845400 753 /* CLKCR register clear mask */
AnnaBridge 172:65be27845400 754 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 755 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
AnnaBridge 172:65be27845400 756 SDMMC_CLKCR_WIDBUS |\
AnnaBridge 172:65be27845400 757 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
AnnaBridge 172:65be27845400 758 #else
AnnaBridge 172:65be27845400 759 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
AnnaBridge 172:65be27845400 760 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
AnnaBridge 172:65be27845400 761 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
AnnaBridge 172:65be27845400 762 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 763
AnnaBridge 172:65be27845400 764 /* --- DCTRL Register ---*/
AnnaBridge 172:65be27845400 765 /* SDMMC DCTRL Clear Mask */
AnnaBridge 172:65be27845400 766 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
AnnaBridge 172:65be27845400 767 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
AnnaBridge 172:65be27845400 768
AnnaBridge 172:65be27845400 769 /* --- CMD Register ---*/
AnnaBridge 172:65be27845400 770 /* CMD Register clear mask */
AnnaBridge 172:65be27845400 771 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 772 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
AnnaBridge 172:65be27845400 773 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
AnnaBridge 172:65be27845400 774 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND))
AnnaBridge 172:65be27845400 775 #else
AnnaBridge 172:65be27845400 776 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
AnnaBridge 172:65be27845400 777 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
AnnaBridge 172:65be27845400 778 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
AnnaBridge 172:65be27845400 779 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 780
AnnaBridge 172:65be27845400 781 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 782 /* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge 172:65be27845400 783 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */
AnnaBridge 172:65be27845400 784
AnnaBridge 172:65be27845400 785 /* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge 172:65be27845400 786 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */
AnnaBridge 172:65be27845400 787 #else
AnnaBridge 172:65be27845400 788 /* SDMMC Initialization Frequency (400KHz max) */
AnnaBridge 172:65be27845400 789 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
AnnaBridge 172:65be27845400 790
AnnaBridge 172:65be27845400 791 /* SDMMC Data Transfer Frequency (25MHz max) */
AnnaBridge 172:65be27845400 792 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */
AnnaBridge 172:65be27845400 793 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 794
AnnaBridge 172:65be27845400 795 /**
AnnaBridge 172:65be27845400 796 * @}
AnnaBridge 172:65be27845400 797 */
AnnaBridge 172:65be27845400 798
AnnaBridge 172:65be27845400 799 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
AnnaBridge 172:65be27845400 800 * @brief macros to handle interrupts and specific clock configurations
AnnaBridge 172:65be27845400 801 * @{
AnnaBridge 172:65be27845400 802 */
AnnaBridge 172:65be27845400 803
AnnaBridge 172:65be27845400 804 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 805 /**
AnnaBridge 172:65be27845400 806 * @brief Enable the SDMMC device.
AnnaBridge 172:65be27845400 807 * @param __INSTANCE__: SDMMC Instance
AnnaBridge 172:65be27845400 808 * @retval None
AnnaBridge 172:65be27845400 809 */
AnnaBridge 172:65be27845400 810 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
AnnaBridge 172:65be27845400 811
AnnaBridge 172:65be27845400 812 /**
AnnaBridge 172:65be27845400 813 * @brief Disable the SDMMC device.
AnnaBridge 172:65be27845400 814 * @param __INSTANCE__: SDMMC Instance
AnnaBridge 172:65be27845400 815 * @retval None
AnnaBridge 172:65be27845400 816 */
AnnaBridge 172:65be27845400 817 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
AnnaBridge 172:65be27845400 818
AnnaBridge 172:65be27845400 819 /**
AnnaBridge 172:65be27845400 820 * @brief Enable the SDMMC DMA transfer.
AnnaBridge 172:65be27845400 821 * @param __INSTANCE__: SDMMC Instance
AnnaBridge 172:65be27845400 822 * @retval None
AnnaBridge 172:65be27845400 823 */
AnnaBridge 172:65be27845400 824 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
AnnaBridge 172:65be27845400 825 /**
AnnaBridge 172:65be27845400 826 * @brief Disable the SDMMC DMA transfer.
AnnaBridge 172:65be27845400 827 * @param __INSTANCE__: SDMMC Instance
AnnaBridge 172:65be27845400 828 * @retval None
AnnaBridge 172:65be27845400 829 */
AnnaBridge 172:65be27845400 830 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
AnnaBridge 172:65be27845400 831 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge 172:65be27845400 832
AnnaBridge 172:65be27845400 833 /**
AnnaBridge 172:65be27845400 834 * @brief Enable the SDMMC device interrupt.
AnnaBridge 172:65be27845400 835 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 836 * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
AnnaBridge 172:65be27845400 837 * This parameter can be one or a combination of the following values:
AnnaBridge 172:65be27845400 838 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 839 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 840 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge 172:65be27845400 841 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge 172:65be27845400 842 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge 172:65be27845400 843 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge 172:65be27845400 844 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 845 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge 172:65be27845400 846 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge 172:65be27845400 847 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 848 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge 172:65be27845400 849 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge 172:65be27845400 850 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge 172:65be27845400 851 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge 172:65be27845400 852 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge 172:65be27845400 853 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge 172:65be27845400 854 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge 172:65be27845400 855 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge 172:65be27845400 856 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge 172:65be27845400 857 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge 172:65be27845400 858 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge 172:65be27845400 859 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge 172:65be27845400 860 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge 172:65be27845400 861 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge 172:65be27845400 862 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge 172:65be27845400 863 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge 172:65be27845400 864 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge 172:65be27845400 865 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge 172:65be27845400 866 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge 172:65be27845400 867 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge 172:65be27845400 868 * @retval None
AnnaBridge 172:65be27845400 869 */
AnnaBridge 172:65be27845400 870 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
AnnaBridge 172:65be27845400 871
AnnaBridge 172:65be27845400 872 /**
AnnaBridge 172:65be27845400 873 * @brief Disable the SDMMC device interrupt.
AnnaBridge 172:65be27845400 874 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 875 * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
AnnaBridge 172:65be27845400 876 * This parameter can be one or a combination of the following values:
AnnaBridge 172:65be27845400 877 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 878 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 879 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge 172:65be27845400 880 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge 172:65be27845400 881 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge 172:65be27845400 882 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge 172:65be27845400 883 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 884 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge 172:65be27845400 885 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge 172:65be27845400 886 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 887 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge 172:65be27845400 888 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge 172:65be27845400 889 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge 172:65be27845400 890 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge 172:65be27845400 891 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge 172:65be27845400 892 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge 172:65be27845400 893 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge 172:65be27845400 894 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge 172:65be27845400 895 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge 172:65be27845400 896 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge 172:65be27845400 897 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge 172:65be27845400 898 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge 172:65be27845400 899 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge 172:65be27845400 900 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge 172:65be27845400 901 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge 172:65be27845400 902 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge 172:65be27845400 903 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge 172:65be27845400 904 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge 172:65be27845400 905 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge 172:65be27845400 906 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge 172:65be27845400 907 * @retval None
AnnaBridge 172:65be27845400 908 */
AnnaBridge 172:65be27845400 909 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
AnnaBridge 172:65be27845400 910
AnnaBridge 172:65be27845400 911 /**
AnnaBridge 172:65be27845400 912 * @brief Checks whether the specified SDMMC flag is set or not.
AnnaBridge 172:65be27845400 913 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 914 * @param __FLAG__: specifies the flag to check.
AnnaBridge 172:65be27845400 915 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 916 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge 172:65be27845400 917 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge 172:65be27845400 918 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge 172:65be27845400 919 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge 172:65be27845400 920 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge 172:65be27845400 921 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge 172:65be27845400 922 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge 172:65be27845400 923 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge 172:65be27845400 924 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge 172:65be27845400 925 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge 172:65be27845400 926 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
AnnaBridge 172:65be27845400 927 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
AnnaBridge 172:65be27845400 928 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
AnnaBridge 172:65be27845400 929 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
AnnaBridge 172:65be27845400 930 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
AnnaBridge 172:65be27845400 931 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
AnnaBridge 172:65be27845400 932 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
AnnaBridge 172:65be27845400 933 * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge 172:65be27845400 934 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge 172:65be27845400 935 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge 172:65be27845400 936 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge 172:65be27845400 937 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge 172:65be27845400 938 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge 172:65be27845400 939 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge 172:65be27845400 940 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge 172:65be27845400 941 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge 172:65be27845400 942 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge 172:65be27845400 943 * @arg SDMMC_FLAG_TXACT: Data transmit in progress
AnnaBridge 172:65be27845400 944 * @arg SDMMC_FLAG_RXACT: Data receive in progress
AnnaBridge 172:65be27845400 945 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
AnnaBridge 172:65be27845400 946 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
AnnaBridge 172:65be27845400 947 * @retval The new state of SDMMC_FLAG (SET or RESET).
AnnaBridge 172:65be27845400 948 */
AnnaBridge 172:65be27845400 949 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
AnnaBridge 172:65be27845400 950
AnnaBridge 172:65be27845400 951
AnnaBridge 172:65be27845400 952 /**
AnnaBridge 172:65be27845400 953 * @brief Clears the SDMMC pending flags.
AnnaBridge 172:65be27845400 954 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 955 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 172:65be27845400 956 * This parameter can be one or a combination of the following values:
AnnaBridge 172:65be27845400 957 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
AnnaBridge 172:65be27845400 958 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
AnnaBridge 172:65be27845400 959 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
AnnaBridge 172:65be27845400 960 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
AnnaBridge 172:65be27845400 961 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
AnnaBridge 172:65be27845400 962 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
AnnaBridge 172:65be27845400 963 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
AnnaBridge 172:65be27845400 964 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
AnnaBridge 172:65be27845400 965 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
AnnaBridge 172:65be27845400 966 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
AnnaBridge 172:65be27845400 967 * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
AnnaBridge 172:65be27845400 968 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold
AnnaBridge 172:65be27845400 969 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
AnnaBridge 172:65be27845400 970 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
AnnaBridge 172:65be27845400 971 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
AnnaBridge 172:65be27845400 972 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
AnnaBridge 172:65be27845400 973 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
AnnaBridge 172:65be27845400 974 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
AnnaBridge 172:65be27845400 975 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error
AnnaBridge 172:65be27845400 976 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
AnnaBridge 172:65be27845400 977 * @retval None
AnnaBridge 172:65be27845400 978 */
AnnaBridge 172:65be27845400 979 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
AnnaBridge 172:65be27845400 980
AnnaBridge 172:65be27845400 981 /**
AnnaBridge 172:65be27845400 982 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
AnnaBridge 172:65be27845400 983 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 984 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
AnnaBridge 172:65be27845400 985 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 986 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 987 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 988 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge 172:65be27845400 989 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge 172:65be27845400 990 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge 172:65be27845400 991 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge 172:65be27845400 992 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 993 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge 172:65be27845400 994 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
AnnaBridge 172:65be27845400 995 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 996 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
AnnaBridge 172:65be27845400 997 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
AnnaBridge 172:65be27845400 998 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
AnnaBridge 172:65be27845400 999 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
AnnaBridge 172:65be27845400 1000 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
AnnaBridge 172:65be27845400 1001 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
AnnaBridge 172:65be27845400 1002 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
AnnaBridge 172:65be27845400 1003 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge 172:65be27845400 1004 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge 172:65be27845400 1005 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge 172:65be27845400 1006 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge 172:65be27845400 1007 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge 172:65be27845400 1008 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge 172:65be27845400 1009 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge 172:65be27845400 1010 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge 172:65be27845400 1011 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge 172:65be27845400 1012 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
AnnaBridge 172:65be27845400 1013 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
AnnaBridge 172:65be27845400 1014 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
AnnaBridge 172:65be27845400 1015 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
AnnaBridge 172:65be27845400 1016 * @retval The new state of SDMMC_IT (SET or RESET).
AnnaBridge 172:65be27845400 1017 */
AnnaBridge 172:65be27845400 1018 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 172:65be27845400 1019
AnnaBridge 172:65be27845400 1020 /**
AnnaBridge 172:65be27845400 1021 * @brief Clears the SDMMC's interrupt pending bits.
AnnaBridge 172:65be27845400 1022 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1023 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge 172:65be27845400 1024 * This parameter can be one or a combination of the following values:
AnnaBridge 172:65be27845400 1025 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 1026 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
AnnaBridge 172:65be27845400 1027 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
AnnaBridge 172:65be27845400 1028 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
AnnaBridge 172:65be27845400 1029 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
AnnaBridge 172:65be27845400 1030 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
AnnaBridge 172:65be27845400 1031 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
AnnaBridge 172:65be27845400 1032 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
AnnaBridge 172:65be27845400 1033 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
AnnaBridge 172:65be27845400 1034 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
AnnaBridge 172:65be27845400 1035 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
AnnaBridge 172:65be27845400 1036 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
AnnaBridge 172:65be27845400 1037 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
AnnaBridge 172:65be27845400 1038 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
AnnaBridge 172:65be27845400 1039 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
AnnaBridge 172:65be27845400 1040 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
AnnaBridge 172:65be27845400 1041 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
AnnaBridge 172:65be27845400 1042 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
AnnaBridge 172:65be27845400 1043 * @retval None
AnnaBridge 172:65be27845400 1044 */
AnnaBridge 172:65be27845400 1045 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
AnnaBridge 172:65be27845400 1046
AnnaBridge 172:65be27845400 1047 /**
AnnaBridge 172:65be27845400 1048 * @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge 172:65be27845400 1049 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1050 * @retval None
AnnaBridge 172:65be27845400 1051 */
AnnaBridge 172:65be27845400 1052 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
AnnaBridge 172:65be27845400 1053
AnnaBridge 172:65be27845400 1054 /**
AnnaBridge 172:65be27845400 1055 * @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge 172:65be27845400 1056 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1057 * @retval None
AnnaBridge 172:65be27845400 1058 */
AnnaBridge 172:65be27845400 1059 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
AnnaBridge 172:65be27845400 1060
AnnaBridge 172:65be27845400 1061 /**
AnnaBridge 172:65be27845400 1062 * @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge 172:65be27845400 1063 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1064 * @retval None
AnnaBridge 172:65be27845400 1065 */
AnnaBridge 172:65be27845400 1066 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
AnnaBridge 172:65be27845400 1067
AnnaBridge 172:65be27845400 1068 /**
AnnaBridge 172:65be27845400 1069 * @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge 172:65be27845400 1070 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1071 * @retval None
AnnaBridge 172:65be27845400 1072 */
AnnaBridge 172:65be27845400 1073 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
AnnaBridge 172:65be27845400 1074
AnnaBridge 172:65be27845400 1075 /**
AnnaBridge 172:65be27845400 1076 * @brief Enable the SD I/O Mode Operation.
AnnaBridge 172:65be27845400 1077 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1078 * @retval None
AnnaBridge 172:65be27845400 1079 */
AnnaBridge 172:65be27845400 1080 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
AnnaBridge 172:65be27845400 1081
AnnaBridge 172:65be27845400 1082 /**
AnnaBridge 172:65be27845400 1083 * @brief Disable the SD I/O Mode Operation.
AnnaBridge 172:65be27845400 1084 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1085 * @retval None
AnnaBridge 172:65be27845400 1086 */
AnnaBridge 172:65be27845400 1087 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
AnnaBridge 172:65be27845400 1088
AnnaBridge 172:65be27845400 1089 /**
AnnaBridge 172:65be27845400 1090 * @brief Enable the SD I/O Suspend command sending.
AnnaBridge 172:65be27845400 1091 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1092 * @retval None
AnnaBridge 172:65be27845400 1093 */
AnnaBridge 172:65be27845400 1094 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 1095 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
AnnaBridge 172:65be27845400 1096 #else
AnnaBridge 172:65be27845400 1097 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)
AnnaBridge 172:65be27845400 1098 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge 172:65be27845400 1099
AnnaBridge 172:65be27845400 1100 /**
AnnaBridge 172:65be27845400 1101 * @brief Disable the SD I/O Suspend command sending.
AnnaBridge 172:65be27845400 1102 * @param __INSTANCE__: Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1103 * @retval None
AnnaBridge 172:65be27845400 1104 */
AnnaBridge 172:65be27845400 1105 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 1106 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
AnnaBridge 172:65be27845400 1107 #else
AnnaBridge 172:65be27845400 1108 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)
AnnaBridge 172:65be27845400 1109 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge 172:65be27845400 1110
AnnaBridge 172:65be27845400 1111 /**
AnnaBridge 172:65be27845400 1112 * @brief Enable the CMDTRANS mode.
AnnaBridge 172:65be27845400 1113 * @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1114 * @retval None
AnnaBridge 172:65be27845400 1115 */
AnnaBridge 172:65be27845400 1116 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)
AnnaBridge 172:65be27845400 1117
AnnaBridge 172:65be27845400 1118 /**
AnnaBridge 172:65be27845400 1119 * @brief Disable the CMDTRANS mode.
AnnaBridge 172:65be27845400 1120 * @param __INSTANCE__ : Pointer to SDMMC register base
AnnaBridge 172:65be27845400 1121 * @retval None
AnnaBridge 172:65be27845400 1122 */
AnnaBridge 172:65be27845400 1123 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)
AnnaBridge 172:65be27845400 1124 /**
AnnaBridge 172:65be27845400 1125 * @}
AnnaBridge 172:65be27845400 1126 */
AnnaBridge 172:65be27845400 1127
AnnaBridge 172:65be27845400 1128 /**
AnnaBridge 172:65be27845400 1129 * @}
AnnaBridge 172:65be27845400 1130 */
AnnaBridge 172:65be27845400 1131
AnnaBridge 172:65be27845400 1132 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 1133 /** @addtogroup SDMMC_LL_Exported_Functions
AnnaBridge 172:65be27845400 1134 * @{
AnnaBridge 172:65be27845400 1135 */
AnnaBridge 172:65be27845400 1136
AnnaBridge 172:65be27845400 1137 /* Initialization/de-initialization functions **********************************/
AnnaBridge 172:65be27845400 1138 /** @addtogroup HAL_SDMMC_LL_Group1
AnnaBridge 172:65be27845400 1139 * @{
AnnaBridge 172:65be27845400 1140 */
AnnaBridge 172:65be27845400 1141 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
AnnaBridge 172:65be27845400 1142 /**
AnnaBridge 172:65be27845400 1143 * @}
AnnaBridge 172:65be27845400 1144 */
AnnaBridge 172:65be27845400 1145
AnnaBridge 172:65be27845400 1146 /* I/O operation functions *****************************************************/
AnnaBridge 172:65be27845400 1147 /** @addtogroup HAL_SDMMC_LL_Group2
AnnaBridge 172:65be27845400 1148 * @{
AnnaBridge 172:65be27845400 1149 */
AnnaBridge 172:65be27845400 1150 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1151 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
AnnaBridge 172:65be27845400 1152 /**
AnnaBridge 172:65be27845400 1153 * @}
AnnaBridge 172:65be27845400 1154 */
AnnaBridge 172:65be27845400 1155
AnnaBridge 172:65be27845400 1156 /* Peripheral Control functions ************************************************/
AnnaBridge 172:65be27845400 1157 /** @addtogroup HAL_SDMMC_LL_Group3
AnnaBridge 172:65be27845400 1158 * @{
AnnaBridge 172:65be27845400 1159 */
AnnaBridge 172:65be27845400 1160 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1161 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 1162 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1163 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */
AnnaBridge 172:65be27845400 1164 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1165 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1166
AnnaBridge 172:65be27845400 1167 /* Command path state machine (CPSM) management functions */
AnnaBridge 172:65be27845400 1168 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
AnnaBridge 172:65be27845400 1169 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1170 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
AnnaBridge 172:65be27845400 1171
AnnaBridge 172:65be27845400 1172 /* Data path state machine (DPSM) management functions */
AnnaBridge 172:65be27845400 1173 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
AnnaBridge 172:65be27845400 1174 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1175 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1176
AnnaBridge 172:65be27845400 1177 /* SDMMC Cards mode management functions */
AnnaBridge 172:65be27845400 1178 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
AnnaBridge 172:65be27845400 1179
AnnaBridge 172:65be27845400 1180 /* SDMMC Commands management functions */
AnnaBridge 172:65be27845400 1181 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
AnnaBridge 172:65be27845400 1182 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge 172:65be27845400 1183 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
AnnaBridge 172:65be27845400 1184 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge 172:65be27845400 1185 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
AnnaBridge 172:65be27845400 1186 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge 172:65be27845400 1187 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
AnnaBridge 172:65be27845400 1188 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge 172:65be27845400 1189 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
AnnaBridge 172:65be27845400 1190 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1191 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1192 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
AnnaBridge 172:65be27845400 1193 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1194 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1195 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge 172:65be27845400 1196 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge 172:65be27845400 1197 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
AnnaBridge 172:65be27845400 1198 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1199 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1200 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge 172:65be27845400 1201 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
AnnaBridge 172:65be27845400 1202 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge 172:65be27845400 1203 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1204 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge 172:65be27845400 1205 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
AnnaBridge 172:65be27845400 1206 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 1207 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
AnnaBridge 172:65be27845400 1208 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 1209
AnnaBridge 172:65be27845400 1210 /**
AnnaBridge 172:65be27845400 1211 * @}
AnnaBridge 172:65be27845400 1212 */
AnnaBridge 172:65be27845400 1213
AnnaBridge 172:65be27845400 1214 /**
AnnaBridge 172:65be27845400 1215 * @}
AnnaBridge 172:65be27845400 1216 */
AnnaBridge 172:65be27845400 1217
AnnaBridge 172:65be27845400 1218 /**
AnnaBridge 172:65be27845400 1219 * @}
AnnaBridge 172:65be27845400 1220 */
AnnaBridge 172:65be27845400 1221
AnnaBridge 172:65be27845400 1222 /**
AnnaBridge 172:65be27845400 1223 * @}
AnnaBridge 172:65be27845400 1224 */
AnnaBridge 172:65be27845400 1225
AnnaBridge 172:65be27845400 1226 #endif /* SDMMC1 */
AnnaBridge 172:65be27845400 1227
AnnaBridge 172:65be27845400 1228 #ifdef __cplusplus
AnnaBridge 172:65be27845400 1229 }
AnnaBridge 172:65be27845400 1230 #endif
AnnaBridge 172:65be27845400 1231
AnnaBridge 172:65be27845400 1232 #endif /* __STM32L4xx_LL_SDMMC_H */
AnnaBridge 172:65be27845400 1233
AnnaBridge 172:65be27845400 1234 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/