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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_hal_ospi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_hal_ospi.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of OSPI HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 12 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 14 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 17 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 19 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 20 * without specific prior written permission.
AnnaBridge 172:65be27845400 21 *
AnnaBridge 172:65be27845400 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 32 *
AnnaBridge 172:65be27845400 33 ******************************************************************************
AnnaBridge 172:65be27845400 34 */
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 37 #ifndef __STM32L4xx_HAL_OSPI_H
AnnaBridge 172:65be27845400 38 #define __STM32L4xx_HAL_OSPI_H
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 #ifdef __cplusplus
AnnaBridge 172:65be27845400 41 extern "C" {
AnnaBridge 172:65be27845400 42 #endif
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 45 #include "stm32l4xx_hal_def.h"
AnnaBridge 172:65be27845400 46
AnnaBridge 172:65be27845400 47 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
AnnaBridge 172:65be27845400 48
AnnaBridge 172:65be27845400 49 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 172:65be27845400 50 * @{
AnnaBridge 172:65be27845400 51 */
AnnaBridge 172:65be27845400 52
AnnaBridge 172:65be27845400 53 /** @addtogroup OSPI
AnnaBridge 172:65be27845400 54 * @{
AnnaBridge 172:65be27845400 55 */
AnnaBridge 172:65be27845400 56
AnnaBridge 172:65be27845400 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 58 /** @defgroup OSPI_Exported_Types OSPI Exported Types
AnnaBridge 172:65be27845400 59 * @{
AnnaBridge 172:65be27845400 60 */
AnnaBridge 172:65be27845400 61
AnnaBridge 172:65be27845400 62 /**
AnnaBridge 172:65be27845400 63 * @brief OSPI Init structure definition
AnnaBridge 172:65be27845400 64 */
AnnaBridge 172:65be27845400 65 typedef struct
AnnaBridge 172:65be27845400 66 {
AnnaBridge 172:65be27845400 67 uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt
AnnaBridge 172:65be27845400 68 indicating that data are available in reception or free place
AnnaBridge 172:65be27845400 69 is available in transmission.
AnnaBridge 172:65be27845400 70 This parameter can be a value between 1 and 32 */
AnnaBridge 172:65be27845400 71 uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to
AnnaBridge 172:65be27845400 72 quad mode on two different devices to increase the throughput.
AnnaBridge 172:65be27845400 73 This parameter can be a value of @ref OSPI_DualQuad */
AnnaBridge 172:65be27845400 74 uint32_t MemoryType; /* It indicates the external device type connected to the OSPI.
AnnaBridge 172:65be27845400 75 This parameter can be a value of @ref OSPI_MemoryType */
AnnaBridge 172:65be27845400 76 uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI,
AnnaBridge 172:65be27845400 77 it corresponds to the number of address bits required to access
AnnaBridge 172:65be27845400 78 the external device.
AnnaBridge 172:65be27845400 79 This parameter can be a value between 1 and 32 */
AnnaBridge 172:65be27845400 80 uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select
AnnaBridge 172:65be27845400 81 must remain high between commands.
AnnaBridge 172:65be27845400 82 This parameter can be a value between 1 and 8 */
AnnaBridge 172:65be27845400 83 uint32_t FreeRunningClock; /* It enables or not the free running clock.
AnnaBridge 172:65be27845400 84 This parameter can be a value of @ref OSPI_FreeRunningClock */
AnnaBridge 172:65be27845400 85 uint32_t ClockMode; /* It indicates the level of clock when the chip select is released.
AnnaBridge 172:65be27845400 86 This parameter can be a value of @ref OSPI_ClockMode */
AnnaBridge 172:65be27845400 87 uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration.
AnnaBridge 172:65be27845400 88 This parameter can be a value of @ref OSPI_WrapSize */
AnnaBridge 172:65be27845400 89 uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating
AnnaBridge 172:65be27845400 90 the external clock based on the AHB clock.
AnnaBridge 172:65be27845400 91 This parameter can be a value between 1 and 256 */
AnnaBridge 172:65be27845400 92 uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order
AnnaBridge 172:65be27845400 93 to take in account external signal delays.
AnnaBridge 172:65be27845400 94 This parameter can be a value of @ref OSPI_SampleShifting */
AnnaBridge 172:65be27845400 95 uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data.
AnnaBridge 172:65be27845400 96 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
AnnaBridge 172:65be27845400 97 uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and
AnnaBridge 172:65be27845400 98 defines the boundary of bytes to release the chip select.
AnnaBridge 172:65be27845400 99 This parameter can be a value between 0 and 31 */
AnnaBridge 172:65be27845400 100 }OSPI_InitTypeDef;
AnnaBridge 172:65be27845400 101
AnnaBridge 172:65be27845400 102 /**
AnnaBridge 172:65be27845400 103 * @brief HAL OSPI Handle Structure definition
AnnaBridge 172:65be27845400 104 */
AnnaBridge 172:65be27845400 105 typedef struct
AnnaBridge 172:65be27845400 106 {
AnnaBridge 172:65be27845400 107 OCTOSPI_TypeDef *Instance; /* OSPI registers base address */
AnnaBridge 172:65be27845400 108 OSPI_InitTypeDef Init; /* OSPI initialization parameters */
AnnaBridge 172:65be27845400 109 uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */
AnnaBridge 172:65be27845400 110 __IO uint32_t XferSize; /* Number of data to transfer */
AnnaBridge 172:65be27845400 111 __IO uint32_t XferCount; /* Counter of data transferred */
AnnaBridge 172:65be27845400 112 DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */
AnnaBridge 172:65be27845400 113 __IO uint32_t State; /* Internal state of the OSPI HAL driver */
AnnaBridge 172:65be27845400 114 __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */
AnnaBridge 172:65be27845400 115 uint32_t Timeout; /* Timeout used for the OSPI external device access */
AnnaBridge 172:65be27845400 116 }OSPI_HandleTypeDef;
AnnaBridge 172:65be27845400 117
AnnaBridge 172:65be27845400 118 /**
AnnaBridge 172:65be27845400 119 * @brief HAL OSPI Regular Command Structure definition
AnnaBridge 172:65be27845400 120 */
AnnaBridge 172:65be27845400 121 typedef struct
AnnaBridge 172:65be27845400 122 {
AnnaBridge 172:65be27845400 123 uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or
AnnaBridge 172:65be27845400 124 to the registers for the write operation (these registers are only
AnnaBridge 172:65be27845400 125 used for memory-mapped mode).
AnnaBridge 172:65be27845400 126 This parameter can be a value of @ref OSPI_OperationType */
AnnaBridge 172:65be27845400 127 uint32_t FlashId; /* It indicates which external device is selected for this command (it
AnnaBridge 172:65be27845400 128 applies only if Dualquad is disabled in the initialization structure).
AnnaBridge 172:65be27845400 129 This parameter can be a value of @ref OSPI_FlashId */
AnnaBridge 172:65be27845400 130 uint32_t Instruction; /* It contains the instruction to be sent to the device.
AnnaBridge 172:65be27845400 131 This parameter can be a value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 132 uint32_t InstructionMode; /* It indicates the mode of the instruction.
AnnaBridge 172:65be27845400 133 This parameter can be a value of @ref OSPI_InstructionMode */
AnnaBridge 172:65be27845400 134 uint32_t InstructionSize; /* It indicates the size of the instruction.
AnnaBridge 172:65be27845400 135 This parameter can be a value of @ref OSPI_InstructionSize */
AnnaBridge 172:65be27845400 136 uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase.
AnnaBridge 172:65be27845400 137 This parameter can be a value of @ref OSPI_InstructionDtrMode */
AnnaBridge 172:65be27845400 138 uint32_t Address; /* It contains the address to be sent to the device.
AnnaBridge 172:65be27845400 139 This parameter can be a value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 140 uint32_t AddressMode; /* It indicates the mode of the address.
AnnaBridge 172:65be27845400 141 This parameter can be a value of @ref OSPI_AddressMode */
AnnaBridge 172:65be27845400 142 uint32_t AddressSize; /* It indicates the size of the address.
AnnaBridge 172:65be27845400 143 This parameter can be a value of @ref OSPI_AddressSize */
AnnaBridge 172:65be27845400 144 uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase.
AnnaBridge 172:65be27845400 145 This parameter can be a value of @ref OSPI_AddressDtrMode */
AnnaBridge 172:65be27845400 146 uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device.
AnnaBridge 172:65be27845400 147 This parameter can be a value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 148 uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes.
AnnaBridge 172:65be27845400 149 This parameter can be a value of @ref OSPI_AlternateBytesMode */
AnnaBridge 172:65be27845400 150 uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes.
AnnaBridge 172:65be27845400 151 This parameter can be a value of @ref OSPI_AlternateBytesSize */
AnnaBridge 172:65be27845400 152 uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase.
AnnaBridge 172:65be27845400 153 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
AnnaBridge 172:65be27845400 154 uint32_t DataMode; /* It indicates the mode of the data.
AnnaBridge 172:65be27845400 155 This parameter can be a value of @ref OSPI_DataMode */
AnnaBridge 172:65be27845400 156 uint32_t NbData; /* It indicates the number of data transferred with this command.
AnnaBridge 172:65be27845400 157 This field is only used for indirect mode.
AnnaBridge 172:65be27845400 158 This parameter can be a value between 1 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 159 uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase.
AnnaBridge 172:65be27845400 160 This parameter can be a value of @ref OSPI_DataDtrMode */
AnnaBridge 172:65be27845400 161 uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase.
AnnaBridge 172:65be27845400 162 This parameter can be a value between 0 and 31 */
AnnaBridge 172:65be27845400 163 uint32_t DQSMode; /* It enables or not the data strobe management.
AnnaBridge 172:65be27845400 164 This parameter can be a value of @ref OSPI_DQSMode */
AnnaBridge 172:65be27845400 165 uint32_t SIOOMode; /* It enables or not the SIOO mode.
AnnaBridge 172:65be27845400 166 This parameter can be a value of @ref OSPI_SIOOMode */
AnnaBridge 172:65be27845400 167 }OSPI_RegularCmdTypeDef;
AnnaBridge 172:65be27845400 168
AnnaBridge 172:65be27845400 169 /**
AnnaBridge 172:65be27845400 170 * @brief HAL OSPI Hyperbus Configuration Structure definition
AnnaBridge 172:65be27845400 171 */
AnnaBridge 172:65be27845400 172 typedef struct
AnnaBridge 172:65be27845400 173 {
AnnaBridge 172:65be27845400 174 uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time.
AnnaBridge 172:65be27845400 175 This parameter can be a value between 0 and 255 */
AnnaBridge 172:65be27845400 176 uint32_t AccessTime; /* It indicates the number of cycles for the device acces time.
AnnaBridge 172:65be27845400 177 This parameter can be a value between 0 and 255 */
AnnaBridge 172:65be27845400 178 uint32_t WriteZeroLatency; /* It enables or not the latency for the write access.
AnnaBridge 172:65be27845400 179 This parameter can be a value of @ref OSPI_WriteZeroLatency */
AnnaBridge 172:65be27845400 180 uint32_t LatencyMode; /* It configures the latency mode.
AnnaBridge 172:65be27845400 181 This parameter can be a value of @ref OSPI_LatencyMode */
AnnaBridge 172:65be27845400 182 }OSPI_HyperbusCfgTypeDef;
AnnaBridge 172:65be27845400 183
AnnaBridge 172:65be27845400 184 /**
AnnaBridge 172:65be27845400 185 * @brief HAL OSPI Hyperbus Command Structure definition
AnnaBridge 172:65be27845400 186 */
AnnaBridge 172:65be27845400 187 typedef struct
AnnaBridge 172:65be27845400 188 {
AnnaBridge 172:65be27845400 189 uint32_t AddressSpace; /* It indicates the address space accessed by the command.
AnnaBridge 172:65be27845400 190 This parameter can be a value of @ref OSPI_AddressSpace */
AnnaBridge 172:65be27845400 191 uint32_t Address; /* It contains the address to be sent tot he device.
AnnaBridge 172:65be27845400 192 This parameter can be a value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 193 uint32_t AddressSize; /* It indicates the size of the address.
AnnaBridge 172:65be27845400 194 This parameter can be a value of @ref OSPI_AddressSize */
AnnaBridge 172:65be27845400 195 uint32_t NbData; /* It indicates the number of data transferred with this command.
AnnaBridge 172:65be27845400 196 This field is only used for indirect mode.
AnnaBridge 172:65be27845400 197 This parameter can be a value between 1 and 0xFFFFFFFF
AnnaBridge 172:65be27845400 198 In case of autopolling mode, this parameter can be any value between 1 and 4 */
AnnaBridge 172:65be27845400 199 uint32_t DQSMode; /* It enables or not the data strobe management.
AnnaBridge 172:65be27845400 200 This parameter can be a value of @ref OSPI_DQSMode */
AnnaBridge 172:65be27845400 201 }OSPI_HyperbusCmdTypeDef;
AnnaBridge 172:65be27845400 202
AnnaBridge 172:65be27845400 203 /**
AnnaBridge 172:65be27845400 204 * @brief HAL OSPI Auto Polling mode configuration structure definition
AnnaBridge 172:65be27845400 205 */
AnnaBridge 172:65be27845400 206 typedef struct
AnnaBridge 172:65be27845400 207 {
AnnaBridge 172:65be27845400 208 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
AnnaBridge 172:65be27845400 209 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 210 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
AnnaBridge 172:65be27845400 211 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 172:65be27845400 212 uint32_t MatchMode; /* Specifies the method used for determining a match.
AnnaBridge 172:65be27845400 213 This parameter can be a value of @ref OSPI_MatchMode */
AnnaBridge 172:65be27845400 214 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
AnnaBridge 172:65be27845400 215 This parameter can be a value of @ref OSPI_AutomaticStop */
AnnaBridge 172:65be27845400 216 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
AnnaBridge 172:65be27845400 217 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 172:65be27845400 218 }OSPI_AutoPollingTypeDef;
AnnaBridge 172:65be27845400 219
AnnaBridge 172:65be27845400 220 /**
AnnaBridge 172:65be27845400 221 * @brief HAL OSPI Memory Mapped mode configuration structure definition
AnnaBridge 172:65be27845400 222 */
AnnaBridge 172:65be27845400 223 typedef struct
AnnaBridge 172:65be27845400 224 {
AnnaBridge 172:65be27845400 225 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
AnnaBridge 172:65be27845400 226 This parameter can be a value of @ref OSPI_TimeOutActivation */
AnnaBridge 172:65be27845400 227 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
AnnaBridge 172:65be27845400 228 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 172:65be27845400 229 }OSPI_MemoryMappedTypeDef;
AnnaBridge 172:65be27845400 230
AnnaBridge 172:65be27845400 231 /**
AnnaBridge 172:65be27845400 232 * @brief HAL OSPI IO Manager Configuration structure definition
AnnaBridge 172:65be27845400 233 */
AnnaBridge 172:65be27845400 234 typedef struct
AnnaBridge 172:65be27845400 235 {
AnnaBridge 172:65be27845400 236 uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins.
AnnaBridge 172:65be27845400 237 This parameter can be a value between 1 and 8 */
AnnaBridge 172:65be27845400 238 uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin.
AnnaBridge 172:65be27845400 239 This parameter can be a value between 1 and 8 */
AnnaBridge 172:65be27845400 240 uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin.
AnnaBridge 172:65be27845400 241 This parameter can be a value between 1 and 8 */
AnnaBridge 172:65be27845400 242 uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.
AnnaBridge 172:65be27845400 243 This parameter can be a value of @ref OSPIM_IOPort */
AnnaBridge 172:65be27845400 244 uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
AnnaBridge 172:65be27845400 245 This parameter can be a value of @ref OSPIM_IOPort */
AnnaBridge 172:65be27845400 246 }OSPIM_CfgTypeDef;
AnnaBridge 172:65be27845400 247
AnnaBridge 172:65be27845400 248 /**
AnnaBridge 172:65be27845400 249 * @}
AnnaBridge 172:65be27845400 250 */
AnnaBridge 172:65be27845400 251
AnnaBridge 172:65be27845400 252 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 253 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants
AnnaBridge 172:65be27845400 254 * @{
AnnaBridge 172:65be27845400 255 */
AnnaBridge 172:65be27845400 256
AnnaBridge 172:65be27845400 257 /** @defgroup OSPI_State OSPI State
AnnaBridge 172:65be27845400 258 * @{
AnnaBridge 172:65be27845400 259 */
AnnaBridge 172:65be27845400 260 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */
AnnaBridge 172:65be27845400 261 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */
AnnaBridge 172:65be27845400 262 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */
AnnaBridge 172:65be27845400 263 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */
AnnaBridge 172:65be27845400 264 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */
AnnaBridge 172:65be27845400 265 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */
AnnaBridge 172:65be27845400 266 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */
AnnaBridge 172:65be27845400 267 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */
AnnaBridge 172:65be27845400 268 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */
AnnaBridge 172:65be27845400 269 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */
AnnaBridge 172:65be27845400 270 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */
AnnaBridge 172:65be27845400 271 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */
AnnaBridge 172:65be27845400 272 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */
AnnaBridge 172:65be27845400 273 /**
AnnaBridge 172:65be27845400 274 * @}
AnnaBridge 172:65be27845400 275 */
AnnaBridge 172:65be27845400 276
AnnaBridge 172:65be27845400 277 /** @defgroup OSPI_ErrorCode OSPI Error Code
AnnaBridge 172:65be27845400 278 * @{
AnnaBridge 172:65be27845400 279 */
AnnaBridge 172:65be27845400 280 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
AnnaBridge 172:65be27845400 281 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
AnnaBridge 172:65be27845400 282 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
AnnaBridge 172:65be27845400 283 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
AnnaBridge 172:65be27845400 284 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
AnnaBridge 172:65be27845400 285 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */
AnnaBridge 172:65be27845400 286 /**
AnnaBridge 172:65be27845400 287 * @}
AnnaBridge 172:65be27845400 288 */
AnnaBridge 172:65be27845400 289
AnnaBridge 172:65be27845400 290 /** @defgroup OSPI_DualQuad OSPI Dual-Quad
AnnaBridge 172:65be27845400 291 * @{
AnnaBridge 172:65be27845400 292 */
AnnaBridge 172:65be27845400 293 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */
AnnaBridge 172:65be27845400 294 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */
AnnaBridge 172:65be27845400 295 /**
AnnaBridge 172:65be27845400 296 * @}
AnnaBridge 172:65be27845400 297 */
AnnaBridge 172:65be27845400 298
AnnaBridge 172:65be27845400 299 /** @defgroup OSPI_MemoryType OSPI Memory Type
AnnaBridge 172:65be27845400 300 * @{
AnnaBridge 172:65be27845400 301 */
AnnaBridge 172:65be27845400 302 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */
AnnaBridge 172:65be27845400 303 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */
AnnaBridge 172:65be27845400 304 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */
AnnaBridge 172:65be27845400 305 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
AnnaBridge 172:65be27845400 306 /**
AnnaBridge 172:65be27845400 307 * @}
AnnaBridge 172:65be27845400 308 */
AnnaBridge 172:65be27845400 309
AnnaBridge 172:65be27845400 310 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock
AnnaBridge 172:65be27845400 311 * @{
AnnaBridge 172:65be27845400 312 */
AnnaBridge 172:65be27845400 313 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */
AnnaBridge 172:65be27845400 314 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */
AnnaBridge 172:65be27845400 315 /**
AnnaBridge 172:65be27845400 316 * @}
AnnaBridge 172:65be27845400 317 */
AnnaBridge 172:65be27845400 318
AnnaBridge 172:65be27845400 319 /** @defgroup OSPI_ClockMode OSPI Clock Mode
AnnaBridge 172:65be27845400 320 * @{
AnnaBridge 172:65be27845400 321 */
AnnaBridge 172:65be27845400 322 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */
AnnaBridge 172:65be27845400 323 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */
AnnaBridge 172:65be27845400 324 /**
AnnaBridge 172:65be27845400 325 * @}
AnnaBridge 172:65be27845400 326 */
AnnaBridge 172:65be27845400 327
AnnaBridge 172:65be27845400 328 /** @defgroup OSPI_WrapSize OSPI Wrap-Size
AnnaBridge 172:65be27845400 329 * @{
AnnaBridge 172:65be27845400 330 */
AnnaBridge 172:65be27845400 331 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */
AnnaBridge 172:65be27845400 332 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */
AnnaBridge 172:65be27845400 333 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */
AnnaBridge 172:65be27845400 334 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */
AnnaBridge 172:65be27845400 335 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */
AnnaBridge 172:65be27845400 336 /**
AnnaBridge 172:65be27845400 337 * @}
AnnaBridge 172:65be27845400 338 */
AnnaBridge 172:65be27845400 339
AnnaBridge 172:65be27845400 340 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting
AnnaBridge 172:65be27845400 341 * @{
AnnaBridge 172:65be27845400 342 */
AnnaBridge 172:65be27845400 343 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */
AnnaBridge 172:65be27845400 344 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */
AnnaBridge 172:65be27845400 345 /**
AnnaBridge 172:65be27845400 346 * @}
AnnaBridge 172:65be27845400 347 */
AnnaBridge 172:65be27845400 348
AnnaBridge 172:65be27845400 349 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle
AnnaBridge 172:65be27845400 350 * @{
AnnaBridge 172:65be27845400 351 */
AnnaBridge 172:65be27845400 352 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */
AnnaBridge 172:65be27845400 353 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */
AnnaBridge 172:65be27845400 354 /**
AnnaBridge 172:65be27845400 355 * @}
AnnaBridge 172:65be27845400 356 */
AnnaBridge 172:65be27845400 357
AnnaBridge 172:65be27845400 358 /** @defgroup OSPI_OperationType OSPI Operation Type
AnnaBridge 172:65be27845400 359 * @{
AnnaBridge 172:65be27845400 360 */
AnnaBridge 172:65be27845400 361 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
AnnaBridge 172:65be27845400 362 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */
AnnaBridge 172:65be27845400 363 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */
AnnaBridge 172:65be27845400 364 /**
AnnaBridge 172:65be27845400 365 * @}
AnnaBridge 172:65be27845400 366 */
AnnaBridge 172:65be27845400 367
AnnaBridge 172:65be27845400 368 /** @defgroup OSPI_FlashID OSPI Flash Id
AnnaBridge 172:65be27845400 369 * @{
AnnaBridge 172:65be27845400 370 */
AnnaBridge 172:65be27845400 371 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */
AnnaBridge 172:65be27845400 372 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */
AnnaBridge 172:65be27845400 373 /**
AnnaBridge 172:65be27845400 374 * @}
AnnaBridge 172:65be27845400 375 */
AnnaBridge 172:65be27845400 376
AnnaBridge 172:65be27845400 377 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode
AnnaBridge 172:65be27845400 378 * @{
AnnaBridge 172:65be27845400 379 */
AnnaBridge 172:65be27845400 380 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */
AnnaBridge 172:65be27845400 381 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */
AnnaBridge 172:65be27845400 382 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */
AnnaBridge 172:65be27845400 383 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */
AnnaBridge 172:65be27845400 384 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */
AnnaBridge 172:65be27845400 385 /**
AnnaBridge 172:65be27845400 386 * @}
AnnaBridge 172:65be27845400 387 */
AnnaBridge 172:65be27845400 388
AnnaBridge 172:65be27845400 389 /** @defgroup OSPI_InstructionSize OSPI Instruction Size
AnnaBridge 172:65be27845400 390 * @{
AnnaBridge 172:65be27845400 391 */
AnnaBridge 172:65be27845400 392 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */
AnnaBridge 172:65be27845400 393 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */
AnnaBridge 172:65be27845400 394 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */
AnnaBridge 172:65be27845400 395 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */
AnnaBridge 172:65be27845400 396 /**
AnnaBridge 172:65be27845400 397 * @}
AnnaBridge 172:65be27845400 398 */
AnnaBridge 172:65be27845400 399
AnnaBridge 172:65be27845400 400 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode
AnnaBridge 172:65be27845400 401 * @{
AnnaBridge 172:65be27845400 402 */
AnnaBridge 172:65be27845400 403 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */
AnnaBridge 172:65be27845400 404 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */
AnnaBridge 172:65be27845400 405 /**
AnnaBridge 172:65be27845400 406 * @}
AnnaBridge 172:65be27845400 407 */
AnnaBridge 172:65be27845400 408
AnnaBridge 172:65be27845400 409 /** @defgroup OSPI_AddressMode OSPI Address Mode
AnnaBridge 172:65be27845400 410 * @{
AnnaBridge 172:65be27845400 411 */
AnnaBridge 172:65be27845400 412 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */
AnnaBridge 172:65be27845400 413 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */
AnnaBridge 172:65be27845400 414 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */
AnnaBridge 172:65be27845400 415 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */
AnnaBridge 172:65be27845400 416 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */
AnnaBridge 172:65be27845400 417 /**
AnnaBridge 172:65be27845400 418 * @}
AnnaBridge 172:65be27845400 419 */
AnnaBridge 172:65be27845400 420
AnnaBridge 172:65be27845400 421 /** @defgroup OSPI_AddressSize OSPI Address Size
AnnaBridge 172:65be27845400 422 * @{
AnnaBridge 172:65be27845400 423 */
AnnaBridge 172:65be27845400 424 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */
AnnaBridge 172:65be27845400 425 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */
AnnaBridge 172:65be27845400 426 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */
AnnaBridge 172:65be27845400 427 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */
AnnaBridge 172:65be27845400 428 /**
AnnaBridge 172:65be27845400 429 * @}
AnnaBridge 172:65be27845400 430 */
AnnaBridge 172:65be27845400 431
AnnaBridge 172:65be27845400 432 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode
AnnaBridge 172:65be27845400 433 * @{
AnnaBridge 172:65be27845400 434 */
AnnaBridge 172:65be27845400 435 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */
AnnaBridge 172:65be27845400 436 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */
AnnaBridge 172:65be27845400 437 /**
AnnaBridge 172:65be27845400 438 * @}
AnnaBridge 172:65be27845400 439 */
AnnaBridge 172:65be27845400 440
AnnaBridge 172:65be27845400 441 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode
AnnaBridge 172:65be27845400 442 * @{
AnnaBridge 172:65be27845400 443 */
AnnaBridge 172:65be27845400 444 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */
AnnaBridge 172:65be27845400 445 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */
AnnaBridge 172:65be27845400 446 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */
AnnaBridge 172:65be27845400 447 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */
AnnaBridge 172:65be27845400 448 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */
AnnaBridge 172:65be27845400 449 /**
AnnaBridge 172:65be27845400 450 * @}
AnnaBridge 172:65be27845400 451 */
AnnaBridge 172:65be27845400 452
AnnaBridge 172:65be27845400 453 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size
AnnaBridge 172:65be27845400 454 * @{
AnnaBridge 172:65be27845400 455 */
AnnaBridge 172:65be27845400 456 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */
AnnaBridge 172:65be27845400 457 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */
AnnaBridge 172:65be27845400 458 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */
AnnaBridge 172:65be27845400 459 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */
AnnaBridge 172:65be27845400 460 /**
AnnaBridge 172:65be27845400 461 * @}
AnnaBridge 172:65be27845400 462 */
AnnaBridge 172:65be27845400 463
AnnaBridge 172:65be27845400 464 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode
AnnaBridge 172:65be27845400 465 * @{
AnnaBridge 172:65be27845400 466 */
AnnaBridge 172:65be27845400 467 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */
AnnaBridge 172:65be27845400 468 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */
AnnaBridge 172:65be27845400 469 /**
AnnaBridge 172:65be27845400 470 * @}
AnnaBridge 172:65be27845400 471 */
AnnaBridge 172:65be27845400 472
AnnaBridge 172:65be27845400 473 /** @defgroup OSPI_DataMode OSPI Data Mode
AnnaBridge 172:65be27845400 474 * @{
AnnaBridge 172:65be27845400 475 */
AnnaBridge 172:65be27845400 476 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */
AnnaBridge 172:65be27845400 477 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */
AnnaBridge 172:65be27845400 478 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */
AnnaBridge 172:65be27845400 479 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */
AnnaBridge 172:65be27845400 480 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */
AnnaBridge 172:65be27845400 481 /**
AnnaBridge 172:65be27845400 482 * @}
AnnaBridge 172:65be27845400 483 */
AnnaBridge 172:65be27845400 484
AnnaBridge 172:65be27845400 485 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode
AnnaBridge 172:65be27845400 486 * @{
AnnaBridge 172:65be27845400 487 */
AnnaBridge 172:65be27845400 488 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */
AnnaBridge 172:65be27845400 489 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */
AnnaBridge 172:65be27845400 490 /**
AnnaBridge 172:65be27845400 491 * @}
AnnaBridge 172:65be27845400 492 */
AnnaBridge 172:65be27845400 493
AnnaBridge 172:65be27845400 494 /** @defgroup OSPI_DQSMode OSPI DQS Mode
AnnaBridge 172:65be27845400 495 * @{
AnnaBridge 172:65be27845400 496 */
AnnaBridge 172:65be27845400 497 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */
AnnaBridge 172:65be27845400 498 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */
AnnaBridge 172:65be27845400 499 /**
AnnaBridge 172:65be27845400 500 * @}
AnnaBridge 172:65be27845400 501 */
AnnaBridge 172:65be27845400 502
AnnaBridge 172:65be27845400 503 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode
AnnaBridge 172:65be27845400 504 * @{
AnnaBridge 172:65be27845400 505 */
AnnaBridge 172:65be27845400 506 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */
AnnaBridge 172:65be27845400 507 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */
AnnaBridge 172:65be27845400 508 /**
AnnaBridge 172:65be27845400 509 * @}
AnnaBridge 172:65be27845400 510 */
AnnaBridge 172:65be27845400 511
AnnaBridge 172:65be27845400 512 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation
AnnaBridge 172:65be27845400 513 * @{
AnnaBridge 172:65be27845400 514 */
AnnaBridge 172:65be27845400 515 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */
AnnaBridge 172:65be27845400 516 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */
AnnaBridge 172:65be27845400 517 /**
AnnaBridge 172:65be27845400 518 * @}
AnnaBridge 172:65be27845400 519 */
AnnaBridge 172:65be27845400 520
AnnaBridge 172:65be27845400 521 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode
AnnaBridge 172:65be27845400 522 * @{
AnnaBridge 172:65be27845400 523 */
AnnaBridge 172:65be27845400 524 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */
AnnaBridge 172:65be27845400 525 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */
AnnaBridge 172:65be27845400 526 /**
AnnaBridge 172:65be27845400 527 * @}
AnnaBridge 172:65be27845400 528 */
AnnaBridge 172:65be27845400 529
AnnaBridge 172:65be27845400 530 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space
AnnaBridge 172:65be27845400 531 * @{
AnnaBridge 172:65be27845400 532 */
AnnaBridge 172:65be27845400 533 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */
AnnaBridge 172:65be27845400 534 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
AnnaBridge 172:65be27845400 535 /**
AnnaBridge 172:65be27845400 536 * @}
AnnaBridge 172:65be27845400 537 */
AnnaBridge 172:65be27845400 538
AnnaBridge 172:65be27845400 539 /** @defgroup OSPI_MatchMode OSPI Match Mode
AnnaBridge 172:65be27845400 540 * @{
AnnaBridge 172:65be27845400 541 */
AnnaBridge 172:65be27845400 542 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */
AnnaBridge 172:65be27845400 543 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */
AnnaBridge 172:65be27845400 544 /**
AnnaBridge 172:65be27845400 545 * @}
AnnaBridge 172:65be27845400 546 */
AnnaBridge 172:65be27845400 547
AnnaBridge 172:65be27845400 548 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop
AnnaBridge 172:65be27845400 549 * @{
AnnaBridge 172:65be27845400 550 */
AnnaBridge 172:65be27845400 551 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */
AnnaBridge 172:65be27845400 552 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */
AnnaBridge 172:65be27845400 553 /**
AnnaBridge 172:65be27845400 554 * @}
AnnaBridge 172:65be27845400 555 */
AnnaBridge 172:65be27845400 556
AnnaBridge 172:65be27845400 557 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation
AnnaBridge 172:65be27845400 558 * @{
AnnaBridge 172:65be27845400 559 */
AnnaBridge 172:65be27845400 560 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */
AnnaBridge 172:65be27845400 561 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */
AnnaBridge 172:65be27845400 562 /**
AnnaBridge 172:65be27845400 563 * @}
AnnaBridge 172:65be27845400 564 */
AnnaBridge 172:65be27845400 565
AnnaBridge 172:65be27845400 566 /** @defgroup OSPI_Flags OSPI Flags
AnnaBridge 172:65be27845400 567 * @{
AnnaBridge 172:65be27845400 568 */
AnnaBridge 172:65be27845400 569 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */
AnnaBridge 172:65be27845400 570 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */
AnnaBridge 172:65be27845400 571 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */
AnnaBridge 172:65be27845400 572 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */
AnnaBridge 172:65be27845400 573 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */
AnnaBridge 172:65be27845400 574 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */
AnnaBridge 172:65be27845400 575 /**
AnnaBridge 172:65be27845400 576 * @}
AnnaBridge 172:65be27845400 577 */
AnnaBridge 172:65be27845400 578
AnnaBridge 172:65be27845400 579 /** @defgroup OSPI_Interrupts OSPI Interrupts
AnnaBridge 172:65be27845400 580 * @{
AnnaBridge 172:65be27845400 581 */
AnnaBridge 172:65be27845400 582 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */
AnnaBridge 172:65be27845400 583 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */
AnnaBridge 172:65be27845400 584 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */
AnnaBridge 172:65be27845400 585 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */
AnnaBridge 172:65be27845400 586 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */
AnnaBridge 172:65be27845400 587 /**
AnnaBridge 172:65be27845400 588 * @}
AnnaBridge 172:65be27845400 589 */
AnnaBridge 172:65be27845400 590
AnnaBridge 172:65be27845400 591 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition
AnnaBridge 172:65be27845400 592 * @{
AnnaBridge 172:65be27845400 593 */
AnnaBridge 172:65be27845400 594 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */
AnnaBridge 172:65be27845400 595 /**
AnnaBridge 172:65be27845400 596 * @}
AnnaBridge 172:65be27845400 597 */
AnnaBridge 172:65be27845400 598
AnnaBridge 172:65be27845400 599 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port
AnnaBridge 172:65be27845400 600 * @{
AnnaBridge 172:65be27845400 601 */
AnnaBridge 172:65be27845400 602 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1)) /*!< Port 1 - IO[3:0] */
AnnaBridge 172:65be27845400 603 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */
AnnaBridge 172:65be27845400 604 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */
AnnaBridge 172:65be27845400 605 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */
AnnaBridge 172:65be27845400 606 /**
AnnaBridge 172:65be27845400 607 * @}
AnnaBridge 172:65be27845400 608 */
AnnaBridge 172:65be27845400 609 /**
AnnaBridge 172:65be27845400 610 * @}
AnnaBridge 172:65be27845400 611 */
AnnaBridge 172:65be27845400 612
AnnaBridge 172:65be27845400 613 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 172:65be27845400 614 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros
AnnaBridge 172:65be27845400 615 * @{
AnnaBridge 172:65be27845400 616 */
AnnaBridge 172:65be27845400 617 /** @brief Reset OSPI handle state.
AnnaBridge 172:65be27845400 618 * @param __HANDLE__: OSPI handle.
AnnaBridge 172:65be27845400 619 * @retval None
AnnaBridge 172:65be27845400 620 */
AnnaBridge 172:65be27845400 621 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
AnnaBridge 172:65be27845400 622
AnnaBridge 172:65be27845400 623 /** @brief Enable the OSPI peripheral.
AnnaBridge 172:65be27845400 624 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 625 * @retval None
AnnaBridge 172:65be27845400 626 */
AnnaBridge 172:65be27845400 627 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
AnnaBridge 172:65be27845400 628
AnnaBridge 172:65be27845400 629 /** @brief Disable the OSPI peripheral.
AnnaBridge 172:65be27845400 630 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 631 * @retval None
AnnaBridge 172:65be27845400 632 */
AnnaBridge 172:65be27845400 633 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
AnnaBridge 172:65be27845400 634
AnnaBridge 172:65be27845400 635 /** @brief Enable the specified OSPI interrupt.
AnnaBridge 172:65be27845400 636 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 637 * @param __INTERRUPT__: specifies the OSPI interrupt source to enable.
AnnaBridge 172:65be27845400 638 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 639 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
AnnaBridge 172:65be27845400 640 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
AnnaBridge 172:65be27845400 641 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
AnnaBridge 172:65be27845400 642 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
AnnaBridge 172:65be27845400 643 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
AnnaBridge 172:65be27845400 644 * @retval None
AnnaBridge 172:65be27845400 645 */
AnnaBridge 172:65be27845400 646 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 172:65be27845400 647
AnnaBridge 172:65be27845400 648
AnnaBridge 172:65be27845400 649 /** @brief Disable the specified OSPI interrupt.
AnnaBridge 172:65be27845400 650 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 651 * @param __INTERRUPT__: specifies the OSPI interrupt source to disable.
AnnaBridge 172:65be27845400 652 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 653 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
AnnaBridge 172:65be27845400 654 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
AnnaBridge 172:65be27845400 655 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
AnnaBridge 172:65be27845400 656 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
AnnaBridge 172:65be27845400 657 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
AnnaBridge 172:65be27845400 658 * @retval None
AnnaBridge 172:65be27845400 659 */
AnnaBridge 172:65be27845400 660 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 172:65be27845400 661
AnnaBridge 172:65be27845400 662 /** @brief Check whether the specified OSPI interrupt source is enabled or not.
AnnaBridge 172:65be27845400 663 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 664 * @param __INTERRUPT__: specifies the OSPI interrupt source to check.
AnnaBridge 172:65be27845400 665 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 666 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt
AnnaBridge 172:65be27845400 667 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt
AnnaBridge 172:65be27845400 668 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt
AnnaBridge 172:65be27845400 669 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt
AnnaBridge 172:65be27845400 670 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt
AnnaBridge 172:65be27845400 671 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 172:65be27845400 672 */
AnnaBridge 172:65be27845400 673 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 172:65be27845400 674
AnnaBridge 172:65be27845400 675 /**
AnnaBridge 172:65be27845400 676 * @brief Check whether the selected OSPI flag is set or not.
AnnaBridge 172:65be27845400 677 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 678 * @param __FLAG__: specifies the OSPI flag to check.
AnnaBridge 172:65be27845400 679 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 680 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag
AnnaBridge 172:65be27845400 681 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
AnnaBridge 172:65be27845400 682 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
AnnaBridge 172:65be27845400 683 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag
AnnaBridge 172:65be27845400 684 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
AnnaBridge 172:65be27845400 685 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
AnnaBridge 172:65be27845400 686 * @retval None
AnnaBridge 172:65be27845400 687 */
AnnaBridge 172:65be27845400 688 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET)
AnnaBridge 172:65be27845400 689
AnnaBridge 172:65be27845400 690 /** @brief Clears the specified OSPI's flag status.
AnnaBridge 172:65be27845400 691 * @param __HANDLE__: specifies the OSPI Handle.
AnnaBridge 172:65be27845400 692 * @param __FLAG__: specifies the OSPI clear register flag that needs to be set
AnnaBridge 172:65be27845400 693 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 694 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag
AnnaBridge 172:65be27845400 695 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag
AnnaBridge 172:65be27845400 696 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag
AnnaBridge 172:65be27845400 697 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag
AnnaBridge 172:65be27845400 698 * @retval None
AnnaBridge 172:65be27845400 699 */
AnnaBridge 172:65be27845400 700 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
AnnaBridge 172:65be27845400 701
AnnaBridge 172:65be27845400 702 /**
AnnaBridge 172:65be27845400 703 * @}
AnnaBridge 172:65be27845400 704 */
AnnaBridge 172:65be27845400 705
AnnaBridge 172:65be27845400 706 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 707 /** @addtogroup OSPI_Exported_Functions
AnnaBridge 172:65be27845400 708 * @{
AnnaBridge 172:65be27845400 709 */
AnnaBridge 172:65be27845400 710
AnnaBridge 172:65be27845400 711 /* Initialization/de-initialization functions ********************************/
AnnaBridge 172:65be27845400 712 /** @addtogroup OSPI_Exported_Functions_Group1
AnnaBridge 172:65be27845400 713 * @{
AnnaBridge 172:65be27845400 714 */
AnnaBridge 172:65be27845400 715 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 716 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 717 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 718 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 719
AnnaBridge 172:65be27845400 720 /**
AnnaBridge 172:65be27845400 721 * @}
AnnaBridge 172:65be27845400 722 */
AnnaBridge 172:65be27845400 723
AnnaBridge 172:65be27845400 724 /* IO operation functions *****************************************************/
AnnaBridge 172:65be27845400 725 /** @addtogroup OSPI_Exported_Functions_Group2
AnnaBridge 172:65be27845400 726 * @{
AnnaBridge 172:65be27845400 727 */
AnnaBridge 172:65be27845400 728 /* OSPI IRQ handler function */
AnnaBridge 172:65be27845400 729 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 730
AnnaBridge 172:65be27845400 731 /* OSPI command configuration functions */
AnnaBridge 172:65be27845400 732 HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
AnnaBridge 172:65be27845400 733 HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
AnnaBridge 172:65be27845400 734 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
AnnaBridge 172:65be27845400 735 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
AnnaBridge 172:65be27845400 736
AnnaBridge 172:65be27845400 737 /* OSPI indirect mode functions */
AnnaBridge 172:65be27845400 738 HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 172:65be27845400 739 HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 172:65be27845400 740 HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData);
AnnaBridge 172:65be27845400 741 HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData);
AnnaBridge 172:65be27845400 742 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData);
AnnaBridge 172:65be27845400 743 HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData);
AnnaBridge 172:65be27845400 744
AnnaBridge 172:65be27845400 745 /* OSPI status flag polling mode functions */
AnnaBridge 172:65be27845400 746 HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
AnnaBridge 172:65be27845400 747 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
AnnaBridge 172:65be27845400 748
AnnaBridge 172:65be27845400 749 /* OSPI memory-mapped mode functions */
AnnaBridge 172:65be27845400 750 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
AnnaBridge 172:65be27845400 751
AnnaBridge 172:65be27845400 752 /* Callback functions in non-blocking modes ***********************************/
AnnaBridge 172:65be27845400 753 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 754 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 755 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 756
AnnaBridge 172:65be27845400 757 /* OSPI indirect mode functions */
AnnaBridge 172:65be27845400 758 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 759 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 760 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 761 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 762 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 763
AnnaBridge 172:65be27845400 764 /* OSPI status flag polling mode functions */
AnnaBridge 172:65be27845400 765 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 766
AnnaBridge 172:65be27845400 767 /* OSPI memory-mapped mode functions */
AnnaBridge 172:65be27845400 768 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 769
AnnaBridge 172:65be27845400 770 /**
AnnaBridge 172:65be27845400 771 * @}
AnnaBridge 172:65be27845400 772 */
AnnaBridge 172:65be27845400 773
AnnaBridge 172:65be27845400 774 /* Peripheral Control and State functions ************************************/
AnnaBridge 172:65be27845400 775 /** @addtogroup OSPI_Exported_Functions_Group3
AnnaBridge 172:65be27845400 776 * @{
AnnaBridge 172:65be27845400 777 */
AnnaBridge 172:65be27845400 778 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 779 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 780 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
AnnaBridge 172:65be27845400 781 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 782 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
AnnaBridge 172:65be27845400 783 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 784 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi);
AnnaBridge 172:65be27845400 785
AnnaBridge 172:65be27845400 786 /**
AnnaBridge 172:65be27845400 787 * @}
AnnaBridge 172:65be27845400 788 */
AnnaBridge 172:65be27845400 789
AnnaBridge 172:65be27845400 790 /* OSPI IO Manager configuration function ************************************/
AnnaBridge 172:65be27845400 791 /** @addtogroup OSPI_Exported_Functions_Group4
AnnaBridge 172:65be27845400 792 * @{
AnnaBridge 172:65be27845400 793 */
AnnaBridge 172:65be27845400 794 HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
AnnaBridge 172:65be27845400 795
AnnaBridge 172:65be27845400 796 /**
AnnaBridge 172:65be27845400 797 * @}
AnnaBridge 172:65be27845400 798 */
AnnaBridge 172:65be27845400 799
AnnaBridge 172:65be27845400 800 /**
AnnaBridge 172:65be27845400 801 * @}
AnnaBridge 172:65be27845400 802 */
AnnaBridge 172:65be27845400 803 /* End of exported functions -------------------------------------------------*/
AnnaBridge 172:65be27845400 804
AnnaBridge 172:65be27845400 805 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 806 /**
AnnaBridge 172:65be27845400 807 @cond 0
AnnaBridge 172:65be27845400 808 */
AnnaBridge 172:65be27845400 809 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1) && ((THRESHOLD) <= 32))
AnnaBridge 172:65be27845400 810
AnnaBridge 172:65be27845400 811 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
AnnaBridge 172:65be27845400 812 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
AnnaBridge 172:65be27845400 813
AnnaBridge 172:65be27845400 814 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \
AnnaBridge 172:65be27845400 815 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
AnnaBridge 172:65be27845400 816 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
AnnaBridge 172:65be27845400 817
AnnaBridge 172:65be27845400 818 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 32))
AnnaBridge 172:65be27845400 819
AnnaBridge 172:65be27845400 820 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1) && ((TIME) <= 8))
AnnaBridge 172:65be27845400 821
AnnaBridge 172:65be27845400 822 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
AnnaBridge 172:65be27845400 823 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
AnnaBridge 172:65be27845400 824
AnnaBridge 172:65be27845400 825 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
AnnaBridge 172:65be27845400 826 ((MODE) == HAL_OSPI_CLOCK_MODE_3))
AnnaBridge 172:65be27845400 827
AnnaBridge 172:65be27845400 828 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \
AnnaBridge 172:65be27845400 829 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \
AnnaBridge 172:65be27845400 830 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \
AnnaBridge 172:65be27845400 831 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \
AnnaBridge 172:65be27845400 832 ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
AnnaBridge 172:65be27845400 833
AnnaBridge 172:65be27845400 834 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 256))
AnnaBridge 172:65be27845400 835
AnnaBridge 172:65be27845400 836 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \
AnnaBridge 172:65be27845400 837 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
AnnaBridge 172:65be27845400 838
AnnaBridge 172:65be27845400 839 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
AnnaBridge 172:65be27845400 840 ((CYCLE) == HAL_OSPI_DHQC_ENABLE))
AnnaBridge 172:65be27845400 841
AnnaBridge 172:65be27845400 842 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
AnnaBridge 172:65be27845400 843 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \
AnnaBridge 172:65be27845400 844 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG))
AnnaBridge 172:65be27845400 845
AnnaBridge 172:65be27845400 846 #define IS_OSPI_FLASH_ID(FLASH) (((FLASH) == HAL_OSPI_FLASH_ID_1) || \
AnnaBridge 172:65be27845400 847 ((FLASH) == HAL_OSPI_FLASH_ID_2))
AnnaBridge 172:65be27845400 848
AnnaBridge 172:65be27845400 849 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \
AnnaBridge 172:65be27845400 850 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
AnnaBridge 172:65be27845400 851 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
AnnaBridge 172:65be27845400 852 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
AnnaBridge 172:65be27845400 853 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
AnnaBridge 172:65be27845400 854
AnnaBridge 172:65be27845400 855 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \
AnnaBridge 172:65be27845400 856 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
AnnaBridge 172:65be27845400 857 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
AnnaBridge 172:65be27845400 858 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
AnnaBridge 172:65be27845400 859
AnnaBridge 172:65be27845400 860 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
AnnaBridge 172:65be27845400 861 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
AnnaBridge 172:65be27845400 862
AnnaBridge 172:65be27845400 863 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \
AnnaBridge 172:65be27845400 864 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
AnnaBridge 172:65be27845400 865 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
AnnaBridge 172:65be27845400 866 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
AnnaBridge 172:65be27845400 867 ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
AnnaBridge 172:65be27845400 868
AnnaBridge 172:65be27845400 869 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \
AnnaBridge 172:65be27845400 870 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
AnnaBridge 172:65be27845400 871 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
AnnaBridge 172:65be27845400 872 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
AnnaBridge 172:65be27845400 873
AnnaBridge 172:65be27845400 874 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
AnnaBridge 172:65be27845400 875 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
AnnaBridge 172:65be27845400 876
AnnaBridge 172:65be27845400 877 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \
AnnaBridge 172:65be27845400 878 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
AnnaBridge 172:65be27845400 879 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
AnnaBridge 172:65be27845400 880 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
AnnaBridge 172:65be27845400 881 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
AnnaBridge 172:65be27845400 882
AnnaBridge 172:65be27845400 883 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \
AnnaBridge 172:65be27845400 884 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
AnnaBridge 172:65be27845400 885 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
AnnaBridge 172:65be27845400 886 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
AnnaBridge 172:65be27845400 887
AnnaBridge 172:65be27845400 888 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
AnnaBridge 172:65be27845400 889 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
AnnaBridge 172:65be27845400 890
AnnaBridge 172:65be27845400 891 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \
AnnaBridge 172:65be27845400 892 ((MODE) == HAL_OSPI_DATA_1_LINE) || \
AnnaBridge 172:65be27845400 893 ((MODE) == HAL_OSPI_DATA_2_LINES) || \
AnnaBridge 172:65be27845400 894 ((MODE) == HAL_OSPI_DATA_4_LINES) || \
AnnaBridge 172:65be27845400 895 ((MODE) == HAL_OSPI_DATA_8_LINES))
AnnaBridge 172:65be27845400 896
AnnaBridge 172:65be27845400 897 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1)
AnnaBridge 172:65be27845400 898
AnnaBridge 172:65be27845400 899 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
AnnaBridge 172:65be27845400 900 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
AnnaBridge 172:65be27845400 901
AnnaBridge 172:65be27845400 902 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31)
AnnaBridge 172:65be27845400 903
AnnaBridge 172:65be27845400 904 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \
AnnaBridge 172:65be27845400 905 ((MODE) == HAL_OSPI_DQS_ENABLE))
AnnaBridge 172:65be27845400 906
AnnaBridge 172:65be27845400 907 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
AnnaBridge 172:65be27845400 908 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
AnnaBridge 172:65be27845400 909
AnnaBridge 172:65be27845400 910 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255)
AnnaBridge 172:65be27845400 911
AnnaBridge 172:65be27845400 912 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255)
AnnaBridge 172:65be27845400 913
AnnaBridge 172:65be27845400 914 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
AnnaBridge 172:65be27845400 915 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
AnnaBridge 172:65be27845400 916
AnnaBridge 172:65be27845400 917 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
AnnaBridge 172:65be27845400 918 ((MODE) == HAL_OSPI_FIXED_LATENCY))
AnnaBridge 172:65be27845400 919
AnnaBridge 172:65be27845400 920 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
AnnaBridge 172:65be27845400 921 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
AnnaBridge 172:65be27845400 922
AnnaBridge 172:65be27845400 923 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
AnnaBridge 172:65be27845400 924 ((MODE) == HAL_OSPI_MATCH_MODE_OR))
AnnaBridge 172:65be27845400 925
AnnaBridge 172:65be27845400 926 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
AnnaBridge 172:65be27845400 927 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
AnnaBridge 172:65be27845400 928
AnnaBridge 172:65be27845400 929 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFF)
AnnaBridge 172:65be27845400 930
AnnaBridge 172:65be27845400 931 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
AnnaBridge 172:65be27845400 932
AnnaBridge 172:65be27845400 933 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
AnnaBridge 172:65be27845400 934 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
AnnaBridge 172:65be27845400 935
AnnaBridge 172:65be27845400 936 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
AnnaBridge 172:65be27845400 937
AnnaBridge 172:65be27845400 938 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31)
AnnaBridge 172:65be27845400 939
AnnaBridge 172:65be27845400 940 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1) && ((NUMBER) <= 2))
AnnaBridge 172:65be27845400 941
AnnaBridge 172:65be27845400 942 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
AnnaBridge 172:65be27845400 943 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
AnnaBridge 172:65be27845400 944 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
AnnaBridge 172:65be27845400 945 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH))
AnnaBridge 172:65be27845400 946 /**
AnnaBridge 172:65be27845400 947 @endcond
AnnaBridge 172:65be27845400 948 */
AnnaBridge 172:65be27845400 949
AnnaBridge 172:65be27845400 950 /* End of private macros -----------------------------------------------------*/
AnnaBridge 172:65be27845400 951
AnnaBridge 172:65be27845400 952 /**
AnnaBridge 172:65be27845400 953 * @}
AnnaBridge 172:65be27845400 954 */
AnnaBridge 172:65be27845400 955
AnnaBridge 172:65be27845400 956 /**
AnnaBridge 172:65be27845400 957 * @}
AnnaBridge 172:65be27845400 958 */
AnnaBridge 172:65be27845400 959
AnnaBridge 172:65be27845400 960 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
AnnaBridge 172:65be27845400 961
AnnaBridge 172:65be27845400 962 #ifdef __cplusplus
AnnaBridge 172:65be27845400 963 }
AnnaBridge 172:65be27845400 964 #endif
AnnaBridge 172:65be27845400 965
AnnaBridge 172:65be27845400 966 #endif /* __STM32L4xx_HAL_OSPI_H */
AnnaBridge 172:65be27845400 967
AnnaBridge 172:65be27845400 968 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/