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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4xx_hal_dsi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_hal_dsi.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of DSI HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_HAL_DSI_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_HAL_DSI_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	#if defined(DSI)
AnnaBridge	172:65be27845400	48
AnnaBridge	172:65be27845400	49	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	172:65be27845400	50	* @{
AnnaBridge	172:65be27845400	51	*/
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	/** @defgroup DSI DSI
AnnaBridge	172:65be27845400	54	* @brief DSI HAL module driver
AnnaBridge	172:65be27845400	55	* @{
AnnaBridge	172:65be27845400	56	*/
AnnaBridge	172:65be27845400	57
AnnaBridge	172:65be27845400	58	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	59	/**
AnnaBridge	172:65be27845400	60	* @brief DSI Init Structure definition
AnnaBridge	172:65be27845400	61	*/
AnnaBridge	172:65be27845400	62	typedef struct
AnnaBridge	172:65be27845400	63	{
AnnaBridge	172:65be27845400	64	uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
AnnaBridge	172:65be27845400	65	This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
AnnaBridge	172:65be27845400	66
AnnaBridge	172:65be27845400	67	uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
AnnaBridge	172:65be27845400	68	The values 0 and 1 stop the TX_ESC clock generation */
AnnaBridge	172:65be27845400	69
AnnaBridge	172:65be27845400	70	uint32_t NumberOfLanes; /*!< Number of lanes
AnnaBridge	172:65be27845400	71	This parameter can be any value of @ref DSI_Number_Of_Lanes */
AnnaBridge	172:65be27845400	72
AnnaBridge	172:65be27845400	73	}DSI_InitTypeDef;
AnnaBridge	172:65be27845400	74
AnnaBridge	172:65be27845400	75	/**
AnnaBridge	172:65be27845400	76	* @brief DSI PLL Clock structure definition
AnnaBridge	172:65be27845400	77	*/
AnnaBridge	172:65be27845400	78	typedef struct
AnnaBridge	172:65be27845400	79	{
AnnaBridge	172:65be27845400	80	uint32_t PLLNDIV; /*!< PLL Loop Division Factor
AnnaBridge	172:65be27845400	81	This parameter must be a value between 10 and 125 */
AnnaBridge	172:65be27845400	82
AnnaBridge	172:65be27845400	83	uint32_t PLLIDF; /*!< PLL Input Division Factor
AnnaBridge	172:65be27845400	84	This parameter can be any value of @ref DSI_PLL_IDF */
AnnaBridge	172:65be27845400	85
AnnaBridge	172:65be27845400	86	uint32_t PLLODF; /*!< PLL Output Division Factor
AnnaBridge	172:65be27845400	87	This parameter can be any value of @ref DSI_PLL_ODF */
AnnaBridge	172:65be27845400	88
AnnaBridge	172:65be27845400	89	}DSI_PLLInitTypeDef;
AnnaBridge	172:65be27845400	90
AnnaBridge	172:65be27845400	91	/**
AnnaBridge	172:65be27845400	92	* @brief DSI Video mode configuration
AnnaBridge	172:65be27845400	93	*/
AnnaBridge	172:65be27845400	94	typedef struct
AnnaBridge	172:65be27845400	95	{
AnnaBridge	172:65be27845400	96	uint32_t VirtualChannelID; /!< Virtual channel ID /
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge	172:65be27845400	99	This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge	172:65be27845400	100
AnnaBridge	172:65be27845400	101	uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
AnnaBridge	172:65be27845400	102	18-bit configuration).
AnnaBridge	172:65be27845400	103	This parameter can be any value of @ref DSI_LooselyPacked */
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	uint32_t Mode; /*!< Video mode type
AnnaBridge	172:65be27845400	106	This parameter can be any value of @ref DSI_Video_Mode_Type */
AnnaBridge	172:65be27845400	107
AnnaBridge	172:65be27845400	108	uint32_t PacketSize; /!< Video packet size /
AnnaBridge	172:65be27845400	109
AnnaBridge	172:65be27845400	110	uint32_t NumberOfChunks; /!< Number of chunks /
AnnaBridge	172:65be27845400	111
AnnaBridge	172:65be27845400	112	uint32_t NullPacketSize; /!< Null packet size /
AnnaBridge	172:65be27845400	113
AnnaBridge	172:65be27845400	114	uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge	172:65be27845400	115	This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge	172:65be27845400	116
AnnaBridge	172:65be27845400	117	uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge	172:65be27845400	118	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
AnnaBridge	172:65be27845400	119
AnnaBridge	172:65be27845400	120	uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge	172:65be27845400	121	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	uint32_t HorizontalSyncActive; /!< Horizontal synchronism active duration (in lane byte clock cycles) /
AnnaBridge	172:65be27845400	124
AnnaBridge	172:65be27845400	125	uint32_t HorizontalBackPorch; /!< Horizontal back-porch duration (in lane byte clock cycles) /
AnnaBridge	172:65be27845400	126
AnnaBridge	172:65be27845400	127	uint32_t HorizontalLine; /!< Horizontal line duration (in lane byte clock cycles) /
AnnaBridge	172:65be27845400	128
AnnaBridge	172:65be27845400	129	uint32_t VerticalSyncActive; /!< Vertical synchronism active duration /
AnnaBridge	172:65be27845400	130
AnnaBridge	172:65be27845400	131	uint32_t VerticalBackPorch; /!< Vertical back-porch duration /
AnnaBridge	172:65be27845400	132
AnnaBridge	172:65be27845400	133	uint32_t VerticalFrontPorch; /!< Vertical front-porch duration /
AnnaBridge	172:65be27845400	134
AnnaBridge	172:65be27845400	135	uint32_t VerticalActive; /!< Vertical active duration /
AnnaBridge	172:65be27845400	136
AnnaBridge	172:65be27845400	137	uint32_t LPCommandEnable; /*!< Low-power command enable
AnnaBridge	172:65be27845400	138	This parameter can be any value of @ref DSI_LP_Command */
AnnaBridge	172:65be27845400	139
AnnaBridge	172:65be27845400	140	uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge	172:65be27845400	141	can fit in a line during VSA, VBP and VFP regions */
AnnaBridge	172:65be27845400	142
AnnaBridge	172:65be27845400	143	uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge	172:65be27845400	144	can fit in a line during VACT region */
AnnaBridge	172:65be27845400	145
AnnaBridge	172:65be27845400	146	uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
AnnaBridge	172:65be27845400	147	This parameter can be any value of @ref DSI_LP_HFP */
AnnaBridge	172:65be27845400	148
AnnaBridge	172:65be27845400	149	uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
AnnaBridge	172:65be27845400	150	This parameter can be any value of @ref DSI_LP_HBP */
AnnaBridge	172:65be27845400	151
AnnaBridge	172:65be27845400	152	uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
AnnaBridge	172:65be27845400	153	This parameter can be any value of @ref DSI_LP_VACT */
AnnaBridge	172:65be27845400	154
AnnaBridge	172:65be27845400	155	uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
AnnaBridge	172:65be27845400	156	This parameter can be any value of @ref DSI_LP_VFP */
AnnaBridge	172:65be27845400	157
AnnaBridge	172:65be27845400	158	uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
AnnaBridge	172:65be27845400	159	This parameter can be any value of @ref DSI_LP_VBP */
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
AnnaBridge	172:65be27845400	162	This parameter can be any value of @ref DSI_LP_VSYNC */
AnnaBridge	172:65be27845400	163
AnnaBridge	172:65be27845400	164	uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
AnnaBridge	172:65be27845400	165	This parameter can be any value of @ref DSI_FBTA_acknowledge */
AnnaBridge	172:65be27845400	166
AnnaBridge	172:65be27845400	167	}DSI_VidCfgTypeDef;
AnnaBridge	172:65be27845400	168
AnnaBridge	172:65be27845400	169	/**
AnnaBridge	172:65be27845400	170	* @brief DSI Adapted command mode configuration
AnnaBridge	172:65be27845400	171	*/
AnnaBridge	172:65be27845400	172	typedef struct
AnnaBridge	172:65be27845400	173	{
AnnaBridge	172:65be27845400	174	uint32_t VirtualChannelID; /!< Virtual channel ID /
AnnaBridge	172:65be27845400	175
AnnaBridge	172:65be27845400	176	uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge	172:65be27845400	177	This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
AnnaBridge	172:65be27845400	180	pixels. This parameter can be any value between 0x00 and 0xFFFFU */
AnnaBridge	172:65be27845400	181
AnnaBridge	172:65be27845400	182	uint32_t TearingEffectSource; /*!< Tearing effect source
AnnaBridge	172:65be27845400	183	This parameter can be any value of @ref DSI_TearingEffectSource */
AnnaBridge	172:65be27845400	184
AnnaBridge	172:65be27845400	185	uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
AnnaBridge	172:65be27845400	186	This parameter can be any value of @ref DSI_TearingEffectPolarity */
AnnaBridge	172:65be27845400	187
AnnaBridge	172:65be27845400	188	uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge	172:65be27845400	189	This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge	172:65be27845400	192	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
AnnaBridge	172:65be27845400	193
AnnaBridge	172:65be27845400	194	uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge	172:65be27845400	195	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge	172:65be27845400	196
AnnaBridge	172:65be27845400	197	uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
AnnaBridge	172:65be27845400	198	This parameter can be any value of @ref DSI_Vsync_Polarity */
AnnaBridge	172:65be27845400	199
AnnaBridge	172:65be27845400	200	uint32_t AutomaticRefresh; /*!< Automatic refresh mode
AnnaBridge	172:65be27845400	201	This parameter can be any value of @ref DSI_AutomaticRefresh */
AnnaBridge	172:65be27845400	202
AnnaBridge	172:65be27845400	203	uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
AnnaBridge	172:65be27845400	204	This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
AnnaBridge	172:65be27845400	205
AnnaBridge	172:65be27845400	206	}DSI_CmdCfgTypeDef;
AnnaBridge	172:65be27845400	207
AnnaBridge	172:65be27845400	208	/**
AnnaBridge	172:65be27845400	209	* @brief DSI command transmission mode configuration
AnnaBridge	172:65be27845400	210	*/
AnnaBridge	172:65be27845400	211	typedef struct
AnnaBridge	172:65be27845400	212	{
AnnaBridge	172:65be27845400	213	uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
AnnaBridge	172:65be27845400	214	This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
AnnaBridge	172:65be27845400	215
AnnaBridge	172:65be27845400	216	uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
AnnaBridge	172:65be27845400	217	This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
AnnaBridge	172:65be27845400	218
AnnaBridge	172:65be27845400	219	uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
AnnaBridge	172:65be27845400	220	This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
AnnaBridge	172:65be27845400	221
AnnaBridge	172:65be27845400	222	uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
AnnaBridge	172:65be27845400	223	This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
AnnaBridge	172:65be27845400	224
AnnaBridge	172:65be27845400	225	uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
AnnaBridge	172:65be27845400	226	This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
AnnaBridge	172:65be27845400	227
AnnaBridge	172:65be27845400	228	uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
AnnaBridge	172:65be27845400	229	This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
AnnaBridge	172:65be27845400	230
AnnaBridge	172:65be27845400	231	uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
AnnaBridge	172:65be27845400	232	This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
AnnaBridge	172:65be27845400	233
AnnaBridge	172:65be27845400	234	uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
AnnaBridge	172:65be27845400	235	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
AnnaBridge	172:65be27845400	236
AnnaBridge	172:65be27845400	237	uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
AnnaBridge	172:65be27845400	238	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
AnnaBridge	172:65be27845400	239
AnnaBridge	172:65be27845400	240	uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
AnnaBridge	172:65be27845400	241	This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
AnnaBridge	172:65be27845400	242
AnnaBridge	172:65be27845400	243	uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
AnnaBridge	172:65be27845400	244	This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
AnnaBridge	172:65be27845400	245
AnnaBridge	172:65be27845400	246	uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
AnnaBridge	172:65be27845400	247	This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
AnnaBridge	172:65be27845400	248
AnnaBridge	172:65be27845400	249	uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
AnnaBridge	172:65be27845400	250	This parameter can be any value of @ref DSI_AcknowledgeRequest */
AnnaBridge	172:65be27845400	251
AnnaBridge	172:65be27845400	252	}DSI_LPCmdTypeDef;
AnnaBridge	172:65be27845400	253
AnnaBridge	172:65be27845400	254	/**
AnnaBridge	172:65be27845400	255	* @brief DSI PHY Timings definition
AnnaBridge	172:65be27845400	256	*/
AnnaBridge	172:65be27845400	257	typedef struct
AnnaBridge	172:65be27845400	258	{
AnnaBridge	172:65be27845400	259	uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
AnnaBridge	172:65be27845400	260	to low-power transmission */
AnnaBridge	172:65be27845400	261
AnnaBridge	172:65be27845400	262	uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
AnnaBridge	172:65be27845400	263	to high-speed transmission */
AnnaBridge	172:65be27845400	264
AnnaBridge	172:65be27845400	265	uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
AnnaBridge	172:65be27845400	266	to low-power transmission */
AnnaBridge	172:65be27845400	267
AnnaBridge	172:65be27845400	268	uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
AnnaBridge	172:65be27845400	269	to high-speed transmission */
AnnaBridge	172:65be27845400	270
AnnaBridge	172:65be27845400	271	uint32_t DataLaneMaxReadTime; /!< The maximum time required to perform a read command /
AnnaBridge	172:65be27845400	272
AnnaBridge	172:65be27845400	273	uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
AnnaBridge	172:65be27845400	274	Stop state */
AnnaBridge	172:65be27845400	275
AnnaBridge	172:65be27845400	276	}DSI_PHY_TimerTypeDef;
AnnaBridge	172:65be27845400	277
AnnaBridge	172:65be27845400	278	/**
AnnaBridge	172:65be27845400	279	* @brief DSI HOST Timeouts definition
AnnaBridge	172:65be27845400	280	*/
AnnaBridge	172:65be27845400	281	typedef struct
AnnaBridge	172:65be27845400	282	{
AnnaBridge	172:65be27845400	283	uint32_t TimeoutCkdiv; /!< Time-out clock division /
AnnaBridge	172:65be27845400	284
AnnaBridge	172:65be27845400	285	uint32_t HighSpeedTransmissionTimeout; /!< High-speed transmission time-out /
AnnaBridge	172:65be27845400	286
AnnaBridge	172:65be27845400	287	uint32_t LowPowerReceptionTimeout; /!< Low-power reception time-out /
AnnaBridge	172:65be27845400	288
AnnaBridge	172:65be27845400	289	uint32_t HighSpeedReadTimeout; /!< High-speed read time-out /
AnnaBridge	172:65be27845400	290
AnnaBridge	172:65be27845400	291	uint32_t LowPowerReadTimeout; /!< Low-power read time-out /
AnnaBridge	172:65be27845400	292
AnnaBridge	172:65be27845400	293	uint32_t HighSpeedWriteTimeout; /!< High-speed write time-out /
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
AnnaBridge	172:65be27845400	296	This parameter can be any value of @ref DSI_HS_PrespMode */
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	uint32_t LowPowerWriteTimeout; /!< Low-speed write time-out /
AnnaBridge	172:65be27845400	299
AnnaBridge	172:65be27845400	300	uint32_t BTATimeout; /!< BTA time-out /
AnnaBridge	172:65be27845400	301
AnnaBridge	172:65be27845400	302	}DSI_HOST_TimeoutTypeDef;
AnnaBridge	172:65be27845400	303
AnnaBridge	172:65be27845400	304	/**
AnnaBridge	172:65be27845400	305	* @brief DSI States Structure definition
AnnaBridge	172:65be27845400	306	*/
AnnaBridge	172:65be27845400	307	typedef enum
AnnaBridge	172:65be27845400	308	{
AnnaBridge	172:65be27845400	309	HAL_DSI_STATE_RESET = 0x00U,
AnnaBridge	172:65be27845400	310	HAL_DSI_STATE_READY = 0x01U,
AnnaBridge	172:65be27845400	311	HAL_DSI_STATE_ERROR = 0x02U,
AnnaBridge	172:65be27845400	312	HAL_DSI_STATE_BUSY = 0x03U,
AnnaBridge	172:65be27845400	313	HAL_DSI_STATE_TIMEOUT = 0x04U
AnnaBridge	172:65be27845400	314	}HAL_DSI_StateTypeDef;
AnnaBridge	172:65be27845400	315
AnnaBridge	172:65be27845400	316	/**
AnnaBridge	172:65be27845400	317	* @brief DSI Handle Structure definition
AnnaBridge	172:65be27845400	318	*/
AnnaBridge	172:65be27845400	319	typedef struct
AnnaBridge	172:65be27845400	320	{
AnnaBridge	172:65be27845400	321	DSI_TypeDef Instance; /!< Register base address */
AnnaBridge	172:65be27845400	322	DSI_InitTypeDef Init; /!< DSI required parameters /
AnnaBridge	172:65be27845400	323	HAL_LockTypeDef Lock; /!< DSI peripheral status /
AnnaBridge	172:65be27845400	324	__IO HAL_DSI_StateTypeDef State; /!< DSI communication state /
AnnaBridge	172:65be27845400	325	__IO uint32_t ErrorCode; /!< DSI Error code /
AnnaBridge	172:65be27845400	326	uint32_t ErrorMsk; /!< DSI Error monitoring mask /
AnnaBridge	172:65be27845400	327	}DSI_HandleTypeDef;
AnnaBridge	172:65be27845400	328
AnnaBridge	172:65be27845400	329	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	330	/** @defgroup DSI_DCS_Command DSI DCS Command
AnnaBridge	172:65be27845400	331	* @{
AnnaBridge	172:65be27845400	332	*/
AnnaBridge	172:65be27845400	333	#define DSI_ENTER_IDLE_MODE 0x39U
AnnaBridge	172:65be27845400	334	#define DSI_ENTER_INVERT_MODE 0x21U
AnnaBridge	172:65be27845400	335	#define DSI_ENTER_NORMAL_MODE 0x13U
AnnaBridge	172:65be27845400	336	#define DSI_ENTER_PARTIAL_MODE 0x12U
AnnaBridge	172:65be27845400	337	#define DSI_ENTER_SLEEP_MODE 0x10U
AnnaBridge	172:65be27845400	338	#define DSI_EXIT_IDLE_MODE 0x38U
AnnaBridge	172:65be27845400	339	#define DSI_EXIT_INVERT_MODE 0x20U
AnnaBridge	172:65be27845400	340	#define DSI_EXIT_SLEEP_MODE 0x11U
AnnaBridge	172:65be27845400	341	#define DSI_GET_3D_CONTROL 0x3FU
AnnaBridge	172:65be27845400	342	#define DSI_GET_ADDRESS_MODE 0x0BU
AnnaBridge	172:65be27845400	343	#define DSI_GET_BLUE_CHANNEL 0x08U
AnnaBridge	172:65be27845400	344	#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
AnnaBridge	172:65be27845400	345	#define DSI_GET_DISPLAY_MODE 0x0DU
AnnaBridge	172:65be27845400	346	#define DSI_GET_GREEN_CHANNEL 0x07U
AnnaBridge	172:65be27845400	347	#define DSI_GET_PIXEL_FORMAT 0x0CU
AnnaBridge	172:65be27845400	348	#define DSI_GET_POWER_MODE 0x0AU
AnnaBridge	172:65be27845400	349	#define DSI_GET_RED_CHANNEL 0x06U
AnnaBridge	172:65be27845400	350	#define DSI_GET_SCANLINE 0x45U
AnnaBridge	172:65be27845400	351	#define DSI_GET_SIGNAL_MODE 0x0EU
AnnaBridge	172:65be27845400	352	#define DSI_NOP 0x00U
AnnaBridge	172:65be27845400	353	#define DSI_READ_DDB_CONTINUE 0xA8U
AnnaBridge	172:65be27845400	354	#define DSI_READ_DDB_START 0xA1U
AnnaBridge	172:65be27845400	355	#define DSI_READ_MEMORY_CONTINUE 0x3EU
AnnaBridge	172:65be27845400	356	#define DSI_READ_MEMORY_START 0x2EU
AnnaBridge	172:65be27845400	357	#define DSI_SET_3D_CONTROL 0x3DU
AnnaBridge	172:65be27845400	358	#define DSI_SET_ADDRESS_MODE 0x36U
AnnaBridge	172:65be27845400	359	#define DSI_SET_COLUMN_ADDRESS 0x2AU
AnnaBridge	172:65be27845400	360	#define DSI_SET_DISPLAY_OFF 0x28U
AnnaBridge	172:65be27845400	361	#define DSI_SET_DISPLAY_ON 0x29U
AnnaBridge	172:65be27845400	362	#define DSI_SET_GAMMA_CURVE 0x26U
AnnaBridge	172:65be27845400	363	#define DSI_SET_PAGE_ADDRESS 0x2BU
AnnaBridge	172:65be27845400	364	#define DSI_SET_PARTIAL_COLUMNS 0x31U
AnnaBridge	172:65be27845400	365	#define DSI_SET_PARTIAL_ROWS 0x30U
AnnaBridge	172:65be27845400	366	#define DSI_SET_PIXEL_FORMAT 0x3AU
AnnaBridge	172:65be27845400	367	#define DSI_SET_SCROLL_AREA 0x33U
AnnaBridge	172:65be27845400	368	#define DSI_SET_SCROLL_START 0x37U
AnnaBridge	172:65be27845400	369	#define DSI_SET_TEAR_OFF 0x34U
AnnaBridge	172:65be27845400	370	#define DSI_SET_TEAR_ON 0x35U
AnnaBridge	172:65be27845400	371	#define DSI_SET_TEAR_SCANLINE 0x44U
AnnaBridge	172:65be27845400	372	#define DSI_SET_VSYNC_TIMING 0x40U
AnnaBridge	172:65be27845400	373	#define DSI_SOFT_RESET 0x01U
AnnaBridge	172:65be27845400	374	#define DSI_WRITE_LUT 0x2DU
AnnaBridge	172:65be27845400	375	#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
AnnaBridge	172:65be27845400	376	#define DSI_WRITE_MEMORY_START 0x2CU
AnnaBridge	172:65be27845400	377	/**
AnnaBridge	172:65be27845400	378	* @}
AnnaBridge	172:65be27845400	379	*/
AnnaBridge	172:65be27845400	380
AnnaBridge	172:65be27845400	381	/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
AnnaBridge	172:65be27845400	382	* @{
AnnaBridge	172:65be27845400	383	*/
AnnaBridge	172:65be27845400	384	#define DSI_VID_MODE_NB_PULSES 0U
AnnaBridge	172:65be27845400	385	#define DSI_VID_MODE_NB_EVENTS 1U
AnnaBridge	172:65be27845400	386	#define DSI_VID_MODE_BURST 2U
AnnaBridge	172:65be27845400	387	/**
AnnaBridge	172:65be27845400	388	* @}
AnnaBridge	172:65be27845400	389	*/
AnnaBridge	172:65be27845400	390
AnnaBridge	172:65be27845400	391	/** @defgroup DSI_Color_Mode DSI Color Mode
AnnaBridge	172:65be27845400	392	* @{
AnnaBridge	172:65be27845400	393	*/
AnnaBridge	172:65be27845400	394	#define DSI_COLOR_MODE_FULL 0x00000000U
AnnaBridge	172:65be27845400	395	#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
AnnaBridge	172:65be27845400	396	/**
AnnaBridge	172:65be27845400	397	* @}
AnnaBridge	172:65be27845400	398	*/
AnnaBridge	172:65be27845400	399
AnnaBridge	172:65be27845400	400	/** @defgroup DSI_ShutDown DSI ShutDown
AnnaBridge	172:65be27845400	401	* @{
AnnaBridge	172:65be27845400	402	*/
AnnaBridge	172:65be27845400	403	#define DSI_DISPLAY_ON 0x00000000U
AnnaBridge	172:65be27845400	404	#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
AnnaBridge	172:65be27845400	405	/**
AnnaBridge	172:65be27845400	406	* @}
AnnaBridge	172:65be27845400	407	*/
AnnaBridge	172:65be27845400	408
AnnaBridge	172:65be27845400	409	/** @defgroup DSI_LP_Command DSI LP Command
AnnaBridge	172:65be27845400	410	* @{
AnnaBridge	172:65be27845400	411	*/
AnnaBridge	172:65be27845400	412	#define DSI_LP_COMMAND_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	413	#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
AnnaBridge	172:65be27845400	414	/**
AnnaBridge	172:65be27845400	415	* @}
AnnaBridge	172:65be27845400	416	*/
AnnaBridge	172:65be27845400	417
AnnaBridge	172:65be27845400	418	/** @defgroup DSI_LP_HFP DSI LP HFP
AnnaBridge	172:65be27845400	419	* @{
AnnaBridge	172:65be27845400	420	*/
AnnaBridge	172:65be27845400	421	#define DSI_LP_HFP_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	422	#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
AnnaBridge	172:65be27845400	423	/**
AnnaBridge	172:65be27845400	424	* @}
AnnaBridge	172:65be27845400	425	*/
AnnaBridge	172:65be27845400	426
AnnaBridge	172:65be27845400	427	/** @defgroup DSI_LP_HBP DSI LP HBP
AnnaBridge	172:65be27845400	428	* @{
AnnaBridge	172:65be27845400	429	*/
AnnaBridge	172:65be27845400	430	#define DSI_LP_HBP_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	431	#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
AnnaBridge	172:65be27845400	432	/**
AnnaBridge	172:65be27845400	433	* @}
AnnaBridge	172:65be27845400	434	*/
AnnaBridge	172:65be27845400	435
AnnaBridge	172:65be27845400	436	/** @defgroup DSI_LP_VACT DSI LP VACT
AnnaBridge	172:65be27845400	437	* @{
AnnaBridge	172:65be27845400	438	*/
AnnaBridge	172:65be27845400	439	#define DSI_LP_VACT_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	440	#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
AnnaBridge	172:65be27845400	441	/**
AnnaBridge	172:65be27845400	442	* @}
AnnaBridge	172:65be27845400	443	*/
AnnaBridge	172:65be27845400	444
AnnaBridge	172:65be27845400	445	/** @defgroup DSI_LP_VFP DSI LP VFP
AnnaBridge	172:65be27845400	446	* @{
AnnaBridge	172:65be27845400	447	*/
AnnaBridge	172:65be27845400	448	#define DSI_LP_VFP_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	449	#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
AnnaBridge	172:65be27845400	450	/**
AnnaBridge	172:65be27845400	451	* @}
AnnaBridge	172:65be27845400	452	*/
AnnaBridge	172:65be27845400	453
AnnaBridge	172:65be27845400	454	/** @defgroup DSI_LP_VBP DSI LP VBP
AnnaBridge	172:65be27845400	455	* @{
AnnaBridge	172:65be27845400	456	*/
AnnaBridge	172:65be27845400	457	#define DSI_LP_VBP_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	458	#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
AnnaBridge	172:65be27845400	459	/**
AnnaBridge	172:65be27845400	460	* @}
AnnaBridge	172:65be27845400	461	*/
AnnaBridge	172:65be27845400	462
AnnaBridge	172:65be27845400	463	/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
AnnaBridge	172:65be27845400	464	* @{
AnnaBridge	172:65be27845400	465	*/
AnnaBridge	172:65be27845400	466	#define DSI_LP_VSYNC_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	467	#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
AnnaBridge	172:65be27845400	468	/**
AnnaBridge	172:65be27845400	469	* @}
AnnaBridge	172:65be27845400	470	*/
AnnaBridge	172:65be27845400	471
AnnaBridge	172:65be27845400	472	/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
AnnaBridge	172:65be27845400	473	* @{
AnnaBridge	172:65be27845400	474	*/
AnnaBridge	172:65be27845400	475	#define DSI_FBTAA_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	476	#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
AnnaBridge	172:65be27845400	477	/**
AnnaBridge	172:65be27845400	478	* @}
AnnaBridge	172:65be27845400	479	*/
AnnaBridge	172:65be27845400	480
AnnaBridge	172:65be27845400	481	/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
AnnaBridge	172:65be27845400	482	* @{
AnnaBridge	172:65be27845400	483	*/
AnnaBridge	172:65be27845400	484	#define DSI_TE_DSILINK 0x00000000U
AnnaBridge	172:65be27845400	485	#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
AnnaBridge	172:65be27845400	486	/**
AnnaBridge	172:65be27845400	487	* @}
AnnaBridge	172:65be27845400	488	*/
AnnaBridge	172:65be27845400	489
AnnaBridge	172:65be27845400	490	/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
AnnaBridge	172:65be27845400	491	* @{
AnnaBridge	172:65be27845400	492	*/
AnnaBridge	172:65be27845400	493	#define DSI_TE_RISING_EDGE 0x00000000U
AnnaBridge	172:65be27845400	494	#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
AnnaBridge	172:65be27845400	495	/**
AnnaBridge	172:65be27845400	496	* @}
AnnaBridge	172:65be27845400	497	*/
AnnaBridge	172:65be27845400	498
AnnaBridge	172:65be27845400	499	/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
AnnaBridge	172:65be27845400	500	* @{
AnnaBridge	172:65be27845400	501	*/
AnnaBridge	172:65be27845400	502	#define DSI_VSYNC_FALLING 0x00000000U
AnnaBridge	172:65be27845400	503	#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
AnnaBridge	172:65be27845400	504	/**
AnnaBridge	172:65be27845400	505	* @}
AnnaBridge	172:65be27845400	506	*/
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
AnnaBridge	172:65be27845400	509	* @{
AnnaBridge	172:65be27845400	510	*/
AnnaBridge	172:65be27845400	511	#define DSI_AR_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	512	#define DSI_AR_ENABLE DSI_WCFGR_AR
AnnaBridge	172:65be27845400	513	/**
AnnaBridge	172:65be27845400	514	* @}
AnnaBridge	172:65be27845400	515	*/
AnnaBridge	172:65be27845400	516
AnnaBridge	172:65be27845400	517	/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
AnnaBridge	172:65be27845400	518	* @{
AnnaBridge	172:65be27845400	519	*/
AnnaBridge	172:65be27845400	520	#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	521	#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
AnnaBridge	172:65be27845400	522	/**
AnnaBridge	172:65be27845400	523	* @}
AnnaBridge	172:65be27845400	524	*/
AnnaBridge	172:65be27845400	525
AnnaBridge	172:65be27845400	526	/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
AnnaBridge	172:65be27845400	527	* @{
AnnaBridge	172:65be27845400	528	*/
AnnaBridge	172:65be27845400	529	#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	530	#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
AnnaBridge	172:65be27845400	531	/**
AnnaBridge	172:65be27845400	532	* @}
AnnaBridge	172:65be27845400	533	*/
AnnaBridge	172:65be27845400	534
AnnaBridge	172:65be27845400	535	/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
AnnaBridge	172:65be27845400	536	* @{
AnnaBridge	172:65be27845400	537	*/
AnnaBridge	172:65be27845400	538	#define DSI_LP_GSW0P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	539	#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
AnnaBridge	172:65be27845400	540	/**
AnnaBridge	172:65be27845400	541	* @}
AnnaBridge	172:65be27845400	542	*/
AnnaBridge	172:65be27845400	543
AnnaBridge	172:65be27845400	544	/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
AnnaBridge	172:65be27845400	545	* @{
AnnaBridge	172:65be27845400	546	*/
AnnaBridge	172:65be27845400	547	#define DSI_LP_GSW1P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	548	#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
AnnaBridge	172:65be27845400	549	/**
AnnaBridge	172:65be27845400	550	* @}
AnnaBridge	172:65be27845400	551	*/
AnnaBridge	172:65be27845400	552
AnnaBridge	172:65be27845400	553	/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
AnnaBridge	172:65be27845400	554	* @{
AnnaBridge	172:65be27845400	555	*/
AnnaBridge	172:65be27845400	556	#define DSI_LP_GSW2P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	557	#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
AnnaBridge	172:65be27845400	558	/**
AnnaBridge	172:65be27845400	559	* @}
AnnaBridge	172:65be27845400	560	*/
AnnaBridge	172:65be27845400	561
AnnaBridge	172:65be27845400	562	/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
AnnaBridge	172:65be27845400	563	* @{
AnnaBridge	172:65be27845400	564	*/
AnnaBridge	172:65be27845400	565	#define DSI_LP_GSR0P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	566	#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
AnnaBridge	172:65be27845400	567	/**
AnnaBridge	172:65be27845400	568	* @}
AnnaBridge	172:65be27845400	569	*/
AnnaBridge	172:65be27845400	570
AnnaBridge	172:65be27845400	571	/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
AnnaBridge	172:65be27845400	572	* @{
AnnaBridge	172:65be27845400	573	*/
AnnaBridge	172:65be27845400	574	#define DSI_LP_GSR1P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	575	#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
AnnaBridge	172:65be27845400	576	/**
AnnaBridge	172:65be27845400	577	* @}
AnnaBridge	172:65be27845400	578	*/
AnnaBridge	172:65be27845400	579
AnnaBridge	172:65be27845400	580	/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
AnnaBridge	172:65be27845400	581	* @{
AnnaBridge	172:65be27845400	582	*/
AnnaBridge	172:65be27845400	583	#define DSI_LP_GSR2P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	584	#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
AnnaBridge	172:65be27845400	585	/**
AnnaBridge	172:65be27845400	586	* @}
AnnaBridge	172:65be27845400	587	*/
AnnaBridge	172:65be27845400	588
AnnaBridge	172:65be27845400	589	/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
AnnaBridge	172:65be27845400	590	* @{
AnnaBridge	172:65be27845400	591	*/
AnnaBridge	172:65be27845400	592	#define DSI_LP_GLW_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	593	#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
AnnaBridge	172:65be27845400	594	/**
AnnaBridge	172:65be27845400	595	* @}
AnnaBridge	172:65be27845400	596	*/
AnnaBridge	172:65be27845400	597
AnnaBridge	172:65be27845400	598	/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
AnnaBridge	172:65be27845400	599	* @{
AnnaBridge	172:65be27845400	600	*/
AnnaBridge	172:65be27845400	601	#define DSI_LP_DSW0P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	602	#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
AnnaBridge	172:65be27845400	603	/**
AnnaBridge	172:65be27845400	604	* @}
AnnaBridge	172:65be27845400	605	*/
AnnaBridge	172:65be27845400	606
AnnaBridge	172:65be27845400	607	/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
AnnaBridge	172:65be27845400	608	* @{
AnnaBridge	172:65be27845400	609	*/
AnnaBridge	172:65be27845400	610	#define DSI_LP_DSW1P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	611	#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
AnnaBridge	172:65be27845400	612	/**
AnnaBridge	172:65be27845400	613	* @}
AnnaBridge	172:65be27845400	614	*/
AnnaBridge	172:65be27845400	615
AnnaBridge	172:65be27845400	616	/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
AnnaBridge	172:65be27845400	617	* @{
AnnaBridge	172:65be27845400	618	*/
AnnaBridge	172:65be27845400	619	#define DSI_LP_DSR0P_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	620	#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
AnnaBridge	172:65be27845400	621	/**
AnnaBridge	172:65be27845400	622	* @}
AnnaBridge	172:65be27845400	623	*/
AnnaBridge	172:65be27845400	624
AnnaBridge	172:65be27845400	625	/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
AnnaBridge	172:65be27845400	626	* @{
AnnaBridge	172:65be27845400	627	*/
AnnaBridge	172:65be27845400	628	#define DSI_LP_DLW_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	629	#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
AnnaBridge	172:65be27845400	630	/**
AnnaBridge	172:65be27845400	631	* @}
AnnaBridge	172:65be27845400	632	*/
AnnaBridge	172:65be27845400	633
AnnaBridge	172:65be27845400	634	/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
AnnaBridge	172:65be27845400	635	* @{
AnnaBridge	172:65be27845400	636	*/
AnnaBridge	172:65be27845400	637	#define DSI_LP_MRDP_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	638	#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
AnnaBridge	172:65be27845400	639	/**
AnnaBridge	172:65be27845400	640	* @}
AnnaBridge	172:65be27845400	641	*/
AnnaBridge	172:65be27845400	642
AnnaBridge	172:65be27845400	643	/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
AnnaBridge	172:65be27845400	644	* @{
AnnaBridge	172:65be27845400	645	*/
AnnaBridge	172:65be27845400	646	#define DSI_HS_PM_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	647	#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
AnnaBridge	172:65be27845400	648	/**
AnnaBridge	172:65be27845400	649	* @}
AnnaBridge	172:65be27845400	650	*/
AnnaBridge	172:65be27845400	651
AnnaBridge	172:65be27845400	652
AnnaBridge	172:65be27845400	653	/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
AnnaBridge	172:65be27845400	654	* @{
AnnaBridge	172:65be27845400	655	*/
AnnaBridge	172:65be27845400	656	#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	657	#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
AnnaBridge	172:65be27845400	658	/**
AnnaBridge	172:65be27845400	659	* @}
AnnaBridge	172:65be27845400	660	*/
AnnaBridge	172:65be27845400	661
AnnaBridge	172:65be27845400	662	/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
AnnaBridge	172:65be27845400	663	* @{
AnnaBridge	172:65be27845400	664	*/
AnnaBridge	172:65be27845400	665	#define DSI_ONE_DATA_LANE 0U
AnnaBridge	172:65be27845400	666	#define DSI_TWO_DATA_LANES 1U
AnnaBridge	172:65be27845400	667	/**
AnnaBridge	172:65be27845400	668	* @}
AnnaBridge	172:65be27845400	669	*/
AnnaBridge	172:65be27845400	670
AnnaBridge	172:65be27845400	671	/** @defgroup DSI_FlowControl DSI Flow Control
AnnaBridge	172:65be27845400	672	* @{
AnnaBridge	172:65be27845400	673	*/
AnnaBridge	172:65be27845400	674	#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
AnnaBridge	172:65be27845400	675	#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
AnnaBridge	172:65be27845400	676	#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
AnnaBridge	172:65be27845400	677	#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
AnnaBridge	172:65be27845400	678	#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
AnnaBridge	172:65be27845400	679	#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX \| DSI_FLOW_CONTROL_ECC_RX \| \
AnnaBridge	172:65be27845400	680	DSI_FLOW_CONTROL_BTA \| DSI_FLOW_CONTROL_EOTP_RX \| \
AnnaBridge	172:65be27845400	681	DSI_FLOW_CONTROL_EOTP_TX)
AnnaBridge	172:65be27845400	682	/**
AnnaBridge	172:65be27845400	683	* @}
AnnaBridge	172:65be27845400	684	*/
AnnaBridge	172:65be27845400	685
AnnaBridge	172:65be27845400	686	/** @defgroup DSI_Color_Coding DSI Color Coding
AnnaBridge	172:65be27845400	687	* @{
AnnaBridge	172:65be27845400	688	*/
AnnaBridge	172:65be27845400	689	#define DSI_RGB565 0x00000000U /!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration /
AnnaBridge	172:65be27845400	690	#define DSI_RGB666 0x00000003U /!< The value 0x00000004 can also be used for the RGB666 color mode configuration /
AnnaBridge	172:65be27845400	691	#define DSI_RGB888 0x00000005U
AnnaBridge	172:65be27845400	692	/**
AnnaBridge	172:65be27845400	693	* @}
AnnaBridge	172:65be27845400	694	*/
AnnaBridge	172:65be27845400	695
AnnaBridge	172:65be27845400	696	/** @defgroup DSI_LooselyPacked DSI Loosely Packed
AnnaBridge	172:65be27845400	697	* @{
AnnaBridge	172:65be27845400	698	*/
AnnaBridge	172:65be27845400	699	#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
AnnaBridge	172:65be27845400	700	#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
AnnaBridge	172:65be27845400	701	/**
AnnaBridge	172:65be27845400	702	* @}
AnnaBridge	172:65be27845400	703	*/
AnnaBridge	172:65be27845400	704
AnnaBridge	172:65be27845400	705	/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
AnnaBridge	172:65be27845400	706	* @{
AnnaBridge	172:65be27845400	707	*/
AnnaBridge	172:65be27845400	708	#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
AnnaBridge	172:65be27845400	709	#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
AnnaBridge	172:65be27845400	710	/**
AnnaBridge	172:65be27845400	711	* @}
AnnaBridge	172:65be27845400	712	*/
AnnaBridge	172:65be27845400	713
AnnaBridge	172:65be27845400	714	/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
AnnaBridge	172:65be27845400	715	* @{
AnnaBridge	172:65be27845400	716	*/
AnnaBridge	172:65be27845400	717	#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
AnnaBridge	172:65be27845400	718	#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
AnnaBridge	172:65be27845400	719	/**
AnnaBridge	172:65be27845400	720	* @}
AnnaBridge	172:65be27845400	721	*/
AnnaBridge	172:65be27845400	722
AnnaBridge	172:65be27845400	723	/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
AnnaBridge	172:65be27845400	724	* @{
AnnaBridge	172:65be27845400	725	*/
AnnaBridge	172:65be27845400	726	#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
AnnaBridge	172:65be27845400	727	#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
AnnaBridge	172:65be27845400	728	/**
AnnaBridge	172:65be27845400	729	* @}
AnnaBridge	172:65be27845400	730	*/
AnnaBridge	172:65be27845400	731
AnnaBridge	172:65be27845400	732	/** @defgroup DSI_PLL_IDF DSI PLL IDF
AnnaBridge	172:65be27845400	733	* @{
AnnaBridge	172:65be27845400	734	*/
AnnaBridge	172:65be27845400	735	#define DSI_PLL_IN_DIV1 0x00000001U
AnnaBridge	172:65be27845400	736	#define DSI_PLL_IN_DIV2 0x00000002U
AnnaBridge	172:65be27845400	737	#define DSI_PLL_IN_DIV3 0x00000003U
AnnaBridge	172:65be27845400	738	#define DSI_PLL_IN_DIV4 0x00000004U
AnnaBridge	172:65be27845400	739	#define DSI_PLL_IN_DIV5 0x00000005U
AnnaBridge	172:65be27845400	740	#define DSI_PLL_IN_DIV6 0x00000006U
AnnaBridge	172:65be27845400	741	#define DSI_PLL_IN_DIV7 0x00000007U
AnnaBridge	172:65be27845400	742	/**
AnnaBridge	172:65be27845400	743	* @}
AnnaBridge	172:65be27845400	744	*/
AnnaBridge	172:65be27845400	745
AnnaBridge	172:65be27845400	746	/** @defgroup DSI_PLL_ODF DSI PLL ODF
AnnaBridge	172:65be27845400	747	* @{
AnnaBridge	172:65be27845400	748	*/
AnnaBridge	172:65be27845400	749	#define DSI_PLL_OUT_DIV1 0x00000000U
AnnaBridge	172:65be27845400	750	#define DSI_PLL_OUT_DIV2 0x00000001U
AnnaBridge	172:65be27845400	751	#define DSI_PLL_OUT_DIV4 0x00000002U
AnnaBridge	172:65be27845400	752	#define DSI_PLL_OUT_DIV8 0x00000003U
AnnaBridge	172:65be27845400	753	/**
AnnaBridge	172:65be27845400	754	* @}
AnnaBridge	172:65be27845400	755	*/
AnnaBridge	172:65be27845400	756
AnnaBridge	172:65be27845400	757	/** @defgroup DSI_Flags DSI Flags
AnnaBridge	172:65be27845400	758	* @{
AnnaBridge	172:65be27845400	759	*/
AnnaBridge	172:65be27845400	760	#define DSI_FLAG_TE DSI_WISR_TEIF
AnnaBridge	172:65be27845400	761	#define DSI_FLAG_ER DSI_WISR_ERIF
AnnaBridge	172:65be27845400	762	#define DSI_FLAG_BUSY DSI_WISR_BUSY
AnnaBridge	172:65be27845400	763	#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
AnnaBridge	172:65be27845400	764	#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
AnnaBridge	172:65be27845400	765	#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
AnnaBridge	172:65be27845400	766	#define DSI_FLAG_RRS DSI_WISR_RRS
AnnaBridge	172:65be27845400	767	#define DSI_FLAG_RR DSI_WISR_RRIF
AnnaBridge	172:65be27845400	768	/**
AnnaBridge	172:65be27845400	769	* @}
AnnaBridge	172:65be27845400	770	*/
AnnaBridge	172:65be27845400	771
AnnaBridge	172:65be27845400	772	/** @defgroup DSI_Interrupts DSI Interrupts
AnnaBridge	172:65be27845400	773	* @{
AnnaBridge	172:65be27845400	774	*/
AnnaBridge	172:65be27845400	775	#define DSI_IT_TE DSI_WIER_TEIE
AnnaBridge	172:65be27845400	776	#define DSI_IT_ER DSI_WIER_ERIE
AnnaBridge	172:65be27845400	777	#define DSI_IT_PLLL DSI_WIER_PLLLIE
AnnaBridge	172:65be27845400	778	#define DSI_IT_PLLU DSI_WIER_PLLUIE
AnnaBridge	172:65be27845400	779	#define DSI_IT_RR DSI_WIER_RRIE
AnnaBridge	172:65be27845400	780	/**
AnnaBridge	172:65be27845400	781	* @}
AnnaBridge	172:65be27845400	782	*/
AnnaBridge	172:65be27845400	783
AnnaBridge	172:65be27845400	784	/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
AnnaBridge	172:65be27845400	785	* @{
AnnaBridge	172:65be27845400	786	*/
AnnaBridge	172:65be27845400	787	#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /!< DCS short write, no parameters /
AnnaBridge	172:65be27845400	788	#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /!< DCS short write, one parameter /
AnnaBridge	172:65be27845400	789	#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /!< Generic short write, no parameters /
AnnaBridge	172:65be27845400	790	#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /!< Generic short write, one parameter /
AnnaBridge	172:65be27845400	791	#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /!< Generic short write, two parameters /
AnnaBridge	172:65be27845400	792	/**
AnnaBridge	172:65be27845400	793	* @}
AnnaBridge	172:65be27845400	794	*/
AnnaBridge	172:65be27845400	795
AnnaBridge	172:65be27845400	796	/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
AnnaBridge	172:65be27845400	797	* @{
AnnaBridge	172:65be27845400	798	*/
AnnaBridge	172:65be27845400	799	#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /!< DCS long write /
AnnaBridge	172:65be27845400	800	#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /!< Generic long write /
AnnaBridge	172:65be27845400	801	/**
AnnaBridge	172:65be27845400	802	* @}
AnnaBridge	172:65be27845400	803	*/
AnnaBridge	172:65be27845400	804
AnnaBridge	172:65be27845400	805	/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
AnnaBridge	172:65be27845400	806	* @{
AnnaBridge	172:65be27845400	807	*/
AnnaBridge	172:65be27845400	808	#define DSI_DCS_SHORT_PKT_READ 0x00000006U /!< DCS short read /
AnnaBridge	172:65be27845400	809	#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /!< Generic short read, no parameters /
AnnaBridge	172:65be27845400	810	#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /!< Generic short read, one parameter /
AnnaBridge	172:65be27845400	811	#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /!< Generic short read, two parameters /
AnnaBridge	172:65be27845400	812	/**
AnnaBridge	172:65be27845400	813	* @}
AnnaBridge	172:65be27845400	814	*/
AnnaBridge	172:65be27845400	815
AnnaBridge	172:65be27845400	816	/** @defgroup DSI_Error_Data_Type DSI Error Data Type
AnnaBridge	172:65be27845400	817	* @{
AnnaBridge	172:65be27845400	818	*/
AnnaBridge	172:65be27845400	819	#define HAL_DSI_ERROR_NONE 0U
AnnaBridge	172:65be27845400	820	#define HAL_DSI_ERROR_ACK 0x00000001U /!< acknowledge errors /
AnnaBridge	172:65be27845400	821	#define HAL_DSI_ERROR_PHY 0x00000002U /!< PHY related errors /
AnnaBridge	172:65be27845400	822	#define HAL_DSI_ERROR_TX 0x00000004U /!< transmission error /
AnnaBridge	172:65be27845400	823	#define HAL_DSI_ERROR_RX 0x00000008U /!< reception error /
AnnaBridge	172:65be27845400	824	#define HAL_DSI_ERROR_ECC 0x00000010U /!< ECC errors /
AnnaBridge	172:65be27845400	825	#define HAL_DSI_ERROR_CRC 0x00000020U /!< CRC error /
AnnaBridge	172:65be27845400	826	#define HAL_DSI_ERROR_PSE 0x00000040U /!< Packet Size error /
AnnaBridge	172:65be27845400	827	#define HAL_DSI_ERROR_EOT 0x00000080U /!< End Of Transmission error /
AnnaBridge	172:65be27845400	828	#define HAL_DSI_ERROR_OVF 0x00000100U /!< FIFO overflow error /
AnnaBridge	172:65be27845400	829	#define HAL_DSI_ERROR_GEN 0x00000200U /!< Generic FIFO related errors /
AnnaBridge	172:65be27845400	830	/**
AnnaBridge	172:65be27845400	831	* @}
AnnaBridge	172:65be27845400	832	*/
AnnaBridge	172:65be27845400	833
AnnaBridge	172:65be27845400	834	/** @defgroup DSI_Lane_Group DSI Lane Group
AnnaBridge	172:65be27845400	835	* @{
AnnaBridge	172:65be27845400	836	*/
AnnaBridge	172:65be27845400	837	#define DSI_CLOCK_LANE 0x00000000U
AnnaBridge	172:65be27845400	838	#define DSI_DATA_LANES 0x00000001U
AnnaBridge	172:65be27845400	839	/**
AnnaBridge	172:65be27845400	840	* @}
AnnaBridge	172:65be27845400	841	*/
AnnaBridge	172:65be27845400	842
AnnaBridge	172:65be27845400	843	/** @defgroup DSI_Communication_Delay DSI Communication Delay
AnnaBridge	172:65be27845400	844	* @{
AnnaBridge	172:65be27845400	845	*/
AnnaBridge	172:65be27845400	846	#define DSI_SLEW_RATE_HSTX 0x00000000U
AnnaBridge	172:65be27845400	847	#define DSI_SLEW_RATE_LPTX 0x00000001U
AnnaBridge	172:65be27845400	848	#define DSI_HS_DELAY 0x00000002U
AnnaBridge	172:65be27845400	849	/**
AnnaBridge	172:65be27845400	850	* @}
AnnaBridge	172:65be27845400	851	*/
AnnaBridge	172:65be27845400	852
AnnaBridge	172:65be27845400	853	/** @defgroup DSI_CustomLane DSI CustomLane
AnnaBridge	172:65be27845400	854	* @{
AnnaBridge	172:65be27845400	855	*/
AnnaBridge	172:65be27845400	856	#define DSI_SWAP_LANE_PINS 0x00000000U
AnnaBridge	172:65be27845400	857	#define DSI_INVERT_HS_SIGNAL 0x00000001U
AnnaBridge	172:65be27845400	858	/**
AnnaBridge	172:65be27845400	859	* @}
AnnaBridge	172:65be27845400	860	*/
AnnaBridge	172:65be27845400	861
AnnaBridge	172:65be27845400	862	/** @defgroup DSI_Lane_Select DSI Lane Select
AnnaBridge	172:65be27845400	863	* @{
AnnaBridge	172:65be27845400	864	*/
AnnaBridge	172:65be27845400	865	#define DSI_CLK_LANE 0x00000000U
AnnaBridge	172:65be27845400	866	#define DSI_DATA_LANE0 0x00000001U
AnnaBridge	172:65be27845400	867	#define DSI_DATA_LANE1 0x00000002U
AnnaBridge	172:65be27845400	868	/**
AnnaBridge	172:65be27845400	869	* @}
AnnaBridge	172:65be27845400	870	*/
AnnaBridge	172:65be27845400	871
AnnaBridge	172:65be27845400	872	/** @defgroup DSI_PHY_Timing DSI PHY Timing
AnnaBridge	172:65be27845400	873	* @{
AnnaBridge	172:65be27845400	874	*/
AnnaBridge	172:65be27845400	875	#define DSI_TCLK_POST 0x00000000U
AnnaBridge	172:65be27845400	876	#define DSI_TLPX_CLK 0x00000001U
AnnaBridge	172:65be27845400	877	#define DSI_THS_EXIT 0x00000002U
AnnaBridge	172:65be27845400	878	#define DSI_TLPX_DATA 0x00000003U
AnnaBridge	172:65be27845400	879	#define DSI_THS_ZERO 0x00000004U
AnnaBridge	172:65be27845400	880	#define DSI_THS_TRAIL 0x00000005U
AnnaBridge	172:65be27845400	881	#define DSI_THS_PREPARE 0x00000006U
AnnaBridge	172:65be27845400	882	#define DSI_TCLK_ZERO 0x00000007U
AnnaBridge	172:65be27845400	883	#define DSI_TCLK_PREPARE 0x00000008U
AnnaBridge	172:65be27845400	884	/**
AnnaBridge	172:65be27845400	885	* @}
AnnaBridge	172:65be27845400	886	*/
AnnaBridge	172:65be27845400	887
AnnaBridge	172:65be27845400	888	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	172:65be27845400	889	/**
AnnaBridge	172:65be27845400	890	* @brief Reset DSI handle state.
AnnaBridge	172:65be27845400	891	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	892	* @retval None
AnnaBridge	172:65be27845400	893	*/
AnnaBridge	172:65be27845400	894	#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	/**
AnnaBridge	172:65be27845400	897	* @brief Enables the DSI host.
AnnaBridge	172:65be27845400	898	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	899	* @retval None.
AnnaBridge	172:65be27845400	900	*/
AnnaBridge	172:65be27845400	901	#define __HAL_DSI_ENABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	902	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	903	SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	172:65be27845400	904	/* Delay after an DSI Host enabling */ \
AnnaBridge	172:65be27845400	905	tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	172:65be27845400	906	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	907	}while(0U)
AnnaBridge	172:65be27845400	908
AnnaBridge	172:65be27845400	909	/**
AnnaBridge	172:65be27845400	910	* @brief Disables the DSI host.
AnnaBridge	172:65be27845400	911	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	912	* @retval None.
AnnaBridge	172:65be27845400	913	*/
AnnaBridge	172:65be27845400	914	#define __HAL_DSI_DISABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	915	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	916	CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	172:65be27845400	917	/* Delay after an DSI Host disabling */ \
AnnaBridge	172:65be27845400	918	tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	172:65be27845400	919	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	920	}while(0U)
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	/**
AnnaBridge	172:65be27845400	923	* @brief Enables the DSI wrapper.
AnnaBridge	172:65be27845400	924	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	925	* @retval None.
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927	#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	928	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	929	SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	172:65be27845400	930	/* Delay after an DSI warpper enabling */ \
AnnaBridge	172:65be27845400	931	tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	172:65be27845400	932	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	933	}while(0U)
AnnaBridge	172:65be27845400	934
AnnaBridge	172:65be27845400	935	/**
AnnaBridge	172:65be27845400	936	* @brief Disable the DSI wrapper.
AnnaBridge	172:65be27845400	937	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	938	* @retval None.
AnnaBridge	172:65be27845400	939	*/
AnnaBridge	172:65be27845400	940	#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	941	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	942	CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	172:65be27845400	943	/* Delay after an DSI warpper disabling*/ \
AnnaBridge	172:65be27845400	944	tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	172:65be27845400	945	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	946	}while(0U)
AnnaBridge	172:65be27845400	947
AnnaBridge	172:65be27845400	948	/**
AnnaBridge	172:65be27845400	949	* @brief Enables the DSI PLL.
AnnaBridge	172:65be27845400	950	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	951	* @retval None.
AnnaBridge	172:65be27845400	952	*/
AnnaBridge	172:65be27845400	953	#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	954	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	955	SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	172:65be27845400	956	/* Delay after an DSI PLL enabling */ \
AnnaBridge	172:65be27845400	957	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	172:65be27845400	958	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	959	}while(0U)
AnnaBridge	172:65be27845400	960
AnnaBridge	172:65be27845400	961	/**
AnnaBridge	172:65be27845400	962	* @brief Disables the DSI PLL.
AnnaBridge	172:65be27845400	963	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	964	* @retval None.
AnnaBridge	172:65be27845400	965	*/
AnnaBridge	172:65be27845400	966	#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	967	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	968	CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	172:65be27845400	969	/* Delay after an DSI PLL disabling */ \
AnnaBridge	172:65be27845400	970	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	172:65be27845400	971	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	972	}while(0U)
AnnaBridge	172:65be27845400	973
AnnaBridge	172:65be27845400	974	/**
AnnaBridge	172:65be27845400	975	* @brief Enables the DSI regulator.
AnnaBridge	172:65be27845400	976	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	977	* @retval None.
AnnaBridge	172:65be27845400	978	*/
AnnaBridge	172:65be27845400	979	#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	980	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	981	SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	172:65be27845400	982	/* Delay after an DSI regulator enabling */ \
AnnaBridge	172:65be27845400	983	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	172:65be27845400	984	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	985	}while(0U)
AnnaBridge	172:65be27845400	986
AnnaBridge	172:65be27845400	987	/**
AnnaBridge	172:65be27845400	988	* @brief Disables the DSI regulator.
AnnaBridge	172:65be27845400	989	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	990	* @retval None.
AnnaBridge	172:65be27845400	991	*/
AnnaBridge	172:65be27845400	992	#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
AnnaBridge	172:65be27845400	993	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	172:65be27845400	994	CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	172:65be27845400	995	/* Delay after an DSI regulator disabling */ \
AnnaBridge	172:65be27845400	996	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	172:65be27845400	997	UNUSED(tmpreg); \
AnnaBridge	172:65be27845400	998	}while(0U)
AnnaBridge	172:65be27845400	999
AnnaBridge	172:65be27845400	1000	/**
AnnaBridge	172:65be27845400	1001	* @brief Get the DSI pending flags.
AnnaBridge	172:65be27845400	1002	* @param __HANDLE__: DSI handle.
AnnaBridge	172:65be27845400	1003	* @param __FLAG__: Get the specified flag.
AnnaBridge	172:65be27845400	1004	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1005	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge	172:65be27845400	1006	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge	172:65be27845400	1007	* @arg DSI_FLAG_BUSY : Busy Flag
AnnaBridge	172:65be27845400	1008	* @arg DSI_FLAG_PLLLS: PLL Lock Status
AnnaBridge	172:65be27845400	1009	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge	172:65be27845400	1010	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge	172:65be27845400	1011	* @arg DSI_FLAG_RRS : Regulator Ready Flag
AnnaBridge	172:65be27845400	1012	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge	172:65be27845400	1013	* @retval The state of FLAG (SET or RESET).
AnnaBridge	172:65be27845400	1014	*/
AnnaBridge	172:65be27845400	1015	#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
AnnaBridge	172:65be27845400	1016
AnnaBridge	172:65be27845400	1017	/**
AnnaBridge	172:65be27845400	1018	* @brief Clears the DSI pending flags.
AnnaBridge	172:65be27845400	1019	* @param __HANDLE__: DSI handle.
AnnaBridge	172:65be27845400	1020	* @param __FLAG__: specifies the flag to clear.
AnnaBridge	172:65be27845400	1021	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1022	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge	172:65be27845400	1023	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge	172:65be27845400	1024	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge	172:65be27845400	1025	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge	172:65be27845400	1026	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge	172:65be27845400	1027	* @retval None
AnnaBridge	172:65be27845400	1028	*/
AnnaBridge	172:65be27845400	1029	#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
AnnaBridge	172:65be27845400	1030
AnnaBridge	172:65be27845400	1031	/**
AnnaBridge	172:65be27845400	1032	* @brief Enables the specified DSI interrupts.
AnnaBridge	172:65be27845400	1033	* @param __HANDLE__: DSI handle.
AnnaBridge	172:65be27845400	1034	* @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
AnnaBridge	172:65be27845400	1035	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1036	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	172:65be27845400	1037	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	172:65be27845400	1038	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	172:65be27845400	1039	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	172:65be27845400	1040	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	172:65be27845400	1041	* @retval None
AnnaBridge	172:65be27845400	1042	*/
AnnaBridge	172:65be27845400	1043	#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	1044
AnnaBridge	172:65be27845400	1045	/**
AnnaBridge	172:65be27845400	1046	* @brief Disables the specified DSI interrupts.
AnnaBridge	172:65be27845400	1047	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	1048	* @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
AnnaBridge	172:65be27845400	1049	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	1050	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	172:65be27845400	1051	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	172:65be27845400	1052	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	172:65be27845400	1053	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	172:65be27845400	1054	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	172:65be27845400	1055	* @retval None
AnnaBridge	172:65be27845400	1056	*/
AnnaBridge	172:65be27845400	1057	#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	1058
AnnaBridge	172:65be27845400	1059	/**
AnnaBridge	172:65be27845400	1060	* @brief Checks whether the specified DSI interrupt source is enabled or not.
AnnaBridge	172:65be27845400	1061	* @param __HANDLE__: DSI handle
AnnaBridge	172:65be27845400	1062	* @param __INTERRUPT__: specifies the DSI interrupt source to check.
AnnaBridge	172:65be27845400	1063	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1064	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	172:65be27845400	1065	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	172:65be27845400	1066	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	172:65be27845400	1067	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	172:65be27845400	1068	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	172:65be27845400	1069	* @retval The state of INTERRUPT (SET or RESET).
AnnaBridge	172:65be27845400	1070	*/
AnnaBridge	172:65be27845400	1071	#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
AnnaBridge	172:65be27845400	1072
AnnaBridge	172:65be27845400	1073	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	1074	/** @defgroup DSI_Exported_Functions DSI Exported Functions
AnnaBridge	172:65be27845400	1075	* @{
AnnaBridge	172:65be27845400	1076	*/
AnnaBridge	172:65be27845400	1077	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit);
AnnaBridge	172:65be27845400	1078	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1079	void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1080	void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1081
AnnaBridge	172:65be27845400	1082	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1083	void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1084	void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1085	void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1086
AnnaBridge	172:65be27845400	1087	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
AnnaBridge	172:65be27845400	1088	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg);
AnnaBridge	172:65be27845400	1089	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg);
AnnaBridge	172:65be27845400	1090	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd);
AnnaBridge	172:65be27845400	1091	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
AnnaBridge	172:65be27845400	1092	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers);
AnnaBridge	172:65be27845400	1093	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts);
AnnaBridge	172:65be27845400	1094	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1095	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1096	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1097	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
AnnaBridge	172:65be27845400	1098	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
AnnaBridge	172:65be27845400	1099	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge	172:65be27845400	1100	uint32_t ChannelID,
AnnaBridge	172:65be27845400	1101	uint32_t Mode,
AnnaBridge	172:65be27845400	1102	uint32_t Param1,
AnnaBridge	172:65be27845400	1103	uint32_t Param2);
AnnaBridge	172:65be27845400	1104	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge	172:65be27845400	1105	uint32_t ChannelID,
AnnaBridge	172:65be27845400	1106	uint32_t Mode,
AnnaBridge	172:65be27845400	1107	uint32_t NbParams,
AnnaBridge	172:65be27845400	1108	uint32_t Param1,
AnnaBridge	172:65be27845400	1109	uint8_t* ParametersTable);
AnnaBridge	172:65be27845400	1110	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
AnnaBridge	172:65be27845400	1111	uint32_t ChannelNbr,
AnnaBridge	172:65be27845400	1112	uint8_t* Array,
AnnaBridge	172:65be27845400	1113	uint32_t Size,
AnnaBridge	172:65be27845400	1114	uint32_t Mode,
AnnaBridge	172:65be27845400	1115	uint32_t DCSCmd,
AnnaBridge	172:65be27845400	1116	uint8_t* ParametersTable);
AnnaBridge	172:65be27845400	1117	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1118	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1119	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1120	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1121
AnnaBridge	172:65be27845400	1122	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
AnnaBridge	172:65be27845400	1123	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1124
AnnaBridge	172:65be27845400	1125	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
AnnaBridge	172:65be27845400	1126	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
AnnaBridge	172:65be27845400	1127	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	172:65be27845400	1128	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
AnnaBridge	172:65be27845400	1129	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
AnnaBridge	172:65be27845400	1130	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
AnnaBridge	172:65be27845400	1131	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	172:65be27845400	1132	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	172:65be27845400	1133	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	172:65be27845400	1134	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	172:65be27845400	1135
AnnaBridge	172:65be27845400	1136	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1137	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
AnnaBridge	172:65be27845400	1138	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
AnnaBridge	172:65be27845400	1139	/**
AnnaBridge	172:65be27845400	1140	* @}
AnnaBridge	172:65be27845400	1141	*/
AnnaBridge	172:65be27845400	1142
AnnaBridge	172:65be27845400	1143	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1144	/** @defgroup DSI_Private_Types DSI Private Types
AnnaBridge	172:65be27845400	1145	* @{
AnnaBridge	172:65be27845400	1146	*/
AnnaBridge	172:65be27845400	1147
AnnaBridge	172:65be27845400	1148	/**
AnnaBridge	172:65be27845400	1149	* @}
AnnaBridge	172:65be27845400	1150	*/
AnnaBridge	172:65be27845400	1151
AnnaBridge	172:65be27845400	1152	/* Private defines -----------------------------------------------------------*/
AnnaBridge	172:65be27845400	1153	/** @defgroup DSI_Private_Defines DSI Private Defines
AnnaBridge	172:65be27845400	1154	* @{
AnnaBridge	172:65be27845400	1155	*/
AnnaBridge	172:65be27845400	1156
AnnaBridge	172:65be27845400	1157	/**
AnnaBridge	172:65be27845400	1158	* @}
AnnaBridge	172:65be27845400	1159	*/
AnnaBridge	172:65be27845400	1160
AnnaBridge	172:65be27845400	1161	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	1162	/** @defgroup DSI_Private_Variables DSI Private Variables
AnnaBridge	172:65be27845400	1163	* @{
AnnaBridge	172:65be27845400	1164	*/
AnnaBridge	172:65be27845400	1165
AnnaBridge	172:65be27845400	1166	/**
AnnaBridge	172:65be27845400	1167	* @}
AnnaBridge	172:65be27845400	1168	*/
AnnaBridge	172:65be27845400	1169
AnnaBridge	172:65be27845400	1170	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	1171	/** @defgroup DSI_Private_Constants DSI Private Constants
AnnaBridge	172:65be27845400	1172	* @{
AnnaBridge	172:65be27845400	1173	*/
AnnaBridge	172:65be27845400	1174	#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /!< Maximum return packet configuration /
AnnaBridge	172:65be27845400	1175	/**
AnnaBridge	172:65be27845400	1176	* @}
AnnaBridge	172:65be27845400	1177	*/
AnnaBridge	172:65be27845400	1178
AnnaBridge	172:65be27845400	1179	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1180	/** @defgroup DSI_Private_Macros DSI Private Macros
AnnaBridge	172:65be27845400	1181	* @{
AnnaBridge	172:65be27845400	1182	*/
AnnaBridge	172:65be27845400	1183	#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
AnnaBridge	172:65be27845400	1184	#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) \|\| \
AnnaBridge	172:65be27845400	1185	((IDF) == DSI_PLL_IN_DIV2) \|\| \
AnnaBridge	172:65be27845400	1186	((IDF) == DSI_PLL_IN_DIV3) \|\| \
AnnaBridge	172:65be27845400	1187	((IDF) == DSI_PLL_IN_DIV4) \|\| \
AnnaBridge	172:65be27845400	1188	((IDF) == DSI_PLL_IN_DIV5) \|\| \
AnnaBridge	172:65be27845400	1189	((IDF) == DSI_PLL_IN_DIV6) \|\| \
AnnaBridge	172:65be27845400	1190	((IDF) == DSI_PLL_IN_DIV7))
AnnaBridge	172:65be27845400	1191	#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) \|\| \
AnnaBridge	172:65be27845400	1192	((ODF) == DSI_PLL_OUT_DIV2) \|\| \
AnnaBridge	172:65be27845400	1193	((ODF) == DSI_PLL_OUT_DIV4) \|\| \
AnnaBridge	172:65be27845400	1194	((ODF) == DSI_PLL_OUT_DIV8))
AnnaBridge	172:65be27845400	1195	#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) \|\| ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
AnnaBridge	172:65be27845400	1196	#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) \|\| ((NumberOfLanes) == DSI_TWO_DATA_LANES))
AnnaBridge	172:65be27845400	1197	#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) \| DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
AnnaBridge	172:65be27845400	1198	#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
AnnaBridge	172:65be27845400	1199	#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) \|\| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
AnnaBridge	172:65be27845400	1200	#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) \|\| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
AnnaBridge	172:65be27845400	1201	#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) \|\| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
AnnaBridge	172:65be27845400	1202	#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) \|\| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
AnnaBridge	172:65be27845400	1203	#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) \|\| \
AnnaBridge	172:65be27845400	1204	((VideoModeType) == DSI_VID_MODE_NB_EVENTS) \|\| \
AnnaBridge	172:65be27845400	1205	((VideoModeType) == DSI_VID_MODE_BURST))
AnnaBridge	172:65be27845400	1206	#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) \|\| ((ColorMode) == DSI_COLOR_MODE_EIGHT))
AnnaBridge	172:65be27845400	1207	#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) \|\| ((ShutDown) == DSI_DISPLAY_OFF))
AnnaBridge	172:65be27845400	1208	#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) \|\| ((LPCommand) == DSI_LP_COMMAND_ENABLE))
AnnaBridge	172:65be27845400	1209	#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) \|\| ((LPHFP) == DSI_LP_HFP_ENABLE))
AnnaBridge	172:65be27845400	1210	#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) \|\| ((LPHBP) == DSI_LP_HBP_ENABLE))
AnnaBridge	172:65be27845400	1211	#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) \|\| ((LPVActive) == DSI_LP_VACT_ENABLE))
AnnaBridge	172:65be27845400	1212	#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) \|\| ((LPVFP) == DSI_LP_VFP_ENABLE))
AnnaBridge	172:65be27845400	1213	#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) \|\| ((LPVBP) == DSI_LP_VBP_ENABLE))
AnnaBridge	172:65be27845400	1214	#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) \|\| ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
AnnaBridge	172:65be27845400	1215	#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) \|\| ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
AnnaBridge	172:65be27845400	1216	#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) \|\| ((TESource) == DSI_TE_EXTERNAL))
AnnaBridge	172:65be27845400	1217	#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) \|\| ((TEPolarity) == DSI_TE_FALLING_EDGE))
AnnaBridge	172:65be27845400	1218	#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) \|\| ((AutomaticRefresh) == DSI_AR_ENABLE))
AnnaBridge	172:65be27845400	1219	#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) \|\| ((VSPolarity) == DSI_VSYNC_RISING))
AnnaBridge	172:65be27845400	1220	#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) \|\| ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
AnnaBridge	172:65be27845400	1221	#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) \|\| ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
AnnaBridge	172:65be27845400	1222	#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) \|\| ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
AnnaBridge	172:65be27845400	1223	#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) \|\| ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
AnnaBridge	172:65be27845400	1224	#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) \|\| ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
AnnaBridge	172:65be27845400	1225	#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) \|\| ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
AnnaBridge	172:65be27845400	1226	#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) \|\| ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
AnnaBridge	172:65be27845400	1227	#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) \|\| ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
AnnaBridge	172:65be27845400	1228	#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) \|\| ((LP_GLW) == DSI_LP_GLW_ENABLE))
AnnaBridge	172:65be27845400	1229	#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) \|\| ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
AnnaBridge	172:65be27845400	1230	#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) \|\| ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
AnnaBridge	172:65be27845400	1231	#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) \|\| ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
AnnaBridge	172:65be27845400	1232	#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) \|\| ((LP_DLW) == DSI_LP_DLW_ENABLE))
AnnaBridge	172:65be27845400	1233	#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) \|\| ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
AnnaBridge	172:65be27845400	1234	#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) \|\| \
AnnaBridge	172:65be27845400	1235	((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) \|\| \
AnnaBridge	172:65be27845400	1236	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) \|\| \
AnnaBridge	172:65be27845400	1237	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) \|\| \
AnnaBridge	172:65be27845400	1238	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
AnnaBridge	172:65be27845400	1239	#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) \|\| \
AnnaBridge	172:65be27845400	1240	((MODE) == DSI_GEN_LONG_PKT_WRITE))
AnnaBridge	172:65be27845400	1241	#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) \|\| \
AnnaBridge	172:65be27845400	1242	((MODE) == DSI_GEN_SHORT_PKT_READ_P0) \|\| \
AnnaBridge	172:65be27845400	1243	((MODE) == DSI_GEN_SHORT_PKT_READ_P1) \|\| \
AnnaBridge	172:65be27845400	1244	((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
AnnaBridge	172:65be27845400	1245	#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) \|\| ((CommDelay) == DSI_SLEW_RATE_LPTX) \|\| ((CommDelay) == DSI_HS_DELAY))
AnnaBridge	172:65be27845400	1246	#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANES))
AnnaBridge	172:65be27845400	1247	#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) \|\| ((CustomLane) == DSI_INVERT_HS_SIGNAL))
AnnaBridge	172:65be27845400	1248	#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANE0) \|\| ((Lane) == DSI_DATA_LANE1))
AnnaBridge	172:65be27845400	1249	#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) \|\| \
AnnaBridge	172:65be27845400	1250	((Timing) == DSI_TLPX_CLK ) \|\| \
AnnaBridge	172:65be27845400	1251	((Timing) == DSI_THS_EXIT ) \|\| \
AnnaBridge	172:65be27845400	1252	((Timing) == DSI_TLPX_DATA ) \|\| \
AnnaBridge	172:65be27845400	1253	((Timing) == DSI_THS_ZERO ) \|\| \
AnnaBridge	172:65be27845400	1254	((Timing) == DSI_THS_TRAIL ) \|\| \
AnnaBridge	172:65be27845400	1255	((Timing) == DSI_THS_PREPARE ) \|\| \
AnnaBridge	172:65be27845400	1256	((Timing) == DSI_TCLK_ZERO ) \|\| \
AnnaBridge	172:65be27845400	1257	((Timing) == DSI_TCLK_PREPARE))
AnnaBridge	172:65be27845400	1258
AnnaBridge	172:65be27845400	1259	/**
AnnaBridge	172:65be27845400	1260	* @}
AnnaBridge	172:65be27845400	1261	*/
AnnaBridge	172:65be27845400	1262
AnnaBridge	172:65be27845400	1263	/* Private functions prototypes ----------------------------------------------*/
AnnaBridge	172:65be27845400	1264	/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
AnnaBridge	172:65be27845400	1265	* @{
AnnaBridge	172:65be27845400	1266	*/
AnnaBridge	172:65be27845400	1267
AnnaBridge	172:65be27845400	1268	/**
AnnaBridge	172:65be27845400	1269	* @}
AnnaBridge	172:65be27845400	1270	*/
AnnaBridge	172:65be27845400	1271
AnnaBridge	172:65be27845400	1272	/* Private functions ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	1273	/** @defgroup DSI_Private_Functions DSI Private Functions
AnnaBridge	172:65be27845400	1274	* @{
AnnaBridge	172:65be27845400	1275	*/
AnnaBridge	172:65be27845400	1276
AnnaBridge	172:65be27845400	1277	/**
AnnaBridge	172:65be27845400	1278	* @}
AnnaBridge	172:65be27845400	1279	*/
AnnaBridge	172:65be27845400	1280
AnnaBridge	172:65be27845400	1281	/**
AnnaBridge	172:65be27845400	1282	* @}
AnnaBridge	172:65be27845400	1283	*/
AnnaBridge	172:65be27845400	1284
AnnaBridge	172:65be27845400	1285	/**
AnnaBridge	172:65be27845400	1286	* @}
AnnaBridge	172:65be27845400	1287	*/
AnnaBridge	172:65be27845400	1288	#endif /* DSI */
AnnaBridge	172:65be27845400	1289
AnnaBridge	172:65be27845400	1290	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1291	}
AnnaBridge	172:65be27845400	1292	#endif
AnnaBridge	172:65be27845400	1293
AnnaBridge	172:65be27845400	1294	#endif /* __STM32L4xx_HAL_DSI_H */
AnnaBridge	172:65be27845400	1295
AnnaBridge	172:65be27845400	1296	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/