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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_IAR/stm32l4r5xx.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32l4r5xx.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief CMSIS STM32L4R5xx Device Peripheral Access Layer Header File. |
| AnnaBridge | 172:65be27845400 | 6 | * |
| AnnaBridge | 172:65be27845400 | 7 | * This file contains: |
| AnnaBridge | 172:65be27845400 | 8 | * - Data structures and the address mapping for all peripherals |
| AnnaBridge | 172:65be27845400 | 9 | * - Peripheral's registers declarations and bits definition |
| AnnaBridge | 172:65be27845400 | 10 | * - Macros to access peripherals registers hardware |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 13 | * @attention |
| AnnaBridge | 172:65be27845400 | 14 | * |
| AnnaBridge | 172:65be27845400 | 15 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 172:65be27845400 | 16 | * |
| AnnaBridge | 172:65be27845400 | 17 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 172:65be27845400 | 18 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 172:65be27845400 | 19 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 172:65be27845400 | 20 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 172:65be27845400 | 21 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 172:65be27845400 | 22 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 172:65be27845400 | 23 | * and/or other materials provided with the distribution. |
| AnnaBridge | 172:65be27845400 | 24 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 172:65be27845400 | 25 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 172:65be27845400 | 26 | * without specific prior written permission. |
| AnnaBridge | 172:65be27845400 | 27 | * |
| AnnaBridge | 172:65be27845400 | 28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 172:65be27845400 | 29 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 172:65be27845400 | 30 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 172:65be27845400 | 31 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 172:65be27845400 | 32 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 172:65be27845400 | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 172:65be27845400 | 34 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 172:65be27845400 | 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 172:65be27845400 | 36 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 172:65be27845400 | 37 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 172:65be27845400 | 38 | * |
| AnnaBridge | 172:65be27845400 | 39 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 40 | */ |
| AnnaBridge | 172:65be27845400 | 41 | |
| AnnaBridge | 172:65be27845400 | 42 | /** @addtogroup CMSIS_Device |
| AnnaBridge | 172:65be27845400 | 43 | * @{ |
| AnnaBridge | 172:65be27845400 | 44 | */ |
| AnnaBridge | 172:65be27845400 | 45 | |
| AnnaBridge | 172:65be27845400 | 46 | /** @addtogroup stm32l4r5xx |
| AnnaBridge | 172:65be27845400 | 47 | * @{ |
| AnnaBridge | 172:65be27845400 | 48 | */ |
| AnnaBridge | 172:65be27845400 | 49 | |
| AnnaBridge | 172:65be27845400 | 50 | #ifndef __STM32L4R5xx_H |
| AnnaBridge | 172:65be27845400 | 51 | #define __STM32L4R5xx_H |
| AnnaBridge | 172:65be27845400 | 52 | |
| AnnaBridge | 172:65be27845400 | 53 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 54 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 55 | #endif /* __cplusplus */ |
| AnnaBridge | 172:65be27845400 | 56 | |
| AnnaBridge | 172:65be27845400 | 57 | /** @addtogroup Configuration_section_for_CMSIS |
| AnnaBridge | 172:65be27845400 | 58 | * @{ |
| AnnaBridge | 172:65be27845400 | 59 | */ |
| AnnaBridge | 172:65be27845400 | 60 | |
| AnnaBridge | 172:65be27845400 | 61 | /** |
| AnnaBridge | 172:65be27845400 | 62 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| AnnaBridge | 172:65be27845400 | 63 | */ |
| AnnaBridge | 172:65be27845400 | 64 | #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ |
| AnnaBridge | 172:65be27845400 | 65 | #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ |
| AnnaBridge | 172:65be27845400 | 66 | #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ |
| AnnaBridge | 172:65be27845400 | 67 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| AnnaBridge | 172:65be27845400 | 68 | #define __FPU_PRESENT 1 /*!< FPU present */ |
| AnnaBridge | 172:65be27845400 | 69 | |
| AnnaBridge | 172:65be27845400 | 70 | /** |
| AnnaBridge | 172:65be27845400 | 71 | * @} |
| AnnaBridge | 172:65be27845400 | 72 | */ |
| AnnaBridge | 172:65be27845400 | 73 | |
| AnnaBridge | 172:65be27845400 | 74 | /** @addtogroup Peripheral_interrupt_number_definition |
| AnnaBridge | 172:65be27845400 | 75 | * @{ |
| AnnaBridge | 172:65be27845400 | 76 | */ |
| AnnaBridge | 172:65be27845400 | 77 | |
| AnnaBridge | 172:65be27845400 | 78 | /** |
| AnnaBridge | 172:65be27845400 | 79 | * @brief STM32L4XX Interrupt Number Definition, according to the selected device |
| AnnaBridge | 172:65be27845400 | 80 | * in @ref Library_configuration_section |
| AnnaBridge | 172:65be27845400 | 81 | */ |
| AnnaBridge | 172:65be27845400 | 82 | typedef enum |
| AnnaBridge | 172:65be27845400 | 83 | { |
| AnnaBridge | 172:65be27845400 | 84 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| AnnaBridge | 172:65be27845400 | 85 | NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ |
| AnnaBridge | 172:65be27845400 | 86 | HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ |
| AnnaBridge | 172:65be27845400 | 87 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| AnnaBridge | 172:65be27845400 | 88 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| AnnaBridge | 172:65be27845400 | 89 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| AnnaBridge | 172:65be27845400 | 90 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| AnnaBridge | 172:65be27845400 | 91 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| AnnaBridge | 172:65be27845400 | 92 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| AnnaBridge | 172:65be27845400 | 93 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| AnnaBridge | 172:65be27845400 | 94 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| AnnaBridge | 172:65be27845400 | 95 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| AnnaBridge | 172:65be27845400 | 96 | PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ |
| AnnaBridge | 172:65be27845400 | 97 | TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| AnnaBridge | 172:65be27845400 | 98 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| AnnaBridge | 172:65be27845400 | 99 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 100 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 101 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 102 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 103 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 104 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 105 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 106 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 107 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 108 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 109 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 110 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 111 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 112 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 113 | ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 114 | CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ |
| AnnaBridge | 172:65be27845400 | 115 | CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 116 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| AnnaBridge | 172:65be27845400 | 117 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| AnnaBridge | 172:65be27845400 | 118 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| AnnaBridge | 172:65be27845400 | 119 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 120 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 121 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 122 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| AnnaBridge | 172:65be27845400 | 123 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 124 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 125 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 126 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| AnnaBridge | 172:65be27845400 | 127 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| AnnaBridge | 172:65be27845400 | 128 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| AnnaBridge | 172:65be27845400 | 129 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| AnnaBridge | 172:65be27845400 | 130 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 131 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 132 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 133 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 134 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 135 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| AnnaBridge | 172:65be27845400 | 136 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| AnnaBridge | 172:65be27845400 | 137 | DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 138 | TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
| AnnaBridge | 172:65be27845400 | 139 | TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
| AnnaBridge | 172:65be27845400 | 140 | TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
| AnnaBridge | 172:65be27845400 | 141 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| AnnaBridge | 172:65be27845400 | 142 | FMC_IRQn = 48, /*!< FMC global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 143 | SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 144 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 145 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 146 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 147 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 148 | TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| AnnaBridge | 172:65be27845400 | 149 | TIM7_IRQn = 55, /*!< TIM7 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 150 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 151 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 152 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 153 | DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 154 | DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 155 | DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 156 | DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 157 | DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 158 | COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ |
| AnnaBridge | 172:65be27845400 | 159 | LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ |
| AnnaBridge | 172:65be27845400 | 160 | LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ |
| AnnaBridge | 172:65be27845400 | 161 | OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| AnnaBridge | 172:65be27845400 | 162 | DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 163 | DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 164 | LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ |
| AnnaBridge | 172:65be27845400 | 165 | OCTOSPI1_IRQn = 71, /*!< OctoSPI1 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 166 | I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| AnnaBridge | 172:65be27845400 | 167 | I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| AnnaBridge | 172:65be27845400 | 168 | SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 169 | SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 170 | OCTOSPI2_IRQn = 76, /*!< OctoSPI2 global interrupt */ |
| AnnaBridge | 172:65be27845400 | 171 | TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ |
| AnnaBridge | 172:65be27845400 | 172 | RNG_IRQn = 80, /*!< RNG global interrupt */ |
| AnnaBridge | 172:65be27845400 | 173 | FPU_IRQn = 81, /*!< FPU global interrupt */ |
| AnnaBridge | 172:65be27845400 | 174 | CRS_IRQn = 82, /*!< CRS global interrupt */ |
| AnnaBridge | 172:65be27845400 | 175 | I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */ |
| AnnaBridge | 172:65be27845400 | 176 | I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */ |
| AnnaBridge | 172:65be27845400 | 177 | DCMI_IRQn = 85, /*!< DCMI global interrupt */ |
| AnnaBridge | 172:65be27845400 | 178 | DMA2D_IRQn = 90, /*!< DMA2D global interrupt */ |
| AnnaBridge | 172:65be27845400 | 179 | DMAMUX1_OVR_IRQn = 94 /*!< DMAMUX1 overrun global interrupt */ |
| AnnaBridge | 172:65be27845400 | 180 | } IRQn_Type; |
| AnnaBridge | 172:65be27845400 | 181 | |
| AnnaBridge | 172:65be27845400 | 182 | /** |
| AnnaBridge | 172:65be27845400 | 183 | * @} |
| AnnaBridge | 172:65be27845400 | 184 | */ |
| AnnaBridge | 172:65be27845400 | 185 | |
| AnnaBridge | 172:65be27845400 | 186 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| AnnaBridge | 172:65be27845400 | 187 | #include "system_stm32l4xx.h" |
| AnnaBridge | 172:65be27845400 | 188 | #include <stdint.h> |
| AnnaBridge | 172:65be27845400 | 189 | |
| AnnaBridge | 172:65be27845400 | 190 | /** @addtogroup Peripheral_registers_structures |
| AnnaBridge | 172:65be27845400 | 191 | * @{ |
| AnnaBridge | 172:65be27845400 | 192 | */ |
| AnnaBridge | 172:65be27845400 | 193 | |
| AnnaBridge | 172:65be27845400 | 194 | /** |
| AnnaBridge | 172:65be27845400 | 195 | * @brief Analog to Digital Converter |
| AnnaBridge | 172:65be27845400 | 196 | */ |
| AnnaBridge | 172:65be27845400 | 197 | |
| AnnaBridge | 172:65be27845400 | 198 | typedef struct |
| AnnaBridge | 172:65be27845400 | 199 | { |
| AnnaBridge | 172:65be27845400 | 200 | __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 201 | __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 202 | __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 203 | __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 204 | __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 205 | __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 206 | __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 207 | uint32_t RESERVED1; /*!< Reserved, 0x1C */ |
| AnnaBridge | 172:65be27845400 | 208 | __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 209 | __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 210 | __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 211 | uint32_t RESERVED2; /*!< Reserved, 0x2C */ |
| AnnaBridge | 172:65be27845400 | 212 | __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 213 | __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 214 | __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 215 | __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 216 | __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 217 | uint32_t RESERVED3; /*!< Reserved, 0x44 */ |
| AnnaBridge | 172:65be27845400 | 218 | uint32_t RESERVED4; /*!< Reserved, 0x48 */ |
| AnnaBridge | 172:65be27845400 | 219 | __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 220 | uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ |
| AnnaBridge | 172:65be27845400 | 221 | __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ |
| AnnaBridge | 172:65be27845400 | 222 | __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ |
| AnnaBridge | 172:65be27845400 | 223 | __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ |
| AnnaBridge | 172:65be27845400 | 224 | __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ |
| AnnaBridge | 172:65be27845400 | 225 | uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ |
| AnnaBridge | 172:65be27845400 | 226 | __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ |
| AnnaBridge | 172:65be27845400 | 227 | __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ |
| AnnaBridge | 172:65be27845400 | 228 | __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ |
| AnnaBridge | 172:65be27845400 | 229 | __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ |
| AnnaBridge | 172:65be27845400 | 230 | uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ |
| AnnaBridge | 172:65be27845400 | 231 | __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ |
| AnnaBridge | 172:65be27845400 | 232 | __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ |
| AnnaBridge | 172:65be27845400 | 233 | uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ |
| AnnaBridge | 172:65be27845400 | 234 | uint32_t RESERVED9; /*!< Reserved, 0x0AC */ |
| AnnaBridge | 172:65be27845400 | 235 | __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ |
| AnnaBridge | 172:65be27845400 | 236 | __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ |
| AnnaBridge | 172:65be27845400 | 237 | |
| AnnaBridge | 172:65be27845400 | 238 | } ADC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 239 | |
| AnnaBridge | 172:65be27845400 | 240 | typedef struct |
| AnnaBridge | 172:65be27845400 | 241 | { |
| AnnaBridge | 172:65be27845400 | 242 | uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ |
| AnnaBridge | 172:65be27845400 | 243 | uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ |
| AnnaBridge | 172:65be27845400 | 244 | __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ |
| AnnaBridge | 172:65be27845400 | 245 | uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ |
| AnnaBridge | 172:65be27845400 | 246 | } ADC_Common_TypeDef; |
| AnnaBridge | 172:65be27845400 | 247 | |
| AnnaBridge | 172:65be27845400 | 248 | /** |
| AnnaBridge | 172:65be27845400 | 249 | * @brief DCMI |
| AnnaBridge | 172:65be27845400 | 250 | */ |
| AnnaBridge | 172:65be27845400 | 251 | |
| AnnaBridge | 172:65be27845400 | 252 | typedef struct |
| AnnaBridge | 172:65be27845400 | 253 | { |
| AnnaBridge | 172:65be27845400 | 254 | __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 255 | __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 256 | __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 257 | __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 258 | __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 259 | __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 260 | __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 261 | __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 262 | __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 263 | __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 264 | __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 265 | } DCMI_TypeDef; |
| AnnaBridge | 172:65be27845400 | 266 | |
| AnnaBridge | 172:65be27845400 | 267 | /** |
| AnnaBridge | 172:65be27845400 | 268 | * @brief Controller Area Network TxMailBox |
| AnnaBridge | 172:65be27845400 | 269 | */ |
| AnnaBridge | 172:65be27845400 | 270 | |
| AnnaBridge | 172:65be27845400 | 271 | typedef struct |
| AnnaBridge | 172:65be27845400 | 272 | { |
| AnnaBridge | 172:65be27845400 | 273 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| AnnaBridge | 172:65be27845400 | 274 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| AnnaBridge | 172:65be27845400 | 275 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| AnnaBridge | 172:65be27845400 | 276 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| AnnaBridge | 172:65be27845400 | 277 | } CAN_TxMailBox_TypeDef; |
| AnnaBridge | 172:65be27845400 | 278 | |
| AnnaBridge | 172:65be27845400 | 279 | /** |
| AnnaBridge | 172:65be27845400 | 280 | * @brief Controller Area Network FIFOMailBox |
| AnnaBridge | 172:65be27845400 | 281 | */ |
| AnnaBridge | 172:65be27845400 | 282 | |
| AnnaBridge | 172:65be27845400 | 283 | typedef struct |
| AnnaBridge | 172:65be27845400 | 284 | { |
| AnnaBridge | 172:65be27845400 | 285 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| AnnaBridge | 172:65be27845400 | 286 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| AnnaBridge | 172:65be27845400 | 287 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| AnnaBridge | 172:65be27845400 | 288 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| AnnaBridge | 172:65be27845400 | 289 | } CAN_FIFOMailBox_TypeDef; |
| AnnaBridge | 172:65be27845400 | 290 | |
| AnnaBridge | 172:65be27845400 | 291 | /** |
| AnnaBridge | 172:65be27845400 | 292 | * @brief Controller Area Network FilterRegister |
| AnnaBridge | 172:65be27845400 | 293 | */ |
| AnnaBridge | 172:65be27845400 | 294 | |
| AnnaBridge | 172:65be27845400 | 295 | typedef struct |
| AnnaBridge | 172:65be27845400 | 296 | { |
| AnnaBridge | 172:65be27845400 | 297 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| AnnaBridge | 172:65be27845400 | 298 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| AnnaBridge | 172:65be27845400 | 299 | } CAN_FilterRegister_TypeDef; |
| AnnaBridge | 172:65be27845400 | 300 | |
| AnnaBridge | 172:65be27845400 | 301 | /** |
| AnnaBridge | 172:65be27845400 | 302 | * @brief Controller Area Network |
| AnnaBridge | 172:65be27845400 | 303 | */ |
| AnnaBridge | 172:65be27845400 | 304 | |
| AnnaBridge | 172:65be27845400 | 305 | typedef struct |
| AnnaBridge | 172:65be27845400 | 306 | { |
| AnnaBridge | 172:65be27845400 | 307 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 308 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 309 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 310 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 311 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 312 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 313 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 314 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 315 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| AnnaBridge | 172:65be27845400 | 316 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| AnnaBridge | 172:65be27845400 | 317 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| AnnaBridge | 172:65be27845400 | 318 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| AnnaBridge | 172:65be27845400 | 319 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| AnnaBridge | 172:65be27845400 | 320 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| AnnaBridge | 172:65be27845400 | 321 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| AnnaBridge | 172:65be27845400 | 322 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| AnnaBridge | 172:65be27845400 | 323 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| AnnaBridge | 172:65be27845400 | 324 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| AnnaBridge | 172:65be27845400 | 325 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| AnnaBridge | 172:65be27845400 | 326 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| AnnaBridge | 172:65be27845400 | 327 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| AnnaBridge | 172:65be27845400 | 328 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| AnnaBridge | 172:65be27845400 | 329 | } CAN_TypeDef; |
| AnnaBridge | 172:65be27845400 | 330 | |
| AnnaBridge | 172:65be27845400 | 331 | |
| AnnaBridge | 172:65be27845400 | 332 | /** |
| AnnaBridge | 172:65be27845400 | 333 | * @brief Comparator |
| AnnaBridge | 172:65be27845400 | 334 | */ |
| AnnaBridge | 172:65be27845400 | 335 | |
| AnnaBridge | 172:65be27845400 | 336 | typedef struct |
| AnnaBridge | 172:65be27845400 | 337 | { |
| AnnaBridge | 172:65be27845400 | 338 | __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 339 | } COMP_TypeDef; |
| AnnaBridge | 172:65be27845400 | 340 | |
| AnnaBridge | 172:65be27845400 | 341 | typedef struct |
| AnnaBridge | 172:65be27845400 | 342 | { |
| AnnaBridge | 172:65be27845400 | 343 | __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 344 | } COMP_Common_TypeDef; |
| AnnaBridge | 172:65be27845400 | 345 | |
| AnnaBridge | 172:65be27845400 | 346 | /** |
| AnnaBridge | 172:65be27845400 | 347 | * @brief CRC calculation unit |
| AnnaBridge | 172:65be27845400 | 348 | */ |
| AnnaBridge | 172:65be27845400 | 349 | |
| AnnaBridge | 172:65be27845400 | 350 | typedef struct |
| AnnaBridge | 172:65be27845400 | 351 | { |
| AnnaBridge | 172:65be27845400 | 352 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 353 | __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 354 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 355 | uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| AnnaBridge | 172:65be27845400 | 356 | __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 357 | __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 358 | } CRC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 359 | |
| AnnaBridge | 172:65be27845400 | 360 | /** |
| AnnaBridge | 172:65be27845400 | 361 | * @brief Clock Recovery System |
| AnnaBridge | 172:65be27845400 | 362 | */ |
| AnnaBridge | 172:65be27845400 | 363 | typedef struct |
| AnnaBridge | 172:65be27845400 | 364 | { |
| AnnaBridge | 172:65be27845400 | 365 | __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 366 | __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 367 | __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 368 | __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 369 | } CRS_TypeDef; |
| AnnaBridge | 172:65be27845400 | 370 | |
| AnnaBridge | 172:65be27845400 | 371 | /** |
| AnnaBridge | 172:65be27845400 | 372 | * @brief Digital to Analog Converter |
| AnnaBridge | 172:65be27845400 | 373 | */ |
| AnnaBridge | 172:65be27845400 | 374 | |
| AnnaBridge | 172:65be27845400 | 375 | typedef struct |
| AnnaBridge | 172:65be27845400 | 376 | { |
| AnnaBridge | 172:65be27845400 | 377 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 378 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 379 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 380 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 381 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 382 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 383 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 384 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 385 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 386 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 387 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 388 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 389 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 390 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 391 | __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 392 | __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 393 | __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 394 | __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 395 | __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 396 | __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 397 | } DAC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 398 | |
| AnnaBridge | 172:65be27845400 | 399 | /** |
| AnnaBridge | 172:65be27845400 | 400 | * @brief DFSDM module registers |
| AnnaBridge | 172:65be27845400 | 401 | */ |
| AnnaBridge | 172:65be27845400 | 402 | typedef struct |
| AnnaBridge | 172:65be27845400 | 403 | { |
| AnnaBridge | 172:65be27845400 | 404 | __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ |
| AnnaBridge | 172:65be27845400 | 405 | __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ |
| AnnaBridge | 172:65be27845400 | 406 | __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ |
| AnnaBridge | 172:65be27845400 | 407 | __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ |
| AnnaBridge | 172:65be27845400 | 408 | __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ |
| AnnaBridge | 172:65be27845400 | 409 | __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ |
| AnnaBridge | 172:65be27845400 | 410 | __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ |
| AnnaBridge | 172:65be27845400 | 411 | __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ |
| AnnaBridge | 172:65be27845400 | 412 | __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ |
| AnnaBridge | 172:65be27845400 | 413 | __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ |
| AnnaBridge | 172:65be27845400 | 414 | __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ |
| AnnaBridge | 172:65be27845400 | 415 | __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ |
| AnnaBridge | 172:65be27845400 | 416 | __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ |
| AnnaBridge | 172:65be27845400 | 417 | __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ |
| AnnaBridge | 172:65be27845400 | 418 | __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ |
| AnnaBridge | 172:65be27845400 | 419 | } DFSDM_Filter_TypeDef; |
| AnnaBridge | 172:65be27845400 | 420 | |
| AnnaBridge | 172:65be27845400 | 421 | /** |
| AnnaBridge | 172:65be27845400 | 422 | * @brief DFSDM channel configuration registers |
| AnnaBridge | 172:65be27845400 | 423 | */ |
| AnnaBridge | 172:65be27845400 | 424 | typedef struct |
| AnnaBridge | 172:65be27845400 | 425 | { |
| AnnaBridge | 172:65be27845400 | 426 | __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 427 | __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 428 | __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and |
| AnnaBridge | 172:65be27845400 | 429 | short circuit detector register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 430 | __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 431 | __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 432 | __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 433 | } DFSDM_Channel_TypeDef; |
| AnnaBridge | 172:65be27845400 | 434 | |
| AnnaBridge | 172:65be27845400 | 435 | /** |
| AnnaBridge | 172:65be27845400 | 436 | * @brief Debug MCU |
| AnnaBridge | 172:65be27845400 | 437 | */ |
| AnnaBridge | 172:65be27845400 | 438 | |
| AnnaBridge | 172:65be27845400 | 439 | typedef struct |
| AnnaBridge | 172:65be27845400 | 440 | { |
| AnnaBridge | 172:65be27845400 | 441 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 442 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 443 | __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 444 | __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 445 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 446 | } DBGMCU_TypeDef; |
| AnnaBridge | 172:65be27845400 | 447 | |
| AnnaBridge | 172:65be27845400 | 448 | |
| AnnaBridge | 172:65be27845400 | 449 | /** |
| AnnaBridge | 172:65be27845400 | 450 | * @brief DMA Controller |
| AnnaBridge | 172:65be27845400 | 451 | */ |
| AnnaBridge | 172:65be27845400 | 452 | |
| AnnaBridge | 172:65be27845400 | 453 | typedef struct |
| AnnaBridge | 172:65be27845400 | 454 | { |
| AnnaBridge | 172:65be27845400 | 455 | __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| AnnaBridge | 172:65be27845400 | 456 | __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| AnnaBridge | 172:65be27845400 | 457 | __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| AnnaBridge | 172:65be27845400 | 458 | __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| AnnaBridge | 172:65be27845400 | 459 | } DMA_Channel_TypeDef; |
| AnnaBridge | 172:65be27845400 | 460 | |
| AnnaBridge | 172:65be27845400 | 461 | typedef struct |
| AnnaBridge | 172:65be27845400 | 462 | { |
| AnnaBridge | 172:65be27845400 | 463 | __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 464 | __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 465 | } DMA_TypeDef; |
| AnnaBridge | 172:65be27845400 | 466 | |
| AnnaBridge | 172:65be27845400 | 467 | /** |
| AnnaBridge | 172:65be27845400 | 468 | * @brief DMA Multiplexer |
| AnnaBridge | 172:65be27845400 | 469 | */ |
| AnnaBridge | 172:65be27845400 | 470 | |
| AnnaBridge | 172:65be27845400 | 471 | typedef struct |
| AnnaBridge | 172:65be27845400 | 472 | { |
| AnnaBridge | 172:65be27845400 | 473 | __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ |
| AnnaBridge | 172:65be27845400 | 474 | }DMAMUX_Channel_TypeDef; |
| AnnaBridge | 172:65be27845400 | 475 | |
| AnnaBridge | 172:65be27845400 | 476 | typedef struct |
| AnnaBridge | 172:65be27845400 | 477 | { |
| AnnaBridge | 172:65be27845400 | 478 | __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ |
| AnnaBridge | 172:65be27845400 | 479 | __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ |
| AnnaBridge | 172:65be27845400 | 480 | }DMAMUX_ChannelStatus_TypeDef; |
| AnnaBridge | 172:65be27845400 | 481 | |
| AnnaBridge | 172:65be27845400 | 482 | typedef struct |
| AnnaBridge | 172:65be27845400 | 483 | { |
| AnnaBridge | 172:65be27845400 | 484 | __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ |
| AnnaBridge | 172:65be27845400 | 485 | }DMAMUX_RequestGen_TypeDef; |
| AnnaBridge | 172:65be27845400 | 486 | |
| AnnaBridge | 172:65be27845400 | 487 | typedef struct |
| AnnaBridge | 172:65be27845400 | 488 | { |
| AnnaBridge | 172:65be27845400 | 489 | __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ |
| AnnaBridge | 172:65be27845400 | 490 | __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ |
| AnnaBridge | 172:65be27845400 | 491 | }DMAMUX_RequestGenStatus_TypeDef; |
| AnnaBridge | 172:65be27845400 | 492 | |
| AnnaBridge | 172:65be27845400 | 493 | |
| AnnaBridge | 172:65be27845400 | 494 | /** |
| AnnaBridge | 172:65be27845400 | 495 | * @brief DMA2D Controller |
| AnnaBridge | 172:65be27845400 | 496 | */ |
| AnnaBridge | 172:65be27845400 | 497 | |
| AnnaBridge | 172:65be27845400 | 498 | typedef struct |
| AnnaBridge | 172:65be27845400 | 499 | { |
| AnnaBridge | 172:65be27845400 | 500 | __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 501 | __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 502 | __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 503 | __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 504 | __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 505 | __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 506 | __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 507 | __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 508 | __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 509 | __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 510 | __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 511 | __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 512 | __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 513 | __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 514 | __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 515 | __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 516 | __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 517 | __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 518 | __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 519 | __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 520 | uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */ |
| AnnaBridge | 172:65be27845400 | 521 | __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */ |
| AnnaBridge | 172:65be27845400 | 522 | __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */ |
| AnnaBridge | 172:65be27845400 | 523 | } DMA2D_TypeDef; |
| AnnaBridge | 172:65be27845400 | 524 | |
| AnnaBridge | 172:65be27845400 | 525 | /** |
| AnnaBridge | 172:65be27845400 | 526 | * @brief External Interrupt/Event Controller |
| AnnaBridge | 172:65be27845400 | 527 | */ |
| AnnaBridge | 172:65be27845400 | 528 | |
| AnnaBridge | 172:65be27845400 | 529 | typedef struct |
| AnnaBridge | 172:65be27845400 | 530 | { |
| AnnaBridge | 172:65be27845400 | 531 | __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 532 | __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 533 | __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 534 | __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 535 | __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 536 | __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 537 | uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| AnnaBridge | 172:65be27845400 | 538 | uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| AnnaBridge | 172:65be27845400 | 539 | __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 540 | __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 541 | __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 542 | __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 543 | __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 544 | __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 545 | } EXTI_TypeDef; |
| AnnaBridge | 172:65be27845400 | 546 | |
| AnnaBridge | 172:65be27845400 | 547 | |
| AnnaBridge | 172:65be27845400 | 548 | /** |
| AnnaBridge | 172:65be27845400 | 549 | * @brief Firewall |
| AnnaBridge | 172:65be27845400 | 550 | */ |
| AnnaBridge | 172:65be27845400 | 551 | |
| AnnaBridge | 172:65be27845400 | 552 | typedef struct |
| AnnaBridge | 172:65be27845400 | 553 | { |
| AnnaBridge | 172:65be27845400 | 554 | __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 555 | __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 556 | __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 557 | __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 558 | __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 559 | __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 560 | uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 561 | uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 562 | __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 563 | } FIREWALL_TypeDef; |
| AnnaBridge | 172:65be27845400 | 564 | |
| AnnaBridge | 172:65be27845400 | 565 | |
| AnnaBridge | 172:65be27845400 | 566 | /** |
| AnnaBridge | 172:65be27845400 | 567 | * @brief FLASH Registers |
| AnnaBridge | 172:65be27845400 | 568 | */ |
| AnnaBridge | 172:65be27845400 | 569 | |
| AnnaBridge | 172:65be27845400 | 570 | typedef struct |
| AnnaBridge | 172:65be27845400 | 571 | { |
| AnnaBridge | 172:65be27845400 | 572 | __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 573 | __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 574 | __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 575 | __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 576 | __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 577 | __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 578 | __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 579 | __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 580 | __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 581 | __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 582 | __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 583 | __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 584 | __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 585 | uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34-0x40 */ |
| AnnaBridge | 172:65be27845400 | 586 | __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 587 | __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 588 | __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 589 | __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ |
| AnnaBridge | 172:65be27845400 | 590 | uint32_t RESERVED3[55]; /*!< Reserved3, Address offset: 0x54-0x12C */ |
| AnnaBridge | 172:65be27845400 | 591 | __IO uint32_t CFGR; /*!< FLASH configuration register, Address offset: 0x130 */ |
| AnnaBridge | 172:65be27845400 | 592 | } FLASH_TypeDef; |
| AnnaBridge | 172:65be27845400 | 593 | |
| AnnaBridge | 172:65be27845400 | 594 | |
| AnnaBridge | 172:65be27845400 | 595 | /** |
| AnnaBridge | 172:65be27845400 | 596 | * @brief Flexible Memory Controller |
| AnnaBridge | 172:65be27845400 | 597 | */ |
| AnnaBridge | 172:65be27845400 | 598 | |
| AnnaBridge | 172:65be27845400 | 599 | typedef struct |
| AnnaBridge | 172:65be27845400 | 600 | { |
| AnnaBridge | 172:65be27845400 | 601 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| AnnaBridge | 172:65be27845400 | 602 | } FMC_Bank1_TypeDef; |
| AnnaBridge | 172:65be27845400 | 603 | |
| AnnaBridge | 172:65be27845400 | 604 | /** |
| AnnaBridge | 172:65be27845400 | 605 | * @brief Flexible Memory Controller Bank1E |
| AnnaBridge | 172:65be27845400 | 606 | */ |
| AnnaBridge | 172:65be27845400 | 607 | |
| AnnaBridge | 172:65be27845400 | 608 | typedef struct |
| AnnaBridge | 172:65be27845400 | 609 | { |
| AnnaBridge | 172:65be27845400 | 610 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| AnnaBridge | 172:65be27845400 | 611 | } FMC_Bank1E_TypeDef; |
| AnnaBridge | 172:65be27845400 | 612 | |
| AnnaBridge | 172:65be27845400 | 613 | /** |
| AnnaBridge | 172:65be27845400 | 614 | * @brief Flexible Memory Controller Bank3 |
| AnnaBridge | 172:65be27845400 | 615 | */ |
| AnnaBridge | 172:65be27845400 | 616 | |
| AnnaBridge | 172:65be27845400 | 617 | typedef struct |
| AnnaBridge | 172:65be27845400 | 618 | { |
| AnnaBridge | 172:65be27845400 | 619 | __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ |
| AnnaBridge | 172:65be27845400 | 620 | __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ |
| AnnaBridge | 172:65be27845400 | 621 | __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ |
| AnnaBridge | 172:65be27845400 | 622 | __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ |
| AnnaBridge | 172:65be27845400 | 623 | uint32_t RESERVED0; /*!< Reserved, 0x90 */ |
| AnnaBridge | 172:65be27845400 | 624 | __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ |
| AnnaBridge | 172:65be27845400 | 625 | } FMC_Bank3_TypeDef; |
| AnnaBridge | 172:65be27845400 | 626 | |
| AnnaBridge | 172:65be27845400 | 627 | /** |
| AnnaBridge | 172:65be27845400 | 628 | * @brief General Purpose I/O |
| AnnaBridge | 172:65be27845400 | 629 | */ |
| AnnaBridge | 172:65be27845400 | 630 | |
| AnnaBridge | 172:65be27845400 | 631 | typedef struct |
| AnnaBridge | 172:65be27845400 | 632 | { |
| AnnaBridge | 172:65be27845400 | 633 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 634 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 635 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 636 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 637 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 638 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 639 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 640 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 641 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| AnnaBridge | 172:65be27845400 | 642 | __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 643 | |
| AnnaBridge | 172:65be27845400 | 644 | } GPIO_TypeDef; |
| AnnaBridge | 172:65be27845400 | 645 | |
| AnnaBridge | 172:65be27845400 | 646 | |
| AnnaBridge | 172:65be27845400 | 647 | /** |
| AnnaBridge | 172:65be27845400 | 648 | * @brief Inter-integrated Circuit Interface |
| AnnaBridge | 172:65be27845400 | 649 | */ |
| AnnaBridge | 172:65be27845400 | 650 | |
| AnnaBridge | 172:65be27845400 | 651 | typedef struct |
| AnnaBridge | 172:65be27845400 | 652 | { |
| AnnaBridge | 172:65be27845400 | 653 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 654 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 655 | __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 656 | __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 657 | __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 658 | __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 659 | __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 660 | __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 661 | __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 662 | __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 663 | __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 664 | } I2C_TypeDef; |
| AnnaBridge | 172:65be27845400 | 665 | |
| AnnaBridge | 172:65be27845400 | 666 | /** |
| AnnaBridge | 172:65be27845400 | 667 | * @brief Independent WATCHDOG |
| AnnaBridge | 172:65be27845400 | 668 | */ |
| AnnaBridge | 172:65be27845400 | 669 | |
| AnnaBridge | 172:65be27845400 | 670 | typedef struct |
| AnnaBridge | 172:65be27845400 | 671 | { |
| AnnaBridge | 172:65be27845400 | 672 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 673 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 674 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 675 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 676 | __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 677 | } IWDG_TypeDef; |
| AnnaBridge | 172:65be27845400 | 678 | |
| AnnaBridge | 172:65be27845400 | 679 | /** |
| AnnaBridge | 172:65be27845400 | 680 | * @brief LPTIMER |
| AnnaBridge | 172:65be27845400 | 681 | */ |
| AnnaBridge | 172:65be27845400 | 682 | typedef struct |
| AnnaBridge | 172:65be27845400 | 683 | { |
| AnnaBridge | 172:65be27845400 | 684 | __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 685 | __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 686 | __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 687 | __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 688 | __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 689 | __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 690 | __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 691 | __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 692 | __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 693 | } LPTIM_TypeDef; |
| AnnaBridge | 172:65be27845400 | 694 | |
| AnnaBridge | 172:65be27845400 | 695 | /** |
| AnnaBridge | 172:65be27845400 | 696 | * @brief Operational Amplifier (OPAMP) |
| AnnaBridge | 172:65be27845400 | 697 | */ |
| AnnaBridge | 172:65be27845400 | 698 | |
| AnnaBridge | 172:65be27845400 | 699 | typedef struct |
| AnnaBridge | 172:65be27845400 | 700 | { |
| AnnaBridge | 172:65be27845400 | 701 | __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 702 | __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 703 | __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 704 | } OPAMP_TypeDef; |
| AnnaBridge | 172:65be27845400 | 705 | |
| AnnaBridge | 172:65be27845400 | 706 | typedef struct |
| AnnaBridge | 172:65be27845400 | 707 | { |
| AnnaBridge | 172:65be27845400 | 708 | __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 709 | } OPAMP_Common_TypeDef; |
| AnnaBridge | 172:65be27845400 | 710 | |
| AnnaBridge | 172:65be27845400 | 711 | /** |
| AnnaBridge | 172:65be27845400 | 712 | * @brief Power Control |
| AnnaBridge | 172:65be27845400 | 713 | */ |
| AnnaBridge | 172:65be27845400 | 714 | |
| AnnaBridge | 172:65be27845400 | 715 | typedef struct |
| AnnaBridge | 172:65be27845400 | 716 | { |
| AnnaBridge | 172:65be27845400 | 717 | __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 718 | __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 719 | __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 720 | __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 721 | __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 722 | __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 723 | __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 724 | uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 725 | __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 726 | __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 727 | __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 728 | __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 729 | __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 730 | __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 731 | __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 732 | __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 733 | __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 734 | __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 735 | __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 736 | __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 737 | __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ |
| AnnaBridge | 172:65be27845400 | 738 | __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ |
| AnnaBridge | 172:65be27845400 | 739 | __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ |
| AnnaBridge | 172:65be27845400 | 740 | __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ |
| AnnaBridge | 172:65be27845400 | 741 | __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */ |
| AnnaBridge | 172:65be27845400 | 742 | __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */ |
| AnnaBridge | 172:65be27845400 | 743 | uint32_t RESERVED1[6]; /*!< Reserved, Address offset: 0x68-0x7C */ |
| AnnaBridge | 172:65be27845400 | 744 | __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ |
| AnnaBridge | 172:65be27845400 | 745 | } PWR_TypeDef; |
| AnnaBridge | 172:65be27845400 | 746 | |
| AnnaBridge | 172:65be27845400 | 747 | |
| AnnaBridge | 172:65be27845400 | 748 | /** |
| AnnaBridge | 172:65be27845400 | 749 | * @brief OCTO Serial Peripheral Interface |
| AnnaBridge | 172:65be27845400 | 750 | */ |
| AnnaBridge | 172:65be27845400 | 751 | |
| AnnaBridge | 172:65be27845400 | 752 | typedef struct |
| AnnaBridge | 172:65be27845400 | 753 | { |
| AnnaBridge | 172:65be27845400 | 754 | __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ |
| AnnaBridge | 172:65be27845400 | 755 | uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ |
| AnnaBridge | 172:65be27845400 | 756 | __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ |
| AnnaBridge | 172:65be27845400 | 757 | __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ |
| AnnaBridge | 172:65be27845400 | 758 | __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ |
| AnnaBridge | 172:65be27845400 | 759 | uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x014-0x01C */ |
| AnnaBridge | 172:65be27845400 | 760 | __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ |
| AnnaBridge | 172:65be27845400 | 761 | __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ |
| AnnaBridge | 172:65be27845400 | 762 | uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ |
| AnnaBridge | 172:65be27845400 | 763 | __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ |
| AnnaBridge | 172:65be27845400 | 764 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ |
| AnnaBridge | 172:65be27845400 | 765 | __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ |
| AnnaBridge | 172:65be27845400 | 766 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ |
| AnnaBridge | 172:65be27845400 | 767 | __IO uint32_t DR; /*!< OCTOPSI Data register, Address offset: 0x050 */ |
| AnnaBridge | 172:65be27845400 | 768 | uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ |
| AnnaBridge | 172:65be27845400 | 769 | __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ |
| AnnaBridge | 172:65be27845400 | 770 | uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ |
| AnnaBridge | 172:65be27845400 | 771 | __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ |
| AnnaBridge | 172:65be27845400 | 772 | uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ |
| AnnaBridge | 172:65be27845400 | 773 | __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ |
| AnnaBridge | 172:65be27845400 | 774 | uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ |
| AnnaBridge | 172:65be27845400 | 775 | __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ |
| AnnaBridge | 172:65be27845400 | 776 | uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ |
| AnnaBridge | 172:65be27845400 | 777 | __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ |
| AnnaBridge | 172:65be27845400 | 778 | uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ |
| AnnaBridge | 172:65be27845400 | 779 | __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ |
| AnnaBridge | 172:65be27845400 | 780 | uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ |
| AnnaBridge | 172:65be27845400 | 781 | __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ |
| AnnaBridge | 172:65be27845400 | 782 | uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ |
| AnnaBridge | 172:65be27845400 | 783 | __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ |
| AnnaBridge | 172:65be27845400 | 784 | uint32_t RESERVED13[19]; /*!< Reserved, Address offset: 0x134-0x17C */ |
| AnnaBridge | 172:65be27845400 | 785 | __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ |
| AnnaBridge | 172:65be27845400 | 786 | uint32_t RESERVED14; /*!< Reserved, Address offset: 0x184 */ |
| AnnaBridge | 172:65be27845400 | 787 | __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ |
| AnnaBridge | 172:65be27845400 | 788 | uint32_t RESERVED15; /*!< Reserved, Address offset: 0x18C */ |
| AnnaBridge | 172:65be27845400 | 789 | __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ |
| AnnaBridge | 172:65be27845400 | 790 | uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x194-0x19C */ |
| AnnaBridge | 172:65be27845400 | 791 | __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ |
| AnnaBridge | 172:65be27845400 | 792 | uint32_t RESERVED17[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ |
| AnnaBridge | 172:65be27845400 | 793 | __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ |
| AnnaBridge | 172:65be27845400 | 794 | } OCTOSPI_TypeDef; |
| AnnaBridge | 172:65be27845400 | 795 | |
| AnnaBridge | 172:65be27845400 | 796 | /** |
| AnnaBridge | 172:65be27845400 | 797 | * @brief OCTO Serial Peripheral Interface IO Manager |
| AnnaBridge | 172:65be27845400 | 798 | */ |
| AnnaBridge | 172:65be27845400 | 799 | |
| AnnaBridge | 172:65be27845400 | 800 | typedef struct |
| AnnaBridge | 172:65be27845400 | 801 | { |
| AnnaBridge | 172:65be27845400 | 802 | uint32_t RESERVED; /*!< Reserved, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 803 | __IO uint32_t PCR[2]; /*!< OCTOSPI IO Manager Port[1:2] Configuration register, Address offset: 0x04-0x08 */ |
| AnnaBridge | 172:65be27845400 | 804 | } OCTOSPIM_TypeDef; |
| AnnaBridge | 172:65be27845400 | 805 | |
| AnnaBridge | 172:65be27845400 | 806 | /** |
| AnnaBridge | 172:65be27845400 | 807 | * @brief Reset and Clock Control |
| AnnaBridge | 172:65be27845400 | 808 | */ |
| AnnaBridge | 172:65be27845400 | 809 | |
| AnnaBridge | 172:65be27845400 | 810 | typedef struct |
| AnnaBridge | 172:65be27845400 | 811 | { |
| AnnaBridge | 172:65be27845400 | 812 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 813 | __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 814 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 815 | __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 816 | __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 817 | __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 818 | __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 819 | __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 820 | __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 821 | uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 822 | __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 823 | __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 824 | __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 825 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 826 | __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 827 | __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 828 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 829 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 830 | __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 831 | __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 832 | __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ |
| AnnaBridge | 172:65be27845400 | 833 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ |
| AnnaBridge | 172:65be27845400 | 834 | __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ |
| AnnaBridge | 172:65be27845400 | 835 | __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ |
| AnnaBridge | 172:65be27845400 | 836 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ |
| AnnaBridge | 172:65be27845400 | 837 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ |
| AnnaBridge | 172:65be27845400 | 838 | __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ |
| AnnaBridge | 172:65be27845400 | 839 | __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ |
| AnnaBridge | 172:65be27845400 | 840 | __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ |
| AnnaBridge | 172:65be27845400 | 841 | uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ |
| AnnaBridge | 172:65be27845400 | 842 | __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ |
| AnnaBridge | 172:65be27845400 | 843 | __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ |
| AnnaBridge | 172:65be27845400 | 844 | __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ |
| AnnaBridge | 172:65be27845400 | 845 | uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ |
| AnnaBridge | 172:65be27845400 | 846 | __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ |
| AnnaBridge | 172:65be27845400 | 847 | uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ |
| AnnaBridge | 172:65be27845400 | 848 | __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ |
| AnnaBridge | 172:65be27845400 | 849 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ |
| AnnaBridge | 172:65be27845400 | 850 | __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ |
| AnnaBridge | 172:65be27845400 | 851 | __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ |
| AnnaBridge | 172:65be27845400 | 852 | } RCC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 853 | |
| AnnaBridge | 172:65be27845400 | 854 | /** |
| AnnaBridge | 172:65be27845400 | 855 | * @brief Real-Time Clock |
| AnnaBridge | 172:65be27845400 | 856 | */ |
| AnnaBridge | 172:65be27845400 | 857 | |
| AnnaBridge | 172:65be27845400 | 858 | typedef struct |
| AnnaBridge | 172:65be27845400 | 859 | { |
| AnnaBridge | 172:65be27845400 | 860 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 861 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 862 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 863 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 864 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 865 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 866 | uint32_t reserved; /*!< Reserved */ |
| AnnaBridge | 172:65be27845400 | 867 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 868 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 869 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 870 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 871 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 872 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 873 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 874 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 875 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 876 | __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 877 | __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 878 | __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 879 | __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 880 | __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| AnnaBridge | 172:65be27845400 | 881 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| AnnaBridge | 172:65be27845400 | 882 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| AnnaBridge | 172:65be27845400 | 883 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| AnnaBridge | 172:65be27845400 | 884 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| AnnaBridge | 172:65be27845400 | 885 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| AnnaBridge | 172:65be27845400 | 886 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| AnnaBridge | 172:65be27845400 | 887 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| AnnaBridge | 172:65be27845400 | 888 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| AnnaBridge | 172:65be27845400 | 889 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| AnnaBridge | 172:65be27845400 | 890 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| AnnaBridge | 172:65be27845400 | 891 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| AnnaBridge | 172:65be27845400 | 892 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| AnnaBridge | 172:65be27845400 | 893 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| AnnaBridge | 172:65be27845400 | 894 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| AnnaBridge | 172:65be27845400 | 895 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| AnnaBridge | 172:65be27845400 | 896 | __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| AnnaBridge | 172:65be27845400 | 897 | __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| AnnaBridge | 172:65be27845400 | 898 | __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| AnnaBridge | 172:65be27845400 | 899 | __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| AnnaBridge | 172:65be27845400 | 900 | __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ |
| AnnaBridge | 172:65be27845400 | 901 | __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ |
| AnnaBridge | 172:65be27845400 | 902 | __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ |
| AnnaBridge | 172:65be27845400 | 903 | __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ |
| AnnaBridge | 172:65be27845400 | 904 | __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ |
| AnnaBridge | 172:65be27845400 | 905 | __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ |
| AnnaBridge | 172:65be27845400 | 906 | __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ |
| AnnaBridge | 172:65be27845400 | 907 | __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ |
| AnnaBridge | 172:65be27845400 | 908 | __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ |
| AnnaBridge | 172:65be27845400 | 909 | __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ |
| AnnaBridge | 172:65be27845400 | 910 | __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ |
| AnnaBridge | 172:65be27845400 | 911 | __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ |
| AnnaBridge | 172:65be27845400 | 912 | } RTC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 913 | |
| AnnaBridge | 172:65be27845400 | 914 | |
| AnnaBridge | 172:65be27845400 | 915 | /** |
| AnnaBridge | 172:65be27845400 | 916 | * @brief Serial Audio Interface |
| AnnaBridge | 172:65be27845400 | 917 | */ |
| AnnaBridge | 172:65be27845400 | 918 | |
| AnnaBridge | 172:65be27845400 | 919 | typedef struct |
| AnnaBridge | 172:65be27845400 | 920 | { |
| AnnaBridge | 172:65be27845400 | 921 | __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 922 | uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ |
| AnnaBridge | 172:65be27845400 | 923 | __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 924 | __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 925 | } SAI_TypeDef; |
| AnnaBridge | 172:65be27845400 | 926 | |
| AnnaBridge | 172:65be27845400 | 927 | typedef struct |
| AnnaBridge | 172:65be27845400 | 928 | { |
| AnnaBridge | 172:65be27845400 | 929 | __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 930 | __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 931 | __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 932 | __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 933 | __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 934 | __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 935 | __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 936 | __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 937 | } SAI_Block_TypeDef; |
| AnnaBridge | 172:65be27845400 | 938 | |
| AnnaBridge | 172:65be27845400 | 939 | |
| AnnaBridge | 172:65be27845400 | 940 | /** |
| AnnaBridge | 172:65be27845400 | 941 | * @brief Secure digital input/output Interface |
| AnnaBridge | 172:65be27845400 | 942 | */ |
| AnnaBridge | 172:65be27845400 | 943 | |
| AnnaBridge | 172:65be27845400 | 944 | typedef struct |
| AnnaBridge | 172:65be27845400 | 945 | { |
| AnnaBridge | 172:65be27845400 | 946 | __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 947 | __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 948 | __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 949 | __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 950 | __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 951 | __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 952 | __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 953 | __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 954 | __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 955 | __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 956 | __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 957 | __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 958 | __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 959 | __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 960 | __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 961 | __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 962 | __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 963 | uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ |
| AnnaBridge | 172:65be27845400 | 964 | __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ |
| AnnaBridge | 172:65be27845400 | 965 | __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ |
| AnnaBridge | 172:65be27845400 | 966 | __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ |
| AnnaBridge | 172:65be27845400 | 967 | __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ |
| AnnaBridge | 172:65be27845400 | 968 | uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ |
| AnnaBridge | 172:65be27845400 | 969 | __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ |
| AnnaBridge | 172:65be27845400 | 970 | } SDMMC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 971 | /** |
| AnnaBridge | 172:65be27845400 | 972 | * @brief Serial Peripheral Interface |
| AnnaBridge | 172:65be27845400 | 973 | */ |
| AnnaBridge | 172:65be27845400 | 974 | |
| AnnaBridge | 172:65be27845400 | 975 | typedef struct |
| AnnaBridge | 172:65be27845400 | 976 | { |
| AnnaBridge | 172:65be27845400 | 977 | __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 978 | __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 979 | __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 980 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 981 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 982 | __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 983 | __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 984 | } SPI_TypeDef; |
| AnnaBridge | 172:65be27845400 | 985 | |
| AnnaBridge | 172:65be27845400 | 986 | |
| AnnaBridge | 172:65be27845400 | 987 | /** |
| AnnaBridge | 172:65be27845400 | 988 | * @brief System configuration controller |
| AnnaBridge | 172:65be27845400 | 989 | */ |
| AnnaBridge | 172:65be27845400 | 990 | |
| AnnaBridge | 172:65be27845400 | 991 | typedef struct |
| AnnaBridge | 172:65be27845400 | 992 | { |
| AnnaBridge | 172:65be27845400 | 993 | __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 994 | __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 995 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| AnnaBridge | 172:65be27845400 | 996 | __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 997 | __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 998 | __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 999 | __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 1000 | __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 1001 | } SYSCFG_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1002 | |
| AnnaBridge | 172:65be27845400 | 1003 | |
| AnnaBridge | 172:65be27845400 | 1004 | /** |
| AnnaBridge | 172:65be27845400 | 1005 | * @brief TIM |
| AnnaBridge | 172:65be27845400 | 1006 | */ |
| AnnaBridge | 172:65be27845400 | 1007 | |
| AnnaBridge | 172:65be27845400 | 1008 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1009 | { |
| AnnaBridge | 172:65be27845400 | 1010 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 1011 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 1012 | __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 1013 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 1014 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 1015 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 1016 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 1017 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 1018 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 1019 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 1020 | __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 1021 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 1022 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 1023 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| AnnaBridge | 172:65be27845400 | 1024 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| AnnaBridge | 172:65be27845400 | 1025 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| AnnaBridge | 172:65be27845400 | 1026 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| AnnaBridge | 172:65be27845400 | 1027 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| AnnaBridge | 172:65be27845400 | 1028 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| AnnaBridge | 172:65be27845400 | 1029 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| AnnaBridge | 172:65be27845400 | 1030 | __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ |
| AnnaBridge | 172:65be27845400 | 1031 | __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ |
| AnnaBridge | 172:65be27845400 | 1032 | __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ |
| AnnaBridge | 172:65be27845400 | 1033 | __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ |
| AnnaBridge | 172:65be27845400 | 1034 | __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ |
| AnnaBridge | 172:65be27845400 | 1035 | __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ |
| AnnaBridge | 172:65be27845400 | 1036 | } TIM_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1037 | |
| AnnaBridge | 172:65be27845400 | 1038 | |
| AnnaBridge | 172:65be27845400 | 1039 | /** |
| AnnaBridge | 172:65be27845400 | 1040 | * @brief Touch Sensing Controller (TSC) |
| AnnaBridge | 172:65be27845400 | 1041 | */ |
| AnnaBridge | 172:65be27845400 | 1042 | |
| AnnaBridge | 172:65be27845400 | 1043 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1044 | { |
| AnnaBridge | 172:65be27845400 | 1045 | __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 1046 | __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 1047 | __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 1048 | __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 1049 | __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 1050 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 1051 | __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 1052 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 1053 | __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 1054 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 1055 | __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 1056 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 1057 | __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ |
| AnnaBridge | 172:65be27845400 | 1058 | __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ |
| AnnaBridge | 172:65be27845400 | 1059 | } TSC_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1060 | |
| AnnaBridge | 172:65be27845400 | 1061 | /** |
| AnnaBridge | 172:65be27845400 | 1062 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| AnnaBridge | 172:65be27845400 | 1063 | */ |
| AnnaBridge | 172:65be27845400 | 1064 | |
| AnnaBridge | 172:65be27845400 | 1065 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1066 | { |
| AnnaBridge | 172:65be27845400 | 1067 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 1068 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 1069 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 1070 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| AnnaBridge | 172:65be27845400 | 1071 | __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| AnnaBridge | 172:65be27845400 | 1072 | uint16_t RESERVED2; /*!< Reserved, 0x12 */ |
| AnnaBridge | 172:65be27845400 | 1073 | __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| AnnaBridge | 172:65be27845400 | 1074 | __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| AnnaBridge | 172:65be27845400 | 1075 | uint16_t RESERVED3; /*!< Reserved, 0x1A */ |
| AnnaBridge | 172:65be27845400 | 1076 | __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| AnnaBridge | 172:65be27845400 | 1077 | __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| AnnaBridge | 172:65be27845400 | 1078 | __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| AnnaBridge | 172:65be27845400 | 1079 | uint16_t RESERVED4; /*!< Reserved, 0x26 */ |
| AnnaBridge | 172:65be27845400 | 1080 | __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| AnnaBridge | 172:65be27845400 | 1081 | uint16_t RESERVED5; /*!< Reserved, 0x2A */ |
| AnnaBridge | 172:65be27845400 | 1082 | __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ |
| AnnaBridge | 172:65be27845400 | 1083 | } USART_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1084 | |
| AnnaBridge | 172:65be27845400 | 1085 | /** |
| AnnaBridge | 172:65be27845400 | 1086 | * @brief VREFBUF |
| AnnaBridge | 172:65be27845400 | 1087 | */ |
| AnnaBridge | 172:65be27845400 | 1088 | |
| AnnaBridge | 172:65be27845400 | 1089 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1090 | { |
| AnnaBridge | 172:65be27845400 | 1091 | __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 1092 | __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 1093 | } VREFBUF_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1094 | |
| AnnaBridge | 172:65be27845400 | 1095 | /** |
| AnnaBridge | 172:65be27845400 | 1096 | * @brief Window WATCHDOG |
| AnnaBridge | 172:65be27845400 | 1097 | */ |
| AnnaBridge | 172:65be27845400 | 1098 | |
| AnnaBridge | 172:65be27845400 | 1099 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1100 | { |
| AnnaBridge | 172:65be27845400 | 1101 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 1102 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 1103 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 1104 | } WWDG_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1105 | |
| AnnaBridge | 172:65be27845400 | 1106 | /** |
| AnnaBridge | 172:65be27845400 | 1107 | * @brief RNG |
| AnnaBridge | 172:65be27845400 | 1108 | */ |
| AnnaBridge | 172:65be27845400 | 1109 | |
| AnnaBridge | 172:65be27845400 | 1110 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1111 | { |
| AnnaBridge | 172:65be27845400 | 1112 | __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ |
| AnnaBridge | 172:65be27845400 | 1113 | __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ |
| AnnaBridge | 172:65be27845400 | 1114 | __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ |
| AnnaBridge | 172:65be27845400 | 1115 | } RNG_TypeDef; |
| AnnaBridge | 172:65be27845400 | 1116 | |
| AnnaBridge | 172:65be27845400 | 1117 | /** |
| AnnaBridge | 172:65be27845400 | 1118 | * @brief USB_OTG_Core_register |
| AnnaBridge | 172:65be27845400 | 1119 | */ |
| AnnaBridge | 172:65be27845400 | 1120 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1121 | { |
| AnnaBridge | 172:65be27845400 | 1122 | __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ |
| AnnaBridge | 172:65be27845400 | 1123 | __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ |
| AnnaBridge | 172:65be27845400 | 1124 | __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ |
| AnnaBridge | 172:65be27845400 | 1125 | __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ |
| AnnaBridge | 172:65be27845400 | 1126 | __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ |
| AnnaBridge | 172:65be27845400 | 1127 | __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ |
| AnnaBridge | 172:65be27845400 | 1128 | __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ |
| AnnaBridge | 172:65be27845400 | 1129 | __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ |
| AnnaBridge | 172:65be27845400 | 1130 | __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ |
| AnnaBridge | 172:65be27845400 | 1131 | __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ |
| AnnaBridge | 172:65be27845400 | 1132 | __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ |
| AnnaBridge | 172:65be27845400 | 1133 | __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ |
| AnnaBridge | 172:65be27845400 | 1134 | uint32_t Reserved30[2]; /* Reserved 030h*/ |
| AnnaBridge | 172:65be27845400 | 1135 | __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ |
| AnnaBridge | 172:65be27845400 | 1136 | __IO uint32_t CID; /* User ID Register 03Ch*/ |
| AnnaBridge | 172:65be27845400 | 1137 | __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ |
| AnnaBridge | 172:65be27845400 | 1138 | __IO uint32_t GHWCFG1; /* User HW config1 044h*/ |
| AnnaBridge | 172:65be27845400 | 1139 | __IO uint32_t GHWCFG2; /* User HW config2 048h*/ |
| AnnaBridge | 172:65be27845400 | 1140 | __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ |
| AnnaBridge | 172:65be27845400 | 1141 | uint32_t Reserved6; /* Reserved 050h*/ |
| AnnaBridge | 172:65be27845400 | 1142 | __IO uint32_t GLPMCFG; /* LPM Register 054h*/ |
| AnnaBridge | 172:65be27845400 | 1143 | __IO uint32_t GPWRDN; /* Power Down Register 058h*/ |
| AnnaBridge | 172:65be27845400 | 1144 | __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ |
| AnnaBridge | 172:65be27845400 | 1145 | __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ |
| AnnaBridge | 172:65be27845400 | 1146 | uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ |
| AnnaBridge | 172:65be27845400 | 1147 | __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ |
| AnnaBridge | 172:65be27845400 | 1148 | __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ |
| AnnaBridge | 172:65be27845400 | 1149 | } USB_OTG_GlobalTypeDef; |
| AnnaBridge | 172:65be27845400 | 1150 | |
| AnnaBridge | 172:65be27845400 | 1151 | /** |
| AnnaBridge | 172:65be27845400 | 1152 | * @brief USB_OTG_device_Registers |
| AnnaBridge | 172:65be27845400 | 1153 | */ |
| AnnaBridge | 172:65be27845400 | 1154 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1155 | { |
| AnnaBridge | 172:65be27845400 | 1156 | __IO uint32_t DCFG; /* dev Configuration Register 800h*/ |
| AnnaBridge | 172:65be27845400 | 1157 | __IO uint32_t DCTL; /* dev Control Register 804h*/ |
| AnnaBridge | 172:65be27845400 | 1158 | __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ |
| AnnaBridge | 172:65be27845400 | 1159 | uint32_t Reserved0C; /* Reserved 80Ch*/ |
| AnnaBridge | 172:65be27845400 | 1160 | __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ |
| AnnaBridge | 172:65be27845400 | 1161 | __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ |
| AnnaBridge | 172:65be27845400 | 1162 | __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ |
| AnnaBridge | 172:65be27845400 | 1163 | __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ |
| AnnaBridge | 172:65be27845400 | 1164 | uint32_t Reserved20; /* Reserved 820h*/ |
| AnnaBridge | 172:65be27845400 | 1165 | uint32_t Reserved9; /* Reserved 824h*/ |
| AnnaBridge | 172:65be27845400 | 1166 | __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ |
| AnnaBridge | 172:65be27845400 | 1167 | __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ |
| AnnaBridge | 172:65be27845400 | 1168 | __IO uint32_t DTHRCTL; /* dev thr 830h*/ |
| AnnaBridge | 172:65be27845400 | 1169 | __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ |
| AnnaBridge | 172:65be27845400 | 1170 | __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ |
| AnnaBridge | 172:65be27845400 | 1171 | __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ |
| AnnaBridge | 172:65be27845400 | 1172 | uint32_t Reserved40; /* dedicated EP mask 840h*/ |
| AnnaBridge | 172:65be27845400 | 1173 | __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ |
| AnnaBridge | 172:65be27845400 | 1174 | uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ |
| AnnaBridge | 172:65be27845400 | 1175 | __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ |
| AnnaBridge | 172:65be27845400 | 1176 | } USB_OTG_DeviceTypeDef; |
| AnnaBridge | 172:65be27845400 | 1177 | |
| AnnaBridge | 172:65be27845400 | 1178 | /** |
| AnnaBridge | 172:65be27845400 | 1179 | * @brief USB_OTG_IN_Endpoint-Specific_Register |
| AnnaBridge | 172:65be27845400 | 1180 | */ |
| AnnaBridge | 172:65be27845400 | 1181 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1182 | { |
| AnnaBridge | 172:65be27845400 | 1183 | __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ |
| AnnaBridge | 172:65be27845400 | 1184 | uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ |
| AnnaBridge | 172:65be27845400 | 1185 | __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ |
| AnnaBridge | 172:65be27845400 | 1186 | uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ |
| AnnaBridge | 172:65be27845400 | 1187 | __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ |
| AnnaBridge | 172:65be27845400 | 1188 | __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ |
| AnnaBridge | 172:65be27845400 | 1189 | __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ |
| AnnaBridge | 172:65be27845400 | 1190 | uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ |
| AnnaBridge | 172:65be27845400 | 1191 | } USB_OTG_INEndpointTypeDef; |
| AnnaBridge | 172:65be27845400 | 1192 | |
| AnnaBridge | 172:65be27845400 | 1193 | /** |
| AnnaBridge | 172:65be27845400 | 1194 | * @brief USB_OTG_OUT_Endpoint-Specific_Registers |
| AnnaBridge | 172:65be27845400 | 1195 | */ |
| AnnaBridge | 172:65be27845400 | 1196 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1197 | { |
| AnnaBridge | 172:65be27845400 | 1198 | __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ |
| AnnaBridge | 172:65be27845400 | 1199 | uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ |
| AnnaBridge | 172:65be27845400 | 1200 | __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ |
| AnnaBridge | 172:65be27845400 | 1201 | uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ |
| AnnaBridge | 172:65be27845400 | 1202 | __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ |
| AnnaBridge | 172:65be27845400 | 1203 | __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ |
| AnnaBridge | 172:65be27845400 | 1204 | uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ |
| AnnaBridge | 172:65be27845400 | 1205 | } USB_OTG_OUTEndpointTypeDef; |
| AnnaBridge | 172:65be27845400 | 1206 | |
| AnnaBridge | 172:65be27845400 | 1207 | /** |
| AnnaBridge | 172:65be27845400 | 1208 | * @brief USB_OTG_Host_Mode_Register_Structures |
| AnnaBridge | 172:65be27845400 | 1209 | */ |
| AnnaBridge | 172:65be27845400 | 1210 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1211 | { |
| AnnaBridge | 172:65be27845400 | 1212 | __IO uint32_t HCFG; /* Host Configuration Register 400h*/ |
| AnnaBridge | 172:65be27845400 | 1213 | __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ |
| AnnaBridge | 172:65be27845400 | 1214 | __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ |
| AnnaBridge | 172:65be27845400 | 1215 | uint32_t Reserved40C; /* Reserved 40Ch*/ |
| AnnaBridge | 172:65be27845400 | 1216 | __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ |
| AnnaBridge | 172:65be27845400 | 1217 | __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ |
| AnnaBridge | 172:65be27845400 | 1218 | __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ |
| AnnaBridge | 172:65be27845400 | 1219 | } USB_OTG_HostTypeDef; |
| AnnaBridge | 172:65be27845400 | 1220 | |
| AnnaBridge | 172:65be27845400 | 1221 | /** |
| AnnaBridge | 172:65be27845400 | 1222 | * @brief USB_OTG_Host_Channel_Specific_Registers |
| AnnaBridge | 172:65be27845400 | 1223 | */ |
| AnnaBridge | 172:65be27845400 | 1224 | typedef struct |
| AnnaBridge | 172:65be27845400 | 1225 | { |
| AnnaBridge | 172:65be27845400 | 1226 | __IO uint32_t HCCHAR; |
| AnnaBridge | 172:65be27845400 | 1227 | __IO uint32_t HCSPLT; |
| AnnaBridge | 172:65be27845400 | 1228 | __IO uint32_t HCINT; |
| AnnaBridge | 172:65be27845400 | 1229 | __IO uint32_t HCINTMSK; |
| AnnaBridge | 172:65be27845400 | 1230 | __IO uint32_t HCTSIZ; |
| AnnaBridge | 172:65be27845400 | 1231 | __IO uint32_t HCDMA; |
| AnnaBridge | 172:65be27845400 | 1232 | uint32_t Reserved[2]; |
| AnnaBridge | 172:65be27845400 | 1233 | } USB_OTG_HostChannelTypeDef; |
| AnnaBridge | 172:65be27845400 | 1234 | |
| AnnaBridge | 172:65be27845400 | 1235 | /** |
| AnnaBridge | 172:65be27845400 | 1236 | * @} |
| AnnaBridge | 172:65be27845400 | 1237 | */ |
| AnnaBridge | 172:65be27845400 | 1238 | |
| AnnaBridge | 172:65be27845400 | 1239 | /** @addtogroup Peripheral_memory_map |
| AnnaBridge | 172:65be27845400 | 1240 | * @{ |
| AnnaBridge | 172:65be27845400 | 1241 | */ |
| AnnaBridge | 172:65be27845400 | 1242 | #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 2 MB) base address */ |
| AnnaBridge | 172:65be27845400 | 1243 | #define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 192 KB) base address */ |
| AnnaBridge | 172:65be27845400 | 1244 | #define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */ |
| AnnaBridge | 172:65be27845400 | 1245 | #define SRAM3_BASE ((uint32_t)0x20040000U) /*!< SRAM3(384 KB) base address */ |
| AnnaBridge | 172:65be27845400 | 1246 | #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ |
| AnnaBridge | 172:65be27845400 | 1247 | #define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ |
| AnnaBridge | 172:65be27845400 | 1248 | #define OCTOSPI1_BASE ((uint32_t)0x90000000U) /*!< OCTOSPI1 memories accessible over AHB base address */ |
| AnnaBridge | 172:65be27845400 | 1249 | #define OCTOSPI2_BASE ((uint32_t)0x70000000U) /*!< OCTOSPI2 memories accessible over AHB base address */ |
| AnnaBridge | 172:65be27845400 | 1250 | |
| AnnaBridge | 172:65be27845400 | 1251 | #define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ |
| AnnaBridge | 172:65be27845400 | 1252 | #define OCTOSPI1_R_BASE ((uint32_t)0xA0001000U) /*!< OCTOSPI1 control registers base address */ |
| AnnaBridge | 172:65be27845400 | 1253 | #define OCTOSPI2_R_BASE ((uint32_t)0xA0001400U) /*!< OCTOSPI2 control registers base address */ |
| AnnaBridge | 172:65be27845400 | 1254 | #define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ |
| AnnaBridge | 172:65be27845400 | 1255 | #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ |
| AnnaBridge | 172:65be27845400 | 1256 | |
| AnnaBridge | 172:65be27845400 | 1257 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 1258 | #define SRAM_BASE SRAM1_BASE |
| AnnaBridge | 172:65be27845400 | 1259 | #define SRAM_BB_BASE SRAM1_BB_BASE |
| AnnaBridge | 172:65be27845400 | 1260 | |
| AnnaBridge | 172:65be27845400 | 1261 | #define SRAM1_SIZE_MAX ((uint32_t)0x00030000U) /*!< maximum SRAM1 size (up to 192 KBytes) */ |
| AnnaBridge | 172:65be27845400 | 1262 | #define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */ |
| AnnaBridge | 172:65be27845400 | 1263 | #define SRAM3_SIZE ((uint32_t)0x00060000U) /*!< SRAM3 size (384 KBytes) */ |
| AnnaBridge | 172:65be27845400 | 1264 | |
| AnnaBridge | 172:65be27845400 | 1265 | /*!< Peripheral memory map */ |
| AnnaBridge | 172:65be27845400 | 1266 | #define APB1PERIPH_BASE PERIPH_BASE |
| AnnaBridge | 172:65be27845400 | 1267 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) |
| AnnaBridge | 172:65be27845400 | 1268 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) |
| AnnaBridge | 172:65be27845400 | 1269 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) |
| AnnaBridge | 172:65be27845400 | 1270 | |
| AnnaBridge | 172:65be27845400 | 1271 | #define FMC_BANK1 FMC_BASE |
| AnnaBridge | 172:65be27845400 | 1272 | #define FMC_BANK1_1 FMC_BANK1 |
| AnnaBridge | 172:65be27845400 | 1273 | #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) |
| AnnaBridge | 172:65be27845400 | 1274 | #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) |
| AnnaBridge | 172:65be27845400 | 1275 | #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) |
| AnnaBridge | 172:65be27845400 | 1276 | #define FMC_BANK3 (FMC_BASE + 0x20000000U) |
| AnnaBridge | 172:65be27845400 | 1277 | |
| AnnaBridge | 172:65be27845400 | 1278 | /*!< APB1 peripherals */ |
| AnnaBridge | 172:65be27845400 | 1279 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) |
| AnnaBridge | 172:65be27845400 | 1280 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) |
| AnnaBridge | 172:65be27845400 | 1281 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) |
| AnnaBridge | 172:65be27845400 | 1282 | #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) |
| AnnaBridge | 172:65be27845400 | 1283 | #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) |
| AnnaBridge | 172:65be27845400 | 1284 | #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) |
| AnnaBridge | 172:65be27845400 | 1285 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800U) |
| AnnaBridge | 172:65be27845400 | 1286 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) |
| AnnaBridge | 172:65be27845400 | 1287 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) |
| AnnaBridge | 172:65be27845400 | 1288 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) |
| AnnaBridge | 172:65be27845400 | 1289 | #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) |
| AnnaBridge | 172:65be27845400 | 1290 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400U) |
| AnnaBridge | 172:65be27845400 | 1291 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800U) |
| AnnaBridge | 172:65be27845400 | 1292 | #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) |
| AnnaBridge | 172:65be27845400 | 1293 | #define UART5_BASE (APB1PERIPH_BASE + 0x5000U) |
| AnnaBridge | 172:65be27845400 | 1294 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) |
| AnnaBridge | 172:65be27845400 | 1295 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) |
| AnnaBridge | 172:65be27845400 | 1296 | #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) |
| AnnaBridge | 172:65be27845400 | 1297 | #define CRS_BASE (APB1PERIPH_BASE + 0x6000U) |
| AnnaBridge | 172:65be27845400 | 1298 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) |
| AnnaBridge | 172:65be27845400 | 1299 | #define I2C4_BASE (APB1PERIPH_BASE + 0x8400U) |
| AnnaBridge | 172:65be27845400 | 1300 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000U) |
| AnnaBridge | 172:65be27845400 | 1301 | #define DAC_BASE (APB1PERIPH_BASE + 0x7400U) |
| AnnaBridge | 172:65be27845400 | 1302 | #define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) |
| AnnaBridge | 172:65be27845400 | 1303 | #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) |
| AnnaBridge | 172:65be27845400 | 1304 | #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) |
| AnnaBridge | 172:65be27845400 | 1305 | #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) |
| AnnaBridge | 172:65be27845400 | 1306 | #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) |
| AnnaBridge | 172:65be27845400 | 1307 | #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) |
| AnnaBridge | 172:65be27845400 | 1308 | #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) |
| AnnaBridge | 172:65be27845400 | 1309 | |
| AnnaBridge | 172:65be27845400 | 1310 | |
| AnnaBridge | 172:65be27845400 | 1311 | /*!< APB2 peripherals */ |
| AnnaBridge | 172:65be27845400 | 1312 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) |
| AnnaBridge | 172:65be27845400 | 1313 | #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) |
| AnnaBridge | 172:65be27845400 | 1314 | #define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) |
| AnnaBridge | 172:65be27845400 | 1315 | #define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) |
| AnnaBridge | 172:65be27845400 | 1316 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) |
| AnnaBridge | 172:65be27845400 | 1317 | #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) |
| AnnaBridge | 172:65be27845400 | 1318 | #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) |
| AnnaBridge | 172:65be27845400 | 1319 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) |
| AnnaBridge | 172:65be27845400 | 1320 | #define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) |
| AnnaBridge | 172:65be27845400 | 1321 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800U) |
| AnnaBridge | 172:65be27845400 | 1322 | #define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) |
| AnnaBridge | 172:65be27845400 | 1323 | #define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) |
| AnnaBridge | 172:65be27845400 | 1324 | #define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) |
| AnnaBridge | 172:65be27845400 | 1325 | #define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) |
| AnnaBridge | 172:65be27845400 | 1326 | #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) |
| AnnaBridge | 172:65be27845400 | 1327 | #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) |
| AnnaBridge | 172:65be27845400 | 1328 | #define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) |
| AnnaBridge | 172:65be27845400 | 1329 | #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) |
| AnnaBridge | 172:65be27845400 | 1330 | #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) |
| AnnaBridge | 172:65be27845400 | 1331 | #define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) |
| AnnaBridge | 172:65be27845400 | 1332 | #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) |
| AnnaBridge | 172:65be27845400 | 1333 | #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) |
| AnnaBridge | 172:65be27845400 | 1334 | #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) |
| AnnaBridge | 172:65be27845400 | 1335 | #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) |
| AnnaBridge | 172:65be27845400 | 1336 | #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) |
| AnnaBridge | 172:65be27845400 | 1337 | #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) |
| AnnaBridge | 172:65be27845400 | 1338 | #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) |
| AnnaBridge | 172:65be27845400 | 1339 | #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) |
| AnnaBridge | 172:65be27845400 | 1340 | #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) |
| AnnaBridge | 172:65be27845400 | 1341 | #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) |
| AnnaBridge | 172:65be27845400 | 1342 | #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) |
| AnnaBridge | 172:65be27845400 | 1343 | #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) |
| AnnaBridge | 172:65be27845400 | 1344 | |
| AnnaBridge | 172:65be27845400 | 1345 | /*!< AHB1 peripherals */ |
| AnnaBridge | 172:65be27845400 | 1346 | #define DMA1_BASE (AHB1PERIPH_BASE) |
| AnnaBridge | 172:65be27845400 | 1347 | #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) |
| AnnaBridge | 172:65be27845400 | 1348 | #define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800U) |
| AnnaBridge | 172:65be27845400 | 1349 | #define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) |
| AnnaBridge | 172:65be27845400 | 1350 | #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) |
| AnnaBridge | 172:65be27845400 | 1351 | #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) |
| AnnaBridge | 172:65be27845400 | 1352 | #define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) |
| AnnaBridge | 172:65be27845400 | 1353 | #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) |
| AnnaBridge | 172:65be27845400 | 1354 | |
| AnnaBridge | 172:65be27845400 | 1355 | |
| AnnaBridge | 172:65be27845400 | 1356 | #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) |
| AnnaBridge | 172:65be27845400 | 1357 | #define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) |
| AnnaBridge | 172:65be27845400 | 1358 | #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) |
| AnnaBridge | 172:65be27845400 | 1359 | #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) |
| AnnaBridge | 172:65be27845400 | 1360 | #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) |
| AnnaBridge | 172:65be27845400 | 1361 | #define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) |
| AnnaBridge | 172:65be27845400 | 1362 | #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) |
| AnnaBridge | 172:65be27845400 | 1363 | |
| AnnaBridge | 172:65be27845400 | 1364 | |
| AnnaBridge | 172:65be27845400 | 1365 | #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) |
| AnnaBridge | 172:65be27845400 | 1366 | #define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) |
| AnnaBridge | 172:65be27845400 | 1367 | #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) |
| AnnaBridge | 172:65be27845400 | 1368 | #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) |
| AnnaBridge | 172:65be27845400 | 1369 | #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) |
| AnnaBridge | 172:65be27845400 | 1370 | #define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) |
| AnnaBridge | 172:65be27845400 | 1371 | #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) |
| AnnaBridge | 172:65be27845400 | 1372 | |
| AnnaBridge | 172:65be27845400 | 1373 | #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) |
| AnnaBridge | 172:65be27845400 | 1374 | #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004) |
| AnnaBridge | 172:65be27845400 | 1375 | #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008) |
| AnnaBridge | 172:65be27845400 | 1376 | #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000C) |
| AnnaBridge | 172:65be27845400 | 1377 | #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010) |
| AnnaBridge | 172:65be27845400 | 1378 | #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014) |
| AnnaBridge | 172:65be27845400 | 1379 | #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018) |
| AnnaBridge | 172:65be27845400 | 1380 | #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0000001C) |
| AnnaBridge | 172:65be27845400 | 1381 | #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x00000020) |
| AnnaBridge | 172:65be27845400 | 1382 | #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x00000024) |
| AnnaBridge | 172:65be27845400 | 1383 | #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x00000028) |
| AnnaBridge | 172:65be27845400 | 1384 | #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0000002C) |
| AnnaBridge | 172:65be27845400 | 1385 | #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x00000030) |
| AnnaBridge | 172:65be27845400 | 1386 | #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x00000034) |
| AnnaBridge | 172:65be27845400 | 1387 | |
| AnnaBridge | 172:65be27845400 | 1388 | #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100) |
| AnnaBridge | 172:65be27845400 | 1389 | #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104) |
| AnnaBridge | 172:65be27845400 | 1390 | #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108) |
| AnnaBridge | 172:65be27845400 | 1391 | #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010C) |
| AnnaBridge | 172:65be27845400 | 1392 | |
| AnnaBridge | 172:65be27845400 | 1393 | #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080) |
| AnnaBridge | 172:65be27845400 | 1394 | #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140) |
| AnnaBridge | 172:65be27845400 | 1395 | |
| AnnaBridge | 172:65be27845400 | 1396 | /*!< AHB2 peripherals */ |
| AnnaBridge | 172:65be27845400 | 1397 | #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) |
| AnnaBridge | 172:65be27845400 | 1398 | #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) |
| AnnaBridge | 172:65be27845400 | 1399 | #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) |
| AnnaBridge | 172:65be27845400 | 1400 | #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) |
| AnnaBridge | 172:65be27845400 | 1401 | #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) |
| AnnaBridge | 172:65be27845400 | 1402 | #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) |
| AnnaBridge | 172:65be27845400 | 1403 | #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) |
| AnnaBridge | 172:65be27845400 | 1404 | #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) |
| AnnaBridge | 172:65be27845400 | 1405 | #define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U) |
| AnnaBridge | 172:65be27845400 | 1406 | |
| AnnaBridge | 172:65be27845400 | 1407 | #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) |
| AnnaBridge | 172:65be27845400 | 1408 | |
| AnnaBridge | 172:65be27845400 | 1409 | #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) |
| AnnaBridge | 172:65be27845400 | 1410 | #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) |
| AnnaBridge | 172:65be27845400 | 1411 | |
| AnnaBridge | 172:65be27845400 | 1412 | #define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U) |
| AnnaBridge | 172:65be27845400 | 1413 | |
| AnnaBridge | 172:65be27845400 | 1414 | #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) |
| AnnaBridge | 172:65be27845400 | 1415 | |
| AnnaBridge | 172:65be27845400 | 1416 | #define OCTOSPIM_BASE (AHB2PERIPH_BASE + 0x08061C00U) |
| AnnaBridge | 172:65be27845400 | 1417 | #define SDMMC1_BASE (AHB2PERIPH_BASE + 0x08062400U) |
| AnnaBridge | 172:65be27845400 | 1418 | |
| AnnaBridge | 172:65be27845400 | 1419 | /*!< FMC Banks registers base address */ |
| AnnaBridge | 172:65be27845400 | 1420 | #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) |
| AnnaBridge | 172:65be27845400 | 1421 | #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) |
| AnnaBridge | 172:65be27845400 | 1422 | #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) |
| AnnaBridge | 172:65be27845400 | 1423 | |
| AnnaBridge | 172:65be27845400 | 1424 | /* Debug MCU registers base address */ |
| AnnaBridge | 172:65be27845400 | 1425 | #define DBGMCU_BASE ((uint32_t)0xE0042000U) |
| AnnaBridge | 172:65be27845400 | 1426 | |
| AnnaBridge | 172:65be27845400 | 1427 | /*!< USB registers base address */ |
| AnnaBridge | 172:65be27845400 | 1428 | #define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) |
| AnnaBridge | 172:65be27845400 | 1429 | |
| AnnaBridge | 172:65be27845400 | 1430 | #define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 1431 | #define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) |
| AnnaBridge | 172:65be27845400 | 1432 | #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) |
| AnnaBridge | 172:65be27845400 | 1433 | #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) |
| AnnaBridge | 172:65be27845400 | 1434 | #define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) |
| AnnaBridge | 172:65be27845400 | 1435 | #define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) |
| AnnaBridge | 172:65be27845400 | 1436 | #define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) |
| AnnaBridge | 172:65be27845400 | 1437 | #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) |
| AnnaBridge | 172:65be27845400 | 1438 | #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) |
| AnnaBridge | 172:65be27845400 | 1439 | #define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) |
| AnnaBridge | 172:65be27845400 | 1440 | #define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) |
| AnnaBridge | 172:65be27845400 | 1441 | #define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) |
| AnnaBridge | 172:65be27845400 | 1442 | |
| AnnaBridge | 172:65be27845400 | 1443 | |
| AnnaBridge | 172:65be27845400 | 1444 | #define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ |
| AnnaBridge | 172:65be27845400 | 1445 | #define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ |
| AnnaBridge | 172:65be27845400 | 1446 | #define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ |
| AnnaBridge | 172:65be27845400 | 1447 | /** |
| AnnaBridge | 172:65be27845400 | 1448 | * @} |
| AnnaBridge | 172:65be27845400 | 1449 | */ |
| AnnaBridge | 172:65be27845400 | 1450 | |
| AnnaBridge | 172:65be27845400 | 1451 | /** @addtogroup Peripheral_declaration |
| AnnaBridge | 172:65be27845400 | 1452 | * @{ |
| AnnaBridge | 172:65be27845400 | 1453 | */ |
| AnnaBridge | 172:65be27845400 | 1454 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| AnnaBridge | 172:65be27845400 | 1455 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| AnnaBridge | 172:65be27845400 | 1456 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| AnnaBridge | 172:65be27845400 | 1457 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| AnnaBridge | 172:65be27845400 | 1458 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| AnnaBridge | 172:65be27845400 | 1459 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| AnnaBridge | 172:65be27845400 | 1460 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
| AnnaBridge | 172:65be27845400 | 1461 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| AnnaBridge | 172:65be27845400 | 1462 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| AnnaBridge | 172:65be27845400 | 1463 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| AnnaBridge | 172:65be27845400 | 1464 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| AnnaBridge | 172:65be27845400 | 1465 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
| AnnaBridge | 172:65be27845400 | 1466 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
| AnnaBridge | 172:65be27845400 | 1467 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
| AnnaBridge | 172:65be27845400 | 1468 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
| AnnaBridge | 172:65be27845400 | 1469 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| AnnaBridge | 172:65be27845400 | 1470 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| AnnaBridge | 172:65be27845400 | 1471 | #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| AnnaBridge | 172:65be27845400 | 1472 | #define CRS ((CRS_TypeDef *) CRS_BASE) |
| AnnaBridge | 172:65be27845400 | 1473 | //#define CAN ((CAN_TypeDef *) CAN1_BASE) // MBED FIX : already defined in mbed API |
| AnnaBridge | 172:65be27845400 | 1474 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| AnnaBridge | 172:65be27845400 | 1475 | #define I2C4 ((I2C_TypeDef *) I2C4_BASE) |
| AnnaBridge | 172:65be27845400 | 1476 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
| AnnaBridge | 172:65be27845400 | 1477 | #define DAC ((DAC_TypeDef *) DAC1_BASE) |
| AnnaBridge | 172:65be27845400 | 1478 | #define DAC1 ((DAC_TypeDef *) DAC1_BASE) |
| AnnaBridge | 172:65be27845400 | 1479 | #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
| AnnaBridge | 172:65be27845400 | 1480 | #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) |
| AnnaBridge | 172:65be27845400 | 1481 | #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) |
| AnnaBridge | 172:65be27845400 | 1482 | #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) |
| AnnaBridge | 172:65be27845400 | 1483 | #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
| AnnaBridge | 172:65be27845400 | 1484 | #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) |
| AnnaBridge | 172:65be27845400 | 1485 | #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) |
| AnnaBridge | 172:65be27845400 | 1486 | |
| AnnaBridge | 172:65be27845400 | 1487 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| AnnaBridge | 172:65be27845400 | 1488 | #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) |
| AnnaBridge | 172:65be27845400 | 1489 | #define COMP1 ((COMP_TypeDef *) COMP1_BASE) |
| AnnaBridge | 172:65be27845400 | 1490 | #define COMP2 ((COMP_TypeDef *) COMP2_BASE) |
| AnnaBridge | 172:65be27845400 | 1491 | #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) |
| AnnaBridge | 172:65be27845400 | 1492 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| AnnaBridge | 172:65be27845400 | 1493 | #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) |
| AnnaBridge | 172:65be27845400 | 1494 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| AnnaBridge | 172:65be27845400 | 1495 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| AnnaBridge | 172:65be27845400 | 1496 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| AnnaBridge | 172:65be27845400 | 1497 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
| AnnaBridge | 172:65be27845400 | 1498 | #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
| AnnaBridge | 172:65be27845400 | 1499 | #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| AnnaBridge | 172:65be27845400 | 1500 | #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| AnnaBridge | 172:65be27845400 | 1501 | #define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
| AnnaBridge | 172:65be27845400 | 1502 | #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
| AnnaBridge | 172:65be27845400 | 1503 | #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
| AnnaBridge | 172:65be27845400 | 1504 | #define SAI2 ((SAI_TypeDef *) SAI2_BASE) |
| AnnaBridge | 172:65be27845400 | 1505 | #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) |
| AnnaBridge | 172:65be27845400 | 1506 | #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) |
| AnnaBridge | 172:65be27845400 | 1507 | #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) |
| AnnaBridge | 172:65be27845400 | 1508 | #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) |
| AnnaBridge | 172:65be27845400 | 1509 | #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) |
| AnnaBridge | 172:65be27845400 | 1510 | #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) |
| AnnaBridge | 172:65be27845400 | 1511 | #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) |
| AnnaBridge | 172:65be27845400 | 1512 | #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) |
| AnnaBridge | 172:65be27845400 | 1513 | #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) |
| AnnaBridge | 172:65be27845400 | 1514 | #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) |
| AnnaBridge | 172:65be27845400 | 1515 | #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) |
| AnnaBridge | 172:65be27845400 | 1516 | #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) |
| AnnaBridge | 172:65be27845400 | 1517 | #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) |
| AnnaBridge | 172:65be27845400 | 1518 | #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) |
| AnnaBridge | 172:65be27845400 | 1519 | /* Aliases to keep compatibility after DFSDM renaming */ |
| AnnaBridge | 172:65be27845400 | 1520 | #define DFSDM_Channel0 DFSDM1_Channel0 |
| AnnaBridge | 172:65be27845400 | 1521 | #define DFSDM_Channel1 DFSDM1_Channel1 |
| AnnaBridge | 172:65be27845400 | 1522 | #define DFSDM_Channel2 DFSDM1_Channel2 |
| AnnaBridge | 172:65be27845400 | 1523 | #define DFSDM_Channel3 DFSDM1_Channel3 |
| AnnaBridge | 172:65be27845400 | 1524 | #define DFSDM_Channel4 DFSDM1_Channel4 |
| AnnaBridge | 172:65be27845400 | 1525 | #define DFSDM_Channel5 DFSDM1_Channel5 |
| AnnaBridge | 172:65be27845400 | 1526 | #define DFSDM_Channel6 DFSDM1_Channel6 |
| AnnaBridge | 172:65be27845400 | 1527 | #define DFSDM_Channel7 DFSDM1_Channel7 |
| AnnaBridge | 172:65be27845400 | 1528 | #define DFSDM_Filter0 DFSDM1_Filter0 |
| AnnaBridge | 172:65be27845400 | 1529 | #define DFSDM_Filter1 DFSDM1_Filter1 |
| AnnaBridge | 172:65be27845400 | 1530 | #define DFSDM_Filter2 DFSDM1_Filter2 |
| AnnaBridge | 172:65be27845400 | 1531 | #define DFSDM_Filter3 DFSDM1_Filter3 |
| AnnaBridge | 172:65be27845400 | 1532 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| AnnaBridge | 172:65be27845400 | 1533 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| AnnaBridge | 172:65be27845400 | 1534 | #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) |
| AnnaBridge | 172:65be27845400 | 1535 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
| AnnaBridge | 172:65be27845400 | 1536 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| AnnaBridge | 172:65be27845400 | 1537 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
| AnnaBridge | 172:65be27845400 | 1538 | #define TSC ((TSC_TypeDef *) TSC_BASE) |
| AnnaBridge | 172:65be27845400 | 1539 | |
| AnnaBridge | 172:65be27845400 | 1540 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| AnnaBridge | 172:65be27845400 | 1541 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| AnnaBridge | 172:65be27845400 | 1542 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| AnnaBridge | 172:65be27845400 | 1543 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| AnnaBridge | 172:65be27845400 | 1544 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| AnnaBridge | 172:65be27845400 | 1545 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| AnnaBridge | 172:65be27845400 | 1546 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| AnnaBridge | 172:65be27845400 | 1547 | #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| AnnaBridge | 172:65be27845400 | 1548 | #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
| AnnaBridge | 172:65be27845400 | 1549 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| AnnaBridge | 172:65be27845400 | 1550 | #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) |
| AnnaBridge | 172:65be27845400 | 1551 | #define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
| AnnaBridge | 172:65be27845400 | 1552 | #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
| AnnaBridge | 172:65be27845400 | 1553 | #define RNG ((RNG_TypeDef *) RNG_BASE) |
| AnnaBridge | 172:65be27845400 | 1554 | #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) |
| AnnaBridge | 172:65be27845400 | 1555 | |
| AnnaBridge | 172:65be27845400 | 1556 | |
| AnnaBridge | 172:65be27845400 | 1557 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| AnnaBridge | 172:65be27845400 | 1558 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| AnnaBridge | 172:65be27845400 | 1559 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| AnnaBridge | 172:65be27845400 | 1560 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| AnnaBridge | 172:65be27845400 | 1561 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| AnnaBridge | 172:65be27845400 | 1562 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| AnnaBridge | 172:65be27845400 | 1563 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| AnnaBridge | 172:65be27845400 | 1564 | |
| AnnaBridge | 172:65be27845400 | 1565 | |
| AnnaBridge | 172:65be27845400 | 1566 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
| AnnaBridge | 172:65be27845400 | 1567 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
| AnnaBridge | 172:65be27845400 | 1568 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
| AnnaBridge | 172:65be27845400 | 1569 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
| AnnaBridge | 172:65be27845400 | 1570 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
| AnnaBridge | 172:65be27845400 | 1571 | #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) |
| AnnaBridge | 172:65be27845400 | 1572 | #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) |
| AnnaBridge | 172:65be27845400 | 1573 | |
| AnnaBridge | 172:65be27845400 | 1574 | #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) |
| AnnaBridge | 172:65be27845400 | 1575 | #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) |
| AnnaBridge | 172:65be27845400 | 1576 | #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) |
| AnnaBridge | 172:65be27845400 | 1577 | #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) |
| AnnaBridge | 172:65be27845400 | 1578 | #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) |
| AnnaBridge | 172:65be27845400 | 1579 | #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) |
| AnnaBridge | 172:65be27845400 | 1580 | #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) |
| AnnaBridge | 172:65be27845400 | 1581 | #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) |
| AnnaBridge | 172:65be27845400 | 1582 | #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) |
| AnnaBridge | 172:65be27845400 | 1583 | #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) |
| AnnaBridge | 172:65be27845400 | 1584 | #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) |
| AnnaBridge | 172:65be27845400 | 1585 | #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) |
| AnnaBridge | 172:65be27845400 | 1586 | #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) |
| AnnaBridge | 172:65be27845400 | 1587 | #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) |
| AnnaBridge | 172:65be27845400 | 1588 | |
| AnnaBridge | 172:65be27845400 | 1589 | #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) |
| AnnaBridge | 172:65be27845400 | 1590 | #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) |
| AnnaBridge | 172:65be27845400 | 1591 | #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) |
| AnnaBridge | 172:65be27845400 | 1592 | #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) |
| AnnaBridge | 172:65be27845400 | 1593 | |
| AnnaBridge | 172:65be27845400 | 1594 | #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) |
| AnnaBridge | 172:65be27845400 | 1595 | #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) |
| AnnaBridge | 172:65be27845400 | 1596 | |
| AnnaBridge | 172:65be27845400 | 1597 | |
| AnnaBridge | 172:65be27845400 | 1598 | #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
| AnnaBridge | 172:65be27845400 | 1599 | #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
| AnnaBridge | 172:65be27845400 | 1600 | #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
| AnnaBridge | 172:65be27845400 | 1601 | |
| AnnaBridge | 172:65be27845400 | 1602 | #define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE) |
| AnnaBridge | 172:65be27845400 | 1603 | #define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE) |
| AnnaBridge | 172:65be27845400 | 1604 | #define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE) |
| AnnaBridge | 172:65be27845400 | 1605 | |
| AnnaBridge | 172:65be27845400 | 1606 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| AnnaBridge | 172:65be27845400 | 1607 | |
| AnnaBridge | 172:65be27845400 | 1608 | #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| AnnaBridge | 172:65be27845400 | 1609 | /** |
| AnnaBridge | 172:65be27845400 | 1610 | * @} |
| AnnaBridge | 172:65be27845400 | 1611 | */ |
| AnnaBridge | 172:65be27845400 | 1612 | |
| AnnaBridge | 172:65be27845400 | 1613 | /** @addtogroup Exported_constants |
| AnnaBridge | 172:65be27845400 | 1614 | * @{ |
| AnnaBridge | 172:65be27845400 | 1615 | */ |
| AnnaBridge | 172:65be27845400 | 1616 | |
| AnnaBridge | 172:65be27845400 | 1617 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| AnnaBridge | 172:65be27845400 | 1618 | * @{ |
| AnnaBridge | 172:65be27845400 | 1619 | */ |
| AnnaBridge | 172:65be27845400 | 1620 | |
| AnnaBridge | 172:65be27845400 | 1621 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 1622 | /* Peripheral Registers_Bits_Definition */ |
| AnnaBridge | 172:65be27845400 | 1623 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 1624 | |
| AnnaBridge | 172:65be27845400 | 1625 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 1626 | /* */ |
| AnnaBridge | 172:65be27845400 | 1627 | /* Analog to Digital Converter */ |
| AnnaBridge | 172:65be27845400 | 1628 | /* */ |
| AnnaBridge | 172:65be27845400 | 1629 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 1630 | |
| AnnaBridge | 172:65be27845400 | 1631 | /* |
| AnnaBridge | 172:65be27845400 | 1632 | * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) |
| AnnaBridge | 172:65be27845400 | 1633 | */ |
| AnnaBridge | 172:65be27845400 | 1634 | |
| AnnaBridge | 172:65be27845400 | 1635 | /******************** Bit definition for ADC_ISR register *******************/ |
| AnnaBridge | 172:65be27845400 | 1636 | #define ADC_ISR_ADRDY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1637 | #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1638 | #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ |
| AnnaBridge | 172:65be27845400 | 1639 | #define ADC_ISR_EOSMP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 1640 | #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1641 | #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ |
| AnnaBridge | 172:65be27845400 | 1642 | #define ADC_ISR_EOC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 1643 | #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1644 | #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ |
| AnnaBridge | 172:65be27845400 | 1645 | #define ADC_ISR_EOS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 1646 | #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1647 | #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| AnnaBridge | 172:65be27845400 | 1648 | #define ADC_ISR_OVR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 1649 | #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1650 | #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ |
| AnnaBridge | 172:65be27845400 | 1651 | #define ADC_ISR_JEOC_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 1652 | #define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1653 | #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ |
| AnnaBridge | 172:65be27845400 | 1654 | #define ADC_ISR_JEOS_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 1655 | #define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 1656 | #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
| AnnaBridge | 172:65be27845400 | 1657 | #define ADC_ISR_AWD1_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 1658 | #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 1659 | #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ |
| AnnaBridge | 172:65be27845400 | 1660 | #define ADC_ISR_AWD2_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 1661 | #define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 1662 | #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ |
| AnnaBridge | 172:65be27845400 | 1663 | #define ADC_ISR_AWD3_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 1664 | #define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 1665 | #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ |
| AnnaBridge | 172:65be27845400 | 1666 | #define ADC_ISR_JQOVF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 1667 | #define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 1668 | #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ |
| AnnaBridge | 172:65be27845400 | 1669 | |
| AnnaBridge | 172:65be27845400 | 1670 | /******************** Bit definition for ADC_IER register *******************/ |
| AnnaBridge | 172:65be27845400 | 1671 | #define ADC_IER_ADRDYIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1672 | #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1673 | #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ |
| AnnaBridge | 172:65be27845400 | 1674 | #define ADC_IER_EOSMPIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 1675 | #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1676 | #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ |
| AnnaBridge | 172:65be27845400 | 1677 | #define ADC_IER_EOCIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 1678 | #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1679 | #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ |
| AnnaBridge | 172:65be27845400 | 1680 | #define ADC_IER_EOSIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 1681 | #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1682 | #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| AnnaBridge | 172:65be27845400 | 1683 | #define ADC_IER_OVRIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 1684 | #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1685 | #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ |
| AnnaBridge | 172:65be27845400 | 1686 | #define ADC_IER_JEOCIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 1687 | #define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1688 | #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ |
| AnnaBridge | 172:65be27845400 | 1689 | #define ADC_IER_JEOSIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 1690 | #define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 1691 | #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
| AnnaBridge | 172:65be27845400 | 1692 | #define ADC_IER_AWD1IE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 1693 | #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 1694 | #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| AnnaBridge | 172:65be27845400 | 1695 | #define ADC_IER_AWD2IE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 1696 | #define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 1697 | #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ |
| AnnaBridge | 172:65be27845400 | 1698 | #define ADC_IER_AWD3IE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 1699 | #define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 1700 | #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ |
| AnnaBridge | 172:65be27845400 | 1701 | #define ADC_IER_JQOVFIE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 1702 | #define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 1703 | #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ |
| AnnaBridge | 172:65be27845400 | 1704 | |
| AnnaBridge | 172:65be27845400 | 1705 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 1706 | #define ADC_IER_ADRDY (ADC_IER_ADRDYIE) |
| AnnaBridge | 172:65be27845400 | 1707 | #define ADC_IER_EOSMP (ADC_IER_EOSMPIE) |
| AnnaBridge | 172:65be27845400 | 1708 | #define ADC_IER_EOC (ADC_IER_EOCIE) |
| AnnaBridge | 172:65be27845400 | 1709 | #define ADC_IER_EOS (ADC_IER_EOSIE) |
| AnnaBridge | 172:65be27845400 | 1710 | #define ADC_IER_OVR (ADC_IER_OVRIE) |
| AnnaBridge | 172:65be27845400 | 1711 | #define ADC_IER_JEOC (ADC_IER_JEOCIE) |
| AnnaBridge | 172:65be27845400 | 1712 | #define ADC_IER_JEOS (ADC_IER_JEOSIE) |
| AnnaBridge | 172:65be27845400 | 1713 | #define ADC_IER_AWD1 (ADC_IER_AWD1IE) |
| AnnaBridge | 172:65be27845400 | 1714 | #define ADC_IER_AWD2 (ADC_IER_AWD2IE) |
| AnnaBridge | 172:65be27845400 | 1715 | #define ADC_IER_AWD3 (ADC_IER_AWD3IE) |
| AnnaBridge | 172:65be27845400 | 1716 | #define ADC_IER_JQOVF (ADC_IER_JQOVFIE) |
| AnnaBridge | 172:65be27845400 | 1717 | |
| AnnaBridge | 172:65be27845400 | 1718 | /******************** Bit definition for ADC_CR register ********************/ |
| AnnaBridge | 172:65be27845400 | 1719 | #define ADC_CR_ADEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1720 | #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1721 | #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ |
| AnnaBridge | 172:65be27845400 | 1722 | #define ADC_CR_ADDIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 1723 | #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1724 | #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ |
| AnnaBridge | 172:65be27845400 | 1725 | #define ADC_CR_ADSTART_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 1726 | #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1727 | #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ |
| AnnaBridge | 172:65be27845400 | 1728 | #define ADC_CR_JADSTART_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 1729 | #define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1730 | #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ |
| AnnaBridge | 172:65be27845400 | 1731 | #define ADC_CR_ADSTP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 1732 | #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1733 | #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ |
| AnnaBridge | 172:65be27845400 | 1734 | #define ADC_CR_JADSTP_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 1735 | #define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1736 | #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ |
| AnnaBridge | 172:65be27845400 | 1737 | #define ADC_CR_ADVREGEN_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 1738 | #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 1739 | #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ |
| AnnaBridge | 172:65be27845400 | 1740 | #define ADC_CR_DEEPPWD_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 1741 | #define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 1742 | #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ |
| AnnaBridge | 172:65be27845400 | 1743 | #define ADC_CR_ADCALDIF_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 1744 | #define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 1745 | #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ |
| AnnaBridge | 172:65be27845400 | 1746 | #define ADC_CR_ADCAL_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 1747 | #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 1748 | #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ |
| AnnaBridge | 172:65be27845400 | 1749 | |
| AnnaBridge | 172:65be27845400 | 1750 | /******************** Bit definition for ADC_CFGR register ******************/ |
| AnnaBridge | 172:65be27845400 | 1751 | #define ADC_CFGR_DMAEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1752 | #define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1753 | #define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ |
| AnnaBridge | 172:65be27845400 | 1754 | #define ADC_CFGR_DMACFG_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 1755 | #define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1756 | #define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ |
| AnnaBridge | 172:65be27845400 | 1757 | |
| AnnaBridge | 172:65be27845400 | 1758 | #define ADC_CFGR_DFSDMCFG_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 1759 | #define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1760 | #define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ |
| AnnaBridge | 172:65be27845400 | 1761 | |
| AnnaBridge | 172:65be27845400 | 1762 | #define ADC_CFGR_RES_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 1763 | #define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 172:65be27845400 | 1764 | #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ |
| AnnaBridge | 172:65be27845400 | 1765 | #define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1766 | #define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1767 | |
| AnnaBridge | 172:65be27845400 | 1768 | #define ADC_CFGR_ALIGN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 1769 | #define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1770 | #define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ |
| AnnaBridge | 172:65be27845400 | 1771 | |
| AnnaBridge | 172:65be27845400 | 1772 | #define ADC_CFGR_EXTSEL_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 1773 | #define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ |
| AnnaBridge | 172:65be27845400 | 1774 | #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| AnnaBridge | 172:65be27845400 | 1775 | #define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 1776 | #define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 1777 | #define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 1778 | #define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 1779 | |
| AnnaBridge | 172:65be27845400 | 1780 | #define ADC_CFGR_EXTEN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 1781 | #define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 1782 | #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ |
| AnnaBridge | 172:65be27845400 | 1783 | #define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 1784 | #define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 1785 | |
| AnnaBridge | 172:65be27845400 | 1786 | #define ADC_CFGR_OVRMOD_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 1787 | #define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 1788 | #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ |
| AnnaBridge | 172:65be27845400 | 1789 | #define ADC_CFGR_CONT_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 1790 | #define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 1791 | #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| AnnaBridge | 172:65be27845400 | 1792 | #define ADC_CFGR_AUTDLY_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 1793 | #define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 1794 | #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ |
| AnnaBridge | 172:65be27845400 | 1795 | |
| AnnaBridge | 172:65be27845400 | 1796 | #define ADC_CFGR_DISCEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 1797 | #define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 1798 | #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| AnnaBridge | 172:65be27845400 | 1799 | |
| AnnaBridge | 172:65be27845400 | 1800 | #define ADC_CFGR_DISCNUM_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 1801 | #define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 172:65be27845400 | 1802 | #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
| AnnaBridge | 172:65be27845400 | 1803 | #define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 1804 | #define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 1805 | #define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 1806 | |
| AnnaBridge | 172:65be27845400 | 1807 | #define ADC_CFGR_JDISCEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 1808 | #define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 1809 | #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
| AnnaBridge | 172:65be27845400 | 1810 | #define ADC_CFGR_JQM_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 1811 | #define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 1812 | #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ |
| AnnaBridge | 172:65be27845400 | 1813 | #define ADC_CFGR_AWD1SGL_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 1814 | #define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 1815 | #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| AnnaBridge | 172:65be27845400 | 1816 | #define ADC_CFGR_AWD1EN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 1817 | #define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 1818 | #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| AnnaBridge | 172:65be27845400 | 1819 | #define ADC_CFGR_JAWD1EN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 1820 | #define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 1821 | #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
| AnnaBridge | 172:65be27845400 | 1822 | #define ADC_CFGR_JAUTO_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 1823 | #define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 1824 | #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
| AnnaBridge | 172:65be27845400 | 1825 | |
| AnnaBridge | 172:65be27845400 | 1826 | #define ADC_CFGR_AWD1CH_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 1827 | #define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 172:65be27845400 | 1828 | #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| AnnaBridge | 172:65be27845400 | 1829 | #define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 1830 | #define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 1831 | #define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 1832 | #define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 1833 | #define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 1834 | |
| AnnaBridge | 172:65be27845400 | 1835 | #define ADC_CFGR_JQDIS_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 1836 | #define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 1837 | #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ |
| AnnaBridge | 172:65be27845400 | 1838 | |
| AnnaBridge | 172:65be27845400 | 1839 | /******************** Bit definition for ADC_CFGR2 register *****************/ |
| AnnaBridge | 172:65be27845400 | 1840 | #define ADC_CFGR2_ROVSE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1841 | #define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1842 | #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ |
| AnnaBridge | 172:65be27845400 | 1843 | #define ADC_CFGR2_JOVSE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 1844 | #define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1845 | #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ |
| AnnaBridge | 172:65be27845400 | 1846 | |
| AnnaBridge | 172:65be27845400 | 1847 | #define ADC_CFGR2_OVSR_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 1848 | #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ |
| AnnaBridge | 172:65be27845400 | 1849 | #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ |
| AnnaBridge | 172:65be27845400 | 1850 | #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1851 | #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1852 | #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1853 | |
| AnnaBridge | 172:65be27845400 | 1854 | #define ADC_CFGR2_OVSS_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 1855 | #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ |
| AnnaBridge | 172:65be27845400 | 1856 | #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ |
| AnnaBridge | 172:65be27845400 | 1857 | #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1858 | #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 1859 | #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 1860 | #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 1861 | |
| AnnaBridge | 172:65be27845400 | 1862 | #define ADC_CFGR2_TROVS_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 1863 | #define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 1864 | #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ |
| AnnaBridge | 172:65be27845400 | 1865 | #define ADC_CFGR2_ROVSM_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 1866 | #define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 1867 | #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ |
| AnnaBridge | 172:65be27845400 | 1868 | |
| AnnaBridge | 172:65be27845400 | 1869 | /******************** Bit definition for ADC_SMPR1 register *****************/ |
| AnnaBridge | 172:65be27845400 | 1870 | #define ADC_SMPR1_SMP0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1871 | #define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 1872 | #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1873 | #define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1874 | #define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1875 | #define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1876 | |
| AnnaBridge | 172:65be27845400 | 1877 | #define ADC_SMPR1_SMP1_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 1878 | #define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 172:65be27845400 | 1879 | #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1880 | #define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1881 | #define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1882 | #define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1883 | |
| AnnaBridge | 172:65be27845400 | 1884 | #define ADC_SMPR1_SMP2_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 1885 | #define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ |
| AnnaBridge | 172:65be27845400 | 1886 | #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1887 | #define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 1888 | #define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 1889 | #define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 1890 | |
| AnnaBridge | 172:65be27845400 | 1891 | #define ADC_SMPR1_SMP3_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 1892 | #define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 172:65be27845400 | 1893 | #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1894 | #define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 1895 | #define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 1896 | #define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 1897 | |
| AnnaBridge | 172:65be27845400 | 1898 | #define ADC_SMPR1_SMP4_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 1899 | #define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 1900 | #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1901 | #define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 1902 | #define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 1903 | #define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 1904 | |
| AnnaBridge | 172:65be27845400 | 1905 | #define ADC_SMPR1_SMP5_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 1906 | #define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ |
| AnnaBridge | 172:65be27845400 | 1907 | #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1908 | #define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 1909 | #define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 1910 | #define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 1911 | |
| AnnaBridge | 172:65be27845400 | 1912 | #define ADC_SMPR1_SMP6_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 1913 | #define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 172:65be27845400 | 1914 | #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1915 | #define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 1916 | #define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 1917 | #define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 1918 | |
| AnnaBridge | 172:65be27845400 | 1919 | #define ADC_SMPR1_SMP7_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 1920 | #define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 172:65be27845400 | 1921 | #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1922 | #define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 1923 | #define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 1924 | #define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 1925 | |
| AnnaBridge | 172:65be27845400 | 1926 | #define ADC_SMPR1_SMP8_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 1927 | #define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 1928 | #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1929 | #define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 1930 | #define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 1931 | #define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 1932 | |
| AnnaBridge | 172:65be27845400 | 1933 | #define ADC_SMPR1_SMP9_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 1934 | #define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ |
| AnnaBridge | 172:65be27845400 | 1935 | #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1936 | #define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 1937 | #define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 1938 | #define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 1939 | |
| AnnaBridge | 172:65be27845400 | 1940 | #define ADC_SMPR1_SMPPLUS_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 1941 | #define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 1942 | #define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ |
| AnnaBridge | 172:65be27845400 | 1943 | |
| AnnaBridge | 172:65be27845400 | 1944 | /******************** Bit definition for ADC_SMPR2 register *****************/ |
| AnnaBridge | 172:65be27845400 | 1945 | #define ADC_SMPR2_SMP10_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 1946 | #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 1947 | #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1948 | #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 1949 | #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 1950 | #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 1951 | |
| AnnaBridge | 172:65be27845400 | 1952 | #define ADC_SMPR2_SMP11_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 1953 | #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 172:65be27845400 | 1954 | #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1955 | #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 1956 | #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 1957 | #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 1958 | |
| AnnaBridge | 172:65be27845400 | 1959 | #define ADC_SMPR2_SMP12_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 1960 | #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ |
| AnnaBridge | 172:65be27845400 | 1961 | #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1962 | #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 1963 | #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 1964 | #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 1965 | |
| AnnaBridge | 172:65be27845400 | 1966 | #define ADC_SMPR2_SMP13_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 1967 | #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 172:65be27845400 | 1968 | #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1969 | #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 1970 | #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 1971 | #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 1972 | |
| AnnaBridge | 172:65be27845400 | 1973 | #define ADC_SMPR2_SMP14_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 1974 | #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 1975 | #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1976 | #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 1977 | #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 1978 | #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 1979 | |
| AnnaBridge | 172:65be27845400 | 1980 | #define ADC_SMPR2_SMP15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 1981 | #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ |
| AnnaBridge | 172:65be27845400 | 1982 | #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1983 | #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 1984 | #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 1985 | #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 1986 | |
| AnnaBridge | 172:65be27845400 | 1987 | #define ADC_SMPR2_SMP16_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 1988 | #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 172:65be27845400 | 1989 | #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1990 | #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 1991 | #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 1992 | #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 1993 | |
| AnnaBridge | 172:65be27845400 | 1994 | #define ADC_SMPR2_SMP17_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 1995 | #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 172:65be27845400 | 1996 | #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 1997 | #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 1998 | #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 1999 | #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2000 | |
| AnnaBridge | 172:65be27845400 | 2001 | #define ADC_SMPR2_SMP18_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2002 | #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 2003 | #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ |
| AnnaBridge | 172:65be27845400 | 2004 | #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2005 | #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 2006 | #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2007 | |
| AnnaBridge | 172:65be27845400 | 2008 | /******************** Bit definition for ADC_TR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 2009 | #define ADC_TR1_LT1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2010 | #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 2011 | #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ |
| AnnaBridge | 172:65be27845400 | 2012 | #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2013 | #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2014 | #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2015 | #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2016 | #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2017 | #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2018 | #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2019 | #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2020 | #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2021 | #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2022 | #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2023 | #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2024 | |
| AnnaBridge | 172:65be27845400 | 2025 | #define ADC_TR1_HT1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2026 | #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 172:65be27845400 | 2027 | #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ |
| AnnaBridge | 172:65be27845400 | 2028 | #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2029 | #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2030 | #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2031 | #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2032 | #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2033 | #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2034 | #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2035 | #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2036 | #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2037 | #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 2038 | #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2039 | #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2040 | |
| AnnaBridge | 172:65be27845400 | 2041 | /******************** Bit definition for ADC_TR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 2042 | #define ADC_TR2_LT2_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2043 | #define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 2044 | #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ |
| AnnaBridge | 172:65be27845400 | 2045 | #define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2046 | #define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2047 | #define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2048 | #define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2049 | #define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2050 | #define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2051 | #define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2052 | #define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2053 | |
| AnnaBridge | 172:65be27845400 | 2054 | #define ADC_TR2_HT2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2055 | #define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 2056 | #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ |
| AnnaBridge | 172:65be27845400 | 2057 | #define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2058 | #define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2059 | #define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2060 | #define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2061 | #define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2062 | #define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2063 | #define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2064 | #define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2065 | |
| AnnaBridge | 172:65be27845400 | 2066 | /******************** Bit definition for ADC_TR3 register *******************/ |
| AnnaBridge | 172:65be27845400 | 2067 | #define ADC_TR3_LT3_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2068 | #define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 2069 | #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ |
| AnnaBridge | 172:65be27845400 | 2070 | #define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2071 | #define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2072 | #define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2073 | #define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2074 | #define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2075 | #define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2076 | #define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2077 | #define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2078 | |
| AnnaBridge | 172:65be27845400 | 2079 | #define ADC_TR3_HT3_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2080 | #define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 2081 | #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ |
| AnnaBridge | 172:65be27845400 | 2082 | #define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2083 | #define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2084 | #define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2085 | #define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2086 | #define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2087 | #define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2088 | #define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2089 | #define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2090 | |
| AnnaBridge | 172:65be27845400 | 2091 | /******************** Bit definition for ADC_SQR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2092 | #define ADC_SQR1_L_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2093 | #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 2094 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
| AnnaBridge | 172:65be27845400 | 2095 | #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2096 | #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2097 | #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2098 | #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2099 | |
| AnnaBridge | 172:65be27845400 | 2100 | #define ADC_SQR1_SQ1_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2101 | #define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 172:65be27845400 | 2102 | #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
| AnnaBridge | 172:65be27845400 | 2103 | #define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2104 | #define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2105 | #define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2106 | #define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2107 | #define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2108 | |
| AnnaBridge | 172:65be27845400 | 2109 | #define ADC_SQR1_SQ2_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 2110 | #define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ |
| AnnaBridge | 172:65be27845400 | 2111 | #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
| AnnaBridge | 172:65be27845400 | 2112 | #define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2113 | #define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2114 | #define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2115 | #define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2116 | #define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2117 | |
| AnnaBridge | 172:65be27845400 | 2118 | #define ADC_SQR1_SQ3_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 2119 | #define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 172:65be27845400 | 2120 | #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
| AnnaBridge | 172:65be27845400 | 2121 | #define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2122 | #define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2123 | #define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2124 | #define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2125 | #define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2126 | |
| AnnaBridge | 172:65be27845400 | 2127 | #define ADC_SQR1_SQ4_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2128 | #define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 172:65be27845400 | 2129 | #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
| AnnaBridge | 172:65be27845400 | 2130 | #define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2131 | #define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 2132 | #define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2133 | #define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2134 | #define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2135 | |
| AnnaBridge | 172:65be27845400 | 2136 | /******************** Bit definition for ADC_SQR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2137 | #define ADC_SQR2_SQ5_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2138 | #define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 2139 | #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
| AnnaBridge | 172:65be27845400 | 2140 | #define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2141 | #define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2142 | #define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2143 | #define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2144 | #define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2145 | |
| AnnaBridge | 172:65be27845400 | 2146 | #define ADC_SQR2_SQ6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2147 | #define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 172:65be27845400 | 2148 | #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
| AnnaBridge | 172:65be27845400 | 2149 | #define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2150 | #define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2151 | #define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2152 | #define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2153 | #define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2154 | |
| AnnaBridge | 172:65be27845400 | 2155 | #define ADC_SQR2_SQ7_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 2156 | #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ |
| AnnaBridge | 172:65be27845400 | 2157 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
| AnnaBridge | 172:65be27845400 | 2158 | #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2159 | #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2160 | #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2161 | #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2162 | #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2163 | |
| AnnaBridge | 172:65be27845400 | 2164 | #define ADC_SQR2_SQ8_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 2165 | #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 172:65be27845400 | 2166 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
| AnnaBridge | 172:65be27845400 | 2167 | #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2168 | #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2169 | #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2170 | #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2171 | #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2172 | |
| AnnaBridge | 172:65be27845400 | 2173 | #define ADC_SQR2_SQ9_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2174 | #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 172:65be27845400 | 2175 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
| AnnaBridge | 172:65be27845400 | 2176 | #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2177 | #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 2178 | #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2179 | #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2180 | #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2181 | |
| AnnaBridge | 172:65be27845400 | 2182 | /******************** Bit definition for ADC_SQR3 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2183 | #define ADC_SQR3_SQ10_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2184 | #define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 2185 | #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
| AnnaBridge | 172:65be27845400 | 2186 | #define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2187 | #define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2188 | #define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2189 | #define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2190 | #define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2191 | |
| AnnaBridge | 172:65be27845400 | 2192 | #define ADC_SQR3_SQ11_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2193 | #define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 172:65be27845400 | 2194 | #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ |
| AnnaBridge | 172:65be27845400 | 2195 | #define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2196 | #define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2197 | #define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2198 | #define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2199 | #define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2200 | |
| AnnaBridge | 172:65be27845400 | 2201 | #define ADC_SQR3_SQ12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 2202 | #define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ |
| AnnaBridge | 172:65be27845400 | 2203 | #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
| AnnaBridge | 172:65be27845400 | 2204 | #define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2205 | #define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2206 | #define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2207 | #define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2208 | #define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2209 | |
| AnnaBridge | 172:65be27845400 | 2210 | #define ADC_SQR3_SQ13_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 2211 | #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ |
| AnnaBridge | 172:65be27845400 | 2212 | #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
| AnnaBridge | 172:65be27845400 | 2213 | #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2214 | #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2215 | #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2216 | #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2217 | #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2218 | |
| AnnaBridge | 172:65be27845400 | 2219 | #define ADC_SQR3_SQ14_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2220 | #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 172:65be27845400 | 2221 | #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
| AnnaBridge | 172:65be27845400 | 2222 | #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2223 | #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 2224 | #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2225 | #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2226 | #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2227 | |
| AnnaBridge | 172:65be27845400 | 2228 | /******************** Bit definition for ADC_SQR4 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2229 | #define ADC_SQR4_SQ15_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2230 | #define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 2231 | #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
| AnnaBridge | 172:65be27845400 | 2232 | #define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2233 | #define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2234 | #define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2235 | #define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2236 | #define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2237 | |
| AnnaBridge | 172:65be27845400 | 2238 | #define ADC_SQR4_SQ16_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2239 | #define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 172:65be27845400 | 2240 | #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
| AnnaBridge | 172:65be27845400 | 2241 | #define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2242 | #define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2243 | #define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2244 | #define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2245 | #define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2246 | |
| AnnaBridge | 172:65be27845400 | 2247 | /******************** Bit definition for ADC_DR register ********************/ |
| AnnaBridge | 172:65be27845400 | 2248 | #define ADC_DR_RDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2249 | #define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 2250 | #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ |
| AnnaBridge | 172:65be27845400 | 2251 | #define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2252 | #define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2253 | #define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2254 | #define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2255 | #define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2256 | #define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2257 | #define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2258 | #define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2259 | #define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2260 | #define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2261 | #define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2262 | #define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2263 | #define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2264 | #define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2265 | #define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2266 | #define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2267 | |
| AnnaBridge | 172:65be27845400 | 2268 | /******************** Bit definition for ADC_JSQR register ******************/ |
| AnnaBridge | 172:65be27845400 | 2269 | #define ADC_JSQR_JL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2270 | #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 2271 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
| AnnaBridge | 172:65be27845400 | 2272 | #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2273 | #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2274 | |
| AnnaBridge | 172:65be27845400 | 2275 | #define ADC_JSQR_JEXTSEL_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2276 | #define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ |
| AnnaBridge | 172:65be27845400 | 2277 | #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
| AnnaBridge | 172:65be27845400 | 2278 | #define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2279 | #define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2280 | #define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2281 | #define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2282 | |
| AnnaBridge | 172:65be27845400 | 2283 | #define ADC_JSQR_JEXTEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2284 | #define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 2285 | #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ |
| AnnaBridge | 172:65be27845400 | 2286 | #define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2287 | #define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2288 | |
| AnnaBridge | 172:65be27845400 | 2289 | #define ADC_JSQR_JSQ1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2290 | #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 2291 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
| AnnaBridge | 172:65be27845400 | 2292 | #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2293 | #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2294 | #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2295 | #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2296 | #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2297 | |
| AnnaBridge | 172:65be27845400 | 2298 | #define ADC_JSQR_JSQ2_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 2299 | #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ |
| AnnaBridge | 172:65be27845400 | 2300 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
| AnnaBridge | 172:65be27845400 | 2301 | #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2302 | #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2303 | #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2304 | #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2305 | #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2306 | |
| AnnaBridge | 172:65be27845400 | 2307 | #define ADC_JSQR_JSQ3_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 2308 | #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ |
| AnnaBridge | 172:65be27845400 | 2309 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
| AnnaBridge | 172:65be27845400 | 2310 | #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2311 | #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2312 | #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2313 | #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2314 | #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2315 | |
| AnnaBridge | 172:65be27845400 | 2316 | #define ADC_JSQR_JSQ4_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2317 | #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 172:65be27845400 | 2318 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
| AnnaBridge | 172:65be27845400 | 2319 | #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2320 | #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2321 | #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2322 | #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 2323 | #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2324 | |
| AnnaBridge | 172:65be27845400 | 2325 | /******************** Bit definition for ADC_OFR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2326 | #define ADC_OFR1_OFFSET1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2327 | #define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 2328 | #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ |
| AnnaBridge | 172:65be27845400 | 2329 | #define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2330 | #define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2331 | #define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2332 | #define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2333 | #define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2334 | #define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2335 | #define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2336 | #define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2337 | #define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2338 | #define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2339 | #define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2340 | #define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2341 | |
| AnnaBridge | 172:65be27845400 | 2342 | #define ADC_OFR1_OFFSET1_CH_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2343 | #define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 172:65be27845400 | 2344 | #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ |
| AnnaBridge | 172:65be27845400 | 2345 | #define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2346 | #define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2347 | #define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2348 | #define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 2349 | #define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2350 | |
| AnnaBridge | 172:65be27845400 | 2351 | #define ADC_OFR1_OFFSET1_EN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 2352 | #define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 2353 | #define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ |
| AnnaBridge | 172:65be27845400 | 2354 | |
| AnnaBridge | 172:65be27845400 | 2355 | /******************** Bit definition for ADC_OFR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2356 | #define ADC_OFR2_OFFSET2_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2357 | #define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 2358 | #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ |
| AnnaBridge | 172:65be27845400 | 2359 | #define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2360 | #define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2361 | #define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2362 | #define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2363 | #define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2364 | #define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2365 | #define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2366 | #define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2367 | #define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2368 | #define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2369 | #define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2370 | #define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2371 | |
| AnnaBridge | 172:65be27845400 | 2372 | #define ADC_OFR2_OFFSET2_CH_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2373 | #define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 172:65be27845400 | 2374 | #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ |
| AnnaBridge | 172:65be27845400 | 2375 | #define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2376 | #define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2377 | #define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2378 | #define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 2379 | #define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2380 | |
| AnnaBridge | 172:65be27845400 | 2381 | #define ADC_OFR2_OFFSET2_EN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 2382 | #define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 2383 | #define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ |
| AnnaBridge | 172:65be27845400 | 2384 | |
| AnnaBridge | 172:65be27845400 | 2385 | /******************** Bit definition for ADC_OFR3 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2386 | #define ADC_OFR3_OFFSET3_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2387 | #define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 2388 | #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ |
| AnnaBridge | 172:65be27845400 | 2389 | #define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2390 | #define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2391 | #define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2392 | #define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2393 | #define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2394 | #define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2395 | #define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2396 | #define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2397 | #define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2398 | #define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2399 | #define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2400 | #define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2401 | |
| AnnaBridge | 172:65be27845400 | 2402 | #define ADC_OFR3_OFFSET3_CH_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2403 | #define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 172:65be27845400 | 2404 | #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ |
| AnnaBridge | 172:65be27845400 | 2405 | #define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2406 | #define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2407 | #define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2408 | #define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 2409 | #define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2410 | |
| AnnaBridge | 172:65be27845400 | 2411 | #define ADC_OFR3_OFFSET3_EN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 2412 | #define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 2413 | #define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ |
| AnnaBridge | 172:65be27845400 | 2414 | |
| AnnaBridge | 172:65be27845400 | 2415 | /******************** Bit definition for ADC_OFR4 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2416 | #define ADC_OFR4_OFFSET4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2417 | #define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 2418 | #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ |
| AnnaBridge | 172:65be27845400 | 2419 | #define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2420 | #define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2421 | #define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2422 | #define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2423 | #define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2424 | #define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2425 | #define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2426 | #define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2427 | #define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2428 | #define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2429 | #define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2430 | #define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2431 | |
| AnnaBridge | 172:65be27845400 | 2432 | #define ADC_OFR4_OFFSET4_CH_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2433 | #define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ |
| AnnaBridge | 172:65be27845400 | 2434 | #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ |
| AnnaBridge | 172:65be27845400 | 2435 | #define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2436 | #define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2437 | #define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2438 | #define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 2439 | #define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2440 | |
| AnnaBridge | 172:65be27845400 | 2441 | #define ADC_OFR4_OFFSET4_EN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 2442 | #define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 2443 | #define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ |
| AnnaBridge | 172:65be27845400 | 2444 | |
| AnnaBridge | 172:65be27845400 | 2445 | /******************** Bit definition for ADC_JDR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2446 | #define ADC_JDR1_JDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2447 | #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 2448 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
| AnnaBridge | 172:65be27845400 | 2449 | #define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2450 | #define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2451 | #define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2452 | #define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2453 | #define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2454 | #define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2455 | #define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2456 | #define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2457 | #define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2458 | #define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2459 | #define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2460 | #define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2461 | #define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2462 | #define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2463 | #define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2464 | #define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2465 | |
| AnnaBridge | 172:65be27845400 | 2466 | /******************** Bit definition for ADC_JDR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2467 | #define ADC_JDR2_JDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2468 | #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 2469 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
| AnnaBridge | 172:65be27845400 | 2470 | #define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2471 | #define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2472 | #define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2473 | #define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2474 | #define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2475 | #define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2476 | #define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2477 | #define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2478 | #define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2479 | #define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2480 | #define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2481 | #define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2482 | #define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2483 | #define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2484 | #define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2485 | #define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2486 | |
| AnnaBridge | 172:65be27845400 | 2487 | /******************** Bit definition for ADC_JDR3 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2488 | #define ADC_JDR3_JDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2489 | #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 2490 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
| AnnaBridge | 172:65be27845400 | 2491 | #define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2492 | #define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2493 | #define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2494 | #define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2495 | #define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2496 | #define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2497 | #define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2498 | #define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2499 | #define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2500 | #define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2501 | #define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2502 | #define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2503 | #define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2504 | #define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2505 | #define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2506 | #define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2507 | |
| AnnaBridge | 172:65be27845400 | 2508 | /******************** Bit definition for ADC_JDR4 register ******************/ |
| AnnaBridge | 172:65be27845400 | 2509 | #define ADC_JDR4_JDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2510 | #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 2511 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
| AnnaBridge | 172:65be27845400 | 2512 | #define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2513 | #define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2514 | #define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2515 | #define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2516 | #define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2517 | #define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2518 | #define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2519 | #define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2520 | #define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2521 | #define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2522 | #define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2523 | #define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2524 | #define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2525 | #define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2526 | #define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2527 | #define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2528 | |
| AnnaBridge | 172:65be27845400 | 2529 | /******************** Bit definition for ADC_AWD2CR register ****************/ |
| AnnaBridge | 172:65be27845400 | 2530 | #define ADC_AWD2CR_AWD2CH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2531 | #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 172:65be27845400 | 2532 | #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ |
| AnnaBridge | 172:65be27845400 | 2533 | #define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2534 | #define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2535 | #define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2536 | #define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2537 | #define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2538 | #define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2539 | #define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2540 | #define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2541 | #define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2542 | #define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2543 | #define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2544 | #define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2545 | #define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2546 | #define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2547 | #define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2548 | #define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2549 | #define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2550 | #define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2551 | #define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2552 | |
| AnnaBridge | 172:65be27845400 | 2553 | /******************** Bit definition for ADC_AWD3CR register ****************/ |
| AnnaBridge | 172:65be27845400 | 2554 | #define ADC_AWD3CR_AWD3CH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2555 | #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 172:65be27845400 | 2556 | #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ |
| AnnaBridge | 172:65be27845400 | 2557 | #define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2558 | #define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2559 | #define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2560 | #define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2561 | #define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2562 | #define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2563 | #define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2564 | #define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2565 | #define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2566 | #define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2567 | #define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2568 | #define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2569 | #define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2570 | #define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2571 | #define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2572 | #define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2573 | #define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2574 | #define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2575 | #define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2576 | |
| AnnaBridge | 172:65be27845400 | 2577 | /******************** Bit definition for ADC_DIFSEL register ****************/ |
| AnnaBridge | 172:65be27845400 | 2578 | #define ADC_DIFSEL_DIFSEL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2579 | #define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 172:65be27845400 | 2580 | #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ |
| AnnaBridge | 172:65be27845400 | 2581 | #define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2582 | #define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2583 | #define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2584 | #define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2585 | #define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2586 | #define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2587 | #define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2588 | #define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2589 | #define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2590 | #define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2591 | #define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2592 | #define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2593 | #define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 2594 | #define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 2595 | #define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 2596 | #define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2597 | #define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2598 | #define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2599 | #define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2600 | |
| AnnaBridge | 172:65be27845400 | 2601 | /******************** Bit definition for ADC_CALFACT register ***************/ |
| AnnaBridge | 172:65be27845400 | 2602 | #define ADC_CALFACT_CALFACT_S_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2603 | #define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 172:65be27845400 | 2604 | #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ |
| AnnaBridge | 172:65be27845400 | 2605 | #define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2606 | #define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2607 | #define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2608 | #define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2609 | #define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2610 | #define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2611 | #define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2612 | |
| AnnaBridge | 172:65be27845400 | 2613 | #define ADC_CALFACT_CALFACT_D_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2614 | #define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ |
| AnnaBridge | 172:65be27845400 | 2615 | #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ |
| AnnaBridge | 172:65be27845400 | 2616 | #define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2617 | #define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2618 | #define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2619 | #define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2620 | #define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2621 | #define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2622 | #define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2623 | |
| AnnaBridge | 172:65be27845400 | 2624 | /************************* ADC Common registers *****************************/ |
| AnnaBridge | 172:65be27845400 | 2625 | /******************** Bit definition for ADC_CCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 2626 | #define ADC_CCR_CKMODE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2627 | #define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 2628 | #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ |
| AnnaBridge | 172:65be27845400 | 2629 | #define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2630 | #define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2631 | |
| AnnaBridge | 172:65be27845400 | 2632 | #define ADC_CCR_PRESC_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 2633 | #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ |
| AnnaBridge | 172:65be27845400 | 2634 | #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ |
| AnnaBridge | 172:65be27845400 | 2635 | #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2636 | #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2637 | #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2638 | #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2639 | |
| AnnaBridge | 172:65be27845400 | 2640 | #define ADC_CCR_VREFEN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 2641 | #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2642 | #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ |
| AnnaBridge | 172:65be27845400 | 2643 | #define ADC_CCR_TSEN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 2644 | #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2645 | #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ |
| AnnaBridge | 172:65be27845400 | 2646 | #define ADC_CCR_VBATEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2647 | #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2648 | #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ |
| AnnaBridge | 172:65be27845400 | 2649 | |
| AnnaBridge | 172:65be27845400 | 2650 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 2651 | /* */ |
| AnnaBridge | 172:65be27845400 | 2652 | /* Controller Area Network */ |
| AnnaBridge | 172:65be27845400 | 2653 | /* */ |
| AnnaBridge | 172:65be27845400 | 2654 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 2655 | /*!<CAN control and status registers */ |
| AnnaBridge | 172:65be27845400 | 2656 | /******************* Bit definition for CAN_MCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 2657 | #define CAN_MCR_INRQ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2658 | #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2659 | #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ |
| AnnaBridge | 172:65be27845400 | 2660 | #define CAN_MCR_SLEEP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2661 | #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2662 | #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ |
| AnnaBridge | 172:65be27845400 | 2663 | #define CAN_MCR_TXFP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2664 | #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2665 | #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ |
| AnnaBridge | 172:65be27845400 | 2666 | #define CAN_MCR_RFLM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2667 | #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2668 | #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ |
| AnnaBridge | 172:65be27845400 | 2669 | #define CAN_MCR_NART_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 2670 | #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2671 | #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ |
| AnnaBridge | 172:65be27845400 | 2672 | #define CAN_MCR_AWUM_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 2673 | #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2674 | #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ |
| AnnaBridge | 172:65be27845400 | 2675 | #define CAN_MCR_ABOM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2676 | #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2677 | #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ |
| AnnaBridge | 172:65be27845400 | 2678 | #define CAN_MCR_TTCM_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 2679 | #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2680 | #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ |
| AnnaBridge | 172:65be27845400 | 2681 | #define CAN_MCR_RESET_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 2682 | #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2683 | #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ |
| AnnaBridge | 172:65be27845400 | 2684 | |
| AnnaBridge | 172:65be27845400 | 2685 | /******************* Bit definition for CAN_MSR register ********************/ |
| AnnaBridge | 172:65be27845400 | 2686 | #define CAN_MSR_INAK_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2687 | #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2688 | #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ |
| AnnaBridge | 172:65be27845400 | 2689 | #define CAN_MSR_SLAK_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2690 | #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2691 | #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ |
| AnnaBridge | 172:65be27845400 | 2692 | #define CAN_MSR_ERRI_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2693 | #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2694 | #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ |
| AnnaBridge | 172:65be27845400 | 2695 | #define CAN_MSR_WKUI_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2696 | #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2697 | #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ |
| AnnaBridge | 172:65be27845400 | 2698 | #define CAN_MSR_SLAKI_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 2699 | #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2700 | #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ |
| AnnaBridge | 172:65be27845400 | 2701 | #define CAN_MSR_TXM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2702 | #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2703 | #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ |
| AnnaBridge | 172:65be27845400 | 2704 | #define CAN_MSR_RXM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 2705 | #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2706 | #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ |
| AnnaBridge | 172:65be27845400 | 2707 | #define CAN_MSR_SAMP_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 2708 | #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2709 | #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ |
| AnnaBridge | 172:65be27845400 | 2710 | #define CAN_MSR_RX_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 2711 | #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2712 | #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ |
| AnnaBridge | 172:65be27845400 | 2713 | |
| AnnaBridge | 172:65be27845400 | 2714 | /******************* Bit definition for CAN_TSR register ********************/ |
| AnnaBridge | 172:65be27845400 | 2715 | #define CAN_TSR_RQCP0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2716 | #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2717 | #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ |
| AnnaBridge | 172:65be27845400 | 2718 | #define CAN_TSR_TXOK0_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2719 | #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2720 | #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ |
| AnnaBridge | 172:65be27845400 | 2721 | #define CAN_TSR_ALST0_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2722 | #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2723 | #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ |
| AnnaBridge | 172:65be27845400 | 2724 | #define CAN_TSR_TERR0_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2725 | #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2726 | #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ |
| AnnaBridge | 172:65be27845400 | 2727 | #define CAN_TSR_ABRQ0_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 2728 | #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 2729 | #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ |
| AnnaBridge | 172:65be27845400 | 2730 | #define CAN_TSR_RQCP1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2731 | #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2732 | #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ |
| AnnaBridge | 172:65be27845400 | 2733 | #define CAN_TSR_TXOK1_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 2734 | #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2735 | #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ |
| AnnaBridge | 172:65be27845400 | 2736 | #define CAN_TSR_ALST1_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 2737 | #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2738 | #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ |
| AnnaBridge | 172:65be27845400 | 2739 | #define CAN_TSR_TERR1_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 2740 | #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2741 | #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ |
| AnnaBridge | 172:65be27845400 | 2742 | #define CAN_TSR_ABRQ1_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 2743 | #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2744 | #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ |
| AnnaBridge | 172:65be27845400 | 2745 | #define CAN_TSR_RQCP2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2746 | #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2747 | #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ |
| AnnaBridge | 172:65be27845400 | 2748 | #define CAN_TSR_TXOK2_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 2749 | #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2750 | #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ |
| AnnaBridge | 172:65be27845400 | 2751 | #define CAN_TSR_ALST2_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 2752 | #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2753 | #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ |
| AnnaBridge | 172:65be27845400 | 2754 | #define CAN_TSR_TERR2_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 2755 | #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2756 | #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ |
| AnnaBridge | 172:65be27845400 | 2757 | #define CAN_TSR_ABRQ2_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 2758 | #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 2759 | #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ |
| AnnaBridge | 172:65be27845400 | 2760 | #define CAN_TSR_CODE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2761 | #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 2762 | #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ |
| AnnaBridge | 172:65be27845400 | 2763 | |
| AnnaBridge | 172:65be27845400 | 2764 | #define CAN_TSR_TME_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2765 | #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| AnnaBridge | 172:65be27845400 | 2766 | #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ |
| AnnaBridge | 172:65be27845400 | 2767 | #define CAN_TSR_TME0_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 2768 | #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 2769 | #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ |
| AnnaBridge | 172:65be27845400 | 2770 | #define CAN_TSR_TME1_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 2771 | #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 2772 | #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ |
| AnnaBridge | 172:65be27845400 | 2773 | #define CAN_TSR_TME2_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 2774 | #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 2775 | #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ |
| AnnaBridge | 172:65be27845400 | 2776 | |
| AnnaBridge | 172:65be27845400 | 2777 | #define CAN_TSR_LOW_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 2778 | #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| AnnaBridge | 172:65be27845400 | 2779 | #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ |
| AnnaBridge | 172:65be27845400 | 2780 | #define CAN_TSR_LOW0_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 2781 | #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 2782 | #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ |
| AnnaBridge | 172:65be27845400 | 2783 | #define CAN_TSR_LOW1_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 2784 | #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2785 | #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ |
| AnnaBridge | 172:65be27845400 | 2786 | #define CAN_TSR_LOW2_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 2787 | #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 2788 | #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ |
| AnnaBridge | 172:65be27845400 | 2789 | |
| AnnaBridge | 172:65be27845400 | 2790 | /******************* Bit definition for CAN_RF0R register *******************/ |
| AnnaBridge | 172:65be27845400 | 2791 | #define CAN_RF0R_FMP0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2792 | #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 2793 | #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ |
| AnnaBridge | 172:65be27845400 | 2794 | #define CAN_RF0R_FULL0_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2795 | #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2796 | #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ |
| AnnaBridge | 172:65be27845400 | 2797 | #define CAN_RF0R_FOVR0_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 2798 | #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2799 | #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ |
| AnnaBridge | 172:65be27845400 | 2800 | #define CAN_RF0R_RFOM0_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 2801 | #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2802 | #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ |
| AnnaBridge | 172:65be27845400 | 2803 | |
| AnnaBridge | 172:65be27845400 | 2804 | /******************* Bit definition for CAN_RF1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 2805 | #define CAN_RF1R_FMP1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2806 | #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 2807 | #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ |
| AnnaBridge | 172:65be27845400 | 2808 | #define CAN_RF1R_FULL1_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2809 | #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2810 | #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ |
| AnnaBridge | 172:65be27845400 | 2811 | #define CAN_RF1R_FOVR1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 2812 | #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2813 | #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ |
| AnnaBridge | 172:65be27845400 | 2814 | #define CAN_RF1R_RFOM1_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 2815 | #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2816 | #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ |
| AnnaBridge | 172:65be27845400 | 2817 | |
| AnnaBridge | 172:65be27845400 | 2818 | /******************** Bit definition for CAN_IER register *******************/ |
| AnnaBridge | 172:65be27845400 | 2819 | #define CAN_IER_TMEIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2820 | #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2821 | #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2822 | #define CAN_IER_FMPIE0_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2823 | #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2824 | #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2825 | #define CAN_IER_FFIE0_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2826 | #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2827 | #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2828 | #define CAN_IER_FOVIE0_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2829 | #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 2830 | #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2831 | #define CAN_IER_FMPIE1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 2832 | #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2833 | #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2834 | #define CAN_IER_FFIE1_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 2835 | #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2836 | #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2837 | #define CAN_IER_FOVIE1_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 2838 | #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2839 | #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2840 | #define CAN_IER_EWGIE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2841 | #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2842 | #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2843 | #define CAN_IER_EPVIE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 2844 | #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 2845 | #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2846 | #define CAN_IER_BOFIE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 2847 | #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 2848 | #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2849 | #define CAN_IER_LECIE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 2850 | #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 2851 | #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2852 | #define CAN_IER_ERRIE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 2853 | #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 2854 | #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2855 | #define CAN_IER_WKUIE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2856 | #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2857 | #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2858 | #define CAN_IER_SLKIE_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 2859 | #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2860 | #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 2861 | |
| AnnaBridge | 172:65be27845400 | 2862 | /******************** Bit definition for CAN_ESR register *******************/ |
| AnnaBridge | 172:65be27845400 | 2863 | #define CAN_ESR_EWGF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2864 | #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2865 | #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ |
| AnnaBridge | 172:65be27845400 | 2866 | #define CAN_ESR_EPVF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2867 | #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2868 | #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ |
| AnnaBridge | 172:65be27845400 | 2869 | #define CAN_ESR_BOFF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2870 | #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2871 | #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ |
| AnnaBridge | 172:65be27845400 | 2872 | |
| AnnaBridge | 172:65be27845400 | 2873 | #define CAN_ESR_LEC_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 2874 | #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 2875 | #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ |
| AnnaBridge | 172:65be27845400 | 2876 | #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 2877 | #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 2878 | #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 2879 | |
| AnnaBridge | 172:65be27845400 | 2880 | #define CAN_ESR_TEC_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2881 | #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 2882 | #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| AnnaBridge | 172:65be27845400 | 2883 | #define CAN_ESR_REC_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2884 | #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 2885 | #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ |
| AnnaBridge | 172:65be27845400 | 2886 | |
| AnnaBridge | 172:65be27845400 | 2887 | /******************* Bit definition for CAN_BTR register ********************/ |
| AnnaBridge | 172:65be27845400 | 2888 | #define CAN_BTR_BRP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2889 | #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 2890 | #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| AnnaBridge | 172:65be27845400 | 2891 | #define CAN_BTR_TS1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2892 | #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 2893 | #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| AnnaBridge | 172:65be27845400 | 2894 | #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 2895 | #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 2896 | #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 2897 | #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 2898 | #define CAN_BTR_TS2_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 2899 | #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| AnnaBridge | 172:65be27845400 | 2900 | #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| AnnaBridge | 172:65be27845400 | 2901 | #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 2902 | #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 2903 | #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 2904 | #define CAN_BTR_SJW_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2905 | #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 2906 | #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| AnnaBridge | 172:65be27845400 | 2907 | #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 2908 | #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 2909 | #define CAN_BTR_LBKM_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 2910 | #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 2911 | #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| AnnaBridge | 172:65be27845400 | 2912 | #define CAN_BTR_SILM_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 2913 | #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 2914 | #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| AnnaBridge | 172:65be27845400 | 2915 | |
| AnnaBridge | 172:65be27845400 | 2916 | /*!<Mailbox registers */ |
| AnnaBridge | 172:65be27845400 | 2917 | /****************** Bit definition for CAN_TI0R register ********************/ |
| AnnaBridge | 172:65be27845400 | 2918 | #define CAN_TI0R_TXRQ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2919 | #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2920 | #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 172:65be27845400 | 2921 | #define CAN_TI0R_RTR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2922 | #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2923 | #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 172:65be27845400 | 2924 | #define CAN_TI0R_IDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2925 | #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2926 | #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 172:65be27845400 | 2927 | #define CAN_TI0R_EXID_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2928 | #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 172:65be27845400 | 2929 | #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 2930 | #define CAN_TI0R_STID_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 2931 | #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 172:65be27845400 | 2932 | #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 2933 | |
| AnnaBridge | 172:65be27845400 | 2934 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| AnnaBridge | 172:65be27845400 | 2935 | #define CAN_TDT0R_DLC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2936 | #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 2937 | #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 172:65be27845400 | 2938 | #define CAN_TDT0R_TGT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2939 | #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2940 | #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 172:65be27845400 | 2941 | #define CAN_TDT0R_TIME_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2942 | #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 2943 | #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 172:65be27845400 | 2944 | |
| AnnaBridge | 172:65be27845400 | 2945 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| AnnaBridge | 172:65be27845400 | 2946 | #define CAN_TDL0R_DATA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2947 | #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 2948 | #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 172:65be27845400 | 2949 | #define CAN_TDL0R_DATA1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2950 | #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 2951 | #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 172:65be27845400 | 2952 | #define CAN_TDL0R_DATA2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2953 | #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 2954 | #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 172:65be27845400 | 2955 | #define CAN_TDL0R_DATA3_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2956 | #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 2957 | #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 172:65be27845400 | 2958 | |
| AnnaBridge | 172:65be27845400 | 2959 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| AnnaBridge | 172:65be27845400 | 2960 | #define CAN_TDH0R_DATA4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2961 | #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 2962 | #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 172:65be27845400 | 2963 | #define CAN_TDH0R_DATA5_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2964 | #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 2965 | #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 172:65be27845400 | 2966 | #define CAN_TDH0R_DATA6_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2967 | #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 2968 | #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 172:65be27845400 | 2969 | #define CAN_TDH0R_DATA7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 2970 | #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 2971 | #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 172:65be27845400 | 2972 | |
| AnnaBridge | 172:65be27845400 | 2973 | /******************* Bit definition for CAN_TI1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 2974 | #define CAN_TI1R_TXRQ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2975 | #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 2976 | #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 172:65be27845400 | 2977 | #define CAN_TI1R_RTR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 2978 | #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 2979 | #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 172:65be27845400 | 2980 | #define CAN_TI1R_IDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 2981 | #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 2982 | #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 172:65be27845400 | 2983 | #define CAN_TI1R_EXID_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 2984 | #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 172:65be27845400 | 2985 | #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 2986 | #define CAN_TI1R_STID_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 2987 | #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 172:65be27845400 | 2988 | #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 2989 | |
| AnnaBridge | 172:65be27845400 | 2990 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| AnnaBridge | 172:65be27845400 | 2991 | #define CAN_TDT1R_DLC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 2992 | #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 2993 | #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 172:65be27845400 | 2994 | #define CAN_TDT1R_TGT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 2995 | #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 2996 | #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 172:65be27845400 | 2997 | #define CAN_TDT1R_TIME_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 2998 | #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 2999 | #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 172:65be27845400 | 3000 | |
| AnnaBridge | 172:65be27845400 | 3001 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3002 | #define CAN_TDL1R_DATA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3003 | #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3004 | #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 172:65be27845400 | 3005 | #define CAN_TDL1R_DATA1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3006 | #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3007 | #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 172:65be27845400 | 3008 | #define CAN_TDL1R_DATA2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3009 | #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3010 | #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 172:65be27845400 | 3011 | #define CAN_TDL1R_DATA3_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3012 | #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3013 | #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 172:65be27845400 | 3014 | |
| AnnaBridge | 172:65be27845400 | 3015 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3016 | #define CAN_TDH1R_DATA4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3017 | #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3018 | #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 172:65be27845400 | 3019 | #define CAN_TDH1R_DATA5_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3020 | #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3021 | #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 172:65be27845400 | 3022 | #define CAN_TDH1R_DATA6_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3023 | #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3024 | #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 172:65be27845400 | 3025 | #define CAN_TDH1R_DATA7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3026 | #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3027 | #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 172:65be27845400 | 3028 | |
| AnnaBridge | 172:65be27845400 | 3029 | /******************* Bit definition for CAN_TI2R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3030 | #define CAN_TI2R_TXRQ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3031 | #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3032 | #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ |
| AnnaBridge | 172:65be27845400 | 3033 | #define CAN_TI2R_RTR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3034 | #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3035 | #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 172:65be27845400 | 3036 | #define CAN_TI2R_IDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3037 | #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3038 | #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 172:65be27845400 | 3039 | #define CAN_TI2R_EXID_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3040 | #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 172:65be27845400 | 3041 | #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ |
| AnnaBridge | 172:65be27845400 | 3042 | #define CAN_TI2R_STID_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3043 | #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 172:65be27845400 | 3044 | #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 3045 | |
| AnnaBridge | 172:65be27845400 | 3046 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3047 | #define CAN_TDT2R_DLC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3048 | #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 3049 | #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 172:65be27845400 | 3050 | #define CAN_TDT2R_TGT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3051 | #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3052 | #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ |
| AnnaBridge | 172:65be27845400 | 3053 | #define CAN_TDT2R_TIME_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3054 | #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 3055 | #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 172:65be27845400 | 3056 | |
| AnnaBridge | 172:65be27845400 | 3057 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3058 | #define CAN_TDL2R_DATA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3059 | #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3060 | #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 172:65be27845400 | 3061 | #define CAN_TDL2R_DATA1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3062 | #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3063 | #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 172:65be27845400 | 3064 | #define CAN_TDL2R_DATA2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3065 | #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3066 | #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 172:65be27845400 | 3067 | #define CAN_TDL2R_DATA3_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3068 | #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3069 | #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 172:65be27845400 | 3070 | |
| AnnaBridge | 172:65be27845400 | 3071 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3072 | #define CAN_TDH2R_DATA4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3073 | #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3074 | #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 172:65be27845400 | 3075 | #define CAN_TDH2R_DATA5_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3076 | #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3077 | #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 172:65be27845400 | 3078 | #define CAN_TDH2R_DATA6_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3079 | #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3080 | #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 172:65be27845400 | 3081 | #define CAN_TDH2R_DATA7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3082 | #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3083 | #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 172:65be27845400 | 3084 | |
| AnnaBridge | 172:65be27845400 | 3085 | /******************* Bit definition for CAN_RI0R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3086 | #define CAN_RI0R_RTR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3087 | #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3088 | #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 172:65be27845400 | 3089 | #define CAN_RI0R_IDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3090 | #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3091 | #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 172:65be27845400 | 3092 | #define CAN_RI0R_EXID_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3093 | #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 172:65be27845400 | 3094 | #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 3095 | #define CAN_RI0R_STID_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3096 | #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 172:65be27845400 | 3097 | #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 3098 | |
| AnnaBridge | 172:65be27845400 | 3099 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3100 | #define CAN_RDT0R_DLC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3101 | #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 3102 | #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 172:65be27845400 | 3103 | #define CAN_RDT0R_FMI_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3104 | #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3105 | #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ |
| AnnaBridge | 172:65be27845400 | 3106 | #define CAN_RDT0R_TIME_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3107 | #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 3108 | #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 172:65be27845400 | 3109 | |
| AnnaBridge | 172:65be27845400 | 3110 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3111 | #define CAN_RDL0R_DATA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3112 | #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3113 | #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 172:65be27845400 | 3114 | #define CAN_RDL0R_DATA1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3115 | #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3116 | #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 172:65be27845400 | 3117 | #define CAN_RDL0R_DATA2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3118 | #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3119 | #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 172:65be27845400 | 3120 | #define CAN_RDL0R_DATA3_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3121 | #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3122 | #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 172:65be27845400 | 3123 | |
| AnnaBridge | 172:65be27845400 | 3124 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3125 | #define CAN_RDH0R_DATA4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3126 | #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3127 | #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 172:65be27845400 | 3128 | #define CAN_RDH0R_DATA5_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3129 | #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3130 | #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 172:65be27845400 | 3131 | #define CAN_RDH0R_DATA6_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3132 | #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3133 | #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 172:65be27845400 | 3134 | #define CAN_RDH0R_DATA7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3135 | #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3136 | #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 172:65be27845400 | 3137 | |
| AnnaBridge | 172:65be27845400 | 3138 | /******************* Bit definition for CAN_RI1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3139 | #define CAN_RI1R_RTR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3140 | #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3141 | #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ |
| AnnaBridge | 172:65be27845400 | 3142 | #define CAN_RI1R_IDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3143 | #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3144 | #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ |
| AnnaBridge | 172:65be27845400 | 3145 | #define CAN_RI1R_EXID_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3146 | #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| AnnaBridge | 172:65be27845400 | 3147 | #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ |
| AnnaBridge | 172:65be27845400 | 3148 | #define CAN_RI1R_STID_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3149 | #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
| AnnaBridge | 172:65be27845400 | 3150 | #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ |
| AnnaBridge | 172:65be27845400 | 3151 | |
| AnnaBridge | 172:65be27845400 | 3152 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3153 | #define CAN_RDT1R_DLC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3154 | #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 3155 | #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ |
| AnnaBridge | 172:65be27845400 | 3156 | #define CAN_RDT1R_FMI_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3157 | #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3158 | #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ |
| AnnaBridge | 172:65be27845400 | 3159 | #define CAN_RDT1R_TIME_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3160 | #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 3161 | #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ |
| AnnaBridge | 172:65be27845400 | 3162 | |
| AnnaBridge | 172:65be27845400 | 3163 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3164 | #define CAN_RDL1R_DATA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3165 | #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3166 | #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ |
| AnnaBridge | 172:65be27845400 | 3167 | #define CAN_RDL1R_DATA1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3168 | #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3169 | #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ |
| AnnaBridge | 172:65be27845400 | 3170 | #define CAN_RDL1R_DATA2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3171 | #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3172 | #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ |
| AnnaBridge | 172:65be27845400 | 3173 | #define CAN_RDL1R_DATA3_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3174 | #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3175 | #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ |
| AnnaBridge | 172:65be27845400 | 3176 | |
| AnnaBridge | 172:65be27845400 | 3177 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| AnnaBridge | 172:65be27845400 | 3178 | #define CAN_RDH1R_DATA4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3179 | #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 3180 | #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ |
| AnnaBridge | 172:65be27845400 | 3181 | #define CAN_RDH1R_DATA5_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3182 | #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 3183 | #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ |
| AnnaBridge | 172:65be27845400 | 3184 | #define CAN_RDH1R_DATA6_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3185 | #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 3186 | #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ |
| AnnaBridge | 172:65be27845400 | 3187 | #define CAN_RDH1R_DATA7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3188 | #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 3189 | #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ |
| AnnaBridge | 172:65be27845400 | 3190 | |
| AnnaBridge | 172:65be27845400 | 3191 | /*!<CAN filter registers */ |
| AnnaBridge | 172:65be27845400 | 3192 | /******************* Bit definition for CAN_FMR register ********************/ |
| AnnaBridge | 172:65be27845400 | 3193 | #define CAN_FMR_FINIT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3194 | #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3195 | #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ |
| AnnaBridge | 172:65be27845400 | 3196 | |
| AnnaBridge | 172:65be27845400 | 3197 | /******************* Bit definition for CAN_FM1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3198 | #define CAN_FM1R_FBM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3199 | #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 3200 | #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ |
| AnnaBridge | 172:65be27845400 | 3201 | #define CAN_FM1R_FBM0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3202 | #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3203 | #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3204 | #define CAN_FM1R_FBM1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3205 | #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3206 | #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3207 | #define CAN_FM1R_FBM2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3208 | #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3209 | #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3210 | #define CAN_FM1R_FBM3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3211 | #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3212 | #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3213 | #define CAN_FM1R_FBM4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3214 | #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3215 | #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3216 | #define CAN_FM1R_FBM5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3217 | #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3218 | #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3219 | #define CAN_FM1R_FBM6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3220 | #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3221 | #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3222 | #define CAN_FM1R_FBM7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3223 | #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3224 | #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3225 | #define CAN_FM1R_FBM8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3226 | #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3227 | #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3228 | #define CAN_FM1R_FBM9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3229 | #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3230 | #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3231 | #define CAN_FM1R_FBM10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3232 | #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3233 | #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3234 | #define CAN_FM1R_FBM11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3235 | #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3236 | #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3237 | #define CAN_FM1R_FBM12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3238 | #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3239 | #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3240 | #define CAN_FM1R_FBM13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3241 | #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3242 | #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3243 | |
| AnnaBridge | 172:65be27845400 | 3244 | /******************* Bit definition for CAN_FS1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3245 | #define CAN_FS1R_FSC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3246 | #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 3247 | #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ |
| AnnaBridge | 172:65be27845400 | 3248 | #define CAN_FS1R_FSC0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3249 | #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3250 | #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3251 | #define CAN_FS1R_FSC1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3252 | #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3253 | #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3254 | #define CAN_FS1R_FSC2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3255 | #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3256 | #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3257 | #define CAN_FS1R_FSC3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3258 | #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3259 | #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3260 | #define CAN_FS1R_FSC4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3261 | #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3262 | #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3263 | #define CAN_FS1R_FSC5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3264 | #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3265 | #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3266 | #define CAN_FS1R_FSC6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3267 | #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3268 | #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3269 | #define CAN_FS1R_FSC7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3270 | #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3271 | #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3272 | #define CAN_FS1R_FSC8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3273 | #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3274 | #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3275 | #define CAN_FS1R_FSC9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3276 | #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3277 | #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3278 | #define CAN_FS1R_FSC10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3279 | #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3280 | #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3281 | #define CAN_FS1R_FSC11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3282 | #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3283 | #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3284 | #define CAN_FS1R_FSC12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3285 | #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3286 | #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3287 | #define CAN_FS1R_FSC13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3288 | #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3289 | #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3290 | |
| AnnaBridge | 172:65be27845400 | 3291 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3292 | #define CAN_FFA1R_FFA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3293 | #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 3294 | #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ |
| AnnaBridge | 172:65be27845400 | 3295 | #define CAN_FFA1R_FFA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3296 | #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3297 | #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */ |
| AnnaBridge | 172:65be27845400 | 3298 | #define CAN_FFA1R_FFA1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3299 | #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3300 | #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */ |
| AnnaBridge | 172:65be27845400 | 3301 | #define CAN_FFA1R_FFA2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3302 | #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3303 | #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */ |
| AnnaBridge | 172:65be27845400 | 3304 | #define CAN_FFA1R_FFA3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3305 | #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3306 | #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */ |
| AnnaBridge | 172:65be27845400 | 3307 | #define CAN_FFA1R_FFA4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3308 | #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3309 | #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */ |
| AnnaBridge | 172:65be27845400 | 3310 | #define CAN_FFA1R_FFA5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3311 | #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3312 | #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */ |
| AnnaBridge | 172:65be27845400 | 3313 | #define CAN_FFA1R_FFA6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3314 | #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3315 | #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */ |
| AnnaBridge | 172:65be27845400 | 3316 | #define CAN_FFA1R_FFA7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3317 | #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3318 | #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */ |
| AnnaBridge | 172:65be27845400 | 3319 | #define CAN_FFA1R_FFA8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3320 | #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3321 | #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */ |
| AnnaBridge | 172:65be27845400 | 3322 | #define CAN_FFA1R_FFA9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3323 | #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3324 | #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */ |
| AnnaBridge | 172:65be27845400 | 3325 | #define CAN_FFA1R_FFA10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3326 | #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3327 | #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */ |
| AnnaBridge | 172:65be27845400 | 3328 | #define CAN_FFA1R_FFA11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3329 | #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3330 | #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */ |
| AnnaBridge | 172:65be27845400 | 3331 | #define CAN_FFA1R_FFA12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3332 | #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3333 | #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */ |
| AnnaBridge | 172:65be27845400 | 3334 | #define CAN_FFA1R_FFA13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3335 | #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3336 | #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */ |
| AnnaBridge | 172:65be27845400 | 3337 | |
| AnnaBridge | 172:65be27845400 | 3338 | /******************* Bit definition for CAN_FA1R register *******************/ |
| AnnaBridge | 172:65be27845400 | 3339 | #define CAN_FA1R_FACT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3340 | #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 3341 | #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ |
| AnnaBridge | 172:65be27845400 | 3342 | #define CAN_FA1R_FACT0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3343 | #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3344 | #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */ |
| AnnaBridge | 172:65be27845400 | 3345 | #define CAN_FA1R_FACT1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3346 | #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3347 | #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */ |
| AnnaBridge | 172:65be27845400 | 3348 | #define CAN_FA1R_FACT2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3349 | #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3350 | #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */ |
| AnnaBridge | 172:65be27845400 | 3351 | #define CAN_FA1R_FACT3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3352 | #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3353 | #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */ |
| AnnaBridge | 172:65be27845400 | 3354 | #define CAN_FA1R_FACT4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3355 | #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3356 | #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */ |
| AnnaBridge | 172:65be27845400 | 3357 | #define CAN_FA1R_FACT5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3358 | #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3359 | #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */ |
| AnnaBridge | 172:65be27845400 | 3360 | #define CAN_FA1R_FACT6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3361 | #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3362 | #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */ |
| AnnaBridge | 172:65be27845400 | 3363 | #define CAN_FA1R_FACT7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3364 | #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3365 | #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */ |
| AnnaBridge | 172:65be27845400 | 3366 | #define CAN_FA1R_FACT8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3367 | #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3368 | #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */ |
| AnnaBridge | 172:65be27845400 | 3369 | #define CAN_FA1R_FACT9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3370 | #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3371 | #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */ |
| AnnaBridge | 172:65be27845400 | 3372 | #define CAN_FA1R_FACT10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3373 | #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3374 | #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */ |
| AnnaBridge | 172:65be27845400 | 3375 | #define CAN_FA1R_FACT11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3376 | #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3377 | #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */ |
| AnnaBridge | 172:65be27845400 | 3378 | #define CAN_FA1R_FACT12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3379 | #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3380 | #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */ |
| AnnaBridge | 172:65be27845400 | 3381 | #define CAN_FA1R_FACT13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3382 | #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3383 | #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */ |
| AnnaBridge | 172:65be27845400 | 3384 | |
| AnnaBridge | 172:65be27845400 | 3385 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3386 | #define CAN_F0R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3387 | #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3388 | #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3389 | #define CAN_F0R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3390 | #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3391 | #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3392 | #define CAN_F0R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3393 | #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3394 | #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3395 | #define CAN_F0R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3396 | #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3397 | #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3398 | #define CAN_F0R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3399 | #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3400 | #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3401 | #define CAN_F0R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3402 | #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3403 | #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3404 | #define CAN_F0R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3405 | #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3406 | #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3407 | #define CAN_F0R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3408 | #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3409 | #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3410 | #define CAN_F0R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3411 | #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3412 | #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3413 | #define CAN_F0R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3414 | #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3415 | #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3416 | #define CAN_F0R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3417 | #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3418 | #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3419 | #define CAN_F0R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3420 | #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3421 | #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3422 | #define CAN_F0R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3423 | #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3424 | #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3425 | #define CAN_F0R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3426 | #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3427 | #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3428 | #define CAN_F0R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 3429 | #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 3430 | #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 3431 | #define CAN_F0R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 3432 | #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 3433 | #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 3434 | #define CAN_F0R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3435 | #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 3436 | #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 3437 | #define CAN_F0R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 3438 | #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 3439 | #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 3440 | #define CAN_F0R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 3441 | #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 3442 | #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 3443 | #define CAN_F0R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 3444 | #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 3445 | #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 3446 | #define CAN_F0R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 3447 | #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 3448 | #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 3449 | #define CAN_F0R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3450 | #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 3451 | #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 3452 | #define CAN_F0R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 3453 | #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 3454 | #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 3455 | #define CAN_F0R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 3456 | #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 3457 | #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 3458 | #define CAN_F0R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3459 | #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 3460 | #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 3461 | #define CAN_F0R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 3462 | #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 3463 | #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 3464 | #define CAN_F0R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 3465 | #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 3466 | #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 3467 | #define CAN_F0R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 3468 | #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 3469 | #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 3470 | #define CAN_F0R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 3471 | #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 3472 | #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 3473 | #define CAN_F0R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 3474 | #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 3475 | #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 3476 | #define CAN_F0R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 3477 | #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 3478 | #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 3479 | #define CAN_F0R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 3480 | #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 3481 | #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 3482 | |
| AnnaBridge | 172:65be27845400 | 3483 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3484 | #define CAN_F1R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3485 | #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3486 | #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3487 | #define CAN_F1R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3488 | #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3489 | #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3490 | #define CAN_F1R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3491 | #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3492 | #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3493 | #define CAN_F1R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3494 | #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3495 | #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3496 | #define CAN_F1R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3497 | #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3498 | #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3499 | #define CAN_F1R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3500 | #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3501 | #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3502 | #define CAN_F1R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3503 | #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3504 | #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3505 | #define CAN_F1R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3506 | #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3507 | #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3508 | #define CAN_F1R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3509 | #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3510 | #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3511 | #define CAN_F1R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3512 | #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3513 | #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3514 | #define CAN_F1R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3515 | #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3516 | #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3517 | #define CAN_F1R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3518 | #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3519 | #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3520 | #define CAN_F1R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3521 | #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3522 | #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3523 | #define CAN_F1R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3524 | #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3525 | #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3526 | #define CAN_F1R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 3527 | #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 3528 | #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 3529 | #define CAN_F1R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 3530 | #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 3531 | #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 3532 | #define CAN_F1R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3533 | #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 3534 | #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 3535 | #define CAN_F1R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 3536 | #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 3537 | #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 3538 | #define CAN_F1R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 3539 | #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 3540 | #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 3541 | #define CAN_F1R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 3542 | #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 3543 | #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 3544 | #define CAN_F1R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 3545 | #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 3546 | #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 3547 | #define CAN_F1R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3548 | #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 3549 | #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 3550 | #define CAN_F1R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 3551 | #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 3552 | #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 3553 | #define CAN_F1R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 3554 | #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 3555 | #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 3556 | #define CAN_F1R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3557 | #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 3558 | #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 3559 | #define CAN_F1R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 3560 | #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 3561 | #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 3562 | #define CAN_F1R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 3563 | #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 3564 | #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 3565 | #define CAN_F1R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 3566 | #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 3567 | #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 3568 | #define CAN_F1R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 3569 | #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 3570 | #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 3571 | #define CAN_F1R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 3572 | #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 3573 | #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 3574 | #define CAN_F1R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 3575 | #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 3576 | #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 3577 | #define CAN_F1R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 3578 | #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 3579 | #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 3580 | |
| AnnaBridge | 172:65be27845400 | 3581 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3582 | #define CAN_F2R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3583 | #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3584 | #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3585 | #define CAN_F2R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3586 | #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3587 | #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3588 | #define CAN_F2R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3589 | #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3590 | #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3591 | #define CAN_F2R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3592 | #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3593 | #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3594 | #define CAN_F2R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3595 | #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3596 | #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3597 | #define CAN_F2R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3598 | #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3599 | #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3600 | #define CAN_F2R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3601 | #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3602 | #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3603 | #define CAN_F2R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3604 | #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3605 | #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3606 | #define CAN_F2R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3607 | #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3608 | #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3609 | #define CAN_F2R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3610 | #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3611 | #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3612 | #define CAN_F2R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3613 | #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3614 | #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3615 | #define CAN_F2R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3616 | #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3617 | #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3618 | #define CAN_F2R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3619 | #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3620 | #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3621 | #define CAN_F2R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3622 | #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3623 | #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3624 | #define CAN_F2R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 3625 | #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 3626 | #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 3627 | #define CAN_F2R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 3628 | #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 3629 | #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 3630 | #define CAN_F2R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3631 | #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 3632 | #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 3633 | #define CAN_F2R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 3634 | #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 3635 | #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 3636 | #define CAN_F2R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 3637 | #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 3638 | #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 3639 | #define CAN_F2R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 3640 | #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 3641 | #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 3642 | #define CAN_F2R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 3643 | #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 3644 | #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 3645 | #define CAN_F2R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3646 | #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 3647 | #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 3648 | #define CAN_F2R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 3649 | #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 3650 | #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 3651 | #define CAN_F2R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 3652 | #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 3653 | #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 3654 | #define CAN_F2R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3655 | #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 3656 | #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 3657 | #define CAN_F2R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 3658 | #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 3659 | #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 3660 | #define CAN_F2R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 3661 | #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 3662 | #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 3663 | #define CAN_F2R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 3664 | #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 3665 | #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 3666 | #define CAN_F2R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 3667 | #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 3668 | #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 3669 | #define CAN_F2R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 3670 | #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 3671 | #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 3672 | #define CAN_F2R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 3673 | #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 3674 | #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 3675 | #define CAN_F2R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 3676 | #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 3677 | #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 3678 | |
| AnnaBridge | 172:65be27845400 | 3679 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3680 | #define CAN_F3R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3681 | #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3682 | #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3683 | #define CAN_F3R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3684 | #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3685 | #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3686 | #define CAN_F3R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3687 | #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3688 | #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3689 | #define CAN_F3R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3690 | #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3691 | #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3692 | #define CAN_F3R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3693 | #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3694 | #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3695 | #define CAN_F3R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3696 | #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3697 | #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3698 | #define CAN_F3R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3699 | #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3700 | #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3701 | #define CAN_F3R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3702 | #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3703 | #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3704 | #define CAN_F3R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3705 | #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3706 | #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3707 | #define CAN_F3R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3708 | #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3709 | #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3710 | #define CAN_F3R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3711 | #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3712 | #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3713 | #define CAN_F3R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3714 | #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3715 | #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3716 | #define CAN_F3R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3717 | #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3718 | #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3719 | #define CAN_F3R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3720 | #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3721 | #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3722 | #define CAN_F3R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 3723 | #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 3724 | #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 3725 | #define CAN_F3R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 3726 | #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 3727 | #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 3728 | #define CAN_F3R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3729 | #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 3730 | #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 3731 | #define CAN_F3R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 3732 | #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 3733 | #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 3734 | #define CAN_F3R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 3735 | #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 3736 | #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 3737 | #define CAN_F3R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 3738 | #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 3739 | #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 3740 | #define CAN_F3R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 3741 | #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 3742 | #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 3743 | #define CAN_F3R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3744 | #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 3745 | #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 3746 | #define CAN_F3R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 3747 | #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 3748 | #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 3749 | #define CAN_F3R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 3750 | #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 3751 | #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 3752 | #define CAN_F3R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3753 | #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 3754 | #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 3755 | #define CAN_F3R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 3756 | #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 3757 | #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 3758 | #define CAN_F3R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 3759 | #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 3760 | #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 3761 | #define CAN_F3R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 3762 | #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 3763 | #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 3764 | #define CAN_F3R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 3765 | #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 3766 | #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 3767 | #define CAN_F3R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 3768 | #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 3769 | #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 3770 | #define CAN_F3R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 3771 | #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 3772 | #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 3773 | #define CAN_F3R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 3774 | #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 3775 | #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 3776 | |
| AnnaBridge | 172:65be27845400 | 3777 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3778 | #define CAN_F4R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3779 | #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3780 | #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3781 | #define CAN_F4R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3782 | #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3783 | #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3784 | #define CAN_F4R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3785 | #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3786 | #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3787 | #define CAN_F4R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3788 | #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3789 | #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3790 | #define CAN_F4R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3791 | #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3792 | #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3793 | #define CAN_F4R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3794 | #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3795 | #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3796 | #define CAN_F4R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3797 | #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3798 | #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3799 | #define CAN_F4R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3800 | #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3801 | #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3802 | #define CAN_F4R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3803 | #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3804 | #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3805 | #define CAN_F4R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3806 | #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3807 | #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3808 | #define CAN_F4R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3809 | #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3810 | #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3811 | #define CAN_F4R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3812 | #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3813 | #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3814 | #define CAN_F4R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3815 | #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3816 | #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3817 | #define CAN_F4R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3818 | #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3819 | #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3820 | #define CAN_F4R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 3821 | #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 3822 | #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 3823 | #define CAN_F4R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 3824 | #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 3825 | #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 3826 | #define CAN_F4R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3827 | #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 3828 | #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 3829 | #define CAN_F4R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 3830 | #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 3831 | #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 3832 | #define CAN_F4R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 3833 | #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 3834 | #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 3835 | #define CAN_F4R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 3836 | #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 3837 | #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 3838 | #define CAN_F4R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 3839 | #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 3840 | #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 3841 | #define CAN_F4R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3842 | #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 3843 | #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 3844 | #define CAN_F4R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 3845 | #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 3846 | #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 3847 | #define CAN_F4R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 3848 | #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 3849 | #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 3850 | #define CAN_F4R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3851 | #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 3852 | #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 3853 | #define CAN_F4R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 3854 | #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 3855 | #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 3856 | #define CAN_F4R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 3857 | #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 3858 | #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 3859 | #define CAN_F4R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 3860 | #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 3861 | #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 3862 | #define CAN_F4R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 3863 | #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 3864 | #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 3865 | #define CAN_F4R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 3866 | #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 3867 | #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 3868 | #define CAN_F4R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 3869 | #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 3870 | #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 3871 | #define CAN_F4R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 3872 | #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 3873 | #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 3874 | |
| AnnaBridge | 172:65be27845400 | 3875 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3876 | #define CAN_F5R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3877 | #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3878 | #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3879 | #define CAN_F5R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3880 | #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3881 | #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3882 | #define CAN_F5R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3883 | #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3884 | #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3885 | #define CAN_F5R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3886 | #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3887 | #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3888 | #define CAN_F5R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3889 | #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3890 | #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3891 | #define CAN_F5R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3892 | #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3893 | #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3894 | #define CAN_F5R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3895 | #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3896 | #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3897 | #define CAN_F5R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3898 | #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3899 | #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3900 | #define CAN_F5R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3901 | #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 3902 | #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 3903 | #define CAN_F5R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 3904 | #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 3905 | #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 3906 | #define CAN_F5R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 3907 | #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 3908 | #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 3909 | #define CAN_F5R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 3910 | #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 3911 | #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 3912 | #define CAN_F5R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 3913 | #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 3914 | #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 3915 | #define CAN_F5R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 3916 | #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 3917 | #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 3918 | #define CAN_F5R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 3919 | #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 3920 | #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 3921 | #define CAN_F5R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 3922 | #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 3923 | #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 3924 | #define CAN_F5R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 3925 | #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 3926 | #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 3927 | #define CAN_F5R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 3928 | #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 3929 | #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 3930 | #define CAN_F5R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 3931 | #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 3932 | #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 3933 | #define CAN_F5R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 3934 | #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 3935 | #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 3936 | #define CAN_F5R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 3937 | #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 3938 | #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 3939 | #define CAN_F5R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 3940 | #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 3941 | #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 3942 | #define CAN_F5R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 3943 | #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 3944 | #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 3945 | #define CAN_F5R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 3946 | #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 3947 | #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 3948 | #define CAN_F5R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 3949 | #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 3950 | #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 3951 | #define CAN_F5R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 3952 | #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 3953 | #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 3954 | #define CAN_F5R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 3955 | #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 3956 | #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 3957 | #define CAN_F5R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 3958 | #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 3959 | #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 3960 | #define CAN_F5R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 3961 | #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 3962 | #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 3963 | #define CAN_F5R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 3964 | #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 3965 | #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 3966 | #define CAN_F5R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 3967 | #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 3968 | #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 3969 | #define CAN_F5R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 3970 | #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 3971 | #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 3972 | |
| AnnaBridge | 172:65be27845400 | 3973 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 3974 | #define CAN_F6R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 3975 | #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 3976 | #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 3977 | #define CAN_F6R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 3978 | #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 3979 | #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 3980 | #define CAN_F6R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 3981 | #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 3982 | #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 3983 | #define CAN_F6R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 3984 | #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 3985 | #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 3986 | #define CAN_F6R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 3987 | #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 3988 | #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 3989 | #define CAN_F6R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 3990 | #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 3991 | #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 3992 | #define CAN_F6R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 3993 | #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 3994 | #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 3995 | #define CAN_F6R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 3996 | #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 3997 | #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 3998 | #define CAN_F6R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 3999 | #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4000 | #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4001 | #define CAN_F6R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4002 | #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4003 | #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4004 | #define CAN_F6R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4005 | #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4006 | #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4007 | #define CAN_F6R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4008 | #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4009 | #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4010 | #define CAN_F6R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4011 | #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4012 | #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4013 | #define CAN_F6R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4014 | #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4015 | #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4016 | #define CAN_F6R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4017 | #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4018 | #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4019 | #define CAN_F6R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4020 | #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4021 | #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4022 | #define CAN_F6R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4023 | #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4024 | #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4025 | #define CAN_F6R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4026 | #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4027 | #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4028 | #define CAN_F6R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4029 | #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4030 | #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4031 | #define CAN_F6R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4032 | #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4033 | #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4034 | #define CAN_F6R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4035 | #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4036 | #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4037 | #define CAN_F6R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4038 | #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4039 | #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4040 | #define CAN_F6R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4041 | #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4042 | #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4043 | #define CAN_F6R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4044 | #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4045 | #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4046 | #define CAN_F6R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4047 | #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4048 | #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4049 | #define CAN_F6R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4050 | #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4051 | #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4052 | #define CAN_F6R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4053 | #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4054 | #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4055 | #define CAN_F6R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4056 | #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4057 | #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4058 | #define CAN_F6R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4059 | #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4060 | #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4061 | #define CAN_F6R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4062 | #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4063 | #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4064 | #define CAN_F6R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4065 | #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4066 | #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4067 | #define CAN_F6R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4068 | #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4069 | #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4070 | |
| AnnaBridge | 172:65be27845400 | 4071 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 4072 | #define CAN_F7R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4073 | #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4074 | #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4075 | #define CAN_F7R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4076 | #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4077 | #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4078 | #define CAN_F7R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4079 | #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4080 | #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4081 | #define CAN_F7R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4082 | #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4083 | #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4084 | #define CAN_F7R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4085 | #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4086 | #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4087 | #define CAN_F7R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4088 | #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4089 | #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4090 | #define CAN_F7R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4091 | #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4092 | #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4093 | #define CAN_F7R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4094 | #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4095 | #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4096 | #define CAN_F7R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4097 | #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4098 | #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4099 | #define CAN_F7R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4100 | #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4101 | #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4102 | #define CAN_F7R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4103 | #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4104 | #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4105 | #define CAN_F7R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4106 | #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4107 | #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4108 | #define CAN_F7R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4109 | #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4110 | #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4111 | #define CAN_F7R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4112 | #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4113 | #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4114 | #define CAN_F7R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4115 | #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4116 | #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4117 | #define CAN_F7R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4118 | #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4119 | #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4120 | #define CAN_F7R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4121 | #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4122 | #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4123 | #define CAN_F7R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4124 | #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4125 | #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4126 | #define CAN_F7R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4127 | #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4128 | #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4129 | #define CAN_F7R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4130 | #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4131 | #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4132 | #define CAN_F7R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4133 | #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4134 | #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4135 | #define CAN_F7R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4136 | #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4137 | #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4138 | #define CAN_F7R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4139 | #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4140 | #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4141 | #define CAN_F7R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4142 | #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4143 | #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4144 | #define CAN_F7R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4145 | #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4146 | #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4147 | #define CAN_F7R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4148 | #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4149 | #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4150 | #define CAN_F7R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4151 | #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4152 | #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4153 | #define CAN_F7R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4154 | #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4155 | #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4156 | #define CAN_F7R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4157 | #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4158 | #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4159 | #define CAN_F7R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4160 | #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4161 | #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4162 | #define CAN_F7R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4163 | #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4164 | #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4165 | #define CAN_F7R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4166 | #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4167 | #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4168 | |
| AnnaBridge | 172:65be27845400 | 4169 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 4170 | #define CAN_F8R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4171 | #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4172 | #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4173 | #define CAN_F8R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4174 | #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4175 | #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4176 | #define CAN_F8R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4177 | #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4178 | #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4179 | #define CAN_F8R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4180 | #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4181 | #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4182 | #define CAN_F8R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4183 | #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4184 | #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4185 | #define CAN_F8R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4186 | #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4187 | #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4188 | #define CAN_F8R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4189 | #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4190 | #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4191 | #define CAN_F8R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4192 | #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4193 | #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4194 | #define CAN_F8R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4195 | #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4196 | #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4197 | #define CAN_F8R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4198 | #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4199 | #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4200 | #define CAN_F8R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4201 | #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4202 | #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4203 | #define CAN_F8R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4204 | #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4205 | #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4206 | #define CAN_F8R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4207 | #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4208 | #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4209 | #define CAN_F8R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4210 | #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4211 | #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4212 | #define CAN_F8R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4213 | #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4214 | #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4215 | #define CAN_F8R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4216 | #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4217 | #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4218 | #define CAN_F8R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4219 | #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4220 | #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4221 | #define CAN_F8R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4222 | #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4223 | #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4224 | #define CAN_F8R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4225 | #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4226 | #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4227 | #define CAN_F8R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4228 | #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4229 | #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4230 | #define CAN_F8R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4231 | #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4232 | #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4233 | #define CAN_F8R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4234 | #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4235 | #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4236 | #define CAN_F8R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4237 | #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4238 | #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4239 | #define CAN_F8R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4240 | #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4241 | #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4242 | #define CAN_F8R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4243 | #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4244 | #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4245 | #define CAN_F8R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4246 | #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4247 | #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4248 | #define CAN_F8R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4249 | #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4250 | #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4251 | #define CAN_F8R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4252 | #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4253 | #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4254 | #define CAN_F8R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4255 | #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4256 | #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4257 | #define CAN_F8R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4258 | #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4259 | #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4260 | #define CAN_F8R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4261 | #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4262 | #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4263 | #define CAN_F8R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4264 | #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4265 | #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4266 | |
| AnnaBridge | 172:65be27845400 | 4267 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 4268 | #define CAN_F9R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4269 | #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4270 | #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4271 | #define CAN_F9R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4272 | #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4273 | #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4274 | #define CAN_F9R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4275 | #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4276 | #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4277 | #define CAN_F9R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4278 | #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4279 | #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4280 | #define CAN_F9R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4281 | #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4282 | #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4283 | #define CAN_F9R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4284 | #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4285 | #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4286 | #define CAN_F9R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4287 | #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4288 | #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4289 | #define CAN_F9R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4290 | #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4291 | #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4292 | #define CAN_F9R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4293 | #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4294 | #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4295 | #define CAN_F9R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4296 | #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4297 | #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4298 | #define CAN_F9R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4299 | #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4300 | #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4301 | #define CAN_F9R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4302 | #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4303 | #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4304 | #define CAN_F9R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4305 | #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4306 | #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4307 | #define CAN_F9R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4308 | #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4309 | #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4310 | #define CAN_F9R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4311 | #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4312 | #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4313 | #define CAN_F9R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4314 | #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4315 | #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4316 | #define CAN_F9R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4317 | #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4318 | #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4319 | #define CAN_F9R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4320 | #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4321 | #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4322 | #define CAN_F9R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4323 | #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4324 | #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4325 | #define CAN_F9R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4326 | #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4327 | #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4328 | #define CAN_F9R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4329 | #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4330 | #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4331 | #define CAN_F9R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4332 | #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4333 | #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4334 | #define CAN_F9R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4335 | #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4336 | #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4337 | #define CAN_F9R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4338 | #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4339 | #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4340 | #define CAN_F9R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4341 | #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4342 | #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4343 | #define CAN_F9R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4344 | #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4345 | #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4346 | #define CAN_F9R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4347 | #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4348 | #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4349 | #define CAN_F9R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4350 | #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4351 | #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4352 | #define CAN_F9R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4353 | #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4354 | #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4355 | #define CAN_F9R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4356 | #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4357 | #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4358 | #define CAN_F9R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4359 | #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4360 | #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4361 | #define CAN_F9R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4362 | #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4363 | #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4364 | |
| AnnaBridge | 172:65be27845400 | 4365 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 4366 | #define CAN_F10R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4367 | #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4368 | #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4369 | #define CAN_F10R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4370 | #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4371 | #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4372 | #define CAN_F10R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4373 | #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4374 | #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4375 | #define CAN_F10R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4376 | #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4377 | #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4378 | #define CAN_F10R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4379 | #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4380 | #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4381 | #define CAN_F10R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4382 | #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4383 | #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4384 | #define CAN_F10R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4385 | #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4386 | #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4387 | #define CAN_F10R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4388 | #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4389 | #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4390 | #define CAN_F10R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4391 | #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4392 | #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4393 | #define CAN_F10R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4394 | #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4395 | #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4396 | #define CAN_F10R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4397 | #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4398 | #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4399 | #define CAN_F10R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4400 | #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4401 | #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4402 | #define CAN_F10R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4403 | #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4404 | #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4405 | #define CAN_F10R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4406 | #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4407 | #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4408 | #define CAN_F10R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4409 | #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4410 | #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4411 | #define CAN_F10R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4412 | #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4413 | #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4414 | #define CAN_F10R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4415 | #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4416 | #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4417 | #define CAN_F10R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4418 | #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4419 | #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4420 | #define CAN_F10R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4421 | #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4422 | #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4423 | #define CAN_F10R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4424 | #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4425 | #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4426 | #define CAN_F10R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4427 | #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4428 | #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4429 | #define CAN_F10R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4430 | #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4431 | #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4432 | #define CAN_F10R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4433 | #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4434 | #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4435 | #define CAN_F10R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4436 | #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4437 | #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4438 | #define CAN_F10R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4439 | #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4440 | #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4441 | #define CAN_F10R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4442 | #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4443 | #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4444 | #define CAN_F10R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4445 | #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4446 | #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4447 | #define CAN_F10R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4448 | #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4449 | #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4450 | #define CAN_F10R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4451 | #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4452 | #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4453 | #define CAN_F10R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4454 | #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4455 | #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4456 | #define CAN_F10R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4457 | #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4458 | #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4459 | #define CAN_F10R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4460 | #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4461 | #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4462 | |
| AnnaBridge | 172:65be27845400 | 4463 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 4464 | #define CAN_F11R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4465 | #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4466 | #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4467 | #define CAN_F11R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4468 | #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4469 | #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4470 | #define CAN_F11R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4471 | #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4472 | #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4473 | #define CAN_F11R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4474 | #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4475 | #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4476 | #define CAN_F11R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4477 | #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4478 | #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4479 | #define CAN_F11R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4480 | #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4481 | #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4482 | #define CAN_F11R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4483 | #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4484 | #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4485 | #define CAN_F11R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4486 | #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4487 | #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4488 | #define CAN_F11R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4489 | #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4490 | #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4491 | #define CAN_F11R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4492 | #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4493 | #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4494 | #define CAN_F11R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4495 | #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4496 | #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4497 | #define CAN_F11R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4498 | #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4499 | #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4500 | #define CAN_F11R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4501 | #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4502 | #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4503 | #define CAN_F11R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4504 | #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4505 | #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4506 | #define CAN_F11R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4507 | #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4508 | #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4509 | #define CAN_F11R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4510 | #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4511 | #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4512 | #define CAN_F11R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4513 | #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4514 | #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4515 | #define CAN_F11R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4516 | #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4517 | #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4518 | #define CAN_F11R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4519 | #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4520 | #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4521 | #define CAN_F11R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4522 | #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4523 | #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4524 | #define CAN_F11R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4525 | #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4526 | #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4527 | #define CAN_F11R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4528 | #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4529 | #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4530 | #define CAN_F11R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4531 | #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4532 | #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4533 | #define CAN_F11R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4534 | #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4535 | #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4536 | #define CAN_F11R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4537 | #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4538 | #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4539 | #define CAN_F11R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4540 | #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4541 | #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4542 | #define CAN_F11R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4543 | #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4544 | #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4545 | #define CAN_F11R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4546 | #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4547 | #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4548 | #define CAN_F11R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4549 | #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4550 | #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4551 | #define CAN_F11R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4552 | #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4553 | #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4554 | #define CAN_F11R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4555 | #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4556 | #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4557 | #define CAN_F11R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4558 | #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4559 | #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4560 | |
| AnnaBridge | 172:65be27845400 | 4561 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 4562 | #define CAN_F12R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4563 | #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4564 | #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4565 | #define CAN_F12R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4566 | #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4567 | #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4568 | #define CAN_F12R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4569 | #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4570 | #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4571 | #define CAN_F12R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4572 | #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4573 | #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4574 | #define CAN_F12R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4575 | #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4576 | #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4577 | #define CAN_F12R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4578 | #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4579 | #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4580 | #define CAN_F12R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4581 | #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4582 | #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4583 | #define CAN_F12R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4584 | #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4585 | #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4586 | #define CAN_F12R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4587 | #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4588 | #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4589 | #define CAN_F12R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4590 | #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4591 | #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4592 | #define CAN_F12R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4593 | #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4594 | #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4595 | #define CAN_F12R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4596 | #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4597 | #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4598 | #define CAN_F12R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4599 | #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4600 | #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4601 | #define CAN_F12R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4602 | #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4603 | #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4604 | #define CAN_F12R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4605 | #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4606 | #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4607 | #define CAN_F12R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4608 | #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4609 | #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4610 | #define CAN_F12R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4611 | #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4612 | #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4613 | #define CAN_F12R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4614 | #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4615 | #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4616 | #define CAN_F12R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4617 | #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4618 | #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4619 | #define CAN_F12R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4620 | #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4621 | #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4622 | #define CAN_F12R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4623 | #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4624 | #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4625 | #define CAN_F12R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4626 | #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4627 | #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4628 | #define CAN_F12R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4629 | #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4630 | #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4631 | #define CAN_F12R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4632 | #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4633 | #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4634 | #define CAN_F12R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4635 | #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4636 | #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4637 | #define CAN_F12R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4638 | #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4639 | #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4640 | #define CAN_F12R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4641 | #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4642 | #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4643 | #define CAN_F12R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4644 | #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4645 | #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4646 | #define CAN_F12R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4647 | #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4648 | #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4649 | #define CAN_F12R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4650 | #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4651 | #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4652 | #define CAN_F12R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4653 | #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4654 | #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4655 | #define CAN_F12R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4656 | #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4657 | #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4658 | |
| AnnaBridge | 172:65be27845400 | 4659 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 4660 | #define CAN_F13R1_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4661 | #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4662 | #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4663 | #define CAN_F13R1_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4664 | #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4665 | #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4666 | #define CAN_F13R1_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4667 | #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4668 | #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4669 | #define CAN_F13R1_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4670 | #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4671 | #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4672 | #define CAN_F13R1_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4673 | #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4674 | #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4675 | #define CAN_F13R1_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4676 | #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4677 | #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4678 | #define CAN_F13R1_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4679 | #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4680 | #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4681 | #define CAN_F13R1_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4682 | #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4683 | #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4684 | #define CAN_F13R1_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4685 | #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4686 | #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4687 | #define CAN_F13R1_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4688 | #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4689 | #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4690 | #define CAN_F13R1_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4691 | #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4692 | #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4693 | #define CAN_F13R1_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4694 | #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4695 | #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4696 | #define CAN_F13R1_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4697 | #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4698 | #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4699 | #define CAN_F13R1_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4700 | #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4701 | #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4702 | #define CAN_F13R1_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4703 | #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4704 | #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4705 | #define CAN_F13R1_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4706 | #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4707 | #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4708 | #define CAN_F13R1_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4709 | #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4710 | #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4711 | #define CAN_F13R1_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4712 | #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4713 | #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4714 | #define CAN_F13R1_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4715 | #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4716 | #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4717 | #define CAN_F13R1_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4718 | #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4719 | #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4720 | #define CAN_F13R1_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4721 | #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4722 | #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4723 | #define CAN_F13R1_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4724 | #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4725 | #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4726 | #define CAN_F13R1_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4727 | #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4728 | #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4729 | #define CAN_F13R1_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4730 | #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4731 | #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4732 | #define CAN_F13R1_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4733 | #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4734 | #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4735 | #define CAN_F13R1_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4736 | #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4737 | #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4738 | #define CAN_F13R1_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4739 | #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4740 | #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4741 | #define CAN_F13R1_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4742 | #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4743 | #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4744 | #define CAN_F13R1_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4745 | #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4746 | #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4747 | #define CAN_F13R1_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4748 | #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4749 | #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4750 | #define CAN_F13R1_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4751 | #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4752 | #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4753 | #define CAN_F13R1_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4754 | #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4755 | #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4756 | |
| AnnaBridge | 172:65be27845400 | 4757 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 4758 | #define CAN_F0R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4759 | #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4760 | #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4761 | #define CAN_F0R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4762 | #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4763 | #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4764 | #define CAN_F0R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4765 | #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4766 | #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4767 | #define CAN_F0R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4768 | #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4769 | #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4770 | #define CAN_F0R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4771 | #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4772 | #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4773 | #define CAN_F0R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4774 | #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4775 | #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4776 | #define CAN_F0R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4777 | #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4778 | #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4779 | #define CAN_F0R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4780 | #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4781 | #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4782 | #define CAN_F0R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4783 | #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4784 | #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4785 | #define CAN_F0R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4786 | #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4787 | #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4788 | #define CAN_F0R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4789 | #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4790 | #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4791 | #define CAN_F0R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4792 | #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4793 | #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4794 | #define CAN_F0R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4795 | #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4796 | #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4797 | #define CAN_F0R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4798 | #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4799 | #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4800 | #define CAN_F0R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4801 | #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4802 | #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4803 | #define CAN_F0R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4804 | #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4805 | #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4806 | #define CAN_F0R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4807 | #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4808 | #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4809 | #define CAN_F0R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4810 | #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4811 | #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4812 | #define CAN_F0R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4813 | #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4814 | #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4815 | #define CAN_F0R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4816 | #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4817 | #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4818 | #define CAN_F0R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4819 | #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4820 | #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4821 | #define CAN_F0R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4822 | #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4823 | #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4824 | #define CAN_F0R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4825 | #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4826 | #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4827 | #define CAN_F0R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4828 | #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4829 | #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4830 | #define CAN_F0R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4831 | #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4832 | #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4833 | #define CAN_F0R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4834 | #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4835 | #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4836 | #define CAN_F0R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4837 | #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4838 | #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4839 | #define CAN_F0R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4840 | #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4841 | #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4842 | #define CAN_F0R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4843 | #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4844 | #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4845 | #define CAN_F0R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4846 | #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4847 | #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4848 | #define CAN_F0R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4849 | #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4850 | #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4851 | #define CAN_F0R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4852 | #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4853 | #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4854 | |
| AnnaBridge | 172:65be27845400 | 4855 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 4856 | #define CAN_F1R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4857 | #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4858 | #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4859 | #define CAN_F1R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4860 | #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4861 | #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4862 | #define CAN_F1R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4863 | #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4864 | #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4865 | #define CAN_F1R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4866 | #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4867 | #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4868 | #define CAN_F1R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4869 | #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4870 | #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4871 | #define CAN_F1R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4872 | #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4873 | #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4874 | #define CAN_F1R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4875 | #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4876 | #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4877 | #define CAN_F1R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4878 | #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4879 | #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4880 | #define CAN_F1R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4881 | #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4882 | #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4883 | #define CAN_F1R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4884 | #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4885 | #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4886 | #define CAN_F1R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4887 | #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4888 | #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4889 | #define CAN_F1R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4890 | #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4891 | #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4892 | #define CAN_F1R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4893 | #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4894 | #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4895 | #define CAN_F1R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4896 | #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4897 | #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4898 | #define CAN_F1R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4899 | #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4900 | #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4901 | #define CAN_F1R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 4902 | #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 4903 | #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 4904 | #define CAN_F1R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 4905 | #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 4906 | #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 4907 | #define CAN_F1R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 4908 | #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 4909 | #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 4910 | #define CAN_F1R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 4911 | #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 4912 | #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 4913 | #define CAN_F1R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 4914 | #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 4915 | #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 4916 | #define CAN_F1R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 4917 | #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 4918 | #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 4919 | #define CAN_F1R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 4920 | #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 4921 | #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 4922 | #define CAN_F1R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 4923 | #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 4924 | #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 4925 | #define CAN_F1R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 4926 | #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 4927 | #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 4928 | #define CAN_F1R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 4929 | #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 4930 | #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 4931 | #define CAN_F1R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 4932 | #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 4933 | #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 4934 | #define CAN_F1R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 4935 | #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 4936 | #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 4937 | #define CAN_F1R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 4938 | #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 4939 | #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 4940 | #define CAN_F1R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 4941 | #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 4942 | #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 4943 | #define CAN_F1R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 4944 | #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 4945 | #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 4946 | #define CAN_F1R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 4947 | #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 4948 | #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 4949 | #define CAN_F1R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 4950 | #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 4951 | #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 4952 | |
| AnnaBridge | 172:65be27845400 | 4953 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 4954 | #define CAN_F2R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 4955 | #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 4956 | #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 4957 | #define CAN_F2R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 4958 | #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 4959 | #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 4960 | #define CAN_F2R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 4961 | #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 4962 | #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 4963 | #define CAN_F2R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 4964 | #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 4965 | #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 4966 | #define CAN_F2R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 4967 | #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 4968 | #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 4969 | #define CAN_F2R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 4970 | #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 4971 | #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 4972 | #define CAN_F2R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 4973 | #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 4974 | #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 4975 | #define CAN_F2R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 4976 | #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 4977 | #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 4978 | #define CAN_F2R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 4979 | #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 4980 | #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 4981 | #define CAN_F2R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 4982 | #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 4983 | #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 4984 | #define CAN_F2R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 4985 | #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 4986 | #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 4987 | #define CAN_F2R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 4988 | #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 4989 | #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 4990 | #define CAN_F2R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 4991 | #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 4992 | #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 4993 | #define CAN_F2R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 4994 | #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 4995 | #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 4996 | #define CAN_F2R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 4997 | #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 4998 | #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 4999 | #define CAN_F2R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5000 | #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5001 | #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5002 | #define CAN_F2R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5003 | #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5004 | #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5005 | #define CAN_F2R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5006 | #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5007 | #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5008 | #define CAN_F2R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5009 | #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5010 | #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5011 | #define CAN_F2R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5012 | #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5013 | #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5014 | #define CAN_F2R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5015 | #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5016 | #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5017 | #define CAN_F2R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5018 | #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5019 | #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5020 | #define CAN_F2R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5021 | #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5022 | #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5023 | #define CAN_F2R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5024 | #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5025 | #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5026 | #define CAN_F2R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5027 | #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5028 | #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5029 | #define CAN_F2R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5030 | #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5031 | #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5032 | #define CAN_F2R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5033 | #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5034 | #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5035 | #define CAN_F2R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5036 | #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5037 | #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5038 | #define CAN_F2R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5039 | #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5040 | #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5041 | #define CAN_F2R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5042 | #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5043 | #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5044 | #define CAN_F2R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5045 | #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5046 | #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5047 | #define CAN_F2R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5048 | #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5049 | #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5050 | |
| AnnaBridge | 172:65be27845400 | 5051 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5052 | #define CAN_F3R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5053 | #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5054 | #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5055 | #define CAN_F3R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5056 | #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5057 | #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5058 | #define CAN_F3R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5059 | #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5060 | #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5061 | #define CAN_F3R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5062 | #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5063 | #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5064 | #define CAN_F3R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5065 | #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5066 | #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5067 | #define CAN_F3R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5068 | #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5069 | #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5070 | #define CAN_F3R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5071 | #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5072 | #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5073 | #define CAN_F3R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5074 | #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5075 | #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5076 | #define CAN_F3R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5077 | #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5078 | #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5079 | #define CAN_F3R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5080 | #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5081 | #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5082 | #define CAN_F3R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5083 | #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5084 | #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5085 | #define CAN_F3R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5086 | #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5087 | #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5088 | #define CAN_F3R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5089 | #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5090 | #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5091 | #define CAN_F3R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5092 | #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5093 | #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5094 | #define CAN_F3R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5095 | #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5096 | #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5097 | #define CAN_F3R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5098 | #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5099 | #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5100 | #define CAN_F3R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5101 | #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5102 | #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5103 | #define CAN_F3R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5104 | #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5105 | #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5106 | #define CAN_F3R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5107 | #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5108 | #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5109 | #define CAN_F3R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5110 | #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5111 | #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5112 | #define CAN_F3R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5113 | #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5114 | #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5115 | #define CAN_F3R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5116 | #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5117 | #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5118 | #define CAN_F3R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5119 | #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5120 | #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5121 | #define CAN_F3R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5122 | #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5123 | #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5124 | #define CAN_F3R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5125 | #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5126 | #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5127 | #define CAN_F3R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5128 | #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5129 | #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5130 | #define CAN_F3R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5131 | #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5132 | #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5133 | #define CAN_F3R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5134 | #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5135 | #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5136 | #define CAN_F3R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5137 | #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5138 | #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5139 | #define CAN_F3R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5140 | #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5141 | #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5142 | #define CAN_F3R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5143 | #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5144 | #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5145 | #define CAN_F3R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5146 | #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5147 | #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5148 | |
| AnnaBridge | 172:65be27845400 | 5149 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5150 | #define CAN_F4R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5151 | #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5152 | #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5153 | #define CAN_F4R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5154 | #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5155 | #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5156 | #define CAN_F4R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5157 | #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5158 | #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5159 | #define CAN_F4R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5160 | #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5161 | #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5162 | #define CAN_F4R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5163 | #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5164 | #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5165 | #define CAN_F4R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5166 | #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5167 | #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5168 | #define CAN_F4R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5169 | #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5170 | #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5171 | #define CAN_F4R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5172 | #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5173 | #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5174 | #define CAN_F4R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5175 | #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5176 | #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5177 | #define CAN_F4R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5178 | #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5179 | #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5180 | #define CAN_F4R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5181 | #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5182 | #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5183 | #define CAN_F4R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5184 | #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5185 | #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5186 | #define CAN_F4R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5187 | #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5188 | #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5189 | #define CAN_F4R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5190 | #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5191 | #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5192 | #define CAN_F4R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5193 | #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5194 | #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5195 | #define CAN_F4R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5196 | #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5197 | #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5198 | #define CAN_F4R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5199 | #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5200 | #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5201 | #define CAN_F4R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5202 | #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5203 | #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5204 | #define CAN_F4R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5205 | #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5206 | #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5207 | #define CAN_F4R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5208 | #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5209 | #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5210 | #define CAN_F4R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5211 | #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5212 | #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5213 | #define CAN_F4R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5214 | #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5215 | #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5216 | #define CAN_F4R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5217 | #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5218 | #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5219 | #define CAN_F4R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5220 | #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5221 | #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5222 | #define CAN_F4R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5223 | #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5224 | #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5225 | #define CAN_F4R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5226 | #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5227 | #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5228 | #define CAN_F4R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5229 | #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5230 | #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5231 | #define CAN_F4R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5232 | #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5233 | #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5234 | #define CAN_F4R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5235 | #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5236 | #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5237 | #define CAN_F4R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5238 | #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5239 | #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5240 | #define CAN_F4R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5241 | #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5242 | #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5243 | #define CAN_F4R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5244 | #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5245 | #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5246 | |
| AnnaBridge | 172:65be27845400 | 5247 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5248 | #define CAN_F5R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5249 | #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5250 | #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5251 | #define CAN_F5R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5252 | #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5253 | #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5254 | #define CAN_F5R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5255 | #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5256 | #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5257 | #define CAN_F5R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5258 | #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5259 | #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5260 | #define CAN_F5R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5261 | #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5262 | #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5263 | #define CAN_F5R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5264 | #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5265 | #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5266 | #define CAN_F5R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5267 | #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5268 | #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5269 | #define CAN_F5R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5270 | #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5271 | #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5272 | #define CAN_F5R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5273 | #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5274 | #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5275 | #define CAN_F5R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5276 | #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5277 | #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5278 | #define CAN_F5R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5279 | #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5280 | #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5281 | #define CAN_F5R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5282 | #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5283 | #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5284 | #define CAN_F5R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5285 | #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5286 | #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5287 | #define CAN_F5R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5288 | #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5289 | #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5290 | #define CAN_F5R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5291 | #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5292 | #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5293 | #define CAN_F5R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5294 | #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5295 | #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5296 | #define CAN_F5R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5297 | #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5298 | #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5299 | #define CAN_F5R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5300 | #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5301 | #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5302 | #define CAN_F5R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5303 | #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5304 | #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5305 | #define CAN_F5R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5306 | #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5307 | #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5308 | #define CAN_F5R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5309 | #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5310 | #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5311 | #define CAN_F5R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5312 | #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5313 | #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5314 | #define CAN_F5R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5315 | #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5316 | #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5317 | #define CAN_F5R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5318 | #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5319 | #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5320 | #define CAN_F5R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5321 | #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5322 | #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5323 | #define CAN_F5R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5324 | #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5325 | #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5326 | #define CAN_F5R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5327 | #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5328 | #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5329 | #define CAN_F5R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5330 | #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5331 | #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5332 | #define CAN_F5R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5333 | #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5334 | #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5335 | #define CAN_F5R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5336 | #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5337 | #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5338 | #define CAN_F5R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5339 | #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5340 | #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5341 | #define CAN_F5R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5342 | #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5343 | #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5344 | |
| AnnaBridge | 172:65be27845400 | 5345 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5346 | #define CAN_F6R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5347 | #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5348 | #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5349 | #define CAN_F6R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5350 | #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5351 | #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5352 | #define CAN_F6R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5353 | #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5354 | #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5355 | #define CAN_F6R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5356 | #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5357 | #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5358 | #define CAN_F6R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5359 | #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5360 | #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5361 | #define CAN_F6R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5362 | #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5363 | #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5364 | #define CAN_F6R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5365 | #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5366 | #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5367 | #define CAN_F6R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5368 | #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5369 | #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5370 | #define CAN_F6R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5371 | #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5372 | #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5373 | #define CAN_F6R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5374 | #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5375 | #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5376 | #define CAN_F6R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5377 | #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5378 | #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5379 | #define CAN_F6R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5380 | #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5381 | #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5382 | #define CAN_F6R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5383 | #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5384 | #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5385 | #define CAN_F6R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5386 | #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5387 | #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5388 | #define CAN_F6R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5389 | #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5390 | #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5391 | #define CAN_F6R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5392 | #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5393 | #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5394 | #define CAN_F6R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5395 | #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5396 | #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5397 | #define CAN_F6R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5398 | #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5399 | #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5400 | #define CAN_F6R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5401 | #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5402 | #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5403 | #define CAN_F6R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5404 | #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5405 | #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5406 | #define CAN_F6R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5407 | #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5408 | #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5409 | #define CAN_F6R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5410 | #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5411 | #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5412 | #define CAN_F6R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5413 | #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5414 | #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5415 | #define CAN_F6R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5416 | #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5417 | #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5418 | #define CAN_F6R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5419 | #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5420 | #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5421 | #define CAN_F6R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5422 | #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5423 | #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5424 | #define CAN_F6R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5425 | #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5426 | #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5427 | #define CAN_F6R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5428 | #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5429 | #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5430 | #define CAN_F6R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5431 | #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5432 | #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5433 | #define CAN_F6R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5434 | #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5435 | #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5436 | #define CAN_F6R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5437 | #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5438 | #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5439 | #define CAN_F6R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5440 | #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5441 | #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5442 | |
| AnnaBridge | 172:65be27845400 | 5443 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5444 | #define CAN_F7R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5445 | #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5446 | #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5447 | #define CAN_F7R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5448 | #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5449 | #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5450 | #define CAN_F7R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5451 | #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5452 | #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5453 | #define CAN_F7R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5454 | #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5455 | #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5456 | #define CAN_F7R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5457 | #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5458 | #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5459 | #define CAN_F7R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5460 | #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5461 | #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5462 | #define CAN_F7R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5463 | #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5464 | #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5465 | #define CAN_F7R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5466 | #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5467 | #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5468 | #define CAN_F7R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5469 | #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5470 | #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5471 | #define CAN_F7R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5472 | #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5473 | #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5474 | #define CAN_F7R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5475 | #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5476 | #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5477 | #define CAN_F7R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5478 | #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5479 | #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5480 | #define CAN_F7R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5481 | #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5482 | #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5483 | #define CAN_F7R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5484 | #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5485 | #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5486 | #define CAN_F7R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5487 | #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5488 | #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5489 | #define CAN_F7R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5490 | #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5491 | #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5492 | #define CAN_F7R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5493 | #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5494 | #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5495 | #define CAN_F7R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5496 | #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5497 | #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5498 | #define CAN_F7R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5499 | #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5500 | #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5501 | #define CAN_F7R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5502 | #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5503 | #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5504 | #define CAN_F7R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5505 | #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5506 | #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5507 | #define CAN_F7R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5508 | #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5509 | #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5510 | #define CAN_F7R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5511 | #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5512 | #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5513 | #define CAN_F7R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5514 | #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5515 | #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5516 | #define CAN_F7R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5517 | #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5518 | #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5519 | #define CAN_F7R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5520 | #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5521 | #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5522 | #define CAN_F7R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5523 | #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5524 | #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5525 | #define CAN_F7R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5526 | #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5527 | #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5528 | #define CAN_F7R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5529 | #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5530 | #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5531 | #define CAN_F7R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5532 | #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5533 | #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5534 | #define CAN_F7R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5535 | #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5536 | #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5537 | #define CAN_F7R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5538 | #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5539 | #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5540 | |
| AnnaBridge | 172:65be27845400 | 5541 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5542 | #define CAN_F8R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5543 | #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5544 | #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5545 | #define CAN_F8R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5546 | #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5547 | #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5548 | #define CAN_F8R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5549 | #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5550 | #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5551 | #define CAN_F8R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5552 | #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5553 | #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5554 | #define CAN_F8R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5555 | #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5556 | #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5557 | #define CAN_F8R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5558 | #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5559 | #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5560 | #define CAN_F8R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5561 | #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5562 | #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5563 | #define CAN_F8R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5564 | #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5565 | #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5566 | #define CAN_F8R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5567 | #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5568 | #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5569 | #define CAN_F8R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5570 | #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5571 | #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5572 | #define CAN_F8R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5573 | #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5574 | #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5575 | #define CAN_F8R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5576 | #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5577 | #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5578 | #define CAN_F8R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5579 | #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5580 | #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5581 | #define CAN_F8R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5582 | #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5583 | #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5584 | #define CAN_F8R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5585 | #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5586 | #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5587 | #define CAN_F8R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5588 | #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5589 | #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5590 | #define CAN_F8R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5591 | #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5592 | #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5593 | #define CAN_F8R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5594 | #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5595 | #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5596 | #define CAN_F8R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5597 | #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5598 | #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5599 | #define CAN_F8R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5600 | #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5601 | #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5602 | #define CAN_F8R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5603 | #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5604 | #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5605 | #define CAN_F8R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5606 | #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5607 | #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5608 | #define CAN_F8R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5609 | #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5610 | #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5611 | #define CAN_F8R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5612 | #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5613 | #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5614 | #define CAN_F8R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5615 | #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5616 | #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5617 | #define CAN_F8R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5618 | #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5619 | #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5620 | #define CAN_F8R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5621 | #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5622 | #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5623 | #define CAN_F8R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5624 | #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5625 | #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5626 | #define CAN_F8R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5627 | #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5628 | #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5629 | #define CAN_F8R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5630 | #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5631 | #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5632 | #define CAN_F8R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5633 | #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5634 | #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5635 | #define CAN_F8R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5636 | #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5637 | #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5638 | |
| AnnaBridge | 172:65be27845400 | 5639 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 5640 | #define CAN_F9R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5641 | #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5642 | #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5643 | #define CAN_F9R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5644 | #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5645 | #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5646 | #define CAN_F9R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5647 | #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5648 | #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5649 | #define CAN_F9R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5650 | #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5651 | #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5652 | #define CAN_F9R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5653 | #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5654 | #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5655 | #define CAN_F9R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5656 | #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5657 | #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5658 | #define CAN_F9R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5659 | #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5660 | #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5661 | #define CAN_F9R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5662 | #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5663 | #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5664 | #define CAN_F9R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5665 | #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5666 | #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5667 | #define CAN_F9R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5668 | #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5669 | #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5670 | #define CAN_F9R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5671 | #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5672 | #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5673 | #define CAN_F9R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5674 | #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5675 | #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5676 | #define CAN_F9R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5677 | #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5678 | #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5679 | #define CAN_F9R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5680 | #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5681 | #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5682 | #define CAN_F9R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5683 | #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5684 | #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5685 | #define CAN_F9R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5686 | #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5687 | #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5688 | #define CAN_F9R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5689 | #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5690 | #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5691 | #define CAN_F9R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5692 | #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5693 | #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5694 | #define CAN_F9R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5695 | #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5696 | #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5697 | #define CAN_F9R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5698 | #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5699 | #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5700 | #define CAN_F9R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5701 | #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5702 | #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5703 | #define CAN_F9R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5704 | #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5705 | #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5706 | #define CAN_F9R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5707 | #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5708 | #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5709 | #define CAN_F9R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5710 | #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5711 | #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5712 | #define CAN_F9R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5713 | #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5714 | #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5715 | #define CAN_F9R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5716 | #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5717 | #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5718 | #define CAN_F9R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5719 | #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5720 | #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5721 | #define CAN_F9R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5722 | #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5723 | #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5724 | #define CAN_F9R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5725 | #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5726 | #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5727 | #define CAN_F9R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5728 | #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5729 | #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5730 | #define CAN_F9R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5731 | #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5732 | #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5733 | #define CAN_F9R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5734 | #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5735 | #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5736 | |
| AnnaBridge | 172:65be27845400 | 5737 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 5738 | #define CAN_F10R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5739 | #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5740 | #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5741 | #define CAN_F10R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5742 | #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5743 | #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5744 | #define CAN_F10R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5745 | #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5746 | #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5747 | #define CAN_F10R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5748 | #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5749 | #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5750 | #define CAN_F10R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5751 | #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5752 | #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5753 | #define CAN_F10R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5754 | #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5755 | #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5756 | #define CAN_F10R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5757 | #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5758 | #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5759 | #define CAN_F10R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5760 | #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5761 | #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5762 | #define CAN_F10R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5763 | #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5764 | #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5765 | #define CAN_F10R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5766 | #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5767 | #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5768 | #define CAN_F10R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5769 | #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5770 | #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5771 | #define CAN_F10R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5772 | #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5773 | #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5774 | #define CAN_F10R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5775 | #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5776 | #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5777 | #define CAN_F10R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5778 | #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5779 | #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5780 | #define CAN_F10R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5781 | #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5782 | #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5783 | #define CAN_F10R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5784 | #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5785 | #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5786 | #define CAN_F10R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5787 | #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5788 | #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5789 | #define CAN_F10R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5790 | #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5791 | #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5792 | #define CAN_F10R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5793 | #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5794 | #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5795 | #define CAN_F10R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5796 | #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5797 | #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5798 | #define CAN_F10R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5799 | #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5800 | #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5801 | #define CAN_F10R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5802 | #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5803 | #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5804 | #define CAN_F10R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5805 | #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5806 | #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5807 | #define CAN_F10R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5808 | #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5809 | #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5810 | #define CAN_F10R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5811 | #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5812 | #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5813 | #define CAN_F10R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5814 | #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5815 | #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5816 | #define CAN_F10R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5817 | #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5818 | #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5819 | #define CAN_F10R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5820 | #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5821 | #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5822 | #define CAN_F10R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5823 | #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5824 | #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5825 | #define CAN_F10R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5826 | #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5827 | #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5828 | #define CAN_F10R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5829 | #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5830 | #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5831 | #define CAN_F10R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5832 | #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5833 | #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5834 | |
| AnnaBridge | 172:65be27845400 | 5835 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 5836 | #define CAN_F11R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5837 | #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5838 | #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5839 | #define CAN_F11R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5840 | #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5841 | #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5842 | #define CAN_F11R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5843 | #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5844 | #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5845 | #define CAN_F11R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5846 | #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5847 | #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5848 | #define CAN_F11R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5849 | #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5850 | #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5851 | #define CAN_F11R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5852 | #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5853 | #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5854 | #define CAN_F11R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5855 | #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5856 | #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5857 | #define CAN_F11R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5858 | #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5859 | #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5860 | #define CAN_F11R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5861 | #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5862 | #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5863 | #define CAN_F11R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5864 | #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5865 | #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5866 | #define CAN_F11R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5867 | #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5868 | #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5869 | #define CAN_F11R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5870 | #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5871 | #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5872 | #define CAN_F11R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5873 | #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5874 | #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5875 | #define CAN_F11R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5876 | #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5877 | #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5878 | #define CAN_F11R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5879 | #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5880 | #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5881 | #define CAN_F11R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5882 | #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5883 | #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5884 | #define CAN_F11R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5885 | #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5886 | #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5887 | #define CAN_F11R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5888 | #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5889 | #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5890 | #define CAN_F11R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5891 | #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5892 | #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5893 | #define CAN_F11R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5894 | #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5895 | #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5896 | #define CAN_F11R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5897 | #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5898 | #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5899 | #define CAN_F11R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5900 | #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5901 | #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 5902 | #define CAN_F11R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 5903 | #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 5904 | #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 5905 | #define CAN_F11R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 5906 | #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 5907 | #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 5908 | #define CAN_F11R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 5909 | #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 5910 | #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 5911 | #define CAN_F11R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 5912 | #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 5913 | #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 5914 | #define CAN_F11R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 5915 | #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 5916 | #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 5917 | #define CAN_F11R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 5918 | #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 5919 | #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 5920 | #define CAN_F11R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 5921 | #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 5922 | #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 5923 | #define CAN_F11R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 5924 | #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 5925 | #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 5926 | #define CAN_F11R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 5927 | #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 5928 | #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 5929 | #define CAN_F11R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 5930 | #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 5931 | #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 5932 | |
| AnnaBridge | 172:65be27845400 | 5933 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 5934 | #define CAN_F12R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 5935 | #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 5936 | #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 5937 | #define CAN_F12R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 5938 | #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 5939 | #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 5940 | #define CAN_F12R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 5941 | #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 5942 | #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 5943 | #define CAN_F12R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 5944 | #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 5945 | #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 5946 | #define CAN_F12R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 5947 | #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 5948 | #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 5949 | #define CAN_F12R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 5950 | #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 5951 | #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 5952 | #define CAN_F12R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 5953 | #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 5954 | #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 5955 | #define CAN_F12R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 5956 | #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 5957 | #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 5958 | #define CAN_F12R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 5959 | #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 5960 | #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 5961 | #define CAN_F12R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 5962 | #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 5963 | #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 5964 | #define CAN_F12R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 5965 | #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 5966 | #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 5967 | #define CAN_F12R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 5968 | #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 5969 | #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 5970 | #define CAN_F12R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 5971 | #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 5972 | #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 5973 | #define CAN_F12R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 5974 | #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 5975 | #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 5976 | #define CAN_F12R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 5977 | #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 5978 | #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 5979 | #define CAN_F12R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 5980 | #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 5981 | #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 5982 | #define CAN_F12R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 5983 | #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 5984 | #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 5985 | #define CAN_F12R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 5986 | #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 5987 | #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 5988 | #define CAN_F12R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 5989 | #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 5990 | #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 5991 | #define CAN_F12R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 5992 | #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 5993 | #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 5994 | #define CAN_F12R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 5995 | #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 5996 | #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 5997 | #define CAN_F12R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 5998 | #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 5999 | #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 6000 | #define CAN_F12R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 6001 | #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6002 | #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 6003 | #define CAN_F12R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 6004 | #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6005 | #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 6006 | #define CAN_F12R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6007 | #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6008 | #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 6009 | #define CAN_F12R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 6010 | #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6011 | #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 6012 | #define CAN_F12R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 6013 | #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6014 | #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 6015 | #define CAN_F12R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 6016 | #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6017 | #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 6018 | #define CAN_F12R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 6019 | #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6020 | #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 6021 | #define CAN_F12R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 6022 | #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6023 | #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 6024 | #define CAN_F12R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 6025 | #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6026 | #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 6027 | #define CAN_F12R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 6028 | #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6029 | #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 6030 | |
| AnnaBridge | 172:65be27845400 | 6031 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6032 | #define CAN_F13R2_FB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6033 | #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6034 | #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ |
| AnnaBridge | 172:65be27845400 | 6035 | #define CAN_F13R2_FB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6036 | #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6037 | #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ |
| AnnaBridge | 172:65be27845400 | 6038 | #define CAN_F13R2_FB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6039 | #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6040 | #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ |
| AnnaBridge | 172:65be27845400 | 6041 | #define CAN_F13R2_FB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6042 | #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6043 | #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ |
| AnnaBridge | 172:65be27845400 | 6044 | #define CAN_F13R2_FB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6045 | #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6046 | #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ |
| AnnaBridge | 172:65be27845400 | 6047 | #define CAN_F13R2_FB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 6048 | #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6049 | #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ |
| AnnaBridge | 172:65be27845400 | 6050 | #define CAN_F13R2_FB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 6051 | #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6052 | #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ |
| AnnaBridge | 172:65be27845400 | 6053 | #define CAN_F13R2_FB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 6054 | #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6055 | #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ |
| AnnaBridge | 172:65be27845400 | 6056 | #define CAN_F13R2_FB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6057 | #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6058 | #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ |
| AnnaBridge | 172:65be27845400 | 6059 | #define CAN_F13R2_FB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 6060 | #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6061 | #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ |
| AnnaBridge | 172:65be27845400 | 6062 | #define CAN_F13R2_FB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 6063 | #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6064 | #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ |
| AnnaBridge | 172:65be27845400 | 6065 | #define CAN_F13R2_FB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 6066 | #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6067 | #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ |
| AnnaBridge | 172:65be27845400 | 6068 | #define CAN_F13R2_FB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 6069 | #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6070 | #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ |
| AnnaBridge | 172:65be27845400 | 6071 | #define CAN_F13R2_FB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 6072 | #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6073 | #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ |
| AnnaBridge | 172:65be27845400 | 6074 | #define CAN_F13R2_FB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 6075 | #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6076 | #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ |
| AnnaBridge | 172:65be27845400 | 6077 | #define CAN_F13R2_FB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 6078 | #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6079 | #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ |
| AnnaBridge | 172:65be27845400 | 6080 | #define CAN_F13R2_FB16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6081 | #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6082 | #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ |
| AnnaBridge | 172:65be27845400 | 6083 | #define CAN_F13R2_FB17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 6084 | #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6085 | #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ |
| AnnaBridge | 172:65be27845400 | 6086 | #define CAN_F13R2_FB18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 6087 | #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6088 | #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ |
| AnnaBridge | 172:65be27845400 | 6089 | #define CAN_F13R2_FB19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 6090 | #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6091 | #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ |
| AnnaBridge | 172:65be27845400 | 6092 | #define CAN_F13R2_FB20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 6093 | #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6094 | #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ |
| AnnaBridge | 172:65be27845400 | 6095 | #define CAN_F13R2_FB21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 6096 | #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6097 | #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ |
| AnnaBridge | 172:65be27845400 | 6098 | #define CAN_F13R2_FB22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 6099 | #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6100 | #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ |
| AnnaBridge | 172:65be27845400 | 6101 | #define CAN_F13R2_FB23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 6102 | #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6103 | #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ |
| AnnaBridge | 172:65be27845400 | 6104 | #define CAN_F13R2_FB24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6105 | #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6106 | #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ |
| AnnaBridge | 172:65be27845400 | 6107 | #define CAN_F13R2_FB25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 6108 | #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6109 | #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ |
| AnnaBridge | 172:65be27845400 | 6110 | #define CAN_F13R2_FB26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 6111 | #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6112 | #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ |
| AnnaBridge | 172:65be27845400 | 6113 | #define CAN_F13R2_FB27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 6114 | #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6115 | #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ |
| AnnaBridge | 172:65be27845400 | 6116 | #define CAN_F13R2_FB28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 6117 | #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6118 | #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ |
| AnnaBridge | 172:65be27845400 | 6119 | #define CAN_F13R2_FB29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 6120 | #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6121 | #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ |
| AnnaBridge | 172:65be27845400 | 6122 | #define CAN_F13R2_FB30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 6123 | #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6124 | #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ |
| AnnaBridge | 172:65be27845400 | 6125 | #define CAN_F13R2_FB31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 6126 | #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6127 | #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ |
| AnnaBridge | 172:65be27845400 | 6128 | |
| AnnaBridge | 172:65be27845400 | 6129 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6130 | /* */ |
| AnnaBridge | 172:65be27845400 | 6131 | /* CRC calculation unit */ |
| AnnaBridge | 172:65be27845400 | 6132 | /* */ |
| AnnaBridge | 172:65be27845400 | 6133 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6134 | /******************* Bit definition for CRC_DR register *********************/ |
| AnnaBridge | 172:65be27845400 | 6135 | #define CRC_DR_DR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6136 | #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 6137 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| AnnaBridge | 172:65be27845400 | 6138 | |
| AnnaBridge | 172:65be27845400 | 6139 | /******************* Bit definition for CRC_IDR register ********************/ |
| AnnaBridge | 172:65be27845400 | 6140 | #define CRC_IDR_IDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6141 | #define CRC_IDR_IDR_Msk (0xFFFFFFFFU << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 6142 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */ |
| AnnaBridge | 172:65be27845400 | 6143 | |
| AnnaBridge | 172:65be27845400 | 6144 | /******************** Bit definition for CRC_CR register ********************/ |
| AnnaBridge | 172:65be27845400 | 6145 | #define CRC_CR_RESET_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6146 | #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6147 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ |
| AnnaBridge | 172:65be27845400 | 6148 | #define CRC_CR_POLYSIZE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6149 | #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 172:65be27845400 | 6150 | #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ |
| AnnaBridge | 172:65be27845400 | 6151 | #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6152 | #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6153 | #define CRC_CR_REV_IN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 6154 | #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 172:65be27845400 | 6155 | #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ |
| AnnaBridge | 172:65be27845400 | 6156 | #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6157 | #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6158 | #define CRC_CR_REV_OUT_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 6159 | #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6160 | #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ |
| AnnaBridge | 172:65be27845400 | 6161 | |
| AnnaBridge | 172:65be27845400 | 6162 | /******************* Bit definition for CRC_INIT register *******************/ |
| AnnaBridge | 172:65be27845400 | 6163 | #define CRC_INIT_INIT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6164 | #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 6165 | #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ |
| AnnaBridge | 172:65be27845400 | 6166 | |
| AnnaBridge | 172:65be27845400 | 6167 | /******************* Bit definition for CRC_POL register ********************/ |
| AnnaBridge | 172:65be27845400 | 6168 | #define CRC_POL_POL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6169 | #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 6170 | #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ |
| AnnaBridge | 172:65be27845400 | 6171 | |
| AnnaBridge | 172:65be27845400 | 6172 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6173 | /* */ |
| AnnaBridge | 172:65be27845400 | 6174 | /* CRS Clock Recovery System */ |
| AnnaBridge | 172:65be27845400 | 6175 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6176 | |
| AnnaBridge | 172:65be27845400 | 6177 | /******************* Bit definition for CRS_CR register *********************/ |
| AnnaBridge | 172:65be27845400 | 6178 | #define CRS_CR_SYNCOKIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6179 | #define CRS_CR_SYNCOKIE_Msk (0x1U << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6180 | #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6181 | #define CRS_CR_SYNCWARNIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6182 | #define CRS_CR_SYNCWARNIE_Msk (0x1U << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6183 | #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6184 | #define CRS_CR_ERRIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6185 | #define CRS_CR_ERRIE_Msk (0x1U << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6186 | #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6187 | #define CRS_CR_ESYNCIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6188 | #define CRS_CR_ESYNCIE_Msk (0x1U << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6189 | #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6190 | #define CRS_CR_CEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 6191 | #define CRS_CR_CEN_Msk (0x1U << CRS_CR_CEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6192 | #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ |
| AnnaBridge | 172:65be27845400 | 6193 | #define CRS_CR_AUTOTRIMEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 6194 | #define CRS_CR_AUTOTRIMEN_Msk (0x1U << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6195 | #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ |
| AnnaBridge | 172:65be27845400 | 6196 | #define CRS_CR_SWSYNC_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 6197 | #define CRS_CR_SWSYNC_Msk (0x1U << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6198 | #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ |
| AnnaBridge | 172:65be27845400 | 6199 | #define CRS_CR_TRIM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6200 | #define CRS_CR_TRIM_Msk (0x3FU << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ |
| AnnaBridge | 172:65be27845400 | 6201 | #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ |
| AnnaBridge | 172:65be27845400 | 6202 | |
| AnnaBridge | 172:65be27845400 | 6203 | /******************* Bit definition for CRS_CFGR register *********************/ |
| AnnaBridge | 172:65be27845400 | 6204 | #define CRS_CFGR_RELOAD_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6205 | #define CRS_CFGR_RELOAD_Msk (0xFFFFU << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 6206 | #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ |
| AnnaBridge | 172:65be27845400 | 6207 | #define CRS_CFGR_FELIM_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6208 | #define CRS_CFGR_FELIM_Msk (0xFFU << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6209 | #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ |
| AnnaBridge | 172:65be27845400 | 6210 | |
| AnnaBridge | 172:65be27845400 | 6211 | #define CRS_CFGR_SYNCDIV_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6212 | #define CRS_CFGR_SYNCDIV_Msk (0x7U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 6213 | #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ |
| AnnaBridge | 172:65be27845400 | 6214 | #define CRS_CFGR_SYNCDIV_0 (0x1U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6215 | #define CRS_CFGR_SYNCDIV_1 (0x2U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6216 | #define CRS_CFGR_SYNCDIV_2 (0x4U << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6217 | |
| AnnaBridge | 172:65be27845400 | 6218 | #define CRS_CFGR_SYNCSRC_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 6219 | #define CRS_CFGR_SYNCSRC_Msk (0x3U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 6220 | #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ |
| AnnaBridge | 172:65be27845400 | 6221 | #define CRS_CFGR_SYNCSRC_0 (0x1U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6222 | #define CRS_CFGR_SYNCSRC_1 (0x2U << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6223 | |
| AnnaBridge | 172:65be27845400 | 6224 | #define CRS_CFGR_SYNCPOL_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 6225 | #define CRS_CFGR_SYNCPOL_Msk (0x1U << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6226 | #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ |
| AnnaBridge | 172:65be27845400 | 6227 | |
| AnnaBridge | 172:65be27845400 | 6228 | /******************* Bit definition for CRS_ISR register *********************/ |
| AnnaBridge | 172:65be27845400 | 6229 | #define CRS_ISR_SYNCOKF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6230 | #define CRS_ISR_SYNCOKF_Msk (0x1U << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6231 | #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ |
| AnnaBridge | 172:65be27845400 | 6232 | #define CRS_ISR_SYNCWARNF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6233 | #define CRS_ISR_SYNCWARNF_Msk (0x1U << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6234 | #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ |
| AnnaBridge | 172:65be27845400 | 6235 | #define CRS_ISR_ERRF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6236 | #define CRS_ISR_ERRF_Msk (0x1U << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6237 | #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ |
| AnnaBridge | 172:65be27845400 | 6238 | #define CRS_ISR_ESYNCF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6239 | #define CRS_ISR_ESYNCF_Msk (0x1U << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6240 | #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ |
| AnnaBridge | 172:65be27845400 | 6241 | #define CRS_ISR_SYNCERR_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6242 | #define CRS_ISR_SYNCERR_Msk (0x1U << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6243 | #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ |
| AnnaBridge | 172:65be27845400 | 6244 | #define CRS_ISR_SYNCMISS_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 6245 | #define CRS_ISR_SYNCMISS_Msk (0x1U << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6246 | #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ |
| AnnaBridge | 172:65be27845400 | 6247 | #define CRS_ISR_TRIMOVF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 6248 | #define CRS_ISR_TRIMOVF_Msk (0x1U << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6249 | #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ |
| AnnaBridge | 172:65be27845400 | 6250 | #define CRS_ISR_FEDIR_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 6251 | #define CRS_ISR_FEDIR_Msk (0x1U << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6252 | #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ |
| AnnaBridge | 172:65be27845400 | 6253 | #define CRS_ISR_FECAP_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6254 | #define CRS_ISR_FECAP_Msk (0xFFFFU << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 6255 | #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ |
| AnnaBridge | 172:65be27845400 | 6256 | |
| AnnaBridge | 172:65be27845400 | 6257 | /******************* Bit definition for CRS_ICR register *********************/ |
| AnnaBridge | 172:65be27845400 | 6258 | #define CRS_ICR_SYNCOKC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6259 | #define CRS_ICR_SYNCOKC_Msk (0x1U << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6260 | #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ |
| AnnaBridge | 172:65be27845400 | 6261 | #define CRS_ICR_SYNCWARNC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6262 | #define CRS_ICR_SYNCWARNC_Msk (0x1U << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6263 | #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ |
| AnnaBridge | 172:65be27845400 | 6264 | #define CRS_ICR_ERRC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6265 | #define CRS_ICR_ERRC_Msk (0x1U << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6266 | #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ |
| AnnaBridge | 172:65be27845400 | 6267 | #define CRS_ICR_ESYNCC_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6268 | #define CRS_ICR_ESYNCC_Msk (0x1U << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6269 | #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ |
| AnnaBridge | 172:65be27845400 | 6270 | |
| AnnaBridge | 172:65be27845400 | 6271 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6272 | /* */ |
| AnnaBridge | 172:65be27845400 | 6273 | /* Digital to Analog Converter */ |
| AnnaBridge | 172:65be27845400 | 6274 | /* */ |
| AnnaBridge | 172:65be27845400 | 6275 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6276 | /* |
| AnnaBridge | 172:65be27845400 | 6277 | * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) |
| AnnaBridge | 172:65be27845400 | 6278 | */ |
| AnnaBridge | 172:65be27845400 | 6279 | #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ |
| AnnaBridge | 172:65be27845400 | 6280 | |
| AnnaBridge | 172:65be27845400 | 6281 | /******************** Bit definition for DAC_CR register ********************/ |
| AnnaBridge | 172:65be27845400 | 6282 | #define DAC_CR_EN1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6283 | #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6284 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ |
| AnnaBridge | 172:65be27845400 | 6285 | #define DAC_CR_TEN1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6286 | #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6287 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ |
| AnnaBridge | 172:65be27845400 | 6288 | |
| AnnaBridge | 172:65be27845400 | 6289 | #define DAC_CR_TSEL1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6290 | #define DAC_CR_TSEL1_Msk (0xFU << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */ |
| AnnaBridge | 172:65be27845400 | 6291 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */ |
| AnnaBridge | 172:65be27845400 | 6292 | #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6293 | #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6294 | #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6295 | #define DAC_CR_TSEL1_3 (0x8U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6296 | |
| AnnaBridge | 172:65be27845400 | 6297 | #define DAC_CR_WAVE1_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 6298 | #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 6299 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| AnnaBridge | 172:65be27845400 | 6300 | #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6301 | #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6302 | |
| AnnaBridge | 172:65be27845400 | 6303 | #define DAC_CR_MAMP1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6304 | #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 6305 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| AnnaBridge | 172:65be27845400 | 6306 | #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6307 | #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6308 | #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6309 | #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6310 | |
| AnnaBridge | 172:65be27845400 | 6311 | #define DAC_CR_DMAEN1_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 6312 | #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6313 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ |
| AnnaBridge | 172:65be27845400 | 6314 | #define DAC_CR_DMAUDRIE1_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 6315 | #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6316 | #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/ |
| AnnaBridge | 172:65be27845400 | 6317 | #define DAC_CR_CEN1_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 6318 | #define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6319 | #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/ |
| AnnaBridge | 172:65be27845400 | 6320 | |
| AnnaBridge | 172:65be27845400 | 6321 | #define DAC_CR_HFSEL_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 6322 | #define DAC_CR_HFSEL_Msk (0x1U << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6323 | #define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/ |
| AnnaBridge | 172:65be27845400 | 6324 | |
| AnnaBridge | 172:65be27845400 | 6325 | #define DAC_CR_EN2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6326 | #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6327 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ |
| AnnaBridge | 172:65be27845400 | 6328 | #define DAC_CR_TEN2_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 6329 | #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6330 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ |
| AnnaBridge | 172:65be27845400 | 6331 | |
| AnnaBridge | 172:65be27845400 | 6332 | #define DAC_CR_TSEL2_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 6333 | #define DAC_CR_TSEL2_Msk (0xFU << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */ |
| AnnaBridge | 172:65be27845400 | 6334 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */ |
| AnnaBridge | 172:65be27845400 | 6335 | #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6336 | #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6337 | #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6338 | #define DAC_CR_TSEL2_3 (0x8U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6339 | |
| AnnaBridge | 172:65be27845400 | 6340 | #define DAC_CR_WAVE2_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 6341 | #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 172:65be27845400 | 6342 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| AnnaBridge | 172:65be27845400 | 6343 | #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6344 | #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6345 | |
| AnnaBridge | 172:65be27845400 | 6346 | #define DAC_CR_MAMP2_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6347 | #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 6348 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| AnnaBridge | 172:65be27845400 | 6349 | #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6350 | #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6351 | #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6352 | #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6353 | |
| AnnaBridge | 172:65be27845400 | 6354 | #define DAC_CR_DMAEN2_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 6355 | #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6356 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ |
| AnnaBridge | 172:65be27845400 | 6357 | #define DAC_CR_DMAUDRIE2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 6358 | #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6359 | #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/ |
| AnnaBridge | 172:65be27845400 | 6360 | #define DAC_CR_CEN2_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 6361 | #define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6362 | #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/ |
| AnnaBridge | 172:65be27845400 | 6363 | |
| AnnaBridge | 172:65be27845400 | 6364 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| AnnaBridge | 172:65be27845400 | 6365 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6366 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6367 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ |
| AnnaBridge | 172:65be27845400 | 6368 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6369 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6370 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ |
| AnnaBridge | 172:65be27845400 | 6371 | |
| AnnaBridge | 172:65be27845400 | 6372 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6373 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6374 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 6375 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6376 | |
| AnnaBridge | 172:65be27845400 | 6377 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6378 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6379 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 172:65be27845400 | 6380 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ |
| AnnaBridge | 172:65be27845400 | 6381 | |
| AnnaBridge | 172:65be27845400 | 6382 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6383 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6384 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6385 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6386 | |
| AnnaBridge | 172:65be27845400 | 6387 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6388 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6389 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 6390 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6391 | |
| AnnaBridge | 172:65be27845400 | 6392 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6393 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6394 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 172:65be27845400 | 6395 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ |
| AnnaBridge | 172:65be27845400 | 6396 | |
| AnnaBridge | 172:65be27845400 | 6397 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6398 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6399 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6400 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6401 | |
| AnnaBridge | 172:65be27845400 | 6402 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| AnnaBridge | 172:65be27845400 | 6403 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6404 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 6405 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6406 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6407 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 172:65be27845400 | 6408 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6409 | |
| AnnaBridge | 172:65be27845400 | 6410 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| AnnaBridge | 172:65be27845400 | 6411 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6412 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 172:65be27845400 | 6413 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ |
| AnnaBridge | 172:65be27845400 | 6414 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 6415 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
| AnnaBridge | 172:65be27845400 | 6416 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ |
| AnnaBridge | 172:65be27845400 | 6417 | |
| AnnaBridge | 172:65be27845400 | 6418 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| AnnaBridge | 172:65be27845400 | 6419 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6420 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6421 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6422 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6423 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 6424 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ |
| AnnaBridge | 172:65be27845400 | 6425 | |
| AnnaBridge | 172:65be27845400 | 6426 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 6427 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6428 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 6429 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ |
| AnnaBridge | 172:65be27845400 | 6430 | |
| AnnaBridge | 172:65be27845400 | 6431 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 6432 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6433 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 6434 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ |
| AnnaBridge | 172:65be27845400 | 6435 | |
| AnnaBridge | 172:65be27845400 | 6436 | /******************** Bit definition for DAC_SR register ********************/ |
| AnnaBridge | 172:65be27845400 | 6437 | #define DAC_SR_DMAUDR1_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 6438 | #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6439 | #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ |
| AnnaBridge | 172:65be27845400 | 6440 | #define DAC_SR_CAL_FLAG1_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 6441 | #define DAC_SR_CAL_FLAG1_Msk (0x1U << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6442 | #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */ |
| AnnaBridge | 172:65be27845400 | 6443 | #define DAC_SR_BWST1_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 6444 | #define DAC_SR_BWST1_Msk (0x1U << DAC_SR_BWST1_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6445 | #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */ |
| AnnaBridge | 172:65be27845400 | 6446 | |
| AnnaBridge | 172:65be27845400 | 6447 | #define DAC_SR_DMAUDR2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 6448 | #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6449 | #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ |
| AnnaBridge | 172:65be27845400 | 6450 | #define DAC_SR_CAL_FLAG2_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 6451 | #define DAC_SR_CAL_FLAG2_Msk (0x1U << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6452 | #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */ |
| AnnaBridge | 172:65be27845400 | 6453 | #define DAC_SR_BWST2_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 6454 | #define DAC_SR_BWST2_Msk (0x1U << DAC_SR_BWST2_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6455 | #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */ |
| AnnaBridge | 172:65be27845400 | 6456 | |
| AnnaBridge | 172:65be27845400 | 6457 | /******************* Bit definition for DAC_CCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 6458 | #define DAC_CCR_OTRIM1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6459 | #define DAC_CCR_OTRIM1_Msk (0x1FU << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 6460 | #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */ |
| AnnaBridge | 172:65be27845400 | 6461 | #define DAC_CCR_OTRIM2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6462 | #define DAC_CCR_OTRIM2_Msk (0x1FU << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 172:65be27845400 | 6463 | #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */ |
| AnnaBridge | 172:65be27845400 | 6464 | |
| AnnaBridge | 172:65be27845400 | 6465 | /******************* Bit definition for DAC_MCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 6466 | #define DAC_MCR_MODE1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6467 | #define DAC_MCR_MODE1_Msk (0x7U << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 6468 | #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */ |
| AnnaBridge | 172:65be27845400 | 6469 | #define DAC_MCR_MODE1_0 (0x1U << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6470 | #define DAC_MCR_MODE1_1 (0x2U << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6471 | #define DAC_MCR_MODE1_2 (0x4U << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6472 | |
| AnnaBridge | 172:65be27845400 | 6473 | #define DAC_MCR_MODE2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6474 | #define DAC_MCR_MODE2_Msk (0x7U << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 6475 | #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */ |
| AnnaBridge | 172:65be27845400 | 6476 | #define DAC_MCR_MODE2_0 (0x1U << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6477 | #define DAC_MCR_MODE2_1 (0x2U << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6478 | #define DAC_MCR_MODE2_2 (0x4U << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6479 | |
| AnnaBridge | 172:65be27845400 | 6480 | /****************** Bit definition for DAC_SHSR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6481 | #define DAC_SHSR1_TSAMPLE1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6482 | #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 6483 | #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */ |
| AnnaBridge | 172:65be27845400 | 6484 | |
| AnnaBridge | 172:65be27845400 | 6485 | /****************** Bit definition for DAC_SHSR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6486 | #define DAC_SHSR2_TSAMPLE2_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6487 | #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 6488 | #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */ |
| AnnaBridge | 172:65be27845400 | 6489 | |
| AnnaBridge | 172:65be27845400 | 6490 | /****************** Bit definition for DAC_SHHR register ******************/ |
| AnnaBridge | 172:65be27845400 | 6491 | #define DAC_SHHR_THOLD1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6492 | #define DAC_SHHR_THOLD1_Msk (0x3FFU << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 6493 | #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */ |
| AnnaBridge | 172:65be27845400 | 6494 | #define DAC_SHHR_THOLD2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6495 | #define DAC_SHHR_THOLD2_Msk (0x3FFU << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6496 | #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */ |
| AnnaBridge | 172:65be27845400 | 6497 | |
| AnnaBridge | 172:65be27845400 | 6498 | /****************** Bit definition for DAC_SHRR register ******************/ |
| AnnaBridge | 172:65be27845400 | 6499 | #define DAC_SHRR_TREFRESH1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6500 | #define DAC_SHRR_TREFRESH1_Msk (0xFFU << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6501 | #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */ |
| AnnaBridge | 172:65be27845400 | 6502 | #define DAC_SHRR_TREFRESH2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6503 | #define DAC_SHRR_TREFRESH2_Msk (0xFFU << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6504 | #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */ |
| AnnaBridge | 172:65be27845400 | 6505 | |
| AnnaBridge | 172:65be27845400 | 6506 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6507 | /* */ |
| AnnaBridge | 172:65be27845400 | 6508 | /* DCMI */ |
| AnnaBridge | 172:65be27845400 | 6509 | /* */ |
| AnnaBridge | 172:65be27845400 | 6510 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6511 | /******************** Bits definition for DCMI_CR register ******************/ |
| AnnaBridge | 172:65be27845400 | 6512 | #define DCMI_CR_CAPTURE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6513 | #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6514 | #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk /*!< DCMI Capture enable */ |
| AnnaBridge | 172:65be27845400 | 6515 | #define DCMI_CR_CM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6516 | #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6517 | #define DCMI_CR_CM DCMI_CR_CM_Msk /*!< DCMI Capture mode */ |
| AnnaBridge | 172:65be27845400 | 6518 | #define DCMI_CR_CROP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6519 | #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6520 | #define DCMI_CR_CROP DCMI_CR_CROP_Msk /*!< DCMI Crop feature */ |
| AnnaBridge | 172:65be27845400 | 6521 | #define DCMI_CR_JPEG_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6522 | #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6523 | #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk /*!< DCMI JPEG format */ |
| AnnaBridge | 172:65be27845400 | 6524 | #define DCMI_CR_ESS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6525 | #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6526 | #define DCMI_CR_ESS DCMI_CR_ESS_Msk /*!< DCMI Embedded synchronization select */ |
| AnnaBridge | 172:65be27845400 | 6527 | #define DCMI_CR_PCKPOL_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 6528 | #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6529 | #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk /*!< DCMI Pixel clock polarity */ |
| AnnaBridge | 172:65be27845400 | 6530 | #define DCMI_CR_HSPOL_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 6531 | #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6532 | #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk /*!< DCMI Horizontal synchronization polarity */ |
| AnnaBridge | 172:65be27845400 | 6533 | #define DCMI_CR_VSPOL_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 6534 | #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6535 | #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk /*!< DCMI Vertical synchronization polarity */ |
| AnnaBridge | 172:65be27845400 | 6536 | #define DCMI_CR_FCRC_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6537 | #define DCMI_CR_FCRC_Msk (0x3U << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 6538 | #define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */ |
| AnnaBridge | 172:65be27845400 | 6539 | #define DCMI_CR_FCRC_0 (0x1U << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6540 | #define DCMI_CR_FCRC_1 (0x2U << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6541 | #define DCMI_CR_EDM_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 6542 | #define DCMI_CR_EDM_Msk (0x3U << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 6543 | #define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */ |
| AnnaBridge | 172:65be27845400 | 6544 | #define DCMI_CR_EDM_0 (0x1U << DCMI_CR_EDM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6545 | #define DCMI_CR_EDM_1 (0x2U << DCMI_CR_EDM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6546 | #define DCMI_CR_ENABLE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 6547 | #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6548 | #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk /*!< DCMI DCMI enable */ |
| AnnaBridge | 172:65be27845400 | 6549 | #define DCMI_CR_BSM_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6550 | #define DCMI_CR_BSM_Msk (0x3U << DCMI_CR_BSM_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 6551 | #define DCMI_CR_BSM DCMI_CR_BSM_Msk /*!< DCMI Byte Select mode BSM[1:0] */ |
| AnnaBridge | 172:65be27845400 | 6552 | #define DCMI_CR_BSM_0 (0x1U << DCMI_CR_BSM_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6553 | #define DCMI_CR_BSM_1 (0x2U << DCMI_CR_BSM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6554 | #define DCMI_CR_OEBS_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 6555 | #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6556 | #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk /*!< DCMI Odd/Even Byte Select (Byte Select Start) */ |
| AnnaBridge | 172:65be27845400 | 6557 | #define DCMI_CR_LSM_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 6558 | #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6559 | #define DCMI_CR_LSM DCMI_CR_LSM_Msk /*!< DCMI Line Select mode */ |
| AnnaBridge | 172:65be27845400 | 6560 | #define DCMI_CR_OELS_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 6561 | #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6562 | #define DCMI_CR_OELS DCMI_CR_OELS_Msk /*!< DCMI Odd/Even Line Select (Line Select Start) */ |
| AnnaBridge | 172:65be27845400 | 6563 | |
| AnnaBridge | 172:65be27845400 | 6564 | /******************** Bits definition for DCMI_SR register ******************/ |
| AnnaBridge | 172:65be27845400 | 6565 | #define DCMI_SR_HSYNC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6566 | #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6567 | #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk |
| AnnaBridge | 172:65be27845400 | 6568 | #define DCMI_SR_VSYNC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6569 | #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6570 | #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk |
| AnnaBridge | 172:65be27845400 | 6571 | #define DCMI_SR_FNE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6572 | #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6573 | #define DCMI_SR_FNE DCMI_SR_FNE_Msk /*!< DCMI FIFO not empty */ |
| AnnaBridge | 172:65be27845400 | 6574 | |
| AnnaBridge | 172:65be27845400 | 6575 | /******************** Bits definition for DCMI_RISR register ****************/ |
| AnnaBridge | 172:65be27845400 | 6576 | #define DCMI_RIS_FRAME_RIS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6577 | #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6578 | #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk /*!< DCMI Capture complete raw interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6579 | #define DCMI_RIS_OVR_RIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6580 | #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6581 | #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk /*!< DCMI Overrun raw interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6582 | #define DCMI_RIS_ERR_RIS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6583 | #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6584 | #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk /*!< DCMI Synchronization error raw interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6585 | #define DCMI_RIS_VSYNC_RIS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6586 | #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6587 | #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk /*!< DCMI VSYNC raw interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6588 | #define DCMI_RIS_LINE_RIS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6589 | #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6590 | #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /*!< DCMI Line raw interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6591 | |
| AnnaBridge | 172:65be27845400 | 6592 | /******************** Bits definition for DCMI_IER register *****************/ |
| AnnaBridge | 172:65be27845400 | 6593 | #define DCMI_IER_FRAME_IE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6594 | #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6595 | #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk /*!< DCMI Capture complete interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6596 | #define DCMI_IER_OVR_IE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6597 | #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6598 | #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk /*!< DCMI Overrun interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6599 | #define DCMI_IER_ERR_IE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6600 | #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6601 | #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk /*!< DCMI Synchronization error interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6602 | #define DCMI_IER_VSYNC_IE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6603 | #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6604 | #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk /*!< DCMI VSYNC interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6605 | #define DCMI_IER_LINE_IE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6606 | #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6607 | #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk /*!< DCMI Line interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 6608 | #define DCMI_IER_INT_IE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6609 | #define DCMI_IER_INT_IE_Msk (0x1FU << DCMI_IER_INT_IE_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 6610 | #define DCMI_IER_INT_IE DCMI_IER_INT_IE_Msk |
| AnnaBridge | 172:65be27845400 | 6611 | |
| AnnaBridge | 172:65be27845400 | 6612 | /******************** Bits definition for DCMI_MIS register *****************/ |
| AnnaBridge | 172:65be27845400 | 6613 | #define DCMI_MIS_FRAME_MIS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6614 | #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6615 | #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk /*!< DCMI Capture complete masked interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6616 | #define DCMI_MIS_OVR_MIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6617 | #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6618 | #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk /*!< DCMI Overrun masked interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6619 | #define DCMI_MIS_ERR_MIS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6620 | #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6621 | #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk /*!< DCMI Synchronization error masked interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6622 | #define DCMI_MIS_VSYNC_MIS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6623 | #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6624 | #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk /*!< DCMI VSYNC masked interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6625 | #define DCMI_MIS_LINE_MIS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6626 | #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6627 | #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk /*!< DCMI Line masked interrupt status */ |
| AnnaBridge | 172:65be27845400 | 6628 | |
| AnnaBridge | 172:65be27845400 | 6629 | /******************** Bits definition for DCMI_ICR register *****************/ |
| AnnaBridge | 172:65be27845400 | 6630 | #define DCMI_ICR_FRAME_ISC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6631 | #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6632 | #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk /*!< DCMI Capture complete interrupt status clear */ |
| AnnaBridge | 172:65be27845400 | 6633 | #define DCMI_ICR_OVR_ISC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6634 | #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6635 | #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk /*!< DCMI Overrun interrupt status clear */ |
| AnnaBridge | 172:65be27845400 | 6636 | #define DCMI_ICR_ERR_ISC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6637 | #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6638 | #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk /*!< DCMI Synchronization error interrupt status clear */ |
| AnnaBridge | 172:65be27845400 | 6639 | #define DCMI_ICR_VSYNC_ISC_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6640 | #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6641 | #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk /*!< DCMI Vertical synch interrupt status clear */ |
| AnnaBridge | 172:65be27845400 | 6642 | #define DCMI_ICR_LINE_ISC_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6643 | #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6644 | #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk /*!< DCMI line interrupt status clear */ |
| AnnaBridge | 172:65be27845400 | 6645 | |
| AnnaBridge | 172:65be27845400 | 6646 | /******************** Bits definition for DCMI_ESCR register ****************/ |
| AnnaBridge | 172:65be27845400 | 6647 | #define DCMI_ESCR_FSC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6648 | #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6649 | #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk /*!< DCMI Frame start delimiter code FSC[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6650 | #define DCMI_ESCR_FSC_0 (0x01U << DCMI_ESCR_FSC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6651 | #define DCMI_ESCR_FSC_1 (0x02U << DCMI_ESCR_FSC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6652 | #define DCMI_ESCR_FSC_2 (0x04U << DCMI_ESCR_FSC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6653 | #define DCMI_ESCR_FSC_3 (0x08U << DCMI_ESCR_FSC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6654 | #define DCMI_ESCR_FSC_4 (0x10U << DCMI_ESCR_FSC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6655 | #define DCMI_ESCR_FSC_5 (0x20U << DCMI_ESCR_FSC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6656 | #define DCMI_ESCR_FSC_6 (0x40U << DCMI_ESCR_FSC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6657 | #define DCMI_ESCR_FSC_7 (0x80U << DCMI_ESCR_FSC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6658 | #define DCMI_ESCR_LSC_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6659 | #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 6660 | #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk /*!< DCMI Line start delimiter code LSC[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6661 | #define DCMI_ESCR_LSC_0 (0x01U << DCMI_ESCR_LSC_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6662 | #define DCMI_ESCR_LSC_1 (0x02U << DCMI_ESCR_LSC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6663 | #define DCMI_ESCR_LSC_2 (0x04U << DCMI_ESCR_LSC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6664 | #define DCMI_ESCR_LSC_3 (0x08U << DCMI_ESCR_LSC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6665 | #define DCMI_ESCR_LSC_4 (0x10U << DCMI_ESCR_LSC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6666 | #define DCMI_ESCR_LSC_5 (0x20U << DCMI_ESCR_LSC_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6667 | #define DCMI_ESCR_LSC_6 (0x40U << DCMI_ESCR_LSC_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6668 | #define DCMI_ESCR_LSC_7 (0x80U << DCMI_ESCR_LSC_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6669 | #define DCMI_ESCR_LEC_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6670 | #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6671 | #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk /*!< DCMI Line end delimiter code LEC[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6672 | #define DCMI_ESCR_LEC_0 (0x01U << DCMI_ESCR_LEC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6673 | #define DCMI_ESCR_LEC_1 (0x02U << DCMI_ESCR_LEC_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6674 | #define DCMI_ESCR_LEC_2 (0x04U << DCMI_ESCR_LEC_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6675 | #define DCMI_ESCR_LEC_3 (0x08U << DCMI_ESCR_LEC_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6676 | #define DCMI_ESCR_LEC_4 (0x10U << DCMI_ESCR_LEC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6677 | #define DCMI_ESCR_LEC_5 (0x20U << DCMI_ESCR_LEC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6678 | #define DCMI_ESCR_LEC_6 (0x40U << DCMI_ESCR_LEC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6679 | #define DCMI_ESCR_LEC_7 (0x80U << DCMI_ESCR_LEC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6680 | #define DCMI_ESCR_FEC_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6681 | #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 6682 | #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk /*!< DCMI Frame end delimiter code FEC[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6683 | #define DCMI_ESCR_FEC_0 (0x01U << DCMI_ESCR_FEC_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6684 | #define DCMI_ESCR_FEC_1 (0x02U << DCMI_ESCR_FEC_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6685 | #define DCMI_ESCR_FEC_2 (0x04U << DCMI_ESCR_FEC_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6686 | #define DCMI_ESCR_FEC_3 (0x08U << DCMI_ESCR_FEC_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6687 | #define DCMI_ESCR_FEC_4 (0x10U << DCMI_ESCR_FEC_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6688 | #define DCMI_ESCR_FEC_5 (0x20U << DCMI_ESCR_FEC_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6689 | #define DCMI_ESCR_FEC_6 (0x40U << DCMI_ESCR_FEC_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6690 | #define DCMI_ESCR_FEC_7 (0x80U << DCMI_ESCR_FEC_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6691 | |
| AnnaBridge | 172:65be27845400 | 6692 | /******************** Bits definition for DCMI_ESUR register ****************/ |
| AnnaBridge | 172:65be27845400 | 6693 | #define DCMI_ESUR_FSU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6694 | #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6695 | #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk /*!< DCMI Frame start delimiter unmask FSU[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6696 | #define DCMI_ESUR_FSU_0 (0x01U << DCMI_ESUR_FSU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6697 | #define DCMI_ESUR_FSU_1 (0x02U << DCMI_ESUR_FSU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6698 | #define DCMI_ESUR_FSU_2 (0x04U << DCMI_ESUR_FSU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6699 | #define DCMI_ESUR_FSU_3 (0x08U << DCMI_ESUR_FSU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6700 | #define DCMI_ESUR_FSU_4 (0x10U << DCMI_ESUR_FSU_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6701 | #define DCMI_ESUR_FSU_5 (0x20U << DCMI_ESUR_FSU_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6702 | #define DCMI_ESUR_FSU_6 (0x40U << DCMI_ESUR_FSU_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6703 | #define DCMI_ESUR_FSU_7 (0x80U << DCMI_ESUR_FSU_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6704 | #define DCMI_ESUR_LSU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6705 | #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 6706 | #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk /*!< DCMI Line start delimiter unmask LSU[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6707 | #define DCMI_ESUR_LSU_0 (0x01U << DCMI_ESUR_LSU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6708 | #define DCMI_ESUR_LSU_1 (0x02U << DCMI_ESUR_LSU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6709 | #define DCMI_ESUR_LSU_2 (0x04U << DCMI_ESUR_LSU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6710 | #define DCMI_ESUR_LSU_3 (0x08U << DCMI_ESUR_LSU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6711 | #define DCMI_ESUR_LSU_4 (0x10U << DCMI_ESUR_LSU_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6712 | #define DCMI_ESUR_LSU_5 (0x20U << DCMI_ESUR_LSU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6713 | #define DCMI_ESUR_LSU_6 (0x40U << DCMI_ESUR_LSU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6714 | #define DCMI_ESUR_LSU_7 (0x80U << DCMI_ESUR_LSU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6715 | #define DCMI_ESUR_LEU_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6716 | #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6717 | #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk /*!< DCMI Line end delimiter unmask LEU[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6718 | #define DCMI_ESUR_LEU_0 (0x01U << DCMI_ESUR_LEU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6719 | #define DCMI_ESUR_LEU_1 (0x02U << DCMI_ESUR_LEU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6720 | #define DCMI_ESUR_LEU_2 (0x04U << DCMI_ESUR_LEU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6721 | #define DCMI_ESUR_LEU_3 (0x08U << DCMI_ESUR_LEU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6722 | #define DCMI_ESUR_LEU_4 (0x10U << DCMI_ESUR_LEU_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6723 | #define DCMI_ESUR_LEU_5 (0x20U << DCMI_ESUR_LEU_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6724 | #define DCMI_ESUR_LEU_6 (0x40U << DCMI_ESUR_LEU_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6725 | #define DCMI_ESUR_LEU_7 (0x80U << DCMI_ESUR_LEU_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6726 | #define DCMI_ESUR_FEU_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6727 | #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 6728 | #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk /*!< DCMI Frame end delimiter unmask FEU[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6729 | #define DCMI_ESUR_FEU_0 (0x01U << DCMI_ESUR_FEU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6730 | #define DCMI_ESUR_FEU_1 (0x02U << DCMI_ESUR_FEU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6731 | #define DCMI_ESUR_FEU_2 (0x04U << DCMI_ESUR_FEU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6732 | #define DCMI_ESUR_FEU_3 (0x08U << DCMI_ESUR_FEU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6733 | #define DCMI_ESUR_FEU_4 (0x10U << DCMI_ESUR_FEU_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6734 | #define DCMI_ESUR_FEU_5 (0x20U << DCMI_ESUR_FEU_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6735 | #define DCMI_ESUR_FEU_6 (0x40U << DCMI_ESUR_FEU_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6736 | #define DCMI_ESUR_FEU_7 (0x80U << DCMI_ESUR_FEU_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6737 | |
| AnnaBridge | 172:65be27845400 | 6738 | /******************** Bits definition for DCMI_CWSTRT register **************/ |
| AnnaBridge | 172:65be27845400 | 6739 | #define DCMI_CWSTRT_HOFFCNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6740 | #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 6741 | #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk /*!< DCMI Horizontal offset count HOFFCNT[13:0] */ |
| AnnaBridge | 172:65be27845400 | 6742 | #define DCMI_CWSTRT_HOFFCNT_0 (0x0001U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6743 | #define DCMI_CWSTRT_HOFFCNT_1 (0x0002U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6744 | #define DCMI_CWSTRT_HOFFCNT_2 (0x0004U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6745 | #define DCMI_CWSTRT_HOFFCNT_3 (0x0008U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6746 | #define DCMI_CWSTRT_HOFFCNT_4 (0x0010U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6747 | #define DCMI_CWSTRT_HOFFCNT_5 (0x0020U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6748 | #define DCMI_CWSTRT_HOFFCNT_6 (0x0040U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6749 | #define DCMI_CWSTRT_HOFFCNT_7 (0x0080U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6750 | #define DCMI_CWSTRT_HOFFCNT_8 (0x0100U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6751 | #define DCMI_CWSTRT_HOFFCNT_9 (0x0200U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6752 | #define DCMI_CWSTRT_HOFFCNT_10 (0x0400U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6753 | #define DCMI_CWSTRT_HOFFCNT_11 (0x0800U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6754 | #define DCMI_CWSTRT_HOFFCNT_12 (0x1000U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6755 | #define DCMI_CWSTRT_HOFFCNT_13 (0x2000U << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6756 | #define DCMI_CWSTRT_VST_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6757 | #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ |
| AnnaBridge | 172:65be27845400 | 6758 | #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk /*!< DCMI Vertical start line count VST[12:0] */ |
| AnnaBridge | 172:65be27845400 | 6759 | #define DCMI_CWSTRT_VST_0 (0x0001U << DCMI_CWSTRT_VST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6760 | #define DCMI_CWSTRT_VST_1 (0x0002U << DCMI_CWSTRT_VST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6761 | #define DCMI_CWSTRT_VST_2 (0x0004U << DCMI_CWSTRT_VST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6762 | #define DCMI_CWSTRT_VST_3 (0x0008U << DCMI_CWSTRT_VST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6763 | #define DCMI_CWSTRT_VST_4 (0x0010U << DCMI_CWSTRT_VST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6764 | #define DCMI_CWSTRT_VST_5 (0x0020U << DCMI_CWSTRT_VST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6765 | #define DCMI_CWSTRT_VST_6 (0x0040U << DCMI_CWSTRT_VST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6766 | #define DCMI_CWSTRT_VST_7 (0x0080U << DCMI_CWSTRT_VST_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6767 | #define DCMI_CWSTRT_VST_8 (0x0100U << DCMI_CWSTRT_VST_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6768 | #define DCMI_CWSTRT_VST_9 (0x0200U << DCMI_CWSTRT_VST_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6769 | #define DCMI_CWSTRT_VST_10 (0x0400U << DCMI_CWSTRT_VST_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6770 | #define DCMI_CWSTRT_VST_11 (0x0800U << DCMI_CWSTRT_VST_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6771 | #define DCMI_CWSTRT_VST_12 (0x1000U << DCMI_CWSTRT_VST_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6772 | |
| AnnaBridge | 172:65be27845400 | 6773 | /******************** Bits definition for DCMI_CWSIZE register **************/ |
| AnnaBridge | 172:65be27845400 | 6774 | #define DCMI_CWSIZE_CAPCNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6775 | #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 6776 | #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk /*!< DCMI Capture count CAPCNT[13:0] */ |
| AnnaBridge | 172:65be27845400 | 6777 | #define DCMI_CWSIZE_CAPCNT_0 (0x0001U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6778 | #define DCMI_CWSIZE_CAPCNT_1 (0x0002U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6779 | #define DCMI_CWSIZE_CAPCNT_2 (0x0004U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6780 | #define DCMI_CWSIZE_CAPCNT_3 (0x0008U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6781 | #define DCMI_CWSIZE_CAPCNT_4 (0x0010U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6782 | #define DCMI_CWSIZE_CAPCNT_5 (0x0020U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6783 | #define DCMI_CWSIZE_CAPCNT_6 (0x0040U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6784 | #define DCMI_CWSIZE_CAPCNT_7 (0x0080U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6785 | #define DCMI_CWSIZE_CAPCNT_8 (0x0100U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6786 | #define DCMI_CWSIZE_CAPCNT_9 (0x0200U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6787 | #define DCMI_CWSIZE_CAPCNT_10 (0x0400U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6788 | #define DCMI_CWSIZE_CAPCNT_11 (0x0800U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6789 | #define DCMI_CWSIZE_CAPCNT_12 (0x1000U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6790 | #define DCMI_CWSIZE_CAPCNT_13 (0x2000U << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6791 | #define DCMI_CWSIZE_VLINE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6792 | #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ |
| AnnaBridge | 172:65be27845400 | 6793 | #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk /*!< DCMI Vertical line count VLINE[13:0] */ |
| AnnaBridge | 172:65be27845400 | 6794 | #define DCMI_CWSIZE_VLINE_0 (0x0001U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6795 | #define DCMI_CWSIZE_VLINE_1 (0x0002U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6796 | #define DCMI_CWSIZE_VLINE_2 (0x0004U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6797 | #define DCMI_CWSIZE_VLINE_3 (0x0008U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6798 | #define DCMI_CWSIZE_VLINE_4 (0x0010U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6799 | #define DCMI_CWSIZE_VLINE_5 (0x0020U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6800 | #define DCMI_CWSIZE_VLINE_6 (0x0040U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6801 | #define DCMI_CWSIZE_VLINE_7 (0x0080U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6802 | #define DCMI_CWSIZE_VLINE_8 (0x0100U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6803 | #define DCMI_CWSIZE_VLINE_9 (0x0200U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6804 | #define DCMI_CWSIZE_VLINE_10 (0x0400U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6805 | #define DCMI_CWSIZE_VLINE_11 (0x0800U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6806 | #define DCMI_CWSIZE_VLINE_12 (0x1000U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6807 | #define DCMI_CWSIZE_VLINE_13 (0x2000U << DCMI_CWSIZE_VLINE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6808 | |
| AnnaBridge | 172:65be27845400 | 6809 | /******************** Bits definition for DCMI_DR register **************/ |
| AnnaBridge | 172:65be27845400 | 6810 | #define DCMI_DR_BYTE0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6811 | #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6812 | #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk /*!< DCMI Data byte 0 Byte0[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6813 | #define DCMI_DR_BYTE0_0 (0x01U << DCMI_DR_BYTE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6814 | #define DCMI_DR_BYTE0_1 (0x02U << DCMI_DR_BYTE0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6815 | #define DCMI_DR_BYTE0_2 (0x04U << DCMI_DR_BYTE0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6816 | #define DCMI_DR_BYTE0_3 (0x08U << DCMI_DR_BYTE0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6817 | #define DCMI_DR_BYTE0_4 (0x10U << DCMI_DR_BYTE0_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6818 | #define DCMI_DR_BYTE0_5 (0x20U << DCMI_DR_BYTE0_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6819 | #define DCMI_DR_BYTE0_6 (0x40U << DCMI_DR_BYTE0_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6820 | #define DCMI_DR_BYTE0_7 (0x80U << DCMI_DR_BYTE0_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6821 | #define DCMI_DR_BYTE1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6822 | #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 6823 | #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk /*!< DCMI Data byte 1 Byte1[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6824 | #define DCMI_DR_BYTE1_0 (0x01U << DCMI_DR_BYTE1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6825 | #define DCMI_DR_BYTE1_1 (0x02U << DCMI_DR_BYTE1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6826 | #define DCMI_DR_BYTE1_2 (0x04U << DCMI_DR_BYTE1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6827 | #define DCMI_DR_BYTE1_3 (0x08U << DCMI_DR_BYTE1_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6828 | #define DCMI_DR_BYTE1_4 (0x10U << DCMI_DR_BYTE1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6829 | #define DCMI_DR_BYTE1_5 (0x20U << DCMI_DR_BYTE1_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6830 | #define DCMI_DR_BYTE1_6 (0x40U << DCMI_DR_BYTE1_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6831 | #define DCMI_DR_BYTE1_7 (0x80U << DCMI_DR_BYTE1_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6832 | #define DCMI_DR_BYTE2_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6833 | #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6834 | #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk /*!< DCMI Data byte 2 Byte2[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6835 | #define DCMI_DR_BYTE2_0 (0x01U << DCMI_DR_BYTE2_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 6836 | #define DCMI_DR_BYTE2_1 (0x02U << DCMI_DR_BYTE2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6837 | #define DCMI_DR_BYTE2_2 (0x04U << DCMI_DR_BYTE2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6838 | #define DCMI_DR_BYTE2_3 (0x08U << DCMI_DR_BYTE2_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6839 | #define DCMI_DR_BYTE2_4 (0x10U << DCMI_DR_BYTE2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 6840 | #define DCMI_DR_BYTE2_5 (0x20U << DCMI_DR_BYTE2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6841 | #define DCMI_DR_BYTE2_6 (0x40U << DCMI_DR_BYTE2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6842 | #define DCMI_DR_BYTE2_7 (0x80U << DCMI_DR_BYTE2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6843 | #define DCMI_DR_BYTE3_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6844 | #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 6845 | #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk /*!< DCMI Data byte 3 Byte3[7:0] */ |
| AnnaBridge | 172:65be27845400 | 6846 | #define DCMI_DR_BYTE3_0 (0x01U << DCMI_DR_BYTE3_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 6847 | #define DCMI_DR_BYTE3_1 (0x02U << DCMI_DR_BYTE3_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 6848 | #define DCMI_DR_BYTE3_2 (0x04U << DCMI_DR_BYTE3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 6849 | #define DCMI_DR_BYTE3_3 (0x08U << DCMI_DR_BYTE3_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 6850 | #define DCMI_DR_BYTE3_4 (0x10U << DCMI_DR_BYTE3_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 6851 | #define DCMI_DR_BYTE3_5 (0x20U << DCMI_DR_BYTE3_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6852 | #define DCMI_DR_BYTE3_6 (0x40U << DCMI_DR_BYTE3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6853 | #define DCMI_DR_BYTE3_7 (0x80U << DCMI_DR_BYTE3_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6854 | |
| AnnaBridge | 172:65be27845400 | 6855 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6856 | /* */ |
| AnnaBridge | 172:65be27845400 | 6857 | /* Digital Filter for Sigma Delta Modulators */ |
| AnnaBridge | 172:65be27845400 | 6858 | /* */ |
| AnnaBridge | 172:65be27845400 | 6859 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 6860 | |
| AnnaBridge | 172:65be27845400 | 6861 | /**************** DFSDM channel configuration registers ********************/ |
| AnnaBridge | 172:65be27845400 | 6862 | |
| AnnaBridge | 172:65be27845400 | 6863 | /*************** Bit definition for DFSDM_CHCFGR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6864 | #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 6865 | #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 6866 | #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */ |
| AnnaBridge | 172:65be27845400 | 6867 | #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 6868 | #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6869 | #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */ |
| AnnaBridge | 172:65be27845400 | 6870 | #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6871 | #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 6872 | #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */ |
| AnnaBridge | 172:65be27845400 | 6873 | #define DFSDM_CHCFGR1_DATPACK_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 6874 | #define DFSDM_CHCFGR1_DATPACK_Msk (0x3U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 6875 | #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */ |
| AnnaBridge | 172:65be27845400 | 6876 | #define DFSDM_CHCFGR1_DATPACK_1 (0x2U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 6877 | #define DFSDM_CHCFGR1_DATPACK_0 (0x1U << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6878 | #define DFSDM_CHCFGR1_DATMPX_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 6879 | #define DFSDM_CHCFGR1_DATMPX_Msk (0x3U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 6880 | #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */ |
| AnnaBridge | 172:65be27845400 | 6881 | #define DFSDM_CHCFGR1_DATMPX_1 (0x2U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6882 | #define DFSDM_CHCFGR1_DATMPX_0 (0x1U << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6883 | #define DFSDM_CHCFGR1_CHINSEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6884 | #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6885 | #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */ |
| AnnaBridge | 172:65be27845400 | 6886 | #define DFSDM_CHCFGR1_CHEN_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 6887 | #define DFSDM_CHCFGR1_CHEN_Msk (0x1U << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 6888 | #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */ |
| AnnaBridge | 172:65be27845400 | 6889 | #define DFSDM_CHCFGR1_CKABEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 6890 | #define DFSDM_CHCFGR1_CKABEN_Msk (0x1U << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 6891 | #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */ |
| AnnaBridge | 172:65be27845400 | 6892 | #define DFSDM_CHCFGR1_SCDEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 6893 | #define DFSDM_CHCFGR1_SCDEN_Msk (0x1U << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6894 | #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */ |
| AnnaBridge | 172:65be27845400 | 6895 | #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 6896 | #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 6897 | #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */ |
| AnnaBridge | 172:65be27845400 | 6898 | #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6899 | #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 6900 | #define DFSDM_CHCFGR1_SITP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6901 | #define DFSDM_CHCFGR1_SITP_Msk (0x3U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 6902 | #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */ |
| AnnaBridge | 172:65be27845400 | 6903 | #define DFSDM_CHCFGR1_SITP_1 (0x2U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6904 | #define DFSDM_CHCFGR1_SITP_0 (0x1U << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6905 | |
| AnnaBridge | 172:65be27845400 | 6906 | /*************** Bit definition for DFSDM_CHCFGR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 6907 | #define DFSDM_CHCFGR2_OFFSET_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6908 | #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 6909 | #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */ |
| AnnaBridge | 172:65be27845400 | 6910 | #define DFSDM_CHCFGR2_DTRBS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6911 | #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */ |
| AnnaBridge | 172:65be27845400 | 6912 | #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */ |
| AnnaBridge | 172:65be27845400 | 6913 | |
| AnnaBridge | 172:65be27845400 | 6914 | /**************** Bit definition for DFSDM_CHAWSCDR register *****************/ |
| AnnaBridge | 172:65be27845400 | 6915 | #define DFSDM_CHAWSCDR_AWFORD_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 6916 | #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 172:65be27845400 | 6917 | #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */ |
| AnnaBridge | 172:65be27845400 | 6918 | #define DFSDM_CHAWSCDR_AWFORD_1 (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 6919 | #define DFSDM_CHAWSCDR_AWFORD_0 (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 6920 | #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6921 | #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 172:65be27845400 | 6922 | #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */ |
| AnnaBridge | 172:65be27845400 | 6923 | #define DFSDM_CHAWSCDR_BKSCD_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 6924 | #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 6925 | #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */ |
| AnnaBridge | 172:65be27845400 | 6926 | #define DFSDM_CHAWSCDR_SCDT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6927 | #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 6928 | #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */ |
| AnnaBridge | 172:65be27845400 | 6929 | |
| AnnaBridge | 172:65be27845400 | 6930 | /**************** Bit definition for DFSDM_CHWDATR register *******************/ |
| AnnaBridge | 172:65be27845400 | 6931 | #define DFSDM_CHWDATR_WDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6932 | #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 6933 | #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */ |
| AnnaBridge | 172:65be27845400 | 6934 | |
| AnnaBridge | 172:65be27845400 | 6935 | /**************** Bit definition for DFSDM_CHDATINR register *****************/ |
| AnnaBridge | 172:65be27845400 | 6936 | #define DFSDM_CHDATINR_INDAT0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6937 | #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 6938 | #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */ |
| AnnaBridge | 172:65be27845400 | 6939 | #define DFSDM_CHDATINR_INDAT1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 6940 | #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 6941 | #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */ |
| AnnaBridge | 172:65be27845400 | 6942 | |
| AnnaBridge | 172:65be27845400 | 6943 | /**************** Bit definition for DFSDM_CHDLYR register *******************/ |
| AnnaBridge | 172:65be27845400 | 6944 | #define DFSDM_CHDLYR_PLSSKP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6945 | #define DFSDM_CHDLYR_PLSSKP_Msk (0x3FU << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 172:65be27845400 | 6946 | #define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk /*!< PLSSKP[5:0] Number of input serial samples that will be skipped */ |
| AnnaBridge | 172:65be27845400 | 6947 | |
| AnnaBridge | 172:65be27845400 | 6948 | /************************ DFSDM module registers ****************************/ |
| AnnaBridge | 172:65be27845400 | 6949 | |
| AnnaBridge | 172:65be27845400 | 6950 | /***************** Bit definition for DFSDM_FLTCR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 6951 | #define DFSDM_FLTCR1_AWFSEL_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 6952 | #define DFSDM_FLTCR1_AWFSEL_Msk (0x1U << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 6953 | #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */ |
| AnnaBridge | 172:65be27845400 | 6954 | #define DFSDM_FLTCR1_FAST_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 6955 | #define DFSDM_FLTCR1_FAST_Msk (0x1U << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 6956 | #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */ |
| AnnaBridge | 172:65be27845400 | 6957 | #define DFSDM_FLTCR1_RCH_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 6958 | #define DFSDM_FLTCR1_RCH_Msk (0x7U << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 6959 | #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */ |
| AnnaBridge | 172:65be27845400 | 6960 | #define DFSDM_FLTCR1_RDMAEN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 6961 | #define DFSDM_FLTCR1_RDMAEN_Msk (0x1U << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 6962 | #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */ |
| AnnaBridge | 172:65be27845400 | 6963 | #define DFSDM_FLTCR1_RSYNC_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 6964 | #define DFSDM_FLTCR1_RSYNC_Msk (0x1U << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 6965 | #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */ |
| AnnaBridge | 172:65be27845400 | 6966 | #define DFSDM_FLTCR1_RCONT_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 6967 | #define DFSDM_FLTCR1_RCONT_Msk (0x1U << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 6968 | #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */ |
| AnnaBridge | 172:65be27845400 | 6969 | #define DFSDM_FLTCR1_RSWSTART_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 6970 | #define DFSDM_FLTCR1_RSWSTART_Msk (0x1U << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 6971 | #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */ |
| AnnaBridge | 172:65be27845400 | 6972 | #define DFSDM_FLTCR1_JEXTEN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 6973 | #define DFSDM_FLTCR1_JEXTEN_Msk (0x3U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 172:65be27845400 | 6974 | #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */ |
| AnnaBridge | 172:65be27845400 | 6975 | #define DFSDM_FLTCR1_JEXTEN_1 (0x2U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 6976 | #define DFSDM_FLTCR1_JEXTEN_0 (0x1U << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 6977 | #define DFSDM_FLTCR1_JEXTSEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 6978 | #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FU << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 6979 | #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */ |
| AnnaBridge | 172:65be27845400 | 6980 | #define DFSDM_FLTCR1_JEXTSEL_4 (0x10U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 6981 | #define DFSDM_FLTCR1_JEXTSEL_3 (0x08U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 6982 | #define DFSDM_FLTCR1_JEXTSEL_2 (0x04U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 6983 | #define DFSDM_FLTCR1_JEXTSEL_1 (0x02U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 6984 | #define DFSDM_FLTCR1_JEXTSEL_0 (0x01U << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 6985 | #define DFSDM_FLTCR1_JDMAEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 6986 | #define DFSDM_FLTCR1_JDMAEN_Msk (0x1U << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 6987 | #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */ |
| AnnaBridge | 172:65be27845400 | 6988 | #define DFSDM_FLTCR1_JSCAN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 6989 | #define DFSDM_FLTCR1_JSCAN_Msk (0x1U << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 6990 | #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */ |
| AnnaBridge | 172:65be27845400 | 6991 | #define DFSDM_FLTCR1_JSYNC_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 6992 | #define DFSDM_FLTCR1_JSYNC_Msk (0x1U << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 6993 | #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */ |
| AnnaBridge | 172:65be27845400 | 6994 | #define DFSDM_FLTCR1_JSWSTART_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 6995 | #define DFSDM_FLTCR1_JSWSTART_Msk (0x1U << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 6996 | #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */ |
| AnnaBridge | 172:65be27845400 | 6997 | #define DFSDM_FLTCR1_DFEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 6998 | #define DFSDM_FLTCR1_DFEN_Msk (0x1U << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 6999 | #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */ |
| AnnaBridge | 172:65be27845400 | 7000 | |
| AnnaBridge | 172:65be27845400 | 7001 | /***************** Bit definition for DFSDM_FLTCR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 7002 | #define DFSDM_FLTCR2_AWDCH_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7003 | #define DFSDM_FLTCR2_AWDCH_Msk (0xFFU << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 7004 | #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */ |
| AnnaBridge | 172:65be27845400 | 7005 | #define DFSDM_FLTCR2_EXCH_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7006 | #define DFSDM_FLTCR2_EXCH_Msk (0xFFU << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7007 | #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */ |
| AnnaBridge | 172:65be27845400 | 7008 | #define DFSDM_FLTCR2_CKABIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7009 | #define DFSDM_FLTCR2_CKABIE_Msk (0x1U << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7010 | #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7011 | #define DFSDM_FLTCR2_SCDIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7012 | #define DFSDM_FLTCR2_SCDIE_Msk (0x1U << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7013 | #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7014 | #define DFSDM_FLTCR2_AWDIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7015 | #define DFSDM_FLTCR2_AWDIE_Msk (0x1U << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7016 | #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7017 | #define DFSDM_FLTCR2_ROVRIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7018 | #define DFSDM_FLTCR2_ROVRIE_Msk (0x1U << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7019 | #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7020 | #define DFSDM_FLTCR2_JOVRIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7021 | #define DFSDM_FLTCR2_JOVRIE_Msk (0x1U << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7022 | #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7023 | #define DFSDM_FLTCR2_REOCIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7024 | #define DFSDM_FLTCR2_REOCIE_Msk (0x1U << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7025 | #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7026 | #define DFSDM_FLTCR2_JEOCIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7027 | #define DFSDM_FLTCR2_JEOCIE_Msk (0x1U << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7028 | #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7029 | |
| AnnaBridge | 172:65be27845400 | 7030 | /***************** Bit definition for DFSDM_FLTISR register *******************/ |
| AnnaBridge | 172:65be27845400 | 7031 | #define DFSDM_FLTISR_SCDF_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7032 | #define DFSDM_FLTISR_SCDF_Msk (0xFFU << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 7033 | #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */ |
| AnnaBridge | 172:65be27845400 | 7034 | #define DFSDM_FLTISR_CKABF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7035 | #define DFSDM_FLTISR_CKABF_Msk (0xFFU << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 7036 | #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */ |
| AnnaBridge | 172:65be27845400 | 7037 | #define DFSDM_FLTISR_RCIP_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 7038 | #define DFSDM_FLTISR_RCIP_Msk (0x1U << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 7039 | #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */ |
| AnnaBridge | 172:65be27845400 | 7040 | #define DFSDM_FLTISR_JCIP_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7041 | #define DFSDM_FLTISR_JCIP_Msk (0x1U << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7042 | #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */ |
| AnnaBridge | 172:65be27845400 | 7043 | #define DFSDM_FLTISR_AWDF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7044 | #define DFSDM_FLTISR_AWDF_Msk (0x1U << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7045 | #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */ |
| AnnaBridge | 172:65be27845400 | 7046 | #define DFSDM_FLTISR_ROVRF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7047 | #define DFSDM_FLTISR_ROVRF_Msk (0x1U << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7048 | #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */ |
| AnnaBridge | 172:65be27845400 | 7049 | #define DFSDM_FLTISR_JOVRF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7050 | #define DFSDM_FLTISR_JOVRF_Msk (0x1U << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7051 | #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */ |
| AnnaBridge | 172:65be27845400 | 7052 | #define DFSDM_FLTISR_REOCF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7053 | #define DFSDM_FLTISR_REOCF_Msk (0x1U << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7054 | #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */ |
| AnnaBridge | 172:65be27845400 | 7055 | #define DFSDM_FLTISR_JEOCF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7056 | #define DFSDM_FLTISR_JEOCF_Msk (0x1U << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7057 | #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */ |
| AnnaBridge | 172:65be27845400 | 7058 | |
| AnnaBridge | 172:65be27845400 | 7059 | /***************** Bit definition for DFSDM_FLTICR register *******************/ |
| AnnaBridge | 172:65be27845400 | 7060 | #define DFSDM_FLTICR_CLRSCSDF_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7061 | #define DFSDM_FLTICR_CLRSCSDF_Msk (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 7062 | #define DFSDM_FLTICR_CLRSCSDF DFSDM_FLTICR_CLRSCSDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */ |
| AnnaBridge | 172:65be27845400 | 7063 | #define DFSDM_FLTICR_CLRCKABF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7064 | #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 7065 | #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */ |
| AnnaBridge | 172:65be27845400 | 7066 | #define DFSDM_FLTICR_CLRROVRF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7067 | #define DFSDM_FLTICR_CLRROVRF_Msk (0x1U << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7068 | #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */ |
| AnnaBridge | 172:65be27845400 | 7069 | #define DFSDM_FLTICR_CLRJOVRF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7070 | #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7071 | #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */ |
| AnnaBridge | 172:65be27845400 | 7072 | |
| AnnaBridge | 172:65be27845400 | 7073 | /**************** Bit definition for DFSDM_FLTJCHGR register ******************/ |
| AnnaBridge | 172:65be27845400 | 7074 | #define DFSDM_FLTJCHGR_JCHG_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7075 | #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7076 | #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */ |
| AnnaBridge | 172:65be27845400 | 7077 | |
| AnnaBridge | 172:65be27845400 | 7078 | /***************** Bit definition for DFSDM_FLTFCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 7079 | #define DFSDM_FLTFCR_FORD_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 7080 | #define DFSDM_FLTFCR_FORD_Msk (0x7U << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */ |
| AnnaBridge | 172:65be27845400 | 7081 | #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */ |
| AnnaBridge | 172:65be27845400 | 7082 | #define DFSDM_FLTFCR_FORD_2 (0x4U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 7083 | #define DFSDM_FLTFCR_FORD_1 (0x2U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 7084 | #define DFSDM_FLTFCR_FORD_0 (0x1U << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 7085 | #define DFSDM_FLTFCR_FOSR_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7086 | #define DFSDM_FLTFCR_FOSR_Msk (0x3FFU << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */ |
| AnnaBridge | 172:65be27845400 | 7087 | #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */ |
| AnnaBridge | 172:65be27845400 | 7088 | #define DFSDM_FLTFCR_IOSR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7089 | #define DFSDM_FLTFCR_IOSR_Msk (0xFFU << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7090 | #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */ |
| AnnaBridge | 172:65be27845400 | 7091 | |
| AnnaBridge | 172:65be27845400 | 7092 | /*************** Bit definition for DFSDM_FLTJDATAR register *****************/ |
| AnnaBridge | 172:65be27845400 | 7093 | #define DFSDM_FLTJDATAR_JDATA_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7094 | #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 7095 | #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */ |
| AnnaBridge | 172:65be27845400 | 7096 | #define DFSDM_FLTJDATAR_JDATACH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7097 | #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 7098 | #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */ |
| AnnaBridge | 172:65be27845400 | 7099 | |
| AnnaBridge | 172:65be27845400 | 7100 | /*************** Bit definition for DFSDM_FLTRDATAR register *****************/ |
| AnnaBridge | 172:65be27845400 | 7101 | #define DFSDM_FLTRDATAR_RDATA_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7102 | #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 7103 | #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */ |
| AnnaBridge | 172:65be27845400 | 7104 | #define DFSDM_FLTRDATAR_RPEND_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7105 | #define DFSDM_FLTRDATAR_RPEND_Msk (0x1U << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7106 | #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */ |
| AnnaBridge | 172:65be27845400 | 7107 | #define DFSDM_FLTRDATAR_RDATACH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7108 | #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 7109 | #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */ |
| AnnaBridge | 172:65be27845400 | 7110 | |
| AnnaBridge | 172:65be27845400 | 7111 | /*************** Bit definition for DFSDM_FLTAWHTR register ******************/ |
| AnnaBridge | 172:65be27845400 | 7112 | #define DFSDM_FLTAWHTR_AWHT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7113 | #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 7114 | #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */ |
| AnnaBridge | 172:65be27845400 | 7115 | #define DFSDM_FLTAWHTR_BKAWH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7116 | #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 7117 | #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */ |
| AnnaBridge | 172:65be27845400 | 7118 | |
| AnnaBridge | 172:65be27845400 | 7119 | /*************** Bit definition for DFSDM_FLTAWLTR register ******************/ |
| AnnaBridge | 172:65be27845400 | 7120 | #define DFSDM_FLTAWLTR_AWLT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7121 | #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 7122 | #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWLT[23:0] Analog watchdog low threshold */ |
| AnnaBridge | 172:65be27845400 | 7123 | #define DFSDM_FLTAWLTR_BKAWL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7124 | #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 7125 | #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */ |
| AnnaBridge | 172:65be27845400 | 7126 | |
| AnnaBridge | 172:65be27845400 | 7127 | /*************** Bit definition for DFSDM_FLTAWSR register *******************/ |
| AnnaBridge | 172:65be27845400 | 7128 | #define DFSDM_FLTAWSR_AWHTF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7129 | #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7130 | #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */ |
| AnnaBridge | 172:65be27845400 | 7131 | #define DFSDM_FLTAWSR_AWLTF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7132 | #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7133 | #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */ |
| AnnaBridge | 172:65be27845400 | 7134 | |
| AnnaBridge | 172:65be27845400 | 7135 | /*************** Bit definition for DFSDM_FLTAWCFR register ******************/ |
| AnnaBridge | 172:65be27845400 | 7136 | #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7137 | #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7138 | #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */ |
| AnnaBridge | 172:65be27845400 | 7139 | #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7140 | #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7141 | #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */ |
| AnnaBridge | 172:65be27845400 | 7142 | |
| AnnaBridge | 172:65be27845400 | 7143 | /*************** Bit definition for DFSDM_FLTEXMAX register ******************/ |
| AnnaBridge | 172:65be27845400 | 7144 | #define DFSDM_FLTEXMAX_EXMAX_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7145 | #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 7146 | #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */ |
| AnnaBridge | 172:65be27845400 | 7147 | #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7148 | #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 7149 | #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */ |
| AnnaBridge | 172:65be27845400 | 7150 | |
| AnnaBridge | 172:65be27845400 | 7151 | /*************** Bit definition for DFSDM_FLTEXMIN register ******************/ |
| AnnaBridge | 172:65be27845400 | 7152 | #define DFSDM_FLTEXMIN_EXMIN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7153 | #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */ |
| AnnaBridge | 172:65be27845400 | 7154 | #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */ |
| AnnaBridge | 172:65be27845400 | 7155 | #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7156 | #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 7157 | #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */ |
| AnnaBridge | 172:65be27845400 | 7158 | |
| AnnaBridge | 172:65be27845400 | 7159 | /*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7160 | #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7161 | #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */ |
| AnnaBridge | 172:65be27845400 | 7162 | #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */ |
| AnnaBridge | 172:65be27845400 | 7163 | |
| AnnaBridge | 172:65be27845400 | 7164 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7165 | /* */ |
| AnnaBridge | 172:65be27845400 | 7166 | /* DMA Controller (DMA) */ |
| AnnaBridge | 172:65be27845400 | 7167 | /* */ |
| AnnaBridge | 172:65be27845400 | 7168 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7169 | |
| AnnaBridge | 172:65be27845400 | 7170 | /******************* Bit definition for DMA_ISR register ********************/ |
| AnnaBridge | 172:65be27845400 | 7171 | #define DMA_ISR_GIF1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7172 | #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7173 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7174 | #define DMA_ISR_TCIF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7175 | #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7176 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7177 | #define DMA_ISR_HTIF1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7178 | #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7179 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7180 | #define DMA_ISR_TEIF1_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7181 | #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7182 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7183 | #define DMA_ISR_GIF2_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7184 | #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7185 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7186 | #define DMA_ISR_TCIF2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7187 | #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7188 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7189 | #define DMA_ISR_HTIF2_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7190 | #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7191 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7192 | #define DMA_ISR_TEIF2_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 7193 | #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7194 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7195 | #define DMA_ISR_GIF3_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7196 | #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7197 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7198 | #define DMA_ISR_TCIF3_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7199 | #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7200 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7201 | #define DMA_ISR_HTIF3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7202 | #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7203 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7204 | #define DMA_ISR_TEIF3_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 7205 | #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7206 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7207 | #define DMA_ISR_GIF4_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7208 | #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7209 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7210 | #define DMA_ISR_TCIF4_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7211 | #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7212 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7213 | #define DMA_ISR_HTIF4_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 7214 | #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 7215 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7216 | #define DMA_ISR_TEIF4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 7217 | #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 7218 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7219 | #define DMA_ISR_GIF5_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7220 | #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7221 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7222 | #define DMA_ISR_TCIF5_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 7223 | #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7224 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7225 | #define DMA_ISR_HTIF5_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 7226 | #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 7227 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7228 | #define DMA_ISR_TEIF5_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 7229 | #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 7230 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7231 | #define DMA_ISR_GIF6_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 7232 | #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7233 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7234 | #define DMA_ISR_TCIF6_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 7235 | #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7236 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7237 | #define DMA_ISR_HTIF6_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 7238 | #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 7239 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7240 | #define DMA_ISR_TEIF6_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 7241 | #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 7242 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7243 | #define DMA_ISR_GIF7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7244 | #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 7245 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 7246 | #define DMA_ISR_TCIF7_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 7247 | #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 7248 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
| AnnaBridge | 172:65be27845400 | 7249 | #define DMA_ISR_HTIF7_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 7250 | #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 7251 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
| AnnaBridge | 172:65be27845400 | 7252 | #define DMA_ISR_TEIF7_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 7253 | #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 7254 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
| AnnaBridge | 172:65be27845400 | 7255 | |
| AnnaBridge | 172:65be27845400 | 7256 | /******************* Bit definition for DMA_IFCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 7257 | #define DMA_IFCR_CGIF1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7258 | #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7259 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ |
| AnnaBridge | 172:65be27845400 | 7260 | #define DMA_IFCR_CTCIF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7261 | #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7262 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7263 | #define DMA_IFCR_CHTIF1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7264 | #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7265 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7266 | #define DMA_IFCR_CTEIF1_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7267 | #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7268 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7269 | #define DMA_IFCR_CGIF2_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7270 | #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7271 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 7272 | #define DMA_IFCR_CTCIF2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7273 | #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7274 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7275 | #define DMA_IFCR_CHTIF2_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7276 | #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7277 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7278 | #define DMA_IFCR_CTEIF2_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 7279 | #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7280 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7281 | #define DMA_IFCR_CGIF3_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7282 | #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7283 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 7284 | #define DMA_IFCR_CTCIF3_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7285 | #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7286 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7287 | #define DMA_IFCR_CHTIF3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7288 | #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7289 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7290 | #define DMA_IFCR_CTEIF3_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 7291 | #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7292 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7293 | #define DMA_IFCR_CGIF4_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7294 | #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7295 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 7296 | #define DMA_IFCR_CTCIF4_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7297 | #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7298 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7299 | #define DMA_IFCR_CHTIF4_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 7300 | #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 7301 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7302 | #define DMA_IFCR_CTEIF4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 7303 | #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 7304 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7305 | #define DMA_IFCR_CGIF5_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7306 | #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7307 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 7308 | #define DMA_IFCR_CTCIF5_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 7309 | #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7310 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7311 | #define DMA_IFCR_CHTIF5_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 7312 | #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 7313 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7314 | #define DMA_IFCR_CTEIF5_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 7315 | #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 7316 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7317 | #define DMA_IFCR_CGIF6_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 7318 | #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7319 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 7320 | #define DMA_IFCR_CTCIF6_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 7321 | #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7322 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7323 | #define DMA_IFCR_CHTIF6_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 7324 | #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 7325 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7326 | #define DMA_IFCR_CTEIF6_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 7327 | #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 7328 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7329 | #define DMA_IFCR_CGIF7_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7330 | #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 7331 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 7332 | #define DMA_IFCR_CTCIF7_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 7333 | #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 7334 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
| AnnaBridge | 172:65be27845400 | 7335 | #define DMA_IFCR_CHTIF7_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 7336 | #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 7337 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
| AnnaBridge | 172:65be27845400 | 7338 | #define DMA_IFCR_CTEIF7_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 7339 | #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 7340 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
| AnnaBridge | 172:65be27845400 | 7341 | |
| AnnaBridge | 172:65be27845400 | 7342 | /******************* Bit definition for DMA_CCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 7343 | #define DMA_CCR_EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7344 | #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7345 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
| AnnaBridge | 172:65be27845400 | 7346 | #define DMA_CCR_TCIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7347 | #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7348 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7349 | #define DMA_CCR_HTIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7350 | #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7351 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7352 | #define DMA_CCR_TEIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7353 | #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7354 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 7355 | #define DMA_CCR_DIR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7356 | #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7357 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
| AnnaBridge | 172:65be27845400 | 7358 | #define DMA_CCR_CIRC_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7359 | #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7360 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
| AnnaBridge | 172:65be27845400 | 7361 | #define DMA_CCR_PINC_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7362 | #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7363 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
| AnnaBridge | 172:65be27845400 | 7364 | #define DMA_CCR_MINC_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 7365 | #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7366 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
| AnnaBridge | 172:65be27845400 | 7367 | |
| AnnaBridge | 172:65be27845400 | 7368 | #define DMA_CCR_PSIZE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7369 | #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 7370 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
| AnnaBridge | 172:65be27845400 | 7371 | #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7372 | #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7373 | |
| AnnaBridge | 172:65be27845400 | 7374 | #define DMA_CCR_MSIZE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7375 | #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 7376 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
| AnnaBridge | 172:65be27845400 | 7377 | #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7378 | #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7379 | |
| AnnaBridge | 172:65be27845400 | 7380 | #define DMA_CCR_PL_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7381 | #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 7382 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ |
| AnnaBridge | 172:65be27845400 | 7383 | #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7384 | #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7385 | |
| AnnaBridge | 172:65be27845400 | 7386 | #define DMA_CCR_MEM2MEM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 7387 | #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 7388 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
| AnnaBridge | 172:65be27845400 | 7389 | |
| AnnaBridge | 172:65be27845400 | 7390 | /****************** Bit definition for DMA_CNDTR register *******************/ |
| AnnaBridge | 172:65be27845400 | 7391 | #define DMA_CNDTR_NDT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7392 | #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 7393 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
| AnnaBridge | 172:65be27845400 | 7394 | |
| AnnaBridge | 172:65be27845400 | 7395 | /****************** Bit definition for DMA_CPAR register ********************/ |
| AnnaBridge | 172:65be27845400 | 7396 | #define DMA_CPAR_PA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7397 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7398 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
| AnnaBridge | 172:65be27845400 | 7399 | |
| AnnaBridge | 172:65be27845400 | 7400 | /****************** Bit definition for DMA_CMAR register ********************/ |
| AnnaBridge | 172:65be27845400 | 7401 | #define DMA_CMAR_MA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7402 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7403 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 172:65be27845400 | 7404 | |
| AnnaBridge | 172:65be27845400 | 7405 | |
| AnnaBridge | 172:65be27845400 | 7406 | |
| AnnaBridge | 172:65be27845400 | 7407 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7408 | /* */ |
| AnnaBridge | 172:65be27845400 | 7409 | /* DMAMUX Controller */ |
| AnnaBridge | 172:65be27845400 | 7410 | /* */ |
| AnnaBridge | 172:65be27845400 | 7411 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7412 | |
| AnnaBridge | 172:65be27845400 | 7413 | /******************** Bits definition for DMAMUX_CxCR register **************/ |
| AnnaBridge | 172:65be27845400 | 7414 | #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7415 | #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFU << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7416 | #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk |
| AnnaBridge | 172:65be27845400 | 7417 | #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7418 | #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7419 | #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7420 | #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7421 | #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7422 | #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7423 | #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7424 | #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7425 | |
| AnnaBridge | 172:65be27845400 | 7426 | #define DMAMUX_CxCR_SOIE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7427 | #define DMAMUX_CxCR_SOIE_Msk (0x1U << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7428 | #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk |
| AnnaBridge | 172:65be27845400 | 7429 | |
| AnnaBridge | 172:65be27845400 | 7430 | #define DMAMUX_CxCR_EGE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7431 | #define DMAMUX_CxCR_EGE_Msk (0x1U << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7432 | #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk |
| AnnaBridge | 172:65be27845400 | 7433 | |
| AnnaBridge | 172:65be27845400 | 7434 | #define DMAMUX_CxCR_SE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7435 | #define DMAMUX_CxCR_SE_Msk (0x1U << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7436 | #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk |
| AnnaBridge | 172:65be27845400 | 7437 | |
| AnnaBridge | 172:65be27845400 | 7438 | #define DMAMUX_CxCR_SPOL_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 7439 | #define DMAMUX_CxCR_SPOL_Msk (0x3U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 172:65be27845400 | 7440 | #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk |
| AnnaBridge | 172:65be27845400 | 7441 | #define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7442 | #define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 7443 | |
| AnnaBridge | 172:65be27845400 | 7444 | #define DMAMUX_CxCR_NBREQ_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 7445 | #define DMAMUX_CxCR_NBREQ_Msk (0x1FU << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 172:65be27845400 | 7446 | #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk |
| AnnaBridge | 172:65be27845400 | 7447 | #define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 7448 | #define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7449 | #define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7450 | #define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 7451 | #define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 7452 | |
| AnnaBridge | 172:65be27845400 | 7453 | #define DMAMUX_CxCR_SYNC_ID_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7454 | #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FU << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ |
| AnnaBridge | 172:65be27845400 | 7455 | #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk |
| AnnaBridge | 172:65be27845400 | 7456 | #define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 7457 | #define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 7458 | #define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 7459 | #define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 7460 | #define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 7461 | |
| AnnaBridge | 172:65be27845400 | 7462 | /******************** Bits definition for DMAMUX_CSR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7463 | #define DMAMUX_CSR_SOF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7464 | #define DMAMUX_CSR_SOF0_Msk (0x1U << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7465 | #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk |
| AnnaBridge | 172:65be27845400 | 7466 | #define DMAMUX_CSR_SOF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7467 | #define DMAMUX_CSR_SOF1_Msk (0x1U << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7468 | #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk |
| AnnaBridge | 172:65be27845400 | 7469 | #define DMAMUX_CSR_SOF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7470 | #define DMAMUX_CSR_SOF2_Msk (0x1U << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7471 | #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk |
| AnnaBridge | 172:65be27845400 | 7472 | #define DMAMUX_CSR_SOF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7473 | #define DMAMUX_CSR_SOF3_Msk (0x1U << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7474 | #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk |
| AnnaBridge | 172:65be27845400 | 7475 | #define DMAMUX_CSR_SOF4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7476 | #define DMAMUX_CSR_SOF4_Msk (0x1U << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7477 | #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk |
| AnnaBridge | 172:65be27845400 | 7478 | #define DMAMUX_CSR_SOF5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7479 | #define DMAMUX_CSR_SOF5_Msk (0x1U << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7480 | #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk |
| AnnaBridge | 172:65be27845400 | 7481 | #define DMAMUX_CSR_SOF6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7482 | #define DMAMUX_CSR_SOF6_Msk (0x1U << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7483 | #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk |
| AnnaBridge | 172:65be27845400 | 7484 | #define DMAMUX_CSR_SOF7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 7485 | #define DMAMUX_CSR_SOF7_Msk (0x1U << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7486 | #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk |
| AnnaBridge | 172:65be27845400 | 7487 | #define DMAMUX_CSR_SOF8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7488 | #define DMAMUX_CSR_SOF8_Msk (0x1U << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7489 | #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk |
| AnnaBridge | 172:65be27845400 | 7490 | #define DMAMUX_CSR_SOF9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7491 | #define DMAMUX_CSR_SOF9_Msk (0x1U << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7492 | #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk |
| AnnaBridge | 172:65be27845400 | 7493 | #define DMAMUX_CSR_SOF10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7494 | #define DMAMUX_CSR_SOF10_Msk (0x1U << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7495 | #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk |
| AnnaBridge | 172:65be27845400 | 7496 | #define DMAMUX_CSR_SOF11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 7497 | #define DMAMUX_CSR_SOF11_Msk (0x1U << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7498 | #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk |
| AnnaBridge | 172:65be27845400 | 7499 | #define DMAMUX_CSR_SOF12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7500 | #define DMAMUX_CSR_SOF12_Msk (0x1U << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7501 | #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk |
| AnnaBridge | 172:65be27845400 | 7502 | #define DMAMUX_CSR_SOF13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7503 | #define DMAMUX_CSR_SOF13_Msk (0x1U << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7504 | #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk |
| AnnaBridge | 172:65be27845400 | 7505 | |
| AnnaBridge | 172:65be27845400 | 7506 | /******************** Bits definition for DMAMUX_CFR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7507 | |
| AnnaBridge | 172:65be27845400 | 7508 | #define DMAMUX_CFR_CSOF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7509 | #define DMAMUX_CFR_CSOF0_Msk (0x1U << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7510 | #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk |
| AnnaBridge | 172:65be27845400 | 7511 | #define DMAMUX_CFR_CSOF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7512 | #define DMAMUX_CFR_CSOF1_Msk (0x1U << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7513 | #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk |
| AnnaBridge | 172:65be27845400 | 7514 | #define DMAMUX_CFR_CSOF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7515 | #define DMAMUX_CFR_CSOF2_Msk (0x1U << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7516 | #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk |
| AnnaBridge | 172:65be27845400 | 7517 | #define DMAMUX_CFR_CSOF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7518 | #define DMAMUX_CFR_CSOF3_Msk (0x1U << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7519 | #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk |
| AnnaBridge | 172:65be27845400 | 7520 | #define DMAMUX_CFR_CSOF4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7521 | #define DMAMUX_CFR_CSOF4_Msk (0x1U << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7522 | #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk |
| AnnaBridge | 172:65be27845400 | 7523 | #define DMAMUX_CFR_CSOF5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7524 | #define DMAMUX_CFR_CSOF5_Msk (0x1U << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7525 | #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk |
| AnnaBridge | 172:65be27845400 | 7526 | #define DMAMUX_CFR_CSOF6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7527 | #define DMAMUX_CFR_CSOF6_Msk (0x1U << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7528 | #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk |
| AnnaBridge | 172:65be27845400 | 7529 | #define DMAMUX_CFR_CSOF7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 7530 | #define DMAMUX_CFR_CSOF7_Msk (0x1U << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7531 | #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk |
| AnnaBridge | 172:65be27845400 | 7532 | #define DMAMUX_CFR_CSOF8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7533 | #define DMAMUX_CFR_CSOF8_Msk (0x1U << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7534 | #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk |
| AnnaBridge | 172:65be27845400 | 7535 | #define DMAMUX_CFR_CSOF9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7536 | #define DMAMUX_CFR_CSOF9_Msk (0x1U << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7537 | #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk |
| AnnaBridge | 172:65be27845400 | 7538 | #define DMAMUX_CFR_CSOF10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7539 | #define DMAMUX_CFR_CSOF10_Msk (0x1U << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7540 | #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk |
| AnnaBridge | 172:65be27845400 | 7541 | #define DMAMUX_CFR_CSOF11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 7542 | #define DMAMUX_CFR_CSOF11_Msk (0x1U << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7543 | #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk |
| AnnaBridge | 172:65be27845400 | 7544 | #define DMAMUX_CFR_CSOF12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7545 | #define DMAMUX_CFR_CSOF12_Msk (0x1U << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7546 | #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk |
| AnnaBridge | 172:65be27845400 | 7547 | #define DMAMUX_CFR_CSOF13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7548 | #define DMAMUX_CFR_CSOF13_Msk (0x1U << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7549 | #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk |
| AnnaBridge | 172:65be27845400 | 7550 | |
| AnnaBridge | 172:65be27845400 | 7551 | /******************** Bits definition for DMAMUX_RGxCR register ************/ |
| AnnaBridge | 172:65be27845400 | 7552 | #define DMAMUX_RGxCR_SIG_ID_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7553 | #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FU << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 7554 | #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk |
| AnnaBridge | 172:65be27845400 | 7555 | #define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7556 | #define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7557 | #define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7558 | #define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7559 | #define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7560 | |
| AnnaBridge | 172:65be27845400 | 7561 | #define DMAMUX_RGxCR_OIE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7562 | #define DMAMUX_RGxCR_OIE_Msk (0x1U << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7563 | #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk |
| AnnaBridge | 172:65be27845400 | 7564 | |
| AnnaBridge | 172:65be27845400 | 7565 | #define DMAMUX_RGxCR_GE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7566 | #define DMAMUX_RGxCR_GE_Msk (0x1U << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7567 | #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk |
| AnnaBridge | 172:65be27845400 | 7568 | |
| AnnaBridge | 172:65be27845400 | 7569 | #define DMAMUX_RGxCR_GPOL_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 7570 | #define DMAMUX_RGxCR_GPOL_Msk (0x3U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 172:65be27845400 | 7571 | #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk |
| AnnaBridge | 172:65be27845400 | 7572 | #define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7573 | #define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 7574 | |
| AnnaBridge | 172:65be27845400 | 7575 | #define DMAMUX_RGxCR_GNBREQ_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 7576 | #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FU << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ |
| AnnaBridge | 172:65be27845400 | 7577 | #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk |
| AnnaBridge | 172:65be27845400 | 7578 | #define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 7579 | #define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7580 | #define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7581 | #define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 7582 | #define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 7583 | |
| AnnaBridge | 172:65be27845400 | 7584 | /******************** Bits definition for DMAMUX_RGSR register **************/ |
| AnnaBridge | 172:65be27845400 | 7585 | #define DMAMUX_RGSR_OF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7586 | #define DMAMUX_RGSR_OF0_Msk (0x1U << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7587 | #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk |
| AnnaBridge | 172:65be27845400 | 7588 | #define DMAMUX_RGSR_OF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7589 | #define DMAMUX_RGSR_OF1_Msk (0x1U << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7590 | #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk |
| AnnaBridge | 172:65be27845400 | 7591 | #define DMAMUX_RGSR_OF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7592 | #define DMAMUX_RGSR_OF2_Msk (0x1U << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7593 | #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk |
| AnnaBridge | 172:65be27845400 | 7594 | #define DMAMUX_RGSR_OF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7595 | #define DMAMUX_RGSR_OF3_Msk (0x1U << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7596 | #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk |
| AnnaBridge | 172:65be27845400 | 7597 | |
| AnnaBridge | 172:65be27845400 | 7598 | /******************** Bits definition for DMAMUX_RGCFR register ************/ |
| AnnaBridge | 172:65be27845400 | 7599 | #define DMAMUX_RGCFR_COF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7600 | #define DMAMUX_RGCFR_COF0_Msk (0x1U << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7601 | #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk |
| AnnaBridge | 172:65be27845400 | 7602 | #define DMAMUX_RGCFR_COF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7603 | #define DMAMUX_RGCFR_COF1_Msk (0x1U << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7604 | #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk |
| AnnaBridge | 172:65be27845400 | 7605 | #define DMAMUX_RGCFR_COF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7606 | #define DMAMUX_RGCFR_COF2_Msk (0x1U << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7607 | #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk |
| AnnaBridge | 172:65be27845400 | 7608 | #define DMAMUX_RGCFR_COF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7609 | #define DMAMUX_RGCFR_COF3_Msk (0x1U << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7610 | #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk |
| AnnaBridge | 172:65be27845400 | 7611 | |
| AnnaBridge | 172:65be27845400 | 7612 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7613 | /* */ |
| AnnaBridge | 172:65be27845400 | 7614 | /* AHB Master DMA2D Controller (DMA2D) */ |
| AnnaBridge | 172:65be27845400 | 7615 | /* */ |
| AnnaBridge | 172:65be27845400 | 7616 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7617 | /* |
| AnnaBridge | 172:65be27845400 | 7618 | * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) |
| AnnaBridge | 172:65be27845400 | 7619 | */ |
| AnnaBridge | 172:65be27845400 | 7620 | #define DMA2D_LINE_OFFSET_MODE_SUPPORT |
| AnnaBridge | 172:65be27845400 | 7621 | #define DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT |
| AnnaBridge | 172:65be27845400 | 7622 | #define DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT |
| AnnaBridge | 172:65be27845400 | 7623 | |
| AnnaBridge | 172:65be27845400 | 7624 | /******************** Bit definition for DMA2D_CR register ******************/ |
| AnnaBridge | 172:65be27845400 | 7625 | |
| AnnaBridge | 172:65be27845400 | 7626 | #define DMA2D_CR_START_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7627 | #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7628 | #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */ |
| AnnaBridge | 172:65be27845400 | 7629 | #define DMA2D_CR_SUSP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7630 | #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7631 | #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */ |
| AnnaBridge | 172:65be27845400 | 7632 | #define DMA2D_CR_ABORT_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7633 | #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7634 | #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */ |
| AnnaBridge | 172:65be27845400 | 7635 | #define DMA2D_CR_LOM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7636 | #define DMA2D_CR_LOM_Msk (0x1U << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7637 | #define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */ |
| AnnaBridge | 172:65be27845400 | 7638 | #define DMA2D_CR_TEIE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7639 | #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7640 | #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 7641 | #define DMA2D_CR_TCIE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7642 | #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7643 | #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 7644 | #define DMA2D_CR_TWIE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7645 | #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7646 | #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 7647 | #define DMA2D_CR_CAEIE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 7648 | #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7649 | #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 7650 | #define DMA2D_CR_CTCIE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7651 | #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7652 | #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 7653 | #define DMA2D_CR_CEIE_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7654 | #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7655 | #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 7656 | #define DMA2D_CR_MODE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7657 | #define DMA2D_CR_MODE_Msk (0x7U << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 7658 | #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */ |
| AnnaBridge | 172:65be27845400 | 7659 | #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7660 | #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7661 | #define DMA2D_CR_MODE_2 (0x4U << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 7662 | |
| AnnaBridge | 172:65be27845400 | 7663 | /******************** Bit definition for DMA2D_ISR register *****************/ |
| AnnaBridge | 172:65be27845400 | 7664 | |
| AnnaBridge | 172:65be27845400 | 7665 | #define DMA2D_ISR_TEIF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7666 | #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7667 | #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7668 | #define DMA2D_ISR_TCIF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7669 | #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7670 | #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7671 | #define DMA2D_ISR_TWIF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7672 | #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7673 | #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7674 | #define DMA2D_ISR_CAEIF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7675 | #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7676 | #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7677 | #define DMA2D_ISR_CTCIF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7678 | #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7679 | #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7680 | #define DMA2D_ISR_CEIF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7681 | #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7682 | #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7683 | |
| AnnaBridge | 172:65be27845400 | 7684 | /******************** Bit definition for DMA2D_IFCR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7685 | |
| AnnaBridge | 172:65be27845400 | 7686 | #define DMA2D_IFCR_CTEIF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7687 | #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7688 | #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7689 | #define DMA2D_IFCR_CTCIF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7690 | #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7691 | #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7692 | #define DMA2D_IFCR_CTWIF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7693 | #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7694 | #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7695 | #define DMA2D_IFCR_CAECIF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7696 | #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7697 | #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7698 | #define DMA2D_IFCR_CCTCIF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7699 | #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7700 | #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7701 | #define DMA2D_IFCR_CCEIF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7702 | #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7703 | #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 7704 | |
| AnnaBridge | 172:65be27845400 | 7705 | /******************** Bit definition for DMA2D_FGMAR register ***************/ |
| AnnaBridge | 172:65be27845400 | 7706 | |
| AnnaBridge | 172:65be27845400 | 7707 | #define DMA2D_FGMAR_MA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7708 | #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7709 | #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 172:65be27845400 | 7710 | |
| AnnaBridge | 172:65be27845400 | 7711 | /******************** Bit definition for DMA2D_FGOR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7712 | |
| AnnaBridge | 172:65be27845400 | 7713 | #define DMA2D_FGOR_LO_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7714 | #define DMA2D_FGOR_LO_Msk (0xFFFFU << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 7715 | #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */ |
| AnnaBridge | 172:65be27845400 | 7716 | |
| AnnaBridge | 172:65be27845400 | 7717 | /******************** Bit definition for DMA2D_BGMAR register ***************/ |
| AnnaBridge | 172:65be27845400 | 7718 | |
| AnnaBridge | 172:65be27845400 | 7719 | #define DMA2D_BGMAR_MA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7720 | #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7721 | #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 172:65be27845400 | 7722 | |
| AnnaBridge | 172:65be27845400 | 7723 | /******************** Bit definition for DMA2D_BGOR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7724 | |
| AnnaBridge | 172:65be27845400 | 7725 | #define DMA2D_BGOR_LO_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7726 | #define DMA2D_BGOR_LO_Msk (0xFFFFU << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 7727 | #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */ |
| AnnaBridge | 172:65be27845400 | 7728 | |
| AnnaBridge | 172:65be27845400 | 7729 | /******************** Bit definition for DMA2D_FGPFCCR register *************/ |
| AnnaBridge | 172:65be27845400 | 7730 | |
| AnnaBridge | 172:65be27845400 | 7731 | #define DMA2D_FGPFCCR_CM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7732 | #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 7733 | #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ |
| AnnaBridge | 172:65be27845400 | 7734 | #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7735 | #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7736 | #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7737 | #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7738 | #define DMA2D_FGPFCCR_CCM_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7739 | #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7740 | #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */ |
| AnnaBridge | 172:65be27845400 | 7741 | #define DMA2D_FGPFCCR_START_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7742 | #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7743 | #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */ |
| AnnaBridge | 172:65be27845400 | 7744 | #define DMA2D_FGPFCCR_CS_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7745 | #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7746 | #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */ |
| AnnaBridge | 172:65be27845400 | 7747 | #define DMA2D_FGPFCCR_AM_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7748 | #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 7749 | #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ |
| AnnaBridge | 172:65be27845400 | 7750 | #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7751 | #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7752 | #define DMA2D_FGPFCCR_AI_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 7753 | #define DMA2D_FGPFCCR_AI_Msk (0x1U << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7754 | #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Alpha Inverted */ |
| AnnaBridge | 172:65be27845400 | 7755 | #define DMA2D_FGPFCCR_RBS_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 7756 | #define DMA2D_FGPFCCR_RBS_Msk (0x1U << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7757 | #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Red Blue Swap */ |
| AnnaBridge | 172:65be27845400 | 7758 | #define DMA2D_FGPFCCR_ALPHA_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7759 | #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 7760 | #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */ |
| AnnaBridge | 172:65be27845400 | 7761 | |
| AnnaBridge | 172:65be27845400 | 7762 | /******************** Bit definition for DMA2D_FGCOLR register **************/ |
| AnnaBridge | 172:65be27845400 | 7763 | |
| AnnaBridge | 172:65be27845400 | 7764 | #define DMA2D_FGCOLR_BLUE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7765 | #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7766 | #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */ |
| AnnaBridge | 172:65be27845400 | 7767 | #define DMA2D_FGCOLR_GREEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7768 | #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7769 | #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */ |
| AnnaBridge | 172:65be27845400 | 7770 | #define DMA2D_FGCOLR_RED_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7771 | #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 7772 | #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */ |
| AnnaBridge | 172:65be27845400 | 7773 | |
| AnnaBridge | 172:65be27845400 | 7774 | /******************** Bit definition for DMA2D_BGPFCCR register *************/ |
| AnnaBridge | 172:65be27845400 | 7775 | |
| AnnaBridge | 172:65be27845400 | 7776 | #define DMA2D_BGPFCCR_CM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7777 | #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 7778 | #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ |
| AnnaBridge | 172:65be27845400 | 7779 | #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7780 | #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7781 | #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7782 | #define DMA2D_BGPFCCR_CM_3 (0x8U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7783 | #define DMA2D_BGPFCCR_CCM_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7784 | #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7785 | #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */ |
| AnnaBridge | 172:65be27845400 | 7786 | #define DMA2D_BGPFCCR_START_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7787 | #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7788 | #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */ |
| AnnaBridge | 172:65be27845400 | 7789 | #define DMA2D_BGPFCCR_CS_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7790 | #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7791 | #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */ |
| AnnaBridge | 172:65be27845400 | 7792 | #define DMA2D_BGPFCCR_AM_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7793 | #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 7794 | #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ |
| AnnaBridge | 172:65be27845400 | 7795 | #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7796 | #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7797 | #define DMA2D_BGPFCCR_AI_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 7798 | #define DMA2D_BGPFCCR_AI_Msk (0x1U << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7799 | #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< Alpha Inverted */ |
| AnnaBridge | 172:65be27845400 | 7800 | #define DMA2D_BGPFCCR_RBS_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 7801 | #define DMA2D_BGPFCCR_RBS_Msk (0x1U << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7802 | #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Red Blue Swap */ |
| AnnaBridge | 172:65be27845400 | 7803 | #define DMA2D_BGPFCCR_ALPHA_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7804 | #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 7805 | #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< Alpha value */ |
| AnnaBridge | 172:65be27845400 | 7806 | |
| AnnaBridge | 172:65be27845400 | 7807 | /******************** Bit definition for DMA2D_BGCOLR register **************/ |
| AnnaBridge | 172:65be27845400 | 7808 | |
| AnnaBridge | 172:65be27845400 | 7809 | #define DMA2D_BGCOLR_BLUE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7810 | #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 7811 | #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */ |
| AnnaBridge | 172:65be27845400 | 7812 | #define DMA2D_BGCOLR_GREEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7813 | #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7814 | #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */ |
| AnnaBridge | 172:65be27845400 | 7815 | #define DMA2D_BGCOLR_RED_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7816 | #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 7817 | #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */ |
| AnnaBridge | 172:65be27845400 | 7818 | |
| AnnaBridge | 172:65be27845400 | 7819 | /******************** Bit definition for DMA2D_FGCMAR register **************/ |
| AnnaBridge | 172:65be27845400 | 7820 | |
| AnnaBridge | 172:65be27845400 | 7821 | #define DMA2D_FGCMAR_MA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7822 | #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7823 | #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 172:65be27845400 | 7824 | |
| AnnaBridge | 172:65be27845400 | 7825 | /******************** Bit definition for DMA2D_BGCMAR register **************/ |
| AnnaBridge | 172:65be27845400 | 7826 | |
| AnnaBridge | 172:65be27845400 | 7827 | #define DMA2D_BGCMAR_MA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7828 | #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7829 | #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 172:65be27845400 | 7830 | |
| AnnaBridge | 172:65be27845400 | 7831 | /******************** Bit definition for DMA2D_OPFCCR register **************/ |
| AnnaBridge | 172:65be27845400 | 7832 | |
| AnnaBridge | 172:65be27845400 | 7833 | #define DMA2D_OPFCCR_CM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7834 | #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 7835 | #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */ |
| AnnaBridge | 172:65be27845400 | 7836 | #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7837 | #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7838 | #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7839 | #define DMA2D_OPFCCR_SB_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7840 | #define DMA2D_OPFCCR_SB_Msk (0x1U << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7841 | #define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */ |
| AnnaBridge | 172:65be27845400 | 7842 | #define DMA2D_OPFCCR_AI_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 7843 | #define DMA2D_OPFCCR_AI_Msk (0x1U << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7844 | #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Alpha Inverted */ |
| AnnaBridge | 172:65be27845400 | 7845 | #define DMA2D_OPFCCR_RBS_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 7846 | #define DMA2D_OPFCCR_RBS_Msk (0x1U << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7847 | #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Red Blue Swap */ |
| AnnaBridge | 172:65be27845400 | 7848 | |
| AnnaBridge | 172:65be27845400 | 7849 | /******************** Bit definition for DMA2D_OCOLR register ***************/ |
| AnnaBridge | 172:65be27845400 | 7850 | |
| AnnaBridge | 172:65be27845400 | 7851 | /*!<Mode_ARGB8888/RGB888 */ |
| AnnaBridge | 172:65be27845400 | 7852 | |
| AnnaBridge | 172:65be27845400 | 7853 | #define DMA2D_OCOLR_BLUE_1 (0x000000FFU) /*!< Blue Value */ |
| AnnaBridge | 172:65be27845400 | 7854 | #define DMA2D_OCOLR_GREEN_1 (0x0000FF00U) /*!< Green Value */ |
| AnnaBridge | 172:65be27845400 | 7855 | #define DMA2D_OCOLR_RED_1 (0x00FF0000U) /*!< Red Value */ |
| AnnaBridge | 172:65be27845400 | 7856 | #define DMA2D_OCOLR_ALPHA_1 (0xFF000000U) /*!< Alpha Channel Value */ |
| AnnaBridge | 172:65be27845400 | 7857 | |
| AnnaBridge | 172:65be27845400 | 7858 | /*!<Mode_RGB565 */ |
| AnnaBridge | 172:65be27845400 | 7859 | #define DMA2D_OCOLR_BLUE_2 (0x0000001FU) /*!< Blue Value */ |
| AnnaBridge | 172:65be27845400 | 7860 | #define DMA2D_OCOLR_GREEN_2 (0x000007E0U) /*!< Green Value */ |
| AnnaBridge | 172:65be27845400 | 7861 | #define DMA2D_OCOLR_RED_2 (0x0000F800U) /*!< Red Value */ |
| AnnaBridge | 172:65be27845400 | 7862 | |
| AnnaBridge | 172:65be27845400 | 7863 | /*!<Mode_ARGB1555 */ |
| AnnaBridge | 172:65be27845400 | 7864 | #define DMA2D_OCOLR_BLUE_3 (0x0000001FU) /*!< Blue Value */ |
| AnnaBridge | 172:65be27845400 | 7865 | #define DMA2D_OCOLR_GREEN_3 (0x000003E0U) /*!< Green Value */ |
| AnnaBridge | 172:65be27845400 | 7866 | #define DMA2D_OCOLR_RED_3 (0x00007C00U) /*!< Red Value */ |
| AnnaBridge | 172:65be27845400 | 7867 | #define DMA2D_OCOLR_ALPHA_3 (0x00008000U) /*!< Alpha Channel Value */ |
| AnnaBridge | 172:65be27845400 | 7868 | |
| AnnaBridge | 172:65be27845400 | 7869 | /*!<Mode_ARGB4444 */ |
| AnnaBridge | 172:65be27845400 | 7870 | #define DMA2D_OCOLR_BLUE_4 (0x0000000FU) /*!< Blue Value */ |
| AnnaBridge | 172:65be27845400 | 7871 | #define DMA2D_OCOLR_GREEN_4 (0x000000F0U) /*!< Green Value */ |
| AnnaBridge | 172:65be27845400 | 7872 | #define DMA2D_OCOLR_RED_4 (0x00000F00U) /*!< Red Value */ |
| AnnaBridge | 172:65be27845400 | 7873 | #define DMA2D_OCOLR_ALPHA_4 (0x0000F000U) /*!< Alpha Channel Value */ |
| AnnaBridge | 172:65be27845400 | 7874 | |
| AnnaBridge | 172:65be27845400 | 7875 | /******************** Bit definition for DMA2D_OMAR register ****************/ |
| AnnaBridge | 172:65be27845400 | 7876 | |
| AnnaBridge | 172:65be27845400 | 7877 | #define DMA2D_OMAR_MA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7878 | #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 7879 | #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */ |
| AnnaBridge | 172:65be27845400 | 7880 | |
| AnnaBridge | 172:65be27845400 | 7881 | /******************** Bit definition for DMA2D_OOR register *****************/ |
| AnnaBridge | 172:65be27845400 | 7882 | |
| AnnaBridge | 172:65be27845400 | 7883 | #define DMA2D_OOR_LO_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7884 | #define DMA2D_OOR_LO_Msk (0xFFFFU << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 7885 | #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */ |
| AnnaBridge | 172:65be27845400 | 7886 | |
| AnnaBridge | 172:65be27845400 | 7887 | /******************** Bit definition for DMA2D_NLR register *****************/ |
| AnnaBridge | 172:65be27845400 | 7888 | |
| AnnaBridge | 172:65be27845400 | 7889 | #define DMA2D_NLR_NL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7890 | #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 7891 | #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */ |
| AnnaBridge | 172:65be27845400 | 7892 | #define DMA2D_NLR_PL_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7893 | #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */ |
| AnnaBridge | 172:65be27845400 | 7894 | #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */ |
| AnnaBridge | 172:65be27845400 | 7895 | |
| AnnaBridge | 172:65be27845400 | 7896 | /******************** Bit definition for DMA2D_LWR register *****************/ |
| AnnaBridge | 172:65be27845400 | 7897 | |
| AnnaBridge | 172:65be27845400 | 7898 | #define DMA2D_LWR_LW_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7899 | #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 7900 | #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */ |
| AnnaBridge | 172:65be27845400 | 7901 | |
| AnnaBridge | 172:65be27845400 | 7902 | /******************** Bit definition for DMA2D_AMTCR register ***************/ |
| AnnaBridge | 172:65be27845400 | 7903 | |
| AnnaBridge | 172:65be27845400 | 7904 | #define DMA2D_AMTCR_EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7905 | #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7906 | #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ |
| AnnaBridge | 172:65be27845400 | 7907 | #define DMA2D_AMTCR_DT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7908 | #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 7909 | #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ |
| AnnaBridge | 172:65be27845400 | 7910 | |
| AnnaBridge | 172:65be27845400 | 7911 | /******************** Bit definition for DMA2D_FGCLUT register **************/ |
| AnnaBridge | 172:65be27845400 | 7912 | |
| AnnaBridge | 172:65be27845400 | 7913 | /******************** Bit definition for DMA2D_BGCLUT register **************/ |
| AnnaBridge | 172:65be27845400 | 7914 | |
| AnnaBridge | 172:65be27845400 | 7915 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7916 | /* */ |
| AnnaBridge | 172:65be27845400 | 7917 | /* External Interrupt/Event Controller */ |
| AnnaBridge | 172:65be27845400 | 7918 | /* */ |
| AnnaBridge | 172:65be27845400 | 7919 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 7920 | /******************* Bit definition for EXTI_IMR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 7921 | #define EXTI_IMR1_IM0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 7922 | #define EXTI_IMR1_IM0_Msk (0x1U << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 7923 | #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ |
| AnnaBridge | 172:65be27845400 | 7924 | #define EXTI_IMR1_IM1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 7925 | #define EXTI_IMR1_IM1_Msk (0x1U << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 7926 | #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ |
| AnnaBridge | 172:65be27845400 | 7927 | #define EXTI_IMR1_IM2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 7928 | #define EXTI_IMR1_IM2_Msk (0x1U << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 7929 | #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ |
| AnnaBridge | 172:65be27845400 | 7930 | #define EXTI_IMR1_IM3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 7931 | #define EXTI_IMR1_IM3_Msk (0x1U << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 7932 | #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ |
| AnnaBridge | 172:65be27845400 | 7933 | #define EXTI_IMR1_IM4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 7934 | #define EXTI_IMR1_IM4_Msk (0x1U << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 7935 | #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ |
| AnnaBridge | 172:65be27845400 | 7936 | #define EXTI_IMR1_IM5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 7937 | #define EXTI_IMR1_IM5_Msk (0x1U << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 7938 | #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ |
| AnnaBridge | 172:65be27845400 | 7939 | #define EXTI_IMR1_IM6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 7940 | #define EXTI_IMR1_IM6_Msk (0x1U << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 7941 | #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ |
| AnnaBridge | 172:65be27845400 | 7942 | #define EXTI_IMR1_IM7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 7943 | #define EXTI_IMR1_IM7_Msk (0x1U << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 7944 | #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ |
| AnnaBridge | 172:65be27845400 | 7945 | #define EXTI_IMR1_IM8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 7946 | #define EXTI_IMR1_IM8_Msk (0x1U << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 7947 | #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ |
| AnnaBridge | 172:65be27845400 | 7948 | #define EXTI_IMR1_IM9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 7949 | #define EXTI_IMR1_IM9_Msk (0x1U << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 7950 | #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ |
| AnnaBridge | 172:65be27845400 | 7951 | #define EXTI_IMR1_IM10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 7952 | #define EXTI_IMR1_IM10_Msk (0x1U << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 7953 | #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ |
| AnnaBridge | 172:65be27845400 | 7954 | #define EXTI_IMR1_IM11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 7955 | #define EXTI_IMR1_IM11_Msk (0x1U << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 7956 | #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ |
| AnnaBridge | 172:65be27845400 | 7957 | #define EXTI_IMR1_IM12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 7958 | #define EXTI_IMR1_IM12_Msk (0x1U << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 7959 | #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ |
| AnnaBridge | 172:65be27845400 | 7960 | #define EXTI_IMR1_IM13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 7961 | #define EXTI_IMR1_IM13_Msk (0x1U << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 7962 | #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ |
| AnnaBridge | 172:65be27845400 | 7963 | #define EXTI_IMR1_IM14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 7964 | #define EXTI_IMR1_IM14_Msk (0x1U << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 7965 | #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ |
| AnnaBridge | 172:65be27845400 | 7966 | #define EXTI_IMR1_IM15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 7967 | #define EXTI_IMR1_IM15_Msk (0x1U << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 7968 | #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ |
| AnnaBridge | 172:65be27845400 | 7969 | #define EXTI_IMR1_IM16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 7970 | #define EXTI_IMR1_IM16_Msk (0x1U << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 7971 | #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ |
| AnnaBridge | 172:65be27845400 | 7972 | #define EXTI_IMR1_IM17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 7973 | #define EXTI_IMR1_IM17_Msk (0x1U << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 7974 | #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ |
| AnnaBridge | 172:65be27845400 | 7975 | #define EXTI_IMR1_IM18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 7976 | #define EXTI_IMR1_IM18_Msk (0x1U << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 7977 | #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ |
| AnnaBridge | 172:65be27845400 | 7978 | #define EXTI_IMR1_IM19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 7979 | #define EXTI_IMR1_IM19_Msk (0x1U << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 7980 | #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ |
| AnnaBridge | 172:65be27845400 | 7981 | #define EXTI_IMR1_IM20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 7982 | #define EXTI_IMR1_IM20_Msk (0x1U << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 7983 | #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ |
| AnnaBridge | 172:65be27845400 | 7984 | #define EXTI_IMR1_IM21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 7985 | #define EXTI_IMR1_IM21_Msk (0x1U << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 7986 | #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ |
| AnnaBridge | 172:65be27845400 | 7987 | #define EXTI_IMR1_IM22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 7988 | #define EXTI_IMR1_IM22_Msk (0x1U << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 7989 | #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ |
| AnnaBridge | 172:65be27845400 | 7990 | #define EXTI_IMR1_IM23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 7991 | #define EXTI_IMR1_IM23_Msk (0x1U << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 7992 | #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ |
| AnnaBridge | 172:65be27845400 | 7993 | #define EXTI_IMR1_IM24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 7994 | #define EXTI_IMR1_IM24_Msk (0x1U << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 7995 | #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ |
| AnnaBridge | 172:65be27845400 | 7996 | #define EXTI_IMR1_IM25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 7997 | #define EXTI_IMR1_IM25_Msk (0x1U << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 7998 | #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ |
| AnnaBridge | 172:65be27845400 | 7999 | #define EXTI_IMR1_IM26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 8000 | #define EXTI_IMR1_IM26_Msk (0x1U << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 8001 | #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ |
| AnnaBridge | 172:65be27845400 | 8002 | #define EXTI_IMR1_IM27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 8003 | #define EXTI_IMR1_IM27_Msk (0x1U << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 8004 | #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ |
| AnnaBridge | 172:65be27845400 | 8005 | #define EXTI_IMR1_IM28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 8006 | #define EXTI_IMR1_IM28_Msk (0x1U << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 8007 | #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ |
| AnnaBridge | 172:65be27845400 | 8008 | #define EXTI_IMR1_IM29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 8009 | #define EXTI_IMR1_IM29_Msk (0x1U << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 8010 | #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ |
| AnnaBridge | 172:65be27845400 | 8011 | #define EXTI_IMR1_IM30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 8012 | #define EXTI_IMR1_IM30_Msk (0x1U << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 8013 | #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ |
| AnnaBridge | 172:65be27845400 | 8014 | #define EXTI_IMR1_IM31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 8015 | #define EXTI_IMR1_IM31_Msk (0x1U << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8016 | #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ |
| AnnaBridge | 172:65be27845400 | 8017 | #define EXTI_IMR1_IM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8018 | #define EXTI_IMR1_IM_Msk (0x9FFFFFFFU << EXTI_IMR1_IM_Pos) /*!< 0x9FFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 8019 | #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ |
| AnnaBridge | 172:65be27845400 | 8020 | |
| AnnaBridge | 172:65be27845400 | 8021 | /******************* Bit definition for EXTI_EMR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8022 | #define EXTI_EMR1_EM0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8023 | #define EXTI_EMR1_EM0_Msk (0x1U << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8024 | #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ |
| AnnaBridge | 172:65be27845400 | 8025 | #define EXTI_EMR1_EM1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8026 | #define EXTI_EMR1_EM1_Msk (0x1U << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8027 | #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ |
| AnnaBridge | 172:65be27845400 | 8028 | #define EXTI_EMR1_EM2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8029 | #define EXTI_EMR1_EM2_Msk (0x1U << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8030 | #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ |
| AnnaBridge | 172:65be27845400 | 8031 | #define EXTI_EMR1_EM3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8032 | #define EXTI_EMR1_EM3_Msk (0x1U << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8033 | #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ |
| AnnaBridge | 172:65be27845400 | 8034 | #define EXTI_EMR1_EM4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8035 | #define EXTI_EMR1_EM4_Msk (0x1U << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8036 | #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ |
| AnnaBridge | 172:65be27845400 | 8037 | #define EXTI_EMR1_EM5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8038 | #define EXTI_EMR1_EM5_Msk (0x1U << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8039 | #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ |
| AnnaBridge | 172:65be27845400 | 8040 | #define EXTI_EMR1_EM6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8041 | #define EXTI_EMR1_EM6_Msk (0x1U << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8042 | #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ |
| AnnaBridge | 172:65be27845400 | 8043 | #define EXTI_EMR1_EM7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 8044 | #define EXTI_EMR1_EM7_Msk (0x1U << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8045 | #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ |
| AnnaBridge | 172:65be27845400 | 8046 | #define EXTI_EMR1_EM8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8047 | #define EXTI_EMR1_EM8_Msk (0x1U << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8048 | #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ |
| AnnaBridge | 172:65be27845400 | 8049 | #define EXTI_EMR1_EM9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8050 | #define EXTI_EMR1_EM9_Msk (0x1U << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8051 | #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ |
| AnnaBridge | 172:65be27845400 | 8052 | #define EXTI_EMR1_EM10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 8053 | #define EXTI_EMR1_EM10_Msk (0x1U << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8054 | #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ |
| AnnaBridge | 172:65be27845400 | 8055 | #define EXTI_EMR1_EM11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8056 | #define EXTI_EMR1_EM11_Msk (0x1U << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8057 | #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ |
| AnnaBridge | 172:65be27845400 | 8058 | #define EXTI_EMR1_EM12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8059 | #define EXTI_EMR1_EM12_Msk (0x1U << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8060 | #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ |
| AnnaBridge | 172:65be27845400 | 8061 | #define EXTI_EMR1_EM13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8062 | #define EXTI_EMR1_EM13_Msk (0x1U << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8063 | #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ |
| AnnaBridge | 172:65be27845400 | 8064 | #define EXTI_EMR1_EM14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8065 | #define EXTI_EMR1_EM14_Msk (0x1U << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8066 | #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ |
| AnnaBridge | 172:65be27845400 | 8067 | #define EXTI_EMR1_EM15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8068 | #define EXTI_EMR1_EM15_Msk (0x1U << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8069 | #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ |
| AnnaBridge | 172:65be27845400 | 8070 | #define EXTI_EMR1_EM16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8071 | #define EXTI_EMR1_EM16_Msk (0x1U << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8072 | #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ |
| AnnaBridge | 172:65be27845400 | 8073 | #define EXTI_EMR1_EM17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 8074 | #define EXTI_EMR1_EM17_Msk (0x1U << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8075 | #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ |
| AnnaBridge | 172:65be27845400 | 8076 | #define EXTI_EMR1_EM18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8077 | #define EXTI_EMR1_EM18_Msk (0x1U << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8078 | #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ |
| AnnaBridge | 172:65be27845400 | 8079 | #define EXTI_EMR1_EM19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8080 | #define EXTI_EMR1_EM19_Msk (0x1U << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8081 | #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ |
| AnnaBridge | 172:65be27845400 | 8082 | #define EXTI_EMR1_EM20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8083 | #define EXTI_EMR1_EM20_Msk (0x1U << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8084 | #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */ |
| AnnaBridge | 172:65be27845400 | 8085 | #define EXTI_EMR1_EM21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8086 | #define EXTI_EMR1_EM21_Msk (0x1U << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8087 | #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ |
| AnnaBridge | 172:65be27845400 | 8088 | #define EXTI_EMR1_EM22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8089 | #define EXTI_EMR1_EM22_Msk (0x1U << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8090 | #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */ |
| AnnaBridge | 172:65be27845400 | 8091 | #define EXTI_EMR1_EM23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 8092 | #define EXTI_EMR1_EM23_Msk (0x1U << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 8093 | #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ |
| AnnaBridge | 172:65be27845400 | 8094 | #define EXTI_EMR1_EM24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 8095 | #define EXTI_EMR1_EM24_Msk (0x1U << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 8096 | #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */ |
| AnnaBridge | 172:65be27845400 | 8097 | #define EXTI_EMR1_EM25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 8098 | #define EXTI_EMR1_EM25_Msk (0x1U << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 8099 | #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ |
| AnnaBridge | 172:65be27845400 | 8100 | #define EXTI_EMR1_EM26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 8101 | #define EXTI_EMR1_EM26_Msk (0x1U << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 8102 | #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ |
| AnnaBridge | 172:65be27845400 | 8103 | #define EXTI_EMR1_EM27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 8104 | #define EXTI_EMR1_EM27_Msk (0x1U << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 8105 | #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ |
| AnnaBridge | 172:65be27845400 | 8106 | #define EXTI_EMR1_EM28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 8107 | #define EXTI_EMR1_EM28_Msk (0x1U << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 8108 | #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ |
| AnnaBridge | 172:65be27845400 | 8109 | #define EXTI_EMR1_EM29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 8110 | #define EXTI_EMR1_EM29_Msk (0x1U << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 8111 | #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ |
| AnnaBridge | 172:65be27845400 | 8112 | #define EXTI_EMR1_EM30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 8113 | #define EXTI_EMR1_EM30_Msk (0x1U << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 8114 | #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ |
| AnnaBridge | 172:65be27845400 | 8115 | #define EXTI_EMR1_EM31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 8116 | #define EXTI_EMR1_EM31_Msk (0x1U << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8117 | #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ |
| AnnaBridge | 172:65be27845400 | 8118 | |
| AnnaBridge | 172:65be27845400 | 8119 | /****************** Bit definition for EXTI_RTSR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8120 | #define EXTI_RTSR1_RT0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8121 | #define EXTI_RTSR1_RT0_Msk (0x1U << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8122 | #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| AnnaBridge | 172:65be27845400 | 8123 | #define EXTI_RTSR1_RT1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8124 | #define EXTI_RTSR1_RT1_Msk (0x1U << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8125 | #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| AnnaBridge | 172:65be27845400 | 8126 | #define EXTI_RTSR1_RT2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8127 | #define EXTI_RTSR1_RT2_Msk (0x1U << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8128 | #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| AnnaBridge | 172:65be27845400 | 8129 | #define EXTI_RTSR1_RT3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8130 | #define EXTI_RTSR1_RT3_Msk (0x1U << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8131 | #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| AnnaBridge | 172:65be27845400 | 8132 | #define EXTI_RTSR1_RT4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8133 | #define EXTI_RTSR1_RT4_Msk (0x1U << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8134 | #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| AnnaBridge | 172:65be27845400 | 8135 | #define EXTI_RTSR1_RT5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8136 | #define EXTI_RTSR1_RT5_Msk (0x1U << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8137 | #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| AnnaBridge | 172:65be27845400 | 8138 | #define EXTI_RTSR1_RT6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8139 | #define EXTI_RTSR1_RT6_Msk (0x1U << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8140 | #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| AnnaBridge | 172:65be27845400 | 8141 | #define EXTI_RTSR1_RT7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 8142 | #define EXTI_RTSR1_RT7_Msk (0x1U << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8143 | #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| AnnaBridge | 172:65be27845400 | 8144 | #define EXTI_RTSR1_RT8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8145 | #define EXTI_RTSR1_RT8_Msk (0x1U << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8146 | #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| AnnaBridge | 172:65be27845400 | 8147 | #define EXTI_RTSR1_RT9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8148 | #define EXTI_RTSR1_RT9_Msk (0x1U << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8149 | #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| AnnaBridge | 172:65be27845400 | 8150 | #define EXTI_RTSR1_RT10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 8151 | #define EXTI_RTSR1_RT10_Msk (0x1U << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8152 | #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| AnnaBridge | 172:65be27845400 | 8153 | #define EXTI_RTSR1_RT11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8154 | #define EXTI_RTSR1_RT11_Msk (0x1U << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8155 | #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| AnnaBridge | 172:65be27845400 | 8156 | #define EXTI_RTSR1_RT12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8157 | #define EXTI_RTSR1_RT12_Msk (0x1U << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8158 | #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| AnnaBridge | 172:65be27845400 | 8159 | #define EXTI_RTSR1_RT13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8160 | #define EXTI_RTSR1_RT13_Msk (0x1U << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8161 | #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| AnnaBridge | 172:65be27845400 | 8162 | #define EXTI_RTSR1_RT14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8163 | #define EXTI_RTSR1_RT14_Msk (0x1U << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8164 | #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| AnnaBridge | 172:65be27845400 | 8165 | #define EXTI_RTSR1_RT15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8166 | #define EXTI_RTSR1_RT15_Msk (0x1U << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8167 | #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| AnnaBridge | 172:65be27845400 | 8168 | #define EXTI_RTSR1_RT16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8169 | #define EXTI_RTSR1_RT16_Msk (0x1U << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8170 | #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| AnnaBridge | 172:65be27845400 | 8171 | #define EXTI_RTSR1_RT18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8172 | #define EXTI_RTSR1_RT18_Msk (0x1U << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8173 | #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
| AnnaBridge | 172:65be27845400 | 8174 | #define EXTI_RTSR1_RT19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8175 | #define EXTI_RTSR1_RT19_Msk (0x1U << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8176 | #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| AnnaBridge | 172:65be27845400 | 8177 | #define EXTI_RTSR1_RT20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8178 | #define EXTI_RTSR1_RT20_Msk (0x1U << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8179 | #define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ |
| AnnaBridge | 172:65be27845400 | 8180 | #define EXTI_RTSR1_RT21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8181 | #define EXTI_RTSR1_RT21_Msk (0x1U << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8182 | #define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ |
| AnnaBridge | 172:65be27845400 | 8183 | #define EXTI_RTSR1_RT22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8184 | #define EXTI_RTSR1_RT22_Msk (0x1U << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8185 | #define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ |
| AnnaBridge | 172:65be27845400 | 8186 | |
| AnnaBridge | 172:65be27845400 | 8187 | /****************** Bit definition for EXTI_FTSR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8188 | #define EXTI_FTSR1_FT0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8189 | #define EXTI_FTSR1_FT0_Msk (0x1U << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8190 | #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| AnnaBridge | 172:65be27845400 | 8191 | #define EXTI_FTSR1_FT1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8192 | #define EXTI_FTSR1_FT1_Msk (0x1U << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8193 | #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| AnnaBridge | 172:65be27845400 | 8194 | #define EXTI_FTSR1_FT2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8195 | #define EXTI_FTSR1_FT2_Msk (0x1U << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8196 | #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| AnnaBridge | 172:65be27845400 | 8197 | #define EXTI_FTSR1_FT3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8198 | #define EXTI_FTSR1_FT3_Msk (0x1U << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8199 | #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| AnnaBridge | 172:65be27845400 | 8200 | #define EXTI_FTSR1_FT4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8201 | #define EXTI_FTSR1_FT4_Msk (0x1U << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8202 | #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| AnnaBridge | 172:65be27845400 | 8203 | #define EXTI_FTSR1_FT5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8204 | #define EXTI_FTSR1_FT5_Msk (0x1U << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8205 | #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| AnnaBridge | 172:65be27845400 | 8206 | #define EXTI_FTSR1_FT6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8207 | #define EXTI_FTSR1_FT6_Msk (0x1U << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8208 | #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| AnnaBridge | 172:65be27845400 | 8209 | #define EXTI_FTSR1_FT7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 8210 | #define EXTI_FTSR1_FT7_Msk (0x1U << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8211 | #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| AnnaBridge | 172:65be27845400 | 8212 | #define EXTI_FTSR1_FT8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8213 | #define EXTI_FTSR1_FT8_Msk (0x1U << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8214 | #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| AnnaBridge | 172:65be27845400 | 8215 | #define EXTI_FTSR1_FT9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8216 | #define EXTI_FTSR1_FT9_Msk (0x1U << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8217 | #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| AnnaBridge | 172:65be27845400 | 8218 | #define EXTI_FTSR1_FT10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 8219 | #define EXTI_FTSR1_FT10_Msk (0x1U << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8220 | #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| AnnaBridge | 172:65be27845400 | 8221 | #define EXTI_FTSR1_FT11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8222 | #define EXTI_FTSR1_FT11_Msk (0x1U << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8223 | #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| AnnaBridge | 172:65be27845400 | 8224 | #define EXTI_FTSR1_FT12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8225 | #define EXTI_FTSR1_FT12_Msk (0x1U << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8226 | #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| AnnaBridge | 172:65be27845400 | 8227 | #define EXTI_FTSR1_FT13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8228 | #define EXTI_FTSR1_FT13_Msk (0x1U << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8229 | #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| AnnaBridge | 172:65be27845400 | 8230 | #define EXTI_FTSR1_FT14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8231 | #define EXTI_FTSR1_FT14_Msk (0x1U << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8232 | #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| AnnaBridge | 172:65be27845400 | 8233 | #define EXTI_FTSR1_FT15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8234 | #define EXTI_FTSR1_FT15_Msk (0x1U << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8235 | #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| AnnaBridge | 172:65be27845400 | 8236 | #define EXTI_FTSR1_FT16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8237 | #define EXTI_FTSR1_FT16_Msk (0x1U << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8238 | #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| AnnaBridge | 172:65be27845400 | 8239 | #define EXTI_FTSR1_FT18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8240 | #define EXTI_FTSR1_FT18_Msk (0x1U << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8241 | #define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
| AnnaBridge | 172:65be27845400 | 8242 | #define EXTI_FTSR1_FT19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8243 | #define EXTI_FTSR1_FT19_Msk (0x1U << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8244 | #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| AnnaBridge | 172:65be27845400 | 8245 | #define EXTI_FTSR1_FT20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8246 | #define EXTI_FTSR1_FT20_Msk (0x1U << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8247 | #define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ |
| AnnaBridge | 172:65be27845400 | 8248 | #define EXTI_FTSR1_FT21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8249 | #define EXTI_FTSR1_FT21_Msk (0x1U << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8250 | #define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ |
| AnnaBridge | 172:65be27845400 | 8251 | #define EXTI_FTSR1_FT22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8252 | #define EXTI_FTSR1_FT22_Msk (0x1U << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8253 | #define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ |
| AnnaBridge | 172:65be27845400 | 8254 | |
| AnnaBridge | 172:65be27845400 | 8255 | /****************** Bit definition for EXTI_SWIER1 register *****************/ |
| AnnaBridge | 172:65be27845400 | 8256 | #define EXTI_SWIER1_SWI0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8257 | #define EXTI_SWIER1_SWI0_Msk (0x1U << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8258 | #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ |
| AnnaBridge | 172:65be27845400 | 8259 | #define EXTI_SWIER1_SWI1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8260 | #define EXTI_SWIER1_SWI1_Msk (0x1U << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8261 | #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ |
| AnnaBridge | 172:65be27845400 | 8262 | #define EXTI_SWIER1_SWI2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8263 | #define EXTI_SWIER1_SWI2_Msk (0x1U << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8264 | #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ |
| AnnaBridge | 172:65be27845400 | 8265 | #define EXTI_SWIER1_SWI3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8266 | #define EXTI_SWIER1_SWI3_Msk (0x1U << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8267 | #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ |
| AnnaBridge | 172:65be27845400 | 8268 | #define EXTI_SWIER1_SWI4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8269 | #define EXTI_SWIER1_SWI4_Msk (0x1U << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8270 | #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ |
| AnnaBridge | 172:65be27845400 | 8271 | #define EXTI_SWIER1_SWI5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8272 | #define EXTI_SWIER1_SWI5_Msk (0x1U << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8273 | #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ |
| AnnaBridge | 172:65be27845400 | 8274 | #define EXTI_SWIER1_SWI6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8275 | #define EXTI_SWIER1_SWI6_Msk (0x1U << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8276 | #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ |
| AnnaBridge | 172:65be27845400 | 8277 | #define EXTI_SWIER1_SWI7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 8278 | #define EXTI_SWIER1_SWI7_Msk (0x1U << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8279 | #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ |
| AnnaBridge | 172:65be27845400 | 8280 | #define EXTI_SWIER1_SWI8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8281 | #define EXTI_SWIER1_SWI8_Msk (0x1U << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8282 | #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ |
| AnnaBridge | 172:65be27845400 | 8283 | #define EXTI_SWIER1_SWI9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8284 | #define EXTI_SWIER1_SWI9_Msk (0x1U << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8285 | #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ |
| AnnaBridge | 172:65be27845400 | 8286 | #define EXTI_SWIER1_SWI10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 8287 | #define EXTI_SWIER1_SWI10_Msk (0x1U << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8288 | #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ |
| AnnaBridge | 172:65be27845400 | 8289 | #define EXTI_SWIER1_SWI11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8290 | #define EXTI_SWIER1_SWI11_Msk (0x1U << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8291 | #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ |
| AnnaBridge | 172:65be27845400 | 8292 | #define EXTI_SWIER1_SWI12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8293 | #define EXTI_SWIER1_SWI12_Msk (0x1U << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8294 | #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ |
| AnnaBridge | 172:65be27845400 | 8295 | #define EXTI_SWIER1_SWI13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8296 | #define EXTI_SWIER1_SWI13_Msk (0x1U << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8297 | #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ |
| AnnaBridge | 172:65be27845400 | 8298 | #define EXTI_SWIER1_SWI14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8299 | #define EXTI_SWIER1_SWI14_Msk (0x1U << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8300 | #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ |
| AnnaBridge | 172:65be27845400 | 8301 | #define EXTI_SWIER1_SWI15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8302 | #define EXTI_SWIER1_SWI15_Msk (0x1U << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8303 | #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ |
| AnnaBridge | 172:65be27845400 | 8304 | #define EXTI_SWIER1_SWI16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8305 | #define EXTI_SWIER1_SWI16_Msk (0x1U << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8306 | #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ |
| AnnaBridge | 172:65be27845400 | 8307 | #define EXTI_SWIER1_SWI18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8308 | #define EXTI_SWIER1_SWI18_Msk (0x1U << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8309 | #define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ |
| AnnaBridge | 172:65be27845400 | 8310 | #define EXTI_SWIER1_SWI19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8311 | #define EXTI_SWIER1_SWI19_Msk (0x1U << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8312 | #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */ |
| AnnaBridge | 172:65be27845400 | 8313 | #define EXTI_SWIER1_SWI20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8314 | #define EXTI_SWIER1_SWI20_Msk (0x1U << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8315 | #define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */ |
| AnnaBridge | 172:65be27845400 | 8316 | #define EXTI_SWIER1_SWI21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8317 | #define EXTI_SWIER1_SWI21_Msk (0x1U << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8318 | #define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */ |
| AnnaBridge | 172:65be27845400 | 8319 | #define EXTI_SWIER1_SWI22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8320 | #define EXTI_SWIER1_SWI22_Msk (0x1U << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8321 | #define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */ |
| AnnaBridge | 172:65be27845400 | 8322 | |
| AnnaBridge | 172:65be27845400 | 8323 | /******************* Bit definition for EXTI_PR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 8324 | #define EXTI_PR1_PIF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8325 | #define EXTI_PR1_PIF0_Msk (0x1U << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8326 | #define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */ |
| AnnaBridge | 172:65be27845400 | 8327 | #define EXTI_PR1_PIF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8328 | #define EXTI_PR1_PIF1_Msk (0x1U << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8329 | #define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */ |
| AnnaBridge | 172:65be27845400 | 8330 | #define EXTI_PR1_PIF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8331 | #define EXTI_PR1_PIF2_Msk (0x1U << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8332 | #define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */ |
| AnnaBridge | 172:65be27845400 | 8333 | #define EXTI_PR1_PIF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8334 | #define EXTI_PR1_PIF3_Msk (0x1U << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8335 | #define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */ |
| AnnaBridge | 172:65be27845400 | 8336 | #define EXTI_PR1_PIF4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8337 | #define EXTI_PR1_PIF4_Msk (0x1U << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8338 | #define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */ |
| AnnaBridge | 172:65be27845400 | 8339 | #define EXTI_PR1_PIF5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8340 | #define EXTI_PR1_PIF5_Msk (0x1U << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8341 | #define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */ |
| AnnaBridge | 172:65be27845400 | 8342 | #define EXTI_PR1_PIF6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8343 | #define EXTI_PR1_PIF6_Msk (0x1U << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8344 | #define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */ |
| AnnaBridge | 172:65be27845400 | 8345 | #define EXTI_PR1_PIF7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 8346 | #define EXTI_PR1_PIF7_Msk (0x1U << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8347 | #define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */ |
| AnnaBridge | 172:65be27845400 | 8348 | #define EXTI_PR1_PIF8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8349 | #define EXTI_PR1_PIF8_Msk (0x1U << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8350 | #define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */ |
| AnnaBridge | 172:65be27845400 | 8351 | #define EXTI_PR1_PIF9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8352 | #define EXTI_PR1_PIF9_Msk (0x1U << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8353 | #define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */ |
| AnnaBridge | 172:65be27845400 | 8354 | #define EXTI_PR1_PIF10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 8355 | #define EXTI_PR1_PIF10_Msk (0x1U << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8356 | #define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */ |
| AnnaBridge | 172:65be27845400 | 8357 | #define EXTI_PR1_PIF11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8358 | #define EXTI_PR1_PIF11_Msk (0x1U << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8359 | #define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */ |
| AnnaBridge | 172:65be27845400 | 8360 | #define EXTI_PR1_PIF12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8361 | #define EXTI_PR1_PIF12_Msk (0x1U << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8362 | #define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */ |
| AnnaBridge | 172:65be27845400 | 8363 | #define EXTI_PR1_PIF13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8364 | #define EXTI_PR1_PIF13_Msk (0x1U << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8365 | #define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */ |
| AnnaBridge | 172:65be27845400 | 8366 | #define EXTI_PR1_PIF14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8367 | #define EXTI_PR1_PIF14_Msk (0x1U << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8368 | #define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */ |
| AnnaBridge | 172:65be27845400 | 8369 | #define EXTI_PR1_PIF15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8370 | #define EXTI_PR1_PIF15_Msk (0x1U << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8371 | #define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */ |
| AnnaBridge | 172:65be27845400 | 8372 | #define EXTI_PR1_PIF16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8373 | #define EXTI_PR1_PIF16_Msk (0x1U << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8374 | #define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */ |
| AnnaBridge | 172:65be27845400 | 8375 | #define EXTI_PR1_PIF18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8376 | #define EXTI_PR1_PIF18_Msk (0x1U << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8377 | #define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */ |
| AnnaBridge | 172:65be27845400 | 8378 | #define EXTI_PR1_PIF19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8379 | #define EXTI_PR1_PIF19_Msk (0x1U << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8380 | #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */ |
| AnnaBridge | 172:65be27845400 | 8381 | #define EXTI_PR1_PIF20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8382 | #define EXTI_PR1_PIF20_Msk (0x1U << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8383 | #define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */ |
| AnnaBridge | 172:65be27845400 | 8384 | #define EXTI_PR1_PIF21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8385 | #define EXTI_PR1_PIF21_Msk (0x1U << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8386 | #define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */ |
| AnnaBridge | 172:65be27845400 | 8387 | #define EXTI_PR1_PIF22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8388 | #define EXTI_PR1_PIF22_Msk (0x1U << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8389 | #define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */ |
| AnnaBridge | 172:65be27845400 | 8390 | |
| AnnaBridge | 172:65be27845400 | 8391 | /******************* Bit definition for EXTI_IMR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8392 | #define EXTI_IMR2_IM32_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8393 | #define EXTI_IMR2_IM32_Msk (0x1U << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8394 | #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */ |
| AnnaBridge | 172:65be27845400 | 8395 | #define EXTI_IMR2_IM33_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8396 | #define EXTI_IMR2_IM33_Msk (0x1U << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8397 | #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */ |
| AnnaBridge | 172:65be27845400 | 8398 | #define EXTI_IMR2_IM35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8399 | #define EXTI_IMR2_IM35_Msk (0x1U << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8400 | #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */ |
| AnnaBridge | 172:65be27845400 | 8401 | #define EXTI_IMR2_IM36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8402 | #define EXTI_IMR2_IM36_Msk (0x1U << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8403 | #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */ |
| AnnaBridge | 172:65be27845400 | 8404 | #define EXTI_IMR2_IM37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8405 | #define EXTI_IMR2_IM37_Msk (0x1U << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8406 | #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */ |
| AnnaBridge | 172:65be27845400 | 8407 | #define EXTI_IMR2_IM38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8408 | #define EXTI_IMR2_IM38_Msk (0x1U << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8409 | #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */ |
| AnnaBridge | 172:65be27845400 | 8410 | #define EXTI_IMR2_IM40_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8411 | #define EXTI_IMR2_IM40_Msk (0x1U << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8412 | #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */ |
| AnnaBridge | 172:65be27845400 | 8413 | #define EXTI_IMR2_IM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8414 | #define EXTI_IMR2_IM_Msk (0x17BU << EXTI_IMR2_IM_Pos) /*!< 0x0000017B */ |
| AnnaBridge | 172:65be27845400 | 8415 | #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */ |
| AnnaBridge | 172:65be27845400 | 8416 | |
| AnnaBridge | 172:65be27845400 | 8417 | /******************* Bit definition for EXTI_EMR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8418 | #define EXTI_EMR2_EM32_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8419 | #define EXTI_EMR2_EM32_Msk (0x1U << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8420 | #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */ |
| AnnaBridge | 172:65be27845400 | 8421 | #define EXTI_EMR2_EM33_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8422 | #define EXTI_EMR2_EM33_Msk (0x1U << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8423 | #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */ |
| AnnaBridge | 172:65be27845400 | 8424 | #define EXTI_EMR2_EM35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8425 | #define EXTI_EMR2_EM35_Msk (0x1U << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8426 | #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */ |
| AnnaBridge | 172:65be27845400 | 8427 | #define EXTI_EMR2_EM36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8428 | #define EXTI_EMR2_EM36_Msk (0x1U << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8429 | #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */ |
| AnnaBridge | 172:65be27845400 | 8430 | #define EXTI_EMR2_EM37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8431 | #define EXTI_EMR2_EM37_Msk (0x1U << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8432 | #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */ |
| AnnaBridge | 172:65be27845400 | 8433 | #define EXTI_EMR2_EM38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8434 | #define EXTI_EMR2_EM38_Msk (0x1U << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8435 | #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */ |
| AnnaBridge | 172:65be27845400 | 8436 | #define EXTI_EMR2_EM40_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8437 | #define EXTI_EMR2_EM40_Msk (0x1U << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8438 | #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */ |
| AnnaBridge | 172:65be27845400 | 8439 | #define EXTI_EMR2_EM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8440 | #define EXTI_EMR2_EM_Msk (0x17BU << EXTI_EMR2_EM_Pos) /*!< 0x0000017B */ |
| AnnaBridge | 172:65be27845400 | 8441 | #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */ |
| AnnaBridge | 172:65be27845400 | 8442 | |
| AnnaBridge | 172:65be27845400 | 8443 | /****************** Bit definition for EXTI_RTSR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8444 | #define EXTI_RTSR2_RT35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8445 | #define EXTI_RTSR2_RT35_Msk (0x1U << EXTI_RTSR2_RT35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8446 | #define EXTI_RTSR2_RT35 EXTI_RTSR2_RT35_Msk /*!< Rising trigger event configuration bit of line 35 */ |
| AnnaBridge | 172:65be27845400 | 8447 | #define EXTI_RTSR2_RT36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8448 | #define EXTI_RTSR2_RT36_Msk (0x1U << EXTI_RTSR2_RT36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8449 | #define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk /*!< Rising trigger event configuration bit of line 36 */ |
| AnnaBridge | 172:65be27845400 | 8450 | #define EXTI_RTSR2_RT37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8451 | #define EXTI_RTSR2_RT37_Msk (0x1U << EXTI_RTSR2_RT37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8452 | #define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk /*!< Rising trigger event configuration bit of line 37 */ |
| AnnaBridge | 172:65be27845400 | 8453 | #define EXTI_RTSR2_RT38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8454 | #define EXTI_RTSR2_RT38_Msk (0x1U << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8455 | #define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */ |
| AnnaBridge | 172:65be27845400 | 8456 | |
| AnnaBridge | 172:65be27845400 | 8457 | /****************** Bit definition for EXTI_FTSR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 8458 | #define EXTI_FTSR2_FT35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8459 | #define EXTI_FTSR2_FT35_Msk (0x1U << EXTI_FTSR2_FT35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8460 | #define EXTI_FTSR2_FT35 EXTI_FTSR2_FT35_Msk /*!< Falling trigger event configuration bit of line 35 */ |
| AnnaBridge | 172:65be27845400 | 8461 | #define EXTI_FTSR2_FT36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8462 | #define EXTI_FTSR2_FT36_Msk (0x1U << EXTI_FTSR2_FT36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8463 | #define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk /*!< Falling trigger event configuration bit of line 36 */ |
| AnnaBridge | 172:65be27845400 | 8464 | #define EXTI_FTSR2_FT37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8465 | #define EXTI_FTSR2_FT37_Msk (0x1U << EXTI_FTSR2_FT37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8466 | #define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk /*!< Falling trigger event configuration bit of line 37 */ |
| AnnaBridge | 172:65be27845400 | 8467 | #define EXTI_FTSR2_FT38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8468 | #define EXTI_FTSR2_FT38_Msk (0x1U << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8469 | #define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 38 */ |
| AnnaBridge | 172:65be27845400 | 8470 | |
| AnnaBridge | 172:65be27845400 | 8471 | /****************** Bit definition for EXTI_SWIER2 register *****************/ |
| AnnaBridge | 172:65be27845400 | 8472 | #define EXTI_SWIER2_SWI35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8473 | #define EXTI_SWIER2_SWI35_Msk (0x1U << EXTI_SWIER2_SWI35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8474 | #define EXTI_SWIER2_SWI35 EXTI_SWIER2_SWI35_Msk /*!< Software Interrupt on line 35 */ |
| AnnaBridge | 172:65be27845400 | 8475 | #define EXTI_SWIER2_SWI36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8476 | #define EXTI_SWIER2_SWI36_Msk (0x1U << EXTI_SWIER2_SWI36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8477 | #define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk /*!< Software Interrupt on line 36 */ |
| AnnaBridge | 172:65be27845400 | 8478 | #define EXTI_SWIER2_SWI37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8479 | #define EXTI_SWIER2_SWI37_Msk (0x1U << EXTI_SWIER2_SWI37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8480 | #define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk /*!< Software Interrupt on line 37 */ |
| AnnaBridge | 172:65be27845400 | 8481 | #define EXTI_SWIER2_SWI38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8482 | #define EXTI_SWIER2_SWI38_Msk (0x1U << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8483 | #define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */ |
| AnnaBridge | 172:65be27845400 | 8484 | |
| AnnaBridge | 172:65be27845400 | 8485 | /******************* Bit definition for EXTI_PR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 8486 | #define EXTI_PR2_PIF35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8487 | #define EXTI_PR2_PIF35_Msk (0x1U << EXTI_PR2_PIF35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8488 | #define EXTI_PR2_PIF35 EXTI_PR2_PIF35_Msk /*!< Pending bit for line 35 */ |
| AnnaBridge | 172:65be27845400 | 8489 | #define EXTI_PR2_PIF36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8490 | #define EXTI_PR2_PIF36_Msk (0x1U << EXTI_PR2_PIF36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8491 | #define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk /*!< Pending bit for line 36 */ |
| AnnaBridge | 172:65be27845400 | 8492 | #define EXTI_PR2_PIF37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8493 | #define EXTI_PR2_PIF37_Msk (0x1U << EXTI_PR2_PIF37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8494 | #define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk /*!< Pending bit for line 37 */ |
| AnnaBridge | 172:65be27845400 | 8495 | #define EXTI_PR2_PIF38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8496 | #define EXTI_PR2_PIF38_Msk (0x1U << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8497 | #define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */ |
| AnnaBridge | 172:65be27845400 | 8498 | |
| AnnaBridge | 172:65be27845400 | 8499 | |
| AnnaBridge | 172:65be27845400 | 8500 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 8501 | /* */ |
| AnnaBridge | 172:65be27845400 | 8502 | /* FLASH */ |
| AnnaBridge | 172:65be27845400 | 8503 | /* */ |
| AnnaBridge | 172:65be27845400 | 8504 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 8505 | /******************* Bits definition for FLASH_ACR register *****************/ |
| AnnaBridge | 172:65be27845400 | 8506 | #define FLASH_ACR_LATENCY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8507 | #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 8508 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk |
| AnnaBridge | 172:65be27845400 | 8509 | #define FLASH_ACR_LATENCY_0WS (0x00000000U) |
| AnnaBridge | 172:65be27845400 | 8510 | #define FLASH_ACR_LATENCY_1WS (0x00000001U) |
| AnnaBridge | 172:65be27845400 | 8511 | #define FLASH_ACR_LATENCY_2WS (0x00000002U) |
| AnnaBridge | 172:65be27845400 | 8512 | #define FLASH_ACR_LATENCY_3WS (0x00000003U) |
| AnnaBridge | 172:65be27845400 | 8513 | #define FLASH_ACR_LATENCY_4WS (0x00000004U) |
| AnnaBridge | 172:65be27845400 | 8514 | #define FLASH_ACR_LATENCY_5WS (0x00000005U) |
| AnnaBridge | 172:65be27845400 | 8515 | #define FLASH_ACR_LATENCY_6WS (0x00000006U) |
| AnnaBridge | 172:65be27845400 | 8516 | #define FLASH_ACR_LATENCY_7WS (0x00000007U) |
| AnnaBridge | 172:65be27845400 | 8517 | #define FLASH_ACR_LATENCY_8WS (0x00000008U) |
| AnnaBridge | 172:65be27845400 | 8518 | #define FLASH_ACR_LATENCY_9WS (0x00000009U) |
| AnnaBridge | 172:65be27845400 | 8519 | #define FLASH_ACR_LATENCY_10WS (0x0000000AU) |
| AnnaBridge | 172:65be27845400 | 8520 | #define FLASH_ACR_LATENCY_11WS (0x0000000BU) |
| AnnaBridge | 172:65be27845400 | 8521 | #define FLASH_ACR_LATENCY_12WS (0x0000000CU) |
| AnnaBridge | 172:65be27845400 | 8522 | #define FLASH_ACR_LATENCY_13WS (0x0000000DU) |
| AnnaBridge | 172:65be27845400 | 8523 | #define FLASH_ACR_LATENCY_14WS (0x0000000EU) |
| AnnaBridge | 172:65be27845400 | 8524 | #define FLASH_ACR_LATENCY_15WS (0x0000000FU) |
| AnnaBridge | 172:65be27845400 | 8525 | #define FLASH_ACR_PRFTEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8526 | #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8527 | #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk |
| AnnaBridge | 172:65be27845400 | 8528 | #define FLASH_ACR_ICEN_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8529 | #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8530 | #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk |
| AnnaBridge | 172:65be27845400 | 8531 | #define FLASH_ACR_DCEN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 8532 | #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8533 | #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk |
| AnnaBridge | 172:65be27845400 | 8534 | #define FLASH_ACR_ICRST_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8535 | #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8536 | #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk |
| AnnaBridge | 172:65be27845400 | 8537 | #define FLASH_ACR_DCRST_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8538 | #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8539 | #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk |
| AnnaBridge | 172:65be27845400 | 8540 | #define FLASH_ACR_RUN_PD_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8541 | #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8542 | #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */ |
| AnnaBridge | 172:65be27845400 | 8543 | #define FLASH_ACR_SLEEP_PD_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8544 | #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8545 | #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */ |
| AnnaBridge | 172:65be27845400 | 8546 | |
| AnnaBridge | 172:65be27845400 | 8547 | /******************* Bits definition for FLASH_SR register ******************/ |
| AnnaBridge | 172:65be27845400 | 8548 | #define FLASH_SR_EOP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8549 | #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8550 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk |
| AnnaBridge | 172:65be27845400 | 8551 | #define FLASH_SR_OPERR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8552 | #define FLASH_SR_OPERR_Msk (0x1U << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8553 | #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk |
| AnnaBridge | 172:65be27845400 | 8554 | #define FLASH_SR_PROGERR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8555 | #define FLASH_SR_PROGERR_Msk (0x1U << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8556 | #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk |
| AnnaBridge | 172:65be27845400 | 8557 | #define FLASH_SR_WRPERR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8558 | #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8559 | #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk |
| AnnaBridge | 172:65be27845400 | 8560 | #define FLASH_SR_PGAERR_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 8561 | #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8562 | #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk |
| AnnaBridge | 172:65be27845400 | 8563 | #define FLASH_SR_SIZERR_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8564 | #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8565 | #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk |
| AnnaBridge | 172:65be27845400 | 8566 | #define FLASH_SR_PGSERR_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 8567 | #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8568 | #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk |
| AnnaBridge | 172:65be27845400 | 8569 | #define FLASH_SR_MISERR_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8570 | #define FLASH_SR_MISERR_Msk (0x1U << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8571 | #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk |
| AnnaBridge | 172:65be27845400 | 8572 | #define FLASH_SR_FASTERR_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8573 | #define FLASH_SR_FASTERR_Msk (0x1U << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8574 | #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk |
| AnnaBridge | 172:65be27845400 | 8575 | #define FLASH_SR_RDERR_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8576 | #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8577 | #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk |
| AnnaBridge | 172:65be27845400 | 8578 | #define FLASH_SR_OPTVERR_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8579 | #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8580 | #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk |
| AnnaBridge | 172:65be27845400 | 8581 | #define FLASH_SR_BSY_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8582 | #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8583 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk |
| AnnaBridge | 172:65be27845400 | 8584 | #define FLASH_SR_PEMPTY_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 8585 | #define FLASH_SR_PEMPTY_Msk (0x1U << FLASH_SR_PEMPTY_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8586 | #define FLASH_SR_PEMPTY FLASH_SR_PEMPTY_Msk |
| AnnaBridge | 172:65be27845400 | 8587 | |
| AnnaBridge | 172:65be27845400 | 8588 | /******************* Bits definition for FLASH_CR register ******************/ |
| AnnaBridge | 172:65be27845400 | 8589 | #define FLASH_CR_PG_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8590 | #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8591 | #define FLASH_CR_PG FLASH_CR_PG_Msk |
| AnnaBridge | 172:65be27845400 | 8592 | #define FLASH_CR_PER_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8593 | #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8594 | #define FLASH_CR_PER FLASH_CR_PER_Msk |
| AnnaBridge | 172:65be27845400 | 8595 | #define FLASH_CR_MER1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8596 | #define FLASH_CR_MER1_Msk (0x1U << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8597 | #define FLASH_CR_MER1 FLASH_CR_MER1_Msk |
| AnnaBridge | 172:65be27845400 | 8598 | #define FLASH_CR_PNB_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8599 | #define FLASH_CR_PNB_Msk (0xFFU << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */ |
| AnnaBridge | 172:65be27845400 | 8600 | #define FLASH_CR_PNB FLASH_CR_PNB_Msk |
| AnnaBridge | 172:65be27845400 | 8601 | #define FLASH_CR_BKER_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8602 | #define FLASH_CR_BKER_Msk (0x1U << FLASH_CR_BKER_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8603 | #define FLASH_CR_BKER FLASH_CR_BKER_Msk |
| AnnaBridge | 172:65be27845400 | 8604 | #define FLASH_CR_MER2_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8605 | #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8606 | #define FLASH_CR_MER2 FLASH_CR_MER2_Msk |
| AnnaBridge | 172:65be27845400 | 8607 | #define FLASH_CR_STRT_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8608 | #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8609 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8610 | #define FLASH_CR_OPTSTRT_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 8611 | #define FLASH_CR_OPTSTRT_Msk (0x1U << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8612 | #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk |
| AnnaBridge | 172:65be27845400 | 8613 | #define FLASH_CR_FSTPG_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8614 | #define FLASH_CR_FSTPG_Msk (0x1U << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8615 | #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk |
| AnnaBridge | 172:65be27845400 | 8616 | #define FLASH_CR_EOPIE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 8617 | #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 8618 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk |
| AnnaBridge | 172:65be27845400 | 8619 | #define FLASH_CR_ERRIE_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 8620 | #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 8621 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk |
| AnnaBridge | 172:65be27845400 | 8622 | #define FLASH_CR_RDERRIE_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 8623 | #define FLASH_CR_RDERRIE_Msk (0x1U << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 8624 | #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk |
| AnnaBridge | 172:65be27845400 | 8625 | #define FLASH_CR_OBL_LAUNCH_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 8626 | #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 8627 | #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk |
| AnnaBridge | 172:65be27845400 | 8628 | #define FLASH_CR_OPTLOCK_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 8629 | #define FLASH_CR_OPTLOCK_Msk (0x1U << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 8630 | #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk |
| AnnaBridge | 172:65be27845400 | 8631 | #define FLASH_CR_LOCK_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 8632 | #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8633 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk |
| AnnaBridge | 172:65be27845400 | 8634 | |
| AnnaBridge | 172:65be27845400 | 8635 | /******************* Bits definition for FLASH_ECCR register ***************/ |
| AnnaBridge | 172:65be27845400 | 8636 | #define FLASH_ECCR_ADDR_ECC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8637 | #define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ |
| AnnaBridge | 172:65be27845400 | 8638 | #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk |
| AnnaBridge | 172:65be27845400 | 8639 | #define FLASH_ECCR_BK_ECC_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8640 | #define FLASH_ECCR_BK_ECC_Msk (0x1U << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8641 | #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk |
| AnnaBridge | 172:65be27845400 | 8642 | #define FLASH_ECCR_SYSF_ECC_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8643 | #define FLASH_ECCR_SYSF_ECC_Msk (0x1U << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8644 | #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk |
| AnnaBridge | 172:65be27845400 | 8645 | #define FLASH_ECCR_ECCIE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 8646 | #define FLASH_ECCR_ECCIE_Msk (0x1U << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 8647 | #define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk |
| AnnaBridge | 172:65be27845400 | 8648 | #define FLASH_ECCR_ECCC2_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 8649 | #define FLASH_ECCR_ECCC2_Msk (0x1U << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 8650 | #define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk |
| AnnaBridge | 172:65be27845400 | 8651 | #define FLASH_ECCR_ECCD2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 8652 | #define FLASH_ECCR_ECCD2_Msk (0x1U << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 8653 | #define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk |
| AnnaBridge | 172:65be27845400 | 8654 | #define FLASH_ECCR_ECCC_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 8655 | #define FLASH_ECCR_ECCC_Msk (0x1U << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 8656 | #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk |
| AnnaBridge | 172:65be27845400 | 8657 | #define FLASH_ECCR_ECCD_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 8658 | #define FLASH_ECCR_ECCD_Msk (0x1U << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8659 | #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk |
| AnnaBridge | 172:65be27845400 | 8660 | |
| AnnaBridge | 172:65be27845400 | 8661 | /******************* Bits definition for FLASH_OPTR register ***************/ |
| AnnaBridge | 172:65be27845400 | 8662 | #define FLASH_OPTR_RDP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8663 | #define FLASH_OPTR_RDP_Msk (0xFFU << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 8664 | #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk |
| AnnaBridge | 172:65be27845400 | 8665 | #define FLASH_OPTR_BOR_LEV_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8666 | #define FLASH_OPTR_BOR_LEV_Msk (0x7U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 8667 | #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk |
| AnnaBridge | 172:65be27845400 | 8668 | #define FLASH_OPTR_BOR_LEV_0 (0x0U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */ |
| AnnaBridge | 172:65be27845400 | 8669 | #define FLASH_OPTR_BOR_LEV_1 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8670 | #define FLASH_OPTR_BOR_LEV_2 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8671 | #define FLASH_OPTR_BOR_LEV_3 (0x3U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 8672 | #define FLASH_OPTR_BOR_LEV_4 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8673 | #define FLASH_OPTR_nRST_STOP_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8674 | #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8675 | #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 8676 | #define FLASH_OPTR_nRST_STDBY_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8677 | #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8678 | #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk |
| AnnaBridge | 172:65be27845400 | 8679 | #define FLASH_OPTR_nRST_SHDW_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8680 | #define FLASH_OPTR_nRST_SHDW_Msk (0x1U << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8681 | #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk |
| AnnaBridge | 172:65be27845400 | 8682 | #define FLASH_OPTR_IWDG_SW_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8683 | #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8684 | #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk |
| AnnaBridge | 172:65be27845400 | 8685 | #define FLASH_OPTR_IWDG_STOP_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 8686 | #define FLASH_OPTR_IWDG_STOP_Msk (0x1U << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8687 | #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 8688 | #define FLASH_OPTR_IWDG_STDBY_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 8689 | #define FLASH_OPTR_IWDG_STDBY_Msk (0x1U << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8690 | #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk |
| AnnaBridge | 172:65be27845400 | 8691 | #define FLASH_OPTR_WWDG_SW_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8692 | #define FLASH_OPTR_WWDG_SW_Msk (0x1U << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8693 | #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk |
| AnnaBridge | 172:65be27845400 | 8694 | #define FLASH_OPTR_BFB2_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8695 | #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8696 | #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk |
| AnnaBridge | 172:65be27845400 | 8697 | #define FLASH_OPTR_DB1M_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8698 | #define FLASH_OPTR_DB1M_Msk (0x1U << FLASH_OPTR_DB1M_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8699 | #define FLASH_OPTR_DB1M FLASH_OPTR_DB1M_Msk |
| AnnaBridge | 172:65be27845400 | 8700 | #define FLASH_OPTR_DBANK_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8701 | #define FLASH_OPTR_DBANK_Msk (0x1U << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8702 | #define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk |
| AnnaBridge | 172:65be27845400 | 8703 | #define FLASH_OPTR_nBOOT1_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 8704 | #define FLASH_OPTR_nBOOT1_Msk (0x1U << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 8705 | #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk |
| AnnaBridge | 172:65be27845400 | 8706 | #define FLASH_OPTR_SRAM2_PE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 8707 | #define FLASH_OPTR_SRAM2_PE_Msk (0x1U << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 8708 | #define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk |
| AnnaBridge | 172:65be27845400 | 8709 | #define FLASH_OPTR_SRAM2_RST_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 8710 | #define FLASH_OPTR_SRAM2_RST_Msk (0x1U << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 8711 | #define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk |
| AnnaBridge | 172:65be27845400 | 8712 | #define FLASH_OPTR_nSWBOOT0_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 8713 | #define FLASH_OPTR_nSWBOOT0_Msk (0x1U << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 8714 | #define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk |
| AnnaBridge | 172:65be27845400 | 8715 | #define FLASH_OPTR_nBOOT0_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 8716 | #define FLASH_OPTR_nBOOT0_Msk (0x1U << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 8717 | #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk |
| AnnaBridge | 172:65be27845400 | 8718 | |
| AnnaBridge | 172:65be27845400 | 8719 | /****************** Bits definition for FLASH_PCROP1SR register **********/ |
| AnnaBridge | 172:65be27845400 | 8720 | #define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8721 | #define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x1FFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0001FFFF */ |
| AnnaBridge | 172:65be27845400 | 8722 | #define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8723 | |
| AnnaBridge | 172:65be27845400 | 8724 | /****************** Bits definition for FLASH_PCROP1ER register ***********/ |
| AnnaBridge | 172:65be27845400 | 8725 | #define FLASH_PCROP1ER_PCROP1_END_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8726 | #define FLASH_PCROP1ER_PCROP1_END_Msk (0x1FFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0001FFFF */ |
| AnnaBridge | 172:65be27845400 | 8727 | #define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk |
| AnnaBridge | 172:65be27845400 | 8728 | #define FLASH_PCROP1ER_PCROP_RDP_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 8729 | #define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8730 | #define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk |
| AnnaBridge | 172:65be27845400 | 8731 | |
| AnnaBridge | 172:65be27845400 | 8732 | /****************** Bits definition for FLASH_WRP1AR register ***************/ |
| AnnaBridge | 172:65be27845400 | 8733 | #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8734 | #define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 8735 | #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8736 | #define FLASH_WRP1AR_WRP1A_END_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8737 | #define FLASH_WRP1AR_WRP1A_END_Msk (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 8738 | #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk |
| AnnaBridge | 172:65be27845400 | 8739 | |
| AnnaBridge | 172:65be27845400 | 8740 | /****************** Bits definition for FLASH_WRPB1R register ***************/ |
| AnnaBridge | 172:65be27845400 | 8741 | #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8742 | #define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 8743 | #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8744 | #define FLASH_WRP1BR_WRP1B_END_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8745 | #define FLASH_WRP1BR_WRP1B_END_Msk (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 8746 | #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk |
| AnnaBridge | 172:65be27845400 | 8747 | |
| AnnaBridge | 172:65be27845400 | 8748 | /****************** Bits definition for FLASH_PCROP2SR register **********/ |
| AnnaBridge | 172:65be27845400 | 8749 | #define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8750 | #define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x1FFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0001FFFF */ |
| AnnaBridge | 172:65be27845400 | 8751 | #define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8752 | |
| AnnaBridge | 172:65be27845400 | 8753 | /****************** Bits definition for FLASH_PCROP2ER register ***********/ |
| AnnaBridge | 172:65be27845400 | 8754 | #define FLASH_PCROP2ER_PCROP2_END_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8755 | #define FLASH_PCROP2ER_PCROP2_END_Msk (0x1FFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0001FFFF */ |
| AnnaBridge | 172:65be27845400 | 8756 | #define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk |
| AnnaBridge | 172:65be27845400 | 8757 | |
| AnnaBridge | 172:65be27845400 | 8758 | /****************** Bits definition for FLASH_WRP2AR register ***************/ |
| AnnaBridge | 172:65be27845400 | 8759 | #define FLASH_WRP2AR_WRP2A_STRT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8760 | #define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 8761 | #define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8762 | #define FLASH_WRP2AR_WRP2A_END_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8763 | #define FLASH_WRP2AR_WRP2A_END_Msk (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 8764 | #define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk |
| AnnaBridge | 172:65be27845400 | 8765 | |
| AnnaBridge | 172:65be27845400 | 8766 | /****************** Bits definition for FLASH_WRP2BR register ***************/ |
| AnnaBridge | 172:65be27845400 | 8767 | #define FLASH_WRP2BR_WRP2B_STRT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8768 | #define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 8769 | #define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk |
| AnnaBridge | 172:65be27845400 | 8770 | #define FLASH_WRP2BR_WRP2B_END_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8771 | #define FLASH_WRP2BR_WRP2B_END_Msk (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 8772 | #define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk |
| AnnaBridge | 172:65be27845400 | 8773 | |
| AnnaBridge | 172:65be27845400 | 8774 | /****************** Bits definition for FLASH_CFGR register *****************/ |
| AnnaBridge | 172:65be27845400 | 8775 | #define FLASH_CFGR_LVEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8776 | #define FLASH_CFGR_LVEN_Msk (0x1U << FLASH_CFGR_LVEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8777 | #define FLASH_CFGR_LVEN FLASH_CFGR_LVEN_Msk /*!< Flash low voltage enable */ |
| AnnaBridge | 172:65be27845400 | 8778 | |
| AnnaBridge | 172:65be27845400 | 8779 | |
| AnnaBridge | 172:65be27845400 | 8780 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 8781 | /* */ |
| AnnaBridge | 172:65be27845400 | 8782 | /* Flexible Memory Controller */ |
| AnnaBridge | 172:65be27845400 | 8783 | /* */ |
| AnnaBridge | 172:65be27845400 | 8784 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 8785 | /****************** Bit definition for FMC_BCR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 8786 | #define FMC_BCR1_CCLKEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8787 | #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8788 | #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ |
| AnnaBridge | 172:65be27845400 | 8789 | #define FMC_BCR1_WFDIS_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 8790 | #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8791 | #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ |
| AnnaBridge | 172:65be27845400 | 8792 | |
| AnnaBridge | 172:65be27845400 | 8793 | /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/ |
| AnnaBridge | 172:65be27845400 | 8794 | #define FMC_BCRx_MBKEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8795 | #define FMC_BCRx_MBKEN_Msk (0x1U << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8796 | #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */ |
| AnnaBridge | 172:65be27845400 | 8797 | #define FMC_BCRx_MUXEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8798 | #define FMC_BCRx_MUXEN_Msk (0x1U << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8799 | #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */ |
| AnnaBridge | 172:65be27845400 | 8800 | |
| AnnaBridge | 172:65be27845400 | 8801 | #define FMC_BCRx_MTYP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8802 | #define FMC_BCRx_MTYP_Msk (0x3U << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 8803 | #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ |
| AnnaBridge | 172:65be27845400 | 8804 | #define FMC_BCRx_MTYP_0 (0x1U << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8805 | #define FMC_BCRx_MTYP_1 (0x2U << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8806 | |
| AnnaBridge | 172:65be27845400 | 8807 | #define FMC_BCRx_MWID_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8808 | #define FMC_BCRx_MWID_Msk (0x3U << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 8809 | #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ |
| AnnaBridge | 172:65be27845400 | 8810 | #define FMC_BCRx_MWID_0 (0x1U << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8811 | #define FMC_BCRx_MWID_1 (0x2U << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8812 | |
| AnnaBridge | 172:65be27845400 | 8813 | #define FMC_BCRx_FACCEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8814 | #define FMC_BCRx_FACCEN_Msk (0x1U << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8815 | #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */ |
| AnnaBridge | 172:65be27845400 | 8816 | #define FMC_BCRx_BURSTEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8817 | #define FMC_BCRx_BURSTEN_Msk (0x1U << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8818 | #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */ |
| AnnaBridge | 172:65be27845400 | 8819 | #define FMC_BCRx_WAITPOL_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8820 | #define FMC_BCRx_WAITPOL_Msk (0x1U << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8821 | #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */ |
| AnnaBridge | 172:65be27845400 | 8822 | #define FMC_BCRx_WAITCFG_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 8823 | #define FMC_BCRx_WAITCFG_Msk (0x1U << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8824 | #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */ |
| AnnaBridge | 172:65be27845400 | 8825 | #define FMC_BCRx_WREN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 8826 | #define FMC_BCRx_WREN_Msk (0x1U << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8827 | #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */ |
| AnnaBridge | 172:65be27845400 | 8828 | #define FMC_BCRx_WAITEN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8829 | #define FMC_BCRx_WAITEN_Msk (0x1U << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8830 | #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */ |
| AnnaBridge | 172:65be27845400 | 8831 | #define FMC_BCRx_EXTMOD_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 8832 | #define FMC_BCRx_EXTMOD_Msk (0x1U << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8833 | #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */ |
| AnnaBridge | 172:65be27845400 | 8834 | #define FMC_BCRx_ASYNCWAIT_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 8835 | #define FMC_BCRx_ASYNCWAIT_Msk (0x1U << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8836 | #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */ |
| AnnaBridge | 172:65be27845400 | 8837 | |
| AnnaBridge | 172:65be27845400 | 8838 | #define FMC_BCRx_CPSIZE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8839 | #define FMC_BCRx_CPSIZE_Msk (0x7U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 8840 | #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */ |
| AnnaBridge | 172:65be27845400 | 8841 | #define FMC_BCRx_CPSIZE_0 (0x1U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8842 | #define FMC_BCRx_CPSIZE_1 (0x2U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8843 | #define FMC_BCRx_CPSIZE_2 (0x4U << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8844 | |
| AnnaBridge | 172:65be27845400 | 8845 | #define FMC_BCRx_CBURSTRW_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 8846 | #define FMC_BCRx_CBURSTRW_Msk (0x1U << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8847 | #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */ |
| AnnaBridge | 172:65be27845400 | 8848 | |
| AnnaBridge | 172:65be27845400 | 8849 | #define FMC_BCRx_NBLSET_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 8850 | #define FMC_BCRx_NBLSET_Msk (0x3U << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 172:65be27845400 | 8851 | #define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */ |
| AnnaBridge | 172:65be27845400 | 8852 | #define FMC_BCRx_NBLSET_0 (0x1U << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */ |
| AnnaBridge | 172:65be27845400 | 8853 | #define FMC_BCRx_NBLSET_1 (0x2U << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 8854 | |
| AnnaBridge | 172:65be27845400 | 8855 | /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/ |
| AnnaBridge | 172:65be27845400 | 8856 | #define FMC_BTRx_ADDSET_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8857 | #define FMC_BTRx_ADDSET_Msk (0xFU << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 8858 | #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8859 | #define FMC_BTRx_ADDSET_0 (0x1U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8860 | #define FMC_BTRx_ADDSET_1 (0x2U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8861 | #define FMC_BTRx_ADDSET_2 (0x4U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8862 | #define FMC_BTRx_ADDSET_3 (0x8U << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8863 | |
| AnnaBridge | 172:65be27845400 | 8864 | #define FMC_BTRx_ADDHLD_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8865 | #define FMC_BTRx_ADDHLD_Msk (0xFU << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 8866 | #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8867 | #define FMC_BTRx_ADDHLD_0 (0x1U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8868 | #define FMC_BTRx_ADDHLD_1 (0x2U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8869 | #define FMC_BTRx_ADDHLD_2 (0x4U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8870 | #define FMC_BTRx_ADDHLD_3 (0x8U << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8871 | |
| AnnaBridge | 172:65be27845400 | 8872 | #define FMC_BTRx_DATAST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8873 | #define FMC_BTRx_DATAST_Msk (0xFFU << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 8874 | #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8875 | #define FMC_BTRx_DATAST_0 (0x01U << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8876 | #define FMC_BTRx_DATAST_1 (0x02U << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8877 | #define FMC_BTRx_DATAST_2 (0x04U << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8878 | #define FMC_BTRx_DATAST_3 (0x08U << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8879 | #define FMC_BTRx_DATAST_4 (0x10U << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8880 | #define FMC_BTRx_DATAST_5 (0x20U << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8881 | #define FMC_BTRx_DATAST_6 (0x40U << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8882 | #define FMC_BTRx_DATAST_7 (0x80U << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8883 | |
| AnnaBridge | 172:65be27845400 | 8884 | #define FMC_BTRx_BUSTURN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8885 | #define FMC_BTRx_BUSTURN_Msk (0xFU << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 8886 | #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8887 | #define FMC_BTRx_BUSTURN_0 (0x1U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8888 | #define FMC_BTRx_BUSTURN_1 (0x2U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8889 | #define FMC_BTRx_BUSTURN_2 (0x4U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8890 | #define FMC_BTRx_BUSTURN_3 (0x8U << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8891 | |
| AnnaBridge | 172:65be27845400 | 8892 | #define FMC_BTRx_CLKDIV_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 8893 | #define FMC_BTRx_CLKDIV_Msk (0xFU << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 8894 | #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| AnnaBridge | 172:65be27845400 | 8895 | #define FMC_BTRx_CLKDIV_0 (0x1U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 8896 | #define FMC_BTRx_CLKDIV_1 (0x2U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 8897 | #define FMC_BTRx_CLKDIV_2 (0x4U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 8898 | #define FMC_BTRx_CLKDIV_3 (0x8U << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 8899 | |
| AnnaBridge | 172:65be27845400 | 8900 | #define FMC_BTRx_DATLAT_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 8901 | #define FMC_BTRx_DATLAT_Msk (0xFU << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 8902 | #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */ |
| AnnaBridge | 172:65be27845400 | 8903 | #define FMC_BTRx_DATLAT_0 (0x1U << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 8904 | #define FMC_BTRx_DATLAT_1 (0x2U << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 8905 | #define FMC_BTRx_DATLAT_2 (0x4U << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 8906 | #define FMC_BTRx_DATLAT_3 (0x8U << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 8907 | |
| AnnaBridge | 172:65be27845400 | 8908 | #define FMC_BTRx_ACCMOD_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 8909 | #define FMC_BTRx_ACCMOD_Msk (0x3U << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 8910 | #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 172:65be27845400 | 8911 | #define FMC_BTRx_ACCMOD_0 (0x1U << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 8912 | #define FMC_BTRx_ACCMOD_1 (0x2U << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 8913 | |
| AnnaBridge | 172:65be27845400 | 8914 | #define FMC_BTRx_DATAHLD_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 8915 | #define FMC_BTRx_DATAHLD_Msk (0x3U << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 172:65be27845400 | 8916 | #define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8917 | #define FMC_BTRx_DATAHLD_0 (0x1U << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 8918 | #define FMC_BTRx_DATAHLD_1 (0x2U << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8919 | |
| AnnaBridge | 172:65be27845400 | 8920 | /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/ |
| AnnaBridge | 172:65be27845400 | 8921 | #define FMC_BWTRx_ADDSET_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 8922 | #define FMC_BWTRx_ADDSET_Msk (0xFU << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 8923 | #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8924 | #define FMC_BWTRx_ADDSET_0 (0x1U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 8925 | #define FMC_BWTRx_ADDSET_1 (0x2U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8926 | #define FMC_BWTRx_ADDSET_2 (0x4U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8927 | #define FMC_BWTRx_ADDSET_3 (0x8U << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8928 | |
| AnnaBridge | 172:65be27845400 | 8929 | #define FMC_BWTRx_ADDHLD_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8930 | #define FMC_BWTRx_ADDHLD_Msk (0xFU << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 8931 | #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8932 | #define FMC_BWTRx_ADDHLD_0 (0x1U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8933 | #define FMC_BWTRx_ADDHLD_1 (0x2U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8934 | #define FMC_BWTRx_ADDHLD_2 (0x4U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8935 | #define FMC_BWTRx_ADDHLD_3 (0x8U << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 8936 | |
| AnnaBridge | 172:65be27845400 | 8937 | #define FMC_BWTRx_DATAST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 8938 | #define FMC_BWTRx_DATAST_Msk (0xFFU << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 8939 | #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8940 | #define FMC_BWTRx_DATAST_0 (0x01U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 8941 | #define FMC_BWTRx_DATAST_1 (0x02U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8942 | #define FMC_BWTRx_DATAST_2 (0x04U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8943 | #define FMC_BWTRx_DATAST_3 (0x08U << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8944 | #define FMC_BWTRx_DATAST_4 (0x10U << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8945 | #define FMC_BWTRx_DATAST_5 (0x20U << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 8946 | #define FMC_BWTRx_DATAST_6 (0x40U << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 8947 | #define FMC_BWTRx_DATAST_7 (0x80U << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 8948 | |
| AnnaBridge | 172:65be27845400 | 8949 | #define FMC_BWTRx_BUSTURN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 8950 | #define FMC_BWTRx_BUSTURN_Msk (0xFU << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 8951 | #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8952 | #define FMC_BWTRx_BUSTURN_0 (0x1U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 8953 | #define FMC_BWTRx_BUSTURN_1 (0x2U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 8954 | #define FMC_BWTRx_BUSTURN_2 (0x4U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 8955 | #define FMC_BWTRx_BUSTURN_3 (0x8U << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 8956 | |
| AnnaBridge | 172:65be27845400 | 8957 | #define FMC_BWTRx_ACCMOD_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 8958 | #define FMC_BWTRx_ACCMOD_Msk (0x3U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 8959 | #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ |
| AnnaBridge | 172:65be27845400 | 8960 | #define FMC_BWTRx_ACCMOD_0 (0x1U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 8961 | #define FMC_BWTRx_ACCMOD_1 (0x2U << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 8962 | |
| AnnaBridge | 172:65be27845400 | 8963 | #define FMC_BWTRx_DATAHLD_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 8964 | #define FMC_BWTRx_DATAHLD_Msk (0x3U << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 172:65be27845400 | 8965 | #define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */ |
| AnnaBridge | 172:65be27845400 | 8966 | #define FMC_BWTRx_DATAHLD_0 (0x1U << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 8967 | #define FMC_BWTRx_DATAHLD_1 (0x2U << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 8968 | |
| AnnaBridge | 172:65be27845400 | 8969 | /****************** Bit definition for FMC_PCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 8970 | #define FMC_PCR_PWAITEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 8971 | #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 8972 | #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */ |
| AnnaBridge | 172:65be27845400 | 8973 | #define FMC_PCR_PBKEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 8974 | #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 8975 | #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */ |
| AnnaBridge | 172:65be27845400 | 8976 | #define FMC_PCR_PTYP_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 8977 | #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 8978 | #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */ |
| AnnaBridge | 172:65be27845400 | 8979 | |
| AnnaBridge | 172:65be27845400 | 8980 | #define FMC_PCR_PWID_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 8981 | #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 8982 | #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */ |
| AnnaBridge | 172:65be27845400 | 8983 | #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 8984 | #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 8985 | |
| AnnaBridge | 172:65be27845400 | 8986 | #define FMC_PCR_ECCEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 8987 | #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 8988 | #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */ |
| AnnaBridge | 172:65be27845400 | 8989 | |
| AnnaBridge | 172:65be27845400 | 8990 | #define FMC_PCR_TCLR_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 8991 | #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */ |
| AnnaBridge | 172:65be27845400 | 8992 | #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */ |
| AnnaBridge | 172:65be27845400 | 8993 | #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 8994 | #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 8995 | #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 8996 | #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 8997 | |
| AnnaBridge | 172:65be27845400 | 8998 | #define FMC_PCR_TAR_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 8999 | #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */ |
| AnnaBridge | 172:65be27845400 | 9000 | #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */ |
| AnnaBridge | 172:65be27845400 | 9001 | #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9002 | #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9003 | #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9004 | #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9005 | |
| AnnaBridge | 172:65be27845400 | 9006 | #define FMC_PCR_ECCPS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 9007 | #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 172:65be27845400 | 9008 | #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */ |
| AnnaBridge | 172:65be27845400 | 9009 | #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9010 | #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9011 | #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9012 | |
| AnnaBridge | 172:65be27845400 | 9013 | /******************* Bit definition for FMC_SR register ********************/ |
| AnnaBridge | 172:65be27845400 | 9014 | #define FMC_SR_IRS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9015 | #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9016 | #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */ |
| AnnaBridge | 172:65be27845400 | 9017 | #define FMC_SR_ILS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 9018 | #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9019 | #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */ |
| AnnaBridge | 172:65be27845400 | 9020 | #define FMC_SR_IFS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9021 | #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9022 | #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */ |
| AnnaBridge | 172:65be27845400 | 9023 | #define FMC_SR_IREN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 9024 | #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9025 | #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */ |
| AnnaBridge | 172:65be27845400 | 9026 | #define FMC_SR_ILEN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9027 | #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9028 | #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */ |
| AnnaBridge | 172:65be27845400 | 9029 | #define FMC_SR_IFEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 9030 | #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9031 | #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */ |
| AnnaBridge | 172:65be27845400 | 9032 | #define FMC_SR_FEMPT_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9033 | #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9034 | #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */ |
| AnnaBridge | 172:65be27845400 | 9035 | |
| AnnaBridge | 172:65be27845400 | 9036 | /****************** Bit definition for FMC_PMEM register ******************/ |
| AnnaBridge | 172:65be27845400 | 9037 | #define FMC_PMEM_MEMSET_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9038 | #define FMC_PMEM_MEMSET_Msk (0xFFU << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 9039 | #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */ |
| AnnaBridge | 172:65be27845400 | 9040 | #define FMC_PMEM_MEMSET_0 (0x01U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9041 | #define FMC_PMEM_MEMSET_1 (0x02U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9042 | #define FMC_PMEM_MEMSET_2 (0x04U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9043 | #define FMC_PMEM_MEMSET_3 (0x08U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9044 | #define FMC_PMEM_MEMSET_4 (0x10U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9045 | #define FMC_PMEM_MEMSET_5 (0x20U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9046 | #define FMC_PMEM_MEMSET_6 (0x40U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9047 | #define FMC_PMEM_MEMSET_7 (0x80U << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9048 | |
| AnnaBridge | 172:65be27845400 | 9049 | #define FMC_PMEM_MEMWAIT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9050 | #define FMC_PMEM_MEMWAIT_Msk (0xFFU << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 9051 | #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */ |
| AnnaBridge | 172:65be27845400 | 9052 | #define FMC_PMEM_MEMWAIT_0 (0x01U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9053 | #define FMC_PMEM_MEMWAIT_1 (0x02U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9054 | #define FMC_PMEM_MEMWAIT_2 (0x04U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9055 | #define FMC_PMEM_MEMWAIT_3 (0x08U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9056 | #define FMC_PMEM_MEMWAIT_4 (0x10U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9057 | #define FMC_PMEM_MEMWAIT_5 (0x20U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9058 | #define FMC_PMEM_MEMWAIT_6 (0x40U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9059 | #define FMC_PMEM_MEMWAIT_7 (0x80U << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9060 | |
| AnnaBridge | 172:65be27845400 | 9061 | #define FMC_PMEM_MEMHOLD_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9062 | #define FMC_PMEM_MEMHOLD_Msk (0xFFU << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 9063 | #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */ |
| AnnaBridge | 172:65be27845400 | 9064 | #define FMC_PMEM_MEMHOLD_0 (0x01U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9065 | #define FMC_PMEM_MEMHOLD_1 (0x02U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9066 | #define FMC_PMEM_MEMHOLD_2 (0x04U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9067 | #define FMC_PMEM_MEMHOLD_3 (0x08U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9068 | #define FMC_PMEM_MEMHOLD_4 (0x10U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 9069 | #define FMC_PMEM_MEMHOLD_5 (0x20U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 9070 | #define FMC_PMEM_MEMHOLD_6 (0x40U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 9071 | #define FMC_PMEM_MEMHOLD_7 (0x80U << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 9072 | |
| AnnaBridge | 172:65be27845400 | 9073 | #define FMC_PMEM_MEMHIZ_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 9074 | #define FMC_PMEM_MEMHIZ_Msk (0xFFU << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 9075 | #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */ |
| AnnaBridge | 172:65be27845400 | 9076 | #define FMC_PMEM_MEMHIZ_0 (0x01U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 9077 | #define FMC_PMEM_MEMHIZ_1 (0x02U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 9078 | #define FMC_PMEM_MEMHIZ_2 (0x04U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 9079 | #define FMC_PMEM_MEMHIZ_3 (0x08U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 9080 | #define FMC_PMEM_MEMHIZ_4 (0x10U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 9081 | #define FMC_PMEM_MEMHIZ_5 (0x20U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 9082 | #define FMC_PMEM_MEMHIZ_6 (0x40U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 9083 | #define FMC_PMEM_MEMHIZ_7 (0x80U << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 9084 | |
| AnnaBridge | 172:65be27845400 | 9085 | /****************** Bit definition for FMC_PATT register *******************/ |
| AnnaBridge | 172:65be27845400 | 9086 | #define FMC_PATT_ATTSET_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9087 | #define FMC_PATT_ATTSET_Msk (0xFFU << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 9088 | #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */ |
| AnnaBridge | 172:65be27845400 | 9089 | #define FMC_PATT_ATTSET_0 (0x01U << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9090 | #define FMC_PATT_ATTSET_1 (0x02U << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9091 | #define FMC_PATT_ATTSET_2 (0x04U << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9092 | #define FMC_PATT_ATTSET_3 (0x08U << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9093 | #define FMC_PATT_ATTSET_4 (0x10U << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9094 | #define FMC_PATT_ATTSET_5 (0x20U << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9095 | #define FMC_PATT_ATTSET_6 (0x40U << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9096 | #define FMC_PATT_ATTSET_7 (0x80U << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9097 | |
| AnnaBridge | 172:65be27845400 | 9098 | #define FMC_PATT_ATTWAIT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9099 | #define FMC_PATT_ATTWAIT_Msk (0xFFU << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 9100 | #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */ |
| AnnaBridge | 172:65be27845400 | 9101 | #define FMC_PATT_ATTWAIT_0 (0x01U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9102 | #define FMC_PATT_ATTWAIT_1 (0x02U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9103 | #define FMC_PATT_ATTWAIT_2 (0x04U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9104 | #define FMC_PATT_ATTWAIT_3 (0x08U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9105 | #define FMC_PATT_ATTWAIT_4 (0x10U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9106 | #define FMC_PATT_ATTWAIT_5 (0x20U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9107 | #define FMC_PATT_ATTWAIT_6 (0x40U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9108 | #define FMC_PATT_ATTWAIT_7 (0x80U << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9109 | |
| AnnaBridge | 172:65be27845400 | 9110 | #define FMC_PATT_ATTHOLD_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9111 | #define FMC_PATT_ATTHOLD_Msk (0xFFU << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 9112 | #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */ |
| AnnaBridge | 172:65be27845400 | 9113 | #define FMC_PATT_ATTHOLD_0 (0x01U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9114 | #define FMC_PATT_ATTHOLD_1 (0x02U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9115 | #define FMC_PATT_ATTHOLD_2 (0x04U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9116 | #define FMC_PATT_ATTHOLD_3 (0x08U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9117 | #define FMC_PATT_ATTHOLD_4 (0x10U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 9118 | #define FMC_PATT_ATTHOLD_5 (0x20U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 9119 | #define FMC_PATT_ATTHOLD_6 (0x40U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 9120 | #define FMC_PATT_ATTHOLD_7 (0x80U << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 9121 | |
| AnnaBridge | 172:65be27845400 | 9122 | #define FMC_PATT_ATTHIZ_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 9123 | #define FMC_PATT_ATTHIZ_Msk (0xFFU << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 9124 | #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */ |
| AnnaBridge | 172:65be27845400 | 9125 | #define FMC_PATT_ATTHIZ_0 (0x01U << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 9126 | #define FMC_PATT_ATTHIZ_1 (0x02U << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 9127 | #define FMC_PATT_ATTHIZ_2 (0x04U << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 9128 | #define FMC_PATT_ATTHIZ_3 (0x08U << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 9129 | #define FMC_PATT_ATTHIZ_4 (0x10U << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 9130 | #define FMC_PATT_ATTHIZ_5 (0x20U << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 9131 | #define FMC_PATT_ATTHIZ_6 (0x40U << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 9132 | #define FMC_PATT_ATTHIZ_7 (0x80U << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 9133 | |
| AnnaBridge | 172:65be27845400 | 9134 | /****************** Bit definition for FMC_ECCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 9135 | #define FMC_ECCR_ECC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9136 | #define FMC_ECCR_ECC_Msk (0xFFFFFFFFU << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 9137 | #define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */ |
| AnnaBridge | 172:65be27845400 | 9138 | |
| AnnaBridge | 172:65be27845400 | 9139 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 9140 | /* */ |
| AnnaBridge | 172:65be27845400 | 9141 | /* General Purpose IOs (GPIO) */ |
| AnnaBridge | 172:65be27845400 | 9142 | /* */ |
| AnnaBridge | 172:65be27845400 | 9143 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 9144 | /****************** Bits definition for GPIO_MODER register *****************/ |
| AnnaBridge | 172:65be27845400 | 9145 | #define GPIO_MODER_MODE0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9146 | #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 9147 | #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk |
| AnnaBridge | 172:65be27845400 | 9148 | #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9149 | #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9150 | #define GPIO_MODER_MODE1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9151 | #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 9152 | #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk |
| AnnaBridge | 172:65be27845400 | 9153 | #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9154 | #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9155 | #define GPIO_MODER_MODE2_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9156 | #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 9157 | #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk |
| AnnaBridge | 172:65be27845400 | 9158 | #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9159 | #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9160 | #define GPIO_MODER_MODE3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9161 | #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 9162 | #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk |
| AnnaBridge | 172:65be27845400 | 9163 | #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9164 | #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9165 | #define GPIO_MODER_MODE4_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9166 | #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 9167 | #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk |
| AnnaBridge | 172:65be27845400 | 9168 | #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9169 | #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9170 | #define GPIO_MODER_MODE5_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9171 | #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 9172 | #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk |
| AnnaBridge | 172:65be27845400 | 9173 | #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9174 | #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9175 | #define GPIO_MODER_MODE6_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9176 | #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 9177 | #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk |
| AnnaBridge | 172:65be27845400 | 9178 | #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9179 | #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9180 | #define GPIO_MODER_MODE7_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9181 | #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 9182 | #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk |
| AnnaBridge | 172:65be27845400 | 9183 | #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9184 | #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9185 | #define GPIO_MODER_MODE8_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9186 | #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 9187 | #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk |
| AnnaBridge | 172:65be27845400 | 9188 | #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9189 | #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9190 | #define GPIO_MODER_MODE9_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 9191 | #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 9192 | #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk |
| AnnaBridge | 172:65be27845400 | 9193 | #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9194 | #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9195 | #define GPIO_MODER_MODE10_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 9196 | #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 9197 | #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk |
| AnnaBridge | 172:65be27845400 | 9198 | #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 9199 | #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 9200 | #define GPIO_MODER_MODE11_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 9201 | #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 172:65be27845400 | 9202 | #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk |
| AnnaBridge | 172:65be27845400 | 9203 | #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 9204 | #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 9205 | #define GPIO_MODER_MODE12_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 9206 | #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 9207 | #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk |
| AnnaBridge | 172:65be27845400 | 9208 | #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 9209 | #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 9210 | #define GPIO_MODER_MODE13_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 9211 | #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 172:65be27845400 | 9212 | #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk |
| AnnaBridge | 172:65be27845400 | 9213 | #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 9214 | #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 9215 | #define GPIO_MODER_MODE14_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 9216 | #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 9217 | #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk |
| AnnaBridge | 172:65be27845400 | 9218 | #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 9219 | #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 9220 | #define GPIO_MODER_MODE15_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 9221 | #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 172:65be27845400 | 9222 | #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk |
| AnnaBridge | 172:65be27845400 | 9223 | #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 9224 | #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 9225 | |
| AnnaBridge | 172:65be27845400 | 9226 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9227 | #define GPIO_MODER_MODER0 GPIO_MODER_MODE0 |
| AnnaBridge | 172:65be27845400 | 9228 | #define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0 |
| AnnaBridge | 172:65be27845400 | 9229 | #define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1 |
| AnnaBridge | 172:65be27845400 | 9230 | #define GPIO_MODER_MODER1 GPIO_MODER_MODE1 |
| AnnaBridge | 172:65be27845400 | 9231 | #define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0 |
| AnnaBridge | 172:65be27845400 | 9232 | #define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1 |
| AnnaBridge | 172:65be27845400 | 9233 | #define GPIO_MODER_MODER2 GPIO_MODER_MODE2 |
| AnnaBridge | 172:65be27845400 | 9234 | #define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0 |
| AnnaBridge | 172:65be27845400 | 9235 | #define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1 |
| AnnaBridge | 172:65be27845400 | 9236 | #define GPIO_MODER_MODER3 GPIO_MODER_MODE3 |
| AnnaBridge | 172:65be27845400 | 9237 | #define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0 |
| AnnaBridge | 172:65be27845400 | 9238 | #define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1 |
| AnnaBridge | 172:65be27845400 | 9239 | #define GPIO_MODER_MODER4 GPIO_MODER_MODE4 |
| AnnaBridge | 172:65be27845400 | 9240 | #define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0 |
| AnnaBridge | 172:65be27845400 | 9241 | #define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1 |
| AnnaBridge | 172:65be27845400 | 9242 | #define GPIO_MODER_MODER5 GPIO_MODER_MODE5 |
| AnnaBridge | 172:65be27845400 | 9243 | #define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0 |
| AnnaBridge | 172:65be27845400 | 9244 | #define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1 |
| AnnaBridge | 172:65be27845400 | 9245 | #define GPIO_MODER_MODER6 GPIO_MODER_MODE6 |
| AnnaBridge | 172:65be27845400 | 9246 | #define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0 |
| AnnaBridge | 172:65be27845400 | 9247 | #define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1 |
| AnnaBridge | 172:65be27845400 | 9248 | #define GPIO_MODER_MODER7 GPIO_MODER_MODE7 |
| AnnaBridge | 172:65be27845400 | 9249 | #define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0 |
| AnnaBridge | 172:65be27845400 | 9250 | #define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1 |
| AnnaBridge | 172:65be27845400 | 9251 | #define GPIO_MODER_MODER8 GPIO_MODER_MODE8 |
| AnnaBridge | 172:65be27845400 | 9252 | #define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0 |
| AnnaBridge | 172:65be27845400 | 9253 | #define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1 |
| AnnaBridge | 172:65be27845400 | 9254 | #define GPIO_MODER_MODER9 GPIO_MODER_MODE9 |
| AnnaBridge | 172:65be27845400 | 9255 | #define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0 |
| AnnaBridge | 172:65be27845400 | 9256 | #define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1 |
| AnnaBridge | 172:65be27845400 | 9257 | #define GPIO_MODER_MODER10 GPIO_MODER_MODE10 |
| AnnaBridge | 172:65be27845400 | 9258 | #define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0 |
| AnnaBridge | 172:65be27845400 | 9259 | #define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1 |
| AnnaBridge | 172:65be27845400 | 9260 | #define GPIO_MODER_MODER11 GPIO_MODER_MODE11 |
| AnnaBridge | 172:65be27845400 | 9261 | #define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0 |
| AnnaBridge | 172:65be27845400 | 9262 | #define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1 |
| AnnaBridge | 172:65be27845400 | 9263 | #define GPIO_MODER_MODER12 GPIO_MODER_MODE12 |
| AnnaBridge | 172:65be27845400 | 9264 | #define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0 |
| AnnaBridge | 172:65be27845400 | 9265 | #define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1 |
| AnnaBridge | 172:65be27845400 | 9266 | #define GPIO_MODER_MODER13 GPIO_MODER_MODE13 |
| AnnaBridge | 172:65be27845400 | 9267 | #define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0 |
| AnnaBridge | 172:65be27845400 | 9268 | #define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1 |
| AnnaBridge | 172:65be27845400 | 9269 | #define GPIO_MODER_MODER14 GPIO_MODER_MODE14 |
| AnnaBridge | 172:65be27845400 | 9270 | #define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0 |
| AnnaBridge | 172:65be27845400 | 9271 | #define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1 |
| AnnaBridge | 172:65be27845400 | 9272 | #define GPIO_MODER_MODER15 GPIO_MODER_MODE15 |
| AnnaBridge | 172:65be27845400 | 9273 | #define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0 |
| AnnaBridge | 172:65be27845400 | 9274 | #define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1 |
| AnnaBridge | 172:65be27845400 | 9275 | |
| AnnaBridge | 172:65be27845400 | 9276 | /****************** Bits definition for GPIO_OTYPER register ****************/ |
| AnnaBridge | 172:65be27845400 | 9277 | #define GPIO_OTYPER_OT0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9278 | #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9279 | #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk |
| AnnaBridge | 172:65be27845400 | 9280 | #define GPIO_OTYPER_OT1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 9281 | #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9282 | #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk |
| AnnaBridge | 172:65be27845400 | 9283 | #define GPIO_OTYPER_OT2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9284 | #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9285 | #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk |
| AnnaBridge | 172:65be27845400 | 9286 | #define GPIO_OTYPER_OT3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 9287 | #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9288 | #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk |
| AnnaBridge | 172:65be27845400 | 9289 | #define GPIO_OTYPER_OT4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9290 | #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9291 | #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk |
| AnnaBridge | 172:65be27845400 | 9292 | #define GPIO_OTYPER_OT5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 9293 | #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9294 | #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk |
| AnnaBridge | 172:65be27845400 | 9295 | #define GPIO_OTYPER_OT6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9296 | #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9297 | #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk |
| AnnaBridge | 172:65be27845400 | 9298 | #define GPIO_OTYPER_OT7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 9299 | #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9300 | #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk |
| AnnaBridge | 172:65be27845400 | 9301 | #define GPIO_OTYPER_OT8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9302 | #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9303 | #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk |
| AnnaBridge | 172:65be27845400 | 9304 | #define GPIO_OTYPER_OT9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 9305 | #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9306 | #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk |
| AnnaBridge | 172:65be27845400 | 9307 | #define GPIO_OTYPER_OT10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9308 | #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9309 | #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk |
| AnnaBridge | 172:65be27845400 | 9310 | #define GPIO_OTYPER_OT11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 9311 | #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9312 | #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk |
| AnnaBridge | 172:65be27845400 | 9313 | #define GPIO_OTYPER_OT12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9314 | #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9315 | #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk |
| AnnaBridge | 172:65be27845400 | 9316 | #define GPIO_OTYPER_OT13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 9317 | #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9318 | #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk |
| AnnaBridge | 172:65be27845400 | 9319 | #define GPIO_OTYPER_OT14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9320 | #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9321 | #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk |
| AnnaBridge | 172:65be27845400 | 9322 | #define GPIO_OTYPER_OT15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 9323 | #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9324 | #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk |
| AnnaBridge | 172:65be27845400 | 9325 | |
| AnnaBridge | 172:65be27845400 | 9326 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9327 | #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 |
| AnnaBridge | 172:65be27845400 | 9328 | #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 |
| AnnaBridge | 172:65be27845400 | 9329 | #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 |
| AnnaBridge | 172:65be27845400 | 9330 | #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 |
| AnnaBridge | 172:65be27845400 | 9331 | #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 |
| AnnaBridge | 172:65be27845400 | 9332 | #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 |
| AnnaBridge | 172:65be27845400 | 9333 | #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 |
| AnnaBridge | 172:65be27845400 | 9334 | #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 |
| AnnaBridge | 172:65be27845400 | 9335 | #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 |
| AnnaBridge | 172:65be27845400 | 9336 | #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 |
| AnnaBridge | 172:65be27845400 | 9337 | #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 |
| AnnaBridge | 172:65be27845400 | 9338 | #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 |
| AnnaBridge | 172:65be27845400 | 9339 | #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 |
| AnnaBridge | 172:65be27845400 | 9340 | #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 |
| AnnaBridge | 172:65be27845400 | 9341 | #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 |
| AnnaBridge | 172:65be27845400 | 9342 | #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 |
| AnnaBridge | 172:65be27845400 | 9343 | |
| AnnaBridge | 172:65be27845400 | 9344 | /****************** Bits definition for GPIO_OSPEEDR register ***************/ |
| AnnaBridge | 172:65be27845400 | 9345 | #define GPIO_OSPEEDR_OSPEED0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9346 | #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 9347 | #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk |
| AnnaBridge | 172:65be27845400 | 9348 | #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9349 | #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9350 | #define GPIO_OSPEEDR_OSPEED1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9351 | #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 9352 | #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk |
| AnnaBridge | 172:65be27845400 | 9353 | #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9354 | #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9355 | #define GPIO_OSPEEDR_OSPEED2_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9356 | #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 9357 | #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk |
| AnnaBridge | 172:65be27845400 | 9358 | #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9359 | #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9360 | #define GPIO_OSPEEDR_OSPEED3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9361 | #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 9362 | #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk |
| AnnaBridge | 172:65be27845400 | 9363 | #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9364 | #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9365 | #define GPIO_OSPEEDR_OSPEED4_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9366 | #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 9367 | #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk |
| AnnaBridge | 172:65be27845400 | 9368 | #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9369 | #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9370 | #define GPIO_OSPEEDR_OSPEED5_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9371 | #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 9372 | #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk |
| AnnaBridge | 172:65be27845400 | 9373 | #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9374 | #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9375 | #define GPIO_OSPEEDR_OSPEED6_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9376 | #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 9377 | #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk |
| AnnaBridge | 172:65be27845400 | 9378 | #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9379 | #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9380 | #define GPIO_OSPEEDR_OSPEED7_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9381 | #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 9382 | #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk |
| AnnaBridge | 172:65be27845400 | 9383 | #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9384 | #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9385 | #define GPIO_OSPEEDR_OSPEED8_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9386 | #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 9387 | #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk |
| AnnaBridge | 172:65be27845400 | 9388 | #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9389 | #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9390 | #define GPIO_OSPEEDR_OSPEED9_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 9391 | #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 9392 | #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk |
| AnnaBridge | 172:65be27845400 | 9393 | #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9394 | #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9395 | #define GPIO_OSPEEDR_OSPEED10_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 9396 | #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 9397 | #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk |
| AnnaBridge | 172:65be27845400 | 9398 | #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 9399 | #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 9400 | #define GPIO_OSPEEDR_OSPEED11_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 9401 | #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 172:65be27845400 | 9402 | #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk |
| AnnaBridge | 172:65be27845400 | 9403 | #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 9404 | #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 9405 | #define GPIO_OSPEEDR_OSPEED12_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 9406 | #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 9407 | #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk |
| AnnaBridge | 172:65be27845400 | 9408 | #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 9409 | #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 9410 | #define GPIO_OSPEEDR_OSPEED13_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 9411 | #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 172:65be27845400 | 9412 | #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk |
| AnnaBridge | 172:65be27845400 | 9413 | #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 9414 | #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 9415 | #define GPIO_OSPEEDR_OSPEED14_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 9416 | #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 9417 | #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk |
| AnnaBridge | 172:65be27845400 | 9418 | #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 9419 | #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 9420 | #define GPIO_OSPEEDR_OSPEED15_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 9421 | #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 172:65be27845400 | 9422 | #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk |
| AnnaBridge | 172:65be27845400 | 9423 | #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 9424 | #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 9425 | |
| AnnaBridge | 172:65be27845400 | 9426 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9427 | #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 |
| AnnaBridge | 172:65be27845400 | 9428 | #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 |
| AnnaBridge | 172:65be27845400 | 9429 | #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 |
| AnnaBridge | 172:65be27845400 | 9430 | #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 |
| AnnaBridge | 172:65be27845400 | 9431 | #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 |
| AnnaBridge | 172:65be27845400 | 9432 | #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 |
| AnnaBridge | 172:65be27845400 | 9433 | #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 |
| AnnaBridge | 172:65be27845400 | 9434 | #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 |
| AnnaBridge | 172:65be27845400 | 9435 | #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 |
| AnnaBridge | 172:65be27845400 | 9436 | #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 |
| AnnaBridge | 172:65be27845400 | 9437 | #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 |
| AnnaBridge | 172:65be27845400 | 9438 | #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 |
| AnnaBridge | 172:65be27845400 | 9439 | #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 |
| AnnaBridge | 172:65be27845400 | 9440 | #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 |
| AnnaBridge | 172:65be27845400 | 9441 | #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 |
| AnnaBridge | 172:65be27845400 | 9442 | #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 |
| AnnaBridge | 172:65be27845400 | 9443 | #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 |
| AnnaBridge | 172:65be27845400 | 9444 | #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 |
| AnnaBridge | 172:65be27845400 | 9445 | #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 |
| AnnaBridge | 172:65be27845400 | 9446 | #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 |
| AnnaBridge | 172:65be27845400 | 9447 | #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 |
| AnnaBridge | 172:65be27845400 | 9448 | #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 |
| AnnaBridge | 172:65be27845400 | 9449 | #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 |
| AnnaBridge | 172:65be27845400 | 9450 | #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 |
| AnnaBridge | 172:65be27845400 | 9451 | #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 |
| AnnaBridge | 172:65be27845400 | 9452 | #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 |
| AnnaBridge | 172:65be27845400 | 9453 | #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 |
| AnnaBridge | 172:65be27845400 | 9454 | #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 |
| AnnaBridge | 172:65be27845400 | 9455 | #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 |
| AnnaBridge | 172:65be27845400 | 9456 | #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 |
| AnnaBridge | 172:65be27845400 | 9457 | #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 |
| AnnaBridge | 172:65be27845400 | 9458 | #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 |
| AnnaBridge | 172:65be27845400 | 9459 | #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 |
| AnnaBridge | 172:65be27845400 | 9460 | #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 |
| AnnaBridge | 172:65be27845400 | 9461 | #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 |
| AnnaBridge | 172:65be27845400 | 9462 | #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 |
| AnnaBridge | 172:65be27845400 | 9463 | #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 |
| AnnaBridge | 172:65be27845400 | 9464 | #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 |
| AnnaBridge | 172:65be27845400 | 9465 | #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 |
| AnnaBridge | 172:65be27845400 | 9466 | #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 |
| AnnaBridge | 172:65be27845400 | 9467 | #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 |
| AnnaBridge | 172:65be27845400 | 9468 | #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 |
| AnnaBridge | 172:65be27845400 | 9469 | #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 |
| AnnaBridge | 172:65be27845400 | 9470 | #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 |
| AnnaBridge | 172:65be27845400 | 9471 | #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 |
| AnnaBridge | 172:65be27845400 | 9472 | #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 |
| AnnaBridge | 172:65be27845400 | 9473 | #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 |
| AnnaBridge | 172:65be27845400 | 9474 | #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 |
| AnnaBridge | 172:65be27845400 | 9475 | |
| AnnaBridge | 172:65be27845400 | 9476 | /****************** Bits definition for GPIO_PUPDR register *****************/ |
| AnnaBridge | 172:65be27845400 | 9477 | #define GPIO_PUPDR_PUPD0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9478 | #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 9479 | #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk |
| AnnaBridge | 172:65be27845400 | 9480 | #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9481 | #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9482 | #define GPIO_PUPDR_PUPD1_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9483 | #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 9484 | #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk |
| AnnaBridge | 172:65be27845400 | 9485 | #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9486 | #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9487 | #define GPIO_PUPDR_PUPD2_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9488 | #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 9489 | #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk |
| AnnaBridge | 172:65be27845400 | 9490 | #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9491 | #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9492 | #define GPIO_PUPDR_PUPD3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9493 | #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 9494 | #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk |
| AnnaBridge | 172:65be27845400 | 9495 | #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9496 | #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9497 | #define GPIO_PUPDR_PUPD4_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9498 | #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 9499 | #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk |
| AnnaBridge | 172:65be27845400 | 9500 | #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9501 | #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9502 | #define GPIO_PUPDR_PUPD5_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9503 | #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 9504 | #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk |
| AnnaBridge | 172:65be27845400 | 9505 | #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9506 | #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9507 | #define GPIO_PUPDR_PUPD6_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9508 | #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 9509 | #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk |
| AnnaBridge | 172:65be27845400 | 9510 | #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9511 | #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9512 | #define GPIO_PUPDR_PUPD7_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9513 | #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 9514 | #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk |
| AnnaBridge | 172:65be27845400 | 9515 | #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9516 | #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9517 | #define GPIO_PUPDR_PUPD8_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9518 | #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 9519 | #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk |
| AnnaBridge | 172:65be27845400 | 9520 | #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9521 | #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9522 | #define GPIO_PUPDR_PUPD9_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 9523 | #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 9524 | #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk |
| AnnaBridge | 172:65be27845400 | 9525 | #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9526 | #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9527 | #define GPIO_PUPDR_PUPD10_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 9528 | #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 9529 | #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk |
| AnnaBridge | 172:65be27845400 | 9530 | #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 9531 | #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 9532 | #define GPIO_PUPDR_PUPD11_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 9533 | #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ |
| AnnaBridge | 172:65be27845400 | 9534 | #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk |
| AnnaBridge | 172:65be27845400 | 9535 | #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 9536 | #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 9537 | #define GPIO_PUPDR_PUPD12_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 9538 | #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 9539 | #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk |
| AnnaBridge | 172:65be27845400 | 9540 | #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 9541 | #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 9542 | #define GPIO_PUPDR_PUPD13_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 9543 | #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 172:65be27845400 | 9544 | #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk |
| AnnaBridge | 172:65be27845400 | 9545 | #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 9546 | #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 9547 | #define GPIO_PUPDR_PUPD14_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 9548 | #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 9549 | #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk |
| AnnaBridge | 172:65be27845400 | 9550 | #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 9551 | #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 9552 | #define GPIO_PUPDR_PUPD15_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 9553 | #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ |
| AnnaBridge | 172:65be27845400 | 9554 | #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk |
| AnnaBridge | 172:65be27845400 | 9555 | #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 9556 | #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 9557 | |
| AnnaBridge | 172:65be27845400 | 9558 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9559 | #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 |
| AnnaBridge | 172:65be27845400 | 9560 | #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 |
| AnnaBridge | 172:65be27845400 | 9561 | #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 |
| AnnaBridge | 172:65be27845400 | 9562 | #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 |
| AnnaBridge | 172:65be27845400 | 9563 | #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 |
| AnnaBridge | 172:65be27845400 | 9564 | #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 |
| AnnaBridge | 172:65be27845400 | 9565 | #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 |
| AnnaBridge | 172:65be27845400 | 9566 | #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 |
| AnnaBridge | 172:65be27845400 | 9567 | #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 |
| AnnaBridge | 172:65be27845400 | 9568 | #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 |
| AnnaBridge | 172:65be27845400 | 9569 | #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 |
| AnnaBridge | 172:65be27845400 | 9570 | #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 |
| AnnaBridge | 172:65be27845400 | 9571 | #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 |
| AnnaBridge | 172:65be27845400 | 9572 | #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 |
| AnnaBridge | 172:65be27845400 | 9573 | #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 |
| AnnaBridge | 172:65be27845400 | 9574 | #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 |
| AnnaBridge | 172:65be27845400 | 9575 | #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 |
| AnnaBridge | 172:65be27845400 | 9576 | #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 |
| AnnaBridge | 172:65be27845400 | 9577 | #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 |
| AnnaBridge | 172:65be27845400 | 9578 | #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 |
| AnnaBridge | 172:65be27845400 | 9579 | #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 |
| AnnaBridge | 172:65be27845400 | 9580 | #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 |
| AnnaBridge | 172:65be27845400 | 9581 | #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 |
| AnnaBridge | 172:65be27845400 | 9582 | #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 |
| AnnaBridge | 172:65be27845400 | 9583 | #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 |
| AnnaBridge | 172:65be27845400 | 9584 | #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 |
| AnnaBridge | 172:65be27845400 | 9585 | #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 |
| AnnaBridge | 172:65be27845400 | 9586 | #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 |
| AnnaBridge | 172:65be27845400 | 9587 | #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 |
| AnnaBridge | 172:65be27845400 | 9588 | #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 |
| AnnaBridge | 172:65be27845400 | 9589 | #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 |
| AnnaBridge | 172:65be27845400 | 9590 | #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 |
| AnnaBridge | 172:65be27845400 | 9591 | #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 |
| AnnaBridge | 172:65be27845400 | 9592 | #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 |
| AnnaBridge | 172:65be27845400 | 9593 | #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 |
| AnnaBridge | 172:65be27845400 | 9594 | #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 |
| AnnaBridge | 172:65be27845400 | 9595 | #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 |
| AnnaBridge | 172:65be27845400 | 9596 | #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 |
| AnnaBridge | 172:65be27845400 | 9597 | #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 |
| AnnaBridge | 172:65be27845400 | 9598 | #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 |
| AnnaBridge | 172:65be27845400 | 9599 | #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 |
| AnnaBridge | 172:65be27845400 | 9600 | #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 |
| AnnaBridge | 172:65be27845400 | 9601 | #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 |
| AnnaBridge | 172:65be27845400 | 9602 | #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 |
| AnnaBridge | 172:65be27845400 | 9603 | #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 |
| AnnaBridge | 172:65be27845400 | 9604 | #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 |
| AnnaBridge | 172:65be27845400 | 9605 | #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 |
| AnnaBridge | 172:65be27845400 | 9606 | #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 |
| AnnaBridge | 172:65be27845400 | 9607 | |
| AnnaBridge | 172:65be27845400 | 9608 | /****************** Bits definition for GPIO_IDR register *******************/ |
| AnnaBridge | 172:65be27845400 | 9609 | #define GPIO_IDR_ID0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9610 | #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9611 | #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk |
| AnnaBridge | 172:65be27845400 | 9612 | #define GPIO_IDR_ID1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 9613 | #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9614 | #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk |
| AnnaBridge | 172:65be27845400 | 9615 | #define GPIO_IDR_ID2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9616 | #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9617 | #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk |
| AnnaBridge | 172:65be27845400 | 9618 | #define GPIO_IDR_ID3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 9619 | #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9620 | #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk |
| AnnaBridge | 172:65be27845400 | 9621 | #define GPIO_IDR_ID4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9622 | #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9623 | #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk |
| AnnaBridge | 172:65be27845400 | 9624 | #define GPIO_IDR_ID5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 9625 | #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9626 | #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk |
| AnnaBridge | 172:65be27845400 | 9627 | #define GPIO_IDR_ID6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9628 | #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9629 | #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk |
| AnnaBridge | 172:65be27845400 | 9630 | #define GPIO_IDR_ID7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 9631 | #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9632 | #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk |
| AnnaBridge | 172:65be27845400 | 9633 | #define GPIO_IDR_ID8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9634 | #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9635 | #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk |
| AnnaBridge | 172:65be27845400 | 9636 | #define GPIO_IDR_ID9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 9637 | #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9638 | #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk |
| AnnaBridge | 172:65be27845400 | 9639 | #define GPIO_IDR_ID10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9640 | #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9641 | #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk |
| AnnaBridge | 172:65be27845400 | 9642 | #define GPIO_IDR_ID11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 9643 | #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9644 | #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk |
| AnnaBridge | 172:65be27845400 | 9645 | #define GPIO_IDR_ID12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9646 | #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9647 | #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk |
| AnnaBridge | 172:65be27845400 | 9648 | #define GPIO_IDR_ID13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 9649 | #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9650 | #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk |
| AnnaBridge | 172:65be27845400 | 9651 | #define GPIO_IDR_ID14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9652 | #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9653 | #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk |
| AnnaBridge | 172:65be27845400 | 9654 | #define GPIO_IDR_ID15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 9655 | #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9656 | #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk |
| AnnaBridge | 172:65be27845400 | 9657 | |
| AnnaBridge | 172:65be27845400 | 9658 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9659 | #define GPIO_IDR_IDR_0 GPIO_IDR_ID0 |
| AnnaBridge | 172:65be27845400 | 9660 | #define GPIO_IDR_IDR_1 GPIO_IDR_ID1 |
| AnnaBridge | 172:65be27845400 | 9661 | #define GPIO_IDR_IDR_2 GPIO_IDR_ID2 |
| AnnaBridge | 172:65be27845400 | 9662 | #define GPIO_IDR_IDR_3 GPIO_IDR_ID3 |
| AnnaBridge | 172:65be27845400 | 9663 | #define GPIO_IDR_IDR_4 GPIO_IDR_ID4 |
| AnnaBridge | 172:65be27845400 | 9664 | #define GPIO_IDR_IDR_5 GPIO_IDR_ID5 |
| AnnaBridge | 172:65be27845400 | 9665 | #define GPIO_IDR_IDR_6 GPIO_IDR_ID6 |
| AnnaBridge | 172:65be27845400 | 9666 | #define GPIO_IDR_IDR_7 GPIO_IDR_ID7 |
| AnnaBridge | 172:65be27845400 | 9667 | #define GPIO_IDR_IDR_8 GPIO_IDR_ID8 |
| AnnaBridge | 172:65be27845400 | 9668 | #define GPIO_IDR_IDR_9 GPIO_IDR_ID9 |
| AnnaBridge | 172:65be27845400 | 9669 | #define GPIO_IDR_IDR_10 GPIO_IDR_ID10 |
| AnnaBridge | 172:65be27845400 | 9670 | #define GPIO_IDR_IDR_11 GPIO_IDR_ID11 |
| AnnaBridge | 172:65be27845400 | 9671 | #define GPIO_IDR_IDR_12 GPIO_IDR_ID12 |
| AnnaBridge | 172:65be27845400 | 9672 | #define GPIO_IDR_IDR_13 GPIO_IDR_ID13 |
| AnnaBridge | 172:65be27845400 | 9673 | #define GPIO_IDR_IDR_14 GPIO_IDR_ID14 |
| AnnaBridge | 172:65be27845400 | 9674 | #define GPIO_IDR_IDR_15 GPIO_IDR_ID15 |
| AnnaBridge | 172:65be27845400 | 9675 | |
| AnnaBridge | 172:65be27845400 | 9676 | /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ |
| AnnaBridge | 172:65be27845400 | 9677 | #define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0 |
| AnnaBridge | 172:65be27845400 | 9678 | #define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1 |
| AnnaBridge | 172:65be27845400 | 9679 | #define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2 |
| AnnaBridge | 172:65be27845400 | 9680 | #define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3 |
| AnnaBridge | 172:65be27845400 | 9681 | #define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4 |
| AnnaBridge | 172:65be27845400 | 9682 | #define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5 |
| AnnaBridge | 172:65be27845400 | 9683 | #define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6 |
| AnnaBridge | 172:65be27845400 | 9684 | #define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7 |
| AnnaBridge | 172:65be27845400 | 9685 | #define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8 |
| AnnaBridge | 172:65be27845400 | 9686 | #define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9 |
| AnnaBridge | 172:65be27845400 | 9687 | #define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10 |
| AnnaBridge | 172:65be27845400 | 9688 | #define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11 |
| AnnaBridge | 172:65be27845400 | 9689 | #define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12 |
| AnnaBridge | 172:65be27845400 | 9690 | #define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13 |
| AnnaBridge | 172:65be27845400 | 9691 | #define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14 |
| AnnaBridge | 172:65be27845400 | 9692 | #define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15 |
| AnnaBridge | 172:65be27845400 | 9693 | |
| AnnaBridge | 172:65be27845400 | 9694 | /****************** Bits definition for GPIO_ODR register *******************/ |
| AnnaBridge | 172:65be27845400 | 9695 | #define GPIO_ODR_OD0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9696 | #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9697 | #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk |
| AnnaBridge | 172:65be27845400 | 9698 | #define GPIO_ODR_OD1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 9699 | #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9700 | #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk |
| AnnaBridge | 172:65be27845400 | 9701 | #define GPIO_ODR_OD2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9702 | #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9703 | #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk |
| AnnaBridge | 172:65be27845400 | 9704 | #define GPIO_ODR_OD3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 9705 | #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9706 | #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk |
| AnnaBridge | 172:65be27845400 | 9707 | #define GPIO_ODR_OD4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9708 | #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9709 | #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk |
| AnnaBridge | 172:65be27845400 | 9710 | #define GPIO_ODR_OD5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 9711 | #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9712 | #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk |
| AnnaBridge | 172:65be27845400 | 9713 | #define GPIO_ODR_OD6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9714 | #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9715 | #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk |
| AnnaBridge | 172:65be27845400 | 9716 | #define GPIO_ODR_OD7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 9717 | #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9718 | #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk |
| AnnaBridge | 172:65be27845400 | 9719 | #define GPIO_ODR_OD8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9720 | #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9721 | #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk |
| AnnaBridge | 172:65be27845400 | 9722 | #define GPIO_ODR_OD9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 9723 | #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9724 | #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk |
| AnnaBridge | 172:65be27845400 | 9725 | #define GPIO_ODR_OD10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9726 | #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9727 | #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk |
| AnnaBridge | 172:65be27845400 | 9728 | #define GPIO_ODR_OD11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 9729 | #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9730 | #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk |
| AnnaBridge | 172:65be27845400 | 9731 | #define GPIO_ODR_OD12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9732 | #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9733 | #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk |
| AnnaBridge | 172:65be27845400 | 9734 | #define GPIO_ODR_OD13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 9735 | #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9736 | #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk |
| AnnaBridge | 172:65be27845400 | 9737 | #define GPIO_ODR_OD14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9738 | #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9739 | #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk |
| AnnaBridge | 172:65be27845400 | 9740 | #define GPIO_ODR_OD15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 9741 | #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9742 | #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk |
| AnnaBridge | 172:65be27845400 | 9743 | |
| AnnaBridge | 172:65be27845400 | 9744 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9745 | #define GPIO_ODR_ODR_0 GPIO_ODR_OD0 |
| AnnaBridge | 172:65be27845400 | 9746 | #define GPIO_ODR_ODR_1 GPIO_ODR_OD1 |
| AnnaBridge | 172:65be27845400 | 9747 | #define GPIO_ODR_ODR_2 GPIO_ODR_OD2 |
| AnnaBridge | 172:65be27845400 | 9748 | #define GPIO_ODR_ODR_3 GPIO_ODR_OD3 |
| AnnaBridge | 172:65be27845400 | 9749 | #define GPIO_ODR_ODR_4 GPIO_ODR_OD4 |
| AnnaBridge | 172:65be27845400 | 9750 | #define GPIO_ODR_ODR_5 GPIO_ODR_OD5 |
| AnnaBridge | 172:65be27845400 | 9751 | #define GPIO_ODR_ODR_6 GPIO_ODR_OD6 |
| AnnaBridge | 172:65be27845400 | 9752 | #define GPIO_ODR_ODR_7 GPIO_ODR_OD7 |
| AnnaBridge | 172:65be27845400 | 9753 | #define GPIO_ODR_ODR_8 GPIO_ODR_OD8 |
| AnnaBridge | 172:65be27845400 | 9754 | #define GPIO_ODR_ODR_9 GPIO_ODR_OD9 |
| AnnaBridge | 172:65be27845400 | 9755 | #define GPIO_ODR_ODR_10 GPIO_ODR_OD10 |
| AnnaBridge | 172:65be27845400 | 9756 | #define GPIO_ODR_ODR_11 GPIO_ODR_OD11 |
| AnnaBridge | 172:65be27845400 | 9757 | #define GPIO_ODR_ODR_12 GPIO_ODR_OD12 |
| AnnaBridge | 172:65be27845400 | 9758 | #define GPIO_ODR_ODR_13 GPIO_ODR_OD13 |
| AnnaBridge | 172:65be27845400 | 9759 | #define GPIO_ODR_ODR_14 GPIO_ODR_OD14 |
| AnnaBridge | 172:65be27845400 | 9760 | #define GPIO_ODR_ODR_15 GPIO_ODR_OD15 |
| AnnaBridge | 172:65be27845400 | 9761 | |
| AnnaBridge | 172:65be27845400 | 9762 | /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ |
| AnnaBridge | 172:65be27845400 | 9763 | #define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0 |
| AnnaBridge | 172:65be27845400 | 9764 | #define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1 |
| AnnaBridge | 172:65be27845400 | 9765 | #define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2 |
| AnnaBridge | 172:65be27845400 | 9766 | #define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3 |
| AnnaBridge | 172:65be27845400 | 9767 | #define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4 |
| AnnaBridge | 172:65be27845400 | 9768 | #define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5 |
| AnnaBridge | 172:65be27845400 | 9769 | #define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6 |
| AnnaBridge | 172:65be27845400 | 9770 | #define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7 |
| AnnaBridge | 172:65be27845400 | 9771 | #define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8 |
| AnnaBridge | 172:65be27845400 | 9772 | #define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9 |
| AnnaBridge | 172:65be27845400 | 9773 | #define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10 |
| AnnaBridge | 172:65be27845400 | 9774 | #define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11 |
| AnnaBridge | 172:65be27845400 | 9775 | #define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12 |
| AnnaBridge | 172:65be27845400 | 9776 | #define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13 |
| AnnaBridge | 172:65be27845400 | 9777 | #define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14 |
| AnnaBridge | 172:65be27845400 | 9778 | #define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15 |
| AnnaBridge | 172:65be27845400 | 9779 | |
| AnnaBridge | 172:65be27845400 | 9780 | /****************** Bits definition for GPIO_BSRR register ******************/ |
| AnnaBridge | 172:65be27845400 | 9781 | #define GPIO_BSRR_BS0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9782 | #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9783 | #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk |
| AnnaBridge | 172:65be27845400 | 9784 | #define GPIO_BSRR_BS1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 9785 | #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9786 | #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk |
| AnnaBridge | 172:65be27845400 | 9787 | #define GPIO_BSRR_BS2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9788 | #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9789 | #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk |
| AnnaBridge | 172:65be27845400 | 9790 | #define GPIO_BSRR_BS3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 9791 | #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9792 | #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk |
| AnnaBridge | 172:65be27845400 | 9793 | #define GPIO_BSRR_BS4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9794 | #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9795 | #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk |
| AnnaBridge | 172:65be27845400 | 9796 | #define GPIO_BSRR_BS5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 9797 | #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9798 | #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk |
| AnnaBridge | 172:65be27845400 | 9799 | #define GPIO_BSRR_BS6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9800 | #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9801 | #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk |
| AnnaBridge | 172:65be27845400 | 9802 | #define GPIO_BSRR_BS7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 9803 | #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9804 | #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk |
| AnnaBridge | 172:65be27845400 | 9805 | #define GPIO_BSRR_BS8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9806 | #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9807 | #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk |
| AnnaBridge | 172:65be27845400 | 9808 | #define GPIO_BSRR_BS9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 9809 | #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9810 | #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk |
| AnnaBridge | 172:65be27845400 | 9811 | #define GPIO_BSRR_BS10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9812 | #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9813 | #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk |
| AnnaBridge | 172:65be27845400 | 9814 | #define GPIO_BSRR_BS11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 9815 | #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9816 | #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk |
| AnnaBridge | 172:65be27845400 | 9817 | #define GPIO_BSRR_BS12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9818 | #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9819 | #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk |
| AnnaBridge | 172:65be27845400 | 9820 | #define GPIO_BSRR_BS13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 9821 | #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9822 | #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk |
| AnnaBridge | 172:65be27845400 | 9823 | #define GPIO_BSRR_BS14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9824 | #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9825 | #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk |
| AnnaBridge | 172:65be27845400 | 9826 | #define GPIO_BSRR_BS15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 9827 | #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9828 | #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk |
| AnnaBridge | 172:65be27845400 | 9829 | #define GPIO_BSRR_BR0_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9830 | #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9831 | #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk |
| AnnaBridge | 172:65be27845400 | 9832 | #define GPIO_BSRR_BR1_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 9833 | #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9834 | #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk |
| AnnaBridge | 172:65be27845400 | 9835 | #define GPIO_BSRR_BR2_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 9836 | #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 9837 | #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk |
| AnnaBridge | 172:65be27845400 | 9838 | #define GPIO_BSRR_BR3_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 9839 | #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 9840 | #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk |
| AnnaBridge | 172:65be27845400 | 9841 | #define GPIO_BSRR_BR4_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 9842 | #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 9843 | #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk |
| AnnaBridge | 172:65be27845400 | 9844 | #define GPIO_BSRR_BR5_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 9845 | #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 9846 | #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk |
| AnnaBridge | 172:65be27845400 | 9847 | #define GPIO_BSRR_BR6_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 9848 | #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 9849 | #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk |
| AnnaBridge | 172:65be27845400 | 9850 | #define GPIO_BSRR_BR7_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 9851 | #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 9852 | #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk |
| AnnaBridge | 172:65be27845400 | 9853 | #define GPIO_BSRR_BR8_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 9854 | #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 9855 | #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk |
| AnnaBridge | 172:65be27845400 | 9856 | #define GPIO_BSRR_BR9_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 9857 | #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 9858 | #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk |
| AnnaBridge | 172:65be27845400 | 9859 | #define GPIO_BSRR_BR10_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 9860 | #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 9861 | #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk |
| AnnaBridge | 172:65be27845400 | 9862 | #define GPIO_BSRR_BR11_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 9863 | #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 9864 | #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk |
| AnnaBridge | 172:65be27845400 | 9865 | #define GPIO_BSRR_BR12_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 9866 | #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 9867 | #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk |
| AnnaBridge | 172:65be27845400 | 9868 | #define GPIO_BSRR_BR13_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 9869 | #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 9870 | #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk |
| AnnaBridge | 172:65be27845400 | 9871 | #define GPIO_BSRR_BR14_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 9872 | #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 9873 | #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk |
| AnnaBridge | 172:65be27845400 | 9874 | #define GPIO_BSRR_BR15_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 9875 | #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 9876 | #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk |
| AnnaBridge | 172:65be27845400 | 9877 | |
| AnnaBridge | 172:65be27845400 | 9878 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 9879 | #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 |
| AnnaBridge | 172:65be27845400 | 9880 | #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 |
| AnnaBridge | 172:65be27845400 | 9881 | #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 |
| AnnaBridge | 172:65be27845400 | 9882 | #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 |
| AnnaBridge | 172:65be27845400 | 9883 | #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 |
| AnnaBridge | 172:65be27845400 | 9884 | #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 |
| AnnaBridge | 172:65be27845400 | 9885 | #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 |
| AnnaBridge | 172:65be27845400 | 9886 | #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 |
| AnnaBridge | 172:65be27845400 | 9887 | #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 |
| AnnaBridge | 172:65be27845400 | 9888 | #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 |
| AnnaBridge | 172:65be27845400 | 9889 | #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 |
| AnnaBridge | 172:65be27845400 | 9890 | #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 |
| AnnaBridge | 172:65be27845400 | 9891 | #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 |
| AnnaBridge | 172:65be27845400 | 9892 | #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 |
| AnnaBridge | 172:65be27845400 | 9893 | #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 |
| AnnaBridge | 172:65be27845400 | 9894 | #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 |
| AnnaBridge | 172:65be27845400 | 9895 | #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 |
| AnnaBridge | 172:65be27845400 | 9896 | #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 |
| AnnaBridge | 172:65be27845400 | 9897 | #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 |
| AnnaBridge | 172:65be27845400 | 9898 | #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 |
| AnnaBridge | 172:65be27845400 | 9899 | #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 |
| AnnaBridge | 172:65be27845400 | 9900 | #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 |
| AnnaBridge | 172:65be27845400 | 9901 | #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 |
| AnnaBridge | 172:65be27845400 | 9902 | #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 |
| AnnaBridge | 172:65be27845400 | 9903 | #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 |
| AnnaBridge | 172:65be27845400 | 9904 | #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 |
| AnnaBridge | 172:65be27845400 | 9905 | #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 |
| AnnaBridge | 172:65be27845400 | 9906 | #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 |
| AnnaBridge | 172:65be27845400 | 9907 | #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 |
| AnnaBridge | 172:65be27845400 | 9908 | #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 |
| AnnaBridge | 172:65be27845400 | 9909 | #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 |
| AnnaBridge | 172:65be27845400 | 9910 | #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 |
| AnnaBridge | 172:65be27845400 | 9911 | |
| AnnaBridge | 172:65be27845400 | 9912 | /****************** Bit definition for GPIO_LCKR register *********************/ |
| AnnaBridge | 172:65be27845400 | 9913 | #define GPIO_LCKR_LCK0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9914 | #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9915 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
| AnnaBridge | 172:65be27845400 | 9916 | #define GPIO_LCKR_LCK1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 9917 | #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9918 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
| AnnaBridge | 172:65be27845400 | 9919 | #define GPIO_LCKR_LCK2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 9920 | #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9921 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
| AnnaBridge | 172:65be27845400 | 9922 | #define GPIO_LCKR_LCK3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 9923 | #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9924 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
| AnnaBridge | 172:65be27845400 | 9925 | #define GPIO_LCKR_LCK4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9926 | #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9927 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
| AnnaBridge | 172:65be27845400 | 9928 | #define GPIO_LCKR_LCK5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 9929 | #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9930 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
| AnnaBridge | 172:65be27845400 | 9931 | #define GPIO_LCKR_LCK6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 9932 | #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9933 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
| AnnaBridge | 172:65be27845400 | 9934 | #define GPIO_LCKR_LCK7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 9935 | #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9936 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
| AnnaBridge | 172:65be27845400 | 9937 | #define GPIO_LCKR_LCK8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9938 | #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9939 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
| AnnaBridge | 172:65be27845400 | 9940 | #define GPIO_LCKR_LCK9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 9941 | #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9942 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
| AnnaBridge | 172:65be27845400 | 9943 | #define GPIO_LCKR_LCK10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 9944 | #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9945 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
| AnnaBridge | 172:65be27845400 | 9946 | #define GPIO_LCKR_LCK11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 9947 | #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9948 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
| AnnaBridge | 172:65be27845400 | 9949 | #define GPIO_LCKR_LCK12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9950 | #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9951 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
| AnnaBridge | 172:65be27845400 | 9952 | #define GPIO_LCKR_LCK13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 9953 | #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9954 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
| AnnaBridge | 172:65be27845400 | 9955 | #define GPIO_LCKR_LCK14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 9956 | #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9957 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
| AnnaBridge | 172:65be27845400 | 9958 | #define GPIO_LCKR_LCK15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 9959 | #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9960 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
| AnnaBridge | 172:65be27845400 | 9961 | #define GPIO_LCKR_LCKK_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9962 | #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9963 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
| AnnaBridge | 172:65be27845400 | 9964 | |
| AnnaBridge | 172:65be27845400 | 9965 | /****************** Bit definition for GPIO_AFRL register *********************/ |
| AnnaBridge | 172:65be27845400 | 9966 | #define GPIO_AFRL_AFSEL0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 9967 | #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 9968 | #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk |
| AnnaBridge | 172:65be27845400 | 9969 | #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 9970 | #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 9971 | #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 9972 | #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 9973 | #define GPIO_AFRL_AFSEL1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 9974 | #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 9975 | #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk |
| AnnaBridge | 172:65be27845400 | 9976 | #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 9977 | #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 9978 | #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 9979 | #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 9980 | #define GPIO_AFRL_AFSEL2_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 9981 | #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 9982 | #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk |
| AnnaBridge | 172:65be27845400 | 9983 | #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 9984 | #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 9985 | #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 9986 | #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 9987 | #define GPIO_AFRL_AFSEL3_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 9988 | #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 9989 | #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk |
| AnnaBridge | 172:65be27845400 | 9990 | #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 9991 | #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 9992 | #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 9993 | #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 9994 | #define GPIO_AFRL_AFSEL4_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 9995 | #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 9996 | #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk |
| AnnaBridge | 172:65be27845400 | 9997 | #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 9998 | #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 9999 | #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 10000 | #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 10001 | #define GPIO_AFRL_AFSEL5_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 10002 | #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 10003 | #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk |
| AnnaBridge | 172:65be27845400 | 10004 | #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 10005 | #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 10006 | #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 10007 | #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 10008 | #define GPIO_AFRL_AFSEL6_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 10009 | #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 10010 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| AnnaBridge | 172:65be27845400 | 10011 | #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 10012 | #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 10013 | #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 10014 | #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 10015 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 10016 | #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 172:65be27845400 | 10017 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| AnnaBridge | 172:65be27845400 | 10018 | #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 10019 | #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 10020 | #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 10021 | #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 10022 | |
| AnnaBridge | 172:65be27845400 | 10023 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 10024 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| AnnaBridge | 172:65be27845400 | 10025 | #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 |
| AnnaBridge | 172:65be27845400 | 10026 | #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 |
| AnnaBridge | 172:65be27845400 | 10027 | #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 |
| AnnaBridge | 172:65be27845400 | 10028 | #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 |
| AnnaBridge | 172:65be27845400 | 10029 | #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 |
| AnnaBridge | 172:65be27845400 | 10030 | #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 |
| AnnaBridge | 172:65be27845400 | 10031 | #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 |
| AnnaBridge | 172:65be27845400 | 10032 | |
| AnnaBridge | 172:65be27845400 | 10033 | /****************** Bit definition for GPIO_AFRH register *********************/ |
| AnnaBridge | 172:65be27845400 | 10034 | #define GPIO_AFRH_AFSEL8_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10035 | #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 10036 | #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk |
| AnnaBridge | 172:65be27845400 | 10037 | #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10038 | #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10039 | #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10040 | #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10041 | #define GPIO_AFRH_AFSEL9_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10042 | #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 10043 | #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk |
| AnnaBridge | 172:65be27845400 | 10044 | #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10045 | #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10046 | #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10047 | #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10048 | #define GPIO_AFRH_AFSEL10_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10049 | #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 10050 | #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk |
| AnnaBridge | 172:65be27845400 | 10051 | #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10052 | #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10053 | #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10054 | #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10055 | #define GPIO_AFRH_AFSEL11_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10056 | #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 10057 | #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk |
| AnnaBridge | 172:65be27845400 | 10058 | #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10059 | #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10060 | #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10061 | #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10062 | #define GPIO_AFRH_AFSEL12_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 10063 | #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 10064 | #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk |
| AnnaBridge | 172:65be27845400 | 10065 | #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 10066 | #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 10067 | #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 10068 | #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 10069 | #define GPIO_AFRH_AFSEL13_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 10070 | #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 10071 | #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk |
| AnnaBridge | 172:65be27845400 | 10072 | #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 10073 | #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 10074 | #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 10075 | #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 10076 | #define GPIO_AFRH_AFSEL14_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 10077 | #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 10078 | #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk |
| AnnaBridge | 172:65be27845400 | 10079 | #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 10080 | #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 10081 | #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 10082 | #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 10083 | #define GPIO_AFRH_AFSEL15_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 10084 | #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 172:65be27845400 | 10085 | #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk |
| AnnaBridge | 172:65be27845400 | 10086 | #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 10087 | #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 10088 | #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 10089 | #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 10090 | |
| AnnaBridge | 172:65be27845400 | 10091 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 10092 | #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 |
| AnnaBridge | 172:65be27845400 | 10093 | #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 |
| AnnaBridge | 172:65be27845400 | 10094 | #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 |
| AnnaBridge | 172:65be27845400 | 10095 | #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 |
| AnnaBridge | 172:65be27845400 | 10096 | #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 |
| AnnaBridge | 172:65be27845400 | 10097 | #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 |
| AnnaBridge | 172:65be27845400 | 10098 | #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 |
| AnnaBridge | 172:65be27845400 | 10099 | #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 |
| AnnaBridge | 172:65be27845400 | 10100 | |
| AnnaBridge | 172:65be27845400 | 10101 | /****************** Bits definition for GPIO_BRR register ******************/ |
| AnnaBridge | 172:65be27845400 | 10102 | #define GPIO_BRR_BR0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10103 | #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10104 | #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk |
| AnnaBridge | 172:65be27845400 | 10105 | #define GPIO_BRR_BR1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10106 | #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10107 | #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk |
| AnnaBridge | 172:65be27845400 | 10108 | #define GPIO_BRR_BR2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10109 | #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10110 | #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk |
| AnnaBridge | 172:65be27845400 | 10111 | #define GPIO_BRR_BR3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10112 | #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10113 | #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk |
| AnnaBridge | 172:65be27845400 | 10114 | #define GPIO_BRR_BR4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10115 | #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10116 | #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk |
| AnnaBridge | 172:65be27845400 | 10117 | #define GPIO_BRR_BR5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10118 | #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10119 | #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk |
| AnnaBridge | 172:65be27845400 | 10120 | #define GPIO_BRR_BR6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10121 | #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10122 | #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk |
| AnnaBridge | 172:65be27845400 | 10123 | #define GPIO_BRR_BR7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10124 | #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10125 | #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk |
| AnnaBridge | 172:65be27845400 | 10126 | #define GPIO_BRR_BR8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10127 | #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10128 | #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk |
| AnnaBridge | 172:65be27845400 | 10129 | #define GPIO_BRR_BR9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10130 | #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10131 | #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk |
| AnnaBridge | 172:65be27845400 | 10132 | #define GPIO_BRR_BR10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10133 | #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10134 | #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk |
| AnnaBridge | 172:65be27845400 | 10135 | #define GPIO_BRR_BR11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10136 | #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10137 | #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk |
| AnnaBridge | 172:65be27845400 | 10138 | #define GPIO_BRR_BR12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10139 | #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10140 | #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk |
| AnnaBridge | 172:65be27845400 | 10141 | #define GPIO_BRR_BR13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10142 | #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10143 | #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk |
| AnnaBridge | 172:65be27845400 | 10144 | #define GPIO_BRR_BR14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10145 | #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10146 | #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk |
| AnnaBridge | 172:65be27845400 | 10147 | #define GPIO_BRR_BR15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10148 | #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10149 | #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk |
| AnnaBridge | 172:65be27845400 | 10150 | |
| AnnaBridge | 172:65be27845400 | 10151 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 10152 | #define GPIO_BRR_BR_0 GPIO_BRR_BR0 |
| AnnaBridge | 172:65be27845400 | 10153 | #define GPIO_BRR_BR_1 GPIO_BRR_BR1 |
| AnnaBridge | 172:65be27845400 | 10154 | #define GPIO_BRR_BR_2 GPIO_BRR_BR2 |
| AnnaBridge | 172:65be27845400 | 10155 | #define GPIO_BRR_BR_3 GPIO_BRR_BR3 |
| AnnaBridge | 172:65be27845400 | 10156 | #define GPIO_BRR_BR_4 GPIO_BRR_BR4 |
| AnnaBridge | 172:65be27845400 | 10157 | #define GPIO_BRR_BR_5 GPIO_BRR_BR5 |
| AnnaBridge | 172:65be27845400 | 10158 | #define GPIO_BRR_BR_6 GPIO_BRR_BR6 |
| AnnaBridge | 172:65be27845400 | 10159 | #define GPIO_BRR_BR_7 GPIO_BRR_BR7 |
| AnnaBridge | 172:65be27845400 | 10160 | #define GPIO_BRR_BR_8 GPIO_BRR_BR8 |
| AnnaBridge | 172:65be27845400 | 10161 | #define GPIO_BRR_BR_9 GPIO_BRR_BR9 |
| AnnaBridge | 172:65be27845400 | 10162 | #define GPIO_BRR_BR_10 GPIO_BRR_BR10 |
| AnnaBridge | 172:65be27845400 | 10163 | #define GPIO_BRR_BR_11 GPIO_BRR_BR11 |
| AnnaBridge | 172:65be27845400 | 10164 | #define GPIO_BRR_BR_12 GPIO_BRR_BR12 |
| AnnaBridge | 172:65be27845400 | 10165 | #define GPIO_BRR_BR_13 GPIO_BRR_BR13 |
| AnnaBridge | 172:65be27845400 | 10166 | #define GPIO_BRR_BR_14 GPIO_BRR_BR14 |
| AnnaBridge | 172:65be27845400 | 10167 | #define GPIO_BRR_BR_15 GPIO_BRR_BR15 |
| AnnaBridge | 172:65be27845400 | 10168 | |
| AnnaBridge | 172:65be27845400 | 10169 | |
| AnnaBridge | 172:65be27845400 | 10170 | |
| AnnaBridge | 172:65be27845400 | 10171 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10172 | /* */ |
| AnnaBridge | 172:65be27845400 | 10173 | /* Inter-integrated Circuit Interface (I2C) */ |
| AnnaBridge | 172:65be27845400 | 10174 | /* */ |
| AnnaBridge | 172:65be27845400 | 10175 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10176 | /******************* Bit definition for I2C_CR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 10177 | #define I2C_CR1_PE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10178 | #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10179 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ |
| AnnaBridge | 172:65be27845400 | 10180 | #define I2C_CR1_TXIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10181 | #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10182 | #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10183 | #define I2C_CR1_RXIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10184 | #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10185 | #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10186 | #define I2C_CR1_ADDRIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10187 | #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10188 | #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10189 | #define I2C_CR1_NACKIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10190 | #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10191 | #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10192 | #define I2C_CR1_STOPIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10193 | #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10194 | #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10195 | #define I2C_CR1_TCIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10196 | #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10197 | #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10198 | #define I2C_CR1_ERRIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10199 | #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10200 | #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 10201 | #define I2C_CR1_DNF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10202 | #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 10203 | #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ |
| AnnaBridge | 172:65be27845400 | 10204 | #define I2C_CR1_ANFOFF_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10205 | #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10206 | #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ |
| AnnaBridge | 172:65be27845400 | 10207 | #define I2C_CR1_SWRST_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10208 | #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10209 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ |
| AnnaBridge | 172:65be27845400 | 10210 | #define I2C_CR1_TXDMAEN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10211 | #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10212 | #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ |
| AnnaBridge | 172:65be27845400 | 10213 | #define I2C_CR1_RXDMAEN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10214 | #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10215 | #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ |
| AnnaBridge | 172:65be27845400 | 10216 | #define I2C_CR1_SBC_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 10217 | #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 10218 | #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ |
| AnnaBridge | 172:65be27845400 | 10219 | #define I2C_CR1_NOSTRETCH_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 10220 | #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 10221 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ |
| AnnaBridge | 172:65be27845400 | 10222 | #define I2C_CR1_WUPEN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 10223 | #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 10224 | #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ |
| AnnaBridge | 172:65be27845400 | 10225 | #define I2C_CR1_GCEN_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 10226 | #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 10227 | #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ |
| AnnaBridge | 172:65be27845400 | 10228 | #define I2C_CR1_SMBHEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 10229 | #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 10230 | #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ |
| AnnaBridge | 172:65be27845400 | 10231 | #define I2C_CR1_SMBDEN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 10232 | #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 10233 | #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ |
| AnnaBridge | 172:65be27845400 | 10234 | #define I2C_CR1_ALERTEN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 10235 | #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 10236 | #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ |
| AnnaBridge | 172:65be27845400 | 10237 | #define I2C_CR1_PECEN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 10238 | #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 10239 | #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ |
| AnnaBridge | 172:65be27845400 | 10240 | |
| AnnaBridge | 172:65be27845400 | 10241 | /****************** Bit definition for I2C_CR2 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10242 | #define I2C_CR2_SADD_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10243 | #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 10244 | #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10245 | #define I2C_CR2_RD_WRN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10246 | #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10247 | #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10248 | #define I2C_CR2_ADD10_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10249 | #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10250 | #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10251 | #define I2C_CR2_HEAD10R_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10252 | #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10253 | #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10254 | #define I2C_CR2_START_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10255 | #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10256 | #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ |
| AnnaBridge | 172:65be27845400 | 10257 | #define I2C_CR2_STOP_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10258 | #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10259 | #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10260 | #define I2C_CR2_NACK_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10261 | #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10262 | #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ |
| AnnaBridge | 172:65be27845400 | 10263 | #define I2C_CR2_NBYTES_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 10264 | #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 10265 | #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ |
| AnnaBridge | 172:65be27845400 | 10266 | #define I2C_CR2_RELOAD_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 10267 | #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 10268 | #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ |
| AnnaBridge | 172:65be27845400 | 10269 | #define I2C_CR2_AUTOEND_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 10270 | #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 10271 | #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10272 | #define I2C_CR2_PECBYTE_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 10273 | #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 10274 | #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ |
| AnnaBridge | 172:65be27845400 | 10275 | |
| AnnaBridge | 172:65be27845400 | 10276 | /******************* Bit definition for I2C_OAR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 10277 | #define I2C_OAR1_OA1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10278 | #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 10279 | #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ |
| AnnaBridge | 172:65be27845400 | 10280 | #define I2C_OAR1_OA1MODE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10281 | #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10282 | #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ |
| AnnaBridge | 172:65be27845400 | 10283 | #define I2C_OAR1_OA1EN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10284 | #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10285 | #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ |
| AnnaBridge | 172:65be27845400 | 10286 | |
| AnnaBridge | 172:65be27845400 | 10287 | /******************* Bit definition for I2C_OAR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 10288 | #define I2C_OAR2_OA2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10289 | #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ |
| AnnaBridge | 172:65be27845400 | 10290 | #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ |
| AnnaBridge | 172:65be27845400 | 10291 | #define I2C_OAR2_OA2MSK_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10292 | #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 10293 | #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ |
| AnnaBridge | 172:65be27845400 | 10294 | #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ |
| AnnaBridge | 172:65be27845400 | 10295 | #define I2C_OAR2_OA2MASK01_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10296 | #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10297 | #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ |
| AnnaBridge | 172:65be27845400 | 10298 | #define I2C_OAR2_OA2MASK02_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10299 | #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10300 | #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ |
| AnnaBridge | 172:65be27845400 | 10301 | #define I2C_OAR2_OA2MASK03_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10302 | #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 10303 | #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ |
| AnnaBridge | 172:65be27845400 | 10304 | #define I2C_OAR2_OA2MASK04_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10305 | #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10306 | #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ |
| AnnaBridge | 172:65be27845400 | 10307 | #define I2C_OAR2_OA2MASK05_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10308 | #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ |
| AnnaBridge | 172:65be27845400 | 10309 | #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ |
| AnnaBridge | 172:65be27845400 | 10310 | #define I2C_OAR2_OA2MASK06_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10311 | #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 172:65be27845400 | 10312 | #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ |
| AnnaBridge | 172:65be27845400 | 10313 | #define I2C_OAR2_OA2MASK07_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10314 | #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 10315 | #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ |
| AnnaBridge | 172:65be27845400 | 10316 | #define I2C_OAR2_OA2EN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10317 | #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10318 | #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ |
| AnnaBridge | 172:65be27845400 | 10319 | |
| AnnaBridge | 172:65be27845400 | 10320 | /******************* Bit definition for I2C_TIMINGR register *******************/ |
| AnnaBridge | 172:65be27845400 | 10321 | #define I2C_TIMINGR_SCLL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10322 | #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 10323 | #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10324 | #define I2C_TIMINGR_SCLH_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10325 | #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 10326 | #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10327 | #define I2C_TIMINGR_SDADEL_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 10328 | #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 10329 | #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ |
| AnnaBridge | 172:65be27845400 | 10330 | #define I2C_TIMINGR_SCLDEL_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 10331 | #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 10332 | #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ |
| AnnaBridge | 172:65be27845400 | 10333 | #define I2C_TIMINGR_PRESC_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 10334 | #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 172:65be27845400 | 10335 | #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ |
| AnnaBridge | 172:65be27845400 | 10336 | |
| AnnaBridge | 172:65be27845400 | 10337 | /******************* Bit definition for I2C_TIMEOUTR register *******************/ |
| AnnaBridge | 172:65be27845400 | 10338 | #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10339 | #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 10340 | #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ |
| AnnaBridge | 172:65be27845400 | 10341 | #define I2C_TIMEOUTR_TIDLE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10342 | #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10343 | #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ |
| AnnaBridge | 172:65be27845400 | 10344 | #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10345 | #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10346 | #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ |
| AnnaBridge | 172:65be27845400 | 10347 | #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 10348 | #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ |
| AnnaBridge | 172:65be27845400 | 10349 | #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */ |
| AnnaBridge | 172:65be27845400 | 10350 | #define I2C_TIMEOUTR_TEXTEN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 10351 | #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 10352 | #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ |
| AnnaBridge | 172:65be27845400 | 10353 | |
| AnnaBridge | 172:65be27845400 | 10354 | /****************** Bit definition for I2C_ISR register *********************/ |
| AnnaBridge | 172:65be27845400 | 10355 | #define I2C_ISR_TXE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10356 | #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10357 | #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ |
| AnnaBridge | 172:65be27845400 | 10358 | #define I2C_ISR_TXIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10359 | #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10360 | #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ |
| AnnaBridge | 172:65be27845400 | 10361 | #define I2C_ISR_RXNE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10362 | #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10363 | #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ |
| AnnaBridge | 172:65be27845400 | 10364 | #define I2C_ISR_ADDR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10365 | #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10366 | #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */ |
| AnnaBridge | 172:65be27845400 | 10367 | #define I2C_ISR_NACKF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10368 | #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10369 | #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ |
| AnnaBridge | 172:65be27845400 | 10370 | #define I2C_ISR_STOPF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10371 | #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10372 | #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ |
| AnnaBridge | 172:65be27845400 | 10373 | #define I2C_ISR_TC_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10374 | #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10375 | #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ |
| AnnaBridge | 172:65be27845400 | 10376 | #define I2C_ISR_TCR_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10377 | #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10378 | #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ |
| AnnaBridge | 172:65be27845400 | 10379 | #define I2C_ISR_BERR_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10380 | #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10381 | #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ |
| AnnaBridge | 172:65be27845400 | 10382 | #define I2C_ISR_ARLO_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10383 | #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10384 | #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ |
| AnnaBridge | 172:65be27845400 | 10385 | #define I2C_ISR_OVR_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10386 | #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10387 | #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ |
| AnnaBridge | 172:65be27845400 | 10388 | #define I2C_ISR_PECERR_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10389 | #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10390 | #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ |
| AnnaBridge | 172:65be27845400 | 10391 | #define I2C_ISR_TIMEOUT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10392 | #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10393 | #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ |
| AnnaBridge | 172:65be27845400 | 10394 | #define I2C_ISR_ALERT_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10395 | #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10396 | #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ |
| AnnaBridge | 172:65be27845400 | 10397 | #define I2C_ISR_BUSY_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10398 | #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10399 | #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ |
| AnnaBridge | 172:65be27845400 | 10400 | #define I2C_ISR_DIR_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 10401 | #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 10402 | #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ |
| AnnaBridge | 172:65be27845400 | 10403 | #define I2C_ISR_ADDCODE_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 10404 | #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ |
| AnnaBridge | 172:65be27845400 | 10405 | #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ |
| AnnaBridge | 172:65be27845400 | 10406 | |
| AnnaBridge | 172:65be27845400 | 10407 | /****************** Bit definition for I2C_ICR register *********************/ |
| AnnaBridge | 172:65be27845400 | 10408 | #define I2C_ICR_ADDRCF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10409 | #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10410 | #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ |
| AnnaBridge | 172:65be27845400 | 10411 | #define I2C_ICR_NACKCF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10412 | #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10413 | #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ |
| AnnaBridge | 172:65be27845400 | 10414 | #define I2C_ICR_STOPCF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10415 | #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10416 | #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ |
| AnnaBridge | 172:65be27845400 | 10417 | #define I2C_ICR_BERRCF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10418 | #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10419 | #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ |
| AnnaBridge | 172:65be27845400 | 10420 | #define I2C_ICR_ARLOCF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10421 | #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10422 | #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ |
| AnnaBridge | 172:65be27845400 | 10423 | #define I2C_ICR_OVRCF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10424 | #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10425 | #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ |
| AnnaBridge | 172:65be27845400 | 10426 | #define I2C_ICR_PECCF_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10427 | #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10428 | #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ |
| AnnaBridge | 172:65be27845400 | 10429 | #define I2C_ICR_TIMOUTCF_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10430 | #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10431 | #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ |
| AnnaBridge | 172:65be27845400 | 10432 | #define I2C_ICR_ALERTCF_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10433 | #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10434 | #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ |
| AnnaBridge | 172:65be27845400 | 10435 | |
| AnnaBridge | 172:65be27845400 | 10436 | /****************** Bit definition for I2C_PECR register *********************/ |
| AnnaBridge | 172:65be27845400 | 10437 | #define I2C_PECR_PEC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10438 | #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 10439 | #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ |
| AnnaBridge | 172:65be27845400 | 10440 | |
| AnnaBridge | 172:65be27845400 | 10441 | /****************** Bit definition for I2C_RXDR register *********************/ |
| AnnaBridge | 172:65be27845400 | 10442 | #define I2C_RXDR_RXDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10443 | #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 10444 | #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ |
| AnnaBridge | 172:65be27845400 | 10445 | |
| AnnaBridge | 172:65be27845400 | 10446 | /****************** Bit definition for I2C_TXDR register *********************/ |
| AnnaBridge | 172:65be27845400 | 10447 | #define I2C_TXDR_TXDATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10448 | #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 10449 | #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ |
| AnnaBridge | 172:65be27845400 | 10450 | |
| AnnaBridge | 172:65be27845400 | 10451 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10452 | /* */ |
| AnnaBridge | 172:65be27845400 | 10453 | /* Independent WATCHDOG */ |
| AnnaBridge | 172:65be27845400 | 10454 | /* */ |
| AnnaBridge | 172:65be27845400 | 10455 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10456 | /******************* Bit definition for IWDG_KR register ********************/ |
| AnnaBridge | 172:65be27845400 | 10457 | #define IWDG_KR_KEY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10458 | #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 10459 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ |
| AnnaBridge | 172:65be27845400 | 10460 | |
| AnnaBridge | 172:65be27845400 | 10461 | /******************* Bit definition for IWDG_PR register ********************/ |
| AnnaBridge | 172:65be27845400 | 10462 | #define IWDG_PR_PR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10463 | #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 10464 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ |
| AnnaBridge | 172:65be27845400 | 10465 | #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10466 | #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10467 | #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10468 | |
| AnnaBridge | 172:65be27845400 | 10469 | /******************* Bit definition for IWDG_RLR register *******************/ |
| AnnaBridge | 172:65be27845400 | 10470 | #define IWDG_RLR_RL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10471 | #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 10472 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ |
| AnnaBridge | 172:65be27845400 | 10473 | |
| AnnaBridge | 172:65be27845400 | 10474 | /******************* Bit definition for IWDG_SR register ********************/ |
| AnnaBridge | 172:65be27845400 | 10475 | #define IWDG_SR_PVU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10476 | #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10477 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
| AnnaBridge | 172:65be27845400 | 10478 | #define IWDG_SR_RVU_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10479 | #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10480 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
| AnnaBridge | 172:65be27845400 | 10481 | #define IWDG_SR_WVU_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10482 | #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10483 | #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ |
| AnnaBridge | 172:65be27845400 | 10484 | |
| AnnaBridge | 172:65be27845400 | 10485 | /******************* Bit definition for IWDG_KR register ********************/ |
| AnnaBridge | 172:65be27845400 | 10486 | #define IWDG_WINR_WIN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10487 | #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 10488 | #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ |
| AnnaBridge | 172:65be27845400 | 10489 | |
| AnnaBridge | 172:65be27845400 | 10490 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10491 | /* */ |
| AnnaBridge | 172:65be27845400 | 10492 | /* Firewall */ |
| AnnaBridge | 172:65be27845400 | 10493 | /* */ |
| AnnaBridge | 172:65be27845400 | 10494 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10495 | |
| AnnaBridge | 172:65be27845400 | 10496 | /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ |
| AnnaBridge | 172:65be27845400 | 10497 | #define FW_CSSA_ADD_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10498 | #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ |
| AnnaBridge | 172:65be27845400 | 10499 | #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ |
| AnnaBridge | 172:65be27845400 | 10500 | #define FW_CSL_LENG_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10501 | #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ |
| AnnaBridge | 172:65be27845400 | 10502 | #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ |
| AnnaBridge | 172:65be27845400 | 10503 | #define FW_NVDSSA_ADD_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10504 | #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ |
| AnnaBridge | 172:65be27845400 | 10505 | #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ |
| AnnaBridge | 172:65be27845400 | 10506 | #define FW_NVDSL_LENG_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10507 | #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ |
| AnnaBridge | 172:65be27845400 | 10508 | #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ |
| AnnaBridge | 172:65be27845400 | 10509 | #define FW_VDSSA_ADD_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10510 | #define FW_VDSSA_ADD_Msk (0xFFFU << FW_VDSSA_ADD_Pos) /*!< 0x0003FFC0 */ |
| AnnaBridge | 172:65be27845400 | 10511 | #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ |
| AnnaBridge | 172:65be27845400 | 10512 | #define FW_VDSL_LENG_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10513 | #define FW_VDSL_LENG_Msk (0xFFFU << FW_VDSL_LENG_Pos) /*!< 0x0003FFC0 */ |
| AnnaBridge | 172:65be27845400 | 10514 | #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ |
| AnnaBridge | 172:65be27845400 | 10515 | |
| AnnaBridge | 172:65be27845400 | 10516 | /**************************Bit definition for CR register *********************/ |
| AnnaBridge | 172:65be27845400 | 10517 | #define FW_CR_FPA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10518 | #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10519 | #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ |
| AnnaBridge | 172:65be27845400 | 10520 | #define FW_CR_VDS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10521 | #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10522 | #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ |
| AnnaBridge | 172:65be27845400 | 10523 | #define FW_CR_VDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10524 | #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10525 | #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ |
| AnnaBridge | 172:65be27845400 | 10526 | |
| AnnaBridge | 172:65be27845400 | 10527 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10528 | /* */ |
| AnnaBridge | 172:65be27845400 | 10529 | /* Power Control */ |
| AnnaBridge | 172:65be27845400 | 10530 | /* */ |
| AnnaBridge | 172:65be27845400 | 10531 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 10532 | |
| AnnaBridge | 172:65be27845400 | 10533 | /******************** Bit definition for PWR_CR1 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10534 | |
| AnnaBridge | 172:65be27845400 | 10535 | #define PWR_CR1_LPR_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10536 | #define PWR_CR1_LPR_Msk (0x1U << PWR_CR1_LPR_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10537 | #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */ |
| AnnaBridge | 172:65be27845400 | 10538 | #define PWR_CR1_VOS_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10539 | #define PWR_CR1_VOS_Msk (0x3U << PWR_CR1_VOS_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 172:65be27845400 | 10540 | #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ |
| AnnaBridge | 172:65be27845400 | 10541 | #define PWR_CR1_VOS_0 (0x1U << PWR_CR1_VOS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10542 | #define PWR_CR1_VOS_1 (0x2U << PWR_CR1_VOS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10543 | #define PWR_CR1_DBP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10544 | #define PWR_CR1_DBP_Msk (0x1U << PWR_CR1_DBP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10545 | #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */ |
| AnnaBridge | 172:65be27845400 | 10546 | #define PWR_CR1_RRSTP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10547 | #define PWR_CR1_RRSTP_Msk (0x1U << PWR_CR1_RRSTP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10548 | #define PWR_CR1_RRSTP PWR_CR1_RRSTP_Msk /*!< SRAM3 Retention in Stop 2 mode */ |
| AnnaBridge | 172:65be27845400 | 10549 | #define PWR_CR1_LPMS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10550 | #define PWR_CR1_LPMS_Msk (0x7U << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 10551 | #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */ |
| AnnaBridge | 172:65be27845400 | 10552 | #define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */ |
| AnnaBridge | 172:65be27845400 | 10553 | #define PWR_CR1_LPMS_STOP1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10554 | #define PWR_CR1_LPMS_STOP1_Msk (0x1U << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10555 | #define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */ |
| AnnaBridge | 172:65be27845400 | 10556 | #define PWR_CR1_LPMS_STOP2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10557 | #define PWR_CR1_LPMS_STOP2_Msk (0x1U << PWR_CR1_LPMS_STOP2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10558 | #define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk /*!< Stop 2 mode */ |
| AnnaBridge | 172:65be27845400 | 10559 | #define PWR_CR1_LPMS_STANDBY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10560 | #define PWR_CR1_LPMS_STANDBY_Msk (0x3U << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 10561 | #define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */ |
| AnnaBridge | 172:65be27845400 | 10562 | #define PWR_CR1_LPMS_SHUTDOWN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10563 | #define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10564 | #define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */ |
| AnnaBridge | 172:65be27845400 | 10565 | |
| AnnaBridge | 172:65be27845400 | 10566 | |
| AnnaBridge | 172:65be27845400 | 10567 | /******************** Bit definition for PWR_CR2 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10568 | #define PWR_CR2_USV_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10569 | #define PWR_CR2_USV_Msk (0x1U << PWR_CR2_USV_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10570 | #define PWR_CR2_USV PWR_CR2_USV_Msk /*!< VDD USB Supply Valid */ |
| AnnaBridge | 172:65be27845400 | 10571 | #define PWR_CR2_IOSV_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10572 | #define PWR_CR2_IOSV_Msk (0x1U << PWR_CR2_IOSV_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10573 | #define PWR_CR2_IOSV PWR_CR2_IOSV_Msk /*!< VDD IO2 independent I/Os Supply Valid */ |
| AnnaBridge | 172:65be27845400 | 10574 | /*!< PVME Peripheral Voltage Monitor Enable */ |
| AnnaBridge | 172:65be27845400 | 10575 | #define PWR_CR2_PVME_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10576 | #define PWR_CR2_PVME_Msk (0xFU << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 10577 | #define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */ |
| AnnaBridge | 172:65be27845400 | 10578 | #define PWR_CR2_PVME4_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10579 | #define PWR_CR2_PVME4_Msk (0x1U << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10580 | #define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */ |
| AnnaBridge | 172:65be27845400 | 10581 | #define PWR_CR2_PVME3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10582 | #define PWR_CR2_PVME3_Msk (0x1U << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10583 | #define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */ |
| AnnaBridge | 172:65be27845400 | 10584 | #define PWR_CR2_PVME2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10585 | #define PWR_CR2_PVME2_Msk (0x1U << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10586 | #define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */ |
| AnnaBridge | 172:65be27845400 | 10587 | #define PWR_CR2_PVME1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10588 | #define PWR_CR2_PVME1_Msk (0x1U << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10589 | #define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */ |
| AnnaBridge | 172:65be27845400 | 10590 | /*!< PVD level configuration */ |
| AnnaBridge | 172:65be27845400 | 10591 | #define PWR_CR2_PLS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10592 | #define PWR_CR2_PLS_Msk (0x7U << PWR_CR2_PLS_Pos) /*!< 0x0000000E */ |
| AnnaBridge | 172:65be27845400 | 10593 | #define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */ |
| AnnaBridge | 172:65be27845400 | 10594 | #define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ |
| AnnaBridge | 172:65be27845400 | 10595 | #define PWR_CR2_PLS_LEV1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10596 | #define PWR_CR2_PLS_LEV1_Msk (0x1U << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10597 | #define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */ |
| AnnaBridge | 172:65be27845400 | 10598 | #define PWR_CR2_PLS_LEV2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10599 | #define PWR_CR2_PLS_LEV2_Msk (0x1U << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10600 | #define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */ |
| AnnaBridge | 172:65be27845400 | 10601 | #define PWR_CR2_PLS_LEV3_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10602 | #define PWR_CR2_PLS_LEV3_Msk (0x3U << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 172:65be27845400 | 10603 | #define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */ |
| AnnaBridge | 172:65be27845400 | 10604 | #define PWR_CR2_PLS_LEV4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10605 | #define PWR_CR2_PLS_LEV4_Msk (0x1U << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10606 | #define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */ |
| AnnaBridge | 172:65be27845400 | 10607 | #define PWR_CR2_PLS_LEV5_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10608 | #define PWR_CR2_PLS_LEV5_Msk (0x5U << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */ |
| AnnaBridge | 172:65be27845400 | 10609 | #define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */ |
| AnnaBridge | 172:65be27845400 | 10610 | #define PWR_CR2_PLS_LEV6_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10611 | #define PWR_CR2_PLS_LEV6_Msk (0x3U << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 10612 | #define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */ |
| AnnaBridge | 172:65be27845400 | 10613 | #define PWR_CR2_PLS_LEV7_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10614 | #define PWR_CR2_PLS_LEV7_Msk (0x7U << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */ |
| AnnaBridge | 172:65be27845400 | 10615 | #define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */ |
| AnnaBridge | 172:65be27845400 | 10616 | #define PWR_CR2_PVDE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10617 | #define PWR_CR2_PVDE_Msk (0x1U << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10618 | #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */ |
| AnnaBridge | 172:65be27845400 | 10619 | |
| AnnaBridge | 172:65be27845400 | 10620 | /******************** Bit definition for PWR_CR3 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10621 | #define PWR_CR3_EIWUL_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10622 | #define PWR_CR3_EIWUL_Msk (0x1U << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10623 | #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */ |
| AnnaBridge | 172:65be27845400 | 10624 | #define PWR_CR3_DSIPDEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10625 | #define PWR_CR3_DSIPDEN_Msk (0x1U << PWR_CR3_DSIPDEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10626 | #define PWR_CR3_DSIPDEN PWR_CR3_DSIPDEN_Msk /*!< Disable DSI pads pull-down */ |
| AnnaBridge | 172:65be27845400 | 10627 | #define PWR_CR3_APC_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10628 | #define PWR_CR3_APC_Msk (0x1U << PWR_CR3_APC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10629 | #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */ |
| AnnaBridge | 172:65be27845400 | 10630 | #define PWR_CR3_RRS_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10631 | #define PWR_CR3_RRS_Msk (0x1U << PWR_CR3_RRS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10632 | #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */ |
| AnnaBridge | 172:65be27845400 | 10633 | #define PWR_CR3_EWUP5_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10634 | #define PWR_CR3_EWUP5_Msk (0x1U << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10635 | #define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */ |
| AnnaBridge | 172:65be27845400 | 10636 | #define PWR_CR3_EWUP4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10637 | #define PWR_CR3_EWUP4_Msk (0x1U << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10638 | #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */ |
| AnnaBridge | 172:65be27845400 | 10639 | #define PWR_CR3_EWUP3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10640 | #define PWR_CR3_EWUP3_Msk (0x1U << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10641 | #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */ |
| AnnaBridge | 172:65be27845400 | 10642 | #define PWR_CR3_EWUP2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10643 | #define PWR_CR3_EWUP2_Msk (0x1U << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10644 | #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */ |
| AnnaBridge | 172:65be27845400 | 10645 | #define PWR_CR3_EWUP1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10646 | #define PWR_CR3_EWUP1_Msk (0x1U << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10647 | #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */ |
| AnnaBridge | 172:65be27845400 | 10648 | #define PWR_CR3_EWUP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10649 | #define PWR_CR3_EWUP_Msk (0x1FU << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 10650 | #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */ |
| AnnaBridge | 172:65be27845400 | 10651 | |
| AnnaBridge | 172:65be27845400 | 10652 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 10653 | #define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos |
| AnnaBridge | 172:65be27845400 | 10654 | #define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk |
| AnnaBridge | 172:65be27845400 | 10655 | #define PWR_CR3_EIWF PWR_CR3_EIWUL |
| AnnaBridge | 172:65be27845400 | 10656 | |
| AnnaBridge | 172:65be27845400 | 10657 | |
| AnnaBridge | 172:65be27845400 | 10658 | /******************** Bit definition for PWR_CR4 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10659 | #define PWR_CR4_VBRS_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10660 | #define PWR_CR4_VBRS_Msk (0x1U << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10661 | #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */ |
| AnnaBridge | 172:65be27845400 | 10662 | #define PWR_CR4_VBE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10663 | #define PWR_CR4_VBE_Msk (0x1U << PWR_CR4_VBE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10664 | #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */ |
| AnnaBridge | 172:65be27845400 | 10665 | #define PWR_CR4_WP5_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10666 | #define PWR_CR4_WP5_Msk (0x1U << PWR_CR4_WP5_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10667 | #define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */ |
| AnnaBridge | 172:65be27845400 | 10668 | #define PWR_CR4_WP4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10669 | #define PWR_CR4_WP4_Msk (0x1U << PWR_CR4_WP4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10670 | #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */ |
| AnnaBridge | 172:65be27845400 | 10671 | #define PWR_CR4_WP3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10672 | #define PWR_CR4_WP3_Msk (0x1U << PWR_CR4_WP3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10673 | #define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */ |
| AnnaBridge | 172:65be27845400 | 10674 | #define PWR_CR4_WP2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10675 | #define PWR_CR4_WP2_Msk (0x1U << PWR_CR4_WP2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10676 | #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */ |
| AnnaBridge | 172:65be27845400 | 10677 | #define PWR_CR4_WP1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10678 | #define PWR_CR4_WP1_Msk (0x1U << PWR_CR4_WP1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10679 | #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */ |
| AnnaBridge | 172:65be27845400 | 10680 | |
| AnnaBridge | 172:65be27845400 | 10681 | /******************** Bit definition for PWR_SR1 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10682 | #define PWR_SR1_WUFI_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10683 | #define PWR_SR1_WUFI_Msk (0x1U << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10684 | #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */ |
| AnnaBridge | 172:65be27845400 | 10685 | #define PWR_SR1_SBF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10686 | #define PWR_SR1_SBF_Msk (0x1U << PWR_SR1_SBF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10687 | #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */ |
| AnnaBridge | 172:65be27845400 | 10688 | #define PWR_SR1_WUF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10689 | #define PWR_SR1_WUF_Msk (0x1FU << PWR_SR1_WUF_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 10690 | #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */ |
| AnnaBridge | 172:65be27845400 | 10691 | #define PWR_SR1_WUF5_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10692 | #define PWR_SR1_WUF5_Msk (0x1U << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10693 | #define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */ |
| AnnaBridge | 172:65be27845400 | 10694 | #define PWR_SR1_WUF4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10695 | #define PWR_SR1_WUF4_Msk (0x1U << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10696 | #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */ |
| AnnaBridge | 172:65be27845400 | 10697 | #define PWR_SR1_WUF3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10698 | #define PWR_SR1_WUF3_Msk (0x1U << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10699 | #define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */ |
| AnnaBridge | 172:65be27845400 | 10700 | #define PWR_SR1_WUF2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10701 | #define PWR_SR1_WUF2_Msk (0x1U << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10702 | #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */ |
| AnnaBridge | 172:65be27845400 | 10703 | #define PWR_SR1_WUF1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10704 | #define PWR_SR1_WUF1_Msk (0x1U << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10705 | #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */ |
| AnnaBridge | 172:65be27845400 | 10706 | |
| AnnaBridge | 172:65be27845400 | 10707 | /******************** Bit definition for PWR_SR2 register ********************/ |
| AnnaBridge | 172:65be27845400 | 10708 | #define PWR_SR2_PVMO4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10709 | #define PWR_SR2_PVMO4_Msk (0x1U << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10710 | #define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */ |
| AnnaBridge | 172:65be27845400 | 10711 | #define PWR_SR2_PVMO3_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10712 | #define PWR_SR2_PVMO3_Msk (0x1U << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10713 | #define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */ |
| AnnaBridge | 172:65be27845400 | 10714 | #define PWR_SR2_PVMO2_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10715 | #define PWR_SR2_PVMO2_Msk (0x1U << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10716 | #define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */ |
| AnnaBridge | 172:65be27845400 | 10717 | #define PWR_SR2_PVMO1_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10718 | #define PWR_SR2_PVMO1_Msk (0x1U << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10719 | #define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */ |
| AnnaBridge | 172:65be27845400 | 10720 | #define PWR_SR2_PVDO_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10721 | #define PWR_SR2_PVDO_Msk (0x1U << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10722 | #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */ |
| AnnaBridge | 172:65be27845400 | 10723 | #define PWR_SR2_VOSF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10724 | #define PWR_SR2_VOSF_Msk (0x1U << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10725 | #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */ |
| AnnaBridge | 172:65be27845400 | 10726 | #define PWR_SR2_REGLPF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10727 | #define PWR_SR2_REGLPF_Msk (0x1U << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10728 | #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */ |
| AnnaBridge | 172:65be27845400 | 10729 | #define PWR_SR2_REGLPS_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10730 | #define PWR_SR2_REGLPS_Msk (0x1U << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10731 | #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */ |
| AnnaBridge | 172:65be27845400 | 10732 | |
| AnnaBridge | 172:65be27845400 | 10733 | /******************** Bit definition for PWR_SCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 10734 | #define PWR_SCR_CSBF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10735 | #define PWR_SCR_CSBF_Msk (0x1U << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10736 | #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */ |
| AnnaBridge | 172:65be27845400 | 10737 | #define PWR_SCR_CWUF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10738 | #define PWR_SCR_CWUF_Msk (0x1FU << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 10739 | #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */ |
| AnnaBridge | 172:65be27845400 | 10740 | #define PWR_SCR_CWUF5_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10741 | #define PWR_SCR_CWUF5_Msk (0x1U << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10742 | #define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */ |
| AnnaBridge | 172:65be27845400 | 10743 | #define PWR_SCR_CWUF4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10744 | #define PWR_SCR_CWUF4_Msk (0x1U << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10745 | #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */ |
| AnnaBridge | 172:65be27845400 | 10746 | #define PWR_SCR_CWUF3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10747 | #define PWR_SCR_CWUF3_Msk (0x1U << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10748 | #define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */ |
| AnnaBridge | 172:65be27845400 | 10749 | #define PWR_SCR_CWUF2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10750 | #define PWR_SCR_CWUF2_Msk (0x1U << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10751 | #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */ |
| AnnaBridge | 172:65be27845400 | 10752 | #define PWR_SCR_CWUF1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10753 | #define PWR_SCR_CWUF1_Msk (0x1U << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10754 | #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */ |
| AnnaBridge | 172:65be27845400 | 10755 | |
| AnnaBridge | 172:65be27845400 | 10756 | /******************** Bit definition for PWR_PUCRA register ********************/ |
| AnnaBridge | 172:65be27845400 | 10757 | #define PWR_PUCRA_PA15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10758 | #define PWR_PUCRA_PA15_Msk (0x1U << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10759 | #define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10760 | #define PWR_PUCRA_PA13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10761 | #define PWR_PUCRA_PA13_Msk (0x1U << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10762 | #define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10763 | #define PWR_PUCRA_PA12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10764 | #define PWR_PUCRA_PA12_Msk (0x1U << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10765 | #define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10766 | #define PWR_PUCRA_PA11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10767 | #define PWR_PUCRA_PA11_Msk (0x1U << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10768 | #define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10769 | #define PWR_PUCRA_PA10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10770 | #define PWR_PUCRA_PA10_Msk (0x1U << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10771 | #define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10772 | #define PWR_PUCRA_PA9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10773 | #define PWR_PUCRA_PA9_Msk (0x1U << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10774 | #define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10775 | #define PWR_PUCRA_PA8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10776 | #define PWR_PUCRA_PA8_Msk (0x1U << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10777 | #define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10778 | #define PWR_PUCRA_PA7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10779 | #define PWR_PUCRA_PA7_Msk (0x1U << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10780 | #define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10781 | #define PWR_PUCRA_PA6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10782 | #define PWR_PUCRA_PA6_Msk (0x1U << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10783 | #define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10784 | #define PWR_PUCRA_PA5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10785 | #define PWR_PUCRA_PA5_Msk (0x1U << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10786 | #define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10787 | #define PWR_PUCRA_PA4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10788 | #define PWR_PUCRA_PA4_Msk (0x1U << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10789 | #define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10790 | #define PWR_PUCRA_PA3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10791 | #define PWR_PUCRA_PA3_Msk (0x1U << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10792 | #define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10793 | #define PWR_PUCRA_PA2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10794 | #define PWR_PUCRA_PA2_Msk (0x1U << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10795 | #define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10796 | #define PWR_PUCRA_PA1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10797 | #define PWR_PUCRA_PA1_Msk (0x1U << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10798 | #define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10799 | #define PWR_PUCRA_PA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10800 | #define PWR_PUCRA_PA0_Msk (0x1U << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10801 | #define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10802 | |
| AnnaBridge | 172:65be27845400 | 10803 | /******************** Bit definition for PWR_PDCRA register ********************/ |
| AnnaBridge | 172:65be27845400 | 10804 | #define PWR_PDCRA_PA14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10805 | #define PWR_PDCRA_PA14_Msk (0x1U << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10806 | #define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10807 | #define PWR_PDCRA_PA12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10808 | #define PWR_PDCRA_PA12_Msk (0x1U << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10809 | #define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10810 | #define PWR_PDCRA_PA11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10811 | #define PWR_PDCRA_PA11_Msk (0x1U << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10812 | #define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10813 | #define PWR_PDCRA_PA10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10814 | #define PWR_PDCRA_PA10_Msk (0x1U << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10815 | #define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10816 | #define PWR_PDCRA_PA9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10817 | #define PWR_PDCRA_PA9_Msk (0x1U << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10818 | #define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10819 | #define PWR_PDCRA_PA8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10820 | #define PWR_PDCRA_PA8_Msk (0x1U << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10821 | #define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10822 | #define PWR_PDCRA_PA7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10823 | #define PWR_PDCRA_PA7_Msk (0x1U << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10824 | #define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10825 | #define PWR_PDCRA_PA6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10826 | #define PWR_PDCRA_PA6_Msk (0x1U << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10827 | #define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10828 | #define PWR_PDCRA_PA5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10829 | #define PWR_PDCRA_PA5_Msk (0x1U << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10830 | #define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10831 | #define PWR_PDCRA_PA4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10832 | #define PWR_PDCRA_PA4_Msk (0x1U << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10833 | #define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10834 | #define PWR_PDCRA_PA3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10835 | #define PWR_PDCRA_PA3_Msk (0x1U << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10836 | #define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10837 | #define PWR_PDCRA_PA2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10838 | #define PWR_PDCRA_PA2_Msk (0x1U << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10839 | #define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10840 | #define PWR_PDCRA_PA1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10841 | #define PWR_PDCRA_PA1_Msk (0x1U << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10842 | #define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10843 | #define PWR_PDCRA_PA0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10844 | #define PWR_PDCRA_PA0_Msk (0x1U << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10845 | #define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10846 | |
| AnnaBridge | 172:65be27845400 | 10847 | /******************** Bit definition for PWR_PUCRB register ********************/ |
| AnnaBridge | 172:65be27845400 | 10848 | #define PWR_PUCRB_PB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10849 | #define PWR_PUCRB_PB15_Msk (0x1U << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10850 | #define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10851 | #define PWR_PUCRB_PB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10852 | #define PWR_PUCRB_PB14_Msk (0x1U << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10853 | #define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10854 | #define PWR_PUCRB_PB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10855 | #define PWR_PUCRB_PB13_Msk (0x1U << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10856 | #define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10857 | #define PWR_PUCRB_PB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10858 | #define PWR_PUCRB_PB12_Msk (0x1U << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10859 | #define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10860 | #define PWR_PUCRB_PB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10861 | #define PWR_PUCRB_PB11_Msk (0x1U << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10862 | #define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10863 | #define PWR_PUCRB_PB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10864 | #define PWR_PUCRB_PB10_Msk (0x1U << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10865 | #define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10866 | #define PWR_PUCRB_PB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10867 | #define PWR_PUCRB_PB9_Msk (0x1U << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10868 | #define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10869 | #define PWR_PUCRB_PB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10870 | #define PWR_PUCRB_PB8_Msk (0x1U << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10871 | #define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10872 | #define PWR_PUCRB_PB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10873 | #define PWR_PUCRB_PB7_Msk (0x1U << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10874 | #define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10875 | #define PWR_PUCRB_PB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10876 | #define PWR_PUCRB_PB6_Msk (0x1U << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10877 | #define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10878 | #define PWR_PUCRB_PB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10879 | #define PWR_PUCRB_PB5_Msk (0x1U << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10880 | #define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10881 | #define PWR_PUCRB_PB4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10882 | #define PWR_PUCRB_PB4_Msk (0x1U << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10883 | #define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10884 | #define PWR_PUCRB_PB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10885 | #define PWR_PUCRB_PB3_Msk (0x1U << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10886 | #define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10887 | #define PWR_PUCRB_PB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10888 | #define PWR_PUCRB_PB2_Msk (0x1U << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10889 | #define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10890 | #define PWR_PUCRB_PB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10891 | #define PWR_PUCRB_PB1_Msk (0x1U << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10892 | #define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10893 | #define PWR_PUCRB_PB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10894 | #define PWR_PUCRB_PB0_Msk (0x1U << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10895 | #define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10896 | |
| AnnaBridge | 172:65be27845400 | 10897 | /******************** Bit definition for PWR_PDCRB register ********************/ |
| AnnaBridge | 172:65be27845400 | 10898 | #define PWR_PDCRB_PB15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10899 | #define PWR_PDCRB_PB15_Msk (0x1U << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10900 | #define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10901 | #define PWR_PDCRB_PB14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10902 | #define PWR_PDCRB_PB14_Msk (0x1U << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10903 | #define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10904 | #define PWR_PDCRB_PB13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10905 | #define PWR_PDCRB_PB13_Msk (0x1U << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10906 | #define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10907 | #define PWR_PDCRB_PB12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10908 | #define PWR_PDCRB_PB12_Msk (0x1U << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10909 | #define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10910 | #define PWR_PDCRB_PB11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10911 | #define PWR_PDCRB_PB11_Msk (0x1U << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10912 | #define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10913 | #define PWR_PDCRB_PB10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10914 | #define PWR_PDCRB_PB10_Msk (0x1U << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10915 | #define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10916 | #define PWR_PDCRB_PB9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10917 | #define PWR_PDCRB_PB9_Msk (0x1U << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10918 | #define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10919 | #define PWR_PDCRB_PB8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10920 | #define PWR_PDCRB_PB8_Msk (0x1U << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10921 | #define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10922 | #define PWR_PDCRB_PB7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10923 | #define PWR_PDCRB_PB7_Msk (0x1U << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10924 | #define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10925 | #define PWR_PDCRB_PB6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10926 | #define PWR_PDCRB_PB6_Msk (0x1U << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10927 | #define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10928 | #define PWR_PDCRB_PB5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10929 | #define PWR_PDCRB_PB5_Msk (0x1U << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10930 | #define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10931 | #define PWR_PDCRB_PB3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10932 | #define PWR_PDCRB_PB3_Msk (0x1U << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10933 | #define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10934 | #define PWR_PDCRB_PB2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10935 | #define PWR_PDCRB_PB2_Msk (0x1U << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10936 | #define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10937 | #define PWR_PDCRB_PB1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10938 | #define PWR_PDCRB_PB1_Msk (0x1U << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10939 | #define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10940 | #define PWR_PDCRB_PB0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10941 | #define PWR_PDCRB_PB0_Msk (0x1U << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10942 | #define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10943 | |
| AnnaBridge | 172:65be27845400 | 10944 | /******************** Bit definition for PWR_PUCRC register ********************/ |
| AnnaBridge | 172:65be27845400 | 10945 | #define PWR_PUCRC_PC15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10946 | #define PWR_PUCRC_PC15_Msk (0x1U << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10947 | #define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10948 | #define PWR_PUCRC_PC14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10949 | #define PWR_PUCRC_PC14_Msk (0x1U << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 10950 | #define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10951 | #define PWR_PUCRC_PC13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 10952 | #define PWR_PUCRC_PC13_Msk (0x1U << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 10953 | #define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10954 | #define PWR_PUCRC_PC12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 10955 | #define PWR_PUCRC_PC12_Msk (0x1U << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 10956 | #define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10957 | #define PWR_PUCRC_PC11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 10958 | #define PWR_PUCRC_PC11_Msk (0x1U << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 10959 | #define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10960 | #define PWR_PUCRC_PC10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 10961 | #define PWR_PUCRC_PC10_Msk (0x1U << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 10962 | #define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10963 | #define PWR_PUCRC_PC9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 10964 | #define PWR_PUCRC_PC9_Msk (0x1U << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 10965 | #define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10966 | #define PWR_PUCRC_PC8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 10967 | #define PWR_PUCRC_PC8_Msk (0x1U << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 10968 | #define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10969 | #define PWR_PUCRC_PC7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 10970 | #define PWR_PUCRC_PC7_Msk (0x1U << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 10971 | #define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10972 | #define PWR_PUCRC_PC6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 10973 | #define PWR_PUCRC_PC6_Msk (0x1U << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 10974 | #define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10975 | #define PWR_PUCRC_PC5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 10976 | #define PWR_PUCRC_PC5_Msk (0x1U << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 10977 | #define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10978 | #define PWR_PUCRC_PC4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 10979 | #define PWR_PUCRC_PC4_Msk (0x1U << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 10980 | #define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10981 | #define PWR_PUCRC_PC3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 10982 | #define PWR_PUCRC_PC3_Msk (0x1U << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 10983 | #define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10984 | #define PWR_PUCRC_PC2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 10985 | #define PWR_PUCRC_PC2_Msk (0x1U << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 10986 | #define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10987 | #define PWR_PUCRC_PC1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 10988 | #define PWR_PUCRC_PC1_Msk (0x1U << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 10989 | #define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10990 | #define PWR_PUCRC_PC0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 10991 | #define PWR_PUCRC_PC0_Msk (0x1U << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 10992 | #define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 10993 | |
| AnnaBridge | 172:65be27845400 | 10994 | /******************** Bit definition for PWR_PDCRC register ********************/ |
| AnnaBridge | 172:65be27845400 | 10995 | #define PWR_PDCRC_PC15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 10996 | #define PWR_PDCRC_PC15_Msk (0x1U << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 10997 | #define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 10998 | #define PWR_PDCRC_PC14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 10999 | #define PWR_PDCRC_PC14_Msk (0x1U << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11000 | #define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11001 | #define PWR_PDCRC_PC13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11002 | #define PWR_PDCRC_PC13_Msk (0x1U << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11003 | #define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11004 | #define PWR_PDCRC_PC12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11005 | #define PWR_PDCRC_PC12_Msk (0x1U << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11006 | #define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11007 | #define PWR_PDCRC_PC11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11008 | #define PWR_PDCRC_PC11_Msk (0x1U << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11009 | #define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11010 | #define PWR_PDCRC_PC10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11011 | #define PWR_PDCRC_PC10_Msk (0x1U << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11012 | #define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11013 | #define PWR_PDCRC_PC9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11014 | #define PWR_PDCRC_PC9_Msk (0x1U << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11015 | #define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11016 | #define PWR_PDCRC_PC8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11017 | #define PWR_PDCRC_PC8_Msk (0x1U << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11018 | #define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11019 | #define PWR_PDCRC_PC7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11020 | #define PWR_PDCRC_PC7_Msk (0x1U << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11021 | #define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11022 | #define PWR_PDCRC_PC6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11023 | #define PWR_PDCRC_PC6_Msk (0x1U << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11024 | #define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11025 | #define PWR_PDCRC_PC5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11026 | #define PWR_PDCRC_PC5_Msk (0x1U << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11027 | #define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11028 | #define PWR_PDCRC_PC4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11029 | #define PWR_PDCRC_PC4_Msk (0x1U << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11030 | #define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11031 | #define PWR_PDCRC_PC3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11032 | #define PWR_PDCRC_PC3_Msk (0x1U << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11033 | #define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11034 | #define PWR_PDCRC_PC2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11035 | #define PWR_PDCRC_PC2_Msk (0x1U << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11036 | #define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11037 | #define PWR_PDCRC_PC1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11038 | #define PWR_PDCRC_PC1_Msk (0x1U << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11039 | #define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11040 | #define PWR_PDCRC_PC0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11041 | #define PWR_PDCRC_PC0_Msk (0x1U << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11042 | #define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11043 | |
| AnnaBridge | 172:65be27845400 | 11044 | /******************** Bit definition for PWR_PUCRD register ********************/ |
| AnnaBridge | 172:65be27845400 | 11045 | #define PWR_PUCRD_PD15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11046 | #define PWR_PUCRD_PD15_Msk (0x1U << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11047 | #define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11048 | #define PWR_PUCRD_PD14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11049 | #define PWR_PUCRD_PD14_Msk (0x1U << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11050 | #define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11051 | #define PWR_PUCRD_PD13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11052 | #define PWR_PUCRD_PD13_Msk (0x1U << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11053 | #define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11054 | #define PWR_PUCRD_PD12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11055 | #define PWR_PUCRD_PD12_Msk (0x1U << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11056 | #define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11057 | #define PWR_PUCRD_PD11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11058 | #define PWR_PUCRD_PD11_Msk (0x1U << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11059 | #define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11060 | #define PWR_PUCRD_PD10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11061 | #define PWR_PUCRD_PD10_Msk (0x1U << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11062 | #define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11063 | #define PWR_PUCRD_PD9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11064 | #define PWR_PUCRD_PD9_Msk (0x1U << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11065 | #define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11066 | #define PWR_PUCRD_PD8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11067 | #define PWR_PUCRD_PD8_Msk (0x1U << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11068 | #define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11069 | #define PWR_PUCRD_PD7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11070 | #define PWR_PUCRD_PD7_Msk (0x1U << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11071 | #define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11072 | #define PWR_PUCRD_PD6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11073 | #define PWR_PUCRD_PD6_Msk (0x1U << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11074 | #define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11075 | #define PWR_PUCRD_PD5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11076 | #define PWR_PUCRD_PD5_Msk (0x1U << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11077 | #define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11078 | #define PWR_PUCRD_PD4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11079 | #define PWR_PUCRD_PD4_Msk (0x1U << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11080 | #define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11081 | #define PWR_PUCRD_PD3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11082 | #define PWR_PUCRD_PD3_Msk (0x1U << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11083 | #define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11084 | #define PWR_PUCRD_PD2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11085 | #define PWR_PUCRD_PD2_Msk (0x1U << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11086 | #define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11087 | #define PWR_PUCRD_PD1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11088 | #define PWR_PUCRD_PD1_Msk (0x1U << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11089 | #define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11090 | #define PWR_PUCRD_PD0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11091 | #define PWR_PUCRD_PD0_Msk (0x1U << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11092 | #define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11093 | |
| AnnaBridge | 172:65be27845400 | 11094 | /******************** Bit definition for PWR_PDCRD register ********************/ |
| AnnaBridge | 172:65be27845400 | 11095 | #define PWR_PDCRD_PD15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11096 | #define PWR_PDCRD_PD15_Msk (0x1U << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11097 | #define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11098 | #define PWR_PDCRD_PD14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11099 | #define PWR_PDCRD_PD14_Msk (0x1U << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11100 | #define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11101 | #define PWR_PDCRD_PD13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11102 | #define PWR_PDCRD_PD13_Msk (0x1U << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11103 | #define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11104 | #define PWR_PDCRD_PD12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11105 | #define PWR_PDCRD_PD12_Msk (0x1U << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11106 | #define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11107 | #define PWR_PDCRD_PD11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11108 | #define PWR_PDCRD_PD11_Msk (0x1U << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11109 | #define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11110 | #define PWR_PDCRD_PD10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11111 | #define PWR_PDCRD_PD10_Msk (0x1U << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11112 | #define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11113 | #define PWR_PDCRD_PD9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11114 | #define PWR_PDCRD_PD9_Msk (0x1U << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11115 | #define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11116 | #define PWR_PDCRD_PD8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11117 | #define PWR_PDCRD_PD8_Msk (0x1U << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11118 | #define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11119 | #define PWR_PDCRD_PD7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11120 | #define PWR_PDCRD_PD7_Msk (0x1U << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11121 | #define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11122 | #define PWR_PDCRD_PD6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11123 | #define PWR_PDCRD_PD6_Msk (0x1U << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11124 | #define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11125 | #define PWR_PDCRD_PD5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11126 | #define PWR_PDCRD_PD5_Msk (0x1U << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11127 | #define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11128 | #define PWR_PDCRD_PD4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11129 | #define PWR_PDCRD_PD4_Msk (0x1U << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11130 | #define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11131 | #define PWR_PDCRD_PD3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11132 | #define PWR_PDCRD_PD3_Msk (0x1U << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11133 | #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11134 | #define PWR_PDCRD_PD2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11135 | #define PWR_PDCRD_PD2_Msk (0x1U << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11136 | #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11137 | #define PWR_PDCRD_PD1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11138 | #define PWR_PDCRD_PD1_Msk (0x1U << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11139 | #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11140 | #define PWR_PDCRD_PD0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11141 | #define PWR_PDCRD_PD0_Msk (0x1U << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11142 | #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11143 | |
| AnnaBridge | 172:65be27845400 | 11144 | /******************** Bit definition for PWR_PUCRE register ********************/ |
| AnnaBridge | 172:65be27845400 | 11145 | #define PWR_PUCRE_PE15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11146 | #define PWR_PUCRE_PE15_Msk (0x1U << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11147 | #define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11148 | #define PWR_PUCRE_PE14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11149 | #define PWR_PUCRE_PE14_Msk (0x1U << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11150 | #define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11151 | #define PWR_PUCRE_PE13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11152 | #define PWR_PUCRE_PE13_Msk (0x1U << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11153 | #define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11154 | #define PWR_PUCRE_PE12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11155 | #define PWR_PUCRE_PE12_Msk (0x1U << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11156 | #define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11157 | #define PWR_PUCRE_PE11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11158 | #define PWR_PUCRE_PE11_Msk (0x1U << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11159 | #define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11160 | #define PWR_PUCRE_PE10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11161 | #define PWR_PUCRE_PE10_Msk (0x1U << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11162 | #define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11163 | #define PWR_PUCRE_PE9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11164 | #define PWR_PUCRE_PE9_Msk (0x1U << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11165 | #define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11166 | #define PWR_PUCRE_PE8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11167 | #define PWR_PUCRE_PE8_Msk (0x1U << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11168 | #define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11169 | #define PWR_PUCRE_PE7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11170 | #define PWR_PUCRE_PE7_Msk (0x1U << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11171 | #define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11172 | #define PWR_PUCRE_PE6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11173 | #define PWR_PUCRE_PE6_Msk (0x1U << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11174 | #define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11175 | #define PWR_PUCRE_PE5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11176 | #define PWR_PUCRE_PE5_Msk (0x1U << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11177 | #define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11178 | #define PWR_PUCRE_PE4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11179 | #define PWR_PUCRE_PE4_Msk (0x1U << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11180 | #define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11181 | #define PWR_PUCRE_PE3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11182 | #define PWR_PUCRE_PE3_Msk (0x1U << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11183 | #define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11184 | #define PWR_PUCRE_PE2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11185 | #define PWR_PUCRE_PE2_Msk (0x1U << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11186 | #define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11187 | #define PWR_PUCRE_PE1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11188 | #define PWR_PUCRE_PE1_Msk (0x1U << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11189 | #define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11190 | #define PWR_PUCRE_PE0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11191 | #define PWR_PUCRE_PE0_Msk (0x1U << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11192 | #define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11193 | |
| AnnaBridge | 172:65be27845400 | 11194 | /******************** Bit definition for PWR_PDCRE register ********************/ |
| AnnaBridge | 172:65be27845400 | 11195 | #define PWR_PDCRE_PE15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11196 | #define PWR_PDCRE_PE15_Msk (0x1U << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11197 | #define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11198 | #define PWR_PDCRE_PE14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11199 | #define PWR_PDCRE_PE14_Msk (0x1U << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11200 | #define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11201 | #define PWR_PDCRE_PE13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11202 | #define PWR_PDCRE_PE13_Msk (0x1U << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11203 | #define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11204 | #define PWR_PDCRE_PE12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11205 | #define PWR_PDCRE_PE12_Msk (0x1U << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11206 | #define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11207 | #define PWR_PDCRE_PE11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11208 | #define PWR_PDCRE_PE11_Msk (0x1U << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11209 | #define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11210 | #define PWR_PDCRE_PE10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11211 | #define PWR_PDCRE_PE10_Msk (0x1U << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11212 | #define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11213 | #define PWR_PDCRE_PE9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11214 | #define PWR_PDCRE_PE9_Msk (0x1U << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11215 | #define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11216 | #define PWR_PDCRE_PE8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11217 | #define PWR_PDCRE_PE8_Msk (0x1U << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11218 | #define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11219 | #define PWR_PDCRE_PE7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11220 | #define PWR_PDCRE_PE7_Msk (0x1U << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11221 | #define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11222 | #define PWR_PDCRE_PE6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11223 | #define PWR_PDCRE_PE6_Msk (0x1U << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11224 | #define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11225 | #define PWR_PDCRE_PE5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11226 | #define PWR_PDCRE_PE5_Msk (0x1U << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11227 | #define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11228 | #define PWR_PDCRE_PE4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11229 | #define PWR_PDCRE_PE4_Msk (0x1U << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11230 | #define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11231 | #define PWR_PDCRE_PE3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11232 | #define PWR_PDCRE_PE3_Msk (0x1U << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11233 | #define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11234 | #define PWR_PDCRE_PE2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11235 | #define PWR_PDCRE_PE2_Msk (0x1U << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11236 | #define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11237 | #define PWR_PDCRE_PE1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11238 | #define PWR_PDCRE_PE1_Msk (0x1U << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11239 | #define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11240 | #define PWR_PDCRE_PE0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11241 | #define PWR_PDCRE_PE0_Msk (0x1U << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11242 | #define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11243 | |
| AnnaBridge | 172:65be27845400 | 11244 | /******************** Bit definition for PWR_PUCRF register ********************/ |
| AnnaBridge | 172:65be27845400 | 11245 | #define PWR_PUCRF_PF15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11246 | #define PWR_PUCRF_PF15_Msk (0x1U << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11247 | #define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11248 | #define PWR_PUCRF_PF14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11249 | #define PWR_PUCRF_PF14_Msk (0x1U << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11250 | #define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11251 | #define PWR_PUCRF_PF13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11252 | #define PWR_PUCRF_PF13_Msk (0x1U << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11253 | #define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11254 | #define PWR_PUCRF_PF12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11255 | #define PWR_PUCRF_PF12_Msk (0x1U << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11256 | #define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11257 | #define PWR_PUCRF_PF11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11258 | #define PWR_PUCRF_PF11_Msk (0x1U << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11259 | #define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11260 | #define PWR_PUCRF_PF10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11261 | #define PWR_PUCRF_PF10_Msk (0x1U << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11262 | #define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11263 | #define PWR_PUCRF_PF9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11264 | #define PWR_PUCRF_PF9_Msk (0x1U << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11265 | #define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11266 | #define PWR_PUCRF_PF8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11267 | #define PWR_PUCRF_PF8_Msk (0x1U << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11268 | #define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11269 | #define PWR_PUCRF_PF7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11270 | #define PWR_PUCRF_PF7_Msk (0x1U << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11271 | #define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11272 | #define PWR_PUCRF_PF6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11273 | #define PWR_PUCRF_PF6_Msk (0x1U << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11274 | #define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11275 | #define PWR_PUCRF_PF5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11276 | #define PWR_PUCRF_PF5_Msk (0x1U << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11277 | #define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11278 | #define PWR_PUCRF_PF4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11279 | #define PWR_PUCRF_PF4_Msk (0x1U << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11280 | #define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11281 | #define PWR_PUCRF_PF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11282 | #define PWR_PUCRF_PF3_Msk (0x1U << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11283 | #define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11284 | #define PWR_PUCRF_PF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11285 | #define PWR_PUCRF_PF2_Msk (0x1U << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11286 | #define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11287 | #define PWR_PUCRF_PF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11288 | #define PWR_PUCRF_PF1_Msk (0x1U << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11289 | #define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11290 | #define PWR_PUCRF_PF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11291 | #define PWR_PUCRF_PF0_Msk (0x1U << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11292 | #define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11293 | |
| AnnaBridge | 172:65be27845400 | 11294 | /******************** Bit definition for PWR_PDCRF register ********************/ |
| AnnaBridge | 172:65be27845400 | 11295 | #define PWR_PDCRF_PF15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11296 | #define PWR_PDCRF_PF15_Msk (0x1U << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11297 | #define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11298 | #define PWR_PDCRF_PF14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11299 | #define PWR_PDCRF_PF14_Msk (0x1U << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11300 | #define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11301 | #define PWR_PDCRF_PF13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11302 | #define PWR_PDCRF_PF13_Msk (0x1U << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11303 | #define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11304 | #define PWR_PDCRF_PF12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11305 | #define PWR_PDCRF_PF12_Msk (0x1U << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11306 | #define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11307 | #define PWR_PDCRF_PF11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11308 | #define PWR_PDCRF_PF11_Msk (0x1U << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11309 | #define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11310 | #define PWR_PDCRF_PF10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11311 | #define PWR_PDCRF_PF10_Msk (0x1U << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11312 | #define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11313 | #define PWR_PDCRF_PF9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11314 | #define PWR_PDCRF_PF9_Msk (0x1U << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11315 | #define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11316 | #define PWR_PDCRF_PF8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11317 | #define PWR_PDCRF_PF8_Msk (0x1U << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11318 | #define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11319 | #define PWR_PDCRF_PF7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11320 | #define PWR_PDCRF_PF7_Msk (0x1U << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11321 | #define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11322 | #define PWR_PDCRF_PF6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11323 | #define PWR_PDCRF_PF6_Msk (0x1U << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11324 | #define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11325 | #define PWR_PDCRF_PF5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11326 | #define PWR_PDCRF_PF5_Msk (0x1U << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11327 | #define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11328 | #define PWR_PDCRF_PF4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11329 | #define PWR_PDCRF_PF4_Msk (0x1U << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11330 | #define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11331 | #define PWR_PDCRF_PF3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11332 | #define PWR_PDCRF_PF3_Msk (0x1U << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11333 | #define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11334 | #define PWR_PDCRF_PF2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11335 | #define PWR_PDCRF_PF2_Msk (0x1U << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11336 | #define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11337 | #define PWR_PDCRF_PF1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11338 | #define PWR_PDCRF_PF1_Msk (0x1U << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11339 | #define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11340 | #define PWR_PDCRF_PF0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11341 | #define PWR_PDCRF_PF0_Msk (0x1U << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11342 | #define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11343 | |
| AnnaBridge | 172:65be27845400 | 11344 | /******************** Bit definition for PWR_PUCRG register ********************/ |
| AnnaBridge | 172:65be27845400 | 11345 | #define PWR_PUCRG_PG15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11346 | #define PWR_PUCRG_PG15_Msk (0x1U << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11347 | #define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11348 | #define PWR_PUCRG_PG14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11349 | #define PWR_PUCRG_PG14_Msk (0x1U << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11350 | #define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11351 | #define PWR_PUCRG_PG13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11352 | #define PWR_PUCRG_PG13_Msk (0x1U << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11353 | #define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11354 | #define PWR_PUCRG_PG12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11355 | #define PWR_PUCRG_PG12_Msk (0x1U << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11356 | #define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11357 | #define PWR_PUCRG_PG11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11358 | #define PWR_PUCRG_PG11_Msk (0x1U << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11359 | #define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11360 | #define PWR_PUCRG_PG10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11361 | #define PWR_PUCRG_PG10_Msk (0x1U << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11362 | #define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11363 | #define PWR_PUCRG_PG9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11364 | #define PWR_PUCRG_PG9_Msk (0x1U << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11365 | #define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11366 | #define PWR_PUCRG_PG8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11367 | #define PWR_PUCRG_PG8_Msk (0x1U << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11368 | #define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11369 | #define PWR_PUCRG_PG7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11370 | #define PWR_PUCRG_PG7_Msk (0x1U << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11371 | #define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11372 | #define PWR_PUCRG_PG6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11373 | #define PWR_PUCRG_PG6_Msk (0x1U << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11374 | #define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11375 | #define PWR_PUCRG_PG5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11376 | #define PWR_PUCRG_PG5_Msk (0x1U << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11377 | #define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11378 | #define PWR_PUCRG_PG4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11379 | #define PWR_PUCRG_PG4_Msk (0x1U << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11380 | #define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11381 | #define PWR_PUCRG_PG3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11382 | #define PWR_PUCRG_PG3_Msk (0x1U << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11383 | #define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11384 | #define PWR_PUCRG_PG2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11385 | #define PWR_PUCRG_PG2_Msk (0x1U << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11386 | #define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11387 | #define PWR_PUCRG_PG1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11388 | #define PWR_PUCRG_PG1_Msk (0x1U << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11389 | #define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11390 | #define PWR_PUCRG_PG0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11391 | #define PWR_PUCRG_PG0_Msk (0x1U << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11392 | #define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11393 | |
| AnnaBridge | 172:65be27845400 | 11394 | /******************** Bit definition for PWR_PDCRG register ********************/ |
| AnnaBridge | 172:65be27845400 | 11395 | #define PWR_PDCRG_PG15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11396 | #define PWR_PDCRG_PG15_Msk (0x1U << PWR_PDCRG_PG15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11397 | #define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk /*!< Port PG15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11398 | #define PWR_PDCRG_PG14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11399 | #define PWR_PDCRG_PG14_Msk (0x1U << PWR_PDCRG_PG14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11400 | #define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk /*!< Port PG14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11401 | #define PWR_PDCRG_PG13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11402 | #define PWR_PDCRG_PG13_Msk (0x1U << PWR_PDCRG_PG13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11403 | #define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk /*!< Port PG13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11404 | #define PWR_PDCRG_PG12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11405 | #define PWR_PDCRG_PG12_Msk (0x1U << PWR_PDCRG_PG12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11406 | #define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk /*!< Port PG12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11407 | #define PWR_PDCRG_PG11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11408 | #define PWR_PDCRG_PG11_Msk (0x1U << PWR_PDCRG_PG11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11409 | #define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk /*!< Port PG11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11410 | #define PWR_PDCRG_PG10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11411 | #define PWR_PDCRG_PG10_Msk (0x1U << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11412 | #define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11413 | #define PWR_PDCRG_PG9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11414 | #define PWR_PDCRG_PG9_Msk (0x1U << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11415 | #define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11416 | #define PWR_PDCRG_PG8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11417 | #define PWR_PDCRG_PG8_Msk (0x1U << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11418 | #define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11419 | #define PWR_PDCRG_PG7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11420 | #define PWR_PDCRG_PG7_Msk (0x1U << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11421 | #define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11422 | #define PWR_PDCRG_PG6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11423 | #define PWR_PDCRG_PG6_Msk (0x1U << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11424 | #define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11425 | #define PWR_PDCRG_PG5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11426 | #define PWR_PDCRG_PG5_Msk (0x1U << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11427 | #define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11428 | #define PWR_PDCRG_PG4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11429 | #define PWR_PDCRG_PG4_Msk (0x1U << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11430 | #define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11431 | #define PWR_PDCRG_PG3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11432 | #define PWR_PDCRG_PG3_Msk (0x1U << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11433 | #define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11434 | #define PWR_PDCRG_PG2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11435 | #define PWR_PDCRG_PG2_Msk (0x1U << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11436 | #define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11437 | #define PWR_PDCRG_PG1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11438 | #define PWR_PDCRG_PG1_Msk (0x1U << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11439 | #define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11440 | #define PWR_PDCRG_PG0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11441 | #define PWR_PDCRG_PG0_Msk (0x1U << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11442 | #define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11443 | |
| AnnaBridge | 172:65be27845400 | 11444 | /******************** Bit definition for PWR_PUCRH register ********************/ |
| AnnaBridge | 172:65be27845400 | 11445 | #define PWR_PUCRH_PH15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11446 | #define PWR_PUCRH_PH15_Msk (0x1U << PWR_PUCRH_PH15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11447 | #define PWR_PUCRH_PH15 PWR_PUCRH_PH15_Msk /*!< Port PH15 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11448 | #define PWR_PUCRH_PH14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11449 | #define PWR_PUCRH_PH14_Msk (0x1U << PWR_PUCRH_PH14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11450 | #define PWR_PUCRH_PH14 PWR_PUCRH_PH14_Msk /*!< Port PH14 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11451 | #define PWR_PUCRH_PH13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11452 | #define PWR_PUCRH_PH13_Msk (0x1U << PWR_PUCRH_PH13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11453 | #define PWR_PUCRH_PH13 PWR_PUCRH_PH13_Msk /*!< Port PH13 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11454 | #define PWR_PUCRH_PH12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11455 | #define PWR_PUCRH_PH12_Msk (0x1U << PWR_PUCRH_PH12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11456 | #define PWR_PUCRH_PH12 PWR_PUCRH_PH12_Msk /*!< Port PH12 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11457 | #define PWR_PUCRH_PH11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11458 | #define PWR_PUCRH_PH11_Msk (0x1U << PWR_PUCRH_PH11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11459 | #define PWR_PUCRH_PH11 PWR_PUCRH_PH11_Msk /*!< Port PH11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11460 | #define PWR_PUCRH_PH10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11461 | #define PWR_PUCRH_PH10_Msk (0x1U << PWR_PUCRH_PH10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11462 | #define PWR_PUCRH_PH10 PWR_PUCRH_PH10_Msk /*!< Port PH10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11463 | #define PWR_PUCRH_PH9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11464 | #define PWR_PUCRH_PH9_Msk (0x1U << PWR_PUCRH_PH9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11465 | #define PWR_PUCRH_PH9 PWR_PUCRH_PH9_Msk /*!< Port PH9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11466 | #define PWR_PUCRH_PH8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11467 | #define PWR_PUCRH_PH8_Msk (0x1U << PWR_PUCRH_PH8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11468 | #define PWR_PUCRH_PH8 PWR_PUCRH_PH8_Msk /*!< Port PH8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11469 | #define PWR_PUCRH_PH7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11470 | #define PWR_PUCRH_PH7_Msk (0x1U << PWR_PUCRH_PH7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11471 | #define PWR_PUCRH_PH7 PWR_PUCRH_PH7_Msk /*!< Port PH7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11472 | #define PWR_PUCRH_PH6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11473 | #define PWR_PUCRH_PH6_Msk (0x1U << PWR_PUCRH_PH6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11474 | #define PWR_PUCRH_PH6 PWR_PUCRH_PH6_Msk /*!< Port PH6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11475 | #define PWR_PUCRH_PH5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11476 | #define PWR_PUCRH_PH5_Msk (0x1U << PWR_PUCRH_PH5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11477 | #define PWR_PUCRH_PH5 PWR_PUCRH_PH5_Msk /*!< Port PH5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11478 | #define PWR_PUCRH_PH4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11479 | #define PWR_PUCRH_PH4_Msk (0x1U << PWR_PUCRH_PH4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11480 | #define PWR_PUCRH_PH4 PWR_PUCRH_PH4_Msk /*!< Port PH4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11481 | #define PWR_PUCRH_PH3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11482 | #define PWR_PUCRH_PH3_Msk (0x1U << PWR_PUCRH_PH3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11483 | #define PWR_PUCRH_PH3 PWR_PUCRH_PH3_Msk /*!< Port PH3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11484 | #define PWR_PUCRH_PH2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11485 | #define PWR_PUCRH_PH2_Msk (0x1U << PWR_PUCRH_PH2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11486 | #define PWR_PUCRH_PH2 PWR_PUCRH_PH2_Msk /*!< Port PH2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11487 | #define PWR_PUCRH_PH1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11488 | #define PWR_PUCRH_PH1_Msk (0x1U << PWR_PUCRH_PH1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11489 | #define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk /*!< Port PH1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11490 | #define PWR_PUCRH_PH0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11491 | #define PWR_PUCRH_PH0_Msk (0x1U << PWR_PUCRH_PH0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11492 | #define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk /*!< Port PH0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11493 | |
| AnnaBridge | 172:65be27845400 | 11494 | /******************** Bit definition for PWR_PDCRH register ********************/ |
| AnnaBridge | 172:65be27845400 | 11495 | #define PWR_PDCRH_PH15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11496 | #define PWR_PDCRH_PH15_Msk (0x1U << PWR_PDCRH_PH15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11497 | #define PWR_PDCRH_PH15 PWR_PDCRH_PH15_Msk /*!< Port PH15 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11498 | #define PWR_PDCRH_PH14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 11499 | #define PWR_PDCRH_PH14_Msk (0x1U << PWR_PDCRH_PH14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11500 | #define PWR_PDCRH_PH14 PWR_PDCRH_PH14_Msk /*!< Port PH14 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11501 | #define PWR_PDCRH_PH13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 11502 | #define PWR_PDCRH_PH13_Msk (0x1U << PWR_PDCRH_PH13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11503 | #define PWR_PDCRH_PH13 PWR_PDCRH_PH13_Msk /*!< Port PH13 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11504 | #define PWR_PDCRH_PH12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 11505 | #define PWR_PDCRH_PH12_Msk (0x1U << PWR_PDCRH_PH12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11506 | #define PWR_PDCRH_PH12 PWR_PDCRH_PH12_Msk /*!< Port PH12 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11507 | #define PWR_PDCRH_PH11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11508 | #define PWR_PDCRH_PH11_Msk (0x1U << PWR_PDCRH_PH11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11509 | #define PWR_PDCRH_PH11 PWR_PDCRH_PH11_Msk /*!< Port PH11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11510 | #define PWR_PDCRH_PH10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11511 | #define PWR_PDCRH_PH10_Msk (0x1U << PWR_PDCRH_PH10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11512 | #define PWR_PDCRH_PH10 PWR_PDCRH_PH10_Msk /*!< Port PH10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11513 | #define PWR_PDCRH_PH9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11514 | #define PWR_PDCRH_PH9_Msk (0x1U << PWR_PDCRH_PH9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11515 | #define PWR_PDCRH_PH9 PWR_PDCRH_PH9_Msk /*!< Port PH9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11516 | #define PWR_PDCRH_PH8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11517 | #define PWR_PDCRH_PH8_Msk (0x1U << PWR_PDCRH_PH8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11518 | #define PWR_PDCRH_PH8 PWR_PDCRH_PH8_Msk /*!< Port PH8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11519 | #define PWR_PDCRH_PH7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11520 | #define PWR_PDCRH_PH7_Msk (0x1U << PWR_PDCRH_PH7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11521 | #define PWR_PDCRH_PH7 PWR_PDCRH_PH7_Msk /*!< Port PH7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11522 | #define PWR_PDCRH_PH6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11523 | #define PWR_PDCRH_PH6_Msk (0x1U << PWR_PDCRH_PH6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11524 | #define PWR_PDCRH_PH6 PWR_PDCRH_PH6_Msk /*!< Port PH6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11525 | #define PWR_PDCRH_PH5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11526 | #define PWR_PDCRH_PH5_Msk (0x1U << PWR_PDCRH_PH5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11527 | #define PWR_PDCRH_PH5 PWR_PDCRH_PH5_Msk /*!< Port PH5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11528 | #define PWR_PDCRH_PH4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11529 | #define PWR_PDCRH_PH4_Msk (0x1U << PWR_PDCRH_PH4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11530 | #define PWR_PDCRH_PH4 PWR_PDCRH_PH4_Msk /*!< Port PH4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11531 | #define PWR_PDCRH_PH3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11532 | #define PWR_PDCRH_PH3_Msk (0x1U << PWR_PDCRH_PH3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11533 | #define PWR_PDCRH_PH3 PWR_PDCRH_PH3_Msk /*!< Port PH3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11534 | #define PWR_PDCRH_PH2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11535 | #define PWR_PDCRH_PH2_Msk (0x1U << PWR_PDCRH_PH2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11536 | #define PWR_PDCRH_PH2 PWR_PDCRH_PH2_Msk /*!< Port PH1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11537 | #define PWR_PDCRH_PH1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11538 | #define PWR_PDCRH_PH1_Msk (0x1U << PWR_PDCRH_PH1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11539 | #define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk /*!< Port PH1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11540 | #define PWR_PDCRH_PH0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11541 | #define PWR_PDCRH_PH0_Msk (0x1U << PWR_PDCRH_PH0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11542 | #define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk /*!< Port PH0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11543 | |
| AnnaBridge | 172:65be27845400 | 11544 | /******************** Bit definition for PWR_PUCRI register ********************/ |
| AnnaBridge | 172:65be27845400 | 11545 | #define PWR_PUCRI_PI11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11546 | #define PWR_PUCRI_PI11_Msk (0x1U << PWR_PUCRI_PI11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11547 | #define PWR_PUCRI_PI11 PWR_PUCRI_PI11_Msk /*!< Port PI11 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11548 | #define PWR_PUCRI_PI10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11549 | #define PWR_PUCRI_PI10_Msk (0x1U << PWR_PUCRI_PI10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11550 | #define PWR_PUCRI_PI10 PWR_PUCRI_PI10_Msk /*!< Port PI10 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11551 | #define PWR_PUCRI_PI9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11552 | #define PWR_PUCRI_PI9_Msk (0x1U << PWR_PUCRI_PI9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11553 | #define PWR_PUCRI_PI9 PWR_PUCRI_PI9_Msk /*!< Port PI9 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11554 | #define PWR_PUCRI_PI8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11555 | #define PWR_PUCRI_PI8_Msk (0x1U << PWR_PUCRI_PI8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11556 | #define PWR_PUCRI_PI8 PWR_PUCRI_PI8_Msk /*!< Port PI8 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11557 | #define PWR_PUCRI_PI7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11558 | #define PWR_PUCRI_PI7_Msk (0x1U << PWR_PUCRI_PI7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11559 | #define PWR_PUCRI_PI7 PWR_PUCRI_PI7_Msk /*!< Port PI7 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11560 | #define PWR_PUCRI_PI6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11561 | #define PWR_PUCRI_PI6_Msk (0x1U << PWR_PUCRI_PI6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11562 | #define PWR_PUCRI_PI6 PWR_PUCRI_PI6_Msk /*!< Port PI6 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11563 | #define PWR_PUCRI_PI5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11564 | #define PWR_PUCRI_PI5_Msk (0x1U << PWR_PUCRI_PI5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11565 | #define PWR_PUCRI_PI5 PWR_PUCRI_PI5_Msk /*!< Port PI5 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11566 | #define PWR_PUCRI_PI4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11567 | #define PWR_PUCRI_PI4_Msk (0x1U << PWR_PUCRI_PI4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11568 | #define PWR_PUCRI_PI4 PWR_PUCRI_PI4_Msk /*!< Port PI4 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11569 | #define PWR_PUCRI_PI3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11570 | #define PWR_PUCRI_PI3_Msk (0x1U << PWR_PUCRI_PI3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11571 | #define PWR_PUCRI_PI3 PWR_PUCRI_PI3_Msk /*!< Port PI3 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11572 | #define PWR_PUCRI_PI2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11573 | #define PWR_PUCRI_PI2_Msk (0x1U << PWR_PUCRI_PI2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11574 | #define PWR_PUCRI_PI2 PWR_PUCRI_PI2_Msk /*!< Port PI2 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11575 | #define PWR_PUCRI_PI1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11576 | #define PWR_PUCRI_PI1_Msk (0x1U << PWR_PUCRI_PI1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11577 | #define PWR_PUCRI_PI1 PWR_PUCRI_PI1_Msk /*!< Port PI1 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11578 | #define PWR_PUCRI_PI0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11579 | #define PWR_PUCRI_PI0_Msk (0x1U << PWR_PUCRI_PI0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11580 | #define PWR_PUCRI_PI0 PWR_PUCRI_PI0_Msk /*!< Port PI0 Pull-Up set */ |
| AnnaBridge | 172:65be27845400 | 11581 | |
| AnnaBridge | 172:65be27845400 | 11582 | /******************** Bit definition for PWR_PDCRI register ********************/ |
| AnnaBridge | 172:65be27845400 | 11583 | #define PWR_PDCRI_PI11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11584 | #define PWR_PDCRI_PI11_Msk (0x1U << PWR_PDCRI_PI11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11585 | #define PWR_PDCRI_PI11 PWR_PDCRI_PI11_Msk /*!< Port PI11 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11586 | #define PWR_PDCRI_PI10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11587 | #define PWR_PDCRI_PI10_Msk (0x1U << PWR_PDCRI_PI10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11588 | #define PWR_PDCRI_PI10 PWR_PDCRI_PI10_Msk /*!< Port PI10 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11589 | #define PWR_PDCRI_PI9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11590 | #define PWR_PDCRI_PI9_Msk (0x1U << PWR_PDCRI_PI9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11591 | #define PWR_PDCRI_PI9 PWR_PDCRI_PI9_Msk /*!< Port PI9 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11592 | #define PWR_PDCRI_PI8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11593 | #define PWR_PDCRI_PI8_Msk (0x1U << PWR_PDCRI_PI8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11594 | #define PWR_PDCRI_PI8 PWR_PDCRI_PI8_Msk /*!< Port PI8 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11595 | #define PWR_PDCRI_PI7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 11596 | #define PWR_PDCRI_PI7_Msk (0x1U << PWR_PDCRI_PI7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11597 | #define PWR_PDCRI_PI7 PWR_PDCRI_PI7_Msk /*!< Port PI7 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11598 | #define PWR_PDCRI_PI6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 11599 | #define PWR_PDCRI_PI6_Msk (0x1U << PWR_PDCRI_PI6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11600 | #define PWR_PDCRI_PI6 PWR_PDCRI_PI6_Msk /*!< Port PI6 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11601 | #define PWR_PDCRI_PI5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 11602 | #define PWR_PDCRI_PI5_Msk (0x1U << PWR_PDCRI_PI5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11603 | #define PWR_PDCRI_PI5 PWR_PDCRI_PI5_Msk /*!< Port PI5 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11604 | #define PWR_PDCRI_PI4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11605 | #define PWR_PDCRI_PI4_Msk (0x1U << PWR_PDCRI_PI4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11606 | #define PWR_PDCRI_PI4 PWR_PDCRI_PI4_Msk /*!< Port PI4 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11607 | #define PWR_PDCRI_PI3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11608 | #define PWR_PDCRI_PI3_Msk (0x1U << PWR_PDCRI_PI3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11609 | #define PWR_PDCRI_PI3 PWR_PDCRI_PI3_Msk /*!< Port PI3 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11610 | #define PWR_PDCRI_PI2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11611 | #define PWR_PDCRI_PI2_Msk (0x1U << PWR_PDCRI_PI2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11612 | #define PWR_PDCRI_PI2 PWR_PDCRI_PI2_Msk /*!< Port PI2 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11613 | #define PWR_PDCRI_PI1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11614 | #define PWR_PDCRI_PI1_Msk (0x1U << PWR_PDCRI_PI1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11615 | #define PWR_PDCRI_PI1 PWR_PDCRI_PI1_Msk /*!< Port PI1 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11616 | #define PWR_PDCRI_PI0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11617 | #define PWR_PDCRI_PI0_Msk (0x1U << PWR_PDCRI_PI0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11618 | #define PWR_PDCRI_PI0 PWR_PDCRI_PI0_Msk /*!< Port PI0 Pull-Down set */ |
| AnnaBridge | 172:65be27845400 | 11619 | |
| AnnaBridge | 172:65be27845400 | 11620 | /******************** Bit definition for PWR_CR5 register ********************/ |
| AnnaBridge | 172:65be27845400 | 11621 | #define PWR_CR5_R1MODE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11622 | #define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11623 | #define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< Range 1 normal mode */ |
| AnnaBridge | 172:65be27845400 | 11624 | |
| AnnaBridge | 172:65be27845400 | 11625 | |
| AnnaBridge | 172:65be27845400 | 11626 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 11627 | /* */ |
| AnnaBridge | 172:65be27845400 | 11628 | /* Reset and Clock Control */ |
| AnnaBridge | 172:65be27845400 | 11629 | /* */ |
| AnnaBridge | 172:65be27845400 | 11630 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 11631 | /* |
| AnnaBridge | 172:65be27845400 | 11632 | * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) |
| AnnaBridge | 172:65be27845400 | 11633 | */ |
| AnnaBridge | 172:65be27845400 | 11634 | #define RCC_HSI48_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11635 | #define RCC_PLLM_DIV_1_16_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11636 | #define RCC_PLLP_DIV_2_31_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11637 | #define RCC_PLLSAI1M_DIV_1_16_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11638 | #define RCC_PLLSAI1P_DIV_2_31_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11639 | #define RCC_PLLSAI2_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11640 | #define RCC_PLLSAI2M_DIV_1_16_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11641 | #define RCC_PLLSAI2P_DIV_2_31_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11642 | #define RCC_PLLSAI2Q_DIV_SUPPORT |
| AnnaBridge | 172:65be27845400 | 11643 | |
| AnnaBridge | 172:65be27845400 | 11644 | /******************** Bit definition for RCC_CR register ********************/ |
| AnnaBridge | 172:65be27845400 | 11645 | #define RCC_CR_MSION_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11646 | #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11647 | #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed oscillator (MSI) clock enable */ |
| AnnaBridge | 172:65be27845400 | 11648 | #define RCC_CR_MSIRDY_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11649 | #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11650 | #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed oscillator (MSI) clock ready flag */ |
| AnnaBridge | 172:65be27845400 | 11651 | #define RCC_CR_MSIPLLEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11652 | #define RCC_CR_MSIPLLEN_Msk (0x1U << RCC_CR_MSIPLLEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11653 | #define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk /*!< Internal Multi Speed oscillator (MSI) PLL enable */ |
| AnnaBridge | 172:65be27845400 | 11654 | #define RCC_CR_MSIRGSEL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 11655 | #define RCC_CR_MSIRGSEL_Msk (0x1U << RCC_CR_MSIRGSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11656 | #define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk /*!< Internal Multi Speed oscillator (MSI) range selection */ |
| AnnaBridge | 172:65be27845400 | 11657 | |
| AnnaBridge | 172:65be27845400 | 11658 | /*!< MSIRANGE configuration : 12 frequency ranges available */ |
| AnnaBridge | 172:65be27845400 | 11659 | #define RCC_CR_MSIRANGE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11660 | #define RCC_CR_MSIRANGE_Msk (0xFU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 11661 | #define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk /*!< Internal Multi Speed oscillator (MSI) clock Range */ |
| AnnaBridge | 172:65be27845400 | 11662 | #define RCC_CR_MSIRANGE_0 (0x0U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000000 */ |
| AnnaBridge | 172:65be27845400 | 11663 | #define RCC_CR_MSIRANGE_1 (0x1U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11664 | #define RCC_CR_MSIRANGE_2 (0x2U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11665 | #define RCC_CR_MSIRANGE_3 (0x3U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 11666 | #define RCC_CR_MSIRANGE_4 (0x4U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11667 | #define RCC_CR_MSIRANGE_5 (0x5U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000050 */ |
| AnnaBridge | 172:65be27845400 | 11668 | #define RCC_CR_MSIRANGE_6 (0x6U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 172:65be27845400 | 11669 | #define RCC_CR_MSIRANGE_7 (0x7U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 11670 | #define RCC_CR_MSIRANGE_8 (0x8U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11671 | #define RCC_CR_MSIRANGE_9 (0x9U << RCC_CR_MSIRANGE_Pos) /*!< 0x00000090 */ |
| AnnaBridge | 172:65be27845400 | 11672 | #define RCC_CR_MSIRANGE_10 (0xAU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000A0 */ |
| AnnaBridge | 172:65be27845400 | 11673 | #define RCC_CR_MSIRANGE_11 (0xBU << RCC_CR_MSIRANGE_Pos) /*!< 0x000000B0 */ |
| AnnaBridge | 172:65be27845400 | 11674 | |
| AnnaBridge | 172:65be27845400 | 11675 | #define RCC_CR_HSION_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11676 | #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11677 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ |
| AnnaBridge | 172:65be27845400 | 11678 | #define RCC_CR_HSIKERON_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 11679 | #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11680 | #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ |
| AnnaBridge | 172:65be27845400 | 11681 | #define RCC_CR_HSIRDY_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 11682 | #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11683 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ |
| AnnaBridge | 172:65be27845400 | 11684 | #define RCC_CR_HSIASFS_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11685 | #define RCC_CR_HSIASFS_Msk (0x1U << RCC_CR_HSIASFS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11686 | #define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk /*!< HSI16 Automatic Start from Stop */ |
| AnnaBridge | 172:65be27845400 | 11687 | |
| AnnaBridge | 172:65be27845400 | 11688 | #define RCC_CR_HSEON_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 11689 | #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 11690 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ |
| AnnaBridge | 172:65be27845400 | 11691 | #define RCC_CR_HSERDY_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 11692 | #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 11693 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ |
| AnnaBridge | 172:65be27845400 | 11694 | #define RCC_CR_HSEBYP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 11695 | #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 11696 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */ |
| AnnaBridge | 172:65be27845400 | 11697 | #define RCC_CR_CSSON_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 11698 | #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 11699 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */ |
| AnnaBridge | 172:65be27845400 | 11700 | |
| AnnaBridge | 172:65be27845400 | 11701 | #define RCC_CR_PLLON_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 11702 | #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 11703 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */ |
| AnnaBridge | 172:65be27845400 | 11704 | #define RCC_CR_PLLRDY_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 11705 | #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 11706 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ |
| AnnaBridge | 172:65be27845400 | 11707 | #define RCC_CR_PLLSAI1ON_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 11708 | #define RCC_CR_PLLSAI1ON_Msk (0x1U << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 11709 | #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */ |
| AnnaBridge | 172:65be27845400 | 11710 | #define RCC_CR_PLLSAI1RDY_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 11711 | #define RCC_CR_PLLSAI1RDY_Msk (0x1U << RCC_CR_PLLSAI1RDY_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 11712 | #define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk /*!< SAI1 PLL ready */ |
| AnnaBridge | 172:65be27845400 | 11713 | #define RCC_CR_PLLSAI2ON_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 11714 | #define RCC_CR_PLLSAI2ON_Msk (0x1U << RCC_CR_PLLSAI2ON_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 11715 | #define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk /*!< SAI2 PLL enable */ |
| AnnaBridge | 172:65be27845400 | 11716 | #define RCC_CR_PLLSAI2RDY_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 11717 | #define RCC_CR_PLLSAI2RDY_Msk (0x1U << RCC_CR_PLLSAI2RDY_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 11718 | #define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk /*!< SAI2 PLL ready */ |
| AnnaBridge | 172:65be27845400 | 11719 | |
| AnnaBridge | 172:65be27845400 | 11720 | /******************** Bit definition for RCC_ICSCR register ***************/ |
| AnnaBridge | 172:65be27845400 | 11721 | /*!< MSICAL configuration */ |
| AnnaBridge | 172:65be27845400 | 11722 | #define RCC_ICSCR_MSICAL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11723 | #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 11724 | #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< MSICAL[7:0] bits */ |
| AnnaBridge | 172:65be27845400 | 11725 | #define RCC_ICSCR_MSICAL_0 (0x01U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11726 | #define RCC_ICSCR_MSICAL_1 (0x02U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11727 | #define RCC_ICSCR_MSICAL_2 (0x04U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11728 | #define RCC_ICSCR_MSICAL_3 (0x08U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11729 | #define RCC_ICSCR_MSICAL_4 (0x10U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11730 | #define RCC_ICSCR_MSICAL_5 (0x20U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11731 | #define RCC_ICSCR_MSICAL_6 (0x40U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11732 | #define RCC_ICSCR_MSICAL_7 (0x80U << RCC_ICSCR_MSICAL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11733 | |
| AnnaBridge | 172:65be27845400 | 11734 | /*!< MSITRIM configuration */ |
| AnnaBridge | 172:65be27845400 | 11735 | #define RCC_ICSCR_MSITRIM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11736 | #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 11737 | #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< MSITRIM[7:0] bits */ |
| AnnaBridge | 172:65be27845400 | 11738 | #define RCC_ICSCR_MSITRIM_0 (0x01U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11739 | #define RCC_ICSCR_MSITRIM_1 (0x02U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11740 | #define RCC_ICSCR_MSITRIM_2 (0x04U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11741 | #define RCC_ICSCR_MSITRIM_3 (0x08U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11742 | #define RCC_ICSCR_MSITRIM_4 (0x10U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11743 | #define RCC_ICSCR_MSITRIM_5 (0x20U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11744 | #define RCC_ICSCR_MSITRIM_6 (0x40U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11745 | #define RCC_ICSCR_MSITRIM_7 (0x80U << RCC_ICSCR_MSITRIM_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11746 | |
| AnnaBridge | 172:65be27845400 | 11747 | /*!< HSICAL configuration */ |
| AnnaBridge | 172:65be27845400 | 11748 | #define RCC_ICSCR_HSICAL_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 11749 | #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 11750 | #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */ |
| AnnaBridge | 172:65be27845400 | 11751 | #define RCC_ICSCR_HSICAL_0 (0x01U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 11752 | #define RCC_ICSCR_HSICAL_1 (0x02U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 11753 | #define RCC_ICSCR_HSICAL_2 (0x04U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 11754 | #define RCC_ICSCR_HSICAL_3 (0x08U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 11755 | #define RCC_ICSCR_HSICAL_4 (0x10U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 11756 | #define RCC_ICSCR_HSICAL_5 (0x20U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 11757 | #define RCC_ICSCR_HSICAL_6 (0x40U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 11758 | #define RCC_ICSCR_HSICAL_7 (0x80U << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 11759 | |
| AnnaBridge | 172:65be27845400 | 11760 | /*!< HSITRIM configuration */ |
| AnnaBridge | 172:65be27845400 | 11761 | #define RCC_ICSCR_HSITRIM_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 11762 | #define RCC_ICSCR_HSITRIM_Msk (0x7FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */ |
| AnnaBridge | 172:65be27845400 | 11763 | #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */ |
| AnnaBridge | 172:65be27845400 | 11764 | #define RCC_ICSCR_HSITRIM_0 (0x01U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 11765 | #define RCC_ICSCR_HSITRIM_1 (0x02U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 11766 | #define RCC_ICSCR_HSITRIM_2 (0x04U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 11767 | #define RCC_ICSCR_HSITRIM_3 (0x08U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 11768 | #define RCC_ICSCR_HSITRIM_4 (0x10U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 11769 | #define RCC_ICSCR_HSITRIM_5 (0x20U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 11770 | #define RCC_ICSCR_HSITRIM_6 (0x40U << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 11771 | |
| AnnaBridge | 172:65be27845400 | 11772 | /******************** Bit definition for RCC_CFGR register ******************/ |
| AnnaBridge | 172:65be27845400 | 11773 | /*!< SW configuration */ |
| AnnaBridge | 172:65be27845400 | 11774 | #define RCC_CFGR_SW_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11775 | #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 11776 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
| AnnaBridge | 172:65be27845400 | 11777 | #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11778 | #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11779 | |
| AnnaBridge | 172:65be27845400 | 11780 | #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI oscillator selection as system clock */ |
| AnnaBridge | 172:65be27845400 | 11781 | #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */ |
| AnnaBridge | 172:65be27845400 | 11782 | #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */ |
| AnnaBridge | 172:65be27845400 | 11783 | #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */ |
| AnnaBridge | 172:65be27845400 | 11784 | |
| AnnaBridge | 172:65be27845400 | 11785 | /*!< SWS configuration */ |
| AnnaBridge | 172:65be27845400 | 11786 | #define RCC_CFGR_SWS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 11787 | #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 11788 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| AnnaBridge | 172:65be27845400 | 11789 | #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 11790 | #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 11791 | |
| AnnaBridge | 172:65be27845400 | 11792 | #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ |
| AnnaBridge | 172:65be27845400 | 11793 | #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */ |
| AnnaBridge | 172:65be27845400 | 11794 | #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ |
| AnnaBridge | 172:65be27845400 | 11795 | #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ |
| AnnaBridge | 172:65be27845400 | 11796 | |
| AnnaBridge | 172:65be27845400 | 11797 | /*!< HPRE configuration */ |
| AnnaBridge | 172:65be27845400 | 11798 | #define RCC_CFGR_HPRE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11799 | #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 11800 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
| AnnaBridge | 172:65be27845400 | 11801 | #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11802 | #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11803 | #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11804 | #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11805 | |
| AnnaBridge | 172:65be27845400 | 11806 | #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ |
| AnnaBridge | 172:65be27845400 | 11807 | #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ |
| AnnaBridge | 172:65be27845400 | 11808 | #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ |
| AnnaBridge | 172:65be27845400 | 11809 | #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ |
| AnnaBridge | 172:65be27845400 | 11810 | #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ |
| AnnaBridge | 172:65be27845400 | 11811 | #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ |
| AnnaBridge | 172:65be27845400 | 11812 | #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ |
| AnnaBridge | 172:65be27845400 | 11813 | #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ |
| AnnaBridge | 172:65be27845400 | 11814 | #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ |
| AnnaBridge | 172:65be27845400 | 11815 | |
| AnnaBridge | 172:65be27845400 | 11816 | /*!< PPRE1 configuration */ |
| AnnaBridge | 172:65be27845400 | 11817 | #define RCC_CFGR_PPRE1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11818 | #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 11819 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */ |
| AnnaBridge | 172:65be27845400 | 11820 | #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11821 | #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11822 | #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11823 | |
| AnnaBridge | 172:65be27845400 | 11824 | #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ |
| AnnaBridge | 172:65be27845400 | 11825 | #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ |
| AnnaBridge | 172:65be27845400 | 11826 | #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ |
| AnnaBridge | 172:65be27845400 | 11827 | #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ |
| AnnaBridge | 172:65be27845400 | 11828 | #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ |
| AnnaBridge | 172:65be27845400 | 11829 | |
| AnnaBridge | 172:65be27845400 | 11830 | /*!< PPRE2 configuration */ |
| AnnaBridge | 172:65be27845400 | 11831 | #define RCC_CFGR_PPRE2_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 11832 | #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
| AnnaBridge | 172:65be27845400 | 11833 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| AnnaBridge | 172:65be27845400 | 11834 | #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11835 | #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11836 | #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11837 | |
| AnnaBridge | 172:65be27845400 | 11838 | #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ |
| AnnaBridge | 172:65be27845400 | 11839 | #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ |
| AnnaBridge | 172:65be27845400 | 11840 | #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ |
| AnnaBridge | 172:65be27845400 | 11841 | #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ |
| AnnaBridge | 172:65be27845400 | 11842 | #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ |
| AnnaBridge | 172:65be27845400 | 11843 | |
| AnnaBridge | 172:65be27845400 | 11844 | #define RCC_CFGR_STOPWUCK_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 11845 | #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 11846 | #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */ |
| AnnaBridge | 172:65be27845400 | 11847 | |
| AnnaBridge | 172:65be27845400 | 11848 | /*!< MCOSEL configuration */ |
| AnnaBridge | 172:65be27845400 | 11849 | #define RCC_CFGR_MCOSEL_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 11850 | #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 11851 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ |
| AnnaBridge | 172:65be27845400 | 11852 | #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 11853 | #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 11854 | #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 11855 | #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 11856 | |
| AnnaBridge | 172:65be27845400 | 11857 | #define RCC_CFGR_MCOPRE_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 11858 | #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ |
| AnnaBridge | 172:65be27845400 | 11859 | #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ |
| AnnaBridge | 172:65be27845400 | 11860 | #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 11861 | #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 11862 | #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 11863 | |
| AnnaBridge | 172:65be27845400 | 11864 | #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ |
| AnnaBridge | 172:65be27845400 | 11865 | #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ |
| AnnaBridge | 172:65be27845400 | 11866 | #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ |
| AnnaBridge | 172:65be27845400 | 11867 | #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ |
| AnnaBridge | 172:65be27845400 | 11868 | #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ |
| AnnaBridge | 172:65be27845400 | 11869 | |
| AnnaBridge | 172:65be27845400 | 11870 | /* Legacy aliases */ |
| AnnaBridge | 172:65be27845400 | 11871 | #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE |
| AnnaBridge | 172:65be27845400 | 11872 | #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 |
| AnnaBridge | 172:65be27845400 | 11873 | #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 |
| AnnaBridge | 172:65be27845400 | 11874 | #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 |
| AnnaBridge | 172:65be27845400 | 11875 | #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 |
| AnnaBridge | 172:65be27845400 | 11876 | #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 |
| AnnaBridge | 172:65be27845400 | 11877 | |
| AnnaBridge | 172:65be27845400 | 11878 | /******************** Bit definition for RCC_PLLCFGR register ***************/ |
| AnnaBridge | 172:65be27845400 | 11879 | #define RCC_PLLCFGR_PLLSRC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11880 | #define RCC_PLLCFGR_PLLSRC_Msk (0x3U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 11881 | #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk |
| AnnaBridge | 172:65be27845400 | 11882 | |
| AnnaBridge | 172:65be27845400 | 11883 | #define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11884 | #define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 11885 | #define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk /*!< MSI oscillator source clock selected */ |
| AnnaBridge | 172:65be27845400 | 11886 | #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 11887 | #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 11888 | #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */ |
| AnnaBridge | 172:65be27845400 | 11889 | #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 11890 | #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 11891 | #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */ |
| AnnaBridge | 172:65be27845400 | 11892 | |
| AnnaBridge | 172:65be27845400 | 11893 | #define RCC_PLLCFGR_PLLM_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11894 | #define RCC_PLLCFGR_PLLM_Msk (0xFU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 11895 | #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk |
| AnnaBridge | 172:65be27845400 | 11896 | #define RCC_PLLCFGR_PLLM_0 (0x1U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11897 | #define RCC_PLLCFGR_PLLM_1 (0x2U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11898 | #define RCC_PLLCFGR_PLLM_2 (0x4U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11899 | #define RCC_PLLCFGR_PLLM_3 (0x8U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11900 | |
| AnnaBridge | 172:65be27845400 | 11901 | #define RCC_PLLCFGR_PLLN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11902 | #define RCC_PLLCFGR_PLLN_Msk (0x7FU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */ |
| AnnaBridge | 172:65be27845400 | 11903 | #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk |
| AnnaBridge | 172:65be27845400 | 11904 | #define RCC_PLLCFGR_PLLN_0 (0x01U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11905 | #define RCC_PLLCFGR_PLLN_1 (0x02U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11906 | #define RCC_PLLCFGR_PLLN_2 (0x04U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11907 | #define RCC_PLLCFGR_PLLN_3 (0x08U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11908 | #define RCC_PLLCFGR_PLLN_4 (0x10U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11909 | #define RCC_PLLCFGR_PLLN_5 (0x20U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11910 | #define RCC_PLLCFGR_PLLN_6 (0x40U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11911 | |
| AnnaBridge | 172:65be27845400 | 11912 | #define RCC_PLLCFGR_PLLPEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 11913 | #define RCC_PLLCFGR_PLLPEN_Msk (0x1U << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 11914 | #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk |
| AnnaBridge | 172:65be27845400 | 11915 | #define RCC_PLLCFGR_PLLP_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 11916 | #define RCC_PLLCFGR_PLLP_Msk (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 11917 | #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk |
| AnnaBridge | 172:65be27845400 | 11918 | #define RCC_PLLCFGR_PLLQEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 11919 | #define RCC_PLLCFGR_PLLQEN_Msk (0x1U << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 11920 | #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk |
| AnnaBridge | 172:65be27845400 | 11921 | |
| AnnaBridge | 172:65be27845400 | 11922 | #define RCC_PLLCFGR_PLLQ_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 11923 | #define RCC_PLLCFGR_PLLQ_Msk (0x3U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 172:65be27845400 | 11924 | #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk |
| AnnaBridge | 172:65be27845400 | 11925 | #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 11926 | #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 11927 | |
| AnnaBridge | 172:65be27845400 | 11928 | #define RCC_PLLCFGR_PLLREN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 11929 | #define RCC_PLLCFGR_PLLREN_Msk (0x1U << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 11930 | #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk |
| AnnaBridge | 172:65be27845400 | 11931 | #define RCC_PLLCFGR_PLLR_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 11932 | #define RCC_PLLCFGR_PLLR_Msk (0x3U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */ |
| AnnaBridge | 172:65be27845400 | 11933 | #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk |
| AnnaBridge | 172:65be27845400 | 11934 | #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 11935 | #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 11936 | |
| AnnaBridge | 172:65be27845400 | 11937 | #define RCC_PLLCFGR_PLLPDIV_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 11938 | #define RCC_PLLCFGR_PLLPDIV_Msk (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */ |
| AnnaBridge | 172:65be27845400 | 11939 | #define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk |
| AnnaBridge | 172:65be27845400 | 11940 | #define RCC_PLLCFGR_PLLPDIV_0 (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 11941 | #define RCC_PLLCFGR_PLLPDIV_1 (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 11942 | #define RCC_PLLCFGR_PLLPDIV_2 (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 11943 | #define RCC_PLLCFGR_PLLPDIV_3 (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 11944 | #define RCC_PLLCFGR_PLLPDIV_4 (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 11945 | |
| AnnaBridge | 172:65be27845400 | 11946 | /******************** Bit definition for RCC_PLLSAI1CFGR register ************/ |
| AnnaBridge | 172:65be27845400 | 11947 | #define RCC_PLLSAI1CFGR_PLLSAI1M_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 11948 | #define RCC_PLLSAI1CFGR_PLLSAI1M_Msk (0xFU << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 11949 | #define RCC_PLLSAI1CFGR_PLLSAI1M RCC_PLLSAI1CFGR_PLLSAI1M_Msk |
| AnnaBridge | 172:65be27845400 | 11950 | #define RCC_PLLSAI1CFGR_PLLSAI1M_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 11951 | #define RCC_PLLSAI1CFGR_PLLSAI1M_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 11952 | #define RCC_PLLSAI1CFGR_PLLSAI1M_2 (0x4U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 11953 | #define RCC_PLLSAI1CFGR_PLLSAI1M_3 (0x8U << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 11954 | |
| AnnaBridge | 172:65be27845400 | 11955 | #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 11956 | #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */ |
| AnnaBridge | 172:65be27845400 | 11957 | #define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk |
| AnnaBridge | 172:65be27845400 | 11958 | #define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 11959 | #define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 11960 | #define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 11961 | #define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 11962 | #define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 11963 | #define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 11964 | #define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 11965 | |
| AnnaBridge | 172:65be27845400 | 11966 | #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 11967 | #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 11968 | #define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk |
| AnnaBridge | 172:65be27845400 | 11969 | #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 11970 | #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 11971 | #define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk |
| AnnaBridge | 172:65be27845400 | 11972 | |
| AnnaBridge | 172:65be27845400 | 11973 | #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 11974 | #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 11975 | #define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk |
| AnnaBridge | 172:65be27845400 | 11976 | #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 11977 | #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 172:65be27845400 | 11978 | #define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk |
| AnnaBridge | 172:65be27845400 | 11979 | #define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 11980 | #define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 11981 | |
| AnnaBridge | 172:65be27845400 | 11982 | #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 11983 | #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 11984 | #define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk |
| AnnaBridge | 172:65be27845400 | 11985 | #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 11986 | #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */ |
| AnnaBridge | 172:65be27845400 | 11987 | #define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk |
| AnnaBridge | 172:65be27845400 | 11988 | #define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 11989 | #define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 11990 | |
| AnnaBridge | 172:65be27845400 | 11991 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 11992 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */ |
| AnnaBridge | 172:65be27845400 | 11993 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk |
| AnnaBridge | 172:65be27845400 | 11994 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0 (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 11995 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1 (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 11996 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2 (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 11997 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3 (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 11998 | #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4 (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 11999 | |
| AnnaBridge | 172:65be27845400 | 12000 | /******************** Bit definition for RCC_PLLSAI2CFGR register ************/ |
| AnnaBridge | 172:65be27845400 | 12001 | #define RCC_PLLSAI2CFGR_PLLSAI2M_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12002 | #define RCC_PLLSAI2CFGR_PLLSAI2M_Msk (0xFU << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 12003 | #define RCC_PLLSAI2CFGR_PLLSAI2M RCC_PLLSAI2CFGR_PLLSAI2M_Msk |
| AnnaBridge | 172:65be27845400 | 12004 | #define RCC_PLLSAI2CFGR_PLLSAI2M_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12005 | #define RCC_PLLSAI2CFGR_PLLSAI2M_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12006 | #define RCC_PLLSAI2CFGR_PLLSAI2M_2 (0x4U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12007 | #define RCC_PLLSAI2CFGR_PLLSAI2M_3 (0x8U << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12008 | |
| AnnaBridge | 172:65be27845400 | 12009 | #define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12010 | #define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */ |
| AnnaBridge | 172:65be27845400 | 12011 | #define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk |
| AnnaBridge | 172:65be27845400 | 12012 | #define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12013 | #define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12014 | #define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12015 | #define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12016 | #define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12017 | #define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12018 | #define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12019 | |
| AnnaBridge | 172:65be27845400 | 12020 | #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12021 | #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12022 | #define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk |
| AnnaBridge | 172:65be27845400 | 12023 | #define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12024 | #define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12025 | #define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk |
| AnnaBridge | 172:65be27845400 | 12026 | |
| AnnaBridge | 172:65be27845400 | 12027 | #define RCC_PLLSAI2CFGR_PLLSAI2QEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12028 | #define RCC_PLLSAI2CFGR_PLLSAI2QEN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2QEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12029 | #define RCC_PLLSAI2CFGR_PLLSAI2QEN RCC_PLLSAI2CFGR_PLLSAI2QEN_Msk |
| AnnaBridge | 172:65be27845400 | 12030 | #define RCC_PLLSAI2CFGR_PLLSAI2Q_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12031 | #define RCC_PLLSAI2CFGR_PLLSAI2Q_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 172:65be27845400 | 12032 | #define RCC_PLLSAI2CFGR_PLLSAI2Q RCC_PLLSAI2CFGR_PLLSAI2Q_Msk |
| AnnaBridge | 172:65be27845400 | 12033 | #define RCC_PLLSAI2CFGR_PLLSAI2Q_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12034 | #define RCC_PLLSAI2CFGR_PLLSAI2Q_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12035 | |
| AnnaBridge | 172:65be27845400 | 12036 | #define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12037 | #define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12038 | #define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk |
| AnnaBridge | 172:65be27845400 | 12039 | #define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 12040 | #define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */ |
| AnnaBridge | 172:65be27845400 | 12041 | #define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk |
| AnnaBridge | 172:65be27845400 | 12042 | #define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 12043 | #define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 12044 | |
| AnnaBridge | 172:65be27845400 | 12045 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 12046 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk (0x1FU << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0xF8000000 */ |
| AnnaBridge | 172:65be27845400 | 12047 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk |
| AnnaBridge | 172:65be27845400 | 12048 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0 (0x01U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 12049 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1 (0x02U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 12050 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2 (0x04U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 12051 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3 (0x08U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 12052 | #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4 (0x10U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 12053 | |
| AnnaBridge | 172:65be27845400 | 12054 | /******************** Bit definition for RCC_CIER register ******************/ |
| AnnaBridge | 172:65be27845400 | 12055 | #define RCC_CIER_LSIRDYIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12056 | #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12057 | #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12058 | #define RCC_CIER_LSERDYIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12059 | #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12060 | #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12061 | #define RCC_CIER_MSIRDYIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12062 | #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12063 | #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12064 | #define RCC_CIER_HSIRDYIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12065 | #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12066 | #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12067 | #define RCC_CIER_HSERDYIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12068 | #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12069 | #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12070 | #define RCC_CIER_PLLRDYIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12071 | #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12072 | #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12073 | #define RCC_CIER_PLLSAI1RDYIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12074 | #define RCC_CIER_PLLSAI1RDYIE_Msk (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12075 | #define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12076 | #define RCC_CIER_PLLSAI2RDYIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12077 | #define RCC_CIER_PLLSAI2RDYIE_Msk (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12078 | #define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12079 | #define RCC_CIER_LSECSSIE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12080 | #define RCC_CIER_LSECSSIE_Msk (0x1U << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12081 | #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk |
| AnnaBridge | 172:65be27845400 | 12082 | #define RCC_CIER_HSI48RDYIE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12083 | #define RCC_CIER_HSI48RDYIE_Msk (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12084 | #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk |
| AnnaBridge | 172:65be27845400 | 12085 | |
| AnnaBridge | 172:65be27845400 | 12086 | /******************** Bit definition for RCC_CIFR register ******************/ |
| AnnaBridge | 172:65be27845400 | 12087 | #define RCC_CIFR_LSIRDYF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12088 | #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12089 | #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12090 | #define RCC_CIFR_LSERDYF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12091 | #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12092 | #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12093 | #define RCC_CIFR_MSIRDYF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12094 | #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12095 | #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12096 | #define RCC_CIFR_HSIRDYF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12097 | #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12098 | #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12099 | #define RCC_CIFR_HSERDYF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12100 | #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12101 | #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12102 | #define RCC_CIFR_PLLRDYF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12103 | #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12104 | #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12105 | #define RCC_CIFR_PLLSAI1RDYF_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12106 | #define RCC_CIFR_PLLSAI1RDYF_Msk (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12107 | #define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12108 | #define RCC_CIFR_PLLSAI2RDYF_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12109 | #define RCC_CIFR_PLLSAI2RDYF_Msk (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12110 | #define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12111 | #define RCC_CIFR_CSSF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12112 | #define RCC_CIFR_CSSF_Msk (0x1U << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12113 | #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk |
| AnnaBridge | 172:65be27845400 | 12114 | #define RCC_CIFR_LSECSSF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12115 | #define RCC_CIFR_LSECSSF_Msk (0x1U << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12116 | #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk |
| AnnaBridge | 172:65be27845400 | 12117 | #define RCC_CIFR_HSI48RDYF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12118 | #define RCC_CIFR_HSI48RDYF_Msk (0x1U << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12119 | #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk |
| AnnaBridge | 172:65be27845400 | 12120 | |
| AnnaBridge | 172:65be27845400 | 12121 | /******************** Bit definition for RCC_CICR register ******************/ |
| AnnaBridge | 172:65be27845400 | 12122 | #define RCC_CICR_LSIRDYC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12123 | #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12124 | #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12125 | #define RCC_CICR_LSERDYC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12126 | #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12127 | #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12128 | #define RCC_CICR_MSIRDYC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12129 | #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12130 | #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12131 | #define RCC_CICR_HSIRDYC_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12132 | #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12133 | #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12134 | #define RCC_CICR_HSERDYC_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12135 | #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12136 | #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12137 | #define RCC_CICR_PLLRDYC_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12138 | #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12139 | #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12140 | #define RCC_CICR_PLLSAI1RDYC_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12141 | #define RCC_CICR_PLLSAI1RDYC_Msk (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12142 | #define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12143 | #define RCC_CICR_PLLSAI2RDYC_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12144 | #define RCC_CICR_PLLSAI2RDYC_Msk (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12145 | #define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12146 | #define RCC_CICR_CSSC_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12147 | #define RCC_CICR_CSSC_Msk (0x1U << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12148 | #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk |
| AnnaBridge | 172:65be27845400 | 12149 | #define RCC_CICR_LSECSSC_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12150 | #define RCC_CICR_LSECSSC_Msk (0x1U << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12151 | #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk |
| AnnaBridge | 172:65be27845400 | 12152 | #define RCC_CICR_HSI48RDYC_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12153 | #define RCC_CICR_HSI48RDYC_Msk (0x1U << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12154 | #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk |
| AnnaBridge | 172:65be27845400 | 12155 | |
| AnnaBridge | 172:65be27845400 | 12156 | /******************** Bit definition for RCC_AHB1RSTR register **************/ |
| AnnaBridge | 172:65be27845400 | 12157 | #define RCC_AHB1RSTR_DMA1RST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12158 | #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12159 | #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12160 | #define RCC_AHB1RSTR_DMA2RST_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12161 | #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12162 | #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12163 | #define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12164 | #define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1U << RCC_AHB1RSTR_DMAMUX1RST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12165 | #define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12166 | #define RCC_AHB1RSTR_FLASHRST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12167 | #define RCC_AHB1RSTR_FLASHRST_Msk (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12168 | #define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk |
| AnnaBridge | 172:65be27845400 | 12169 | #define RCC_AHB1RSTR_CRCRST_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12170 | #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12171 | #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk |
| AnnaBridge | 172:65be27845400 | 12172 | #define RCC_AHB1RSTR_TSCRST_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12173 | #define RCC_AHB1RSTR_TSCRST_Msk (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12174 | #define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk |
| AnnaBridge | 172:65be27845400 | 12175 | #define RCC_AHB1RSTR_DMA2DRST_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12176 | #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12177 | #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk |
| AnnaBridge | 172:65be27845400 | 12178 | |
| AnnaBridge | 172:65be27845400 | 12179 | /******************** Bit definition for RCC_AHB2RSTR register **************/ |
| AnnaBridge | 172:65be27845400 | 12180 | #define RCC_AHB2RSTR_GPIOARST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12181 | #define RCC_AHB2RSTR_GPIOARST_Msk (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12182 | #define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk |
| AnnaBridge | 172:65be27845400 | 12183 | #define RCC_AHB2RSTR_GPIOBRST_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12184 | #define RCC_AHB2RSTR_GPIOBRST_Msk (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12185 | #define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk |
| AnnaBridge | 172:65be27845400 | 12186 | #define RCC_AHB2RSTR_GPIOCRST_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12187 | #define RCC_AHB2RSTR_GPIOCRST_Msk (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12188 | #define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk |
| AnnaBridge | 172:65be27845400 | 12189 | #define RCC_AHB2RSTR_GPIODRST_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12190 | #define RCC_AHB2RSTR_GPIODRST_Msk (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12191 | #define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk |
| AnnaBridge | 172:65be27845400 | 12192 | #define RCC_AHB2RSTR_GPIOERST_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12193 | #define RCC_AHB2RSTR_GPIOERST_Msk (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12194 | #define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk |
| AnnaBridge | 172:65be27845400 | 12195 | #define RCC_AHB2RSTR_GPIOFRST_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12196 | #define RCC_AHB2RSTR_GPIOFRST_Msk (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12197 | #define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk |
| AnnaBridge | 172:65be27845400 | 12198 | #define RCC_AHB2RSTR_GPIOGRST_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12199 | #define RCC_AHB2RSTR_GPIOGRST_Msk (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12200 | #define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk |
| AnnaBridge | 172:65be27845400 | 12201 | #define RCC_AHB2RSTR_GPIOHRST_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12202 | #define RCC_AHB2RSTR_GPIOHRST_Msk (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12203 | #define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk |
| AnnaBridge | 172:65be27845400 | 12204 | #define RCC_AHB2RSTR_GPIOIRST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12205 | #define RCC_AHB2RSTR_GPIOIRST_Msk (0x1U << RCC_AHB2RSTR_GPIOIRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12206 | #define RCC_AHB2RSTR_GPIOIRST RCC_AHB2RSTR_GPIOIRST_Msk |
| AnnaBridge | 172:65be27845400 | 12207 | #define RCC_AHB2RSTR_OTGFSRST_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12208 | #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12209 | #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk |
| AnnaBridge | 172:65be27845400 | 12210 | #define RCC_AHB2RSTR_ADCRST_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 12211 | #define RCC_AHB2RSTR_ADCRST_Msk (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12212 | #define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk |
| AnnaBridge | 172:65be27845400 | 12213 | #define RCC_AHB2RSTR_DCMIRST_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12214 | #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12215 | #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk |
| AnnaBridge | 172:65be27845400 | 12216 | #define RCC_AHB2RSTR_RNGRST_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12217 | #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12218 | #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk |
| AnnaBridge | 172:65be27845400 | 12219 | #define RCC_AHB2RSTR_OSPIMRST_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12220 | #define RCC_AHB2RSTR_OSPIMRST_Msk (0x1U << RCC_AHB2RSTR_OSPIMRST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12221 | #define RCC_AHB2RSTR_OSPIMRST RCC_AHB2RSTR_OSPIMRST_Msk |
| AnnaBridge | 172:65be27845400 | 12222 | #define RCC_AHB2RSTR_SDMMC1RST_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12223 | #define RCC_AHB2RSTR_SDMMC1RST_Msk (0x1U << RCC_AHB2RSTR_SDMMC1RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12224 | #define RCC_AHB2RSTR_SDMMC1RST RCC_AHB2RSTR_SDMMC1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12225 | |
| AnnaBridge | 172:65be27845400 | 12226 | /******************** Bit definition for RCC_AHB3RSTR register **************/ |
| AnnaBridge | 172:65be27845400 | 12227 | #define RCC_AHB3RSTR_FMCRST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12228 | #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12229 | #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk |
| AnnaBridge | 172:65be27845400 | 12230 | #define RCC_AHB3RSTR_OSPI1RST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12231 | #define RCC_AHB3RSTR_OSPI1RST_Msk (0x1U << RCC_AHB3RSTR_OSPI1RST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12232 | #define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12233 | #define RCC_AHB3RSTR_OSPI2RST_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12234 | #define RCC_AHB3RSTR_OSPI2RST_Msk (0x1U << RCC_AHB3RSTR_OSPI2RST_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12235 | #define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12236 | |
| AnnaBridge | 172:65be27845400 | 12237 | /******************** Bit definition for RCC_APB1RSTR1 register **************/ |
| AnnaBridge | 172:65be27845400 | 12238 | #define RCC_APB1RSTR1_TIM2RST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12239 | #define RCC_APB1RSTR1_TIM2RST_Msk (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12240 | #define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12241 | #define RCC_APB1RSTR1_TIM3RST_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12242 | #define RCC_APB1RSTR1_TIM3RST_Msk (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12243 | #define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk |
| AnnaBridge | 172:65be27845400 | 12244 | #define RCC_APB1RSTR1_TIM4RST_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12245 | #define RCC_APB1RSTR1_TIM4RST_Msk (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12246 | #define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk |
| AnnaBridge | 172:65be27845400 | 12247 | #define RCC_APB1RSTR1_TIM5RST_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12248 | #define RCC_APB1RSTR1_TIM5RST_Msk (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12249 | #define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk |
| AnnaBridge | 172:65be27845400 | 12250 | #define RCC_APB1RSTR1_TIM6RST_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12251 | #define RCC_APB1RSTR1_TIM6RST_Msk (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12252 | #define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk |
| AnnaBridge | 172:65be27845400 | 12253 | #define RCC_APB1RSTR1_TIM7RST_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12254 | #define RCC_APB1RSTR1_TIM7RST_Msk (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12255 | #define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk |
| AnnaBridge | 172:65be27845400 | 12256 | #define RCC_APB1RSTR1_SPI2RST_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12257 | #define RCC_APB1RSTR1_SPI2RST_Msk (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12258 | #define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12259 | #define RCC_APB1RSTR1_SPI3RST_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 12260 | #define RCC_APB1RSTR1_SPI3RST_Msk (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 12261 | #define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk |
| AnnaBridge | 172:65be27845400 | 12262 | #define RCC_APB1RSTR1_USART2RST_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12263 | #define RCC_APB1RSTR1_USART2RST_Msk (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12264 | #define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12265 | #define RCC_APB1RSTR1_USART3RST_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12266 | #define RCC_APB1RSTR1_USART3RST_Msk (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12267 | #define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk |
| AnnaBridge | 172:65be27845400 | 12268 | #define RCC_APB1RSTR1_UART4RST_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 12269 | #define RCC_APB1RSTR1_UART4RST_Msk (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 12270 | #define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk |
| AnnaBridge | 172:65be27845400 | 12271 | #define RCC_APB1RSTR1_UART5RST_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12272 | #define RCC_APB1RSTR1_UART5RST_Msk (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12273 | #define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk |
| AnnaBridge | 172:65be27845400 | 12274 | #define RCC_APB1RSTR1_I2C1RST_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12275 | #define RCC_APB1RSTR1_I2C1RST_Msk (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12276 | #define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12277 | #define RCC_APB1RSTR1_I2C2RST_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12278 | #define RCC_APB1RSTR1_I2C2RST_Msk (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12279 | #define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12280 | #define RCC_APB1RSTR1_I2C3RST_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 12281 | #define RCC_APB1RSTR1_I2C3RST_Msk (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 12282 | #define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk |
| AnnaBridge | 172:65be27845400 | 12283 | #define RCC_APB1RSTR1_CRSRST_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12284 | #define RCC_APB1RSTR1_CRSRST_Msk (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12285 | #define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk |
| AnnaBridge | 172:65be27845400 | 12286 | #define RCC_APB1RSTR1_CAN1RST_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 12287 | #define RCC_APB1RSTR1_CAN1RST_Msk (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 12288 | #define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12289 | #define RCC_APB1RSTR1_PWRRST_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 12290 | #define RCC_APB1RSTR1_PWRRST_Msk (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 12291 | #define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk |
| AnnaBridge | 172:65be27845400 | 12292 | #define RCC_APB1RSTR1_DAC1RST_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 12293 | #define RCC_APB1RSTR1_DAC1RST_Msk (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 12294 | #define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12295 | #define RCC_APB1RSTR1_OPAMPRST_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 12296 | #define RCC_APB1RSTR1_OPAMPRST_Msk (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 12297 | #define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk |
| AnnaBridge | 172:65be27845400 | 12298 | #define RCC_APB1RSTR1_LPTIM1RST_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 12299 | #define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 12300 | #define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12301 | |
| AnnaBridge | 172:65be27845400 | 12302 | /******************** Bit definition for RCC_APB1RSTR2 register **************/ |
| AnnaBridge | 172:65be27845400 | 12303 | #define RCC_APB1RSTR2_LPUART1RST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12304 | #define RCC_APB1RSTR2_LPUART1RST_Msk (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12305 | #define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12306 | #define RCC_APB1RSTR2_I2C4RST_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12307 | #define RCC_APB1RSTR2_I2C4RST_Msk (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12308 | #define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk |
| AnnaBridge | 172:65be27845400 | 12309 | #define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12310 | #define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12311 | #define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12312 | |
| AnnaBridge | 172:65be27845400 | 12313 | /******************** Bit definition for RCC_APB2RSTR register **************/ |
| AnnaBridge | 172:65be27845400 | 12314 | #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12315 | #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12316 | #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk |
| AnnaBridge | 172:65be27845400 | 12317 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 12318 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12319 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12320 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12321 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12322 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12323 | #define RCC_APB2RSTR_TIM8RST_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 12324 | #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12325 | #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk |
| AnnaBridge | 172:65be27845400 | 12326 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12327 | #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12328 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12329 | #define RCC_APB2RSTR_TIM15RST_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12330 | #define RCC_APB2RSTR_TIM15RST_Msk (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12331 | #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk |
| AnnaBridge | 172:65be27845400 | 12332 | #define RCC_APB2RSTR_TIM16RST_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12333 | #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12334 | #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk |
| AnnaBridge | 172:65be27845400 | 12335 | #define RCC_APB2RSTR_TIM17RST_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12336 | #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12337 | #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk |
| AnnaBridge | 172:65be27845400 | 12338 | #define RCC_APB2RSTR_SAI1RST_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12339 | #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12340 | #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12341 | #define RCC_APB2RSTR_SAI2RST_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12342 | #define RCC_APB2RSTR_SAI2RST_Msk (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12343 | #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk |
| AnnaBridge | 172:65be27845400 | 12344 | #define RCC_APB2RSTR_DFSDM1RST_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12345 | #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12346 | #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk |
| AnnaBridge | 172:65be27845400 | 12347 | |
| AnnaBridge | 172:65be27845400 | 12348 | /******************** Bit definition for RCC_AHB1ENR register ***************/ |
| AnnaBridge | 172:65be27845400 | 12349 | #define RCC_AHB1ENR_DMA1EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12350 | #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12351 | #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12352 | #define RCC_AHB1ENR_DMA2EN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12353 | #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12354 | #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12355 | #define RCC_AHB1ENR_DMAMUX1EN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12356 | #define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1U << RCC_AHB1ENR_DMAMUX1EN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12357 | #define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12358 | #define RCC_AHB1ENR_FLASHEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12359 | #define RCC_AHB1ENR_FLASHEN_Msk (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12360 | #define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk |
| AnnaBridge | 172:65be27845400 | 12361 | #define RCC_AHB1ENR_CRCEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12362 | #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12363 | #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk |
| AnnaBridge | 172:65be27845400 | 12364 | #define RCC_AHB1ENR_TSCEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12365 | #define RCC_AHB1ENR_TSCEN_Msk (0x1U << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12366 | #define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk |
| AnnaBridge | 172:65be27845400 | 12367 | #define RCC_AHB1ENR_DMA2DEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12368 | #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12369 | #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk |
| AnnaBridge | 172:65be27845400 | 12370 | |
| AnnaBridge | 172:65be27845400 | 12371 | /******************** Bit definition for RCC_AHB2ENR register ***************/ |
| AnnaBridge | 172:65be27845400 | 12372 | #define RCC_AHB2ENR_GPIOAEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12373 | #define RCC_AHB2ENR_GPIOAEN_Msk (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12374 | #define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk |
| AnnaBridge | 172:65be27845400 | 12375 | #define RCC_AHB2ENR_GPIOBEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12376 | #define RCC_AHB2ENR_GPIOBEN_Msk (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12377 | #define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk |
| AnnaBridge | 172:65be27845400 | 12378 | #define RCC_AHB2ENR_GPIOCEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12379 | #define RCC_AHB2ENR_GPIOCEN_Msk (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12380 | #define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk |
| AnnaBridge | 172:65be27845400 | 12381 | #define RCC_AHB2ENR_GPIODEN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12382 | #define RCC_AHB2ENR_GPIODEN_Msk (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12383 | #define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk |
| AnnaBridge | 172:65be27845400 | 12384 | #define RCC_AHB2ENR_GPIOEEN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12385 | #define RCC_AHB2ENR_GPIOEEN_Msk (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12386 | #define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk |
| AnnaBridge | 172:65be27845400 | 12387 | #define RCC_AHB2ENR_GPIOFEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12388 | #define RCC_AHB2ENR_GPIOFEN_Msk (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12389 | #define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk |
| AnnaBridge | 172:65be27845400 | 12390 | #define RCC_AHB2ENR_GPIOGEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12391 | #define RCC_AHB2ENR_GPIOGEN_Msk (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12392 | #define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk |
| AnnaBridge | 172:65be27845400 | 12393 | #define RCC_AHB2ENR_GPIOHEN_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12394 | #define RCC_AHB2ENR_GPIOHEN_Msk (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12395 | #define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk |
| AnnaBridge | 172:65be27845400 | 12396 | #define RCC_AHB2ENR_GPIOIEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12397 | #define RCC_AHB2ENR_GPIOIEN_Msk (0x1U << RCC_AHB2ENR_GPIOIEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12398 | #define RCC_AHB2ENR_GPIOIEN RCC_AHB2ENR_GPIOIEN_Msk |
| AnnaBridge | 172:65be27845400 | 12399 | #define RCC_AHB2ENR_OTGFSEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12400 | #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12401 | #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk |
| AnnaBridge | 172:65be27845400 | 12402 | #define RCC_AHB2ENR_ADCEN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 12403 | #define RCC_AHB2ENR_ADCEN_Msk (0x1U << RCC_AHB2ENR_ADCEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12404 | #define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk |
| AnnaBridge | 172:65be27845400 | 12405 | #define RCC_AHB2ENR_DCMIEN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12406 | #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12407 | #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk |
| AnnaBridge | 172:65be27845400 | 12408 | #define RCC_AHB2ENR_RNGEN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12409 | #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12410 | #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk |
| AnnaBridge | 172:65be27845400 | 12411 | #define RCC_AHB2ENR_OSPIMEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12412 | #define RCC_AHB2ENR_OSPIMEN_Msk (0x1U << RCC_AHB2ENR_OSPIMEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12413 | #define RCC_AHB2ENR_OSPIMEN RCC_AHB2ENR_OSPIMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12414 | #define RCC_AHB2ENR_SDMMC1EN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12415 | #define RCC_AHB2ENR_SDMMC1EN_Msk (0x1U << RCC_AHB2ENR_SDMMC1EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12416 | #define RCC_AHB2ENR_SDMMC1EN RCC_AHB2ENR_SDMMC1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12417 | |
| AnnaBridge | 172:65be27845400 | 12418 | /******************** Bit definition for RCC_AHB3ENR register ***************/ |
| AnnaBridge | 172:65be27845400 | 12419 | #define RCC_AHB3ENR_FMCEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12420 | #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12421 | #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk |
| AnnaBridge | 172:65be27845400 | 12422 | #define RCC_AHB3ENR_OSPI1EN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12423 | #define RCC_AHB3ENR_OSPI1EN_Msk (0x1U << RCC_AHB3ENR_OSPI1EN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12424 | #define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12425 | #define RCC_AHB3ENR_OSPI2EN_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12426 | #define RCC_AHB3ENR_OSPI2EN_Msk (0x1U << RCC_AHB3ENR_OSPI2EN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12427 | #define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12428 | |
| AnnaBridge | 172:65be27845400 | 12429 | /******************** Bit definition for RCC_APB1ENR1 register ***************/ |
| AnnaBridge | 172:65be27845400 | 12430 | #define RCC_APB1ENR1_TIM2EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12431 | #define RCC_APB1ENR1_TIM2EN_Msk (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12432 | #define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12433 | #define RCC_APB1ENR1_TIM3EN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12434 | #define RCC_APB1ENR1_TIM3EN_Msk (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12435 | #define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk |
| AnnaBridge | 172:65be27845400 | 12436 | #define RCC_APB1ENR1_TIM4EN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12437 | #define RCC_APB1ENR1_TIM4EN_Msk (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12438 | #define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk |
| AnnaBridge | 172:65be27845400 | 12439 | #define RCC_APB1ENR1_TIM5EN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12440 | #define RCC_APB1ENR1_TIM5EN_Msk (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12441 | #define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk |
| AnnaBridge | 172:65be27845400 | 12442 | #define RCC_APB1ENR1_TIM6EN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12443 | #define RCC_APB1ENR1_TIM6EN_Msk (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12444 | #define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk |
| AnnaBridge | 172:65be27845400 | 12445 | #define RCC_APB1ENR1_TIM7EN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12446 | #define RCC_APB1ENR1_TIM7EN_Msk (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12447 | #define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk |
| AnnaBridge | 172:65be27845400 | 12448 | #define RCC_APB1ENR1_RTCAPBEN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12449 | #define RCC_APB1ENR1_RTCAPBEN_Msk (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12450 | #define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk |
| AnnaBridge | 172:65be27845400 | 12451 | #define RCC_APB1ENR1_WWDGEN_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 12452 | #define RCC_APB1ENR1_WWDGEN_Msk (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12453 | #define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk |
| AnnaBridge | 172:65be27845400 | 12454 | #define RCC_APB1ENR1_SPI2EN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12455 | #define RCC_APB1ENR1_SPI2EN_Msk (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12456 | #define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12457 | #define RCC_APB1ENR1_SPI3EN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 12458 | #define RCC_APB1ENR1_SPI3EN_Msk (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 12459 | #define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk |
| AnnaBridge | 172:65be27845400 | 12460 | #define RCC_APB1ENR1_USART2EN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12461 | #define RCC_APB1ENR1_USART2EN_Msk (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12462 | #define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12463 | #define RCC_APB1ENR1_USART3EN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12464 | #define RCC_APB1ENR1_USART3EN_Msk (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12465 | #define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk |
| AnnaBridge | 172:65be27845400 | 12466 | #define RCC_APB1ENR1_UART4EN_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 12467 | #define RCC_APB1ENR1_UART4EN_Msk (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 12468 | #define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk |
| AnnaBridge | 172:65be27845400 | 12469 | #define RCC_APB1ENR1_UART5EN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12470 | #define RCC_APB1ENR1_UART5EN_Msk (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12471 | #define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk |
| AnnaBridge | 172:65be27845400 | 12472 | #define RCC_APB1ENR1_I2C1EN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12473 | #define RCC_APB1ENR1_I2C1EN_Msk (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12474 | #define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12475 | #define RCC_APB1ENR1_I2C2EN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12476 | #define RCC_APB1ENR1_I2C2EN_Msk (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12477 | #define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12478 | #define RCC_APB1ENR1_I2C3EN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 12479 | #define RCC_APB1ENR1_I2C3EN_Msk (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 12480 | #define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk |
| AnnaBridge | 172:65be27845400 | 12481 | #define RCC_APB1ENR1_CRSEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12482 | #define RCC_APB1ENR1_CRSEN_Msk (0x1U << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12483 | #define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk |
| AnnaBridge | 172:65be27845400 | 12484 | #define RCC_APB1ENR1_CAN1EN_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 12485 | #define RCC_APB1ENR1_CAN1EN_Msk (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 12486 | #define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12487 | #define RCC_APB1ENR1_PWREN_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 12488 | #define RCC_APB1ENR1_PWREN_Msk (0x1U << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 12489 | #define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk |
| AnnaBridge | 172:65be27845400 | 12490 | #define RCC_APB1ENR1_DAC1EN_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 12491 | #define RCC_APB1ENR1_DAC1EN_Msk (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 12492 | #define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12493 | #define RCC_APB1ENR1_OPAMPEN_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 12494 | #define RCC_APB1ENR1_OPAMPEN_Msk (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 12495 | #define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk |
| AnnaBridge | 172:65be27845400 | 12496 | #define RCC_APB1ENR1_LPTIM1EN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 12497 | #define RCC_APB1ENR1_LPTIM1EN_Msk (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 12498 | #define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12499 | |
| AnnaBridge | 172:65be27845400 | 12500 | /******************** Bit definition for RCC_APB1RSTR2 register **************/ |
| AnnaBridge | 172:65be27845400 | 12501 | #define RCC_APB1ENR2_LPUART1EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12502 | #define RCC_APB1ENR2_LPUART1EN_Msk (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12503 | #define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12504 | #define RCC_APB1ENR2_I2C4EN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12505 | #define RCC_APB1ENR2_I2C4EN_Msk (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12506 | #define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk |
| AnnaBridge | 172:65be27845400 | 12507 | #define RCC_APB1ENR2_LPTIM2EN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12508 | #define RCC_APB1ENR2_LPTIM2EN_Msk (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12509 | #define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12510 | |
| AnnaBridge | 172:65be27845400 | 12511 | /******************** Bit definition for RCC_APB2ENR register ***************/ |
| AnnaBridge | 172:65be27845400 | 12512 | #define RCC_APB2ENR_SYSCFGEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12513 | #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12514 | #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk |
| AnnaBridge | 172:65be27845400 | 12515 | #define RCC_APB2ENR_FWEN_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12516 | #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12517 | #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk |
| AnnaBridge | 172:65be27845400 | 12518 | #define RCC_APB2ENR_TIM1EN_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 12519 | #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12520 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12521 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12522 | #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12523 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12524 | #define RCC_APB2ENR_TIM8EN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 12525 | #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12526 | #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk |
| AnnaBridge | 172:65be27845400 | 12527 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12528 | #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12529 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12530 | #define RCC_APB2ENR_TIM15EN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12531 | #define RCC_APB2ENR_TIM15EN_Msk (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12532 | #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk |
| AnnaBridge | 172:65be27845400 | 12533 | #define RCC_APB2ENR_TIM16EN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12534 | #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12535 | #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk |
| AnnaBridge | 172:65be27845400 | 12536 | #define RCC_APB2ENR_TIM17EN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12537 | #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12538 | #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk |
| AnnaBridge | 172:65be27845400 | 12539 | #define RCC_APB2ENR_SAI1EN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12540 | #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12541 | #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12542 | #define RCC_APB2ENR_SAI2EN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12543 | #define RCC_APB2ENR_SAI2EN_Msk (0x1U << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12544 | #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk |
| AnnaBridge | 172:65be27845400 | 12545 | #define RCC_APB2ENR_DFSDM1EN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12546 | #define RCC_APB2ENR_DFSDM1EN_Msk (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12547 | #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk |
| AnnaBridge | 172:65be27845400 | 12548 | |
| AnnaBridge | 172:65be27845400 | 12549 | /******************** Bit definition for RCC_AHB1SMENR register ***************/ |
| AnnaBridge | 172:65be27845400 | 12550 | #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12551 | #define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12552 | #define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12553 | #define RCC_AHB1SMENR_DMA2SMEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12554 | #define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12555 | #define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12556 | #define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12557 | #define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1U << RCC_AHB1SMENR_DMAMUX1SMEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12558 | #define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12559 | #define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12560 | #define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12561 | #define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12562 | #define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12563 | #define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12564 | #define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12565 | #define RCC_AHB1SMENR_CRCSMEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12566 | #define RCC_AHB1SMENR_CRCSMEN_Msk (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12567 | #define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12568 | #define RCC_AHB1SMENR_TSCSMEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12569 | #define RCC_AHB1SMENR_TSCSMEN_Msk (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12570 | #define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12571 | #define RCC_AHB1SMENR_DMA2DSMEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12572 | #define RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1U << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12573 | #define RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12574 | |
| AnnaBridge | 172:65be27845400 | 12575 | /******************** Bit definition for RCC_AHB2SMENR register *************/ |
| AnnaBridge | 172:65be27845400 | 12576 | #define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12577 | #define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12578 | #define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12579 | #define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12580 | #define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12581 | #define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12582 | #define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12583 | #define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12584 | #define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12585 | #define RCC_AHB2SMENR_GPIODSMEN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12586 | #define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12587 | #define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12588 | #define RCC_AHB2SMENR_GPIOESMEN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12589 | #define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12590 | #define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12591 | #define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12592 | #define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12593 | #define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12594 | #define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12595 | #define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12596 | #define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12597 | #define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12598 | #define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12599 | #define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12600 | #define RCC_AHB2SMENR_GPIOISMEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12601 | #define RCC_AHB2SMENR_GPIOISMEN_Msk (0x1U << RCC_AHB2SMENR_GPIOISMEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12602 | #define RCC_AHB2SMENR_GPIOISMEN RCC_AHB2SMENR_GPIOISMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12603 | #define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12604 | #define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12605 | #define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12606 | #define RCC_AHB2SMENR_SRAM3SMEN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12607 | #define RCC_AHB2SMENR_SRAM3SMEN_Msk (0x1U << RCC_AHB2SMENR_SRAM3SMEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12608 | #define RCC_AHB2SMENR_SRAM3SMEN RCC_AHB2SMENR_SRAM3SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12609 | #define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12610 | #define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12611 | #define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12612 | #define RCC_AHB2SMENR_ADCSMEN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 12613 | #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12614 | #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12615 | #define RCC_AHB2SMENR_DCMISMEN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12616 | #define RCC_AHB2SMENR_DCMISMEN_Msk (0x1U << RCC_AHB2SMENR_DCMISMEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12617 | #define RCC_AHB2SMENR_DCMISMEN RCC_AHB2SMENR_DCMISMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12618 | #define RCC_AHB2SMENR_RNGSMEN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12619 | #define RCC_AHB2SMENR_RNGSMEN_Msk (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12620 | #define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12621 | #define RCC_AHB2SMENR_OSPIMSMEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12622 | #define RCC_AHB2SMENR_OSPIMSMEN_Msk (0x1U << RCC_AHB2SMENR_OSPIMSMEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12623 | #define RCC_AHB2SMENR_OSPIMSMEN RCC_AHB2SMENR_OSPIMSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12624 | #define RCC_AHB2SMENR_SDMMC1SMEN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12625 | #define RCC_AHB2SMENR_SDMMC1SMEN_Msk (0x1U << RCC_AHB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12626 | #define RCC_AHB2SMENR_SDMMC1SMEN RCC_AHB2SMENR_SDMMC1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12627 | |
| AnnaBridge | 172:65be27845400 | 12628 | /******************** Bit definition for RCC_AHB3SMENR register *************/ |
| AnnaBridge | 172:65be27845400 | 12629 | #define RCC_AHB3SMENR_FMCSMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12630 | #define RCC_AHB3SMENR_FMCSMEN_Msk (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12631 | #define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12632 | #define RCC_AHB3SMENR_OSPI1SMEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12633 | #define RCC_AHB3SMENR_OSPI1SMEN_Msk (0x1U << RCC_AHB3SMENR_OSPI1SMEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12634 | #define RCC_AHB3SMENR_OSPI1SMEN RCC_AHB3SMENR_OSPI1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12635 | #define RCC_AHB3SMENR_OSPI2SMEN_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 12636 | #define RCC_AHB3SMENR_OSPI2SMEN_Msk (0x1U << RCC_AHB3SMENR_OSPI2SMEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12637 | #define RCC_AHB3SMENR_OSPI2SMEN RCC_AHB3SMENR_OSPI2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12638 | |
| AnnaBridge | 172:65be27845400 | 12639 | /******************** Bit definition for RCC_APB1SMENR1 register *************/ |
| AnnaBridge | 172:65be27845400 | 12640 | #define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12641 | #define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12642 | #define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12643 | #define RCC_APB1SMENR1_TIM3SMEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12644 | #define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12645 | #define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12646 | #define RCC_APB1SMENR1_TIM4SMEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12647 | #define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12648 | #define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12649 | #define RCC_APB1SMENR1_TIM5SMEN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12650 | #define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12651 | #define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12652 | #define RCC_APB1SMENR1_TIM6SMEN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12653 | #define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12654 | #define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12655 | #define RCC_APB1SMENR1_TIM7SMEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12656 | #define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12657 | #define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12658 | #define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12659 | #define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12660 | #define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12661 | #define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 12662 | #define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12663 | #define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12664 | #define RCC_APB1SMENR1_SPI2SMEN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12665 | #define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12666 | #define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12667 | #define RCC_APB1SMENR1_SPI3SMEN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 12668 | #define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 12669 | #define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12670 | #define RCC_APB1SMENR1_USART2SMEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12671 | #define RCC_APB1SMENR1_USART2SMEN_Msk (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12672 | #define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12673 | #define RCC_APB1SMENR1_USART3SMEN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12674 | #define RCC_APB1SMENR1_USART3SMEN_Msk (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12675 | #define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12676 | #define RCC_APB1SMENR1_UART4SMEN_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 12677 | #define RCC_APB1SMENR1_UART4SMEN_Msk (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 12678 | #define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12679 | #define RCC_APB1SMENR1_UART5SMEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12680 | #define RCC_APB1SMENR1_UART5SMEN_Msk (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12681 | #define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12682 | #define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12683 | #define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12684 | #define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12685 | #define RCC_APB1SMENR1_I2C2SMEN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12686 | #define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12687 | #define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12688 | #define RCC_APB1SMENR1_I2C3SMEN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 12689 | #define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 12690 | #define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12691 | #define RCC_APB1SMENR1_CRSSMEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12692 | #define RCC_APB1SMENR1_CRSSMEN_Msk (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12693 | #define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12694 | #define RCC_APB1SMENR1_CAN1SMEN_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 12695 | #define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 12696 | #define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12697 | #define RCC_APB1SMENR1_PWRSMEN_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 12698 | #define RCC_APB1SMENR1_PWRSMEN_Msk (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 12699 | #define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12700 | #define RCC_APB1SMENR1_DAC1SMEN_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 12701 | #define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 12702 | #define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12703 | #define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 12704 | #define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 12705 | #define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12706 | #define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 12707 | #define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 12708 | #define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12709 | |
| AnnaBridge | 172:65be27845400 | 12710 | /******************** Bit definition for RCC_APB1SMENR2 register *************/ |
| AnnaBridge | 172:65be27845400 | 12711 | #define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12712 | #define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12713 | #define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12714 | #define RCC_APB1SMENR2_I2C4SMEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12715 | #define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12716 | #define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12717 | #define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12718 | #define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12719 | #define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12720 | |
| AnnaBridge | 172:65be27845400 | 12721 | /******************** Bit definition for RCC_APB2SMENR register *************/ |
| AnnaBridge | 172:65be27845400 | 12722 | #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12723 | #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12724 | #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12725 | #define RCC_APB2SMENR_TIM1SMEN_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 12726 | #define RCC_APB2SMENR_TIM1SMEN_Msk (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12727 | #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12728 | #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12729 | #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12730 | #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12731 | #define RCC_APB2SMENR_TIM8SMEN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 12732 | #define RCC_APB2SMENR_TIM8SMEN_Msk (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12733 | #define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12734 | #define RCC_APB2SMENR_USART1SMEN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12735 | #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12736 | #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12737 | #define RCC_APB2SMENR_TIM15SMEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12738 | #define RCC_APB2SMENR_TIM15SMEN_Msk (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12739 | #define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12740 | #define RCC_APB2SMENR_TIM16SMEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 12741 | #define RCC_APB2SMENR_TIM16SMEN_Msk (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12742 | #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12743 | #define RCC_APB2SMENR_TIM17SMEN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12744 | #define RCC_APB2SMENR_TIM17SMEN_Msk (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12745 | #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12746 | #define RCC_APB2SMENR_SAI1SMEN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 12747 | #define RCC_APB2SMENR_SAI1SMEN_Msk (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12748 | #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12749 | #define RCC_APB2SMENR_SAI2SMEN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 12750 | #define RCC_APB2SMENR_SAI2SMEN_Msk (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 12751 | #define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12752 | #define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12753 | #define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12754 | #define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk |
| AnnaBridge | 172:65be27845400 | 12755 | |
| AnnaBridge | 172:65be27845400 | 12756 | /******************** Bit definition for RCC_CCIPR register ******************/ |
| AnnaBridge | 172:65be27845400 | 12757 | #define RCC_CCIPR_USART1SEL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12758 | #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 12759 | #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12760 | #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12761 | #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12762 | |
| AnnaBridge | 172:65be27845400 | 12763 | #define RCC_CCIPR_USART2SEL_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12764 | #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 12765 | #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12766 | #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12767 | #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12768 | |
| AnnaBridge | 172:65be27845400 | 12769 | #define RCC_CCIPR_USART3SEL_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 12770 | #define RCC_CCIPR_USART3SEL_Msk (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 12771 | #define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12772 | #define RCC_CCIPR_USART3SEL_0 (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12773 | #define RCC_CCIPR_USART3SEL_1 (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12774 | |
| AnnaBridge | 172:65be27845400 | 12775 | #define RCC_CCIPR_UART4SEL_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12776 | #define RCC_CCIPR_UART4SEL_Msk (0x3U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 12777 | #define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12778 | #define RCC_CCIPR_UART4SEL_0 (0x1U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12779 | #define RCC_CCIPR_UART4SEL_1 (0x2U << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12780 | |
| AnnaBridge | 172:65be27845400 | 12781 | #define RCC_CCIPR_UART5SEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12782 | #define RCC_CCIPR_UART5SEL_Msk (0x3U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 12783 | #define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12784 | #define RCC_CCIPR_UART5SEL_0 (0x1U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12785 | #define RCC_CCIPR_UART5SEL_1 (0x2U << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12786 | |
| AnnaBridge | 172:65be27845400 | 12787 | #define RCC_CCIPR_LPUART1SEL_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 12788 | #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 12789 | #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12790 | #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12791 | #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12792 | |
| AnnaBridge | 172:65be27845400 | 12793 | #define RCC_CCIPR_I2C1SEL_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 12794 | #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 12795 | #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12796 | #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12797 | #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12798 | |
| AnnaBridge | 172:65be27845400 | 12799 | #define RCC_CCIPR_I2C2SEL_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12800 | #define RCC_CCIPR_I2C2SEL_Msk (0x3U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 12801 | #define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12802 | #define RCC_CCIPR_I2C2SEL_0 (0x1U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12803 | #define RCC_CCIPR_I2C2SEL_1 (0x2U << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 12804 | |
| AnnaBridge | 172:65be27845400 | 12805 | #define RCC_CCIPR_I2C3SEL_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12806 | #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 12807 | #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12808 | #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12809 | #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12810 | |
| AnnaBridge | 172:65be27845400 | 12811 | #define RCC_CCIPR_LPTIM1SEL_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 12812 | #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 12813 | #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12814 | #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 12815 | #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 12816 | |
| AnnaBridge | 172:65be27845400 | 12817 | #define RCC_CCIPR_LPTIM2SEL_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12818 | #define RCC_CCIPR_LPTIM2SEL_Msk (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 12819 | #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12820 | #define RCC_CCIPR_LPTIM2SEL_0 (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12821 | #define RCC_CCIPR_LPTIM2SEL_1 (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12822 | |
| AnnaBridge | 172:65be27845400 | 12823 | #define RCC_CCIPR_CLK48SEL_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 12824 | #define RCC_CCIPR_CLK48SEL_Msk (0x3U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */ |
| AnnaBridge | 172:65be27845400 | 12825 | #define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12826 | #define RCC_CCIPR_CLK48SEL_0 (0x1U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 12827 | #define RCC_CCIPR_CLK48SEL_1 (0x2U << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 12828 | |
| AnnaBridge | 172:65be27845400 | 12829 | #define RCC_CCIPR_ADCSEL_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 12830 | #define RCC_CCIPR_ADCSEL_Msk (0x3U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 12831 | #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk |
| AnnaBridge | 172:65be27845400 | 12832 | #define RCC_CCIPR_ADCSEL_0 (0x1U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 12833 | #define RCC_CCIPR_ADCSEL_1 (0x2U << RCC_CCIPR_ADCSEL_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 12834 | |
| AnnaBridge | 172:65be27845400 | 12835 | /******************** Bit definition for RCC_BDCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 12836 | #define RCC_BDCR_LSEON_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12837 | #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12838 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk |
| AnnaBridge | 172:65be27845400 | 12839 | #define RCC_BDCR_LSERDY_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12840 | #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12841 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk |
| AnnaBridge | 172:65be27845400 | 12842 | #define RCC_BDCR_LSEBYP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12843 | #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12844 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk |
| AnnaBridge | 172:65be27845400 | 12845 | |
| AnnaBridge | 172:65be27845400 | 12846 | #define RCC_BDCR_LSEDRV_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12847 | #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 172:65be27845400 | 12848 | #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk |
| AnnaBridge | 172:65be27845400 | 12849 | #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12850 | #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12851 | |
| AnnaBridge | 172:65be27845400 | 12852 | #define RCC_BDCR_LSECSSON_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12853 | #define RCC_BDCR_LSECSSON_Msk (0x1U << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12854 | #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk |
| AnnaBridge | 172:65be27845400 | 12855 | #define RCC_BDCR_LSECSSD_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 12856 | #define RCC_BDCR_LSECSSD_Msk (0x1U << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12857 | #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk |
| AnnaBridge | 172:65be27845400 | 12858 | |
| AnnaBridge | 172:65be27845400 | 12859 | #define RCC_BDCR_RTCSEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12860 | #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 12861 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk |
| AnnaBridge | 172:65be27845400 | 12862 | #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12863 | #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12864 | |
| AnnaBridge | 172:65be27845400 | 12865 | #define RCC_BDCR_RTCEN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 12866 | #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 12867 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk |
| AnnaBridge | 172:65be27845400 | 12868 | #define RCC_BDCR_BDRST_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12869 | #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12870 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk |
| AnnaBridge | 172:65be27845400 | 12871 | #define RCC_BDCR_LSCOEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12872 | #define RCC_BDCR_LSCOEN_Msk (0x1U << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12873 | #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk |
| AnnaBridge | 172:65be27845400 | 12874 | #define RCC_BDCR_LSCOSEL_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 12875 | #define RCC_BDCR_LSCOSEL_Msk (0x1U << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 12876 | #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk |
| AnnaBridge | 172:65be27845400 | 12877 | |
| AnnaBridge | 172:65be27845400 | 12878 | /******************** Bit definition for RCC_CSR register *******************/ |
| AnnaBridge | 172:65be27845400 | 12879 | #define RCC_CSR_LSION_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12880 | #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12881 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk |
| AnnaBridge | 172:65be27845400 | 12882 | #define RCC_CSR_LSIRDY_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12883 | #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12884 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk |
| AnnaBridge | 172:65be27845400 | 12885 | |
| AnnaBridge | 172:65be27845400 | 12886 | #define RCC_CSR_MSISRANGE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12887 | #define RCC_CSR_MSISRANGE_Msk (0xFU << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 12888 | #define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk |
| AnnaBridge | 172:65be27845400 | 12889 | #define RCC_CSR_MSISRANGE_1 (0x4U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12890 | #define RCC_CSR_MSISRANGE_2 (0x5U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000500 */ |
| AnnaBridge | 172:65be27845400 | 12891 | #define RCC_CSR_MSISRANGE_4 (0x6U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 172:65be27845400 | 12892 | #define RCC_CSR_MSISRANGE_8 (0x7U << RCC_CSR_MSISRANGE_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 12893 | |
| AnnaBridge | 172:65be27845400 | 12894 | #define RCC_CSR_RMVF_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 12895 | #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 12896 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk |
| AnnaBridge | 172:65be27845400 | 12897 | #define RCC_CSR_FWRSTF_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 12898 | #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 12899 | #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12900 | #define RCC_CSR_OBLRSTF_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 12901 | #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 12902 | #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12903 | #define RCC_CSR_PINRSTF_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 12904 | #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 12905 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12906 | #define RCC_CSR_BORRSTF_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 12907 | #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 12908 | #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12909 | #define RCC_CSR_SFTRSTF_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 12910 | #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 12911 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12912 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 12913 | #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 12914 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12915 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 12916 | #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 12917 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12918 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 12919 | #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 12920 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk |
| AnnaBridge | 172:65be27845400 | 12921 | |
| AnnaBridge | 172:65be27845400 | 12922 | /******************** Bit definition for RCC_CRRCR register *****************/ |
| AnnaBridge | 172:65be27845400 | 12923 | #define RCC_CRRCR_HSI48ON_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12924 | #define RCC_CRRCR_HSI48ON_Msk (0x1U << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12925 | #define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk |
| AnnaBridge | 172:65be27845400 | 12926 | #define RCC_CRRCR_HSI48RDY_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 12927 | #define RCC_CRRCR_HSI48RDY_Msk (0x1U << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12928 | #define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk |
| AnnaBridge | 172:65be27845400 | 12929 | |
| AnnaBridge | 172:65be27845400 | 12930 | /*!< HSI48CAL configuration */ |
| AnnaBridge | 172:65be27845400 | 12931 | #define RCC_CRRCR_HSI48CAL_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 12932 | #define RCC_CRRCR_HSI48CAL_Msk (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */ |
| AnnaBridge | 172:65be27845400 | 12933 | #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */ |
| AnnaBridge | 172:65be27845400 | 12934 | #define RCC_CRRCR_HSI48CAL_0 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12935 | #define RCC_CRRCR_HSI48CAL_1 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12936 | #define RCC_CRRCR_HSI48CAL_2 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12937 | #define RCC_CRRCR_HSI48CAL_3 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12938 | #define RCC_CRRCR_HSI48CAL_4 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 12939 | #define RCC_CRRCR_HSI48CAL_5 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 12940 | #define RCC_CRRCR_HSI48CAL_6 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 12941 | #define RCC_CRRCR_HSI48CAL_7 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12942 | #define RCC_CRRCR_HSI48CAL_8 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 12943 | |
| AnnaBridge | 172:65be27845400 | 12944 | /******************** Bit definition for RCC_CCIPR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 12945 | #define RCC_CCIPR2_I2C4SEL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 12946 | #define RCC_CCIPR2_I2C4SEL_Msk (0x3U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 12947 | #define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12948 | #define RCC_CCIPR2_I2C4SEL_0 (0x1U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 12949 | #define RCC_CCIPR2_I2C4SEL_1 (0x2U << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 12950 | |
| AnnaBridge | 172:65be27845400 | 12951 | #define RCC_CCIPR2_DFSDM1SEL_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12952 | #define RCC_CCIPR2_DFSDM1SEL_Msk (0x1U << RCC_CCIPR2_DFSDM1SEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12953 | #define RCC_CCIPR2_DFSDM1SEL RCC_CCIPR2_DFSDM1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12954 | |
| AnnaBridge | 172:65be27845400 | 12955 | #define RCC_CCIPR2_ADFSDM1SEL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 12956 | #define RCC_CCIPR2_ADFSDM1SEL_Msk (0x3U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 172:65be27845400 | 12957 | #define RCC_CCIPR2_ADFSDM1SEL RCC_CCIPR2_ADFSDM1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12958 | #define RCC_CCIPR2_ADFSDM1SEL_0 (0x1U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 12959 | #define RCC_CCIPR2_ADFSDM1SEL_1 (0x2U << RCC_CCIPR2_ADFSDM1SEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 12960 | |
| AnnaBridge | 172:65be27845400 | 12961 | #define RCC_CCIPR2_SAI1SEL_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 12962 | #define RCC_CCIPR2_SAI1SEL_Msk (0x7U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 172:65be27845400 | 12963 | #define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12964 | #define RCC_CCIPR2_SAI1SEL_0 (0x1U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 12965 | #define RCC_CCIPR2_SAI1SEL_1 (0x2U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 12966 | #define RCC_CCIPR2_SAI1SEL_2 (0x4U << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 12967 | |
| AnnaBridge | 172:65be27845400 | 12968 | #define RCC_CCIPR2_SAI2SEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 12969 | #define RCC_CCIPR2_SAI2SEL_Msk (0x7U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 12970 | #define RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk |
| AnnaBridge | 172:65be27845400 | 12971 | #define RCC_CCIPR2_SAI2SEL_0 (0x1U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 12972 | #define RCC_CCIPR2_SAI2SEL_1 (0x2U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 12973 | #define RCC_CCIPR2_SAI2SEL_2 (0x4U << RCC_CCIPR2_SAI2SEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 12974 | |
| AnnaBridge | 172:65be27845400 | 12975 | #define RCC_CCIPR2_SDMMCSEL_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 12976 | #define RCC_CCIPR2_SDMMCSEL_Msk (0x1U << RCC_CCIPR2_SDMMCSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 12977 | #define RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk |
| AnnaBridge | 172:65be27845400 | 12978 | |
| AnnaBridge | 172:65be27845400 | 12979 | #define RCC_CCIPR2_PLLSAI2DIVR_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 12980 | #define RCC_CCIPR2_PLLSAI2DIVR_Msk (0x3U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 12981 | #define RCC_CCIPR2_PLLSAI2DIVR RCC_CCIPR2_PLLSAI2DIVR_Msk |
| AnnaBridge | 172:65be27845400 | 12982 | #define RCC_CCIPR2_PLLSAI2DIVR_0 (0x1U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 12983 | #define RCC_CCIPR2_PLLSAI2DIVR_1 (0x2U << RCC_CCIPR2_PLLSAI2DIVR_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 12984 | |
| AnnaBridge | 172:65be27845400 | 12985 | #define RCC_CCIPR2_OSPISEL_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 12986 | #define RCC_CCIPR2_OSPISEL_Msk (0x3U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 12987 | #define RCC_CCIPR2_OSPISEL RCC_CCIPR2_OSPISEL_Msk |
| AnnaBridge | 172:65be27845400 | 12988 | #define RCC_CCIPR2_OSPISEL_0 (0x1U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 12989 | #define RCC_CCIPR2_OSPISEL_1 (0x2U << RCC_CCIPR2_OSPISEL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 12990 | |
| AnnaBridge | 172:65be27845400 | 12991 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 12992 | /* */ |
| AnnaBridge | 172:65be27845400 | 12993 | /* RNG */ |
| AnnaBridge | 172:65be27845400 | 12994 | /* */ |
| AnnaBridge | 172:65be27845400 | 12995 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 12996 | /******************** Bits definition for RNG_CR register *******************/ |
| AnnaBridge | 172:65be27845400 | 12997 | #define RNG_CR_RNGEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 12998 | #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 12999 | #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk |
| AnnaBridge | 172:65be27845400 | 13000 | #define RNG_CR_IE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 13001 | #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13002 | #define RNG_CR_IE RNG_CR_IE_Msk |
| AnnaBridge | 172:65be27845400 | 13003 | #define RNG_CR_CED_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13004 | #define RNG_CR_CED_Msk (0x1U << RNG_CR_CED_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13005 | #define RNG_CR_CED RNG_CR_CED_Msk |
| AnnaBridge | 172:65be27845400 | 13006 | |
| AnnaBridge | 172:65be27845400 | 13007 | /******************** Bits definition for RNG_SR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13008 | #define RNG_SR_DRDY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13009 | #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13010 | #define RNG_SR_DRDY RNG_SR_DRDY_Msk |
| AnnaBridge | 172:65be27845400 | 13011 | #define RNG_SR_CECS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 13012 | #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13013 | #define RNG_SR_CECS RNG_SR_CECS_Msk |
| AnnaBridge | 172:65be27845400 | 13014 | #define RNG_SR_SECS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 13015 | #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13016 | #define RNG_SR_SECS RNG_SR_SECS_Msk |
| AnnaBridge | 172:65be27845400 | 13017 | #define RNG_SR_CEIS_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13018 | #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13019 | #define RNG_SR_CEIS RNG_SR_CEIS_Msk |
| AnnaBridge | 172:65be27845400 | 13020 | #define RNG_SR_SEIS_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 13021 | #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13022 | #define RNG_SR_SEIS RNG_SR_SEIS_Msk |
| AnnaBridge | 172:65be27845400 | 13023 | |
| AnnaBridge | 172:65be27845400 | 13024 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 13025 | /* */ |
| AnnaBridge | 172:65be27845400 | 13026 | /* Real-Time Clock (RTC) */ |
| AnnaBridge | 172:65be27845400 | 13027 | /* */ |
| AnnaBridge | 172:65be27845400 | 13028 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 13029 | /* |
| AnnaBridge | 172:65be27845400 | 13030 | * @brief Specific device feature definitions |
| AnnaBridge | 172:65be27845400 | 13031 | */ |
| AnnaBridge | 172:65be27845400 | 13032 | #define RTC_TAMPER1_SUPPORT |
| AnnaBridge | 172:65be27845400 | 13033 | #define RTC_TAMPER2_SUPPORT |
| AnnaBridge | 172:65be27845400 | 13034 | #define RTC_TAMPER3_SUPPORT |
| AnnaBridge | 172:65be27845400 | 13035 | #define RTC_WAKEUP_SUPPORT |
| AnnaBridge | 172:65be27845400 | 13036 | #define RTC_BACKUP_SUPPORT |
| AnnaBridge | 172:65be27845400 | 13037 | |
| AnnaBridge | 172:65be27845400 | 13038 | /******************** Bits definition for RTC_TR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13039 | #define RTC_TR_PM_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 13040 | #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13041 | #define RTC_TR_PM RTC_TR_PM_Msk |
| AnnaBridge | 172:65be27845400 | 13042 | #define RTC_TR_HT_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13043 | #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 13044 | #define RTC_TR_HT RTC_TR_HT_Msk |
| AnnaBridge | 172:65be27845400 | 13045 | #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13046 | #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13047 | #define RTC_TR_HU_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13048 | #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 13049 | #define RTC_TR_HU RTC_TR_HU_Msk |
| AnnaBridge | 172:65be27845400 | 13050 | #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13051 | #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13052 | #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13053 | #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13054 | #define RTC_TR_MNT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13055 | #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 13056 | #define RTC_TR_MNT RTC_TR_MNT_Msk |
| AnnaBridge | 172:65be27845400 | 13057 | #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13058 | #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13059 | #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13060 | #define RTC_TR_MNU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13061 | #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13062 | #define RTC_TR_MNU RTC_TR_MNU_Msk |
| AnnaBridge | 172:65be27845400 | 13063 | #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13064 | #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13065 | #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13066 | #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13067 | #define RTC_TR_ST_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13068 | #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 13069 | #define RTC_TR_ST RTC_TR_ST_Msk |
| AnnaBridge | 172:65be27845400 | 13070 | #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13071 | #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13072 | #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13073 | #define RTC_TR_SU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13074 | #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 13075 | #define RTC_TR_SU RTC_TR_SU_Msk |
| AnnaBridge | 172:65be27845400 | 13076 | #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13077 | #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13078 | #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13079 | #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13080 | |
| AnnaBridge | 172:65be27845400 | 13081 | /******************** Bits definition for RTC_DR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13082 | #define RTC_DR_YT_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13083 | #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 13084 | #define RTC_DR_YT RTC_DR_YT_Msk |
| AnnaBridge | 172:65be27845400 | 13085 | #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13086 | #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13087 | #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13088 | #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 13089 | #define RTC_DR_YU_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13090 | #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 13091 | #define RTC_DR_YU RTC_DR_YU_Msk |
| AnnaBridge | 172:65be27845400 | 13092 | #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13093 | #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13094 | #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13095 | #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13096 | #define RTC_DR_WDU_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13097 | #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 172:65be27845400 | 13098 | #define RTC_DR_WDU RTC_DR_WDU_Msk |
| AnnaBridge | 172:65be27845400 | 13099 | #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13100 | #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13101 | #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13102 | #define RTC_DR_MT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13103 | #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13104 | #define RTC_DR_MT RTC_DR_MT_Msk |
| AnnaBridge | 172:65be27845400 | 13105 | #define RTC_DR_MU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13106 | #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13107 | #define RTC_DR_MU RTC_DR_MU_Msk |
| AnnaBridge | 172:65be27845400 | 13108 | #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13109 | #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13110 | #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13111 | #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13112 | #define RTC_DR_DT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13113 | #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 13114 | #define RTC_DR_DT RTC_DR_DT_Msk |
| AnnaBridge | 172:65be27845400 | 13115 | #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13116 | #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13117 | #define RTC_DR_DU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13118 | #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 13119 | #define RTC_DR_DU RTC_DR_DU_Msk |
| AnnaBridge | 172:65be27845400 | 13120 | #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13121 | #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13122 | #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13123 | #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13124 | |
| AnnaBridge | 172:65be27845400 | 13125 | /******************** Bits definition for RTC_CR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13126 | #define RTC_CR_ITSE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 13127 | #define RTC_CR_ITSE_Msk (0x1U << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 13128 | #define RTC_CR_ITSE RTC_CR_ITSE_Msk |
| AnnaBridge | 172:65be27845400 | 13129 | #define RTC_CR_COE_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 13130 | #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 13131 | #define RTC_CR_COE RTC_CR_COE_Msk |
| AnnaBridge | 172:65be27845400 | 13132 | #define RTC_CR_OSEL_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 13133 | #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 172:65be27845400 | 13134 | #define RTC_CR_OSEL RTC_CR_OSEL_Msk |
| AnnaBridge | 172:65be27845400 | 13135 | #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13136 | #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13137 | #define RTC_CR_POL_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13138 | #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13139 | #define RTC_CR_POL RTC_CR_POL_Msk |
| AnnaBridge | 172:65be27845400 | 13140 | #define RTC_CR_COSEL_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 13141 | #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13142 | #define RTC_CR_COSEL RTC_CR_COSEL_Msk |
| AnnaBridge | 172:65be27845400 | 13143 | #define RTC_CR_BKP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 13144 | #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13145 | #define RTC_CR_BKP RTC_CR_BKP_Msk |
| AnnaBridge | 172:65be27845400 | 13146 | #define RTC_CR_SUB1H_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 13147 | #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13148 | #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk |
| AnnaBridge | 172:65be27845400 | 13149 | #define RTC_CR_ADD1H_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13150 | #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13151 | #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk |
| AnnaBridge | 172:65be27845400 | 13152 | #define RTC_CR_TSIE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 13153 | #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13154 | #define RTC_CR_TSIE RTC_CR_TSIE_Msk |
| AnnaBridge | 172:65be27845400 | 13155 | #define RTC_CR_WUTIE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 13156 | #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13157 | #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk |
| AnnaBridge | 172:65be27845400 | 13158 | #define RTC_CR_ALRBIE_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13159 | #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13160 | #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk |
| AnnaBridge | 172:65be27845400 | 13161 | #define RTC_CR_ALRAIE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13162 | #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13163 | #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk |
| AnnaBridge | 172:65be27845400 | 13164 | #define RTC_CR_TSE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 13165 | #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13166 | #define RTC_CR_TSE RTC_CR_TSE_Msk |
| AnnaBridge | 172:65be27845400 | 13167 | #define RTC_CR_WUTE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 13168 | #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13169 | #define RTC_CR_WUTE RTC_CR_WUTE_Msk |
| AnnaBridge | 172:65be27845400 | 13170 | #define RTC_CR_ALRBE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 13171 | #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13172 | #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk |
| AnnaBridge | 172:65be27845400 | 13173 | #define RTC_CR_ALRAE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13174 | #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13175 | #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk |
| AnnaBridge | 172:65be27845400 | 13176 | #define RTC_CR_FMT_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 13177 | #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13178 | #define RTC_CR_FMT RTC_CR_FMT_Msk |
| AnnaBridge | 172:65be27845400 | 13179 | #define RTC_CR_BYPSHAD_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13180 | #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13181 | #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk |
| AnnaBridge | 172:65be27845400 | 13182 | #define RTC_CR_REFCKON_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13183 | #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13184 | #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk |
| AnnaBridge | 172:65be27845400 | 13185 | #define RTC_CR_TSEDGE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 13186 | #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13187 | #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk |
| AnnaBridge | 172:65be27845400 | 13188 | #define RTC_CR_WUCKSEL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13189 | #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 13190 | #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk |
| AnnaBridge | 172:65be27845400 | 13191 | #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13192 | #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13193 | #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13194 | |
| AnnaBridge | 172:65be27845400 | 13195 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 13196 | #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos |
| AnnaBridge | 172:65be27845400 | 13197 | #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk |
| AnnaBridge | 172:65be27845400 | 13198 | #define RTC_CR_BCK RTC_CR_BKP |
| AnnaBridge | 172:65be27845400 | 13199 | |
| AnnaBridge | 172:65be27845400 | 13200 | /******************** Bits definition for RTC_ISR register ******************/ |
| AnnaBridge | 172:65be27845400 | 13201 | #define RTC_ISR_ITSF_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 13202 | #define RTC_ISR_ITSF_Msk (0x1U << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13203 | #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk |
| AnnaBridge | 172:65be27845400 | 13204 | #define RTC_ISR_RECALPF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13205 | #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13206 | #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk |
| AnnaBridge | 172:65be27845400 | 13207 | #define RTC_ISR_TAMP3F_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 13208 | #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13209 | #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk |
| AnnaBridge | 172:65be27845400 | 13210 | #define RTC_ISR_TAMP2F_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 13211 | #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13212 | #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk |
| AnnaBridge | 172:65be27845400 | 13213 | #define RTC_ISR_TAMP1F_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13214 | #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13215 | #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk |
| AnnaBridge | 172:65be27845400 | 13216 | #define RTC_ISR_TSOVF_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13217 | #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13218 | #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk |
| AnnaBridge | 172:65be27845400 | 13219 | #define RTC_ISR_TSF_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 13220 | #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13221 | #define RTC_ISR_TSF RTC_ISR_TSF_Msk |
| AnnaBridge | 172:65be27845400 | 13222 | #define RTC_ISR_WUTF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 13223 | #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13224 | #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk |
| AnnaBridge | 172:65be27845400 | 13225 | #define RTC_ISR_ALRBF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 13226 | #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13227 | #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk |
| AnnaBridge | 172:65be27845400 | 13228 | #define RTC_ISR_ALRAF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13229 | #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13230 | #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk |
| AnnaBridge | 172:65be27845400 | 13231 | #define RTC_ISR_INIT_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 13232 | #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13233 | #define RTC_ISR_INIT RTC_ISR_INIT_Msk |
| AnnaBridge | 172:65be27845400 | 13234 | #define RTC_ISR_INITF_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 13235 | #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13236 | #define RTC_ISR_INITF RTC_ISR_INITF_Msk |
| AnnaBridge | 172:65be27845400 | 13237 | #define RTC_ISR_RSF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13238 | #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13239 | #define RTC_ISR_RSF RTC_ISR_RSF_Msk |
| AnnaBridge | 172:65be27845400 | 13240 | #define RTC_ISR_INITS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13241 | #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13242 | #define RTC_ISR_INITS RTC_ISR_INITS_Msk |
| AnnaBridge | 172:65be27845400 | 13243 | #define RTC_ISR_SHPF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 13244 | #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13245 | #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk |
| AnnaBridge | 172:65be27845400 | 13246 | #define RTC_ISR_WUTWF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 13247 | #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13248 | #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk |
| AnnaBridge | 172:65be27845400 | 13249 | #define RTC_ISR_ALRBWF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 13250 | #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13251 | #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk |
| AnnaBridge | 172:65be27845400 | 13252 | #define RTC_ISR_ALRAWF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13253 | #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13254 | #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk |
| AnnaBridge | 172:65be27845400 | 13255 | |
| AnnaBridge | 172:65be27845400 | 13256 | /******************** Bits definition for RTC_PRER register *****************/ |
| AnnaBridge | 172:65be27845400 | 13257 | #define RTC_PRER_PREDIV_A_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13258 | #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ |
| AnnaBridge | 172:65be27845400 | 13259 | #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk |
| AnnaBridge | 172:65be27845400 | 13260 | #define RTC_PRER_PREDIV_S_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13261 | #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 172:65be27845400 | 13262 | #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk |
| AnnaBridge | 172:65be27845400 | 13263 | |
| AnnaBridge | 172:65be27845400 | 13264 | /******************** Bits definition for RTC_WUTR register *****************/ |
| AnnaBridge | 172:65be27845400 | 13265 | #define RTC_WUTR_WUT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13266 | #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 13267 | #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk |
| AnnaBridge | 172:65be27845400 | 13268 | |
| AnnaBridge | 172:65be27845400 | 13269 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
| AnnaBridge | 172:65be27845400 | 13270 | #define RTC_ALRMAR_MSK4_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 13271 | #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 13272 | #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk |
| AnnaBridge | 172:65be27845400 | 13273 | #define RTC_ALRMAR_WDSEL_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 13274 | #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 13275 | #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk |
| AnnaBridge | 172:65be27845400 | 13276 | #define RTC_ALRMAR_DT_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 13277 | #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 13278 | #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk |
| AnnaBridge | 172:65be27845400 | 13279 | #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 13280 | #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 13281 | #define RTC_ALRMAR_DU_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 13282 | #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 13283 | #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk |
| AnnaBridge | 172:65be27845400 | 13284 | #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 13285 | #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 13286 | #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 13287 | #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 13288 | #define RTC_ALRMAR_MSK3_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 13289 | #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 13290 | #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk |
| AnnaBridge | 172:65be27845400 | 13291 | #define RTC_ALRMAR_PM_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 13292 | #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13293 | #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk |
| AnnaBridge | 172:65be27845400 | 13294 | #define RTC_ALRMAR_HT_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13295 | #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 13296 | #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk |
| AnnaBridge | 172:65be27845400 | 13297 | #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13298 | #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13299 | #define RTC_ALRMAR_HU_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13300 | #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 13301 | #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk |
| AnnaBridge | 172:65be27845400 | 13302 | #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13303 | #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13304 | #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13305 | #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13306 | #define RTC_ALRMAR_MSK2_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 13307 | #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13308 | #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk |
| AnnaBridge | 172:65be27845400 | 13309 | #define RTC_ALRMAR_MNT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13310 | #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 13311 | #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk |
| AnnaBridge | 172:65be27845400 | 13312 | #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13313 | #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13314 | #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13315 | #define RTC_ALRMAR_MNU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13316 | #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13317 | #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk |
| AnnaBridge | 172:65be27845400 | 13318 | #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13319 | #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13320 | #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13321 | #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13322 | #define RTC_ALRMAR_MSK1_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 13323 | #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13324 | #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk |
| AnnaBridge | 172:65be27845400 | 13325 | #define RTC_ALRMAR_ST_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13326 | #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 13327 | #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk |
| AnnaBridge | 172:65be27845400 | 13328 | #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13329 | #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13330 | #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13331 | #define RTC_ALRMAR_SU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13332 | #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 13333 | #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk |
| AnnaBridge | 172:65be27845400 | 13334 | #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13335 | #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13336 | #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13337 | #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13338 | |
| AnnaBridge | 172:65be27845400 | 13339 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
| AnnaBridge | 172:65be27845400 | 13340 | #define RTC_ALRMBR_MSK4_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 13341 | #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 13342 | #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk |
| AnnaBridge | 172:65be27845400 | 13343 | #define RTC_ALRMBR_WDSEL_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 13344 | #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 13345 | #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk |
| AnnaBridge | 172:65be27845400 | 13346 | #define RTC_ALRMBR_DT_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 13347 | #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 13348 | #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk |
| AnnaBridge | 172:65be27845400 | 13349 | #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 13350 | #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 13351 | #define RTC_ALRMBR_DU_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 13352 | #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 13353 | #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk |
| AnnaBridge | 172:65be27845400 | 13354 | #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 13355 | #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 13356 | #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 13357 | #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 13358 | #define RTC_ALRMBR_MSK3_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 13359 | #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 13360 | #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk |
| AnnaBridge | 172:65be27845400 | 13361 | #define RTC_ALRMBR_PM_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 13362 | #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13363 | #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk |
| AnnaBridge | 172:65be27845400 | 13364 | #define RTC_ALRMBR_HT_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13365 | #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 13366 | #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk |
| AnnaBridge | 172:65be27845400 | 13367 | #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13368 | #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13369 | #define RTC_ALRMBR_HU_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13370 | #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 13371 | #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk |
| AnnaBridge | 172:65be27845400 | 13372 | #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13373 | #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13374 | #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13375 | #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13376 | #define RTC_ALRMBR_MSK2_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 13377 | #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13378 | #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk |
| AnnaBridge | 172:65be27845400 | 13379 | #define RTC_ALRMBR_MNT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13380 | #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 13381 | #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk |
| AnnaBridge | 172:65be27845400 | 13382 | #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13383 | #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13384 | #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13385 | #define RTC_ALRMBR_MNU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13386 | #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13387 | #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk |
| AnnaBridge | 172:65be27845400 | 13388 | #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13389 | #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13390 | #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13391 | #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13392 | #define RTC_ALRMBR_MSK1_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 13393 | #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13394 | #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk |
| AnnaBridge | 172:65be27845400 | 13395 | #define RTC_ALRMBR_ST_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13396 | #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 13397 | #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk |
| AnnaBridge | 172:65be27845400 | 13398 | #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13399 | #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13400 | #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13401 | #define RTC_ALRMBR_SU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13402 | #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 13403 | #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk |
| AnnaBridge | 172:65be27845400 | 13404 | #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13405 | #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13406 | #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13407 | #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13408 | |
| AnnaBridge | 172:65be27845400 | 13409 | /******************** Bits definition for RTC_WPR register ******************/ |
| AnnaBridge | 172:65be27845400 | 13410 | #define RTC_WPR_KEY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13411 | #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 13412 | #define RTC_WPR_KEY RTC_WPR_KEY_Msk |
| AnnaBridge | 172:65be27845400 | 13413 | |
| AnnaBridge | 172:65be27845400 | 13414 | /******************** Bits definition for RTC_SSR register ******************/ |
| AnnaBridge | 172:65be27845400 | 13415 | #define RTC_SSR_SS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13416 | #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 13417 | #define RTC_SSR_SS RTC_SSR_SS_Msk |
| AnnaBridge | 172:65be27845400 | 13418 | |
| AnnaBridge | 172:65be27845400 | 13419 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
| AnnaBridge | 172:65be27845400 | 13420 | #define RTC_SHIFTR_SUBFS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13421 | #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 172:65be27845400 | 13422 | #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk |
| AnnaBridge | 172:65be27845400 | 13423 | #define RTC_SHIFTR_ADD1S_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 13424 | #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 13425 | #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk |
| AnnaBridge | 172:65be27845400 | 13426 | |
| AnnaBridge | 172:65be27845400 | 13427 | /******************** Bits definition for RTC_TSTR register *****************/ |
| AnnaBridge | 172:65be27845400 | 13428 | #define RTC_TSTR_PM_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 13429 | #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13430 | #define RTC_TSTR_PM RTC_TSTR_PM_Msk |
| AnnaBridge | 172:65be27845400 | 13431 | #define RTC_TSTR_HT_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13432 | #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 13433 | #define RTC_TSTR_HT RTC_TSTR_HT_Msk |
| AnnaBridge | 172:65be27845400 | 13434 | #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13435 | #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13436 | #define RTC_TSTR_HU_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13437 | #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 13438 | #define RTC_TSTR_HU RTC_TSTR_HU_Msk |
| AnnaBridge | 172:65be27845400 | 13439 | #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13440 | #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13441 | #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13442 | #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13443 | #define RTC_TSTR_MNT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13444 | #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 13445 | #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk |
| AnnaBridge | 172:65be27845400 | 13446 | #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13447 | #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13448 | #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13449 | #define RTC_TSTR_MNU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13450 | #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13451 | #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk |
| AnnaBridge | 172:65be27845400 | 13452 | #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13453 | #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13454 | #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13455 | #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13456 | #define RTC_TSTR_ST_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13457 | #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 13458 | #define RTC_TSTR_ST RTC_TSTR_ST_Msk |
| AnnaBridge | 172:65be27845400 | 13459 | #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13460 | #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13461 | #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13462 | #define RTC_TSTR_SU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13463 | #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 13464 | #define RTC_TSTR_SU RTC_TSTR_SU_Msk |
| AnnaBridge | 172:65be27845400 | 13465 | #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13466 | #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13467 | #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13468 | #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13469 | |
| AnnaBridge | 172:65be27845400 | 13470 | /******************** Bits definition for RTC_TSDR register *****************/ |
| AnnaBridge | 172:65be27845400 | 13471 | #define RTC_TSDR_WDU_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13472 | #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 172:65be27845400 | 13473 | #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk |
| AnnaBridge | 172:65be27845400 | 13474 | #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13475 | #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13476 | #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13477 | #define RTC_TSDR_MT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13478 | #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13479 | #define RTC_TSDR_MT RTC_TSDR_MT_Msk |
| AnnaBridge | 172:65be27845400 | 13480 | #define RTC_TSDR_MU_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13481 | #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13482 | #define RTC_TSDR_MU RTC_TSDR_MU_Msk |
| AnnaBridge | 172:65be27845400 | 13483 | #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13484 | #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13485 | #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13486 | #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13487 | #define RTC_TSDR_DT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13488 | #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 13489 | #define RTC_TSDR_DT RTC_TSDR_DT_Msk |
| AnnaBridge | 172:65be27845400 | 13490 | #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13491 | #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13492 | #define RTC_TSDR_DU_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13493 | #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 13494 | #define RTC_TSDR_DU RTC_TSDR_DU_Msk |
| AnnaBridge | 172:65be27845400 | 13495 | #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13496 | #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13497 | #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13498 | #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13499 | |
| AnnaBridge | 172:65be27845400 | 13500 | /******************** Bits definition for RTC_TSSSR register ****************/ |
| AnnaBridge | 172:65be27845400 | 13501 | #define RTC_TSSSR_SS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13502 | #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 13503 | #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk |
| AnnaBridge | 172:65be27845400 | 13504 | |
| AnnaBridge | 172:65be27845400 | 13505 | /******************** Bits definition for RTC_CAL register *****************/ |
| AnnaBridge | 172:65be27845400 | 13506 | #define RTC_CALR_CALP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 13507 | #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13508 | #define RTC_CALR_CALP RTC_CALR_CALP_Msk |
| AnnaBridge | 172:65be27845400 | 13509 | #define RTC_CALR_CALW8_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 13510 | #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13511 | #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk |
| AnnaBridge | 172:65be27845400 | 13512 | #define RTC_CALR_CALW16_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13513 | #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13514 | #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk |
| AnnaBridge | 172:65be27845400 | 13515 | #define RTC_CALR_CALM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13516 | #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 172:65be27845400 | 13517 | #define RTC_CALR_CALM RTC_CALR_CALM_Msk |
| AnnaBridge | 172:65be27845400 | 13518 | #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13519 | #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13520 | #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13521 | #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13522 | #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13523 | #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13524 | #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13525 | #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13526 | #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13527 | |
| AnnaBridge | 172:65be27845400 | 13528 | /******************** Bits definition for RTC_TAMPCR register ***************/ |
| AnnaBridge | 172:65be27845400 | 13529 | #define RTC_TAMPCR_TAMP3MF_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 13530 | #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 13531 | #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk |
| AnnaBridge | 172:65be27845400 | 13532 | #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 13533 | #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 13534 | #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk |
| AnnaBridge | 172:65be27845400 | 13535 | #define RTC_TAMPCR_TAMP3IE_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 13536 | #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 13537 | #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk |
| AnnaBridge | 172:65be27845400 | 13538 | #define RTC_TAMPCR_TAMP2MF_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 13539 | #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 13540 | #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk |
| AnnaBridge | 172:65be27845400 | 13541 | #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13542 | #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 13543 | #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk |
| AnnaBridge | 172:65be27845400 | 13544 | #define RTC_TAMPCR_TAMP2IE_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 13545 | #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13546 | #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk |
| AnnaBridge | 172:65be27845400 | 13547 | #define RTC_TAMPCR_TAMP1MF_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 13548 | #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13549 | #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk |
| AnnaBridge | 172:65be27845400 | 13550 | #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 13551 | #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13552 | #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk |
| AnnaBridge | 172:65be27845400 | 13553 | #define RTC_TAMPCR_TAMP1IE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13554 | #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13555 | #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk |
| AnnaBridge | 172:65be27845400 | 13556 | #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 13557 | #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13558 | #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk |
| AnnaBridge | 172:65be27845400 | 13559 | #define RTC_TAMPCR_TAMPPRCH_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13560 | #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 172:65be27845400 | 13561 | #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk |
| AnnaBridge | 172:65be27845400 | 13562 | #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13563 | #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13564 | #define RTC_TAMPCR_TAMPFLT_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 13565 | #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 172:65be27845400 | 13566 | #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk |
| AnnaBridge | 172:65be27845400 | 13567 | #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13568 | #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13569 | #define RTC_TAMPCR_TAMPFREQ_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13570 | #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 13571 | #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk |
| AnnaBridge | 172:65be27845400 | 13572 | #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13573 | #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13574 | #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13575 | #define RTC_TAMPCR_TAMPTS_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 13576 | #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13577 | #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk |
| AnnaBridge | 172:65be27845400 | 13578 | #define RTC_TAMPCR_TAMP3TRG_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 13579 | #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13580 | #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk |
| AnnaBridge | 172:65be27845400 | 13581 | #define RTC_TAMPCR_TAMP3E_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13582 | #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13583 | #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk |
| AnnaBridge | 172:65be27845400 | 13584 | #define RTC_TAMPCR_TAMP2TRG_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13585 | #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13586 | #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk |
| AnnaBridge | 172:65be27845400 | 13587 | #define RTC_TAMPCR_TAMP2E_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 13588 | #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13589 | #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk |
| AnnaBridge | 172:65be27845400 | 13590 | #define RTC_TAMPCR_TAMPIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 13591 | #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13592 | #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk |
| AnnaBridge | 172:65be27845400 | 13593 | #define RTC_TAMPCR_TAMP1TRG_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 13594 | #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13595 | #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk |
| AnnaBridge | 172:65be27845400 | 13596 | #define RTC_TAMPCR_TAMP1E_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13597 | #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13598 | #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk |
| AnnaBridge | 172:65be27845400 | 13599 | |
| AnnaBridge | 172:65be27845400 | 13600 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
| AnnaBridge | 172:65be27845400 | 13601 | #define RTC_ALRMASSR_MASKSS_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 13602 | #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 13603 | #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk |
| AnnaBridge | 172:65be27845400 | 13604 | #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 13605 | #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 13606 | #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 13607 | #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 13608 | #define RTC_ALRMASSR_SS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13609 | #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 172:65be27845400 | 13610 | #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk |
| AnnaBridge | 172:65be27845400 | 13611 | |
| AnnaBridge | 172:65be27845400 | 13612 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
| AnnaBridge | 172:65be27845400 | 13613 | #define RTC_ALRMBSSR_MASKSS_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 13614 | #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 13615 | #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk |
| AnnaBridge | 172:65be27845400 | 13616 | #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 13617 | #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 13618 | #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 13619 | #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 13620 | #define RTC_ALRMBSSR_SS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13621 | #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ |
| AnnaBridge | 172:65be27845400 | 13622 | #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk |
| AnnaBridge | 172:65be27845400 | 13623 | |
| AnnaBridge | 172:65be27845400 | 13624 | /******************** Bits definition for RTC_0R register *******************/ |
| AnnaBridge | 172:65be27845400 | 13625 | #define RTC_OR_OUT_RMP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 13626 | #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13627 | #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk |
| AnnaBridge | 172:65be27845400 | 13628 | #define RTC_OR_ALARMOUTTYPE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13629 | #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13630 | #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk |
| AnnaBridge | 172:65be27845400 | 13631 | |
| AnnaBridge | 172:65be27845400 | 13632 | |
| AnnaBridge | 172:65be27845400 | 13633 | /******************** Bits definition for RTC_BKP0R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13634 | #define RTC_BKP0R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13635 | #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13636 | #define RTC_BKP0R RTC_BKP0R_Msk |
| AnnaBridge | 172:65be27845400 | 13637 | |
| AnnaBridge | 172:65be27845400 | 13638 | /******************** Bits definition for RTC_BKP1R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13639 | #define RTC_BKP1R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13640 | #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13641 | #define RTC_BKP1R RTC_BKP1R_Msk |
| AnnaBridge | 172:65be27845400 | 13642 | |
| AnnaBridge | 172:65be27845400 | 13643 | /******************** Bits definition for RTC_BKP2R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13644 | #define RTC_BKP2R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13645 | #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13646 | #define RTC_BKP2R RTC_BKP2R_Msk |
| AnnaBridge | 172:65be27845400 | 13647 | |
| AnnaBridge | 172:65be27845400 | 13648 | /******************** Bits definition for RTC_BKP3R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13649 | #define RTC_BKP3R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13650 | #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13651 | #define RTC_BKP3R RTC_BKP3R_Msk |
| AnnaBridge | 172:65be27845400 | 13652 | |
| AnnaBridge | 172:65be27845400 | 13653 | /******************** Bits definition for RTC_BKP4R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13654 | #define RTC_BKP4R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13655 | #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13656 | #define RTC_BKP4R RTC_BKP4R_Msk |
| AnnaBridge | 172:65be27845400 | 13657 | |
| AnnaBridge | 172:65be27845400 | 13658 | /******************** Bits definition for RTC_BKP5R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13659 | #define RTC_BKP5R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13660 | #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13661 | #define RTC_BKP5R RTC_BKP5R_Msk |
| AnnaBridge | 172:65be27845400 | 13662 | |
| AnnaBridge | 172:65be27845400 | 13663 | /******************** Bits definition for RTC_BKP6R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13664 | #define RTC_BKP6R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13665 | #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13666 | #define RTC_BKP6R RTC_BKP6R_Msk |
| AnnaBridge | 172:65be27845400 | 13667 | |
| AnnaBridge | 172:65be27845400 | 13668 | /******************** Bits definition for RTC_BKP7R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13669 | #define RTC_BKP7R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13670 | #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13671 | #define RTC_BKP7R RTC_BKP7R_Msk |
| AnnaBridge | 172:65be27845400 | 13672 | |
| AnnaBridge | 172:65be27845400 | 13673 | /******************** Bits definition for RTC_BKP8R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13674 | #define RTC_BKP8R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13675 | #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13676 | #define RTC_BKP8R RTC_BKP8R_Msk |
| AnnaBridge | 172:65be27845400 | 13677 | |
| AnnaBridge | 172:65be27845400 | 13678 | /******************** Bits definition for RTC_BKP9R register ****************/ |
| AnnaBridge | 172:65be27845400 | 13679 | #define RTC_BKP9R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13680 | #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13681 | #define RTC_BKP9R RTC_BKP9R_Msk |
| AnnaBridge | 172:65be27845400 | 13682 | |
| AnnaBridge | 172:65be27845400 | 13683 | /******************** Bits definition for RTC_BKP10R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13684 | #define RTC_BKP10R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13685 | #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13686 | #define RTC_BKP10R RTC_BKP10R_Msk |
| AnnaBridge | 172:65be27845400 | 13687 | |
| AnnaBridge | 172:65be27845400 | 13688 | /******************** Bits definition for RTC_BKP11R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13689 | #define RTC_BKP11R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13690 | #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13691 | #define RTC_BKP11R RTC_BKP11R_Msk |
| AnnaBridge | 172:65be27845400 | 13692 | |
| AnnaBridge | 172:65be27845400 | 13693 | /******************** Bits definition for RTC_BKP12R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13694 | #define RTC_BKP12R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13695 | #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13696 | #define RTC_BKP12R RTC_BKP12R_Msk |
| AnnaBridge | 172:65be27845400 | 13697 | |
| AnnaBridge | 172:65be27845400 | 13698 | /******************** Bits definition for RTC_BKP13R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13699 | #define RTC_BKP13R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13700 | #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13701 | #define RTC_BKP13R RTC_BKP13R_Msk |
| AnnaBridge | 172:65be27845400 | 13702 | |
| AnnaBridge | 172:65be27845400 | 13703 | /******************** Bits definition for RTC_BKP14R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13704 | #define RTC_BKP14R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13705 | #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13706 | #define RTC_BKP14R RTC_BKP14R_Msk |
| AnnaBridge | 172:65be27845400 | 13707 | |
| AnnaBridge | 172:65be27845400 | 13708 | /******************** Bits definition for RTC_BKP15R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13709 | #define RTC_BKP15R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13710 | #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13711 | #define RTC_BKP15R RTC_BKP15R_Msk |
| AnnaBridge | 172:65be27845400 | 13712 | |
| AnnaBridge | 172:65be27845400 | 13713 | /******************** Bits definition for RTC_BKP16R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13714 | #define RTC_BKP16R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13715 | #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13716 | #define RTC_BKP16R RTC_BKP16R_Msk |
| AnnaBridge | 172:65be27845400 | 13717 | |
| AnnaBridge | 172:65be27845400 | 13718 | /******************** Bits definition for RTC_BKP17R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13719 | #define RTC_BKP17R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13720 | #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13721 | #define RTC_BKP17R RTC_BKP17R_Msk |
| AnnaBridge | 172:65be27845400 | 13722 | |
| AnnaBridge | 172:65be27845400 | 13723 | /******************** Bits definition for RTC_BKP18R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13724 | #define RTC_BKP18R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13725 | #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13726 | #define RTC_BKP18R RTC_BKP18R_Msk |
| AnnaBridge | 172:65be27845400 | 13727 | |
| AnnaBridge | 172:65be27845400 | 13728 | /******************** Bits definition for RTC_BKP19R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13729 | #define RTC_BKP19R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13730 | #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13731 | #define RTC_BKP19R RTC_BKP19R_Msk |
| AnnaBridge | 172:65be27845400 | 13732 | |
| AnnaBridge | 172:65be27845400 | 13733 | /******************** Bits definition for RTC_BKP20R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13734 | #define RTC_BKP20R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13735 | #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13736 | #define RTC_BKP20R RTC_BKP20R_Msk |
| AnnaBridge | 172:65be27845400 | 13737 | |
| AnnaBridge | 172:65be27845400 | 13738 | /******************** Bits definition for RTC_BKP21R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13739 | #define RTC_BKP21R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13740 | #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13741 | #define RTC_BKP21R RTC_BKP21R_Msk |
| AnnaBridge | 172:65be27845400 | 13742 | |
| AnnaBridge | 172:65be27845400 | 13743 | /******************** Bits definition for RTC_BKP22R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13744 | #define RTC_BKP22R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13745 | #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13746 | #define RTC_BKP22R RTC_BKP22R_Msk |
| AnnaBridge | 172:65be27845400 | 13747 | |
| AnnaBridge | 172:65be27845400 | 13748 | /******************** Bits definition for RTC_BKP23R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13749 | #define RTC_BKP23R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13750 | #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13751 | #define RTC_BKP23R RTC_BKP23R_Msk |
| AnnaBridge | 172:65be27845400 | 13752 | |
| AnnaBridge | 172:65be27845400 | 13753 | /******************** Bits definition for RTC_BKP24R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13754 | #define RTC_BKP24R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13755 | #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13756 | #define RTC_BKP24R RTC_BKP24R_Msk |
| AnnaBridge | 172:65be27845400 | 13757 | |
| AnnaBridge | 172:65be27845400 | 13758 | /******************** Bits definition for RTC_BKP25R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13759 | #define RTC_BKP25R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13760 | #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13761 | #define RTC_BKP25R RTC_BKP25R_Msk |
| AnnaBridge | 172:65be27845400 | 13762 | |
| AnnaBridge | 172:65be27845400 | 13763 | /******************** Bits definition for RTC_BKP26R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13764 | #define RTC_BKP26R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13765 | #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13766 | #define RTC_BKP26R RTC_BKP26R_Msk |
| AnnaBridge | 172:65be27845400 | 13767 | |
| AnnaBridge | 172:65be27845400 | 13768 | /******************** Bits definition for RTC_BKP27R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13769 | #define RTC_BKP27R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13770 | #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13771 | #define RTC_BKP27R RTC_BKP27R_Msk |
| AnnaBridge | 172:65be27845400 | 13772 | |
| AnnaBridge | 172:65be27845400 | 13773 | /******************** Bits definition for RTC_BKP28R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13774 | #define RTC_BKP28R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13775 | #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13776 | #define RTC_BKP28R RTC_BKP28R_Msk |
| AnnaBridge | 172:65be27845400 | 13777 | |
| AnnaBridge | 172:65be27845400 | 13778 | /******************** Bits definition for RTC_BKP29R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13779 | #define RTC_BKP29R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13780 | #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13781 | #define RTC_BKP29R RTC_BKP29R_Msk |
| AnnaBridge | 172:65be27845400 | 13782 | |
| AnnaBridge | 172:65be27845400 | 13783 | /******************** Bits definition for RTC_BKP30R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13784 | #define RTC_BKP30R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13785 | #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13786 | #define RTC_BKP30R RTC_BKP30R_Msk |
| AnnaBridge | 172:65be27845400 | 13787 | |
| AnnaBridge | 172:65be27845400 | 13788 | /******************** Bits definition for RTC_BKP31R register ***************/ |
| AnnaBridge | 172:65be27845400 | 13789 | #define RTC_BKP31R_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13790 | #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 13791 | #define RTC_BKP31R RTC_BKP31R_Msk |
| AnnaBridge | 172:65be27845400 | 13792 | |
| AnnaBridge | 172:65be27845400 | 13793 | /******************** Number of backup registers ******************************/ |
| AnnaBridge | 172:65be27845400 | 13794 | #define RTC_BKP_NUMBER 32U |
| AnnaBridge | 172:65be27845400 | 13795 | |
| AnnaBridge | 172:65be27845400 | 13796 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 13797 | /* */ |
| AnnaBridge | 172:65be27845400 | 13798 | /* Serial Audio Interface */ |
| AnnaBridge | 172:65be27845400 | 13799 | /* */ |
| AnnaBridge | 172:65be27845400 | 13800 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 13801 | /******************** Bit definition for SAI_GCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13802 | #define SAI_GCR_SYNCIN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13803 | #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 13804 | #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ |
| AnnaBridge | 172:65be27845400 | 13805 | #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13806 | #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13807 | |
| AnnaBridge | 172:65be27845400 | 13808 | #define SAI_GCR_SYNCOUT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13809 | #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 13810 | #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ |
| AnnaBridge | 172:65be27845400 | 13811 | #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13812 | #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13813 | |
| AnnaBridge | 172:65be27845400 | 13814 | /******************* Bit definition for SAI_xCR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 13815 | #define SAI_xCR1_MODE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13816 | #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 13817 | #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */ |
| AnnaBridge | 172:65be27845400 | 13818 | #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13819 | #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13820 | |
| AnnaBridge | 172:65be27845400 | 13821 | #define SAI_xCR1_PRTCFG_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 13822 | #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 13823 | #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */ |
| AnnaBridge | 172:65be27845400 | 13824 | #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13825 | #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13826 | |
| AnnaBridge | 172:65be27845400 | 13827 | #define SAI_xCR1_DS_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13828 | #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 172:65be27845400 | 13829 | #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */ |
| AnnaBridge | 172:65be27845400 | 13830 | #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13831 | #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13832 | #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13833 | |
| AnnaBridge | 172:65be27845400 | 13834 | #define SAI_xCR1_LSBFIRST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13835 | #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13836 | #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */ |
| AnnaBridge | 172:65be27845400 | 13837 | #define SAI_xCR1_CKSTR_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 13838 | #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13839 | #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */ |
| AnnaBridge | 172:65be27845400 | 13840 | |
| AnnaBridge | 172:65be27845400 | 13841 | #define SAI_xCR1_SYNCEN_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 13842 | #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 13843 | #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */ |
| AnnaBridge | 172:65be27845400 | 13844 | #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13845 | #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13846 | |
| AnnaBridge | 172:65be27845400 | 13847 | #define SAI_xCR1_MONO_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 13848 | #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13849 | #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */ |
| AnnaBridge | 172:65be27845400 | 13850 | #define SAI_xCR1_OUTDRIV_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13851 | #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13852 | #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */ |
| AnnaBridge | 172:65be27845400 | 13853 | #define SAI_xCR1_SAIEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13854 | #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13855 | #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */ |
| AnnaBridge | 172:65be27845400 | 13856 | #define SAI_xCR1_DMAEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 13857 | #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13858 | #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */ |
| AnnaBridge | 172:65be27845400 | 13859 | #define SAI_xCR1_NOMCK_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 13860 | #define SAI_xCR1_NOMCK_Msk (0x1U << SAI_xCR1_NOMCK_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 13861 | #define SAI_xCR1_NOMCK SAI_xCR1_NOMCK_Msk /*!<No Divider Configuration */ |
| AnnaBridge | 172:65be27845400 | 13862 | |
| AnnaBridge | 172:65be27845400 | 13863 | #define SAI_xCR1_MCKDIV_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 13864 | #define SAI_xCR1_MCKDIV_Msk (0x3FU << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */ |
| AnnaBridge | 172:65be27845400 | 13865 | #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */ |
| AnnaBridge | 172:65be27845400 | 13866 | #define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */ |
| AnnaBridge | 172:65be27845400 | 13867 | #define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */ |
| AnnaBridge | 172:65be27845400 | 13868 | #define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */ |
| AnnaBridge | 172:65be27845400 | 13869 | #define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */ |
| AnnaBridge | 172:65be27845400 | 13870 | #define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */ |
| AnnaBridge | 172:65be27845400 | 13871 | #define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */ |
| AnnaBridge | 172:65be27845400 | 13872 | |
| AnnaBridge | 172:65be27845400 | 13873 | #define SAI_xCR1_OSR_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 13874 | #define SAI_xCR1_OSR_Msk (0x1U << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 13875 | #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */ |
| AnnaBridge | 172:65be27845400 | 13876 | |
| AnnaBridge | 172:65be27845400 | 13877 | /******************* Bit definition for SAI_xCR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 13878 | #define SAI_xCR2_FTH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13879 | #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 13880 | #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */ |
| AnnaBridge | 172:65be27845400 | 13881 | #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13882 | #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13883 | #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13884 | |
| AnnaBridge | 172:65be27845400 | 13885 | #define SAI_xCR2_FFLUSH_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 13886 | #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13887 | #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */ |
| AnnaBridge | 172:65be27845400 | 13888 | #define SAI_xCR2_TRIS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13889 | #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13890 | #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */ |
| AnnaBridge | 172:65be27845400 | 13891 | #define SAI_xCR2_MUTE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13892 | #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13893 | #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */ |
| AnnaBridge | 172:65be27845400 | 13894 | #define SAI_xCR2_MUTEVAL_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 13895 | #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13896 | #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */ |
| AnnaBridge | 172:65be27845400 | 13897 | |
| AnnaBridge | 172:65be27845400 | 13898 | |
| AnnaBridge | 172:65be27845400 | 13899 | #define SAI_xCR2_MUTECNT_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 13900 | #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */ |
| AnnaBridge | 172:65be27845400 | 13901 | #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */ |
| AnnaBridge | 172:65be27845400 | 13902 | #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13903 | #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13904 | #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13905 | #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13906 | #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13907 | #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13908 | |
| AnnaBridge | 172:65be27845400 | 13909 | #define SAI_xCR2_CPL_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 13910 | #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13911 | #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */ |
| AnnaBridge | 172:65be27845400 | 13912 | #define SAI_xCR2_COMP_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 13913 | #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 13914 | #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */ |
| AnnaBridge | 172:65be27845400 | 13915 | #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13916 | #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 13917 | |
| AnnaBridge | 172:65be27845400 | 13918 | |
| AnnaBridge | 172:65be27845400 | 13919 | /****************** Bit definition for SAI_xFRCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13920 | #define SAI_xFRCR_FRL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13921 | #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 13922 | #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */ |
| AnnaBridge | 172:65be27845400 | 13923 | #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13924 | #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13925 | #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13926 | #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13927 | #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13928 | #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13929 | #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13930 | #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13931 | |
| AnnaBridge | 172:65be27845400 | 13932 | #define SAI_xFRCR_FSALL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13933 | #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */ |
| AnnaBridge | 172:65be27845400 | 13934 | #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */ |
| AnnaBridge | 172:65be27845400 | 13935 | #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13936 | #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13937 | #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13938 | #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13939 | #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 13940 | #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 13941 | #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 13942 | |
| AnnaBridge | 172:65be27845400 | 13943 | #define SAI_xFRCR_FSDEF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13944 | #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 13945 | #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */ |
| AnnaBridge | 172:65be27845400 | 13946 | #define SAI_xFRCR_FSPOL_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 13947 | #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 13948 | #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */ |
| AnnaBridge | 172:65be27845400 | 13949 | #define SAI_xFRCR_FSOFF_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 13950 | #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 13951 | #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */ |
| AnnaBridge | 172:65be27845400 | 13952 | |
| AnnaBridge | 172:65be27845400 | 13953 | /****************** Bit definition for SAI_xSLOTR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13954 | #define SAI_xSLOTR_FBOFF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13955 | #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 13956 | #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */ |
| AnnaBridge | 172:65be27845400 | 13957 | #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13958 | #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13959 | #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13960 | #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13961 | #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13962 | |
| AnnaBridge | 172:65be27845400 | 13963 | #define SAI_xSLOTR_SLOTSZ_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 13964 | #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 13965 | #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */ |
| AnnaBridge | 172:65be27845400 | 13966 | #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 13967 | #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 13968 | |
| AnnaBridge | 172:65be27845400 | 13969 | #define SAI_xSLOTR_NBSLOT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 13970 | #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 13971 | #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ |
| AnnaBridge | 172:65be27845400 | 13972 | #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 13973 | #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 13974 | #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 13975 | #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 13976 | |
| AnnaBridge | 172:65be27845400 | 13977 | #define SAI_xSLOTR_SLOTEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 13978 | #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 13979 | #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */ |
| AnnaBridge | 172:65be27845400 | 13980 | |
| AnnaBridge | 172:65be27845400 | 13981 | /******************* Bit definition for SAI_xIMR register *******************/ |
| AnnaBridge | 172:65be27845400 | 13982 | #define SAI_xIMR_OVRUDRIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 13983 | #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 13984 | #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 13985 | #define SAI_xIMR_MUTEDETIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 13986 | #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 13987 | #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 13988 | #define SAI_xIMR_WCKCFGIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 13989 | #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 13990 | #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 13991 | #define SAI_xIMR_FREQIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 13992 | #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 13993 | #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 13994 | #define SAI_xIMR_CNRDYIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 13995 | #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 13996 | #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 13997 | #define SAI_xIMR_AFSDETIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 13998 | #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 13999 | #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 14000 | #define SAI_xIMR_LFSDETIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14001 | #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14002 | #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 14003 | |
| AnnaBridge | 172:65be27845400 | 14004 | /******************** Bit definition for SAI_xSR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14005 | #define SAI_xSR_OVRUDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14006 | #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14007 | #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */ |
| AnnaBridge | 172:65be27845400 | 14008 | #define SAI_xSR_MUTEDET_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14009 | #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14010 | #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */ |
| AnnaBridge | 172:65be27845400 | 14011 | #define SAI_xSR_WCKCFG_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14012 | #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14013 | #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */ |
| AnnaBridge | 172:65be27845400 | 14014 | #define SAI_xSR_FREQ_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14015 | #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14016 | #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */ |
| AnnaBridge | 172:65be27845400 | 14017 | #define SAI_xSR_CNRDY_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14018 | #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14019 | #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */ |
| AnnaBridge | 172:65be27845400 | 14020 | #define SAI_xSR_AFSDET_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14021 | #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14022 | #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */ |
| AnnaBridge | 172:65be27845400 | 14023 | #define SAI_xSR_LFSDET_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14024 | #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14025 | #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */ |
| AnnaBridge | 172:65be27845400 | 14026 | |
| AnnaBridge | 172:65be27845400 | 14027 | #define SAI_xSR_FLVL_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14028 | #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 14029 | #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */ |
| AnnaBridge | 172:65be27845400 | 14030 | #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14031 | #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14032 | #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14033 | |
| AnnaBridge | 172:65be27845400 | 14034 | /****************** Bit definition for SAI_xCLRFR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14035 | #define SAI_xCLRFR_COVRUDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14036 | #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14037 | #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */ |
| AnnaBridge | 172:65be27845400 | 14038 | #define SAI_xCLRFR_CMUTEDET_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14039 | #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14040 | #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */ |
| AnnaBridge | 172:65be27845400 | 14041 | #define SAI_xCLRFR_CWCKCFG_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14042 | #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14043 | #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */ |
| AnnaBridge | 172:65be27845400 | 14044 | #define SAI_xCLRFR_CFREQ_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14045 | #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14046 | #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */ |
| AnnaBridge | 172:65be27845400 | 14047 | #define SAI_xCLRFR_CCNRDY_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14048 | #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14049 | #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */ |
| AnnaBridge | 172:65be27845400 | 14050 | #define SAI_xCLRFR_CAFSDET_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14051 | #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14052 | #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */ |
| AnnaBridge | 172:65be27845400 | 14053 | #define SAI_xCLRFR_CLFSDET_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14054 | #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14055 | #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */ |
| AnnaBridge | 172:65be27845400 | 14056 | |
| AnnaBridge | 172:65be27845400 | 14057 | /****************** Bit definition for SAI_xDR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14058 | #define SAI_xDR_DATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14059 | #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14060 | #define SAI_xDR_DATA SAI_xDR_DATA_Msk |
| AnnaBridge | 172:65be27845400 | 14061 | |
| AnnaBridge | 172:65be27845400 | 14062 | /****************** Bit definition for SAI_PDMCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14063 | #define SAI_PDMCR_PDMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14064 | #define SAI_PDMCR_PDMEN_Msk (0x1U << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14065 | #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */ |
| AnnaBridge | 172:65be27845400 | 14066 | |
| AnnaBridge | 172:65be27845400 | 14067 | #define SAI_PDMCR_MICNBR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14068 | #define SAI_PDMCR_MICNBR_Msk (0x3U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 14069 | #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */ |
| AnnaBridge | 172:65be27845400 | 14070 | #define SAI_PDMCR_MICNBR_0 (0x1U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14071 | #define SAI_PDMCR_MICNBR_1 (0x2U << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14072 | |
| AnnaBridge | 172:65be27845400 | 14073 | #define SAI_PDMCR_CKEN1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14074 | #define SAI_PDMCR_CKEN1_Msk (0x1U << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14075 | #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */ |
| AnnaBridge | 172:65be27845400 | 14076 | #define SAI_PDMCR_CKEN2_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14077 | #define SAI_PDMCR_CKEN2_Msk (0x1U << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14078 | #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */ |
| AnnaBridge | 172:65be27845400 | 14079 | #define SAI_PDMCR_CKEN3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14080 | #define SAI_PDMCR_CKEN3_Msk (0x1U << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14081 | #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */ |
| AnnaBridge | 172:65be27845400 | 14082 | #define SAI_PDMCR_CKEN4_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14083 | #define SAI_PDMCR_CKEN4_Msk (0x1U << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14084 | #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */ |
| AnnaBridge | 172:65be27845400 | 14085 | |
| AnnaBridge | 172:65be27845400 | 14086 | /****************** Bit definition for SAI_PDMDLY register ******************/ |
| AnnaBridge | 172:65be27845400 | 14087 | #define SAI_PDMDLY_DLYM1L_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14088 | #define SAI_PDMDLY_DLYM1L_Msk (0x7U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 14089 | #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */ |
| AnnaBridge | 172:65be27845400 | 14090 | #define SAI_PDMDLY_DLYM1L_0 (0x1U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14091 | #define SAI_PDMDLY_DLYM1L_1 (0x2U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14092 | #define SAI_PDMDLY_DLYM1L_2 (0x4U << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14093 | |
| AnnaBridge | 172:65be27845400 | 14094 | #define SAI_PDMDLY_DLYM1R_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14095 | #define SAI_PDMDLY_DLYM1R_Msk (0x7U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 14096 | #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */ |
| AnnaBridge | 172:65be27845400 | 14097 | #define SAI_PDMDLY_DLYM1R_0 (0x1U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14098 | #define SAI_PDMDLY_DLYM1R_1 (0x2U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14099 | #define SAI_PDMDLY_DLYM1R_2 (0x4U << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14100 | |
| AnnaBridge | 172:65be27845400 | 14101 | #define SAI_PDMDLY_DLYM2L_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14102 | #define SAI_PDMDLY_DLYM2L_Msk (0x7U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 14103 | #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */ |
| AnnaBridge | 172:65be27845400 | 14104 | #define SAI_PDMDLY_DLYM2L_0 (0x1U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14105 | #define SAI_PDMDLY_DLYM2L_1 (0x2U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14106 | #define SAI_PDMDLY_DLYM2L_2 (0x4U << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14107 | |
| AnnaBridge | 172:65be27845400 | 14108 | #define SAI_PDMDLY_DLYM2R_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14109 | #define SAI_PDMDLY_DLYM2R_Msk (0x7U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 14110 | #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */ |
| AnnaBridge | 172:65be27845400 | 14111 | #define SAI_PDMDLY_DLYM2R_0 (0x1U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14112 | #define SAI_PDMDLY_DLYM2R_1 (0x2U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14113 | #define SAI_PDMDLY_DLYM2R_2 (0x4U << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 14114 | |
| AnnaBridge | 172:65be27845400 | 14115 | #define SAI_PDMDLY_DLYM3L_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14116 | #define SAI_PDMDLY_DLYM3L_Msk (0x7U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 14117 | #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */ |
| AnnaBridge | 172:65be27845400 | 14118 | #define SAI_PDMDLY_DLYM3L_0 (0x1U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14119 | #define SAI_PDMDLY_DLYM3L_1 (0x2U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14120 | #define SAI_PDMDLY_DLYM3L_2 (0x4U << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14121 | |
| AnnaBridge | 172:65be27845400 | 14122 | #define SAI_PDMDLY_DLYM3R_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 14123 | #define SAI_PDMDLY_DLYM3R_Msk (0x7U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */ |
| AnnaBridge | 172:65be27845400 | 14124 | #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */ |
| AnnaBridge | 172:65be27845400 | 14125 | #define SAI_PDMDLY_DLYM3R_0 (0x1U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 14126 | #define SAI_PDMDLY_DLYM3R_1 (0x2U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 14127 | #define SAI_PDMDLY_DLYM3R_2 (0x4U << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 14128 | |
| AnnaBridge | 172:65be27845400 | 14129 | #define SAI_PDMDLY_DLYM4L_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 14130 | #define SAI_PDMDLY_DLYM4L_Msk (0x7U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 14131 | #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */ |
| AnnaBridge | 172:65be27845400 | 14132 | #define SAI_PDMDLY_DLYM4L_0 (0x1U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 14133 | #define SAI_PDMDLY_DLYM4L_1 (0x2U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 14134 | #define SAI_PDMDLY_DLYM4L_2 (0x4U << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 14135 | |
| AnnaBridge | 172:65be27845400 | 14136 | #define SAI_PDMDLY_DLYM4R_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 14137 | #define SAI_PDMDLY_DLYM4R_Msk (0x7U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */ |
| AnnaBridge | 172:65be27845400 | 14138 | #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */ |
| AnnaBridge | 172:65be27845400 | 14139 | #define SAI_PDMDLY_DLYM4R_0 (0x1U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 14140 | #define SAI_PDMDLY_DLYM4R_1 (0x2U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 14141 | #define SAI_PDMDLY_DLYM4R_2 (0x4U << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 14142 | |
| AnnaBridge | 172:65be27845400 | 14143 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 14144 | /* */ |
| AnnaBridge | 172:65be27845400 | 14145 | /* SDMMC Interface */ |
| AnnaBridge | 172:65be27845400 | 14146 | /* */ |
| AnnaBridge | 172:65be27845400 | 14147 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 14148 | /****************** Bit definition for SDMMC_POWER register ******************/ |
| AnnaBridge | 172:65be27845400 | 14149 | #define SDMMC_POWER_PWRCTRL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14150 | #define SDMMC_POWER_PWRCTRL_Msk (0x3U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 14151 | #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
| AnnaBridge | 172:65be27845400 | 14152 | #define SDMMC_POWER_PWRCTRL_0 (0x1U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14153 | #define SDMMC_POWER_PWRCTRL_1 (0x2U << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14154 | #define SDMMC_POWER_VSWITCH_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14155 | #define SDMMC_POWER_VSWITCH_Msk (0x1U << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14156 | #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Pos /*!<Voltage switch sequence start */ |
| AnnaBridge | 172:65be27845400 | 14157 | #define SDMMC_POWER_VSWITCHEN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14158 | #define SDMMC_POWER_VSWITCHEN_Msk (0x1U << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14159 | #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Pos /*!<Voltage switch procedure enable */ |
| AnnaBridge | 172:65be27845400 | 14160 | #define SDMMC_POWER_DIRPOL_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14161 | #define SDMMC_POWER_DIRPOL_Msk (0x1U << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14162 | #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Pos /*!<Data and Command direction signals polarity selection */ |
| AnnaBridge | 172:65be27845400 | 14163 | |
| AnnaBridge | 172:65be27845400 | 14164 | /****************** Bit definition for SDMMC_CLKCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14165 | #define SDMMC_CLKCR_CLKDIV_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14166 | #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFU << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */ |
| AnnaBridge | 172:65be27845400 | 14167 | #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */ |
| AnnaBridge | 172:65be27845400 | 14168 | #define SDMMC_CLKCR_PWRSAV_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14169 | #define SDMMC_CLKCR_PWRSAV_Msk (0x1U << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14170 | #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */ |
| AnnaBridge | 172:65be27845400 | 14171 | |
| AnnaBridge | 172:65be27845400 | 14172 | #define SDMMC_CLKCR_WIDBUS_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 14173 | #define SDMMC_CLKCR_WIDBUS_Msk (0x3U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 14174 | #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
| AnnaBridge | 172:65be27845400 | 14175 | #define SDMMC_CLKCR_WIDBUS_0 (0x1U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14176 | #define SDMMC_CLKCR_WIDBUS_1 (0x2U << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14177 | |
| AnnaBridge | 172:65be27845400 | 14178 | #define SDMMC_CLKCR_NEGEDGE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14179 | #define SDMMC_CLKCR_NEGEDGE_Msk (0x1U << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14180 | #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */ |
| AnnaBridge | 172:65be27845400 | 14181 | #define SDMMC_CLKCR_HWFC_EN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 14182 | #define SDMMC_CLKCR_HWFC_EN_Msk (0x1U << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14183 | #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */ |
| AnnaBridge | 172:65be27845400 | 14184 | #define SDMMC_CLKCR_DDR_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 14185 | #define SDMMC_CLKCR_DDR_Msk (0x1U << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14186 | #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */ |
| AnnaBridge | 172:65be27845400 | 14187 | #define SDMMC_CLKCR_BUSSPEED_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 14188 | #define SDMMC_CLKCR_BUSSPEED_Msk (0x1U << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 14189 | #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */ |
| AnnaBridge | 172:65be27845400 | 14190 | |
| AnnaBridge | 172:65be27845400 | 14191 | #define SDMMC_CLKCR_SELCLKRX_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 14192 | #define SDMMC_CLKCR_SELCLKRX_Msk (0x3U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 14193 | #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */ |
| AnnaBridge | 172:65be27845400 | 14194 | #define SDMMC_CLKCR_SELCLKRX_0 (0x1U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14195 | #define SDMMC_CLKCR_SELCLKRX_1 (0x2U << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14196 | |
| AnnaBridge | 172:65be27845400 | 14197 | /******************* Bit definition for SDMMC_ARG register *******************/ |
| AnnaBridge | 172:65be27845400 | 14198 | #define SDMMC_ARG_CMDARG_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14199 | #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14200 | #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */ |
| AnnaBridge | 172:65be27845400 | 14201 | |
| AnnaBridge | 172:65be27845400 | 14202 | /******************* Bit definition for SDMMC_CMD register *******************/ |
| AnnaBridge | 172:65be27845400 | 14203 | #define SDMMC_CMD_CMDINDEX_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14204 | #define SDMMC_CMD_CMDINDEX_Msk (0x3FU << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 172:65be27845400 | 14205 | #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */ |
| AnnaBridge | 172:65be27845400 | 14206 | #define SDMMC_CMD_CMDTRANS_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14207 | #define SDMMC_CMD_CMDTRANS_Msk (0x1U << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14208 | #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */ |
| AnnaBridge | 172:65be27845400 | 14209 | #define SDMMC_CMD_CMDSTOP_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14210 | #define SDMMC_CMD_CMDSTOP_Msk (0x1U << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14211 | #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */ |
| AnnaBridge | 172:65be27845400 | 14212 | |
| AnnaBridge | 172:65be27845400 | 14213 | #define SDMMC_CMD_WAITRESP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14214 | #define SDMMC_CMD_WAITRESP_Msk (0x3U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 14215 | #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
| AnnaBridge | 172:65be27845400 | 14216 | #define SDMMC_CMD_WAITRESP_0 (0x1U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14217 | #define SDMMC_CMD_WAITRESP_1 (0x2U << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14218 | |
| AnnaBridge | 172:65be27845400 | 14219 | #define SDMMC_CMD_WAITINT_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14220 | #define SDMMC_CMD_WAITINT_Msk (0x1U << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14221 | #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */ |
| AnnaBridge | 172:65be27845400 | 14222 | #define SDMMC_CMD_WAITPEND_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14223 | #define SDMMC_CMD_WAITPEND_Msk (0x1U << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14224 | #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
| AnnaBridge | 172:65be27845400 | 14225 | #define SDMMC_CMD_CPSMEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14226 | #define SDMMC_CMD_CPSMEN_Msk (0x1U << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14227 | #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */ |
| AnnaBridge | 172:65be27845400 | 14228 | #define SDMMC_CMD_DTHOLD_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 14229 | #define SDMMC_CMD_DTHOLD_Msk (0x1U << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14230 | #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */ |
| AnnaBridge | 172:65be27845400 | 14231 | #define SDMMC_CMD_BOOTMODE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 14232 | #define SDMMC_CMD_BOOTMODE_Msk (0x1U << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 14233 | #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */ |
| AnnaBridge | 172:65be27845400 | 14234 | #define SDMMC_CMD_BOOTEN_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 14235 | #define SDMMC_CMD_BOOTEN_Msk (0x1U << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 14236 | #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */ |
| AnnaBridge | 172:65be27845400 | 14237 | #define SDMMC_CMD_CMDSUSPEND_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14238 | #define SDMMC_CMD_CMDSUSPEND_Msk (0x1U << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14239 | #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM treats command as a Suspend or Resume command */ |
| AnnaBridge | 172:65be27845400 | 14240 | |
| AnnaBridge | 172:65be27845400 | 14241 | /***************** Bit definition for SDMMC_RESPCMD register *****************/ |
| AnnaBridge | 172:65be27845400 | 14242 | #define SDMMC_RESPCMD_RESPCMD_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14243 | #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 172:65be27845400 | 14244 | #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */ |
| AnnaBridge | 172:65be27845400 | 14245 | |
| AnnaBridge | 172:65be27845400 | 14246 | /****************** Bit definition for SDMMC_RESP1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14247 | #define SDMMC_RESP1_CARDSTATUS1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14248 | #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14249 | #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */ |
| AnnaBridge | 172:65be27845400 | 14250 | |
| AnnaBridge | 172:65be27845400 | 14251 | /****************** Bit definition for SDMMC_RESP2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14252 | #define SDMMC_RESP2_CARDSTATUS2_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14253 | #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14254 | #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */ |
| AnnaBridge | 172:65be27845400 | 14255 | |
| AnnaBridge | 172:65be27845400 | 14256 | /****************** Bit definition for SDMMC_RESP3 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14257 | #define SDMMC_RESP3_CARDSTATUS3_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14258 | #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14259 | #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */ |
| AnnaBridge | 172:65be27845400 | 14260 | |
| AnnaBridge | 172:65be27845400 | 14261 | /****************** Bit definition for SDMMC_RESP4 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14262 | #define SDMMC_RESP4_CARDSTATUS4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14263 | #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14264 | #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */ |
| AnnaBridge | 172:65be27845400 | 14265 | |
| AnnaBridge | 172:65be27845400 | 14266 | /****************** Bit definition for SDMMC_DTIMER register *****************/ |
| AnnaBridge | 172:65be27845400 | 14267 | #define SDMMC_DTIMER_DATATIME_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14268 | #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14269 | #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */ |
| AnnaBridge | 172:65be27845400 | 14270 | |
| AnnaBridge | 172:65be27845400 | 14271 | /****************** Bit definition for SDMMC_DLEN register *******************/ |
| AnnaBridge | 172:65be27845400 | 14272 | #define SDMMC_DLEN_DATALENGTH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14273 | #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14274 | #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */ |
| AnnaBridge | 172:65be27845400 | 14275 | |
| AnnaBridge | 172:65be27845400 | 14276 | /****************** Bit definition for SDMMC_DCTRL register ******************/ |
| AnnaBridge | 172:65be27845400 | 14277 | #define SDMMC_DCTRL_DTEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14278 | #define SDMMC_DCTRL_DTEN_Msk (0x1U << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14279 | #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */ |
| AnnaBridge | 172:65be27845400 | 14280 | #define SDMMC_DCTRL_DTDIR_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14281 | #define SDMMC_DCTRL_DTDIR_Msk (0x1U << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14282 | #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */ |
| AnnaBridge | 172:65be27845400 | 14283 | |
| AnnaBridge | 172:65be27845400 | 14284 | #define SDMMC_DCTRL_DTMODE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14285 | #define SDMMC_DCTRL_DTMODE_Msk (0x3U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 14286 | #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */ |
| AnnaBridge | 172:65be27845400 | 14287 | #define SDMMC_DCTRL_DTMODE_0 (0x1U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14288 | #define SDMMC_DCTRL_DTMODE_1 (0x2U << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14289 | |
| AnnaBridge | 172:65be27845400 | 14290 | #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14291 | #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 14292 | #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
| AnnaBridge | 172:65be27845400 | 14293 | #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14294 | #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14295 | #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14296 | #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14297 | |
| AnnaBridge | 172:65be27845400 | 14298 | #define SDMMC_DCTRL_RWSTART_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14299 | #define SDMMC_DCTRL_RWSTART_Msk (0x1U << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14300 | #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */ |
| AnnaBridge | 172:65be27845400 | 14301 | #define SDMMC_DCTRL_RWSTOP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14302 | #define SDMMC_DCTRL_RWSTOP_Msk (0x1U << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14303 | #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */ |
| AnnaBridge | 172:65be27845400 | 14304 | #define SDMMC_DCTRL_RWMOD_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14305 | #define SDMMC_DCTRL_RWMOD_Msk (0x1U << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14306 | #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */ |
| AnnaBridge | 172:65be27845400 | 14307 | #define SDMMC_DCTRL_SDIOEN_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14308 | #define SDMMC_DCTRL_SDIOEN_Msk (0x1U << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14309 | #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */ |
| AnnaBridge | 172:65be27845400 | 14310 | #define SDMMC_DCTRL_BOOTACKEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14311 | #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1U << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14312 | #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Data transfer mode selection */ |
| AnnaBridge | 172:65be27845400 | 14313 | #define SDMMC_DCTRL_FIFORST_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 14314 | #define SDMMC_DCTRL_FIFORST_Msk (0x1U << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14315 | #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */ |
| AnnaBridge | 172:65be27845400 | 14316 | |
| AnnaBridge | 172:65be27845400 | 14317 | /****************** Bit definition for SDMMC_DCOUNT register *****************/ |
| AnnaBridge | 172:65be27845400 | 14318 | #define SDMMC_DCOUNT_DATACOUNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14319 | #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14320 | #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */ |
| AnnaBridge | 172:65be27845400 | 14321 | |
| AnnaBridge | 172:65be27845400 | 14322 | /****************** Bit definition for SDMMC_STA register ********************/ |
| AnnaBridge | 172:65be27845400 | 14323 | #define SDMMC_STA_CCRCFAIL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14324 | #define SDMMC_STA_CCRCFAIL_Msk (0x1U << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14325 | #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */ |
| AnnaBridge | 172:65be27845400 | 14326 | #define SDMMC_STA_DCRCFAIL_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14327 | #define SDMMC_STA_DCRCFAIL_Msk (0x1U << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14328 | #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */ |
| AnnaBridge | 172:65be27845400 | 14329 | #define SDMMC_STA_CTIMEOUT_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14330 | #define SDMMC_STA_CTIMEOUT_Msk (0x1U << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14331 | #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */ |
| AnnaBridge | 172:65be27845400 | 14332 | #define SDMMC_STA_DTIMEOUT_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14333 | #define SDMMC_STA_DTIMEOUT_Msk (0x1U << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14334 | #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */ |
| AnnaBridge | 172:65be27845400 | 14335 | #define SDMMC_STA_TXUNDERR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14336 | #define SDMMC_STA_TXUNDERR_Msk (0x1U << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14337 | #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */ |
| AnnaBridge | 172:65be27845400 | 14338 | #define SDMMC_STA_RXOVERR_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14339 | #define SDMMC_STA_RXOVERR_Msk (0x1U << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14340 | #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */ |
| AnnaBridge | 172:65be27845400 | 14341 | #define SDMMC_STA_CMDREND_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14342 | #define SDMMC_STA_CMDREND_Msk (0x1U << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14343 | #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */ |
| AnnaBridge | 172:65be27845400 | 14344 | #define SDMMC_STA_CMDSENT_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14345 | #define SDMMC_STA_CMDSENT_Msk (0x1U << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14346 | #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */ |
| AnnaBridge | 172:65be27845400 | 14347 | #define SDMMC_STA_DATAEND_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14348 | #define SDMMC_STA_DATAEND_Msk (0x1U << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14349 | #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
| AnnaBridge | 172:65be27845400 | 14350 | #define SDMMC_STA_DHOLD_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14351 | #define SDMMC_STA_DHOLD_Msk (0x1U << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14352 | #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */ |
| AnnaBridge | 172:65be27845400 | 14353 | #define SDMMC_STA_DBCKEND_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14354 | #define SDMMC_STA_DBCKEND_Msk (0x1U << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14355 | #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */ |
| AnnaBridge | 172:65be27845400 | 14356 | #define SDMMC_STA_DABORT_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14357 | #define SDMMC_STA_DABORT_Msk (0x1U << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14358 | #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */ |
| AnnaBridge | 172:65be27845400 | 14359 | #define SDMMC_STA_DPSMACT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14360 | #define SDMMC_STA_DPSMACT_Msk (0x1U << SDMMC_STA_CPSMACT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14361 | #define SDMMC_STA_DPSMACT SDMMC_STA_CPSMACT_Msk /*!<Data path state machine active */ |
| AnnaBridge | 172:65be27845400 | 14362 | #define SDMMC_STA_CPSMACT_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 14363 | #define SDMMC_STA_CPSMACT_Msk (0x1U << SDMMC_STA_DPSMACT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14364 | #define SDMMC_STA_CPSMACT SDMMC_STA_DPSMACT_Msk /*!<Command path state machine active */ |
| AnnaBridge | 172:65be27845400 | 14365 | #define SDMMC_STA_TXFIFOHE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 14366 | #define SDMMC_STA_TXFIFOHE_Msk (0x1U << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 14367 | #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
| AnnaBridge | 172:65be27845400 | 14368 | #define SDMMC_STA_RXFIFOHF_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 14369 | #define SDMMC_STA_RXFIFOHF_Msk (0x1U << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 14370 | #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
| AnnaBridge | 172:65be27845400 | 14371 | #define SDMMC_STA_TXFIFOF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14372 | #define SDMMC_STA_TXFIFOF_Msk (0x1U << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14373 | #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */ |
| AnnaBridge | 172:65be27845400 | 14374 | #define SDMMC_STA_RXFIFOF_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 14375 | #define SDMMC_STA_RXFIFOF_Msk (0x1U << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14376 | #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */ |
| AnnaBridge | 172:65be27845400 | 14377 | #define SDMMC_STA_TXFIFOE_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 14378 | #define SDMMC_STA_TXFIFOE_Msk (0x1U << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14379 | #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */ |
| AnnaBridge | 172:65be27845400 | 14380 | #define SDMMC_STA_RXFIFOE_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 14381 | #define SDMMC_STA_RXFIFOE_Msk (0x1U << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 14382 | #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */ |
| AnnaBridge | 172:65be27845400 | 14383 | #define SDMMC_STA_BUSYD0_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 14384 | #define SDMMC_STA_BUSYD0_Msk (0x1U << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 14385 | #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */ |
| AnnaBridge | 172:65be27845400 | 14386 | #define SDMMC_STA_BUSYD0END_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 14387 | #define SDMMC_STA_BUSYD0END_Msk (0x1U << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 14388 | #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */ |
| AnnaBridge | 172:65be27845400 | 14389 | #define SDMMC_STA_SDIOIT_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 14390 | #define SDMMC_STA_SDIOIT_Msk (0x1U << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 14391 | #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */ |
| AnnaBridge | 172:65be27845400 | 14392 | #define SDMMC_STA_ACKFAIL_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 14393 | #define SDMMC_STA_ACKFAIL_Msk (0x1U << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 14394 | #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */ |
| AnnaBridge | 172:65be27845400 | 14395 | #define SDMMC_STA_ACKTIMEOUT_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 14396 | #define SDMMC_STA_ACKTIMEOUT_Msk (0x1U << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 14397 | #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */ |
| AnnaBridge | 172:65be27845400 | 14398 | #define SDMMC_STA_VSWEND_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 14399 | #define SDMMC_STA_VSWEND_Msk (0x1U << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 14400 | #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */ |
| AnnaBridge | 172:65be27845400 | 14401 | #define SDMMC_STA_CKSTOP_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 14402 | #define SDMMC_STA_CKSTOP_Msk (0x1U << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 14403 | #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */ |
| AnnaBridge | 172:65be27845400 | 14404 | #define SDMMC_STA_IDMATE_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 14405 | #define SDMMC_STA_IDMATE_Msk (0x1U << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 14406 | #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */ |
| AnnaBridge | 172:65be27845400 | 14407 | #define SDMMC_STA_IDMABTC_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 14408 | #define SDMMC_STA_IDMABTC_Msk (0x1U << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 14409 | #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */ |
| AnnaBridge | 172:65be27845400 | 14410 | |
| AnnaBridge | 172:65be27845400 | 14411 | /******************* Bit definition for SDMMC_ICR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14412 | #define SDMMC_ICR_CCRCFAILC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14413 | #define SDMMC_ICR_CCRCFAILC_Msk (0x1U << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14414 | #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14415 | #define SDMMC_ICR_DCRCFAILC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14416 | #define SDMMC_ICR_DCRCFAILC_Msk (0x1U << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14417 | #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14418 | #define SDMMC_ICR_CTIMEOUTC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14419 | #define SDMMC_ICR_CTIMEOUTC_Msk (0x1U << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14420 | #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14421 | #define SDMMC_ICR_DTIMEOUTC_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14422 | #define SDMMC_ICR_DTIMEOUTC_Msk (0x1U << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14423 | #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14424 | #define SDMMC_ICR_TXUNDERRC_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14425 | #define SDMMC_ICR_TXUNDERRC_Msk (0x1U << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14426 | #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14427 | #define SDMMC_ICR_RXOVERRC_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14428 | #define SDMMC_ICR_RXOVERRC_Msk (0x1U << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14429 | #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14430 | #define SDMMC_ICR_CMDRENDC_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14431 | #define SDMMC_ICR_CMDRENDC_Msk (0x1U << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14432 | #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14433 | #define SDMMC_ICR_CMDSENTC_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14434 | #define SDMMC_ICR_CMDSENTC_Msk (0x1U << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14435 | #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14436 | #define SDMMC_ICR_DATAENDC_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14437 | #define SDMMC_ICR_DATAENDC_Msk (0x1U << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14438 | #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14439 | #define SDMMC_ICR_DHOLDC_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14440 | #define SDMMC_ICR_DHOLDC_Msk (0x1U << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14441 | #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14442 | #define SDMMC_ICR_DBCKENDC_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14443 | #define SDMMC_ICR_DBCKENDC_Msk (0x1U << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14444 | #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14445 | #define SDMMC_ICR_DABORTC_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14446 | #define SDMMC_ICR_DABORTC_Msk (0x1U << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14447 | #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14448 | #define SDMMC_ICR_BUSYD0ENDC_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 14449 | #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1U << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 14450 | #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14451 | #define SDMMC_ICR_SDIOITC_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 14452 | #define SDMMC_ICR_SDIOITC_Msk (0x1U << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 14453 | #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14454 | #define SDMMC_ICR_ACKFAILC_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 14455 | #define SDMMC_ICR_ACKFAILC_Msk (0x1U << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 14456 | #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14457 | #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 14458 | #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1U << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 14459 | #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14460 | #define SDMMC_ICR_VSWENDC_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 14461 | #define SDMMC_ICR_VSWENDC_Msk (0x1U << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 14462 | #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14463 | #define SDMMC_ICR_CKSTOPC_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 14464 | #define SDMMC_ICR_CKSTOPC_Msk (0x1U << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 14465 | #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14466 | #define SDMMC_ICR_IDMATEC_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 14467 | #define SDMMC_ICR_IDMATEC_Msk (0x1U << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 14468 | #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14469 | #define SDMMC_ICR_IDMABTCC_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 14470 | #define SDMMC_ICR_IDMABTCC_Msk (0x1U << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 14471 | #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */ |
| AnnaBridge | 172:65be27845400 | 14472 | |
| AnnaBridge | 172:65be27845400 | 14473 | /****************** Bit definition for SDMMC_MASK register *******************/ |
| AnnaBridge | 172:65be27845400 | 14474 | #define SDMMC_MASK_CCRCFAILIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14475 | #define SDMMC_MASK_CCRCFAILIE_Msk (0x1U << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14476 | #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14477 | #define SDMMC_MASK_DCRCFAILIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14478 | #define SDMMC_MASK_DCRCFAILIE_Msk (0x1U << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14479 | #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14480 | #define SDMMC_MASK_CTIMEOUTIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14481 | #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14482 | #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14483 | #define SDMMC_MASK_DTIMEOUTIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14484 | #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14485 | #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14486 | #define SDMMC_MASK_TXUNDERRIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14487 | #define SDMMC_MASK_TXUNDERRIE_Msk (0x1U << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14488 | #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14489 | #define SDMMC_MASK_RXOVERRIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14490 | #define SDMMC_MASK_RXOVERRIE_Msk (0x1U << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14491 | #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14492 | #define SDMMC_MASK_CMDRENDIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14493 | #define SDMMC_MASK_CMDRENDIE_Msk (0x1U << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14494 | #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14495 | #define SDMMC_MASK_CMDSENTIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14496 | #define SDMMC_MASK_CMDSENTIE_Msk (0x1U << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14497 | #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14498 | #define SDMMC_MASK_DATAENDIE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14499 | #define SDMMC_MASK_DATAENDIE_Msk (0x1U << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14500 | #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14501 | #define SDMMC_MASK_DHOLDIE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14502 | #define SDMMC_MASK_DHOLDIE_Msk (0x1U << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14503 | #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14504 | #define SDMMC_MASK_DBCKENDIE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14505 | #define SDMMC_MASK_DBCKENDIE_Msk (0x1U << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14506 | #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14507 | #define SDMMC_MASK_DABORTIE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14508 | #define SDMMC_MASK_DABORTIE_Msk (0x1U << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14509 | #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14510 | #define SDMMC_MASK_TXFIFOHEIE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 14511 | #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 14512 | #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14513 | #define SDMMC_MASK_RXFIFOHFIE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 14514 | #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 14515 | #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14516 | #define SDMMC_MASK_RXFIFOFIE_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 14517 | #define SDMMC_MASK_RXFIFOFIE_Msk (0x1U << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14518 | #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14519 | #define SDMMC_MASK_TXFIFOEIE_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 14520 | #define SDMMC_MASK_TXFIFOEIE_Msk (0x1U << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14521 | #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14522 | #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 14523 | #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1U << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 14524 | #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0END interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14525 | #define SDMMC_MASK_SDIOITIE_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 14526 | #define SDMMC_MASK_SDIOITIE_Msk (0x1U << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 14527 | #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14528 | #define SDMMC_MASK_ACKFAILIE_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 14529 | #define SDMMC_MASK_ACKFAILIE_Msk (0x1U << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 14530 | #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14531 | #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 14532 | #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1U << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 14533 | #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14534 | #define SDMMC_MASK_VSWENDIE_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 14535 | #define SDMMC_MASK_VSWENDIE_Msk (0x1U << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 14536 | #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14537 | #define SDMMC_MASK_CKSTOPIE_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 14538 | #define SDMMC_MASK_CKSTOPIE_Msk (0x1U << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 14539 | #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14540 | #define SDMMC_MASK_IDMABTCIE_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 14541 | #define SDMMC_MASK_IDMABTCIE_Msk (0x1U << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 14542 | #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14543 | |
| AnnaBridge | 172:65be27845400 | 14544 | /***************** Bit definition for SDMMC_FIFOCNT register *****************/ |
| AnnaBridge | 172:65be27845400 | 14545 | #define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14546 | #define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14547 | #define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */ |
| AnnaBridge | 172:65be27845400 | 14548 | |
| AnnaBridge | 172:65be27845400 | 14549 | /****************** Bit definition for SDMMC_FIFO register *******************/ |
| AnnaBridge | 172:65be27845400 | 14550 | #define SDMMC_FIFO_FIFODATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14551 | #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14552 | #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */ |
| AnnaBridge | 172:65be27845400 | 14553 | |
| AnnaBridge | 172:65be27845400 | 14554 | /****************** Bit definition for SDMMC_IDMACTRL register ****************/ |
| AnnaBridge | 172:65be27845400 | 14555 | #define SDMMC_IDMA_IDMAEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14556 | #define SDMMC_IDMA_IDMAEN_Msk (0x1U << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14557 | #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */ |
| AnnaBridge | 172:65be27845400 | 14558 | #define SDMMC_IDMA_IDMABMODE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14559 | #define SDMMC_IDMA_IDMABMODE_Msk (0x1U << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14560 | #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */ |
| AnnaBridge | 172:65be27845400 | 14561 | #define SDMMC_IDMA_IDMABACT_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14562 | #define SDMMC_IDMA_IDMABACT_Msk (0x1U << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14563 | #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */ |
| AnnaBridge | 172:65be27845400 | 14564 | |
| AnnaBridge | 172:65be27845400 | 14565 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 14566 | /* */ |
| AnnaBridge | 172:65be27845400 | 14567 | /* Serial Peripheral Interface (SPI) */ |
| AnnaBridge | 172:65be27845400 | 14568 | /* */ |
| AnnaBridge | 172:65be27845400 | 14569 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 14570 | /******************* Bit definition for SPI_CR1 register ********************/ |
| AnnaBridge | 172:65be27845400 | 14571 | #define SPI_CR1_CPHA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14572 | #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14573 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ |
| AnnaBridge | 172:65be27845400 | 14574 | #define SPI_CR1_CPOL_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14575 | #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14576 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ |
| AnnaBridge | 172:65be27845400 | 14577 | #define SPI_CR1_MSTR_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14578 | #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14579 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ |
| AnnaBridge | 172:65be27845400 | 14580 | |
| AnnaBridge | 172:65be27845400 | 14581 | #define SPI_CR1_BR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14582 | #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
| AnnaBridge | 172:65be27845400 | 14583 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ |
| AnnaBridge | 172:65be27845400 | 14584 | #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14585 | #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14586 | #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14587 | |
| AnnaBridge | 172:65be27845400 | 14588 | #define SPI_CR1_SPE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14589 | #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14590 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ |
| AnnaBridge | 172:65be27845400 | 14591 | #define SPI_CR1_LSBFIRST_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14592 | #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14593 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ |
| AnnaBridge | 172:65be27845400 | 14594 | #define SPI_CR1_SSI_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14595 | #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14596 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ |
| AnnaBridge | 172:65be27845400 | 14597 | #define SPI_CR1_SSM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14598 | #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14599 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ |
| AnnaBridge | 172:65be27845400 | 14600 | #define SPI_CR1_RXONLY_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 14601 | #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14602 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ |
| AnnaBridge | 172:65be27845400 | 14603 | #define SPI_CR1_CRCL_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14604 | #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14605 | #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */ |
| AnnaBridge | 172:65be27845400 | 14606 | #define SPI_CR1_CRCNEXT_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14607 | #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14608 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ |
| AnnaBridge | 172:65be27845400 | 14609 | #define SPI_CR1_CRCEN_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 14610 | #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14611 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ |
| AnnaBridge | 172:65be27845400 | 14612 | #define SPI_CR1_BIDIOE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 14613 | #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 14614 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ |
| AnnaBridge | 172:65be27845400 | 14615 | #define SPI_CR1_BIDIMODE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 14616 | #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 14617 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ |
| AnnaBridge | 172:65be27845400 | 14618 | |
| AnnaBridge | 172:65be27845400 | 14619 | /******************* Bit definition for SPI_CR2 register ********************/ |
| AnnaBridge | 172:65be27845400 | 14620 | #define SPI_CR2_RXDMAEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14621 | #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14622 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
| AnnaBridge | 172:65be27845400 | 14623 | #define SPI_CR2_TXDMAEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14624 | #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14625 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
| AnnaBridge | 172:65be27845400 | 14626 | #define SPI_CR2_SSOE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14627 | #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14628 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
| AnnaBridge | 172:65be27845400 | 14629 | #define SPI_CR2_NSSP_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14630 | #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14631 | #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */ |
| AnnaBridge | 172:65be27845400 | 14632 | #define SPI_CR2_FRF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14633 | #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14634 | #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ |
| AnnaBridge | 172:65be27845400 | 14635 | #define SPI_CR2_ERRIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14636 | #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14637 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14638 | #define SPI_CR2_RXNEIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14639 | #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14640 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14641 | #define SPI_CR2_TXEIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14642 | #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14643 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14644 | #define SPI_CR2_DS_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14645 | #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 14646 | #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ |
| AnnaBridge | 172:65be27845400 | 14647 | #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14648 | #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14649 | #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14650 | #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14651 | #define SPI_CR2_FRXTH_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14652 | #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14653 | #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ |
| AnnaBridge | 172:65be27845400 | 14654 | #define SPI_CR2_LDMARX_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 14655 | #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14656 | #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */ |
| AnnaBridge | 172:65be27845400 | 14657 | #define SPI_CR2_LDMATX_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 14658 | #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 14659 | #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */ |
| AnnaBridge | 172:65be27845400 | 14660 | |
| AnnaBridge | 172:65be27845400 | 14661 | /******************** Bit definition for SPI_SR register ********************/ |
| AnnaBridge | 172:65be27845400 | 14662 | #define SPI_SR_RXNE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14663 | #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14664 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
| AnnaBridge | 172:65be27845400 | 14665 | #define SPI_SR_TXE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14666 | #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14667 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
| AnnaBridge | 172:65be27845400 | 14668 | #define SPI_SR_CHSIDE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14669 | #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14670 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
| AnnaBridge | 172:65be27845400 | 14671 | #define SPI_SR_UDR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14672 | #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14673 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
| AnnaBridge | 172:65be27845400 | 14674 | #define SPI_SR_CRCERR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14675 | #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14676 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
| AnnaBridge | 172:65be27845400 | 14677 | #define SPI_SR_MODF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14678 | #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14679 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
| AnnaBridge | 172:65be27845400 | 14680 | #define SPI_SR_OVR_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14681 | #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14682 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
| AnnaBridge | 172:65be27845400 | 14683 | #define SPI_SR_BSY_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14684 | #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14685 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
| AnnaBridge | 172:65be27845400 | 14686 | #define SPI_SR_FRE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14687 | #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14688 | #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ |
| AnnaBridge | 172:65be27845400 | 14689 | #define SPI_SR_FRLVL_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 14690 | #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ |
| AnnaBridge | 172:65be27845400 | 14691 | #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ |
| AnnaBridge | 172:65be27845400 | 14692 | #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14693 | #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14694 | #define SPI_SR_FTLVL_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14695 | #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 172:65be27845400 | 14696 | #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ |
| AnnaBridge | 172:65be27845400 | 14697 | #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14698 | #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14699 | |
| AnnaBridge | 172:65be27845400 | 14700 | /******************** Bit definition for SPI_DR register ********************/ |
| AnnaBridge | 172:65be27845400 | 14701 | #define SPI_DR_DR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14702 | #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 14703 | #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ |
| AnnaBridge | 172:65be27845400 | 14704 | |
| AnnaBridge | 172:65be27845400 | 14705 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14706 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14707 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 14708 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ |
| AnnaBridge | 172:65be27845400 | 14709 | |
| AnnaBridge | 172:65be27845400 | 14710 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14711 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14712 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 14713 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ |
| AnnaBridge | 172:65be27845400 | 14714 | |
| AnnaBridge | 172:65be27845400 | 14715 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14716 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14717 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 14718 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ |
| AnnaBridge | 172:65be27845400 | 14719 | |
| AnnaBridge | 172:65be27845400 | 14720 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 14721 | /* */ |
| AnnaBridge | 172:65be27845400 | 14722 | /* OCTOSPI */ |
| AnnaBridge | 172:65be27845400 | 14723 | /* */ |
| AnnaBridge | 172:65be27845400 | 14724 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 14725 | /***************** Bit definition for OCTOSPI_CR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14726 | #define OCTOSPI_CR_EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14727 | #define OCTOSPI_CR_EN_Msk (0x1U << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14728 | #define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */ |
| AnnaBridge | 172:65be27845400 | 14729 | #define OCTOSPI_CR_ABORT_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14730 | #define OCTOSPI_CR_ABORT_Msk (0x1U << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14731 | #define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */ |
| AnnaBridge | 172:65be27845400 | 14732 | #define OCTOSPI_CR_DMAEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14733 | #define OCTOSPI_CR_DMAEN_Msk (0x1U << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14734 | #define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */ |
| AnnaBridge | 172:65be27845400 | 14735 | #define OCTOSPI_CR_TCEN_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14736 | #define OCTOSPI_CR_TCEN_Msk (0x1U << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14737 | #define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ |
| AnnaBridge | 172:65be27845400 | 14738 | #define OCTOSPI_CR_DQM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 14739 | #define OCTOSPI_CR_DQM_Msk (0x1U << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 14740 | #define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */ |
| AnnaBridge | 172:65be27845400 | 14741 | #define OCTOSPI_CR_FSEL_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 14742 | #define OCTOSPI_CR_FSEL_Msk (0x1U << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 14743 | #define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */ |
| AnnaBridge | 172:65be27845400 | 14744 | #define OCTOSPI_CR_FTHRES_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14745 | #define OCTOSPI_CR_FTHRES_Msk (0x1FU << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 14746 | #define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */ |
| AnnaBridge | 172:65be27845400 | 14747 | #define OCTOSPI_CR_TEIE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14748 | #define OCTOSPI_CR_TEIE_Msk (0x1U << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14749 | #define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14750 | #define OCTOSPI_CR_TCIE_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 14751 | #define OCTOSPI_CR_TCIE_Msk (0x1U << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14752 | #define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14753 | #define OCTOSPI_CR_FTIE_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 14754 | #define OCTOSPI_CR_FTIE_Msk (0x1U << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14755 | #define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14756 | #define OCTOSPI_CR_SMIE_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 14757 | #define OCTOSPI_CR_SMIE_Msk (0x1U << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 14758 | #define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14759 | #define OCTOSPI_CR_TOIE_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 14760 | #define OCTOSPI_CR_TOIE_Msk (0x1U << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 14761 | #define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 14762 | #define OCTOSPI_CR_APMS_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 14763 | #define OCTOSPI_CR_APMS_Msk (0x1U << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 14764 | #define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */ |
| AnnaBridge | 172:65be27845400 | 14765 | #define OCTOSPI_CR_PMM_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 14766 | #define OCTOSPI_CR_PMM_Msk (0x1U << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 14767 | #define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */ |
| AnnaBridge | 172:65be27845400 | 14768 | #define OCTOSPI_CR_FMODE_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 14769 | #define OCTOSPI_CR_FMODE_Msk (0x3U << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */ |
| AnnaBridge | 172:65be27845400 | 14770 | #define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */ |
| AnnaBridge | 172:65be27845400 | 14771 | #define OCTOSPI_CR_FMODE_0 (0x1U << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 14772 | #define OCTOSPI_CR_FMODE_1 (0x2U << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 14773 | |
| AnnaBridge | 172:65be27845400 | 14774 | /**************** Bit definition for OCTOSPI_DCR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14775 | #define OCTOSPI_DCR1_CKMODE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14776 | #define OCTOSPI_DCR1_CKMODE_Msk (0x1U << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14777 | #define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */ |
| AnnaBridge | 172:65be27845400 | 14778 | #define OCTOSPI_DCR1_FRCK_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14779 | #define OCTOSPI_DCR1_FRCK_Msk (0x1U << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14780 | #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */ |
| AnnaBridge | 172:65be27845400 | 14781 | #define OCTOSPI_DCR1_CSHT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14782 | #define OCTOSPI_DCR1_CSHT_Msk (0x7U << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 14783 | #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */ |
| AnnaBridge | 172:65be27845400 | 14784 | #define OCTOSPI_DCR1_DEVSIZE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14785 | #define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FU << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 172:65be27845400 | 14786 | #define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */ |
| AnnaBridge | 172:65be27845400 | 14787 | #define OCTOSPI_DCR1_MTYP_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 14788 | #define OCTOSPI_DCR1_MTYP_Msk (0x7U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 14789 | #define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */ |
| AnnaBridge | 172:65be27845400 | 14790 | #define OCTOSPI_DCR1_MTYP_0 (0x1U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 14791 | #define OCTOSPI_DCR1_MTYP_1 (0x2U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 14792 | #define OCTOSPI_DCR1_MTYP_2 (0x4U << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 14793 | |
| AnnaBridge | 172:65be27845400 | 14794 | /**************** Bit definition for OCTOSPI_DCR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14795 | #define OCTOSPI_DCR2_PRESCALER_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14796 | #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFU << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 14797 | #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */ |
| AnnaBridge | 172:65be27845400 | 14798 | #define OCTOSPI_DCR2_WRAPSIZE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14799 | #define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 14800 | #define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */ |
| AnnaBridge | 172:65be27845400 | 14801 | #define OCTOSPI_DCR2_WRAPSIZE_0 (0x1U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14802 | #define OCTOSPI_DCR2_WRAPSIZE_1 (0x2U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14803 | #define OCTOSPI_DCR2_WRAPSIZE_2 (0x4U << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14804 | |
| AnnaBridge | 172:65be27845400 | 14805 | /**************** Bit definition for OCTOSPI_DCR3 register ******************/ |
| AnnaBridge | 172:65be27845400 | 14806 | #define OCTOSPI_DCR3_CSBOUND_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14807 | #define OCTOSPI_DCR3_CSBOUND_Msk (0x1FU << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 172:65be27845400 | 14808 | #define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */ |
| AnnaBridge | 172:65be27845400 | 14809 | |
| AnnaBridge | 172:65be27845400 | 14810 | /***************** Bit definition for OCTOSPI_SR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14811 | #define OCTOSPI_SR_TEF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14812 | #define OCTOSPI_SR_TEF_Msk (0x1U << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14813 | #define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */ |
| AnnaBridge | 172:65be27845400 | 14814 | #define OCTOSPI_SR_TCF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14815 | #define OCTOSPI_SR_TCF_Msk (0x1U << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14816 | #define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */ |
| AnnaBridge | 172:65be27845400 | 14817 | #define OCTOSPI_SR_FTF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 14818 | #define OCTOSPI_SR_FTF_Msk (0x1U << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14819 | #define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */ |
| AnnaBridge | 172:65be27845400 | 14820 | #define OCTOSPI_SR_SMF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14821 | #define OCTOSPI_SR_SMF_Msk (0x1U << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14822 | #define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */ |
| AnnaBridge | 172:65be27845400 | 14823 | #define OCTOSPI_SR_TOF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14824 | #define OCTOSPI_SR_TOF_Msk (0x1U << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14825 | #define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */ |
| AnnaBridge | 172:65be27845400 | 14826 | #define OCTOSPI_SR_BUSY_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 14827 | #define OCTOSPI_SR_BUSY_Msk (0x1U << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14828 | #define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */ |
| AnnaBridge | 172:65be27845400 | 14829 | #define OCTOSPI_SR_FLEVEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14830 | #define OCTOSPI_SR_FLEVEL_Msk (0x3FU << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ |
| AnnaBridge | 172:65be27845400 | 14831 | #define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */ |
| AnnaBridge | 172:65be27845400 | 14832 | |
| AnnaBridge | 172:65be27845400 | 14833 | /**************** Bit definition for OCTOSPI_FCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14834 | #define OCTOSPI_FCR_CTEF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14835 | #define OCTOSPI_FCR_CTEF_Msk (0x1U << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14836 | #define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */ |
| AnnaBridge | 172:65be27845400 | 14837 | #define OCTOSPI_FCR_CTCF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 14838 | #define OCTOSPI_FCR_CTCF_Msk (0x1U << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14839 | #define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */ |
| AnnaBridge | 172:65be27845400 | 14840 | #define OCTOSPI_FCR_CSMF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14841 | #define OCTOSPI_FCR_CSMF_Msk (0x1U << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14842 | #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ |
| AnnaBridge | 172:65be27845400 | 14843 | #define OCTOSPI_FCR_TOF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14844 | #define OCTOSPI_FCR_TOF_Msk (0x1U << OCTOSPI_FCR_TOF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14845 | #define OCTOSPI_FCR_TOF OCTOSPI_FCR_TOF_Msk /*!< Clear Timeout Flag */ |
| AnnaBridge | 172:65be27845400 | 14846 | |
| AnnaBridge | 172:65be27845400 | 14847 | /**************** Bit definition for OCTOSPI_DLR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14848 | #define OCTOSPI_DLR_DL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14849 | #define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFU << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14850 | #define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */ |
| AnnaBridge | 172:65be27845400 | 14851 | |
| AnnaBridge | 172:65be27845400 | 14852 | /***************** Bit definition for OCTOSPI_AR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14853 | #define OCTOSPI_AR_ADDRESS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14854 | #define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14855 | #define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */ |
| AnnaBridge | 172:65be27845400 | 14856 | |
| AnnaBridge | 172:65be27845400 | 14857 | /***************** Bit definition for OCTOSPI_DR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14858 | #define OCTOSPI_DR_DATA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14859 | #define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFU << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14860 | #define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */ |
| AnnaBridge | 172:65be27845400 | 14861 | |
| AnnaBridge | 172:65be27845400 | 14862 | /*************** Bit definition for OCTOSPI_PSMKR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14863 | #define OCTOSPI_PSMKR_MASK_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14864 | #define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14865 | #define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */ |
| AnnaBridge | 172:65be27845400 | 14866 | |
| AnnaBridge | 172:65be27845400 | 14867 | /*************** Bit definition for OCTOSPI_PSMAR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14868 | #define OCTOSPI_PSMAR_MATCH_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14869 | #define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14870 | #define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */ |
| AnnaBridge | 172:65be27845400 | 14871 | |
| AnnaBridge | 172:65be27845400 | 14872 | /**************** Bit definition for OCTOSPI_PIR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14873 | #define OCTOSPI_PIR_INTERVAL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14874 | #define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFU << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 14875 | #define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */ |
| AnnaBridge | 172:65be27845400 | 14876 | |
| AnnaBridge | 172:65be27845400 | 14877 | /**************** Bit definition for OCTOSPI_CCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14878 | #define OCTOSPI_CCR_IMODE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14879 | #define OCTOSPI_CCR_IMODE_Msk (0x7U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 14880 | #define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */ |
| AnnaBridge | 172:65be27845400 | 14881 | #define OCTOSPI_CCR_IMODE_0 (0x1U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14882 | #define OCTOSPI_CCR_IMODE_1 (0x2U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14883 | #define OCTOSPI_CCR_IMODE_2 (0x4U << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14884 | #define OCTOSPI_CCR_IDTR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14885 | #define OCTOSPI_CCR_IDTR_Msk (0x1U << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14886 | #define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 14887 | #define OCTOSPI_CCR_ISIZE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14888 | #define OCTOSPI_CCR_ISIZE_Msk (0x3U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 14889 | #define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */ |
| AnnaBridge | 172:65be27845400 | 14890 | #define OCTOSPI_CCR_ISIZE_0 (0x1U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14891 | #define OCTOSPI_CCR_ISIZE_1 (0x2U << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14892 | #define OCTOSPI_CCR_ADMODE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14893 | #define OCTOSPI_CCR_ADMODE_Msk (0x7U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 14894 | #define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */ |
| AnnaBridge | 172:65be27845400 | 14895 | #define OCTOSPI_CCR_ADMODE_0 (0x1U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14896 | #define OCTOSPI_CCR_ADMODE_1 (0x2U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14897 | #define OCTOSPI_CCR_ADMODE_2 (0x4U << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14898 | #define OCTOSPI_CCR_ADDTR_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14899 | #define OCTOSPI_CCR_ADDTR_Msk (0x1U << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14900 | #define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 14901 | #define OCTOSPI_CCR_ADSIZE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14902 | #define OCTOSPI_CCR_ADSIZE_Msk (0x3U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 14903 | #define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */ |
| AnnaBridge | 172:65be27845400 | 14904 | #define OCTOSPI_CCR_ADSIZE_0 (0x1U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14905 | #define OCTOSPI_CCR_ADSIZE_1 (0x2U << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14906 | #define OCTOSPI_CCR_ABMODE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14907 | #define OCTOSPI_CCR_ABMODE_Msk (0x7U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 14908 | #define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */ |
| AnnaBridge | 172:65be27845400 | 14909 | #define OCTOSPI_CCR_ABMODE_0 (0x1U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14910 | #define OCTOSPI_CCR_ABMODE_1 (0x2U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14911 | #define OCTOSPI_CCR_ABMODE_2 (0x4U << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14912 | #define OCTOSPI_CCR_ABDTR_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 14913 | #define OCTOSPI_CCR_ABDTR_Msk (0x1U << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 14914 | #define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 14915 | #define OCTOSPI_CCR_ABSIZE_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 14916 | #define OCTOSPI_CCR_ABSIZE_Msk (0x3U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 14917 | #define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */ |
| AnnaBridge | 172:65be27845400 | 14918 | #define OCTOSPI_CCR_ABSIZE_0 (0x1U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 14919 | #define OCTOSPI_CCR_ABSIZE_1 (0x2U << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 14920 | #define OCTOSPI_CCR_DMODE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 14921 | #define OCTOSPI_CCR_DMODE_Msk (0x7U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 14922 | #define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */ |
| AnnaBridge | 172:65be27845400 | 14923 | #define OCTOSPI_CCR_DMODE_0 (0x1U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 14924 | #define OCTOSPI_CCR_DMODE_1 (0x2U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 14925 | #define OCTOSPI_CCR_DMODE_2 (0x4U << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 14926 | #define OCTOSPI_CCR_DDTR_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 14927 | #define OCTOSPI_CCR_DDTR_Msk (0x1U << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 14928 | #define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 14929 | #define OCTOSPI_CCR_DQSE_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 14930 | #define OCTOSPI_CCR_DQSE_Msk (0x1U << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 14931 | #define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */ |
| AnnaBridge | 172:65be27845400 | 14932 | #define OCTOSPI_CCR_SIOO_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 14933 | #define OCTOSPI_CCR_SIOO_Msk (0x1U << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 14934 | #define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ |
| AnnaBridge | 172:65be27845400 | 14935 | |
| AnnaBridge | 172:65be27845400 | 14936 | /**************** Bit definition for OCTOSPI_TCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14937 | #define OCTOSPI_TCR_DCYC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14938 | #define OCTOSPI_TCR_DCYC_Msk (0x1FU << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 14939 | #define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */ |
| AnnaBridge | 172:65be27845400 | 14940 | #define OCTOSPI_TCR_DHQC_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 14941 | #define OCTOSPI_TCR_DHQC_Msk (0x1U << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 14942 | #define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */ |
| AnnaBridge | 172:65be27845400 | 14943 | #define OCTOSPI_TCR_SSHIFT_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 14944 | #define OCTOSPI_TCR_SSHIFT_Msk (0x1U << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 14945 | #define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */ |
| AnnaBridge | 172:65be27845400 | 14946 | |
| AnnaBridge | 172:65be27845400 | 14947 | /***************** Bit definition for OCTOSPI_IR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14948 | #define OCTOSPI_IR_INSTRUCTION_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14949 | #define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFU << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14950 | #define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */ |
| AnnaBridge | 172:65be27845400 | 14951 | |
| AnnaBridge | 172:65be27845400 | 14952 | /**************** Bit definition for OCTOSPI_ABR register *******************/ |
| AnnaBridge | 172:65be27845400 | 14953 | #define OCTOSPI_ABR_ALTERNATE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14954 | #define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 14955 | #define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */ |
| AnnaBridge | 172:65be27845400 | 14956 | |
| AnnaBridge | 172:65be27845400 | 14957 | /**************** Bit definition for OCTOSPI_LPTR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14958 | #define OCTOSPI_LPTR_TIMEOUT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14959 | #define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFU << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 14960 | #define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */ |
| AnnaBridge | 172:65be27845400 | 14961 | |
| AnnaBridge | 172:65be27845400 | 14962 | /**************** Bit definition for OCTOSPI_WCCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 14963 | #define OCTOSPI_WCCR_IMODE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 14964 | #define OCTOSPI_WCCR_IMODE_Msk (0x7U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 14965 | #define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */ |
| AnnaBridge | 172:65be27845400 | 14966 | #define OCTOSPI_WCCR_IMODE_0 (0x1U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 14967 | #define OCTOSPI_WCCR_IMODE_1 (0x2U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 14968 | #define OCTOSPI_WCCR_IMODE_2 (0x4U << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 14969 | #define OCTOSPI_WCCR_IDTR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 14970 | #define OCTOSPI_WCCR_IDTR_Msk (0x1U << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 14971 | #define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 14972 | #define OCTOSPI_WCCR_ISIZE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 14973 | #define OCTOSPI_WCCR_ISIZE_Msk (0x3U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 14974 | #define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */ |
| AnnaBridge | 172:65be27845400 | 14975 | #define OCTOSPI_WCCR_ISIZE_0 (0x1U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 14976 | #define OCTOSPI_WCCR_ISIZE_1 (0x2U << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 14977 | #define OCTOSPI_WCCR_ADMODE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 14978 | #define OCTOSPI_WCCR_ADMODE_Msk (0x7U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 14979 | #define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */ |
| AnnaBridge | 172:65be27845400 | 14980 | #define OCTOSPI_WCCR_ADMODE_0 (0x1U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 14981 | #define OCTOSPI_WCCR_ADMODE_1 (0x2U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 14982 | #define OCTOSPI_WCCR_ADMODE_2 (0x4U << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 14983 | #define OCTOSPI_WCCR_ADDTR_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 14984 | #define OCTOSPI_WCCR_ADDTR_Msk (0x1U << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 14985 | #define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 14986 | #define OCTOSPI_WCCR_ADSIZE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 14987 | #define OCTOSPI_WCCR_ADSIZE_Msk (0x3U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 14988 | #define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */ |
| AnnaBridge | 172:65be27845400 | 14989 | #define OCTOSPI_WCCR_ADSIZE_0 (0x1U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 14990 | #define OCTOSPI_WCCR_ADSIZE_1 (0x2U << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 14991 | #define OCTOSPI_WCCR_ABMODE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 14992 | #define OCTOSPI_WCCR_ABMODE_Msk (0x7U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */ |
| AnnaBridge | 172:65be27845400 | 14993 | #define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */ |
| AnnaBridge | 172:65be27845400 | 14994 | #define OCTOSPI_WCCR_ABMODE_0 (0x1U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 14995 | #define OCTOSPI_WCCR_ABMODE_1 (0x2U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 14996 | #define OCTOSPI_WCCR_ABMODE_2 (0x4U << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 14997 | #define OCTOSPI_WCCR_ABDTR_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 14998 | #define OCTOSPI_WCCR_ABDTR_Msk (0x1U << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 14999 | #define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 15000 | #define OCTOSPI_WCCR_ABSIZE_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 15001 | #define OCTOSPI_WCCR_ABSIZE_Msk (0x3U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 15002 | #define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */ |
| AnnaBridge | 172:65be27845400 | 15003 | #define OCTOSPI_WCCR_ABSIZE_0 (0x1U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 15004 | #define OCTOSPI_WCCR_ABSIZE_1 (0x2U << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 15005 | #define OCTOSPI_WCCR_DMODE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 15006 | #define OCTOSPI_WCCR_DMODE_Msk (0x7U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */ |
| AnnaBridge | 172:65be27845400 | 15007 | #define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */ |
| AnnaBridge | 172:65be27845400 | 15008 | #define OCTOSPI_WCCR_DMODE_0 (0x1U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 15009 | #define OCTOSPI_WCCR_DMODE_1 (0x2U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 15010 | #define OCTOSPI_WCCR_DMODE_2 (0x4U << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 15011 | #define OCTOSPI_WCCR_DDTR_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 15012 | #define OCTOSPI_WCCR_DDTR_Msk (0x1U << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 15013 | #define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */ |
| AnnaBridge | 172:65be27845400 | 15014 | #define OCTOSPI_WCCR_DQSE_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 15015 | #define OCTOSPI_WCCR_DQSE_Msk (0x1U << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 15016 | #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */ |
| AnnaBridge | 172:65be27845400 | 15017 | #define OCTOSPI_WCCR_SIOO_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 15018 | #define OCTOSPI_WCCR_SIOO_Msk (0x1U << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 15019 | #define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */ |
| AnnaBridge | 172:65be27845400 | 15020 | |
| AnnaBridge | 172:65be27845400 | 15021 | /**************** Bit definition for OCTOSPI_WTCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 15022 | #define OCTOSPI_WTCR_DCYC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15023 | #define OCTOSPI_WTCR_DCYC_Msk (0x1FU << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 15024 | #define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */ |
| AnnaBridge | 172:65be27845400 | 15025 | |
| AnnaBridge | 172:65be27845400 | 15026 | /**************** Bit definition for OCTOSPI_WIR register *******************/ |
| AnnaBridge | 172:65be27845400 | 15027 | #define OCTOSPI_WIR_INSTRUCTION_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15028 | #define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFU << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 15029 | #define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */ |
| AnnaBridge | 172:65be27845400 | 15030 | |
| AnnaBridge | 172:65be27845400 | 15031 | /**************** Bit definition for OCTOSPI_WABR register ******************/ |
| AnnaBridge | 172:65be27845400 | 15032 | #define OCTOSPI_WABR_ALTERNATE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15033 | #define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFU << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 15034 | #define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */ |
| AnnaBridge | 172:65be27845400 | 15035 | |
| AnnaBridge | 172:65be27845400 | 15036 | /**************** Bit definition for OCTOSPI_HLCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 15037 | #define OCTOSPI_HLCR_LM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15038 | #define OCTOSPI_HLCR_LM_Msk (0x1U << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15039 | #define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */ |
| AnnaBridge | 172:65be27845400 | 15040 | #define OCTOSPI_HLCR_WZL_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15041 | #define OCTOSPI_HLCR_WZL_Msk (0x1U << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15042 | #define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */ |
| AnnaBridge | 172:65be27845400 | 15043 | #define OCTOSPI_HLCR_TACC_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15044 | #define OCTOSPI_HLCR_TACC_Msk (0xFFU << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 15045 | #define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */ |
| AnnaBridge | 172:65be27845400 | 15046 | #define OCTOSPI_HLCR_TRWR_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15047 | #define OCTOSPI_HLCR_TRWR_Msk (0xFFU << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 15048 | #define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */ |
| AnnaBridge | 172:65be27845400 | 15049 | |
| AnnaBridge | 172:65be27845400 | 15050 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 15051 | /* */ |
| AnnaBridge | 172:65be27845400 | 15052 | /* OCTOSPIM */ |
| AnnaBridge | 172:65be27845400 | 15053 | /* */ |
| AnnaBridge | 172:65be27845400 | 15054 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 15055 | /*************** Bit definition for OCTOSPIM_PCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 15056 | #define OCTOSPIM_PCR_CLKEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15057 | #define OCTOSPIM_PCR_CLKEN_Msk (0x1U << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15058 | #define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */ |
| AnnaBridge | 172:65be27845400 | 15059 | #define OCTOSPIM_PCR_CLKSRC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15060 | #define OCTOSPIM_PCR_CLKSRC_Msk (0x1U << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15061 | #define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */ |
| AnnaBridge | 172:65be27845400 | 15062 | #define OCTOSPIM_PCR_DQSEN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15063 | #define OCTOSPIM_PCR_DQSEN_Msk (0x1U << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15064 | #define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */ |
| AnnaBridge | 172:65be27845400 | 15065 | #define OCTOSPIM_PCR_DQSSRC_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15066 | #define OCTOSPIM_PCR_DQSSRC_Msk (0x1U << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15067 | #define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */ |
| AnnaBridge | 172:65be27845400 | 15068 | #define OCTOSPIM_PCR_NCSEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15069 | #define OCTOSPIM_PCR_NCSEN_Msk (0x1U << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15070 | #define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */ |
| AnnaBridge | 172:65be27845400 | 15071 | #define OCTOSPIM_PCR_NCSSRC_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 15072 | #define OCTOSPIM_PCR_NCSSRC_Msk (0x1U << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15073 | #define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */ |
| AnnaBridge | 172:65be27845400 | 15074 | #define OCTOSPIM_PCR_IOLEN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15075 | #define OCTOSPIM_PCR_IOLEN_Msk (0x1U << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15076 | #define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */ |
| AnnaBridge | 172:65be27845400 | 15077 | #define OCTOSPIM_PCR_IOLSRC_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 15078 | #define OCTOSPIM_PCR_IOLSRC_Msk (0x3U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 172:65be27845400 | 15079 | #define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */ |
| AnnaBridge | 172:65be27845400 | 15080 | #define OCTOSPIM_PCR_IOLSRC_0 (0x1U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 15081 | #define OCTOSPIM_PCR_IOLSRC_1 (0x2U << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 15082 | #define OCTOSPIM_PCR_IOHEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 15083 | #define OCTOSPIM_PCR_IOHEN_Msk (0x1U << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 15084 | #define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */ |
| AnnaBridge | 172:65be27845400 | 15085 | #define OCTOSPIM_PCR_IOHSRC_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 15086 | #define OCTOSPIM_PCR_IOHSRC_Msk (0x3U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */ |
| AnnaBridge | 172:65be27845400 | 15087 | #define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */ |
| AnnaBridge | 172:65be27845400 | 15088 | #define OCTOSPIM_PCR_IOHSRC_0 (0x1U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 15089 | #define OCTOSPIM_PCR_IOHSRC_1 (0x2U << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 15090 | |
| AnnaBridge | 172:65be27845400 | 15091 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 15092 | /* */ |
| AnnaBridge | 172:65be27845400 | 15093 | /* SYSCFG */ |
| AnnaBridge | 172:65be27845400 | 15094 | /* */ |
| AnnaBridge | 172:65be27845400 | 15095 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 15096 | /****************** Bit definition for SYSCFG_MEMRMP register ***************/ |
| AnnaBridge | 172:65be27845400 | 15097 | #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15098 | #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 15099 | #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ |
| AnnaBridge | 172:65be27845400 | 15100 | #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15101 | #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15102 | #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15103 | |
| AnnaBridge | 172:65be27845400 | 15104 | #define SYSCFG_MEMRMP_FB_MODE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15105 | #define SYSCFG_MEMRMP_FB_MODE_Msk (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15106 | #define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< Flash Bank mode selection */ |
| AnnaBridge | 172:65be27845400 | 15107 | |
| AnnaBridge | 172:65be27845400 | 15108 | /****************** Bit definition for SYSCFG_CFGR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 15109 | #define SYSCFG_CFGR1_FWDIS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15110 | #define SYSCFG_CFGR1_FWDIS_Msk (0x1U << SYSCFG_CFGR1_FWDIS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15111 | #define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk /*!< FIREWALL access enable*/ |
| AnnaBridge | 172:65be27845400 | 15112 | #define SYSCFG_CFGR1_BOOSTEN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15113 | #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15114 | #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ |
| AnnaBridge | 172:65be27845400 | 15115 | #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15116 | #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15117 | #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15118 | #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 15119 | #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 15120 | #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15121 | #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 15122 | #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 15123 | #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15124 | #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 15125 | #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 15126 | #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15127 | #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 15128 | #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 15129 | #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15130 | #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 15131 | #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 15132 | #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15133 | #define SYSCFG_CFGR1_I2C3_FMP_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 15134 | #define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 15135 | #define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15136 | #define SYSCFG_CFGR1_I2C4_FMP_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 15137 | #define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 15138 | #define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */ |
| AnnaBridge | 172:65be27845400 | 15139 | #define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15140 | #define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15141 | #define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15142 | #define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15143 | #define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15144 | #define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */ |
| AnnaBridge | 172:65be27845400 | 15145 | |
| AnnaBridge | 172:65be27845400 | 15146 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
| AnnaBridge | 172:65be27845400 | 15147 | #define SYSCFG_EXTICR1_EXTI0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15148 | #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 15149 | #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ |
| AnnaBridge | 172:65be27845400 | 15150 | #define SYSCFG_EXTICR1_EXTI1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15151 | #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 15152 | #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ |
| AnnaBridge | 172:65be27845400 | 15153 | #define SYSCFG_EXTICR1_EXTI2_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15154 | #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 15155 | #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ |
| AnnaBridge | 172:65be27845400 | 15156 | #define SYSCFG_EXTICR1_EXTI3_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15157 | #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 15158 | #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ |
| AnnaBridge | 172:65be27845400 | 15159 | |
| AnnaBridge | 172:65be27845400 | 15160 | /** |
| AnnaBridge | 172:65be27845400 | 15161 | * @brief EXTI0 configuration |
| AnnaBridge | 172:65be27845400 | 15162 | */ |
| AnnaBridge | 172:65be27845400 | 15163 | #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15164 | #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15165 | #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15166 | #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15167 | #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15168 | #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15169 | #define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15170 | #define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U) /*!<PH[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15171 | #define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U) /*!<PI[0] pin */ |
| AnnaBridge | 172:65be27845400 | 15172 | |
| AnnaBridge | 172:65be27845400 | 15173 | /** |
| AnnaBridge | 172:65be27845400 | 15174 | * @brief EXTI1 configuration |
| AnnaBridge | 172:65be27845400 | 15175 | */ |
| AnnaBridge | 172:65be27845400 | 15176 | #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15177 | #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15178 | #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15179 | #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15180 | #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15181 | #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15182 | #define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15183 | #define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U) /*!<PH[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15184 | #define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U) /*!<PI[1] pin */ |
| AnnaBridge | 172:65be27845400 | 15185 | |
| AnnaBridge | 172:65be27845400 | 15186 | /** |
| AnnaBridge | 172:65be27845400 | 15187 | * @brief EXTI2 configuration |
| AnnaBridge | 172:65be27845400 | 15188 | */ |
| AnnaBridge | 172:65be27845400 | 15189 | #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15190 | #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15191 | #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15192 | #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15193 | #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15194 | #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15195 | #define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15196 | #define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U) /*!<PH[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15197 | #define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U) /*!<PI[2] pin */ |
| AnnaBridge | 172:65be27845400 | 15198 | |
| AnnaBridge | 172:65be27845400 | 15199 | /** |
| AnnaBridge | 172:65be27845400 | 15200 | * @brief EXTI3 configuration |
| AnnaBridge | 172:65be27845400 | 15201 | */ |
| AnnaBridge | 172:65be27845400 | 15202 | #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15203 | #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15204 | #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15205 | #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15206 | #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15207 | #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15208 | #define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15209 | #define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U) /*!<PH[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15210 | #define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U) /*!<PI[3] pin */ |
| AnnaBridge | 172:65be27845400 | 15211 | |
| AnnaBridge | 172:65be27845400 | 15212 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
| AnnaBridge | 172:65be27845400 | 15213 | #define SYSCFG_EXTICR2_EXTI4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15214 | #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 15215 | #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ |
| AnnaBridge | 172:65be27845400 | 15216 | #define SYSCFG_EXTICR2_EXTI5_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15217 | #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 15218 | #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ |
| AnnaBridge | 172:65be27845400 | 15219 | #define SYSCFG_EXTICR2_EXTI6_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15220 | #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 15221 | #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ |
| AnnaBridge | 172:65be27845400 | 15222 | #define SYSCFG_EXTICR2_EXTI7_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15223 | #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 15224 | #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ |
| AnnaBridge | 172:65be27845400 | 15225 | /** |
| AnnaBridge | 172:65be27845400 | 15226 | * @brief EXTI4 configuration |
| AnnaBridge | 172:65be27845400 | 15227 | */ |
| AnnaBridge | 172:65be27845400 | 15228 | #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15229 | #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15230 | #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15231 | #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15232 | #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15233 | #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15234 | #define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15235 | #define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U) /*!<PH[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15236 | #define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U) /*!<PI[4] pin */ |
| AnnaBridge | 172:65be27845400 | 15237 | |
| AnnaBridge | 172:65be27845400 | 15238 | /** |
| AnnaBridge | 172:65be27845400 | 15239 | * @brief EXTI5 configuration |
| AnnaBridge | 172:65be27845400 | 15240 | */ |
| AnnaBridge | 172:65be27845400 | 15241 | #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15242 | #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15243 | #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15244 | #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15245 | #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15246 | #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15247 | #define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15248 | #define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U) /*!<PH[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15249 | #define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U) /*!<PI[5] pin */ |
| AnnaBridge | 172:65be27845400 | 15250 | |
| AnnaBridge | 172:65be27845400 | 15251 | /** |
| AnnaBridge | 172:65be27845400 | 15252 | * @brief EXTI6 configuration |
| AnnaBridge | 172:65be27845400 | 15253 | */ |
| AnnaBridge | 172:65be27845400 | 15254 | #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15255 | #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15256 | #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15257 | #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15258 | #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15259 | #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15260 | #define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15261 | #define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U) /*!<PH[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15262 | #define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U) /*!<PI[6] pin */ |
| AnnaBridge | 172:65be27845400 | 15263 | |
| AnnaBridge | 172:65be27845400 | 15264 | /** |
| AnnaBridge | 172:65be27845400 | 15265 | * @brief EXTI7 configuration |
| AnnaBridge | 172:65be27845400 | 15266 | */ |
| AnnaBridge | 172:65be27845400 | 15267 | #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15268 | #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15269 | #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15270 | #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15271 | #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15272 | #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15273 | #define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15274 | #define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U) /*!<PH[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15275 | #define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U) /*!<PI[7] pin */ |
| AnnaBridge | 172:65be27845400 | 15276 | |
| AnnaBridge | 172:65be27845400 | 15277 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
| AnnaBridge | 172:65be27845400 | 15278 | #define SYSCFG_EXTICR3_EXTI8_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15279 | #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 15280 | #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ |
| AnnaBridge | 172:65be27845400 | 15281 | #define SYSCFG_EXTICR3_EXTI9_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15282 | #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 15283 | #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ |
| AnnaBridge | 172:65be27845400 | 15284 | #define SYSCFG_EXTICR3_EXTI10_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15285 | #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 15286 | #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ |
| AnnaBridge | 172:65be27845400 | 15287 | #define SYSCFG_EXTICR3_EXTI11_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15288 | #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 15289 | #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ |
| AnnaBridge | 172:65be27845400 | 15290 | |
| AnnaBridge | 172:65be27845400 | 15291 | /** |
| AnnaBridge | 172:65be27845400 | 15292 | * @brief EXTI8 configuration |
| AnnaBridge | 172:65be27845400 | 15293 | */ |
| AnnaBridge | 172:65be27845400 | 15294 | #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15295 | #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15296 | #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15297 | #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15298 | #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15299 | #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15300 | #define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15301 | #define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U) /*!<PH[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15302 | #define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U) /*!<PI[8] pin */ |
| AnnaBridge | 172:65be27845400 | 15303 | |
| AnnaBridge | 172:65be27845400 | 15304 | /** |
| AnnaBridge | 172:65be27845400 | 15305 | * @brief EXTI9 configuration |
| AnnaBridge | 172:65be27845400 | 15306 | */ |
| AnnaBridge | 172:65be27845400 | 15307 | #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15308 | #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15309 | #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15310 | #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15311 | #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15312 | #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15313 | #define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15314 | #define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U) /*!<PH[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15315 | #define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U) /*!<PI[9] pin */ |
| AnnaBridge | 172:65be27845400 | 15316 | |
| AnnaBridge | 172:65be27845400 | 15317 | /** |
| AnnaBridge | 172:65be27845400 | 15318 | * @brief EXTI10 configuration |
| AnnaBridge | 172:65be27845400 | 15319 | */ |
| AnnaBridge | 172:65be27845400 | 15320 | #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15321 | #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15322 | #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15323 | #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15324 | #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15325 | #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15326 | #define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U) /*!<PG[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15327 | #define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U) /*!<PH[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15328 | #define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U) /*!<PI[10] pin */ |
| AnnaBridge | 172:65be27845400 | 15329 | |
| AnnaBridge | 172:65be27845400 | 15330 | /** |
| AnnaBridge | 172:65be27845400 | 15331 | * @brief EXTI11 configuration |
| AnnaBridge | 172:65be27845400 | 15332 | */ |
| AnnaBridge | 172:65be27845400 | 15333 | #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15334 | #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15335 | #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15336 | #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15337 | #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15338 | #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15339 | #define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U) /*!<PG[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15340 | #define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U) /*!<PH[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15341 | #define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U) /*!<PI[11] pin */ |
| AnnaBridge | 172:65be27845400 | 15342 | |
| AnnaBridge | 172:65be27845400 | 15343 | /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ |
| AnnaBridge | 172:65be27845400 | 15344 | #define SYSCFG_EXTICR4_EXTI12_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15345 | #define SYSCFG_EXTICR4_EXTI12_Msk (0x7U << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 15346 | #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ |
| AnnaBridge | 172:65be27845400 | 15347 | #define SYSCFG_EXTICR4_EXTI13_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15348 | #define SYSCFG_EXTICR4_EXTI13_Msk (0x7U << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 15349 | #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ |
| AnnaBridge | 172:65be27845400 | 15350 | #define SYSCFG_EXTICR4_EXTI14_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15351 | #define SYSCFG_EXTICR4_EXTI14_Msk (0x7U << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */ |
| AnnaBridge | 172:65be27845400 | 15352 | #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ |
| AnnaBridge | 172:65be27845400 | 15353 | #define SYSCFG_EXTICR4_EXTI15_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15354 | #define SYSCFG_EXTICR4_EXTI15_Msk (0x7U << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 15355 | #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ |
| AnnaBridge | 172:65be27845400 | 15356 | |
| AnnaBridge | 172:65be27845400 | 15357 | /** |
| AnnaBridge | 172:65be27845400 | 15358 | * @brief EXTI12 configuration |
| AnnaBridge | 172:65be27845400 | 15359 | */ |
| AnnaBridge | 172:65be27845400 | 15360 | #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15361 | #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15362 | #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15363 | #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15364 | #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15365 | #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15366 | #define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U) /*!<PG[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15367 | #define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U) /*!<PH[12] pin */ |
| AnnaBridge | 172:65be27845400 | 15368 | |
| AnnaBridge | 172:65be27845400 | 15369 | /** |
| AnnaBridge | 172:65be27845400 | 15370 | * @brief EXTI13 configuration |
| AnnaBridge | 172:65be27845400 | 15371 | */ |
| AnnaBridge | 172:65be27845400 | 15372 | #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15373 | #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15374 | #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15375 | #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15376 | #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15377 | #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15378 | #define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U) /*!<PG[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15379 | #define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U) /*!<PH[13] pin */ |
| AnnaBridge | 172:65be27845400 | 15380 | |
| AnnaBridge | 172:65be27845400 | 15381 | /** |
| AnnaBridge | 172:65be27845400 | 15382 | * @brief EXTI14 configuration |
| AnnaBridge | 172:65be27845400 | 15383 | */ |
| AnnaBridge | 172:65be27845400 | 15384 | #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15385 | #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15386 | #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15387 | #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15388 | #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15389 | #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15390 | #define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U) /*!<PG[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15391 | #define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U) /*!<PH[14] pin */ |
| AnnaBridge | 172:65be27845400 | 15392 | |
| AnnaBridge | 172:65be27845400 | 15393 | /** |
| AnnaBridge | 172:65be27845400 | 15394 | * @brief EXTI15 configuration |
| AnnaBridge | 172:65be27845400 | 15395 | */ |
| AnnaBridge | 172:65be27845400 | 15396 | #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15397 | #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15398 | #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15399 | #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15400 | #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15401 | #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15402 | #define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U) /*!<PG[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15403 | #define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U) /*!<PH[15] pin */ |
| AnnaBridge | 172:65be27845400 | 15404 | |
| AnnaBridge | 172:65be27845400 | 15405 | /****************** Bit definition for SYSCFG_SCSR register ****************/ |
| AnnaBridge | 172:65be27845400 | 15406 | #define SYSCFG_SCSR_SRAM2ER_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15407 | #define SYSCFG_SCSR_SRAM2ER_Msk (0x1U << SYSCFG_SCSR_SRAM2ER_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15408 | #define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk /*!< SRAM2 Erase Request */ |
| AnnaBridge | 172:65be27845400 | 15409 | #define SYSCFG_SCSR_SRAM2BSY_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15410 | #define SYSCFG_SCSR_SRAM2BSY_Msk (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15411 | #define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk /*!< SRAM2 Erase Ongoing */ |
| AnnaBridge | 172:65be27845400 | 15412 | |
| AnnaBridge | 172:65be27845400 | 15413 | /****************** Bit definition for SYSCFG_CFGR2 register ****************/ |
| AnnaBridge | 172:65be27845400 | 15414 | #define SYSCFG_CFGR2_CLL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15415 | #define SYSCFG_CFGR2_CLL_Msk (0x1U << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15416 | #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */ |
| AnnaBridge | 172:65be27845400 | 15417 | #define SYSCFG_CFGR2_SPL_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15418 | #define SYSCFG_CFGR2_SPL_Msk (0x1U << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15419 | #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/ |
| AnnaBridge | 172:65be27845400 | 15420 | #define SYSCFG_CFGR2_PVDL_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15421 | #define SYSCFG_CFGR2_PVDL_Msk (0x1U << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15422 | #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */ |
| AnnaBridge | 172:65be27845400 | 15423 | #define SYSCFG_CFGR2_ECCL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15424 | #define SYSCFG_CFGR2_ECCL_Msk (0x1U << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15425 | #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/ |
| AnnaBridge | 172:65be27845400 | 15426 | #define SYSCFG_CFGR2_SPF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15427 | #define SYSCFG_CFGR2_SPF_Msk (0x1U << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15428 | #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */ |
| AnnaBridge | 172:65be27845400 | 15429 | |
| AnnaBridge | 172:65be27845400 | 15430 | /****************** Bit definition for SYSCFG_SWPR register ****************/ |
| AnnaBridge | 172:65be27845400 | 15431 | #define SYSCFG_SWPR_PAGE0_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15432 | #define SYSCFG_SWPR_PAGE0_Msk (0x1U << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15433 | #define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk /*!< SRAM2 Write protection page 0 */ |
| AnnaBridge | 172:65be27845400 | 15434 | #define SYSCFG_SWPR_PAGE1_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15435 | #define SYSCFG_SWPR_PAGE1_Msk (0x1U << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15436 | #define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk /*!< SRAM2 Write protection page 1 */ |
| AnnaBridge | 172:65be27845400 | 15437 | #define SYSCFG_SWPR_PAGE2_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15438 | #define SYSCFG_SWPR_PAGE2_Msk (0x1U << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15439 | #define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk /*!< SRAM2 Write protection page 2 */ |
| AnnaBridge | 172:65be27845400 | 15440 | #define SYSCFG_SWPR_PAGE3_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15441 | #define SYSCFG_SWPR_PAGE3_Msk (0x1U << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15442 | #define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk /*!< SRAM2 Write protection page 3 */ |
| AnnaBridge | 172:65be27845400 | 15443 | #define SYSCFG_SWPR_PAGE4_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15444 | #define SYSCFG_SWPR_PAGE4_Msk (0x1U << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15445 | #define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk /*!< SRAM2 Write protection page 4 */ |
| AnnaBridge | 172:65be27845400 | 15446 | #define SYSCFG_SWPR_PAGE5_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15447 | #define SYSCFG_SWPR_PAGE5_Msk (0x1U << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15448 | #define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk /*!< SRAM2 Write protection page 5 */ |
| AnnaBridge | 172:65be27845400 | 15449 | #define SYSCFG_SWPR_PAGE6_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 15450 | #define SYSCFG_SWPR_PAGE6_Msk (0x1U << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15451 | #define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk /*!< SRAM2 Write protection page 6 */ |
| AnnaBridge | 172:65be27845400 | 15452 | #define SYSCFG_SWPR_PAGE7_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15453 | #define SYSCFG_SWPR_PAGE7_Msk (0x1U << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15454 | #define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk /*!< SRAM2 Write protection page 7 */ |
| AnnaBridge | 172:65be27845400 | 15455 | #define SYSCFG_SWPR_PAGE8_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15456 | #define SYSCFG_SWPR_PAGE8_Msk (0x1U << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15457 | #define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk /*!< SRAM2 Write protection page 8 */ |
| AnnaBridge | 172:65be27845400 | 15458 | #define SYSCFG_SWPR_PAGE9_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 15459 | #define SYSCFG_SWPR_PAGE9_Msk (0x1U << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15460 | #define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk /*!< SRAM2 Write protection page 9 */ |
| AnnaBridge | 172:65be27845400 | 15461 | #define SYSCFG_SWPR_PAGE10_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15462 | #define SYSCFG_SWPR_PAGE10_Msk (0x1U << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15463 | #define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk /*!< SRAM2 Write protection page 10*/ |
| AnnaBridge | 172:65be27845400 | 15464 | #define SYSCFG_SWPR_PAGE11_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15465 | #define SYSCFG_SWPR_PAGE11_Msk (0x1U << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15466 | #define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk /*!< SRAM2 Write protection page 11*/ |
| AnnaBridge | 172:65be27845400 | 15467 | #define SYSCFG_SWPR_PAGE12_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15468 | #define SYSCFG_SWPR_PAGE12_Msk (0x1U << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15469 | #define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk /*!< SRAM2 Write protection page 12*/ |
| AnnaBridge | 172:65be27845400 | 15470 | #define SYSCFG_SWPR_PAGE13_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 15471 | #define SYSCFG_SWPR_PAGE13_Msk (0x1U << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15472 | #define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk /*!< SRAM2 Write protection page 13*/ |
| AnnaBridge | 172:65be27845400 | 15473 | #define SYSCFG_SWPR_PAGE14_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 15474 | #define SYSCFG_SWPR_PAGE14_Msk (0x1U << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15475 | #define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk /*!< SRAM2 Write protection page 14*/ |
| AnnaBridge | 172:65be27845400 | 15476 | #define SYSCFG_SWPR_PAGE15_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 15477 | #define SYSCFG_SWPR_PAGE15_Msk (0x1U << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 15478 | #define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk /*!< SRAM2 Write protection page 15*/ |
| AnnaBridge | 172:65be27845400 | 15479 | #define SYSCFG_SWPR_PAGE16_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15480 | #define SYSCFG_SWPR_PAGE16_Msk (0x1U << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15481 | #define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk /*!< SRAM2 Write protection page 16*/ |
| AnnaBridge | 172:65be27845400 | 15482 | #define SYSCFG_SWPR_PAGE17_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 15483 | #define SYSCFG_SWPR_PAGE17_Msk (0x1U << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 15484 | #define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk /*!< SRAM2 Write protection page 17*/ |
| AnnaBridge | 172:65be27845400 | 15485 | #define SYSCFG_SWPR_PAGE18_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 15486 | #define SYSCFG_SWPR_PAGE18_Msk (0x1U << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 15487 | #define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk /*!< SRAM2 Write protection page 18*/ |
| AnnaBridge | 172:65be27845400 | 15488 | #define SYSCFG_SWPR_PAGE19_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 15489 | #define SYSCFG_SWPR_PAGE19_Msk (0x1U << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 15490 | #define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk /*!< SRAM2 Write protection page 19*/ |
| AnnaBridge | 172:65be27845400 | 15491 | #define SYSCFG_SWPR_PAGE20_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 15492 | #define SYSCFG_SWPR_PAGE20_Msk (0x1U << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 15493 | #define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk /*!< SRAM2 Write protection page 20*/ |
| AnnaBridge | 172:65be27845400 | 15494 | #define SYSCFG_SWPR_PAGE21_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 15495 | #define SYSCFG_SWPR_PAGE21_Msk (0x1U << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 15496 | #define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk /*!< SRAM2 Write protection page 21*/ |
| AnnaBridge | 172:65be27845400 | 15497 | #define SYSCFG_SWPR_PAGE22_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 15498 | #define SYSCFG_SWPR_PAGE22_Msk (0x1U << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 15499 | #define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk /*!< SRAM2 Write protection page 22*/ |
| AnnaBridge | 172:65be27845400 | 15500 | #define SYSCFG_SWPR_PAGE23_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 15501 | #define SYSCFG_SWPR_PAGE23_Msk (0x1U << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 15502 | #define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk /*!< SRAM2 Write protection page 23*/ |
| AnnaBridge | 172:65be27845400 | 15503 | #define SYSCFG_SWPR_PAGE24_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 15504 | #define SYSCFG_SWPR_PAGE24_Msk (0x1U << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 15505 | #define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk /*!< SRAM2 Write protection page 24*/ |
| AnnaBridge | 172:65be27845400 | 15506 | #define SYSCFG_SWPR_PAGE25_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 15507 | #define SYSCFG_SWPR_PAGE25_Msk (0x1U << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 15508 | #define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk /*!< SRAM2 Write protection page 25*/ |
| AnnaBridge | 172:65be27845400 | 15509 | #define SYSCFG_SWPR_PAGE26_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 15510 | #define SYSCFG_SWPR_PAGE26_Msk (0x1U << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 15511 | #define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk /*!< SRAM2 Write protection page 26*/ |
| AnnaBridge | 172:65be27845400 | 15512 | #define SYSCFG_SWPR_PAGE27_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 15513 | #define SYSCFG_SWPR_PAGE27_Msk (0x1U << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 15514 | #define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk /*!< SRAM2 Write protection page 27*/ |
| AnnaBridge | 172:65be27845400 | 15515 | #define SYSCFG_SWPR_PAGE28_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 15516 | #define SYSCFG_SWPR_PAGE28_Msk (0x1U << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 15517 | #define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk /*!< SRAM2 Write protection page 28*/ |
| AnnaBridge | 172:65be27845400 | 15518 | #define SYSCFG_SWPR_PAGE29_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 15519 | #define SYSCFG_SWPR_PAGE29_Msk (0x1U << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 15520 | #define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk /*!< SRAM2 Write protection page 29*/ |
| AnnaBridge | 172:65be27845400 | 15521 | #define SYSCFG_SWPR_PAGE30_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 15522 | #define SYSCFG_SWPR_PAGE30_Msk (0x1U << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 15523 | #define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk /*!< SRAM2 Write protection page 30*/ |
| AnnaBridge | 172:65be27845400 | 15524 | #define SYSCFG_SWPR_PAGE31_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 15525 | #define SYSCFG_SWPR_PAGE31_Msk (0x1U << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 15526 | #define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk /*!< SRAM2 Write protection page 31*/ |
| AnnaBridge | 172:65be27845400 | 15527 | |
| AnnaBridge | 172:65be27845400 | 15528 | /****************** Bit definition for SYSCFG_SWPR2 register ***************/ |
| AnnaBridge | 172:65be27845400 | 15529 | #define SYSCFG_SWPR2_PAGE32_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15530 | #define SYSCFG_SWPR2_PAGE32_Msk (0x1U << SYSCFG_SWPR2_PAGE32_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15531 | #define SYSCFG_SWPR2_PAGE32 SYSCFG_SWPR2_PAGE32_Msk /*!< SRAM2 Write protection page 32*/ |
| AnnaBridge | 172:65be27845400 | 15532 | #define SYSCFG_SWPR2_PAGE33_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15533 | #define SYSCFG_SWPR2_PAGE33_Msk (0x1U << SYSCFG_SWPR2_PAGE33_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15534 | #define SYSCFG_SWPR2_PAGE33 SYSCFG_SWPR2_PAGE33_Msk /*!< SRAM2 Write protection page 33*/ |
| AnnaBridge | 172:65be27845400 | 15535 | #define SYSCFG_SWPR2_PAGE34_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15536 | #define SYSCFG_SWPR2_PAGE34_Msk (0x1U << SYSCFG_SWPR2_PAGE34_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15537 | #define SYSCFG_SWPR2_PAGE34 SYSCFG_SWPR2_PAGE34_Msk /*!< SRAM2 Write protection page 34*/ |
| AnnaBridge | 172:65be27845400 | 15538 | #define SYSCFG_SWPR2_PAGE35_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15539 | #define SYSCFG_SWPR2_PAGE35_Msk (0x1U << SYSCFG_SWPR2_PAGE35_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15540 | #define SYSCFG_SWPR2_PAGE35 SYSCFG_SWPR2_PAGE35_Msk /*!< SRAM2 Write protection page 35*/ |
| AnnaBridge | 172:65be27845400 | 15541 | #define SYSCFG_SWPR2_PAGE36_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15542 | #define SYSCFG_SWPR2_PAGE36_Msk (0x1U << SYSCFG_SWPR2_PAGE36_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15543 | #define SYSCFG_SWPR2_PAGE36 SYSCFG_SWPR2_PAGE36_Msk /*!< SRAM2 Write protection page 36*/ |
| AnnaBridge | 172:65be27845400 | 15544 | #define SYSCFG_SWPR2_PAGE37_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15545 | #define SYSCFG_SWPR2_PAGE37_Msk (0x1U << SYSCFG_SWPR2_PAGE37_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15546 | #define SYSCFG_SWPR2_PAGE37 SYSCFG_SWPR2_PAGE37_Msk /*!< SRAM2 Write protection page 37*/ |
| AnnaBridge | 172:65be27845400 | 15547 | #define SYSCFG_SWPR2_PAGE38_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 15548 | #define SYSCFG_SWPR2_PAGE38_Msk (0x1U << SYSCFG_SWPR2_PAGE38_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15549 | #define SYSCFG_SWPR2_PAGE38 SYSCFG_SWPR2_PAGE38_Msk /*!< SRAM2 Write protection page 38*/ |
| AnnaBridge | 172:65be27845400 | 15550 | #define SYSCFG_SWPR2_PAGE39_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15551 | #define SYSCFG_SWPR2_PAGE39_Msk (0x1U << SYSCFG_SWPR2_PAGE39_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15552 | #define SYSCFG_SWPR2_PAGE39 SYSCFG_SWPR2_PAGE39_Msk /*!< SRAM2 Write protection page 39*/ |
| AnnaBridge | 172:65be27845400 | 15553 | #define SYSCFG_SWPR2_PAGE40_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15554 | #define SYSCFG_SWPR2_PAGE40_Msk (0x1U << SYSCFG_SWPR2_PAGE40_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15555 | #define SYSCFG_SWPR2_PAGE40 SYSCFG_SWPR2_PAGE40_Msk /*!< SRAM2 Write protection page 40*/ |
| AnnaBridge | 172:65be27845400 | 15556 | #define SYSCFG_SWPR2_PAGE41_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 15557 | #define SYSCFG_SWPR2_PAGE41_Msk (0x1U << SYSCFG_SWPR2_PAGE41_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15558 | #define SYSCFG_SWPR2_PAGE41 SYSCFG_SWPR2_PAGE41_Msk /*!< SRAM2 Write protection page 41*/ |
| AnnaBridge | 172:65be27845400 | 15559 | #define SYSCFG_SWPR2_PAGE42_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15560 | #define SYSCFG_SWPR2_PAGE42_Msk (0x1U << SYSCFG_SWPR2_PAGE42_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15561 | #define SYSCFG_SWPR2_PAGE42 SYSCFG_SWPR2_PAGE42_Msk /*!< SRAM2 Write protection page 42*/ |
| AnnaBridge | 172:65be27845400 | 15562 | #define SYSCFG_SWPR2_PAGE43_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15563 | #define SYSCFG_SWPR2_PAGE43_Msk (0x1U << SYSCFG_SWPR2_PAGE43_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15564 | #define SYSCFG_SWPR2_PAGE43 SYSCFG_SWPR2_PAGE43_Msk /*!< SRAM2 Write protection page 43*/ |
| AnnaBridge | 172:65be27845400 | 15565 | #define SYSCFG_SWPR2_PAGE44_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15566 | #define SYSCFG_SWPR2_PAGE44_Msk (0x1U << SYSCFG_SWPR2_PAGE44_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15567 | #define SYSCFG_SWPR2_PAGE44 SYSCFG_SWPR2_PAGE44_Msk /*!< SRAM2 Write protection page 44*/ |
| AnnaBridge | 172:65be27845400 | 15568 | #define SYSCFG_SWPR2_PAGE45_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 15569 | #define SYSCFG_SWPR2_PAGE45_Msk (0x1U << SYSCFG_SWPR2_PAGE45_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15570 | #define SYSCFG_SWPR2_PAGE45 SYSCFG_SWPR2_PAGE45_Msk /*!< SRAM2 Write protection page 45*/ |
| AnnaBridge | 172:65be27845400 | 15571 | #define SYSCFG_SWPR2_PAGE46_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 15572 | #define SYSCFG_SWPR2_PAGE46_Msk (0x1U << SYSCFG_SWPR2_PAGE46_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15573 | #define SYSCFG_SWPR2_PAGE46 SYSCFG_SWPR2_PAGE46_Msk /*!< SRAM2 Write protection page 46*/ |
| AnnaBridge | 172:65be27845400 | 15574 | #define SYSCFG_SWPR2_PAGE47_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 15575 | #define SYSCFG_SWPR2_PAGE47_Msk (0x1U << SYSCFG_SWPR2_PAGE47_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 15576 | #define SYSCFG_SWPR2_PAGE47 SYSCFG_SWPR2_PAGE47_Msk /*!< SRAM2 Write protection page 47*/ |
| AnnaBridge | 172:65be27845400 | 15577 | #define SYSCFG_SWPR2_PAGE48_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15578 | #define SYSCFG_SWPR2_PAGE48_Msk (0x1U << SYSCFG_SWPR2_PAGE48_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15579 | #define SYSCFG_SWPR2_PAGE48 SYSCFG_SWPR2_PAGE48_Msk /*!< SRAM2 Write protection page 48*/ |
| AnnaBridge | 172:65be27845400 | 15580 | #define SYSCFG_SWPR2_PAGE49_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 15581 | #define SYSCFG_SWPR2_PAGE49_Msk (0x1U << SYSCFG_SWPR2_PAGE49_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 15582 | #define SYSCFG_SWPR2_PAGE49 SYSCFG_SWPR2_PAGE49_Msk /*!< SRAM2 Write protection page 49*/ |
| AnnaBridge | 172:65be27845400 | 15583 | #define SYSCFG_SWPR2_PAGE50_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 15584 | #define SYSCFG_SWPR2_PAGE50_Msk (0x1U << SYSCFG_SWPR2_PAGE50_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 15585 | #define SYSCFG_SWPR2_PAGE50 SYSCFG_SWPR2_PAGE50_Msk /*!< SRAM2 Write protection page 50*/ |
| AnnaBridge | 172:65be27845400 | 15586 | #define SYSCFG_SWPR2_PAGE51_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 15587 | #define SYSCFG_SWPR2_PAGE51_Msk (0x1U << SYSCFG_SWPR2_PAGE51_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 15588 | #define SYSCFG_SWPR2_PAGE51 SYSCFG_SWPR2_PAGE51_Msk /*!< SRAM2 Write protection page 51*/ |
| AnnaBridge | 172:65be27845400 | 15589 | #define SYSCFG_SWPR2_PAGE52_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 15590 | #define SYSCFG_SWPR2_PAGE52_Msk (0x1U << SYSCFG_SWPR2_PAGE52_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 15591 | #define SYSCFG_SWPR2_PAGE52 SYSCFG_SWPR2_PAGE52_Msk /*!< SRAM2 Write protection page 52*/ |
| AnnaBridge | 172:65be27845400 | 15592 | #define SYSCFG_SWPR2_PAGE53_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 15593 | #define SYSCFG_SWPR2_PAGE53_Msk (0x1U << SYSCFG_SWPR2_PAGE53_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 15594 | #define SYSCFG_SWPR2_PAGE53 SYSCFG_SWPR2_PAGE53_Msk /*!< SRAM2 Write protection page 53*/ |
| AnnaBridge | 172:65be27845400 | 15595 | #define SYSCFG_SWPR2_PAGE54_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 15596 | #define SYSCFG_SWPR2_PAGE54_Msk (0x1U << SYSCFG_SWPR2_PAGE54_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 15597 | #define SYSCFG_SWPR2_PAGE54 SYSCFG_SWPR2_PAGE54_Msk /*!< SRAM2 Write protection page 54*/ |
| AnnaBridge | 172:65be27845400 | 15598 | #define SYSCFG_SWPR2_PAGE55_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 15599 | #define SYSCFG_SWPR2_PAGE55_Msk (0x1U << SYSCFG_SWPR2_PAGE55_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 15600 | #define SYSCFG_SWPR2_PAGE55 SYSCFG_SWPR2_PAGE55_Msk /*!< SRAM2 Write protection page 55*/ |
| AnnaBridge | 172:65be27845400 | 15601 | #define SYSCFG_SWPR2_PAGE56_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 15602 | #define SYSCFG_SWPR2_PAGE56_Msk (0x1U << SYSCFG_SWPR2_PAGE56_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 15603 | #define SYSCFG_SWPR2_PAGE56 SYSCFG_SWPR2_PAGE56_Msk /*!< SRAM2 Write protection page 56*/ |
| AnnaBridge | 172:65be27845400 | 15604 | #define SYSCFG_SWPR2_PAGE57_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 15605 | #define SYSCFG_SWPR2_PAGE57_Msk (0x1U << SYSCFG_SWPR2_PAGE57_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 15606 | #define SYSCFG_SWPR2_PAGE57 SYSCFG_SWPR2_PAGE57_Msk /*!< SRAM2 Write protection page 57*/ |
| AnnaBridge | 172:65be27845400 | 15607 | #define SYSCFG_SWPR2_PAGE58_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 15608 | #define SYSCFG_SWPR2_PAGE58_Msk (0x1U << SYSCFG_SWPR2_PAGE58_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 15609 | #define SYSCFG_SWPR2_PAGE58 SYSCFG_SWPR2_PAGE58_Msk /*!< SRAM2 Write protection page 58*/ |
| AnnaBridge | 172:65be27845400 | 15610 | #define SYSCFG_SWPR2_PAGE59_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 15611 | #define SYSCFG_SWPR2_PAGE59_Msk (0x1U << SYSCFG_SWPR2_PAGE59_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 15612 | #define SYSCFG_SWPR2_PAGE59 SYSCFG_SWPR2_PAGE59_Msk /*!< SRAM2 Write protection page 59*/ |
| AnnaBridge | 172:65be27845400 | 15613 | #define SYSCFG_SWPR2_PAGE60_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 15614 | #define SYSCFG_SWPR2_PAGE60_Msk (0x1U << SYSCFG_SWPR2_PAGE60_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 15615 | #define SYSCFG_SWPR2_PAGE60 SYSCFG_SWPR2_PAGE60_Msk /*!< SRAM2 Write protection page 60*/ |
| AnnaBridge | 172:65be27845400 | 15616 | #define SYSCFG_SWPR2_PAGE61_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 15617 | #define SYSCFG_SWPR2_PAGE61_Msk (0x1U << SYSCFG_SWPR2_PAGE61_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 15618 | #define SYSCFG_SWPR2_PAGE61 SYSCFG_SWPR2_PAGE61_Msk /*!< SRAM2 Write protection page 61*/ |
| AnnaBridge | 172:65be27845400 | 15619 | #define SYSCFG_SWPR2_PAGE62_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 15620 | #define SYSCFG_SWPR2_PAGE62_Msk (0x1U << SYSCFG_SWPR2_PAGE62_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 15621 | #define SYSCFG_SWPR2_PAGE62 SYSCFG_SWPR2_PAGE62_Msk /*!< SRAM2 Write protection page 62*/ |
| AnnaBridge | 172:65be27845400 | 15622 | #define SYSCFG_SWPR2_PAGE63_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 15623 | #define SYSCFG_SWPR2_PAGE63_Msk (0x1U << SYSCFG_SWPR2_PAGE63_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 15624 | #define SYSCFG_SWPR2_PAGE63 SYSCFG_SWPR2_PAGE63_Msk /*!< SRAM2 Write protection page 63*/ |
| AnnaBridge | 172:65be27845400 | 15625 | |
| AnnaBridge | 172:65be27845400 | 15626 | /****************** Bit definition for SYSCFG_SKR register ****************/ |
| AnnaBridge | 172:65be27845400 | 15627 | #define SYSCFG_SKR_KEY_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15628 | #define SYSCFG_SKR_KEY_Msk (0xFFU << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 15629 | #define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< SRAM2 write protection key for software erase */ |
| AnnaBridge | 172:65be27845400 | 15630 | |
| AnnaBridge | 172:65be27845400 | 15631 | |
| AnnaBridge | 172:65be27845400 | 15632 | |
| AnnaBridge | 172:65be27845400 | 15633 | |
| AnnaBridge | 172:65be27845400 | 15634 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 15635 | /* */ |
| AnnaBridge | 172:65be27845400 | 15636 | /* TIM */ |
| AnnaBridge | 172:65be27845400 | 15637 | /* */ |
| AnnaBridge | 172:65be27845400 | 15638 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 15639 | /******************* Bit definition for TIM_CR1 register ********************/ |
| AnnaBridge | 172:65be27845400 | 15640 | #define TIM_CR1_CEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15641 | #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15642 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
| AnnaBridge | 172:65be27845400 | 15643 | #define TIM_CR1_UDIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15644 | #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15645 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
| AnnaBridge | 172:65be27845400 | 15646 | #define TIM_CR1_URS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15647 | #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15648 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
| AnnaBridge | 172:65be27845400 | 15649 | #define TIM_CR1_OPM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15650 | #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15651 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
| AnnaBridge | 172:65be27845400 | 15652 | #define TIM_CR1_DIR_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15653 | #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15654 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
| AnnaBridge | 172:65be27845400 | 15655 | |
| AnnaBridge | 172:65be27845400 | 15656 | #define TIM_CR1_CMS_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15657 | #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
| AnnaBridge | 172:65be27845400 | 15658 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| AnnaBridge | 172:65be27845400 | 15659 | #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15660 | #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15661 | |
| AnnaBridge | 172:65be27845400 | 15662 | #define TIM_CR1_ARPE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15663 | #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15664 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
| AnnaBridge | 172:65be27845400 | 15665 | |
| AnnaBridge | 172:65be27845400 | 15666 | #define TIM_CR1_CKD_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15667 | #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 15668 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
| AnnaBridge | 172:65be27845400 | 15669 | #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15670 | #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15671 | |
| AnnaBridge | 172:65be27845400 | 15672 | #define TIM_CR1_UIFREMAP_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15673 | #define TIM_CR1_UIFREMAP_Msk (0x1U << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15674 | #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */ |
| AnnaBridge | 172:65be27845400 | 15675 | |
| AnnaBridge | 172:65be27845400 | 15676 | /******************* Bit definition for TIM_CR2 register ********************/ |
| AnnaBridge | 172:65be27845400 | 15677 | #define TIM_CR2_CCPC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15678 | #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15679 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
| AnnaBridge | 172:65be27845400 | 15680 | #define TIM_CR2_CCUS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15681 | #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15682 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
| AnnaBridge | 172:65be27845400 | 15683 | #define TIM_CR2_CCDS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15684 | #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15685 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
| AnnaBridge | 172:65be27845400 | 15686 | |
| AnnaBridge | 172:65be27845400 | 15687 | #define TIM_CR2_MMS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15688 | #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 15689 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| AnnaBridge | 172:65be27845400 | 15690 | #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15691 | #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15692 | #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15693 | |
| AnnaBridge | 172:65be27845400 | 15694 | #define TIM_CR2_TI1S_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15695 | #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15696 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
| AnnaBridge | 172:65be27845400 | 15697 | #define TIM_CR2_OIS1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15698 | #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15699 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
| AnnaBridge | 172:65be27845400 | 15700 | #define TIM_CR2_OIS1N_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 15701 | #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15702 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
| AnnaBridge | 172:65be27845400 | 15703 | #define TIM_CR2_OIS2_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15704 | #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15705 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
| AnnaBridge | 172:65be27845400 | 15706 | #define TIM_CR2_OIS2N_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15707 | #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15708 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
| AnnaBridge | 172:65be27845400 | 15709 | #define TIM_CR2_OIS3_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15710 | #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15711 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
| AnnaBridge | 172:65be27845400 | 15712 | #define TIM_CR2_OIS3N_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 15713 | #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15714 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
| AnnaBridge | 172:65be27845400 | 15715 | #define TIM_CR2_OIS4_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 15716 | #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15717 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
| AnnaBridge | 172:65be27845400 | 15718 | #define TIM_CR2_OIS5_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15719 | #define TIM_CR2_OIS5_Msk (0x1U << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15720 | #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */ |
| AnnaBridge | 172:65be27845400 | 15721 | #define TIM_CR2_OIS6_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 15722 | #define TIM_CR2_OIS6_Msk (0x1U << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 15723 | #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */ |
| AnnaBridge | 172:65be27845400 | 15724 | |
| AnnaBridge | 172:65be27845400 | 15725 | #define TIM_CR2_MMS2_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 15726 | #define TIM_CR2_MMS2_Msk (0xFU << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 15727 | #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| AnnaBridge | 172:65be27845400 | 15728 | #define TIM_CR2_MMS2_0 (0x1U << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 15729 | #define TIM_CR2_MMS2_1 (0x2U << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 15730 | #define TIM_CR2_MMS2_2 (0x4U << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 15731 | #define TIM_CR2_MMS2_3 (0x8U << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 15732 | |
| AnnaBridge | 172:65be27845400 | 15733 | /******************* Bit definition for TIM_SMCR register *******************/ |
| AnnaBridge | 172:65be27845400 | 15734 | #define TIM_SMCR_SMS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15735 | #define TIM_SMCR_SMS_Msk (0x10007U << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */ |
| AnnaBridge | 172:65be27845400 | 15736 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
| AnnaBridge | 172:65be27845400 | 15737 | #define TIM_SMCR_SMS_0 (0x00001U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15738 | #define TIM_SMCR_SMS_1 (0x00002U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15739 | #define TIM_SMCR_SMS_2 (0x00004U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15740 | #define TIM_SMCR_SMS_3 (0x10000U << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15741 | |
| AnnaBridge | 172:65be27845400 | 15742 | #define TIM_SMCR_OCCS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15743 | #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15744 | #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ |
| AnnaBridge | 172:65be27845400 | 15745 | |
| AnnaBridge | 172:65be27845400 | 15746 | #define TIM_SMCR_TS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15747 | #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 15748 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
| AnnaBridge | 172:65be27845400 | 15749 | #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15750 | #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15751 | #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15752 | |
| AnnaBridge | 172:65be27845400 | 15753 | #define TIM_SMCR_MSM_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15754 | #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15755 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
| AnnaBridge | 172:65be27845400 | 15756 | |
| AnnaBridge | 172:65be27845400 | 15757 | #define TIM_SMCR_ETF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15758 | #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 15759 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
| AnnaBridge | 172:65be27845400 | 15760 | #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15761 | #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15762 | #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15763 | #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15764 | |
| AnnaBridge | 172:65be27845400 | 15765 | #define TIM_SMCR_ETPS_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15766 | #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 15767 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| AnnaBridge | 172:65be27845400 | 15768 | #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15769 | #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15770 | |
| AnnaBridge | 172:65be27845400 | 15771 | #define TIM_SMCR_ECE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 15772 | #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15773 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
| AnnaBridge | 172:65be27845400 | 15774 | #define TIM_SMCR_ETP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 15775 | #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 15776 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
| AnnaBridge | 172:65be27845400 | 15777 | |
| AnnaBridge | 172:65be27845400 | 15778 | /******************* Bit definition for TIM_DIER register *******************/ |
| AnnaBridge | 172:65be27845400 | 15779 | #define TIM_DIER_UIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15780 | #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15781 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15782 | #define TIM_DIER_CC1IE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15783 | #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15784 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15785 | #define TIM_DIER_CC2IE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15786 | #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15787 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15788 | #define TIM_DIER_CC3IE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15789 | #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15790 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15791 | #define TIM_DIER_CC4IE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15792 | #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15793 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15794 | #define TIM_DIER_COMIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15795 | #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15796 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15797 | #define TIM_DIER_TIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 15798 | #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15799 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15800 | #define TIM_DIER_BIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15801 | #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15802 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 15803 | #define TIM_DIER_UDE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15804 | #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15805 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15806 | #define TIM_DIER_CC1DE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 15807 | #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15808 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15809 | #define TIM_DIER_CC2DE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15810 | #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15811 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15812 | #define TIM_DIER_CC3DE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15813 | #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15814 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15815 | #define TIM_DIER_CC4DE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15816 | #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15817 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15818 | #define TIM_DIER_COMDE_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 15819 | #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15820 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15821 | #define TIM_DIER_TDE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 15822 | #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15823 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
| AnnaBridge | 172:65be27845400 | 15824 | |
| AnnaBridge | 172:65be27845400 | 15825 | /******************** Bit definition for TIM_SR register ********************/ |
| AnnaBridge | 172:65be27845400 | 15826 | #define TIM_SR_UIF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15827 | #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15828 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15829 | #define TIM_SR_CC1IF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15830 | #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15831 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15832 | #define TIM_SR_CC2IF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15833 | #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15834 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15835 | #define TIM_SR_CC3IF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15836 | #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15837 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15838 | #define TIM_SR_CC4IF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15839 | #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15840 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15841 | #define TIM_SR_COMIF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15842 | #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15843 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15844 | #define TIM_SR_TIF_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 15845 | #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15846 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15847 | #define TIM_SR_BIF_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15848 | #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15849 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15850 | #define TIM_SR_B2IF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15851 | #define TIM_SR_B2IF_Msk (0x1U << TIM_SR_B2IF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15852 | #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15853 | #define TIM_SR_CC1OF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 15854 | #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15855 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
| AnnaBridge | 172:65be27845400 | 15856 | #define TIM_SR_CC2OF_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15857 | #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15858 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
| AnnaBridge | 172:65be27845400 | 15859 | #define TIM_SR_CC3OF_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15860 | #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15861 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
| AnnaBridge | 172:65be27845400 | 15862 | #define TIM_SR_CC4OF_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15863 | #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15864 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
| AnnaBridge | 172:65be27845400 | 15865 | #define TIM_SR_SBIF_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 15866 | #define TIM_SR_SBIF_Msk (0x1U << TIM_SR_SBIF_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15867 | #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15868 | #define TIM_SR_CC5IF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 15869 | #define TIM_SR_CC5IF_Msk (0x1U << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15870 | #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15871 | #define TIM_SR_CC6IF_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 15872 | #define TIM_SR_CC6IF_Msk (0x1U << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 15873 | #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 15874 | |
| AnnaBridge | 172:65be27845400 | 15875 | |
| AnnaBridge | 172:65be27845400 | 15876 | /******************* Bit definition for TIM_EGR register ********************/ |
| AnnaBridge | 172:65be27845400 | 15877 | #define TIM_EGR_UG_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15878 | #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15879 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
| AnnaBridge | 172:65be27845400 | 15880 | #define TIM_EGR_CC1G_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 15881 | #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15882 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
| AnnaBridge | 172:65be27845400 | 15883 | #define TIM_EGR_CC2G_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15884 | #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15885 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
| AnnaBridge | 172:65be27845400 | 15886 | #define TIM_EGR_CC3G_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15887 | #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15888 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
| AnnaBridge | 172:65be27845400 | 15889 | #define TIM_EGR_CC4G_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15890 | #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15891 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
| AnnaBridge | 172:65be27845400 | 15892 | #define TIM_EGR_COMG_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 15893 | #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15894 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
| AnnaBridge | 172:65be27845400 | 15895 | #define TIM_EGR_TG_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 15896 | #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15897 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
| AnnaBridge | 172:65be27845400 | 15898 | #define TIM_EGR_BG_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15899 | #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15900 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
| AnnaBridge | 172:65be27845400 | 15901 | #define TIM_EGR_B2G_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15902 | #define TIM_EGR_B2G_Msk (0x1U << TIM_EGR_B2G_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15903 | #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */ |
| AnnaBridge | 172:65be27845400 | 15904 | |
| AnnaBridge | 172:65be27845400 | 15905 | |
| AnnaBridge | 172:65be27845400 | 15906 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 15907 | #define TIM_CCMR1_CC1S_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15908 | #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 15909 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| AnnaBridge | 172:65be27845400 | 15910 | #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15911 | #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15912 | |
| AnnaBridge | 172:65be27845400 | 15913 | #define TIM_CCMR1_OC1FE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15914 | #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15915 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
| AnnaBridge | 172:65be27845400 | 15916 | #define TIM_CCMR1_OC1PE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15917 | #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15918 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
| AnnaBridge | 172:65be27845400 | 15919 | |
| AnnaBridge | 172:65be27845400 | 15920 | #define TIM_CCMR1_OC1M_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15921 | #define TIM_CCMR1_OC1M_Msk (0x1007U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */ |
| AnnaBridge | 172:65be27845400 | 15922 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| AnnaBridge | 172:65be27845400 | 15923 | #define TIM_CCMR1_OC1M_0 (0x0001U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15924 | #define TIM_CCMR1_OC1M_1 (0x0002U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15925 | #define TIM_CCMR1_OC1M_2 (0x0004U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15926 | #define TIM_CCMR1_OC1M_3 (0x1000U << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 15927 | |
| AnnaBridge | 172:65be27845400 | 15928 | #define TIM_CCMR1_OC1CE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 15929 | #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15930 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */ |
| AnnaBridge | 172:65be27845400 | 15931 | |
| AnnaBridge | 172:65be27845400 | 15932 | #define TIM_CCMR1_CC2S_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 15933 | #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 15934 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| AnnaBridge | 172:65be27845400 | 15935 | #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 15936 | #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 15937 | |
| AnnaBridge | 172:65be27845400 | 15938 | #define TIM_CCMR1_OC2FE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15939 | #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15940 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
| AnnaBridge | 172:65be27845400 | 15941 | #define TIM_CCMR1_OC2PE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 15942 | #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15943 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
| AnnaBridge | 172:65be27845400 | 15944 | |
| AnnaBridge | 172:65be27845400 | 15945 | #define TIM_CCMR1_OC2M_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15946 | #define TIM_CCMR1_OC2M_Msk (0x1007U << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */ |
| AnnaBridge | 172:65be27845400 | 15947 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| AnnaBridge | 172:65be27845400 | 15948 | #define TIM_CCMR1_OC2M_0 (0x0001U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15949 | #define TIM_CCMR1_OC2M_1 (0x0002U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15950 | #define TIM_CCMR1_OC2M_2 (0x0004U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15951 | #define TIM_CCMR1_OC2M_3 (0x1000U << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 15952 | |
| AnnaBridge | 172:65be27845400 | 15953 | #define TIM_CCMR1_OC2CE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 15954 | #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 15955 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
| AnnaBridge | 172:65be27845400 | 15956 | |
| AnnaBridge | 172:65be27845400 | 15957 | /*----------------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 15958 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15959 | #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 15960 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| AnnaBridge | 172:65be27845400 | 15961 | #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15962 | #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15963 | |
| AnnaBridge | 172:65be27845400 | 15964 | #define TIM_CCMR1_IC1F_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 15965 | #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 15966 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| AnnaBridge | 172:65be27845400 | 15967 | #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 15968 | #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 15969 | #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 15970 | #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 15971 | |
| AnnaBridge | 172:65be27845400 | 15972 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 15973 | #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 15974 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| AnnaBridge | 172:65be27845400 | 15975 | #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 15976 | #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 15977 | |
| AnnaBridge | 172:65be27845400 | 15978 | #define TIM_CCMR1_IC2F_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 15979 | #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 15980 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| AnnaBridge | 172:65be27845400 | 15981 | #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 15982 | #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 15983 | #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 15984 | #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 15985 | |
| AnnaBridge | 172:65be27845400 | 15986 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 15987 | #define TIM_CCMR2_CC3S_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 15988 | #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 15989 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| AnnaBridge | 172:65be27845400 | 15990 | #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 15991 | #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 15992 | |
| AnnaBridge | 172:65be27845400 | 15993 | #define TIM_CCMR2_OC3FE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 15994 | #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 15995 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
| AnnaBridge | 172:65be27845400 | 15996 | #define TIM_CCMR2_OC3PE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 15997 | #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 15998 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
| AnnaBridge | 172:65be27845400 | 15999 | |
| AnnaBridge | 172:65be27845400 | 16000 | #define TIM_CCMR2_OC3M_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16001 | #define TIM_CCMR2_OC3M_Msk (0x1007U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */ |
| AnnaBridge | 172:65be27845400 | 16002 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| AnnaBridge | 172:65be27845400 | 16003 | #define TIM_CCMR2_OC3M_0 (0x0001U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16004 | #define TIM_CCMR2_OC3M_1 (0x0002U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16005 | #define TIM_CCMR2_OC3M_2 (0x0004U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16006 | #define TIM_CCMR2_OC3M_3 (0x1000U << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16007 | |
| AnnaBridge | 172:65be27845400 | 16008 | #define TIM_CCMR2_OC3CE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 16009 | #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16010 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
| AnnaBridge | 172:65be27845400 | 16011 | |
| AnnaBridge | 172:65be27845400 | 16012 | #define TIM_CCMR2_CC4S_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16013 | #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 16014 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| AnnaBridge | 172:65be27845400 | 16015 | #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16016 | #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16017 | |
| AnnaBridge | 172:65be27845400 | 16018 | #define TIM_CCMR2_OC4FE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16019 | #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16020 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
| AnnaBridge | 172:65be27845400 | 16021 | #define TIM_CCMR2_OC4PE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16022 | #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16023 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
| AnnaBridge | 172:65be27845400 | 16024 | |
| AnnaBridge | 172:65be27845400 | 16025 | #define TIM_CCMR2_OC4M_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16026 | #define TIM_CCMR2_OC4M_Msk (0x1007U << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */ |
| AnnaBridge | 172:65be27845400 | 16027 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| AnnaBridge | 172:65be27845400 | 16028 | #define TIM_CCMR2_OC4M_0 (0x0001U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16029 | #define TIM_CCMR2_OC4M_1 (0x0002U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16030 | #define TIM_CCMR2_OC4M_2 (0x0004U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16031 | #define TIM_CCMR2_OC4M_3 (0x1000U << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 16032 | |
| AnnaBridge | 172:65be27845400 | 16033 | #define TIM_CCMR2_OC4CE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16034 | #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16035 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
| AnnaBridge | 172:65be27845400 | 16036 | |
| AnnaBridge | 172:65be27845400 | 16037 | /*----------------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 16038 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16039 | #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 16040 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| AnnaBridge | 172:65be27845400 | 16041 | #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16042 | #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16043 | |
| AnnaBridge | 172:65be27845400 | 16044 | #define TIM_CCMR2_IC3F_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16045 | #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
| AnnaBridge | 172:65be27845400 | 16046 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| AnnaBridge | 172:65be27845400 | 16047 | #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16048 | #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16049 | #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16050 | #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16051 | |
| AnnaBridge | 172:65be27845400 | 16052 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16053 | #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 16054 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| AnnaBridge | 172:65be27845400 | 16055 | #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16056 | #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16057 | |
| AnnaBridge | 172:65be27845400 | 16058 | #define TIM_CCMR2_IC4F_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16059 | #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
| AnnaBridge | 172:65be27845400 | 16060 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| AnnaBridge | 172:65be27845400 | 16061 | #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16062 | #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16063 | #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16064 | #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16065 | |
| AnnaBridge | 172:65be27845400 | 16066 | /****************** Bit definition for TIM_CCMR3 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16067 | #define TIM_CCMR3_OC5FE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16068 | #define TIM_CCMR3_OC5FE_Msk (0x1U << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16069 | #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */ |
| AnnaBridge | 172:65be27845400 | 16070 | #define TIM_CCMR3_OC5PE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16071 | #define TIM_CCMR3_OC5PE_Msk (0x1U << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16072 | #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */ |
| AnnaBridge | 172:65be27845400 | 16073 | |
| AnnaBridge | 172:65be27845400 | 16074 | #define TIM_CCMR3_OC5M_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16075 | #define TIM_CCMR3_OC5M_Msk (0x1007U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */ |
| AnnaBridge | 172:65be27845400 | 16076 | #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ |
| AnnaBridge | 172:65be27845400 | 16077 | #define TIM_CCMR3_OC5M_0 (0x0001U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16078 | #define TIM_CCMR3_OC5M_1 (0x0002U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16079 | #define TIM_CCMR3_OC5M_2 (0x0004U << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16080 | #define TIM_CCMR3_OC5M_3 (0x1000U << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16081 | |
| AnnaBridge | 172:65be27845400 | 16082 | #define TIM_CCMR3_OC5CE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 16083 | #define TIM_CCMR3_OC5CE_Msk (0x1U << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16084 | #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */ |
| AnnaBridge | 172:65be27845400 | 16085 | |
| AnnaBridge | 172:65be27845400 | 16086 | #define TIM_CCMR3_OC6FE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16087 | #define TIM_CCMR3_OC6FE_Msk (0x1U << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16088 | #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */ |
| AnnaBridge | 172:65be27845400 | 16089 | #define TIM_CCMR3_OC6PE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16090 | #define TIM_CCMR3_OC6PE_Msk (0x1U << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16091 | #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */ |
| AnnaBridge | 172:65be27845400 | 16092 | |
| AnnaBridge | 172:65be27845400 | 16093 | #define TIM_CCMR3_OC6M_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16094 | #define TIM_CCMR3_OC6M_Msk (0x1007U << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */ |
| AnnaBridge | 172:65be27845400 | 16095 | #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ |
| AnnaBridge | 172:65be27845400 | 16096 | #define TIM_CCMR3_OC6M_0 (0x0001U << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16097 | #define TIM_CCMR3_OC6M_1 (0x0002U << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16098 | #define TIM_CCMR3_OC6M_2 (0x0004U << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16099 | #define TIM_CCMR3_OC6M_3 (0x1000U << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 16100 | |
| AnnaBridge | 172:65be27845400 | 16101 | #define TIM_CCMR3_OC6CE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16102 | #define TIM_CCMR3_OC6CE_Msk (0x1U << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16103 | #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */ |
| AnnaBridge | 172:65be27845400 | 16104 | |
| AnnaBridge | 172:65be27845400 | 16105 | /******************* Bit definition for TIM_CCER register *******************/ |
| AnnaBridge | 172:65be27845400 | 16106 | #define TIM_CCER_CC1E_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16107 | #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16108 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
| AnnaBridge | 172:65be27845400 | 16109 | #define TIM_CCER_CC1P_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16110 | #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16111 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16112 | #define TIM_CCER_CC1NE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16113 | #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16114 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
| AnnaBridge | 172:65be27845400 | 16115 | #define TIM_CCER_CC1NP_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16116 | #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16117 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16118 | #define TIM_CCER_CC2E_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16119 | #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16120 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
| AnnaBridge | 172:65be27845400 | 16121 | #define TIM_CCER_CC2P_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 16122 | #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16123 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16124 | #define TIM_CCER_CC2NE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 16125 | #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16126 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
| AnnaBridge | 172:65be27845400 | 16127 | #define TIM_CCER_CC2NP_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 16128 | #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16129 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16130 | #define TIM_CCER_CC3E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16131 | #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16132 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
| AnnaBridge | 172:65be27845400 | 16133 | #define TIM_CCER_CC3P_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16134 | #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16135 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16136 | #define TIM_CCER_CC3NE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16137 | #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16138 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
| AnnaBridge | 172:65be27845400 | 16139 | #define TIM_CCER_CC3NP_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16140 | #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16141 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16142 | #define TIM_CCER_CC4E_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16143 | #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16144 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
| AnnaBridge | 172:65be27845400 | 16145 | #define TIM_CCER_CC4P_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 16146 | #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16147 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16148 | #define TIM_CCER_CC4NP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16149 | #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16150 | #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16151 | #define TIM_CCER_CC5E_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 16152 | #define TIM_CCER_CC5E_Msk (0x1U << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16153 | #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */ |
| AnnaBridge | 172:65be27845400 | 16154 | #define TIM_CCER_CC5P_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 16155 | #define TIM_CCER_CC5P_Msk (0x1U << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 16156 | #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16157 | #define TIM_CCER_CC6E_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 16158 | #define TIM_CCER_CC6E_Msk (0x1U << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 16159 | #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */ |
| AnnaBridge | 172:65be27845400 | 16160 | #define TIM_CCER_CC6P_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 16161 | #define TIM_CCER_CC6P_Msk (0x1U << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 16162 | #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */ |
| AnnaBridge | 172:65be27845400 | 16163 | |
| AnnaBridge | 172:65be27845400 | 16164 | /******************* Bit definition for TIM_CNT register ********************/ |
| AnnaBridge | 172:65be27845400 | 16165 | #define TIM_CNT_CNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16166 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 16167 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
| AnnaBridge | 172:65be27845400 | 16168 | #define TIM_CNT_UIFCPY_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 16169 | #define TIM_CNT_UIFCPY_Msk (0x1U << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 16170 | #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */ |
| AnnaBridge | 172:65be27845400 | 16171 | |
| AnnaBridge | 172:65be27845400 | 16172 | /******************* Bit definition for TIM_PSC register ********************/ |
| AnnaBridge | 172:65be27845400 | 16173 | #define TIM_PSC_PSC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16174 | #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16175 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
| AnnaBridge | 172:65be27845400 | 16176 | |
| AnnaBridge | 172:65be27845400 | 16177 | /******************* Bit definition for TIM_ARR register ********************/ |
| AnnaBridge | 172:65be27845400 | 16178 | #define TIM_ARR_ARR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16179 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 16180 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */ |
| AnnaBridge | 172:65be27845400 | 16181 | |
| AnnaBridge | 172:65be27845400 | 16182 | /******************* Bit definition for TIM_RCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 16183 | #define TIM_RCR_REP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16184 | #define TIM_RCR_REP_Msk (0xFFFFU << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16185 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
| AnnaBridge | 172:65be27845400 | 16186 | |
| AnnaBridge | 172:65be27845400 | 16187 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16188 | #define TIM_CCR1_CCR1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16189 | #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16190 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
| AnnaBridge | 172:65be27845400 | 16191 | |
| AnnaBridge | 172:65be27845400 | 16192 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16193 | #define TIM_CCR2_CCR2_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16194 | #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16195 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
| AnnaBridge | 172:65be27845400 | 16196 | |
| AnnaBridge | 172:65be27845400 | 16197 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16198 | #define TIM_CCR3_CCR3_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16199 | #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16200 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
| AnnaBridge | 172:65be27845400 | 16201 | |
| AnnaBridge | 172:65be27845400 | 16202 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16203 | #define TIM_CCR4_CCR4_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16204 | #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16205 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
| AnnaBridge | 172:65be27845400 | 16206 | |
| AnnaBridge | 172:65be27845400 | 16207 | /******************* Bit definition for TIM_CCR5 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16208 | #define TIM_CCR5_CCR5_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16209 | #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 16210 | #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */ |
| AnnaBridge | 172:65be27845400 | 16211 | #define TIM_CCR5_GC5C1_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 16212 | #define TIM_CCR5_GC5C1_Msk (0x1U << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 16213 | #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */ |
| AnnaBridge | 172:65be27845400 | 16214 | #define TIM_CCR5_GC5C2_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 16215 | #define TIM_CCR5_GC5C2_Msk (0x1U << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 16216 | #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */ |
| AnnaBridge | 172:65be27845400 | 16217 | #define TIM_CCR5_GC5C3_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 16218 | #define TIM_CCR5_GC5C3_Msk (0x1U << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 16219 | #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */ |
| AnnaBridge | 172:65be27845400 | 16220 | |
| AnnaBridge | 172:65be27845400 | 16221 | /******************* Bit definition for TIM_CCR6 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16222 | #define TIM_CCR6_CCR6_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16223 | #define TIM_CCR6_CCR6_Msk (0xFFFFU << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16224 | #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */ |
| AnnaBridge | 172:65be27845400 | 16225 | |
| AnnaBridge | 172:65be27845400 | 16226 | /******************* Bit definition for TIM_BDTR register *******************/ |
| AnnaBridge | 172:65be27845400 | 16227 | #define TIM_BDTR_DTG_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16228 | #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 16229 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| AnnaBridge | 172:65be27845400 | 16230 | #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16231 | #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16232 | #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16233 | #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16234 | #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16235 | #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16236 | #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16237 | #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16238 | |
| AnnaBridge | 172:65be27845400 | 16239 | #define TIM_BDTR_LOCK_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16240 | #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 16241 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
| AnnaBridge | 172:65be27845400 | 16242 | #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16243 | #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16244 | |
| AnnaBridge | 172:65be27845400 | 16245 | #define TIM_BDTR_OSSI_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16246 | #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16247 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
| AnnaBridge | 172:65be27845400 | 16248 | #define TIM_BDTR_OSSR_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16249 | #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16250 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
| AnnaBridge | 172:65be27845400 | 16251 | #define TIM_BDTR_BKE_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16252 | #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16253 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */ |
| AnnaBridge | 172:65be27845400 | 16254 | #define TIM_BDTR_BKP_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 16255 | #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16256 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */ |
| AnnaBridge | 172:65be27845400 | 16257 | #define TIM_BDTR_AOE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16258 | #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16259 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
| AnnaBridge | 172:65be27845400 | 16260 | #define TIM_BDTR_MOE_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16261 | #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16262 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
| AnnaBridge | 172:65be27845400 | 16263 | |
| AnnaBridge | 172:65be27845400 | 16264 | #define TIM_BDTR_BKF_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 16265 | #define TIM_BDTR_BKF_Msk (0xFU << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */ |
| AnnaBridge | 172:65be27845400 | 16266 | #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */ |
| AnnaBridge | 172:65be27845400 | 16267 | #define TIM_BDTR_BK2F_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 16268 | #define TIM_BDTR_BK2F_Msk (0xFU << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */ |
| AnnaBridge | 172:65be27845400 | 16269 | #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */ |
| AnnaBridge | 172:65be27845400 | 16270 | |
| AnnaBridge | 172:65be27845400 | 16271 | #define TIM_BDTR_BK2E_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 16272 | #define TIM_BDTR_BK2E_Msk (0x1U << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 16273 | #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */ |
| AnnaBridge | 172:65be27845400 | 16274 | #define TIM_BDTR_BK2P_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 16275 | #define TIM_BDTR_BK2P_Msk (0x1U << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 16276 | #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */ |
| AnnaBridge | 172:65be27845400 | 16277 | |
| AnnaBridge | 172:65be27845400 | 16278 | /******************* Bit definition for TIM_DCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 16279 | #define TIM_DCR_DBA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16280 | #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16281 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
| AnnaBridge | 172:65be27845400 | 16282 | #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16283 | #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16284 | #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16285 | #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16286 | #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16287 | |
| AnnaBridge | 172:65be27845400 | 16288 | #define TIM_DCR_DBL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16289 | #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16290 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
| AnnaBridge | 172:65be27845400 | 16291 | #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16292 | #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16293 | #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16294 | #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16295 | #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16296 | |
| AnnaBridge | 172:65be27845400 | 16297 | /******************* Bit definition for TIM_DMAR register *******************/ |
| AnnaBridge | 172:65be27845400 | 16298 | #define TIM_DMAR_DMAB_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16299 | #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16300 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
| AnnaBridge | 172:65be27845400 | 16301 | |
| AnnaBridge | 172:65be27845400 | 16302 | /******************* Bit definition for TIM1_OR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16303 | #define TIM1_OR1_ETR_ADC1_RMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16304 | #define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 16305 | #define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */ |
| AnnaBridge | 172:65be27845400 | 16306 | #define TIM1_OR1_ETR_ADC1_RMP_0 (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16307 | #define TIM1_OR1_ETR_ADC1_RMP_1 (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16308 | |
| AnnaBridge | 172:65be27845400 | 16309 | #define TIM1_OR1_TI1_RMP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16310 | #define TIM1_OR1_TI1_RMP_Msk (0x1U << TIM1_OR1_TI1_RMP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16311 | #define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk /*!<TIM1 Input Capture 1 remap */ |
| AnnaBridge | 172:65be27845400 | 16312 | |
| AnnaBridge | 172:65be27845400 | 16313 | /******************* Bit definition for TIM1_OR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16314 | #define TIM1_OR2_BKINE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16315 | #define TIM1_OR2_BKINE_Msk (0x1U << TIM1_OR2_BKINE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16316 | #define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk /*!<BRK BKIN input enable */ |
| AnnaBridge | 172:65be27845400 | 16317 | #define TIM1_OR2_BKCMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16318 | #define TIM1_OR2_BKCMP1E_Msk (0x1U << TIM1_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16319 | #define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16320 | #define TIM1_OR2_BKCMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16321 | #define TIM1_OR2_BKCMP2E_Msk (0x1U << TIM1_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16322 | #define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16323 | #define TIM1_OR2_BKDF1BK0E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16324 | #define TIM1_OR2_BKDF1BK0E_Msk (0x1U << TIM1_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16325 | #define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */ |
| AnnaBridge | 172:65be27845400 | 16326 | #define TIM1_OR2_BKINP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16327 | #define TIM1_OR2_BKINP_Msk (0x1U << TIM1_OR2_BKINP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16328 | #define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ |
| AnnaBridge | 172:65be27845400 | 16329 | #define TIM1_OR2_BKCMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16330 | #define TIM1_OR2_BKCMP1P_Msk (0x1U << TIM1_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16331 | #define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16332 | #define TIM1_OR2_BKCMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16333 | #define TIM1_OR2_BKCMP2P_Msk (0x1U << TIM1_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16334 | #define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16335 | |
| AnnaBridge | 172:65be27845400 | 16336 | #define TIM1_OR2_ETRSEL_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16337 | #define TIM1_OR2_ETRSEL_Msk (0x7U << TIM1_OR2_ETRSEL_Pos) /*!< 0x0001C000 */ |
| AnnaBridge | 172:65be27845400 | 16338 | #define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */ |
| AnnaBridge | 172:65be27845400 | 16339 | #define TIM1_OR2_ETRSEL_0 (0x1U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16340 | #define TIM1_OR2_ETRSEL_1 (0x2U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16341 | #define TIM1_OR2_ETRSEL_2 (0x4U << TIM1_OR2_ETRSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16342 | |
| AnnaBridge | 172:65be27845400 | 16343 | /******************* Bit definition for TIM1_OR3 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16344 | #define TIM1_OR3_BK2INE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16345 | #define TIM1_OR3_BK2INE_Msk (0x1U << TIM1_OR3_BK2INE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16346 | #define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ |
| AnnaBridge | 172:65be27845400 | 16347 | #define TIM1_OR3_BK2CMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16348 | #define TIM1_OR3_BK2CMP1E_Msk (0x1U << TIM1_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16349 | #define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16350 | #define TIM1_OR3_BK2CMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16351 | #define TIM1_OR3_BK2CMP2E_Msk (0x1U << TIM1_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16352 | #define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16353 | #define TIM1_OR3_BK2DF1BK1E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16354 | #define TIM1_OR3_BK2DF1BK1E_Msk (0x1U << TIM1_OR3_BK2DF1BK1E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16355 | #define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk /*!<BRK2 DFSDM1_BREAK[1] enable */ |
| AnnaBridge | 172:65be27845400 | 16356 | #define TIM1_OR3_BK2INP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16357 | #define TIM1_OR3_BK2INP_Msk (0x1U << TIM1_OR3_BK2INP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16358 | #define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16359 | #define TIM1_OR3_BK2CMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16360 | #define TIM1_OR3_BK2CMP1P_Msk (0x1U << TIM1_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16361 | #define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16362 | #define TIM1_OR3_BK2CMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16363 | #define TIM1_OR3_BK2CMP2P_Msk (0x1U << TIM1_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16364 | #define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16365 | |
| AnnaBridge | 172:65be27845400 | 16366 | /******************* Bit definition for TIM8_OR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16367 | #define TIM8_OR1_TI1_RMP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16368 | #define TIM8_OR1_TI1_RMP_Msk (0x1U << TIM8_OR1_TI1_RMP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16369 | #define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk /*!<TIM8 Input Capture 1 remap */ |
| AnnaBridge | 172:65be27845400 | 16370 | |
| AnnaBridge | 172:65be27845400 | 16371 | /******************* Bit definition for TIM8_OR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16372 | #define TIM8_OR2_BKINE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16373 | #define TIM8_OR2_BKINE_Msk (0x1U << TIM8_OR2_BKINE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16374 | #define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk /*!<BRK BKIN input enable */ |
| AnnaBridge | 172:65be27845400 | 16375 | #define TIM8_OR2_BKCMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16376 | #define TIM8_OR2_BKCMP1E_Msk (0x1U << TIM8_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16377 | #define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16378 | #define TIM8_OR2_BKCMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16379 | #define TIM8_OR2_BKCMP2E_Msk (0x1U << TIM8_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16380 | #define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16381 | #define TIM8_OR2_BKDF1BK2E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16382 | #define TIM8_OR2_BKDF1BK2E_Msk (0x1U << TIM8_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16383 | #define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */ |
| AnnaBridge | 172:65be27845400 | 16384 | #define TIM8_OR2_BKINP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16385 | #define TIM8_OR2_BKINP_Msk (0x1U << TIM8_OR2_BKINP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16386 | #define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ |
| AnnaBridge | 172:65be27845400 | 16387 | #define TIM8_OR2_BKCMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16388 | #define TIM8_OR2_BKCMP1P_Msk (0x1U << TIM8_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16389 | #define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16390 | #define TIM8_OR2_BKCMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16391 | #define TIM8_OR2_BKCMP2P_Msk (0x1U << TIM8_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16392 | #define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16393 | |
| AnnaBridge | 172:65be27845400 | 16394 | #define TIM8_OR2_ETRSEL_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16395 | #define TIM8_OR2_ETRSEL_Msk (0x7U << TIM8_OR2_ETRSEL_Pos) /*!< 0x0001C000 */ |
| AnnaBridge | 172:65be27845400 | 16396 | #define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */ |
| AnnaBridge | 172:65be27845400 | 16397 | #define TIM8_OR2_ETRSEL_0 (0x1U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16398 | #define TIM8_OR2_ETRSEL_1 (0x2U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16399 | #define TIM8_OR2_ETRSEL_2 (0x4U << TIM8_OR2_ETRSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16400 | |
| AnnaBridge | 172:65be27845400 | 16401 | /******************* Bit definition for TIM8_OR3 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16402 | #define TIM8_OR3_BK2INE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16403 | #define TIM8_OR3_BK2INE_Msk (0x1U << TIM8_OR3_BK2INE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16404 | #define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk /*!<BRK2 BKIN2 input enable */ |
| AnnaBridge | 172:65be27845400 | 16405 | #define TIM8_OR3_BK2CMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16406 | #define TIM8_OR3_BK2CMP1E_Msk (0x1U << TIM8_OR3_BK2CMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16407 | #define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16408 | #define TIM8_OR3_BK2CMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16409 | #define TIM8_OR3_BK2CMP2E_Msk (0x1U << TIM8_OR3_BK2CMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16410 | #define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16411 | #define TIM8_OR3_BK2DF1BK3E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16412 | #define TIM8_OR3_BK2DF1BK3E_Msk (0x1U << TIM8_OR3_BK2DF1BK3E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16413 | #define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk /*!<BRK2 DFSDM1_BREAK[3] enable */ |
| AnnaBridge | 172:65be27845400 | 16414 | #define TIM8_OR3_BK2INP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16415 | #define TIM8_OR3_BK2INP_Msk (0x1U << TIM8_OR3_BK2INP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16416 | #define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16417 | #define TIM8_OR3_BK2CMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16418 | #define TIM8_OR3_BK2CMP1P_Msk (0x1U << TIM8_OR3_BK2CMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16419 | #define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16420 | #define TIM8_OR3_BK2CMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16421 | #define TIM8_OR3_BK2CMP2P_Msk (0x1U << TIM8_OR3_BK2CMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16422 | #define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16423 | |
| AnnaBridge | 172:65be27845400 | 16424 | /******************* Bit definition for TIM2_OR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16425 | #define TIM2_OR1_ITR1_RMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16426 | #define TIM2_OR1_ITR1_RMP_Msk (0x1U << TIM2_OR1_ITR1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16427 | #define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */ |
| AnnaBridge | 172:65be27845400 | 16428 | #define TIM2_OR1_ETR1_RMP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16429 | #define TIM2_OR1_ETR1_RMP_Msk (0x1U << TIM2_OR1_ETR1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16430 | #define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk /*!<TIM2 External trigger 1 remap */ |
| AnnaBridge | 172:65be27845400 | 16431 | |
| AnnaBridge | 172:65be27845400 | 16432 | #define TIM2_OR1_TI4_RMP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16433 | #define TIM2_OR1_TI4_RMP_Msk (0x3U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 16434 | #define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */ |
| AnnaBridge | 172:65be27845400 | 16435 | #define TIM2_OR1_TI4_RMP_0 (0x1U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16436 | #define TIM2_OR1_TI4_RMP_1 (0x2U << TIM2_OR1_TI4_RMP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16437 | |
| AnnaBridge | 172:65be27845400 | 16438 | /******************* Bit definition for TIM2_OR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16439 | #define TIM2_OR2_ETRSEL_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16440 | #define TIM2_OR2_ETRSEL_Msk (0x7U << TIM2_OR2_ETRSEL_Pos) /*!< 0x0001C000 */ |
| AnnaBridge | 172:65be27845400 | 16441 | #define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */ |
| AnnaBridge | 172:65be27845400 | 16442 | #define TIM2_OR2_ETRSEL_0 (0x1U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16443 | #define TIM2_OR2_ETRSEL_1 (0x2U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16444 | #define TIM2_OR2_ETRSEL_2 (0x4U << TIM2_OR2_ETRSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16445 | |
| AnnaBridge | 172:65be27845400 | 16446 | /******************* Bit definition for TIM3_OR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16447 | #define TIM3_OR1_TI1_RMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16448 | #define TIM3_OR1_TI1_RMP_Msk (0x3U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 16449 | #define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */ |
| AnnaBridge | 172:65be27845400 | 16450 | #define TIM3_OR1_TI1_RMP_0 (0x1U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16451 | #define TIM3_OR1_TI1_RMP_1 (0x2U << TIM3_OR1_TI1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16452 | |
| AnnaBridge | 172:65be27845400 | 16453 | /******************* Bit definition for TIM3_OR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 16454 | #define TIM3_OR2_ETRSEL_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16455 | #define TIM3_OR2_ETRSEL_Msk (0x7U << TIM3_OR2_ETRSEL_Pos) /*!< 0x0001C000 */ |
| AnnaBridge | 172:65be27845400 | 16456 | #define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */ |
| AnnaBridge | 172:65be27845400 | 16457 | #define TIM3_OR2_ETRSEL_0 (0x1U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16458 | #define TIM3_OR2_ETRSEL_1 (0x2U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16459 | #define TIM3_OR2_ETRSEL_2 (0x4U << TIM3_OR2_ETRSEL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16460 | |
| AnnaBridge | 172:65be27845400 | 16461 | /******************* Bit definition for TIM15_OR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 16462 | #define TIM15_OR1_TI1_RMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16463 | #define TIM15_OR1_TI1_RMP_Msk (0x1U << TIM15_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16464 | #define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk /*!<TIM15 Input Capture 1 remap */ |
| AnnaBridge | 172:65be27845400 | 16465 | |
| AnnaBridge | 172:65be27845400 | 16466 | #define TIM15_OR1_ENCODER_MODE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16467 | #define TIM15_OR1_ENCODER_MODE_Msk (0x3U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 172:65be27845400 | 16468 | #define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */ |
| AnnaBridge | 172:65be27845400 | 16469 | #define TIM15_OR1_ENCODER_MODE_0 (0x1U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16470 | #define TIM15_OR1_ENCODER_MODE_1 (0x2U << TIM15_OR1_ENCODER_MODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16471 | |
| AnnaBridge | 172:65be27845400 | 16472 | /******************* Bit definition for TIM15_OR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 16473 | #define TIM15_OR2_BKINE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16474 | #define TIM15_OR2_BKINE_Msk (0x1U << TIM15_OR2_BKINE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16475 | #define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk /*!<BRK BKIN input enable */ |
| AnnaBridge | 172:65be27845400 | 16476 | #define TIM15_OR2_BKCMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16477 | #define TIM15_OR2_BKCMP1E_Msk (0x1U << TIM15_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16478 | #define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16479 | #define TIM15_OR2_BKCMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16480 | #define TIM15_OR2_BKCMP2E_Msk (0x1U << TIM15_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16481 | #define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16482 | #define TIM15_OR2_BKDF1BK0E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16483 | #define TIM15_OR2_BKDF1BK0E_Msk (0x1U << TIM15_OR2_BKDF1BK0E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16484 | #define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk /*!<BRK DFSDM1_BREAK[0] enable */ |
| AnnaBridge | 172:65be27845400 | 16485 | #define TIM15_OR2_BKINP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16486 | #define TIM15_OR2_BKINP_Msk (0x1U << TIM15_OR2_BKINP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16487 | #define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ |
| AnnaBridge | 172:65be27845400 | 16488 | #define TIM15_OR2_BKCMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16489 | #define TIM15_OR2_BKCMP1P_Msk (0x1U << TIM15_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16490 | #define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16491 | #define TIM15_OR2_BKCMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16492 | #define TIM15_OR2_BKCMP2P_Msk (0x1U << TIM15_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16493 | #define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16494 | |
| AnnaBridge | 172:65be27845400 | 16495 | /******************* Bit definition for TIM16_OR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 16496 | #define TIM16_OR1_TI1_RMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16497 | #define TIM16_OR1_TI1_RMP_Msk (0x3U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 16498 | #define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */ |
| AnnaBridge | 172:65be27845400 | 16499 | #define TIM16_OR1_TI1_RMP_0 (0x1U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16500 | #define TIM16_OR1_TI1_RMP_1 (0x2U << TIM16_OR1_TI1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16501 | |
| AnnaBridge | 172:65be27845400 | 16502 | /******************* Bit definition for TIM16_OR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 16503 | #define TIM16_OR2_BKINE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16504 | #define TIM16_OR2_BKINE_Msk (0x1U << TIM16_OR2_BKINE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16505 | #define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk /*!<BRK BKIN input enable */ |
| AnnaBridge | 172:65be27845400 | 16506 | #define TIM16_OR2_BKCMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16507 | #define TIM16_OR2_BKCMP1E_Msk (0x1U << TIM16_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16508 | #define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16509 | #define TIM16_OR2_BKCMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16510 | #define TIM16_OR2_BKCMP2E_Msk (0x1U << TIM16_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16511 | #define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16512 | #define TIM16_OR2_BKDF1BK1E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16513 | #define TIM16_OR2_BKDF1BK1E_Msk (0x1U << TIM16_OR2_BKDF1BK1E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16514 | #define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk /*!<BRK DFSDM1_BREAK[1] enable */ |
| AnnaBridge | 172:65be27845400 | 16515 | #define TIM16_OR2_BKINP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16516 | #define TIM16_OR2_BKINP_Msk (0x1U << TIM16_OR2_BKINP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16517 | #define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ |
| AnnaBridge | 172:65be27845400 | 16518 | #define TIM16_OR2_BKCMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16519 | #define TIM16_OR2_BKCMP1P_Msk (0x1U << TIM16_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16520 | #define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16521 | #define TIM16_OR2_BKCMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16522 | #define TIM16_OR2_BKCMP2P_Msk (0x1U << TIM16_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16523 | #define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16524 | |
| AnnaBridge | 172:65be27845400 | 16525 | /******************* Bit definition for TIM17_OR1 register ******************/ |
| AnnaBridge | 172:65be27845400 | 16526 | #define TIM17_OR1_TI1_RMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16527 | #define TIM17_OR1_TI1_RMP_Msk (0x3U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 16528 | #define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */ |
| AnnaBridge | 172:65be27845400 | 16529 | #define TIM17_OR1_TI1_RMP_0 (0x1U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16530 | #define TIM17_OR1_TI1_RMP_1 (0x2U << TIM17_OR1_TI1_RMP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16531 | |
| AnnaBridge | 172:65be27845400 | 16532 | /******************* Bit definition for TIM17_OR2 register ******************/ |
| AnnaBridge | 172:65be27845400 | 16533 | #define TIM17_OR2_BKINE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16534 | #define TIM17_OR2_BKINE_Msk (0x1U << TIM17_OR2_BKINE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16535 | #define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk /*!<BRK BKIN input enable */ |
| AnnaBridge | 172:65be27845400 | 16536 | #define TIM17_OR2_BKCMP1E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16537 | #define TIM17_OR2_BKCMP1E_Msk (0x1U << TIM17_OR2_BKCMP1E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16538 | #define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk /*!<BRK COMP1 enable */ |
| AnnaBridge | 172:65be27845400 | 16539 | #define TIM17_OR2_BKCMP2E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16540 | #define TIM17_OR2_BKCMP2E_Msk (0x1U << TIM17_OR2_BKCMP2E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16541 | #define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk /*!<BRK COMP2 enable */ |
| AnnaBridge | 172:65be27845400 | 16542 | #define TIM17_OR2_BKDF1BK2E_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16543 | #define TIM17_OR2_BKDF1BK2E_Msk (0x1U << TIM17_OR2_BKDF1BK2E_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16544 | #define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk /*!<BRK DFSDM1_BREAK[2] enable */ |
| AnnaBridge | 172:65be27845400 | 16545 | #define TIM17_OR2_BKINP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16546 | #define TIM17_OR2_BKINP_Msk (0x1U << TIM17_OR2_BKINP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16547 | #define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk /*!<BRK BKIN input polarity */ |
| AnnaBridge | 172:65be27845400 | 16548 | #define TIM17_OR2_BKCMP1P_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16549 | #define TIM17_OR2_BKCMP1P_Msk (0x1U << TIM17_OR2_BKCMP1P_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16550 | #define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk /*!<BRK COMP1 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16551 | #define TIM17_OR2_BKCMP2P_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 16552 | #define TIM17_OR2_BKCMP2P_Msk (0x1U << TIM17_OR2_BKCMP2P_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16553 | #define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk /*!<BRK COMP2 input polarity */ |
| AnnaBridge | 172:65be27845400 | 16554 | |
| AnnaBridge | 172:65be27845400 | 16555 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16556 | /* */ |
| AnnaBridge | 172:65be27845400 | 16557 | /* Low Power Timer (LPTTIM) */ |
| AnnaBridge | 172:65be27845400 | 16558 | /* */ |
| AnnaBridge | 172:65be27845400 | 16559 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16560 | /****************** Bit definition for LPTIM_ISR register *******************/ |
| AnnaBridge | 172:65be27845400 | 16561 | #define LPTIM_ISR_CMPM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16562 | #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16563 | #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ |
| AnnaBridge | 172:65be27845400 | 16564 | #define LPTIM_ISR_ARRM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16565 | #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16566 | #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ |
| AnnaBridge | 172:65be27845400 | 16567 | #define LPTIM_ISR_EXTTRIG_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16568 | #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16569 | #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ |
| AnnaBridge | 172:65be27845400 | 16570 | #define LPTIM_ISR_CMPOK_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16571 | #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16572 | #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ |
| AnnaBridge | 172:65be27845400 | 16573 | #define LPTIM_ISR_ARROK_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16574 | #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16575 | #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ |
| AnnaBridge | 172:65be27845400 | 16576 | #define LPTIM_ISR_UP_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 16577 | #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16578 | #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ |
| AnnaBridge | 172:65be27845400 | 16579 | #define LPTIM_ISR_DOWN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 16580 | #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16581 | #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ |
| AnnaBridge | 172:65be27845400 | 16582 | |
| AnnaBridge | 172:65be27845400 | 16583 | /****************** Bit definition for LPTIM_ICR register *******************/ |
| AnnaBridge | 172:65be27845400 | 16584 | #define LPTIM_ICR_CMPMCF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16585 | #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16586 | #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16587 | #define LPTIM_ICR_ARRMCF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16588 | #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16589 | #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16590 | #define LPTIM_ICR_EXTTRIGCF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16591 | #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16592 | #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16593 | #define LPTIM_ICR_CMPOKCF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16594 | #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16595 | #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16596 | #define LPTIM_ICR_ARROKCF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16597 | #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16598 | #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16599 | #define LPTIM_ICR_UPCF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 16600 | #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16601 | #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16602 | #define LPTIM_ICR_DOWNCF_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 16603 | #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16604 | #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 16605 | |
| AnnaBridge | 172:65be27845400 | 16606 | /****************** Bit definition for LPTIM_IER register ********************/ |
| AnnaBridge | 172:65be27845400 | 16607 | #define LPTIM_IER_CMPMIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16608 | #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16609 | #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16610 | #define LPTIM_IER_ARRMIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16611 | #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16612 | #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16613 | #define LPTIM_IER_EXTTRIGIE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16614 | #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16615 | #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16616 | #define LPTIM_IER_CMPOKIE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16617 | #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16618 | #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16619 | #define LPTIM_IER_ARROKIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16620 | #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16621 | #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16622 | #define LPTIM_IER_UPIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 16623 | #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16624 | #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16625 | #define LPTIM_IER_DOWNIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 16626 | #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16627 | #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 16628 | |
| AnnaBridge | 172:65be27845400 | 16629 | /****************** Bit definition for LPTIM_CFGR register *******************/ |
| AnnaBridge | 172:65be27845400 | 16630 | #define LPTIM_CFGR_CKSEL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16631 | #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16632 | #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ |
| AnnaBridge | 172:65be27845400 | 16633 | |
| AnnaBridge | 172:65be27845400 | 16634 | #define LPTIM_CFGR_CKPOL_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16635 | #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 172:65be27845400 | 16636 | #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ |
| AnnaBridge | 172:65be27845400 | 16637 | #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16638 | #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16639 | |
| AnnaBridge | 172:65be27845400 | 16640 | #define LPTIM_CFGR_CKFLT_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16641 | #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ |
| AnnaBridge | 172:65be27845400 | 16642 | #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ |
| AnnaBridge | 172:65be27845400 | 16643 | #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16644 | #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16645 | |
| AnnaBridge | 172:65be27845400 | 16646 | #define LPTIM_CFGR_TRGFLT_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 16647 | #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 16648 | #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ |
| AnnaBridge | 172:65be27845400 | 16649 | #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16650 | #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16651 | |
| AnnaBridge | 172:65be27845400 | 16652 | #define LPTIM_CFGR_PRESC_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16653 | #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ |
| AnnaBridge | 172:65be27845400 | 16654 | #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ |
| AnnaBridge | 172:65be27845400 | 16655 | #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16656 | #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16657 | #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 16658 | |
| AnnaBridge | 172:65be27845400 | 16659 | #define LPTIM_CFGR_TRIGSEL_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 16660 | #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ |
| AnnaBridge | 172:65be27845400 | 16661 | #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ |
| AnnaBridge | 172:65be27845400 | 16662 | #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16663 | #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16664 | #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16665 | |
| AnnaBridge | 172:65be27845400 | 16666 | #define LPTIM_CFGR_TRIGEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 16667 | #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 172:65be27845400 | 16668 | #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ |
| AnnaBridge | 172:65be27845400 | 16669 | #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 16670 | #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 16671 | |
| AnnaBridge | 172:65be27845400 | 16672 | #define LPTIM_CFGR_TIMOUT_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 16673 | #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 16674 | #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ |
| AnnaBridge | 172:65be27845400 | 16675 | #define LPTIM_CFGR_WAVE_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 16676 | #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 16677 | #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ |
| AnnaBridge | 172:65be27845400 | 16678 | #define LPTIM_CFGR_WAVPOL_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 16679 | #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 16680 | #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ |
| AnnaBridge | 172:65be27845400 | 16681 | #define LPTIM_CFGR_PRELOAD_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 16682 | #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 16683 | #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ |
| AnnaBridge | 172:65be27845400 | 16684 | #define LPTIM_CFGR_COUNTMODE_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 16685 | #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 16686 | #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ |
| AnnaBridge | 172:65be27845400 | 16687 | #define LPTIM_CFGR_ENC_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 16688 | #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 16689 | #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ |
| AnnaBridge | 172:65be27845400 | 16690 | |
| AnnaBridge | 172:65be27845400 | 16691 | /****************** Bit definition for LPTIM_CR register ********************/ |
| AnnaBridge | 172:65be27845400 | 16692 | #define LPTIM_CR_ENABLE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16693 | #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16694 | #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ |
| AnnaBridge | 172:65be27845400 | 16695 | #define LPTIM_CR_SNGSTRT_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16696 | #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16697 | #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ |
| AnnaBridge | 172:65be27845400 | 16698 | #define LPTIM_CR_CNTSTRT_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16699 | #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16700 | #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ |
| AnnaBridge | 172:65be27845400 | 16701 | |
| AnnaBridge | 172:65be27845400 | 16702 | /****************** Bit definition for LPTIM_CMP register *******************/ |
| AnnaBridge | 172:65be27845400 | 16703 | #define LPTIM_CMP_CMP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16704 | #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16705 | #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ |
| AnnaBridge | 172:65be27845400 | 16706 | |
| AnnaBridge | 172:65be27845400 | 16707 | /****************** Bit definition for LPTIM_ARR register *******************/ |
| AnnaBridge | 172:65be27845400 | 16708 | #define LPTIM_ARR_ARR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16709 | #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16710 | #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ |
| AnnaBridge | 172:65be27845400 | 16711 | |
| AnnaBridge | 172:65be27845400 | 16712 | /****************** Bit definition for LPTIM_CNT register *******************/ |
| AnnaBridge | 172:65be27845400 | 16713 | #define LPTIM_CNT_CNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16714 | #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 16715 | #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ |
| AnnaBridge | 172:65be27845400 | 16716 | |
| AnnaBridge | 172:65be27845400 | 16717 | /****************** Bit definition for LPTIM_OR register ********************/ |
| AnnaBridge | 172:65be27845400 | 16718 | #define LPTIM_OR_OR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16719 | #define LPTIM_OR_OR_Msk (0x3U << LPTIM_OR_OR_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 16720 | #define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */ |
| AnnaBridge | 172:65be27845400 | 16721 | #define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16722 | #define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16723 | |
| AnnaBridge | 172:65be27845400 | 16724 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16725 | /* */ |
| AnnaBridge | 172:65be27845400 | 16726 | /* Analog Comparators (COMP) */ |
| AnnaBridge | 172:65be27845400 | 16727 | /* */ |
| AnnaBridge | 172:65be27845400 | 16728 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16729 | /********************** Bit definition for COMP_CSR register ****************/ |
| AnnaBridge | 172:65be27845400 | 16730 | #define COMP_CSR_EN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16731 | #define COMP_CSR_EN_Msk (0x1U << COMP_CSR_EN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16732 | #define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ |
| AnnaBridge | 172:65be27845400 | 16733 | |
| AnnaBridge | 172:65be27845400 | 16734 | #define COMP_CSR_PWRMODE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16735 | #define COMP_CSR_PWRMODE_Msk (0x3U << COMP_CSR_PWRMODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 16736 | #define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ |
| AnnaBridge | 172:65be27845400 | 16737 | #define COMP_CSR_PWRMODE_0 (0x1U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16738 | #define COMP_CSR_PWRMODE_1 (0x2U << COMP_CSR_PWRMODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16739 | |
| AnnaBridge | 172:65be27845400 | 16740 | #define COMP_CSR_INMSEL_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16741 | #define COMP_CSR_INMSEL_Msk (0x7U << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 16742 | #define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ |
| AnnaBridge | 172:65be27845400 | 16743 | #define COMP_CSR_INMSEL_0 (0x1U << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16744 | #define COMP_CSR_INMSEL_1 (0x2U << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16745 | #define COMP_CSR_INMSEL_2 (0x4U << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16746 | |
| AnnaBridge | 172:65be27845400 | 16747 | #define COMP_CSR_INPSEL_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 16748 | #define COMP_CSR_INPSEL_Msk (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16749 | #define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ |
| AnnaBridge | 172:65be27845400 | 16750 | #define COMP_CSR_INPSEL_0 (0x1U << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16751 | |
| AnnaBridge | 172:65be27845400 | 16752 | #define COMP_CSR_WINMODE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 16753 | #define COMP_CSR_WINMODE_Msk (0x1U << COMP_CSR_WINMODE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16754 | #define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ |
| AnnaBridge | 172:65be27845400 | 16755 | |
| AnnaBridge | 172:65be27845400 | 16756 | #define COMP_CSR_POLARITY_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16757 | #define COMP_CSR_POLARITY_Msk (0x1U << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16758 | #define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ |
| AnnaBridge | 172:65be27845400 | 16759 | |
| AnnaBridge | 172:65be27845400 | 16760 | #define COMP_CSR_HYST_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 16761 | #define COMP_CSR_HYST_Msk (0x3U << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ |
| AnnaBridge | 172:65be27845400 | 16762 | #define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */ |
| AnnaBridge | 172:65be27845400 | 16763 | #define COMP_CSR_HYST_0 (0x1U << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 16764 | #define COMP_CSR_HYST_1 (0x2U << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 16765 | |
| AnnaBridge | 172:65be27845400 | 16766 | #define COMP_CSR_BLANKING_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 16767 | #define COMP_CSR_BLANKING_Msk (0x7U << COMP_CSR_BLANKING_Pos) /*!< 0x001C0000 */ |
| AnnaBridge | 172:65be27845400 | 16768 | #define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */ |
| AnnaBridge | 172:65be27845400 | 16769 | #define COMP_CSR_BLANKING_0 (0x1U << COMP_CSR_BLANKING_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 16770 | #define COMP_CSR_BLANKING_1 (0x2U << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 16771 | #define COMP_CSR_BLANKING_2 (0x4U << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 16772 | |
| AnnaBridge | 172:65be27845400 | 16773 | #define COMP_CSR_BRGEN_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 16774 | #define COMP_CSR_BRGEN_Msk (0x1U << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 16775 | #define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator voltage scaler enable */ |
| AnnaBridge | 172:65be27845400 | 16776 | #define COMP_CSR_SCALEN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 16777 | #define COMP_CSR_SCALEN_Msk (0x1U << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 16778 | #define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator scaler bridge enable */ |
| AnnaBridge | 172:65be27845400 | 16779 | |
| AnnaBridge | 172:65be27845400 | 16780 | #define COMP_CSR_VALUE_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 16781 | #define COMP_CSR_VALUE_Msk (0x1U << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 16782 | #define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ |
| AnnaBridge | 172:65be27845400 | 16783 | |
| AnnaBridge | 172:65be27845400 | 16784 | #define COMP_CSR_LOCK_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 16785 | #define COMP_CSR_LOCK_Msk (0x1U << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 16786 | #define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ |
| AnnaBridge | 172:65be27845400 | 16787 | |
| AnnaBridge | 172:65be27845400 | 16788 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16789 | /* */ |
| AnnaBridge | 172:65be27845400 | 16790 | /* Operational Amplifier (OPAMP) */ |
| AnnaBridge | 172:65be27845400 | 16791 | /* */ |
| AnnaBridge | 172:65be27845400 | 16792 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16793 | /********************* Bit definition for OPAMPx_CSR register ***************/ |
| AnnaBridge | 172:65be27845400 | 16794 | #define OPAMP_CSR_OPAMPxEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16795 | #define OPAMP_CSR_OPAMPxEN_Msk (0x1U << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16796 | #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ |
| AnnaBridge | 172:65be27845400 | 16797 | #define OPAMP_CSR_OPALPM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16798 | #define OPAMP_CSR_OPALPM_Msk (0x1U << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16799 | #define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ |
| AnnaBridge | 172:65be27845400 | 16800 | |
| AnnaBridge | 172:65be27845400 | 16801 | #define OPAMP_CSR_OPAMODE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16802 | #define OPAMP_CSR_OPAMODE_Msk (0x3U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 16803 | #define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ |
| AnnaBridge | 172:65be27845400 | 16804 | #define OPAMP_CSR_OPAMODE_0 (0x1U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16805 | #define OPAMP_CSR_OPAMODE_1 (0x2U << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16806 | |
| AnnaBridge | 172:65be27845400 | 16807 | #define OPAMP_CSR_PGGAIN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16808 | #define OPAMP_CSR_PGGAIN_Msk (0x3U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 16809 | #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ |
| AnnaBridge | 172:65be27845400 | 16810 | #define OPAMP_CSR_PGGAIN_0 (0x1U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16811 | #define OPAMP_CSR_PGGAIN_1 (0x2U << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16812 | |
| AnnaBridge | 172:65be27845400 | 16813 | #define OPAMP_CSR_VMSEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16814 | #define OPAMP_CSR_VMSEL_Msk (0x3U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 16815 | #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 172:65be27845400 | 16816 | #define OPAMP_CSR_VMSEL_0 (0x1U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16817 | #define OPAMP_CSR_VMSEL_1 (0x2U << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16818 | |
| AnnaBridge | 172:65be27845400 | 16819 | #define OPAMP_CSR_VPSEL_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16820 | #define OPAMP_CSR_VPSEL_Msk (0x1U << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16821 | #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */ |
| AnnaBridge | 172:65be27845400 | 16822 | #define OPAMP_CSR_CALON_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16823 | #define OPAMP_CSR_CALON_Msk (0x1U << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16824 | #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 172:65be27845400 | 16825 | #define OPAMP_CSR_CALSEL_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 16826 | #define OPAMP_CSR_CALSEL_Msk (0x1U << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16827 | #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 172:65be27845400 | 16828 | #define OPAMP_CSR_USERTRIM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16829 | #define OPAMP_CSR_USERTRIM_Msk (0x1U << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16830 | #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 172:65be27845400 | 16831 | #define OPAMP_CSR_CALOUT_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16832 | #define OPAMP_CSR_CALOUT_Msk (0x1U << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16833 | #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */ |
| AnnaBridge | 172:65be27845400 | 16834 | |
| AnnaBridge | 172:65be27845400 | 16835 | /********************* Bit definition for OPAMP1_CSR register ***************/ |
| AnnaBridge | 172:65be27845400 | 16836 | #define OPAMP1_CSR_OPAEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16837 | #define OPAMP1_CSR_OPAEN_Msk (0x1U << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16838 | #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */ |
| AnnaBridge | 172:65be27845400 | 16839 | #define OPAMP1_CSR_OPALPM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16840 | #define OPAMP1_CSR_OPALPM_Msk (0x1U << OPAMP1_CSR_OPALPM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16841 | #define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk /*!< Operational amplifier1 Low Power Mode */ |
| AnnaBridge | 172:65be27845400 | 16842 | |
| AnnaBridge | 172:65be27845400 | 16843 | #define OPAMP1_CSR_OPAMODE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16844 | #define OPAMP1_CSR_OPAMODE_Msk (0x3U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 16845 | #define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk /*!< Operational amplifier1 PGA mode */ |
| AnnaBridge | 172:65be27845400 | 16846 | #define OPAMP1_CSR_OPAMODE_0 (0x1U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16847 | #define OPAMP1_CSR_OPAMODE_1 (0x2U << OPAMP1_CSR_OPAMODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16848 | |
| AnnaBridge | 172:65be27845400 | 16849 | #define OPAMP1_CSR_PGAGAIN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16850 | #define OPAMP1_CSR_PGAGAIN_Msk (0x3U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 16851 | #define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */ |
| AnnaBridge | 172:65be27845400 | 16852 | #define OPAMP1_CSR_PGAGAIN_0 (0x1U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16853 | #define OPAMP1_CSR_PGAGAIN_1 (0x2U << OPAMP1_CSR_PGAGAIN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16854 | |
| AnnaBridge | 172:65be27845400 | 16855 | #define OPAMP1_CSR_VMSEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16856 | #define OPAMP1_CSR_VMSEL_Msk (0x3U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 16857 | #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 172:65be27845400 | 16858 | #define OPAMP1_CSR_VMSEL_0 (0x1U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16859 | #define OPAMP1_CSR_VMSEL_1 (0x2U << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16860 | |
| AnnaBridge | 172:65be27845400 | 16861 | #define OPAMP1_CSR_VPSEL_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16862 | #define OPAMP1_CSR_VPSEL_Msk (0x1U << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16863 | #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */ |
| AnnaBridge | 172:65be27845400 | 16864 | #define OPAMP1_CSR_CALON_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16865 | #define OPAMP1_CSR_CALON_Msk (0x1U << OPAMP1_CSR_CALON_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16866 | #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 172:65be27845400 | 16867 | #define OPAMP1_CSR_CALSEL_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 16868 | #define OPAMP1_CSR_CALSEL_Msk (0x1U << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16869 | #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 172:65be27845400 | 16870 | #define OPAMP1_CSR_USERTRIM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16871 | #define OPAMP1_CSR_USERTRIM_Msk (0x1U << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16872 | #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 172:65be27845400 | 16873 | #define OPAMP1_CSR_CALOUT_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16874 | #define OPAMP1_CSR_CALOUT_Msk (0x1U << OPAMP1_CSR_CALOUT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16875 | #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */ |
| AnnaBridge | 172:65be27845400 | 16876 | |
| AnnaBridge | 172:65be27845400 | 16877 | #define OPAMP1_CSR_OPARANGE_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 16878 | #define OPAMP1_CSR_OPARANGE_Msk (0x1U << OPAMP1_CSR_OPARANGE_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 16879 | #define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */ |
| AnnaBridge | 172:65be27845400 | 16880 | |
| AnnaBridge | 172:65be27845400 | 16881 | /********************* Bit definition for OPAMP2_CSR register ***************/ |
| AnnaBridge | 172:65be27845400 | 16882 | #define OPAMP2_CSR_OPAEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16883 | #define OPAMP2_CSR_OPAEN_Msk (0x1U << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16884 | #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */ |
| AnnaBridge | 172:65be27845400 | 16885 | #define OPAMP2_CSR_OPALPM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16886 | #define OPAMP2_CSR_OPALPM_Msk (0x1U << OPAMP2_CSR_OPALPM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16887 | #define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk /*!< Operational amplifier2 Low Power Mode */ |
| AnnaBridge | 172:65be27845400 | 16888 | |
| AnnaBridge | 172:65be27845400 | 16889 | #define OPAMP2_CSR_OPAMODE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16890 | #define OPAMP2_CSR_OPAMODE_Msk (0x3U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x0000000C */ |
| AnnaBridge | 172:65be27845400 | 16891 | #define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk /*!< Operational amplifier2 PGA mode */ |
| AnnaBridge | 172:65be27845400 | 16892 | #define OPAMP2_CSR_OPAMODE_0 (0x1U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16893 | #define OPAMP2_CSR_OPAMODE_1 (0x2U << OPAMP2_CSR_OPAMODE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16894 | |
| AnnaBridge | 172:65be27845400 | 16895 | #define OPAMP2_CSR_PGAGAIN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16896 | #define OPAMP2_CSR_PGAGAIN_Msk (0x3U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000030 */ |
| AnnaBridge | 172:65be27845400 | 16897 | #define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */ |
| AnnaBridge | 172:65be27845400 | 16898 | #define OPAMP2_CSR_PGAGAIN_0 (0x1U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16899 | #define OPAMP2_CSR_PGAGAIN_1 (0x2U << OPAMP2_CSR_PGAGAIN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16900 | |
| AnnaBridge | 172:65be27845400 | 16901 | #define OPAMP2_CSR_VMSEL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16902 | #define OPAMP2_CSR_VMSEL_Msk (0x3U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000300 */ |
| AnnaBridge | 172:65be27845400 | 16903 | #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */ |
| AnnaBridge | 172:65be27845400 | 16904 | #define OPAMP2_CSR_VMSEL_0 (0x1U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 16905 | #define OPAMP2_CSR_VMSEL_1 (0x2U << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 16906 | |
| AnnaBridge | 172:65be27845400 | 16907 | #define OPAMP2_CSR_VPSEL_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 16908 | #define OPAMP2_CSR_VPSEL_Msk (0x1U << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 16909 | #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */ |
| AnnaBridge | 172:65be27845400 | 16910 | #define OPAMP2_CSR_CALON_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 16911 | #define OPAMP2_CSR_CALON_Msk (0x1U << OPAMP2_CSR_CALON_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 16912 | #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */ |
| AnnaBridge | 172:65be27845400 | 16913 | #define OPAMP2_CSR_CALSEL_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 16914 | #define OPAMP2_CSR_CALSEL_Msk (0x1U << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 16915 | #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */ |
| AnnaBridge | 172:65be27845400 | 16916 | #define OPAMP2_CSR_USERTRIM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 16917 | #define OPAMP2_CSR_USERTRIM_Msk (0x1U << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 16918 | #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */ |
| AnnaBridge | 172:65be27845400 | 16919 | #define OPAMP2_CSR_CALOUT_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 16920 | #define OPAMP2_CSR_CALOUT_Msk (0x1U << OPAMP2_CSR_CALOUT_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 16921 | #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */ |
| AnnaBridge | 172:65be27845400 | 16922 | |
| AnnaBridge | 172:65be27845400 | 16923 | /******************* Bit definition for OPAMP_OTR register ******************/ |
| AnnaBridge | 172:65be27845400 | 16924 | #define OPAMP_OTR_TRIMOFFSETN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16925 | #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16926 | #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16927 | #define OPAMP_OTR_TRIMOFFSETP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16928 | #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16929 | #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16930 | |
| AnnaBridge | 172:65be27845400 | 16931 | /******************* Bit definition for OPAMP1_OTR register ******************/ |
| AnnaBridge | 172:65be27845400 | 16932 | #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16933 | #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16934 | #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16935 | #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16936 | #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16937 | #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16938 | |
| AnnaBridge | 172:65be27845400 | 16939 | /******************* Bit definition for OPAMP2_OTR register ******************/ |
| AnnaBridge | 172:65be27845400 | 16940 | #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16941 | #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16942 | #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16943 | #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16944 | #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16945 | #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16946 | |
| AnnaBridge | 172:65be27845400 | 16947 | /******************* Bit definition for OPAMP_LPOTR register ****************/ |
| AnnaBridge | 172:65be27845400 | 16948 | #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16949 | #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16950 | #define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16951 | #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16952 | #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16953 | #define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16954 | |
| AnnaBridge | 172:65be27845400 | 16955 | /******************* Bit definition for OPAMP1_LPOTR register ****************/ |
| AnnaBridge | 172:65be27845400 | 16956 | #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16957 | #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16958 | #define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16959 | #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16960 | #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16961 | #define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16962 | |
| AnnaBridge | 172:65be27845400 | 16963 | /******************* Bit definition for OPAMP2_LPOTR register ****************/ |
| AnnaBridge | 172:65be27845400 | 16964 | #define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16965 | #define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ |
| AnnaBridge | 172:65be27845400 | 16966 | #define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16967 | #define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 16968 | #define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ |
| AnnaBridge | 172:65be27845400 | 16969 | #define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ |
| AnnaBridge | 172:65be27845400 | 16970 | |
| AnnaBridge | 172:65be27845400 | 16971 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16972 | /* */ |
| AnnaBridge | 172:65be27845400 | 16973 | /* Touch Sensing Controller (TSC) */ |
| AnnaBridge | 172:65be27845400 | 16974 | /* */ |
| AnnaBridge | 172:65be27845400 | 16975 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 16976 | /******************* Bit definition for TSC_CR register *********************/ |
| AnnaBridge | 172:65be27845400 | 16977 | #define TSC_CR_TSCE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 16978 | #define TSC_CR_TSCE_Msk (0x1U << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 16979 | #define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!<Touch sensing controller enable */ |
| AnnaBridge | 172:65be27845400 | 16980 | #define TSC_CR_START_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 16981 | #define TSC_CR_START_Msk (0x1U << TSC_CR_START_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 16982 | #define TSC_CR_START TSC_CR_START_Msk /*!<Start acquisition */ |
| AnnaBridge | 172:65be27845400 | 16983 | #define TSC_CR_AM_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 16984 | #define TSC_CR_AM_Msk (0x1U << TSC_CR_AM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 16985 | #define TSC_CR_AM TSC_CR_AM_Msk /*!<Acquisition mode */ |
| AnnaBridge | 172:65be27845400 | 16986 | #define TSC_CR_SYNCPOL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 16987 | #define TSC_CR_SYNCPOL_Msk (0x1U << TSC_CR_SYNCPOL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 16988 | #define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk /*!<Synchronization pin polarity */ |
| AnnaBridge | 172:65be27845400 | 16989 | #define TSC_CR_IODEF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 16990 | #define TSC_CR_IODEF_Msk (0x1U << TSC_CR_IODEF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 16991 | #define TSC_CR_IODEF TSC_CR_IODEF_Msk /*!<IO default mode */ |
| AnnaBridge | 172:65be27845400 | 16992 | |
| AnnaBridge | 172:65be27845400 | 16993 | #define TSC_CR_MCV_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 16994 | #define TSC_CR_MCV_Msk (0x7U << TSC_CR_MCV_Pos) /*!< 0x000000E0 */ |
| AnnaBridge | 172:65be27845400 | 16995 | #define TSC_CR_MCV TSC_CR_MCV_Msk /*!<MCV[2:0] bits (Max Count Value) */ |
| AnnaBridge | 172:65be27845400 | 16996 | #define TSC_CR_MCV_0 (0x1U << TSC_CR_MCV_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 16997 | #define TSC_CR_MCV_1 (0x2U << TSC_CR_MCV_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 16998 | #define TSC_CR_MCV_2 (0x4U << TSC_CR_MCV_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 16999 | |
| AnnaBridge | 172:65be27845400 | 17000 | #define TSC_CR_PGPSC_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17001 | #define TSC_CR_PGPSC_Msk (0x7U << TSC_CR_PGPSC_Pos) /*!< 0x00007000 */ |
| AnnaBridge | 172:65be27845400 | 17002 | #define TSC_CR_PGPSC TSC_CR_PGPSC_Msk /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ |
| AnnaBridge | 172:65be27845400 | 17003 | #define TSC_CR_PGPSC_0 (0x1U << TSC_CR_PGPSC_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17004 | #define TSC_CR_PGPSC_1 (0x2U << TSC_CR_PGPSC_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17005 | #define TSC_CR_PGPSC_2 (0x4U << TSC_CR_PGPSC_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17006 | |
| AnnaBridge | 172:65be27845400 | 17007 | #define TSC_CR_SSPSC_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17008 | #define TSC_CR_SSPSC_Msk (0x1U << TSC_CR_SSPSC_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17009 | #define TSC_CR_SSPSC TSC_CR_SSPSC_Msk /*!<Spread Spectrum Prescaler */ |
| AnnaBridge | 172:65be27845400 | 17010 | #define TSC_CR_SSE_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17011 | #define TSC_CR_SSE_Msk (0x1U << TSC_CR_SSE_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17012 | #define TSC_CR_SSE TSC_CR_SSE_Msk /*!<Spread Spectrum Enable */ |
| AnnaBridge | 172:65be27845400 | 17013 | |
| AnnaBridge | 172:65be27845400 | 17014 | #define TSC_CR_SSD_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17015 | #define TSC_CR_SSD_Msk (0x7FU << TSC_CR_SSD_Pos) /*!< 0x00FE0000 */ |
| AnnaBridge | 172:65be27845400 | 17016 | #define TSC_CR_SSD TSC_CR_SSD_Msk /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ |
| AnnaBridge | 172:65be27845400 | 17017 | #define TSC_CR_SSD_0 (0x01U << TSC_CR_SSD_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17018 | #define TSC_CR_SSD_1 (0x02U << TSC_CR_SSD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17019 | #define TSC_CR_SSD_2 (0x04U << TSC_CR_SSD_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17020 | #define TSC_CR_SSD_3 (0x08U << TSC_CR_SSD_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17021 | #define TSC_CR_SSD_4 (0x10U << TSC_CR_SSD_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17022 | #define TSC_CR_SSD_5 (0x20U << TSC_CR_SSD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17023 | #define TSC_CR_SSD_6 (0x40U << TSC_CR_SSD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17024 | |
| AnnaBridge | 172:65be27845400 | 17025 | #define TSC_CR_CTPL_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17026 | #define TSC_CR_CTPL_Msk (0xFU << TSC_CR_CTPL_Pos) /*!< 0x0F000000 */ |
| AnnaBridge | 172:65be27845400 | 17027 | #define TSC_CR_CTPL TSC_CR_CTPL_Msk /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ |
| AnnaBridge | 172:65be27845400 | 17028 | #define TSC_CR_CTPL_0 (0x1U << TSC_CR_CTPL_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17029 | #define TSC_CR_CTPL_1 (0x2U << TSC_CR_CTPL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17030 | #define TSC_CR_CTPL_2 (0x4U << TSC_CR_CTPL_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17031 | #define TSC_CR_CTPL_3 (0x8U << TSC_CR_CTPL_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17032 | |
| AnnaBridge | 172:65be27845400 | 17033 | #define TSC_CR_CTPH_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17034 | #define TSC_CR_CTPH_Msk (0xFU << TSC_CR_CTPH_Pos) /*!< 0xF0000000 */ |
| AnnaBridge | 172:65be27845400 | 17035 | #define TSC_CR_CTPH TSC_CR_CTPH_Msk /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ |
| AnnaBridge | 172:65be27845400 | 17036 | #define TSC_CR_CTPH_0 (0x1U << TSC_CR_CTPH_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 17037 | #define TSC_CR_CTPH_1 (0x2U << TSC_CR_CTPH_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17038 | #define TSC_CR_CTPH_2 (0x4U << TSC_CR_CTPH_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17039 | #define TSC_CR_CTPH_3 (0x8U << TSC_CR_CTPH_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17040 | |
| AnnaBridge | 172:65be27845400 | 17041 | /******************* Bit definition for TSC_IER register ********************/ |
| AnnaBridge | 172:65be27845400 | 17042 | #define TSC_IER_EOAIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17043 | #define TSC_IER_EOAIE_Msk (0x1U << TSC_IER_EOAIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17044 | #define TSC_IER_EOAIE TSC_IER_EOAIE_Msk /*!<End of acquisition interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17045 | #define TSC_IER_MCEIE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17046 | #define TSC_IER_MCEIE_Msk (0x1U << TSC_IER_MCEIE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17047 | #define TSC_IER_MCEIE TSC_IER_MCEIE_Msk /*!<Max count error interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17048 | |
| AnnaBridge | 172:65be27845400 | 17049 | /******************* Bit definition for TSC_ICR register ********************/ |
| AnnaBridge | 172:65be27845400 | 17050 | #define TSC_ICR_EOAIC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17051 | #define TSC_ICR_EOAIC_Msk (0x1U << TSC_ICR_EOAIC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17052 | #define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk /*!<End of acquisition interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 17053 | #define TSC_ICR_MCEIC_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17054 | #define TSC_ICR_MCEIC_Msk (0x1U << TSC_ICR_MCEIC_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17055 | #define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk /*!<Max count error interrupt clear */ |
| AnnaBridge | 172:65be27845400 | 17056 | |
| AnnaBridge | 172:65be27845400 | 17057 | /******************* Bit definition for TSC_ISR register ********************/ |
| AnnaBridge | 172:65be27845400 | 17058 | #define TSC_ISR_EOAF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17059 | #define TSC_ISR_EOAF_Msk (0x1U << TSC_ISR_EOAF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17060 | #define TSC_ISR_EOAF TSC_ISR_EOAF_Msk /*!<End of acquisition flag */ |
| AnnaBridge | 172:65be27845400 | 17061 | #define TSC_ISR_MCEF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17062 | #define TSC_ISR_MCEF_Msk (0x1U << TSC_ISR_MCEF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17063 | #define TSC_ISR_MCEF TSC_ISR_MCEF_Msk /*!<Max count error flag */ |
| AnnaBridge | 172:65be27845400 | 17064 | |
| AnnaBridge | 172:65be27845400 | 17065 | /******************* Bit definition for TSC_IOHCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17066 | #define TSC_IOHCR_G1_IO1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17067 | #define TSC_IOHCR_G1_IO1_Msk (0x1U << TSC_IOHCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17068 | #define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17069 | #define TSC_IOHCR_G1_IO2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17070 | #define TSC_IOHCR_G1_IO2_Msk (0x1U << TSC_IOHCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17071 | #define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17072 | #define TSC_IOHCR_G1_IO3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17073 | #define TSC_IOHCR_G1_IO3_Msk (0x1U << TSC_IOHCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17074 | #define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17075 | #define TSC_IOHCR_G1_IO4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17076 | #define TSC_IOHCR_G1_IO4_Msk (0x1U << TSC_IOHCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17077 | #define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17078 | #define TSC_IOHCR_G2_IO1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17079 | #define TSC_IOHCR_G2_IO1_Msk (0x1U << TSC_IOHCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17080 | #define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17081 | #define TSC_IOHCR_G2_IO2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17082 | #define TSC_IOHCR_G2_IO2_Msk (0x1U << TSC_IOHCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17083 | #define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17084 | #define TSC_IOHCR_G2_IO3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17085 | #define TSC_IOHCR_G2_IO3_Msk (0x1U << TSC_IOHCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17086 | #define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17087 | #define TSC_IOHCR_G2_IO4_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17088 | #define TSC_IOHCR_G2_IO4_Msk (0x1U << TSC_IOHCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17089 | #define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17090 | #define TSC_IOHCR_G3_IO1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17091 | #define TSC_IOHCR_G3_IO1_Msk (0x1U << TSC_IOHCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17092 | #define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17093 | #define TSC_IOHCR_G3_IO2_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17094 | #define TSC_IOHCR_G3_IO2_Msk (0x1U << TSC_IOHCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17095 | #define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17096 | #define TSC_IOHCR_G3_IO3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17097 | #define TSC_IOHCR_G3_IO3_Msk (0x1U << TSC_IOHCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17098 | #define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17099 | #define TSC_IOHCR_G3_IO4_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17100 | #define TSC_IOHCR_G3_IO4_Msk (0x1U << TSC_IOHCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17101 | #define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17102 | #define TSC_IOHCR_G4_IO1_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17103 | #define TSC_IOHCR_G4_IO1_Msk (0x1U << TSC_IOHCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17104 | #define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17105 | #define TSC_IOHCR_G4_IO2_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17106 | #define TSC_IOHCR_G4_IO2_Msk (0x1U << TSC_IOHCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17107 | #define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17108 | #define TSC_IOHCR_G4_IO3_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17109 | #define TSC_IOHCR_G4_IO3_Msk (0x1U << TSC_IOHCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17110 | #define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17111 | #define TSC_IOHCR_G4_IO4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17112 | #define TSC_IOHCR_G4_IO4_Msk (0x1U << TSC_IOHCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17113 | #define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17114 | #define TSC_IOHCR_G5_IO1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17115 | #define TSC_IOHCR_G5_IO1_Msk (0x1U << TSC_IOHCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17116 | #define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17117 | #define TSC_IOHCR_G5_IO2_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17118 | #define TSC_IOHCR_G5_IO2_Msk (0x1U << TSC_IOHCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17119 | #define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17120 | #define TSC_IOHCR_G5_IO3_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17121 | #define TSC_IOHCR_G5_IO3_Msk (0x1U << TSC_IOHCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17122 | #define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17123 | #define TSC_IOHCR_G5_IO4_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17124 | #define TSC_IOHCR_G5_IO4_Msk (0x1U << TSC_IOHCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17125 | #define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17126 | #define TSC_IOHCR_G6_IO1_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17127 | #define TSC_IOHCR_G6_IO1_Msk (0x1U << TSC_IOHCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17128 | #define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17129 | #define TSC_IOHCR_G6_IO2_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17130 | #define TSC_IOHCR_G6_IO2_Msk (0x1U << TSC_IOHCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17131 | #define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17132 | #define TSC_IOHCR_G6_IO3_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17133 | #define TSC_IOHCR_G6_IO3_Msk (0x1U << TSC_IOHCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17134 | #define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17135 | #define TSC_IOHCR_G6_IO4_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17136 | #define TSC_IOHCR_G6_IO4_Msk (0x1U << TSC_IOHCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17137 | #define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17138 | #define TSC_IOHCR_G7_IO1_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17139 | #define TSC_IOHCR_G7_IO1_Msk (0x1U << TSC_IOHCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17140 | #define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17141 | #define TSC_IOHCR_G7_IO2_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 17142 | #define TSC_IOHCR_G7_IO2_Msk (0x1U << TSC_IOHCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17143 | #define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17144 | #define TSC_IOHCR_G7_IO3_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 17145 | #define TSC_IOHCR_G7_IO3_Msk (0x1U << TSC_IOHCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17146 | #define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17147 | #define TSC_IOHCR_G7_IO4_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 17148 | #define TSC_IOHCR_G7_IO4_Msk (0x1U << TSC_IOHCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17149 | #define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17150 | #define TSC_IOHCR_G8_IO1_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17151 | #define TSC_IOHCR_G8_IO1_Msk (0x1U << TSC_IOHCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 17152 | #define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17153 | #define TSC_IOHCR_G8_IO2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 17154 | #define TSC_IOHCR_G8_IO2_Msk (0x1U << TSC_IOHCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17155 | #define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17156 | #define TSC_IOHCR_G8_IO3_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 17157 | #define TSC_IOHCR_G8_IO3_Msk (0x1U << TSC_IOHCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17158 | #define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17159 | #define TSC_IOHCR_G8_IO4_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 17160 | #define TSC_IOHCR_G8_IO4_Msk (0x1U << TSC_IOHCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17161 | #define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ |
| AnnaBridge | 172:65be27845400 | 17162 | |
| AnnaBridge | 172:65be27845400 | 17163 | /******************* Bit definition for TSC_IOASCR register *****************/ |
| AnnaBridge | 172:65be27845400 | 17164 | #define TSC_IOASCR_G1_IO1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17165 | #define TSC_IOASCR_G1_IO1_Msk (0x1U << TSC_IOASCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17166 | #define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk /*!<GROUP1_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17167 | #define TSC_IOASCR_G1_IO2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17168 | #define TSC_IOASCR_G1_IO2_Msk (0x1U << TSC_IOASCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17169 | #define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk /*!<GROUP1_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17170 | #define TSC_IOASCR_G1_IO3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17171 | #define TSC_IOASCR_G1_IO3_Msk (0x1U << TSC_IOASCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17172 | #define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk /*!<GROUP1_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17173 | #define TSC_IOASCR_G1_IO4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17174 | #define TSC_IOASCR_G1_IO4_Msk (0x1U << TSC_IOASCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17175 | #define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk /*!<GROUP1_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17176 | #define TSC_IOASCR_G2_IO1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17177 | #define TSC_IOASCR_G2_IO1_Msk (0x1U << TSC_IOASCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17178 | #define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk /*!<GROUP2_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17179 | #define TSC_IOASCR_G2_IO2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17180 | #define TSC_IOASCR_G2_IO2_Msk (0x1U << TSC_IOASCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17181 | #define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk /*!<GROUP2_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17182 | #define TSC_IOASCR_G2_IO3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17183 | #define TSC_IOASCR_G2_IO3_Msk (0x1U << TSC_IOASCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17184 | #define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk /*!<GROUP2_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17185 | #define TSC_IOASCR_G2_IO4_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17186 | #define TSC_IOASCR_G2_IO4_Msk (0x1U << TSC_IOASCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17187 | #define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk /*!<GROUP2_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17188 | #define TSC_IOASCR_G3_IO1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17189 | #define TSC_IOASCR_G3_IO1_Msk (0x1U << TSC_IOASCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17190 | #define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk /*!<GROUP3_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17191 | #define TSC_IOASCR_G3_IO2_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17192 | #define TSC_IOASCR_G3_IO2_Msk (0x1U << TSC_IOASCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17193 | #define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk /*!<GROUP3_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17194 | #define TSC_IOASCR_G3_IO3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17195 | #define TSC_IOASCR_G3_IO3_Msk (0x1U << TSC_IOASCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17196 | #define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk /*!<GROUP3_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17197 | #define TSC_IOASCR_G3_IO4_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17198 | #define TSC_IOASCR_G3_IO4_Msk (0x1U << TSC_IOASCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17199 | #define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk /*!<GROUP3_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17200 | #define TSC_IOASCR_G4_IO1_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17201 | #define TSC_IOASCR_G4_IO1_Msk (0x1U << TSC_IOASCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17202 | #define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk /*!<GROUP4_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17203 | #define TSC_IOASCR_G4_IO2_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17204 | #define TSC_IOASCR_G4_IO2_Msk (0x1U << TSC_IOASCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17205 | #define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk /*!<GROUP4_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17206 | #define TSC_IOASCR_G4_IO3_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17207 | #define TSC_IOASCR_G4_IO3_Msk (0x1U << TSC_IOASCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17208 | #define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk /*!<GROUP4_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17209 | #define TSC_IOASCR_G4_IO4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17210 | #define TSC_IOASCR_G4_IO4_Msk (0x1U << TSC_IOASCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17211 | #define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk /*!<GROUP4_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17212 | #define TSC_IOASCR_G5_IO1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17213 | #define TSC_IOASCR_G5_IO1_Msk (0x1U << TSC_IOASCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17214 | #define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk /*!<GROUP5_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17215 | #define TSC_IOASCR_G5_IO2_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17216 | #define TSC_IOASCR_G5_IO2_Msk (0x1U << TSC_IOASCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17217 | #define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk /*!<GROUP5_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17218 | #define TSC_IOASCR_G5_IO3_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17219 | #define TSC_IOASCR_G5_IO3_Msk (0x1U << TSC_IOASCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17220 | #define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk /*!<GROUP5_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17221 | #define TSC_IOASCR_G5_IO4_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17222 | #define TSC_IOASCR_G5_IO4_Msk (0x1U << TSC_IOASCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17223 | #define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk /*!<GROUP5_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17224 | #define TSC_IOASCR_G6_IO1_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17225 | #define TSC_IOASCR_G6_IO1_Msk (0x1U << TSC_IOASCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17226 | #define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk /*!<GROUP6_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17227 | #define TSC_IOASCR_G6_IO2_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17228 | #define TSC_IOASCR_G6_IO2_Msk (0x1U << TSC_IOASCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17229 | #define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk /*!<GROUP6_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17230 | #define TSC_IOASCR_G6_IO3_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17231 | #define TSC_IOASCR_G6_IO3_Msk (0x1U << TSC_IOASCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17232 | #define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk /*!<GROUP6_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17233 | #define TSC_IOASCR_G6_IO4_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17234 | #define TSC_IOASCR_G6_IO4_Msk (0x1U << TSC_IOASCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17235 | #define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk /*!<GROUP6_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17236 | #define TSC_IOASCR_G7_IO1_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17237 | #define TSC_IOASCR_G7_IO1_Msk (0x1U << TSC_IOASCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17238 | #define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk /*!<GROUP7_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17239 | #define TSC_IOASCR_G7_IO2_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 17240 | #define TSC_IOASCR_G7_IO2_Msk (0x1U << TSC_IOASCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17241 | #define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk /*!<GROUP7_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17242 | #define TSC_IOASCR_G7_IO3_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 17243 | #define TSC_IOASCR_G7_IO3_Msk (0x1U << TSC_IOASCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17244 | #define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk /*!<GROUP7_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17245 | #define TSC_IOASCR_G7_IO4_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 17246 | #define TSC_IOASCR_G7_IO4_Msk (0x1U << TSC_IOASCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17247 | #define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk /*!<GROUP7_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17248 | #define TSC_IOASCR_G8_IO1_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17249 | #define TSC_IOASCR_G8_IO1_Msk (0x1U << TSC_IOASCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 17250 | #define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk /*!<GROUP8_IO1 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17251 | #define TSC_IOASCR_G8_IO2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 17252 | #define TSC_IOASCR_G8_IO2_Msk (0x1U << TSC_IOASCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17253 | #define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk /*!<GROUP8_IO2 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17254 | #define TSC_IOASCR_G8_IO3_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 17255 | #define TSC_IOASCR_G8_IO3_Msk (0x1U << TSC_IOASCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17256 | #define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk /*!<GROUP8_IO3 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17257 | #define TSC_IOASCR_G8_IO4_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 17258 | #define TSC_IOASCR_G8_IO4_Msk (0x1U << TSC_IOASCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17259 | #define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk /*!<GROUP8_IO4 analog switch enable */ |
| AnnaBridge | 172:65be27845400 | 17260 | |
| AnnaBridge | 172:65be27845400 | 17261 | /******************* Bit definition for TSC_IOSCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17262 | #define TSC_IOSCR_G1_IO1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17263 | #define TSC_IOSCR_G1_IO1_Msk (0x1U << TSC_IOSCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17264 | #define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk /*!<GROUP1_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17265 | #define TSC_IOSCR_G1_IO2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17266 | #define TSC_IOSCR_G1_IO2_Msk (0x1U << TSC_IOSCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17267 | #define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk /*!<GROUP1_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17268 | #define TSC_IOSCR_G1_IO3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17269 | #define TSC_IOSCR_G1_IO3_Msk (0x1U << TSC_IOSCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17270 | #define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk /*!<GROUP1_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17271 | #define TSC_IOSCR_G1_IO4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17272 | #define TSC_IOSCR_G1_IO4_Msk (0x1U << TSC_IOSCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17273 | #define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk /*!<GROUP1_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17274 | #define TSC_IOSCR_G2_IO1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17275 | #define TSC_IOSCR_G2_IO1_Msk (0x1U << TSC_IOSCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17276 | #define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk /*!<GROUP2_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17277 | #define TSC_IOSCR_G2_IO2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17278 | #define TSC_IOSCR_G2_IO2_Msk (0x1U << TSC_IOSCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17279 | #define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk /*!<GROUP2_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17280 | #define TSC_IOSCR_G2_IO3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17281 | #define TSC_IOSCR_G2_IO3_Msk (0x1U << TSC_IOSCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17282 | #define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk /*!<GROUP2_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17283 | #define TSC_IOSCR_G2_IO4_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17284 | #define TSC_IOSCR_G2_IO4_Msk (0x1U << TSC_IOSCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17285 | #define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk /*!<GROUP2_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17286 | #define TSC_IOSCR_G3_IO1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17287 | #define TSC_IOSCR_G3_IO1_Msk (0x1U << TSC_IOSCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17288 | #define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk /*!<GROUP3_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17289 | #define TSC_IOSCR_G3_IO2_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17290 | #define TSC_IOSCR_G3_IO2_Msk (0x1U << TSC_IOSCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17291 | #define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk /*!<GROUP3_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17292 | #define TSC_IOSCR_G3_IO3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17293 | #define TSC_IOSCR_G3_IO3_Msk (0x1U << TSC_IOSCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17294 | #define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk /*!<GROUP3_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17295 | #define TSC_IOSCR_G3_IO4_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17296 | #define TSC_IOSCR_G3_IO4_Msk (0x1U << TSC_IOSCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17297 | #define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk /*!<GROUP3_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17298 | #define TSC_IOSCR_G4_IO1_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17299 | #define TSC_IOSCR_G4_IO1_Msk (0x1U << TSC_IOSCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17300 | #define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk /*!<GROUP4_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17301 | #define TSC_IOSCR_G4_IO2_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17302 | #define TSC_IOSCR_G4_IO2_Msk (0x1U << TSC_IOSCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17303 | #define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk /*!<GROUP4_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17304 | #define TSC_IOSCR_G4_IO3_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17305 | #define TSC_IOSCR_G4_IO3_Msk (0x1U << TSC_IOSCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17306 | #define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk /*!<GROUP4_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17307 | #define TSC_IOSCR_G4_IO4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17308 | #define TSC_IOSCR_G4_IO4_Msk (0x1U << TSC_IOSCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17309 | #define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk /*!<GROUP4_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17310 | #define TSC_IOSCR_G5_IO1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17311 | #define TSC_IOSCR_G5_IO1_Msk (0x1U << TSC_IOSCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17312 | #define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk /*!<GROUP5_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17313 | #define TSC_IOSCR_G5_IO2_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17314 | #define TSC_IOSCR_G5_IO2_Msk (0x1U << TSC_IOSCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17315 | #define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk /*!<GROUP5_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17316 | #define TSC_IOSCR_G5_IO3_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17317 | #define TSC_IOSCR_G5_IO3_Msk (0x1U << TSC_IOSCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17318 | #define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk /*!<GROUP5_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17319 | #define TSC_IOSCR_G5_IO4_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17320 | #define TSC_IOSCR_G5_IO4_Msk (0x1U << TSC_IOSCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17321 | #define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk /*!<GROUP5_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17322 | #define TSC_IOSCR_G6_IO1_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17323 | #define TSC_IOSCR_G6_IO1_Msk (0x1U << TSC_IOSCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17324 | #define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk /*!<GROUP6_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17325 | #define TSC_IOSCR_G6_IO2_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17326 | #define TSC_IOSCR_G6_IO2_Msk (0x1U << TSC_IOSCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17327 | #define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk /*!<GROUP6_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17328 | #define TSC_IOSCR_G6_IO3_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17329 | #define TSC_IOSCR_G6_IO3_Msk (0x1U << TSC_IOSCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17330 | #define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk /*!<GROUP6_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17331 | #define TSC_IOSCR_G6_IO4_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17332 | #define TSC_IOSCR_G6_IO4_Msk (0x1U << TSC_IOSCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17333 | #define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk /*!<GROUP6_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17334 | #define TSC_IOSCR_G7_IO1_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17335 | #define TSC_IOSCR_G7_IO1_Msk (0x1U << TSC_IOSCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17336 | #define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk /*!<GROUP7_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17337 | #define TSC_IOSCR_G7_IO2_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 17338 | #define TSC_IOSCR_G7_IO2_Msk (0x1U << TSC_IOSCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17339 | #define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk /*!<GROUP7_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17340 | #define TSC_IOSCR_G7_IO3_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 17341 | #define TSC_IOSCR_G7_IO3_Msk (0x1U << TSC_IOSCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17342 | #define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk /*!<GROUP7_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17343 | #define TSC_IOSCR_G7_IO4_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 17344 | #define TSC_IOSCR_G7_IO4_Msk (0x1U << TSC_IOSCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17345 | #define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk /*!<GROUP7_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17346 | #define TSC_IOSCR_G8_IO1_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17347 | #define TSC_IOSCR_G8_IO1_Msk (0x1U << TSC_IOSCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 17348 | #define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk /*!<GROUP8_IO1 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17349 | #define TSC_IOSCR_G8_IO2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 17350 | #define TSC_IOSCR_G8_IO2_Msk (0x1U << TSC_IOSCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17351 | #define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk /*!<GROUP8_IO2 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17352 | #define TSC_IOSCR_G8_IO3_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 17353 | #define TSC_IOSCR_G8_IO3_Msk (0x1U << TSC_IOSCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17354 | #define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk /*!<GROUP8_IO3 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17355 | #define TSC_IOSCR_G8_IO4_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 17356 | #define TSC_IOSCR_G8_IO4_Msk (0x1U << TSC_IOSCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17357 | #define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk /*!<GROUP8_IO4 sampling mode */ |
| AnnaBridge | 172:65be27845400 | 17358 | |
| AnnaBridge | 172:65be27845400 | 17359 | /******************* Bit definition for TSC_IOCCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17360 | #define TSC_IOCCR_G1_IO1_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17361 | #define TSC_IOCCR_G1_IO1_Msk (0x1U << TSC_IOCCR_G1_IO1_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17362 | #define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk /*!<GROUP1_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17363 | #define TSC_IOCCR_G1_IO2_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17364 | #define TSC_IOCCR_G1_IO2_Msk (0x1U << TSC_IOCCR_G1_IO2_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17365 | #define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk /*!<GROUP1_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17366 | #define TSC_IOCCR_G1_IO3_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17367 | #define TSC_IOCCR_G1_IO3_Msk (0x1U << TSC_IOCCR_G1_IO3_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17368 | #define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk /*!<GROUP1_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17369 | #define TSC_IOCCR_G1_IO4_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17370 | #define TSC_IOCCR_G1_IO4_Msk (0x1U << TSC_IOCCR_G1_IO4_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17371 | #define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk /*!<GROUP1_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17372 | #define TSC_IOCCR_G2_IO1_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17373 | #define TSC_IOCCR_G2_IO1_Msk (0x1U << TSC_IOCCR_G2_IO1_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17374 | #define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk /*!<GROUP2_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17375 | #define TSC_IOCCR_G2_IO2_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17376 | #define TSC_IOCCR_G2_IO2_Msk (0x1U << TSC_IOCCR_G2_IO2_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17377 | #define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk /*!<GROUP2_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17378 | #define TSC_IOCCR_G2_IO3_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17379 | #define TSC_IOCCR_G2_IO3_Msk (0x1U << TSC_IOCCR_G2_IO3_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17380 | #define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk /*!<GROUP2_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17381 | #define TSC_IOCCR_G2_IO4_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17382 | #define TSC_IOCCR_G2_IO4_Msk (0x1U << TSC_IOCCR_G2_IO4_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17383 | #define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk /*!<GROUP2_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17384 | #define TSC_IOCCR_G3_IO1_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17385 | #define TSC_IOCCR_G3_IO1_Msk (0x1U << TSC_IOCCR_G3_IO1_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17386 | #define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk /*!<GROUP3_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17387 | #define TSC_IOCCR_G3_IO2_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17388 | #define TSC_IOCCR_G3_IO2_Msk (0x1U << TSC_IOCCR_G3_IO2_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17389 | #define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk /*!<GROUP3_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17390 | #define TSC_IOCCR_G3_IO3_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17391 | #define TSC_IOCCR_G3_IO3_Msk (0x1U << TSC_IOCCR_G3_IO3_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17392 | #define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk /*!<GROUP3_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17393 | #define TSC_IOCCR_G3_IO4_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17394 | #define TSC_IOCCR_G3_IO4_Msk (0x1U << TSC_IOCCR_G3_IO4_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17395 | #define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk /*!<GROUP3_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17396 | #define TSC_IOCCR_G4_IO1_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17397 | #define TSC_IOCCR_G4_IO1_Msk (0x1U << TSC_IOCCR_G4_IO1_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17398 | #define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk /*!<GROUP4_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17399 | #define TSC_IOCCR_G4_IO2_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17400 | #define TSC_IOCCR_G4_IO2_Msk (0x1U << TSC_IOCCR_G4_IO2_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17401 | #define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk /*!<GROUP4_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17402 | #define TSC_IOCCR_G4_IO3_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17403 | #define TSC_IOCCR_G4_IO3_Msk (0x1U << TSC_IOCCR_G4_IO3_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17404 | #define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk /*!<GROUP4_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17405 | #define TSC_IOCCR_G4_IO4_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17406 | #define TSC_IOCCR_G4_IO4_Msk (0x1U << TSC_IOCCR_G4_IO4_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17407 | #define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk /*!<GROUP4_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17408 | #define TSC_IOCCR_G5_IO1_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17409 | #define TSC_IOCCR_G5_IO1_Msk (0x1U << TSC_IOCCR_G5_IO1_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17410 | #define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk /*!<GROUP5_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17411 | #define TSC_IOCCR_G5_IO2_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17412 | #define TSC_IOCCR_G5_IO2_Msk (0x1U << TSC_IOCCR_G5_IO2_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17413 | #define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk /*!<GROUP5_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17414 | #define TSC_IOCCR_G5_IO3_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17415 | #define TSC_IOCCR_G5_IO3_Msk (0x1U << TSC_IOCCR_G5_IO3_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17416 | #define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk /*!<GROUP5_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17417 | #define TSC_IOCCR_G5_IO4_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17418 | #define TSC_IOCCR_G5_IO4_Msk (0x1U << TSC_IOCCR_G5_IO4_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17419 | #define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk /*!<GROUP5_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17420 | #define TSC_IOCCR_G6_IO1_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17421 | #define TSC_IOCCR_G6_IO1_Msk (0x1U << TSC_IOCCR_G6_IO1_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17422 | #define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk /*!<GROUP6_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17423 | #define TSC_IOCCR_G6_IO2_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17424 | #define TSC_IOCCR_G6_IO2_Msk (0x1U << TSC_IOCCR_G6_IO2_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17425 | #define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk /*!<GROUP6_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17426 | #define TSC_IOCCR_G6_IO3_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17427 | #define TSC_IOCCR_G6_IO3_Msk (0x1U << TSC_IOCCR_G6_IO3_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17428 | #define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk /*!<GROUP6_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17429 | #define TSC_IOCCR_G6_IO4_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17430 | #define TSC_IOCCR_G6_IO4_Msk (0x1U << TSC_IOCCR_G6_IO4_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17431 | #define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk /*!<GROUP6_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17432 | #define TSC_IOCCR_G7_IO1_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17433 | #define TSC_IOCCR_G7_IO1_Msk (0x1U << TSC_IOCCR_G7_IO1_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17434 | #define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk /*!<GROUP7_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17435 | #define TSC_IOCCR_G7_IO2_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 17436 | #define TSC_IOCCR_G7_IO2_Msk (0x1U << TSC_IOCCR_G7_IO2_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17437 | #define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk /*!<GROUP7_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17438 | #define TSC_IOCCR_G7_IO3_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 17439 | #define TSC_IOCCR_G7_IO3_Msk (0x1U << TSC_IOCCR_G7_IO3_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17440 | #define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk /*!<GROUP7_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17441 | #define TSC_IOCCR_G7_IO4_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 17442 | #define TSC_IOCCR_G7_IO4_Msk (0x1U << TSC_IOCCR_G7_IO4_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17443 | #define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk /*!<GROUP7_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17444 | #define TSC_IOCCR_G8_IO1_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17445 | #define TSC_IOCCR_G8_IO1_Msk (0x1U << TSC_IOCCR_G8_IO1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 17446 | #define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk /*!<GROUP8_IO1 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17447 | #define TSC_IOCCR_G8_IO2_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 17448 | #define TSC_IOCCR_G8_IO2_Msk (0x1U << TSC_IOCCR_G8_IO2_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17449 | #define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk /*!<GROUP8_IO2 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17450 | #define TSC_IOCCR_G8_IO3_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 17451 | #define TSC_IOCCR_G8_IO3_Msk (0x1U << TSC_IOCCR_G8_IO3_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17452 | #define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk /*!<GROUP8_IO3 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17453 | #define TSC_IOCCR_G8_IO4_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 17454 | #define TSC_IOCCR_G8_IO4_Msk (0x1U << TSC_IOCCR_G8_IO4_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17455 | #define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk /*!<GROUP8_IO4 channel mode */ |
| AnnaBridge | 172:65be27845400 | 17456 | |
| AnnaBridge | 172:65be27845400 | 17457 | /******************* Bit definition for TSC_IOGCSR register *****************/ |
| AnnaBridge | 172:65be27845400 | 17458 | #define TSC_IOGCSR_G1E_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17459 | #define TSC_IOGCSR_G1E_Msk (0x1U << TSC_IOGCSR_G1E_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17460 | #define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk /*!<Analog IO GROUP1 enable */ |
| AnnaBridge | 172:65be27845400 | 17461 | #define TSC_IOGCSR_G2E_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17462 | #define TSC_IOGCSR_G2E_Msk (0x1U << TSC_IOGCSR_G2E_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17463 | #define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk /*!<Analog IO GROUP2 enable */ |
| AnnaBridge | 172:65be27845400 | 17464 | #define TSC_IOGCSR_G3E_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17465 | #define TSC_IOGCSR_G3E_Msk (0x1U << TSC_IOGCSR_G3E_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17466 | #define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk /*!<Analog IO GROUP3 enable */ |
| AnnaBridge | 172:65be27845400 | 17467 | #define TSC_IOGCSR_G4E_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17468 | #define TSC_IOGCSR_G4E_Msk (0x1U << TSC_IOGCSR_G4E_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17469 | #define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk /*!<Analog IO GROUP4 enable */ |
| AnnaBridge | 172:65be27845400 | 17470 | #define TSC_IOGCSR_G5E_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17471 | #define TSC_IOGCSR_G5E_Msk (0x1U << TSC_IOGCSR_G5E_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17472 | #define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk /*!<Analog IO GROUP5 enable */ |
| AnnaBridge | 172:65be27845400 | 17473 | #define TSC_IOGCSR_G6E_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17474 | #define TSC_IOGCSR_G6E_Msk (0x1U << TSC_IOGCSR_G6E_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17475 | #define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk /*!<Analog IO GROUP6 enable */ |
| AnnaBridge | 172:65be27845400 | 17476 | #define TSC_IOGCSR_G7E_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17477 | #define TSC_IOGCSR_G7E_Msk (0x1U << TSC_IOGCSR_G7E_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17478 | #define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk /*!<Analog IO GROUP7 enable */ |
| AnnaBridge | 172:65be27845400 | 17479 | #define TSC_IOGCSR_G8E_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17480 | #define TSC_IOGCSR_G8E_Msk (0x1U << TSC_IOGCSR_G8E_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17481 | #define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk /*!<Analog IO GROUP8 enable */ |
| AnnaBridge | 172:65be27845400 | 17482 | #define TSC_IOGCSR_G1S_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17483 | #define TSC_IOGCSR_G1S_Msk (0x1U << TSC_IOGCSR_G1S_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17484 | #define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk /*!<Analog IO GROUP1 status */ |
| AnnaBridge | 172:65be27845400 | 17485 | #define TSC_IOGCSR_G2S_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17486 | #define TSC_IOGCSR_G2S_Msk (0x1U << TSC_IOGCSR_G2S_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17487 | #define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk /*!<Analog IO GROUP2 status */ |
| AnnaBridge | 172:65be27845400 | 17488 | #define TSC_IOGCSR_G3S_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17489 | #define TSC_IOGCSR_G3S_Msk (0x1U << TSC_IOGCSR_G3S_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17490 | #define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk /*!<Analog IO GROUP3 status */ |
| AnnaBridge | 172:65be27845400 | 17491 | #define TSC_IOGCSR_G4S_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17492 | #define TSC_IOGCSR_G4S_Msk (0x1U << TSC_IOGCSR_G4S_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17493 | #define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk /*!<Analog IO GROUP4 status */ |
| AnnaBridge | 172:65be27845400 | 17494 | #define TSC_IOGCSR_G5S_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17495 | #define TSC_IOGCSR_G5S_Msk (0x1U << TSC_IOGCSR_G5S_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17496 | #define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk /*!<Analog IO GROUP5 status */ |
| AnnaBridge | 172:65be27845400 | 17497 | #define TSC_IOGCSR_G6S_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17498 | #define TSC_IOGCSR_G6S_Msk (0x1U << TSC_IOGCSR_G6S_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17499 | #define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk /*!<Analog IO GROUP6 status */ |
| AnnaBridge | 172:65be27845400 | 17500 | #define TSC_IOGCSR_G7S_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17501 | #define TSC_IOGCSR_G7S_Msk (0x1U << TSC_IOGCSR_G7S_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17502 | #define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk /*!<Analog IO GROUP7 status */ |
| AnnaBridge | 172:65be27845400 | 17503 | #define TSC_IOGCSR_G8S_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17504 | #define TSC_IOGCSR_G8S_Msk (0x1U << TSC_IOGCSR_G8S_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17505 | #define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk /*!<Analog IO GROUP8 status */ |
| AnnaBridge | 172:65be27845400 | 17506 | |
| AnnaBridge | 172:65be27845400 | 17507 | /******************* Bit definition for TSC_IOGXCR register *****************/ |
| AnnaBridge | 172:65be27845400 | 17508 | #define TSC_IOGXCR_CNT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17509 | #define TSC_IOGXCR_CNT_Msk (0x3FFFU << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ |
| AnnaBridge | 172:65be27845400 | 17510 | #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!<CNT[13:0] bits (Counter value) */ |
| AnnaBridge | 172:65be27845400 | 17511 | |
| AnnaBridge | 172:65be27845400 | 17512 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 17513 | /* */ |
| AnnaBridge | 172:65be27845400 | 17514 | /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ |
| AnnaBridge | 172:65be27845400 | 17515 | /* */ |
| AnnaBridge | 172:65be27845400 | 17516 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 17517 | |
| AnnaBridge | 172:65be27845400 | 17518 | /* |
| AnnaBridge | 172:65be27845400 | 17519 | * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) |
| AnnaBridge | 172:65be27845400 | 17520 | */ |
| AnnaBridge | 172:65be27845400 | 17521 | #define USART_TCBGT_SUPPORT |
| AnnaBridge | 172:65be27845400 | 17522 | |
| AnnaBridge | 172:65be27845400 | 17523 | /****************** Bit definition for USART_CR1 register *******************/ |
| AnnaBridge | 172:65be27845400 | 17524 | #define USART_CR1_UE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17525 | #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17526 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
| AnnaBridge | 172:65be27845400 | 17527 | #define USART_CR1_UESM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17528 | #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17529 | #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ |
| AnnaBridge | 172:65be27845400 | 17530 | #define USART_CR1_RE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17531 | #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17532 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
| AnnaBridge | 172:65be27845400 | 17533 | #define USART_CR1_TE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17534 | #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17535 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
| AnnaBridge | 172:65be27845400 | 17536 | #define USART_CR1_IDLEIE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17537 | #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17538 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17539 | #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17540 | #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1U << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17541 | #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17542 | // MBED |
| AnnaBridge | 172:65be27845400 | 17543 | #define USART_CR1_RXNEIE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17544 | #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17545 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17546 | #define USART_CR1_TCIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17547 | #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17548 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17549 | #define USART_CR1_TXEIE_TXFNFIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17550 | #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1U << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17551 | #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17552 | // MBED |
| AnnaBridge | 172:65be27845400 | 17553 | #define USART_CR1_TXEIE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17554 | #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17555 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17556 | #define USART_CR1_PEIE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17557 | #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17558 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17559 | #define USART_CR1_PS_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17560 | #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17561 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
| AnnaBridge | 172:65be27845400 | 17562 | #define USART_CR1_PCE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17563 | #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17564 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
| AnnaBridge | 172:65be27845400 | 17565 | #define USART_CR1_WAKE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17566 | #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17567 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ |
| AnnaBridge | 172:65be27845400 | 17568 | #define USART_CR1_M_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17569 | #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */ |
| AnnaBridge | 172:65be27845400 | 17570 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
| AnnaBridge | 172:65be27845400 | 17571 | #define USART_CR1_M0_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17572 | #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17573 | #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ |
| AnnaBridge | 172:65be27845400 | 17574 | #define USART_CR1_MME_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17575 | #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17576 | #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ |
| AnnaBridge | 172:65be27845400 | 17577 | #define USART_CR1_CMIE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17578 | #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17579 | #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17580 | #define USART_CR1_OVER8_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17581 | #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17582 | #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ |
| AnnaBridge | 172:65be27845400 | 17583 | #define USART_CR1_DEDT_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17584 | #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ |
| AnnaBridge | 172:65be27845400 | 17585 | #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ |
| AnnaBridge | 172:65be27845400 | 17586 | #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17587 | #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17588 | #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17589 | #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17590 | #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17591 | #define USART_CR1_DEAT_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17592 | #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ |
| AnnaBridge | 172:65be27845400 | 17593 | #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ |
| AnnaBridge | 172:65be27845400 | 17594 | #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17595 | #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17596 | #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17597 | #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17598 | #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17599 | #define USART_CR1_RTOIE_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 17600 | #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17601 | #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17602 | #define USART_CR1_EOBIE_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 17603 | #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17604 | #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17605 | #define USART_CR1_M1_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17606 | #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 17607 | #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ |
| AnnaBridge | 172:65be27845400 | 17608 | #define USART_CR1_FIFOEN_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 17609 | #define USART_CR1_FIFOEN_Msk (0x1U << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17610 | #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ |
| AnnaBridge | 172:65be27845400 | 17611 | #define USART_CR1_TXFEIE_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 17612 | #define USART_CR1_TXFEIE_Msk (0x1U << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17613 | #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17614 | #define USART_CR1_RXFFIE_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 17615 | #define USART_CR1_RXFFIE_Msk (0x1U << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17616 | #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17617 | |
| AnnaBridge | 172:65be27845400 | 17618 | /****************** Bit definition for USART_CR2 register *******************/ |
| AnnaBridge | 172:65be27845400 | 17619 | #define USART_CR2_SLVEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17620 | #define USART_CR2_SLVEN_Msk (0x1U << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17621 | #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ |
| AnnaBridge | 172:65be27845400 | 17622 | #define USART_CR2_DIS_NSS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17623 | #define USART_CR2_DIS_NSS_Msk (0x1U << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17624 | #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */ |
| AnnaBridge | 172:65be27845400 | 17625 | #define USART_CR2_ADDM7_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17626 | #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17627 | #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ |
| AnnaBridge | 172:65be27845400 | 17628 | #define USART_CR2_LBDL_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17629 | #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17630 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
| AnnaBridge | 172:65be27845400 | 17631 | #define USART_CR2_LBDIE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17632 | #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17633 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17634 | #define USART_CR2_LBCL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17635 | #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17636 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
| AnnaBridge | 172:65be27845400 | 17637 | #define USART_CR2_CPHA_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17638 | #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17639 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
| AnnaBridge | 172:65be27845400 | 17640 | #define USART_CR2_CPOL_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17641 | #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17642 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
| AnnaBridge | 172:65be27845400 | 17643 | #define USART_CR2_CLKEN_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17644 | #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17645 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
| AnnaBridge | 172:65be27845400 | 17646 | #define USART_CR2_STOP_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17647 | #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
| AnnaBridge | 172:65be27845400 | 17648 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
| AnnaBridge | 172:65be27845400 | 17649 | #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17650 | #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17651 | #define USART_CR2_LINEN_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17652 | #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17653 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
| AnnaBridge | 172:65be27845400 | 17654 | #define USART_CR2_SWAP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17655 | #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17656 | #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ |
| AnnaBridge | 172:65be27845400 | 17657 | #define USART_CR2_RXINV_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17658 | #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17659 | #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ |
| AnnaBridge | 172:65be27845400 | 17660 | #define USART_CR2_TXINV_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17661 | #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17662 | #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ |
| AnnaBridge | 172:65be27845400 | 17663 | #define USART_CR2_DATAINV_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17664 | #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17665 | #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ |
| AnnaBridge | 172:65be27845400 | 17666 | #define USART_CR2_MSBFIRST_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17667 | #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17668 | #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ |
| AnnaBridge | 172:65be27845400 | 17669 | #define USART_CR2_ABREN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17670 | #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17671 | #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ |
| AnnaBridge | 172:65be27845400 | 17672 | #define USART_CR2_ABRMODE_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17673 | #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ |
| AnnaBridge | 172:65be27845400 | 17674 | #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ |
| AnnaBridge | 172:65be27845400 | 17675 | #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17676 | #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17677 | #define USART_CR2_RTOEN_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17678 | #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17679 | #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ |
| AnnaBridge | 172:65be27845400 | 17680 | #define USART_CR2_ADD_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17681 | #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 17682 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
| AnnaBridge | 172:65be27845400 | 17683 | |
| AnnaBridge | 172:65be27845400 | 17684 | /****************** Bit definition for USART_CR3 register *******************/ |
| AnnaBridge | 172:65be27845400 | 17685 | #define USART_CR3_EIE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17686 | #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17687 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17688 | #define USART_CR3_IREN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17689 | #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17690 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
| AnnaBridge | 172:65be27845400 | 17691 | #define USART_CR3_IRLP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17692 | #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17693 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
| AnnaBridge | 172:65be27845400 | 17694 | #define USART_CR3_HDSEL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17695 | #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17696 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
| AnnaBridge | 172:65be27845400 | 17697 | #define USART_CR3_NACK_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17698 | #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17699 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ |
| AnnaBridge | 172:65be27845400 | 17700 | #define USART_CR3_SCEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17701 | #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17702 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ |
| AnnaBridge | 172:65be27845400 | 17703 | #define USART_CR3_DMAR_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17704 | #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17705 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
| AnnaBridge | 172:65be27845400 | 17706 | #define USART_CR3_DMAT_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17707 | #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17708 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
| AnnaBridge | 172:65be27845400 | 17709 | #define USART_CR3_RTSE_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17710 | #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17711 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
| AnnaBridge | 172:65be27845400 | 17712 | #define USART_CR3_CTSE_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17713 | #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17714 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
| AnnaBridge | 172:65be27845400 | 17715 | #define USART_CR3_CTSIE_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17716 | #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17717 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17718 | #define USART_CR3_ONEBIT_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17719 | #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17720 | #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ |
| AnnaBridge | 172:65be27845400 | 17721 | #define USART_CR3_OVRDIS_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17722 | #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17723 | #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ |
| AnnaBridge | 172:65be27845400 | 17724 | #define USART_CR3_DDRE_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17725 | #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17726 | #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ |
| AnnaBridge | 172:65be27845400 | 17727 | #define USART_CR3_DEM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17728 | #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17729 | #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ |
| AnnaBridge | 172:65be27845400 | 17730 | #define USART_CR3_DEP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17731 | #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17732 | #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ |
| AnnaBridge | 172:65be27845400 | 17733 | #define USART_CR3_SCARCNT_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17734 | #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ |
| AnnaBridge | 172:65be27845400 | 17735 | #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ |
| AnnaBridge | 172:65be27845400 | 17736 | #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17737 | #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17738 | #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17739 | #define USART_CR3_WUS_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17740 | #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 17741 | #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ |
| AnnaBridge | 172:65be27845400 | 17742 | #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17743 | #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17744 | #define USART_CR3_WUFIE_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17745 | #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17746 | #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17747 | /* MBED */ |
| AnnaBridge | 172:65be27845400 | 17748 | #define USART_CR3_UCESM_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17749 | #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17750 | #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */ |
| AnnaBridge | 172:65be27845400 | 17751 | /* MBED */ |
| AnnaBridge | 172:65be27845400 | 17752 | #define USART_CR3_TXFTIE_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17753 | #define USART_CR3_TXFTIE_Msk (0x1U << USART_CR3_TXFTIE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17754 | #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17755 | #define USART_CR3_TCBGTIE_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17756 | #define USART_CR3_TCBGTIE_Msk (0x1U << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 17757 | #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ |
| AnnaBridge | 172:65be27845400 | 17758 | #define USART_CR3_RXFTCFG_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 17759 | #define USART_CR3_RXFTCFG_Msk (0x7U << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ |
| AnnaBridge | 172:65be27845400 | 17760 | #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG[2:0] bits (RXFIFO threshold configuration) */ |
| AnnaBridge | 172:65be27845400 | 17761 | #define USART_CR3_RXFTCFG_0 (0x1U << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17762 | #define USART_CR3_RXFTCFG_1 (0x2U << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17763 | #define USART_CR3_RXFTCFG_2 (0x4U << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17764 | #define USART_CR3_RXFTIE_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 17765 | #define USART_CR3_RXFTIE_Msk (0x1U << USART_CR3_RXFTIE_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17766 | #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ |
| AnnaBridge | 172:65be27845400 | 17767 | #define USART_CR3_TXFTCFG_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 17768 | #define USART_CR3_TXFTCFG_Msk (0x7U << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ |
| AnnaBridge | 172:65be27845400 | 17769 | #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFTCFG[2:0] bits (TXFIFO threshold configuration) */ |
| AnnaBridge | 172:65be27845400 | 17770 | #define USART_CR3_TXFTCFG_0 (0x1U << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 17771 | #define USART_CR3_TXFTCFG_1 (0x2U << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 17772 | #define USART_CR3_TXFTCFG_2 (0x4U << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 17773 | |
| AnnaBridge | 172:65be27845400 | 17774 | /****************** Bit definition for USART_BRR register *******************/ |
| AnnaBridge | 172:65be27845400 | 17775 | #define USART_BRR_DIV_FRACTION_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17776 | #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 17777 | #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ |
| AnnaBridge | 172:65be27845400 | 17778 | #define USART_BRR_DIV_MANTISSA_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17779 | #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ |
| AnnaBridge | 172:65be27845400 | 17780 | #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ |
| AnnaBridge | 172:65be27845400 | 17781 | |
| AnnaBridge | 172:65be27845400 | 17782 | /****************** Bit definition for USART_GTPR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17783 | #define USART_GTPR_PSC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17784 | #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
| AnnaBridge | 172:65be27845400 | 17785 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
| AnnaBridge | 172:65be27845400 | 17786 | #define USART_GTPR_GT_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17787 | #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
| AnnaBridge | 172:65be27845400 | 17788 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ |
| AnnaBridge | 172:65be27845400 | 17789 | |
| AnnaBridge | 172:65be27845400 | 17790 | /******************* Bit definition for USART_RTOR register *****************/ |
| AnnaBridge | 172:65be27845400 | 17791 | #define USART_RTOR_RTO_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17792 | #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ |
| AnnaBridge | 172:65be27845400 | 17793 | #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ |
| AnnaBridge | 172:65be27845400 | 17794 | #define USART_RTOR_BLEN_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17795 | #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 17796 | #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ |
| AnnaBridge | 172:65be27845400 | 17797 | |
| AnnaBridge | 172:65be27845400 | 17798 | /******************* Bit definition for USART_RQR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17799 | #define USART_RQR_ABRRQ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17800 | #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17801 | #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ |
| AnnaBridge | 172:65be27845400 | 17802 | #define USART_RQR_SBKRQ_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17803 | #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17804 | #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ |
| AnnaBridge | 172:65be27845400 | 17805 | #define USART_RQR_MMRQ_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17806 | #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17807 | #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ |
| AnnaBridge | 172:65be27845400 | 17808 | #define USART_RQR_RXFRQ_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17809 | #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17810 | #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ |
| AnnaBridge | 172:65be27845400 | 17811 | #define USART_RQR_TXFRQ_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17812 | #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17813 | #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ |
| AnnaBridge | 172:65be27845400 | 17814 | |
| AnnaBridge | 172:65be27845400 | 17815 | /******************* Bit definition for USART_ISR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17816 | #define USART_ISR_PE_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17817 | #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17818 | #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ |
| AnnaBridge | 172:65be27845400 | 17819 | #define USART_ISR_FE_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17820 | #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17821 | #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ |
| AnnaBridge | 172:65be27845400 | 17822 | #define USART_ISR_NE_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17823 | #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17824 | #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detected Flag */ |
| AnnaBridge | 172:65be27845400 | 17825 | #define USART_ISR_ORE_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17826 | #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17827 | #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ |
| AnnaBridge | 172:65be27845400 | 17828 | #define USART_ISR_IDLE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17829 | #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17830 | #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ |
| AnnaBridge | 172:65be27845400 | 17831 | #define USART_ISR_RXNE_RXFNE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17832 | #define USART_ISR_RXNE_RXFNE_Msk (0x1U << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17833 | #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */ |
| AnnaBridge | 172:65be27845400 | 17834 | #define USART_ISR_TC_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17835 | #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17836 | #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ |
| AnnaBridge | 172:65be27845400 | 17837 | #define USART_ISR_TXE_TXFNF_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17838 | #define USART_ISR_TXE_TXFNF_Msk (0x1U << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17839 | #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */ |
| AnnaBridge | 172:65be27845400 | 17840 | #define USART_ISR_LBDF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17841 | #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17842 | #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ |
| AnnaBridge | 172:65be27845400 | 17843 | #define USART_ISR_CTSIF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17844 | #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17845 | #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ |
| AnnaBridge | 172:65be27845400 | 17846 | #define USART_ISR_CTS_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 17847 | #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 17848 | #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ |
| AnnaBridge | 172:65be27845400 | 17849 | #define USART_ISR_RTOF_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17850 | #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17851 | #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ |
| AnnaBridge | 172:65be27845400 | 17852 | #define USART_ISR_EOBF_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17853 | #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17854 | #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ |
| AnnaBridge | 172:65be27845400 | 17855 | #define USART_ISR_UDR_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17856 | #define USART_ISR_UDR_Msk (0x1U << USART_ISR_UDR_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17857 | #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */ |
| AnnaBridge | 172:65be27845400 | 17858 | #define USART_ISR_ABRE_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 17859 | #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 17860 | #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ |
| AnnaBridge | 172:65be27845400 | 17861 | #define USART_ISR_ABRF_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 17862 | #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 17863 | #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ |
| AnnaBridge | 172:65be27845400 | 17864 | #define USART_ISR_BUSY_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 17865 | #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 17866 | #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ |
| AnnaBridge | 172:65be27845400 | 17867 | #define USART_ISR_CMF_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17868 | #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17869 | #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ |
| AnnaBridge | 172:65be27845400 | 17870 | #define USART_ISR_SBKF_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 17871 | #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 17872 | #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ |
| AnnaBridge | 172:65be27845400 | 17873 | #define USART_ISR_RWU_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 17874 | #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 17875 | #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ |
| AnnaBridge | 172:65be27845400 | 17876 | #define USART_ISR_WUF_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17877 | #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17878 | #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ |
| AnnaBridge | 172:65be27845400 | 17879 | #define USART_ISR_TEACK_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 17880 | #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 17881 | #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ |
| AnnaBridge | 172:65be27845400 | 17882 | #define USART_ISR_REACK_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 17883 | #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 17884 | #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ |
| AnnaBridge | 172:65be27845400 | 17885 | #define USART_ISR_TXFE_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 17886 | #define USART_ISR_TXFE_Msk (0x1U << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17887 | #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */ |
| AnnaBridge | 172:65be27845400 | 17888 | #define USART_ISR_RXFF_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 17889 | #define USART_ISR_RXFF_Msk (0x1U << USART_ISR_RXFF_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 17890 | #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */ |
| AnnaBridge | 172:65be27845400 | 17891 | #define USART_ISR_TCBGT_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 17892 | #define USART_ISR_TCBGT_Msk (0x1U << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 17893 | #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */ |
| AnnaBridge | 172:65be27845400 | 17894 | #define USART_ISR_RXFT_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 17895 | #define USART_ISR_RXFT_Msk (0x1U << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 17896 | #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */ |
| AnnaBridge | 172:65be27845400 | 17897 | #define USART_ISR_TXFT_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 17898 | #define USART_ISR_TXFT_Msk (0x1U << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 17899 | #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */ |
| AnnaBridge | 172:65be27845400 | 17900 | |
| AnnaBridge | 172:65be27845400 | 17901 | /******************* Bit definition for USART_ICR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17902 | #define USART_ICR_PECF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17903 | #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17904 | #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17905 | #define USART_ICR_FECF_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17906 | #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17907 | #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17908 | #define USART_ICR_NECF_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17909 | #define USART_ICR_NECF_Msk (0x1U << USART_ICR_NECF_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17910 | #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17911 | #define USART_ICR_ORECF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17912 | #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17913 | #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17914 | #define USART_ICR_IDLECF_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 17915 | #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 17916 | #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17917 | #define USART_ICR_TXFECF_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 17918 | #define USART_ICR_TXFECF_Msk (0x1U << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 17919 | #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17920 | #define USART_ICR_TCCF_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 17921 | #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 17922 | #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17923 | #define USART_ICR_TCBGTCF_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 17924 | #define USART_ICR_TCBGTCF_Msk (0x1U << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 17925 | #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17926 | #define USART_ICR_LBDCF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 17927 | #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 17928 | #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17929 | #define USART_ICR_CTSCF_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 17930 | #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 17931 | #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17932 | #define USART_ICR_RTOCF_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 17933 | #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 17934 | #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17935 | #define USART_ICR_EOBCF_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 17936 | #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 17937 | #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17938 | #define USART_ICR_UDRCF_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 17939 | #define USART_ICR_UDRCF_Msk (0x1U << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 17940 | #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17941 | #define USART_ICR_CMCF_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 17942 | #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 17943 | #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17944 | #define USART_ICR_WUCF_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 17945 | #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 17946 | #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ |
| AnnaBridge | 172:65be27845400 | 17947 | |
| AnnaBridge | 172:65be27845400 | 17948 | /* Legacy defines */ |
| AnnaBridge | 172:65be27845400 | 17949 | #define USART_ICR_NCF_Pos USART_ICR_NECF_Pos |
| AnnaBridge | 172:65be27845400 | 17950 | #define USART_ICR_NCF_Msk USART_ICR_NECF_Msk |
| AnnaBridge | 172:65be27845400 | 17951 | #define USART_ICR_NCF USART_ICR_NECF |
| AnnaBridge | 172:65be27845400 | 17952 | |
| AnnaBridge | 172:65be27845400 | 17953 | /******************* Bit definition for USART_RDR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17954 | #define USART_RDR_RDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17955 | #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 172:65be27845400 | 17956 | #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ |
| AnnaBridge | 172:65be27845400 | 17957 | |
| AnnaBridge | 172:65be27845400 | 17958 | /******************* Bit definition for USART_TDR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17959 | #define USART_TDR_TDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17960 | #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */ |
| AnnaBridge | 172:65be27845400 | 17961 | #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ |
| AnnaBridge | 172:65be27845400 | 17962 | |
| AnnaBridge | 172:65be27845400 | 17963 | /******************* Bit definition for USART_PRESC register ******************/ |
| AnnaBridge | 172:65be27845400 | 17964 | #define USART_PRESC_PRESCALER_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17965 | #define USART_PRESC_PRESCALER_Msk (0xFU << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 17966 | #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ |
| AnnaBridge | 172:65be27845400 | 17967 | #define USART_PRESC_PRESCALER_0 (0x1U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17968 | #define USART_PRESC_PRESCALER_1 (0x2U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17969 | #define USART_PRESC_PRESCALER_2 (0x4U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17970 | #define USART_PRESC_PRESCALER_3 (0x8U << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17971 | |
| AnnaBridge | 172:65be27845400 | 17972 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 17973 | /* */ |
| AnnaBridge | 172:65be27845400 | 17974 | /* VREFBUF */ |
| AnnaBridge | 172:65be27845400 | 17975 | /* */ |
| AnnaBridge | 172:65be27845400 | 17976 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 17977 | /******************* Bit definition for VREFBUF_CSR register ****************/ |
| AnnaBridge | 172:65be27845400 | 17978 | #define VREFBUF_CSR_ENVR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17979 | #define VREFBUF_CSR_ENVR_Msk (0x1U << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 17980 | #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */ |
| AnnaBridge | 172:65be27845400 | 17981 | #define VREFBUF_CSR_HIZ_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 17982 | #define VREFBUF_CSR_HIZ_Msk (0x1U << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 17983 | #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */ |
| AnnaBridge | 172:65be27845400 | 17984 | #define VREFBUF_CSR_VRS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 17985 | #define VREFBUF_CSR_VRS_Msk (0x1U << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 17986 | #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */ |
| AnnaBridge | 172:65be27845400 | 17987 | #define VREFBUF_CSR_VRR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 17988 | #define VREFBUF_CSR_VRR_Msk (0x1U << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 17989 | #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */ |
| AnnaBridge | 172:65be27845400 | 17990 | |
| AnnaBridge | 172:65be27845400 | 17991 | /******************* Bit definition for VREFBUF_CCR register ******************/ |
| AnnaBridge | 172:65be27845400 | 17992 | #define VREFBUF_CCR_TRIM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 17993 | #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */ |
| AnnaBridge | 172:65be27845400 | 17994 | #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */ |
| AnnaBridge | 172:65be27845400 | 17995 | |
| AnnaBridge | 172:65be27845400 | 17996 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 17997 | /* */ |
| AnnaBridge | 172:65be27845400 | 17998 | /* Window WATCHDOG */ |
| AnnaBridge | 172:65be27845400 | 17999 | /* */ |
| AnnaBridge | 172:65be27845400 | 18000 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 18001 | /******************* Bit definition for WWDG_CR register ********************/ |
| AnnaBridge | 172:65be27845400 | 18002 | #define WWDG_CR_T_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18003 | #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 172:65be27845400 | 18004 | #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| AnnaBridge | 172:65be27845400 | 18005 | #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18006 | #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18007 | #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18008 | #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18009 | #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18010 | #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18011 | #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18012 | |
| AnnaBridge | 172:65be27845400 | 18013 | #define WWDG_CR_WDGA_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18014 | #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18015 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ |
| AnnaBridge | 172:65be27845400 | 18016 | |
| AnnaBridge | 172:65be27845400 | 18017 | /******************* Bit definition for WWDG_CFR register *******************/ |
| AnnaBridge | 172:65be27845400 | 18018 | #define WWDG_CFR_W_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18019 | #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 172:65be27845400 | 18020 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ |
| AnnaBridge | 172:65be27845400 | 18021 | #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18022 | #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18023 | #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18024 | #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18025 | #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18026 | #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18027 | #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18028 | |
| AnnaBridge | 172:65be27845400 | 18029 | #define WWDG_CFR_WDGTB_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18030 | #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
| AnnaBridge | 172:65be27845400 | 18031 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */ |
| AnnaBridge | 172:65be27845400 | 18032 | #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18033 | #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18034 | |
| AnnaBridge | 172:65be27845400 | 18035 | #define WWDG_CFR_EWI_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 18036 | #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18037 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ |
| AnnaBridge | 172:65be27845400 | 18038 | |
| AnnaBridge | 172:65be27845400 | 18039 | /******************* Bit definition for WWDG_SR register ********************/ |
| AnnaBridge | 172:65be27845400 | 18040 | #define WWDG_SR_EWIF_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18041 | #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18042 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ |
| AnnaBridge | 172:65be27845400 | 18043 | |
| AnnaBridge | 172:65be27845400 | 18044 | |
| AnnaBridge | 172:65be27845400 | 18045 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 18046 | /* */ |
| AnnaBridge | 172:65be27845400 | 18047 | /* Debug MCU */ |
| AnnaBridge | 172:65be27845400 | 18048 | /* */ |
| AnnaBridge | 172:65be27845400 | 18049 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 18050 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
| AnnaBridge | 172:65be27845400 | 18051 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18052 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 18053 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk |
| AnnaBridge | 172:65be27845400 | 18054 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18055 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 18056 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk |
| AnnaBridge | 172:65be27845400 | 18057 | |
| AnnaBridge | 172:65be27845400 | 18058 | /******************** Bit definition for DBGMCU_CR register *****************/ |
| AnnaBridge | 172:65be27845400 | 18059 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18060 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18061 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk |
| AnnaBridge | 172:65be27845400 | 18062 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18063 | #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18064 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18065 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18066 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18067 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk |
| AnnaBridge | 172:65be27845400 | 18068 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18069 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18070 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk |
| AnnaBridge | 172:65be27845400 | 18071 | |
| AnnaBridge | 172:65be27845400 | 18072 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18073 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
| AnnaBridge | 172:65be27845400 | 18074 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk |
| AnnaBridge | 172:65be27845400 | 18075 | #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18076 | #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18077 | |
| AnnaBridge | 172:65be27845400 | 18078 | /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/ |
| AnnaBridge | 172:65be27845400 | 18079 | #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18080 | #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18081 | #define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18082 | #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18083 | #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18084 | #define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18085 | #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18086 | #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18087 | #define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18088 | #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18089 | #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18090 | #define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18091 | #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18092 | #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18093 | #define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18094 | #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18095 | #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18096 | #define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18097 | #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 18098 | #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18099 | #define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18100 | #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 18101 | #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18102 | #define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18103 | #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 18104 | #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 18105 | #define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18106 | #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18107 | #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18108 | #define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18109 | #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 18110 | #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18111 | #define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18112 | #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 18113 | #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18114 | #define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18115 | #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 18116 | #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18117 | #define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18118 | #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 18119 | #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 18120 | #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18121 | |
| AnnaBridge | 172:65be27845400 | 18122 | /******************** Bit definition for DBGMCU_APB1FZR2 register **********/ |
| AnnaBridge | 172:65be27845400 | 18123 | #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18124 | #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18125 | #define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18126 | #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18127 | #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18128 | #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18129 | |
| AnnaBridge | 172:65be27845400 | 18130 | /******************** Bit definition for DBGMCU_APB2FZ register ************/ |
| AnnaBridge | 172:65be27845400 | 18131 | #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 18132 | #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18133 | #define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18134 | #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 18135 | #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 18136 | #define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18137 | #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18138 | #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18139 | #define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18140 | #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18141 | #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18142 | #define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18143 | #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 18144 | #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18145 | #define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk |
| AnnaBridge | 172:65be27845400 | 18146 | |
| AnnaBridge | 172:65be27845400 | 18147 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 18148 | /* */ |
| AnnaBridge | 172:65be27845400 | 18149 | /* USB_OTG */ |
| AnnaBridge | 172:65be27845400 | 18150 | /* */ |
| AnnaBridge | 172:65be27845400 | 18151 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 18152 | /******************** Bit definition for USB_OTG_GOTGCTL register ********************/ |
| AnnaBridge | 172:65be27845400 | 18153 | #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18154 | #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18155 | #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ |
| AnnaBridge | 172:65be27845400 | 18156 | #define USB_OTG_GOTGCTL_SRQ_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18157 | #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18158 | #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ |
| AnnaBridge | 172:65be27845400 | 18159 | #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18160 | #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18161 | #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ |
| AnnaBridge | 172:65be27845400 | 18162 | #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18163 | #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18164 | #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ |
| AnnaBridge | 172:65be27845400 | 18165 | #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18166 | #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18167 | #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ |
| AnnaBridge | 172:65be27845400 | 18168 | #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18169 | #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18170 | #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ |
| AnnaBridge | 172:65be27845400 | 18171 | #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18172 | #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18173 | #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ |
| AnnaBridge | 172:65be27845400 | 18174 | #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18175 | #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18176 | #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ |
| AnnaBridge | 172:65be27845400 | 18177 | #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 18178 | #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18179 | #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid*/ |
| AnnaBridge | 172:65be27845400 | 18180 | |
| AnnaBridge | 172:65be27845400 | 18181 | /******************** Bit definition for USB_OTG_HCFG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18182 | |
| AnnaBridge | 172:65be27845400 | 18183 | #define USB_OTG_HCFG_FSLSPCS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18184 | #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 18185 | #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ |
| AnnaBridge | 172:65be27845400 | 18186 | #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18187 | #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18188 | #define USB_OTG_HCFG_FSLSS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18189 | #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18190 | #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ |
| AnnaBridge | 172:65be27845400 | 18191 | |
| AnnaBridge | 172:65be27845400 | 18192 | /******************** Bit definition for USB_OTG_DCFG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18193 | |
| AnnaBridge | 172:65be27845400 | 18194 | #define USB_OTG_DCFG_DSPD_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18195 | #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ |
| AnnaBridge | 172:65be27845400 | 18196 | #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ |
| AnnaBridge | 172:65be27845400 | 18197 | #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18198 | #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18199 | #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18200 | #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18201 | #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ |
| AnnaBridge | 172:65be27845400 | 18202 | #define USB_OTG_DCFG_DAD_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18203 | #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ |
| AnnaBridge | 172:65be27845400 | 18204 | #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ |
| AnnaBridge | 172:65be27845400 | 18205 | #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18206 | #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18207 | #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18208 | #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18209 | #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18210 | #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18211 | #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18212 | #define USB_OTG_DCFG_PFIVL_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 18213 | #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ |
| AnnaBridge | 172:65be27845400 | 18214 | #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ |
| AnnaBridge | 172:65be27845400 | 18215 | #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18216 | #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 18217 | #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18218 | #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ |
| AnnaBridge | 172:65be27845400 | 18219 | #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ |
| AnnaBridge | 172:65be27845400 | 18220 | #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18221 | #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18222 | |
| AnnaBridge | 172:65be27845400 | 18223 | /******************** Bit definition for USB_OTG_PCGCR register ********************/ |
| AnnaBridge | 172:65be27845400 | 18224 | #define USB_OTG_PCGCR_STPPCLK_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18225 | #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18226 | #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ |
| AnnaBridge | 172:65be27845400 | 18227 | #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18228 | #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18229 | #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ |
| AnnaBridge | 172:65be27845400 | 18230 | #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18231 | #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18232 | #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ |
| AnnaBridge | 172:65be27845400 | 18233 | |
| AnnaBridge | 172:65be27845400 | 18234 | /******************** Bit definition for USB_OTG_GOTGINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 18235 | #define USB_OTG_GOTGINT_SEDET_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18236 | #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18237 | #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ |
| AnnaBridge | 172:65be27845400 | 18238 | #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18239 | #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18240 | #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ |
| AnnaBridge | 172:65be27845400 | 18241 | #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 18242 | #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18243 | #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ |
| AnnaBridge | 172:65be27845400 | 18244 | #define USB_OTG_GOTGINT_HNGDET_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18245 | #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18246 | #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ |
| AnnaBridge | 172:65be27845400 | 18247 | #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 18248 | #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18249 | #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ |
| AnnaBridge | 172:65be27845400 | 18250 | #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 18251 | #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18252 | #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ |
| AnnaBridge | 172:65be27845400 | 18253 | |
| AnnaBridge | 172:65be27845400 | 18254 | /******************** Bit definition for USB_OTG_DCTL register ********************/ |
| AnnaBridge | 172:65be27845400 | 18255 | #define USB_OTG_DCTL_RWUSIG_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18256 | #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18257 | #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ |
| AnnaBridge | 172:65be27845400 | 18258 | #define USB_OTG_DCTL_SDIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18259 | #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18260 | #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ |
| AnnaBridge | 172:65be27845400 | 18261 | #define USB_OTG_DCTL_GINSTS_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18262 | #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18263 | #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ |
| AnnaBridge | 172:65be27845400 | 18264 | #define USB_OTG_DCTL_GONSTS_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18265 | #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18266 | #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ |
| AnnaBridge | 172:65be27845400 | 18267 | |
| AnnaBridge | 172:65be27845400 | 18268 | #define USB_OTG_DCTL_TCTL_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18269 | #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ |
| AnnaBridge | 172:65be27845400 | 18270 | #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ |
| AnnaBridge | 172:65be27845400 | 18271 | #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18272 | #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18273 | #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18274 | #define USB_OTG_DCTL_SGINAK_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18275 | #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18276 | #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ |
| AnnaBridge | 172:65be27845400 | 18277 | #define USB_OTG_DCTL_CGINAK_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18278 | #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18279 | #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ |
| AnnaBridge | 172:65be27845400 | 18280 | #define USB_OTG_DCTL_SGONAK_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 18281 | #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18282 | #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ |
| AnnaBridge | 172:65be27845400 | 18283 | #define USB_OTG_DCTL_CGONAK_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 18284 | #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18285 | #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ |
| AnnaBridge | 172:65be27845400 | 18286 | #define USB_OTG_DCTL_POPRGDNE_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 18287 | #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18288 | #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ |
| AnnaBridge | 172:65be27845400 | 18289 | |
| AnnaBridge | 172:65be27845400 | 18290 | /******************** Bit definition for USB_OTG_HFIR register ********************/ |
| AnnaBridge | 172:65be27845400 | 18291 | #define USB_OTG_HFIR_FRIVL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18292 | #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18293 | #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ |
| AnnaBridge | 172:65be27845400 | 18294 | |
| AnnaBridge | 172:65be27845400 | 18295 | /******************** Bit definition for USB_OTG_HFNUM register ********************/ |
| AnnaBridge | 172:65be27845400 | 18296 | #define USB_OTG_HFNUM_FRNUM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18297 | #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18298 | #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ |
| AnnaBridge | 172:65be27845400 | 18299 | #define USB_OTG_HFNUM_FTREM_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18300 | #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 18301 | #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ |
| AnnaBridge | 172:65be27845400 | 18302 | |
| AnnaBridge | 172:65be27845400 | 18303 | /******************** Bit definition for USB_OTG_DSTS register ********************/ |
| AnnaBridge | 172:65be27845400 | 18304 | #define USB_OTG_DSTS_SUSPSTS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18305 | #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18306 | #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ |
| AnnaBridge | 172:65be27845400 | 18307 | |
| AnnaBridge | 172:65be27845400 | 18308 | #define USB_OTG_DSTS_ENUMSPD_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18309 | #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ |
| AnnaBridge | 172:65be27845400 | 18310 | #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ |
| AnnaBridge | 172:65be27845400 | 18311 | #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18312 | #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18313 | #define USB_OTG_DSTS_EERR_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18314 | #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18315 | #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ |
| AnnaBridge | 172:65be27845400 | 18316 | #define USB_OTG_DSTS_FNSOF_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18317 | #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ |
| AnnaBridge | 172:65be27845400 | 18318 | #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ |
| AnnaBridge | 172:65be27845400 | 18319 | |
| AnnaBridge | 172:65be27845400 | 18320 | /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18321 | #define USB_OTG_GAHBCFG_GINT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18322 | #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18323 | #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18324 | #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18325 | #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ |
| AnnaBridge | 172:65be27845400 | 18326 | #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ |
| AnnaBridge | 172:65be27845400 | 18327 | #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18328 | #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18329 | #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18330 | #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18331 | #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18332 | #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18333 | #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ |
| AnnaBridge | 172:65be27845400 | 18334 | #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18335 | #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18336 | #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ |
| AnnaBridge | 172:65be27845400 | 18337 | #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18338 | #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18339 | #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ |
| AnnaBridge | 172:65be27845400 | 18340 | |
| AnnaBridge | 172:65be27845400 | 18341 | /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18342 | |
| AnnaBridge | 172:65be27845400 | 18343 | #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18344 | #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ |
| AnnaBridge | 172:65be27845400 | 18345 | #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ |
| AnnaBridge | 172:65be27845400 | 18346 | #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18347 | #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18348 | #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18349 | #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18350 | #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18351 | #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ |
| AnnaBridge | 172:65be27845400 | 18352 | #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18353 | #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18354 | #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ |
| AnnaBridge | 172:65be27845400 | 18355 | #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 18356 | #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18357 | #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ |
| AnnaBridge | 172:65be27845400 | 18358 | #define USB_OTG_GUSBCFG_TRDT_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 18359 | #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ |
| AnnaBridge | 172:65be27845400 | 18360 | #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ |
| AnnaBridge | 172:65be27845400 | 18361 | #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18362 | #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18363 | #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 18364 | #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 18365 | #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18366 | #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 18367 | #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ |
| AnnaBridge | 172:65be27845400 | 18368 | #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18369 | #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18370 | #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ |
| AnnaBridge | 172:65be27845400 | 18371 | #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 18372 | #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18373 | #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ |
| AnnaBridge | 172:65be27845400 | 18374 | #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 18375 | #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18376 | #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ |
| AnnaBridge | 172:65be27845400 | 18377 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 18378 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18379 | #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ |
| AnnaBridge | 172:65be27845400 | 18380 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18381 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18382 | #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ |
| AnnaBridge | 172:65be27845400 | 18383 | #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 18384 | #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18385 | #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ |
| AnnaBridge | 172:65be27845400 | 18386 | #define USB_OTG_GUSBCFG_PCCI_Pos (23U) |
| AnnaBridge | 172:65be27845400 | 18387 | #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18388 | #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ |
| AnnaBridge | 172:65be27845400 | 18389 | #define USB_OTG_GUSBCFG_PTCI_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18390 | #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18391 | #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ |
| AnnaBridge | 172:65be27845400 | 18392 | #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 18393 | #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18394 | #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ |
| AnnaBridge | 172:65be27845400 | 18395 | #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 18396 | #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 18397 | #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ |
| AnnaBridge | 172:65be27845400 | 18398 | #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 18399 | #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 18400 | #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ |
| AnnaBridge | 172:65be27845400 | 18401 | #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 18402 | #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 18403 | #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ |
| AnnaBridge | 172:65be27845400 | 18404 | |
| AnnaBridge | 172:65be27845400 | 18405 | /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ |
| AnnaBridge | 172:65be27845400 | 18406 | #define USB_OTG_GRSTCTL_CSRST_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18407 | #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18408 | #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ |
| AnnaBridge | 172:65be27845400 | 18409 | #define USB_OTG_GRSTCTL_HSRST_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18410 | #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18411 | #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ |
| AnnaBridge | 172:65be27845400 | 18412 | #define USB_OTG_GRSTCTL_FCRST_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18413 | #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18414 | #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ |
| AnnaBridge | 172:65be27845400 | 18415 | #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18416 | #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18417 | #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ |
| AnnaBridge | 172:65be27845400 | 18418 | #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18419 | #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18420 | #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ |
| AnnaBridge | 172:65be27845400 | 18421 | #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18422 | #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ |
| AnnaBridge | 172:65be27845400 | 18423 | #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ |
| AnnaBridge | 172:65be27845400 | 18424 | #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18425 | #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18426 | #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18427 | #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18428 | #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18429 | #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 18430 | #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 18431 | #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ |
| AnnaBridge | 172:65be27845400 | 18432 | #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 18433 | #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 18434 | #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ |
| AnnaBridge | 172:65be27845400 | 18435 | |
| AnnaBridge | 172:65be27845400 | 18436 | /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 18437 | #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18438 | #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18439 | #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18440 | #define USB_OTG_DIEPMSK_EPDM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18441 | #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18442 | #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18443 | #define USB_OTG_DIEPMSK_TOM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18444 | #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18445 | #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
| AnnaBridge | 172:65be27845400 | 18446 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18447 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18448 | #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| AnnaBridge | 172:65be27845400 | 18449 | #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18450 | #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18451 | #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| AnnaBridge | 172:65be27845400 | 18452 | #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18453 | #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18454 | #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| AnnaBridge | 172:65be27845400 | 18455 | #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18456 | #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18457 | #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ |
| AnnaBridge | 172:65be27845400 | 18458 | #define USB_OTG_DIEPMSK_BIM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 18459 | #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18460 | #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18461 | |
| AnnaBridge | 172:65be27845400 | 18462 | /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ |
| AnnaBridge | 172:65be27845400 | 18463 | #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18464 | #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18465 | #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ |
| AnnaBridge | 172:65be27845400 | 18466 | #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18467 | #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 18468 | #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ |
| AnnaBridge | 172:65be27845400 | 18469 | #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18470 | #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18471 | #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18472 | #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18473 | #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18474 | #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18475 | #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18476 | #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18477 | |
| AnnaBridge | 172:65be27845400 | 18478 | #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18479 | #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ |
| AnnaBridge | 172:65be27845400 | 18480 | #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ |
| AnnaBridge | 172:65be27845400 | 18481 | #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18482 | #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18483 | #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 18484 | #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 18485 | #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 18486 | #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 18487 | #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 18488 | #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 18489 | |
| AnnaBridge | 172:65be27845400 | 18490 | /******************** Bit definition for USB_OTG_HAINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 18491 | #define USB_OTG_HAINT_HAINT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18492 | #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18493 | #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ |
| AnnaBridge | 172:65be27845400 | 18494 | |
| AnnaBridge | 172:65be27845400 | 18495 | /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 18496 | #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18497 | #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18498 | #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18499 | #define USB_OTG_DOEPMSK_EPDM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18500 | #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18501 | #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18502 | #define USB_OTG_DOEPMSK_STUPM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18503 | #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18504 | #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ |
| AnnaBridge | 172:65be27845400 | 18505 | #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18506 | #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18507 | #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ |
| AnnaBridge | 172:65be27845400 | 18508 | #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18509 | #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18510 | #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ |
| AnnaBridge | 172:65be27845400 | 18511 | #define USB_OTG_DOEPMSK_OPEM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18512 | #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18513 | #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ |
| AnnaBridge | 172:65be27845400 | 18514 | #define USB_OTG_DOEPMSK_BOIM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 18515 | #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18516 | #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18517 | |
| AnnaBridge | 172:65be27845400 | 18518 | /******************** Bit definition for USB_OTG_GINTSTS register ********************/ |
| AnnaBridge | 172:65be27845400 | 18519 | #define USB_OTG_GINTSTS_CMOD_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18520 | #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18521 | #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ |
| AnnaBridge | 172:65be27845400 | 18522 | #define USB_OTG_GINTSTS_MMIS_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18523 | #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18524 | #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ |
| AnnaBridge | 172:65be27845400 | 18525 | #define USB_OTG_GINTSTS_OTGINT_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18526 | #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18527 | #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ |
| AnnaBridge | 172:65be27845400 | 18528 | #define USB_OTG_GINTSTS_SOF_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18529 | #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18530 | #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ |
| AnnaBridge | 172:65be27845400 | 18531 | #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18532 | #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18533 | #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ |
| AnnaBridge | 172:65be27845400 | 18534 | #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18535 | #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18536 | #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ |
| AnnaBridge | 172:65be27845400 | 18537 | #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18538 | #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18539 | #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ |
| AnnaBridge | 172:65be27845400 | 18540 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18541 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18542 | #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ |
| AnnaBridge | 172:65be27845400 | 18543 | #define USB_OTG_GINTSTS_ESUSP_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 18544 | #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18545 | #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ |
| AnnaBridge | 172:65be27845400 | 18546 | #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 18547 | #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18548 | #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ |
| AnnaBridge | 172:65be27845400 | 18549 | #define USB_OTG_GINTSTS_USBRST_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 18550 | #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 18551 | #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ |
| AnnaBridge | 172:65be27845400 | 18552 | #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 18553 | #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 18554 | #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ |
| AnnaBridge | 172:65be27845400 | 18555 | #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 18556 | #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 18557 | #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ |
| AnnaBridge | 172:65be27845400 | 18558 | #define USB_OTG_GINTSTS_EOPF_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18559 | #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 18560 | #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ |
| AnnaBridge | 172:65be27845400 | 18561 | #define USB_OTG_GINTSTS_IEPINT_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 18562 | #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18563 | #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ |
| AnnaBridge | 172:65be27845400 | 18564 | #define USB_OTG_GINTSTS_OEPINT_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 18565 | #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18566 | #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ |
| AnnaBridge | 172:65be27845400 | 18567 | #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 18568 | #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18569 | #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ |
| AnnaBridge | 172:65be27845400 | 18570 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18571 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18572 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ |
| AnnaBridge | 172:65be27845400 | 18573 | #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 18574 | #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18575 | #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ |
| AnnaBridge | 172:65be27845400 | 18576 | #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18577 | #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18578 | #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ |
| AnnaBridge | 172:65be27845400 | 18579 | #define USB_OTG_GINTSTS_HCINT_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 18580 | #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18581 | #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ |
| AnnaBridge | 172:65be27845400 | 18582 | #define USB_OTG_GINTSTS_PTXFE_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 18583 | #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 18584 | #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ |
| AnnaBridge | 172:65be27845400 | 18585 | #define USB_OTG_GINTSTS_LPMINT_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 18586 | #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 18587 | #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ |
| AnnaBridge | 172:65be27845400 | 18588 | #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 18589 | #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 18590 | #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ |
| AnnaBridge | 172:65be27845400 | 18591 | #define USB_OTG_GINTSTS_DISCINT_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 18592 | #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 18593 | #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ |
| AnnaBridge | 172:65be27845400 | 18594 | #define USB_OTG_GINTSTS_SRQINT_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 18595 | #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 18596 | #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ |
| AnnaBridge | 172:65be27845400 | 18597 | #define USB_OTG_GINTSTS_WKUINT_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 18598 | #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 18599 | #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ |
| AnnaBridge | 172:65be27845400 | 18600 | |
| AnnaBridge | 172:65be27845400 | 18601 | /******************** Bit definition for USB_OTG_GINTMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 18602 | |
| AnnaBridge | 172:65be27845400 | 18603 | #define USB_OTG_GINTMSK_MMISM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18604 | #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18605 | #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18606 | #define USB_OTG_GINTMSK_OTGINT_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18607 | #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18608 | #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18609 | #define USB_OTG_GINTMSK_SOFM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18610 | #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18611 | #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ |
| AnnaBridge | 172:65be27845400 | 18612 | #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18613 | #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18614 | #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ |
| AnnaBridge | 172:65be27845400 | 18615 | #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 18616 | #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18617 | #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ |
| AnnaBridge | 172:65be27845400 | 18618 | #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18619 | #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18620 | #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ |
| AnnaBridge | 172:65be27845400 | 18621 | #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18622 | #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18623 | #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ |
| AnnaBridge | 172:65be27845400 | 18624 | #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 18625 | #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18626 | #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ |
| AnnaBridge | 172:65be27845400 | 18627 | #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 18628 | #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 18629 | #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ |
| AnnaBridge | 172:65be27845400 | 18630 | #define USB_OTG_GINTMSK_USBRST_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 18631 | #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 18632 | #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ |
| AnnaBridge | 172:65be27845400 | 18633 | #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 18634 | #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 18635 | #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ |
| AnnaBridge | 172:65be27845400 | 18636 | #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 18637 | #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 18638 | #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18639 | #define USB_OTG_GINTMSK_EOPFM_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18640 | #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 18641 | #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18642 | #define USB_OTG_GINTMSK_EPMISM_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18643 | #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18644 | #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18645 | #define USB_OTG_GINTMSK_IEPINT_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 18646 | #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18647 | #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18648 | #define USB_OTG_GINTMSK_OEPINT_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 18649 | #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18650 | #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18651 | #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 18652 | #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18653 | #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ |
| AnnaBridge | 172:65be27845400 | 18654 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18655 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18656 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ |
| AnnaBridge | 172:65be27845400 | 18657 | #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 18658 | #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18659 | #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ |
| AnnaBridge | 172:65be27845400 | 18660 | #define USB_OTG_GINTMSK_PRTIM_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18661 | #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18662 | #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18663 | #define USB_OTG_GINTMSK_HCIM_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 18664 | #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18665 | #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18666 | #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 18667 | #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 18668 | #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ |
| AnnaBridge | 172:65be27845400 | 18669 | #define USB_OTG_GINTMSK_LPMINTM_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 18670 | #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 18671 | #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ |
| AnnaBridge | 172:65be27845400 | 18672 | #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 18673 | #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 18674 | #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ |
| AnnaBridge | 172:65be27845400 | 18675 | #define USB_OTG_GINTMSK_DISCINT_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 18676 | #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 18677 | #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18678 | #define USB_OTG_GINTMSK_SRQIM_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 18679 | #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 18680 | #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18681 | #define USB_OTG_GINTMSK_WUIM_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 18682 | #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 18683 | #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18684 | |
| AnnaBridge | 172:65be27845400 | 18685 | /******************** Bit definition for USB_OTG_DAINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 18686 | #define USB_OTG_DAINT_IEPINT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18687 | #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18688 | #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ |
| AnnaBridge | 172:65be27845400 | 18689 | #define USB_OTG_DAINT_OEPINT_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18690 | #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 18691 | #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ |
| AnnaBridge | 172:65be27845400 | 18692 | |
| AnnaBridge | 172:65be27845400 | 18693 | /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 18694 | #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18695 | #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18696 | #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 18697 | |
| AnnaBridge | 172:65be27845400 | 18698 | /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ |
| AnnaBridge | 172:65be27845400 | 18699 | #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18700 | #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 18701 | #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18702 | #define USB_OTG_GRXSTSP_BCNT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18703 | #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ |
| AnnaBridge | 172:65be27845400 | 18704 | #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18705 | #define USB_OTG_GRXSTSP_DPID_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18706 | #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ |
| AnnaBridge | 172:65be27845400 | 18707 | #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18708 | #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18709 | #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 172:65be27845400 | 18710 | #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18711 | |
| AnnaBridge | 172:65be27845400 | 18712 | /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 18713 | #define USB_OTG_DAINTMSK_IEPM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18714 | #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18715 | #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18716 | #define USB_OTG_DAINTMSK_OEPM_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18717 | #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 18718 | #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18719 | |
| AnnaBridge | 172:65be27845400 | 18720 | /******************** Bit definition for OTG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18721 | |
| AnnaBridge | 172:65be27845400 | 18722 | #define USB_OTG_CHNUM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18723 | #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 18724 | #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ |
| AnnaBridge | 172:65be27845400 | 18725 | #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18726 | #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18727 | #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18728 | #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18729 | #define USB_OTG_BCNT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18730 | #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ |
| AnnaBridge | 172:65be27845400 | 18731 | #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ |
| AnnaBridge | 172:65be27845400 | 18732 | #define USB_OTG_DPID_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18733 | #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ |
| AnnaBridge | 172:65be27845400 | 18734 | #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ |
| AnnaBridge | 172:65be27845400 | 18735 | #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 18736 | #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18737 | #define USB_OTG_PKTSTS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18738 | #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 172:65be27845400 | 18739 | #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ |
| AnnaBridge | 172:65be27845400 | 18740 | #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18741 | #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18742 | #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18743 | #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18744 | #define USB_OTG_EPNUM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18745 | #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 18746 | #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ |
| AnnaBridge | 172:65be27845400 | 18747 | #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18748 | #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18749 | #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18750 | #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18751 | #define USB_OTG_FRMNUM_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18752 | #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ |
| AnnaBridge | 172:65be27845400 | 18753 | #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ |
| AnnaBridge | 172:65be27845400 | 18754 | #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18755 | #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18756 | #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18757 | #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18758 | |
| AnnaBridge | 172:65be27845400 | 18759 | /******************** Bit definition for OTG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18760 | |
| AnnaBridge | 172:65be27845400 | 18761 | #define USB_OTG_CHNUM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18762 | #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 18763 | #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ |
| AnnaBridge | 172:65be27845400 | 18764 | #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18765 | #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18766 | #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18767 | #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18768 | #define USB_OTG_BCNT_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 18769 | #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ |
| AnnaBridge | 172:65be27845400 | 18770 | #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ |
| AnnaBridge | 172:65be27845400 | 18771 | #define USB_OTG_DPID_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18772 | #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ |
| AnnaBridge | 172:65be27845400 | 18773 | #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ |
| AnnaBridge | 172:65be27845400 | 18774 | #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 18775 | #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18776 | #define USB_OTG_PKTSTS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18777 | #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 172:65be27845400 | 18778 | #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ |
| AnnaBridge | 172:65be27845400 | 18779 | #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18780 | #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18781 | #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18782 | #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18783 | #define USB_OTG_EPNUM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18784 | #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ |
| AnnaBridge | 172:65be27845400 | 18785 | #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ |
| AnnaBridge | 172:65be27845400 | 18786 | #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18787 | #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18788 | #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18789 | #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18790 | #define USB_OTG_FRMNUM_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18791 | #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ |
| AnnaBridge | 172:65be27845400 | 18792 | #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ |
| AnnaBridge | 172:65be27845400 | 18793 | #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18794 | #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18795 | #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18796 | #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18797 | |
| AnnaBridge | 172:65be27845400 | 18798 | /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ |
| AnnaBridge | 172:65be27845400 | 18799 | #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18800 | #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18801 | #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ |
| AnnaBridge | 172:65be27845400 | 18802 | |
| AnnaBridge | 172:65be27845400 | 18803 | /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ |
| AnnaBridge | 172:65be27845400 | 18804 | #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18805 | #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18806 | #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ |
| AnnaBridge | 172:65be27845400 | 18807 | |
| AnnaBridge | 172:65be27845400 | 18808 | /******************** Bit definition for OTG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18809 | #define USB_OTG_NPTXFSA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18810 | #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18811 | #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ |
| AnnaBridge | 172:65be27845400 | 18812 | #define USB_OTG_NPTXFD_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18813 | #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 18814 | #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ |
| AnnaBridge | 172:65be27845400 | 18815 | #define USB_OTG_TX0FSA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18816 | #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18817 | #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ |
| AnnaBridge | 172:65be27845400 | 18818 | #define USB_OTG_TX0FD_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18819 | #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 18820 | #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ |
| AnnaBridge | 172:65be27845400 | 18821 | |
| AnnaBridge | 172:65be27845400 | 18822 | /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ |
| AnnaBridge | 172:65be27845400 | 18823 | #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18824 | #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ |
| AnnaBridge | 172:65be27845400 | 18825 | #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ |
| AnnaBridge | 172:65be27845400 | 18826 | |
| AnnaBridge | 172:65be27845400 | 18827 | /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ |
| AnnaBridge | 172:65be27845400 | 18828 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18829 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18830 | #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ |
| AnnaBridge | 172:65be27845400 | 18831 | |
| AnnaBridge | 172:65be27845400 | 18832 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18833 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ |
| AnnaBridge | 172:65be27845400 | 18834 | #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ |
| AnnaBridge | 172:65be27845400 | 18835 | #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18836 | #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18837 | #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18838 | #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18839 | #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18840 | #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18841 | #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18842 | #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18843 | |
| AnnaBridge | 172:65be27845400 | 18844 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18845 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ |
| AnnaBridge | 172:65be27845400 | 18846 | #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ |
| AnnaBridge | 172:65be27845400 | 18847 | #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18848 | #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18849 | #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 18850 | #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 18851 | #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 18852 | #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 18853 | #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 18854 | |
| AnnaBridge | 172:65be27845400 | 18855 | /******************** Bit definition for USB_OTG_DTHRCTL register ***************/ |
| AnnaBridge | 172:65be27845400 | 18856 | #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18857 | #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18858 | #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ |
| AnnaBridge | 172:65be27845400 | 18859 | #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18860 | #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18861 | #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ |
| AnnaBridge | 172:65be27845400 | 18862 | |
| AnnaBridge | 172:65be27845400 | 18863 | #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18864 | #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ |
| AnnaBridge | 172:65be27845400 | 18865 | #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ |
| AnnaBridge | 172:65be27845400 | 18866 | #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18867 | #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18868 | #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 18869 | #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 18870 | #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18871 | #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18872 | #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 18873 | #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 18874 | #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 18875 | #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18876 | #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18877 | #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ |
| AnnaBridge | 172:65be27845400 | 18878 | |
| AnnaBridge | 172:65be27845400 | 18879 | #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18880 | #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ |
| AnnaBridge | 172:65be27845400 | 18881 | #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ |
| AnnaBridge | 172:65be27845400 | 18882 | #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18883 | #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18884 | #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18885 | #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18886 | #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18887 | #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 18888 | #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 18889 | #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18890 | #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 18891 | #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 18892 | #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 18893 | #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ |
| AnnaBridge | 172:65be27845400 | 18894 | |
| AnnaBridge | 172:65be27845400 | 18895 | /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/ |
| AnnaBridge | 172:65be27845400 | 18896 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18897 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 18898 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ |
| AnnaBridge | 172:65be27845400 | 18899 | |
| AnnaBridge | 172:65be27845400 | 18900 | /******************** Bit definition for USB_OTG_DEACHINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 18901 | #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18902 | #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18903 | #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ |
| AnnaBridge | 172:65be27845400 | 18904 | #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18905 | #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18906 | #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ |
| AnnaBridge | 172:65be27845400 | 18907 | |
| AnnaBridge | 172:65be27845400 | 18908 | /******************** Bit definition for USB_OTG_GCCFG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18909 | #define USB_OTG_GCCFG_DCDET_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18910 | #define USB_OTG_GCCFG_DCDET_Msk (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 18911 | #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ |
| AnnaBridge | 172:65be27845400 | 18912 | #define USB_OTG_GCCFG_PDET_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18913 | #define USB_OTG_GCCFG_PDET_Msk (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18914 | #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */ |
| AnnaBridge | 172:65be27845400 | 18915 | #define USB_OTG_GCCFG_SDET_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 18916 | #define USB_OTG_GCCFG_SDET_Msk (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 18917 | #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ |
| AnnaBridge | 172:65be27845400 | 18918 | #define USB_OTG_GCCFG_PS2DET_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 18919 | #define USB_OTG_GCCFG_PS2DET_Msk (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 18920 | #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ |
| AnnaBridge | 172:65be27845400 | 18921 | #define USB_OTG_GCCFG_PWRDWN_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18922 | #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18923 | #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ |
| AnnaBridge | 172:65be27845400 | 18924 | #define USB_OTG_GCCFG_BCDEN_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18925 | #define USB_OTG_GCCFG_BCDEN_Msk (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18926 | #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ |
| AnnaBridge | 172:65be27845400 | 18927 | #define USB_OTG_GCCFG_DCDEN_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 18928 | #define USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 18929 | #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ |
| AnnaBridge | 172:65be27845400 | 18930 | #define USB_OTG_GCCFG_PDEN_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 18931 | #define USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 18932 | #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ |
| AnnaBridge | 172:65be27845400 | 18933 | #define USB_OTG_GCCFG_SDEN_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 18934 | #define USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 18935 | #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ |
| AnnaBridge | 172:65be27845400 | 18936 | #define USB_OTG_GCCFG_VBDEN_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18937 | #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 18938 | #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */ |
| AnnaBridge | 172:65be27845400 | 18939 | |
| AnnaBridge | 172:65be27845400 | 18940 | /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ |
| AnnaBridge | 172:65be27845400 | 18941 | #define USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18942 | #define USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 18943 | #define USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */ |
| AnnaBridge | 172:65be27845400 | 18944 | |
| AnnaBridge | 172:65be27845400 | 18945 | /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 18946 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 18947 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 18948 | #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ |
| AnnaBridge | 172:65be27845400 | 18949 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18950 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 18951 | #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ |
| AnnaBridge | 172:65be27845400 | 18952 | |
| AnnaBridge | 172:65be27845400 | 18953 | /******************** Bit definition for USB_OTG_CID register ********************/ |
| AnnaBridge | 172:65be27845400 | 18954 | #define USB_OTG_CID_PRODUCT_ID_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 18955 | #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 18956 | #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ |
| AnnaBridge | 172:65be27845400 | 18957 | |
| AnnaBridge | 172:65be27845400 | 18958 | |
| AnnaBridge | 172:65be27845400 | 18959 | /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/ |
| AnnaBridge | 172:65be27845400 | 18960 | #define USB_OTG_GHWCFG3_LPMMode_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 18961 | #define USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 18962 | #define USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ |
| AnnaBridge | 172:65be27845400 | 18963 | |
| AnnaBridge | 172:65be27845400 | 18964 | /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ |
| AnnaBridge | 172:65be27845400 | 18965 | #define USB_OTG_GLPMCFG_ENBESL_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 18966 | #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 18967 | #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ |
| AnnaBridge | 172:65be27845400 | 18968 | #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) |
| AnnaBridge | 172:65be27845400 | 18969 | #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ |
| AnnaBridge | 172:65be27845400 | 18970 | #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ |
| AnnaBridge | 172:65be27845400 | 18971 | #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) |
| AnnaBridge | 172:65be27845400 | 18972 | #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 18973 | #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ |
| AnnaBridge | 172:65be27845400 | 18974 | #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 18975 | #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ |
| AnnaBridge | 172:65be27845400 | 18976 | #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ |
| AnnaBridge | 172:65be27845400 | 18977 | #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 18978 | #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ |
| AnnaBridge | 172:65be27845400 | 18979 | #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ |
| AnnaBridge | 172:65be27845400 | 18980 | #define USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 18981 | #define USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 18982 | #define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ |
| AnnaBridge | 172:65be27845400 | 18983 | #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 18984 | #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 18985 | #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ |
| AnnaBridge | 172:65be27845400 | 18986 | #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 18987 | #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ |
| AnnaBridge | 172:65be27845400 | 18988 | #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ |
| AnnaBridge | 172:65be27845400 | 18989 | #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 18990 | #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 18991 | #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ |
| AnnaBridge | 172:65be27845400 | 18992 | #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 18993 | #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ |
| AnnaBridge | 172:65be27845400 | 18994 | #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ |
| AnnaBridge | 172:65be27845400 | 18995 | #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 18996 | #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 18997 | #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ |
| AnnaBridge | 172:65be27845400 | 18998 | #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 18999 | #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19000 | #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ |
| AnnaBridge | 172:65be27845400 | 19001 | #define USB_OTG_GLPMCFG_BESL_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 19002 | #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ |
| AnnaBridge | 172:65be27845400 | 19003 | #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ |
| AnnaBridge | 172:65be27845400 | 19004 | #define USB_OTG_GLPMCFG_LPMACK_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19005 | #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19006 | #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ |
| AnnaBridge | 172:65be27845400 | 19007 | #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19008 | #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19009 | #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ |
| AnnaBridge | 172:65be27845400 | 19010 | |
| AnnaBridge | 172:65be27845400 | 19011 | |
| AnnaBridge | 172:65be27845400 | 19012 | /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ |
| AnnaBridge | 172:65be27845400 | 19013 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19014 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19015 | #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19016 | #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19017 | #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19018 | #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19019 | #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19020 | #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19021 | #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
| AnnaBridge | 172:65be27845400 | 19022 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19023 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19024 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| AnnaBridge | 172:65be27845400 | 19025 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 19026 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 19027 | #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| AnnaBridge | 172:65be27845400 | 19028 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19029 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19030 | #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| AnnaBridge | 172:65be27845400 | 19031 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 19032 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19033 | #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ |
| AnnaBridge | 172:65be27845400 | 19034 | #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 19035 | #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 19036 | #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19037 | #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 19038 | #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 19039 | #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19040 | |
| AnnaBridge | 172:65be27845400 | 19041 | /******************** Bit definition for USB_OTG_HPRT register ********************/ |
| AnnaBridge | 172:65be27845400 | 19042 | #define USB_OTG_HPRT_PCSTS_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19043 | #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19044 | #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ |
| AnnaBridge | 172:65be27845400 | 19045 | #define USB_OTG_HPRT_PCDET_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19046 | #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19047 | #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ |
| AnnaBridge | 172:65be27845400 | 19048 | #define USB_OTG_HPRT_PENA_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 19049 | #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 19050 | #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ |
| AnnaBridge | 172:65be27845400 | 19051 | #define USB_OTG_HPRT_PENCHNG_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19052 | #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19053 | #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ |
| AnnaBridge | 172:65be27845400 | 19054 | #define USB_OTG_HPRT_POCA_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19055 | #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19056 | #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ |
| AnnaBridge | 172:65be27845400 | 19057 | #define USB_OTG_HPRT_POCCHNG_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 19058 | #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 19059 | #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ |
| AnnaBridge | 172:65be27845400 | 19060 | #define USB_OTG_HPRT_PRES_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19061 | #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19062 | #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ |
| AnnaBridge | 172:65be27845400 | 19063 | #define USB_OTG_HPRT_PSUSP_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 19064 | #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 19065 | #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ |
| AnnaBridge | 172:65be27845400 | 19066 | #define USB_OTG_HPRT_PRST_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 19067 | #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19068 | #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ |
| AnnaBridge | 172:65be27845400 | 19069 | |
| AnnaBridge | 172:65be27845400 | 19070 | #define USB_OTG_HPRT_PLSTS_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 19071 | #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ |
| AnnaBridge | 172:65be27845400 | 19072 | #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ |
| AnnaBridge | 172:65be27845400 | 19073 | #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 19074 | #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 19075 | #define USB_OTG_HPRT_PPWR_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 19076 | #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 19077 | #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ |
| AnnaBridge | 172:65be27845400 | 19078 | |
| AnnaBridge | 172:65be27845400 | 19079 | #define USB_OTG_HPRT_PTCTL_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 19080 | #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ |
| AnnaBridge | 172:65be27845400 | 19081 | #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ |
| AnnaBridge | 172:65be27845400 | 19082 | #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 19083 | #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 19084 | #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 19085 | #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 19086 | |
| AnnaBridge | 172:65be27845400 | 19087 | #define USB_OTG_HPRT_PSPD_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 19088 | #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ |
| AnnaBridge | 172:65be27845400 | 19089 | #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ |
| AnnaBridge | 172:65be27845400 | 19090 | #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 19091 | #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 19092 | |
| AnnaBridge | 172:65be27845400 | 19093 | /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ |
| AnnaBridge | 172:65be27845400 | 19094 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19095 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19096 | #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19097 | #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19098 | #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19099 | #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19100 | #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19101 | #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19102 | #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ |
| AnnaBridge | 172:65be27845400 | 19103 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19104 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19105 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| AnnaBridge | 172:65be27845400 | 19106 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 19107 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 19108 | #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| AnnaBridge | 172:65be27845400 | 19109 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19110 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19111 | #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| AnnaBridge | 172:65be27845400 | 19112 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 19113 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19114 | #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ |
| AnnaBridge | 172:65be27845400 | 19115 | #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 19116 | #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 19117 | #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19118 | #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 19119 | #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 19120 | #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19121 | #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 19122 | #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 19123 | #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19124 | #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 19125 | #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 19126 | #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19127 | |
| AnnaBridge | 172:65be27845400 | 19128 | /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ |
| AnnaBridge | 172:65be27845400 | 19129 | #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19130 | #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 19131 | #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ |
| AnnaBridge | 172:65be27845400 | 19132 | #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 19133 | #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 19134 | #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ |
| AnnaBridge | 172:65be27845400 | 19135 | |
| AnnaBridge | 172:65be27845400 | 19136 | /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ |
| AnnaBridge | 172:65be27845400 | 19137 | #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19138 | #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 172:65be27845400 | 19139 | #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ |
| AnnaBridge | 172:65be27845400 | 19140 | #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 19141 | #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 19142 | #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
| AnnaBridge | 172:65be27845400 | 19143 | #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 19144 | #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 19145 | #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ |
| AnnaBridge | 172:65be27845400 | 19146 | #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 19147 | #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 19148 | #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ |
| AnnaBridge | 172:65be27845400 | 19149 | |
| AnnaBridge | 172:65be27845400 | 19150 | #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 19151 | #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 19152 | #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ |
| AnnaBridge | 172:65be27845400 | 19153 | #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 19154 | #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 19155 | #define USB_OTG_DIEPCTL_STALL_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 19156 | #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 19157 | #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ |
| AnnaBridge | 172:65be27845400 | 19158 | |
| AnnaBridge | 172:65be27845400 | 19159 | #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 19160 | #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ |
| AnnaBridge | 172:65be27845400 | 19161 | #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ |
| AnnaBridge | 172:65be27845400 | 19162 | #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 19163 | #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 19164 | #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 19165 | #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 19166 | #define USB_OTG_DIEPCTL_CNAK_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 19167 | #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 19168 | #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ |
| AnnaBridge | 172:65be27845400 | 19169 | #define USB_OTG_DIEPCTL_SNAK_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 19170 | #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 19171 | #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ |
| AnnaBridge | 172:65be27845400 | 19172 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 19173 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 19174 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
| AnnaBridge | 172:65be27845400 | 19175 | #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 19176 | #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 19177 | #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
| AnnaBridge | 172:65be27845400 | 19178 | #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 19179 | #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 19180 | #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
| AnnaBridge | 172:65be27845400 | 19181 | #define USB_OTG_DIEPCTL_EPENA_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 19182 | #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 19183 | #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ |
| AnnaBridge | 172:65be27845400 | 19184 | |
| AnnaBridge | 172:65be27845400 | 19185 | /******************** Bit definition for USB_OTG_HCCHAR register ********************/ |
| AnnaBridge | 172:65be27845400 | 19186 | #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19187 | #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 172:65be27845400 | 19188 | #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ |
| AnnaBridge | 172:65be27845400 | 19189 | |
| AnnaBridge | 172:65be27845400 | 19190 | #define USB_OTG_HCCHAR_EPNUM_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 19191 | #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ |
| AnnaBridge | 172:65be27845400 | 19192 | #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ |
| AnnaBridge | 172:65be27845400 | 19193 | #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 19194 | #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 19195 | #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 19196 | #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 19197 | #define USB_OTG_HCCHAR_EPDIR_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 19198 | #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 19199 | #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ |
| AnnaBridge | 172:65be27845400 | 19200 | #define USB_OTG_HCCHAR_LSDEV_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 19201 | #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 19202 | #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ |
| AnnaBridge | 172:65be27845400 | 19203 | |
| AnnaBridge | 172:65be27845400 | 19204 | #define USB_OTG_HCCHAR_EPTYP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 19205 | #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 19206 | #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ |
| AnnaBridge | 172:65be27845400 | 19207 | #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 19208 | #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 19209 | |
| AnnaBridge | 172:65be27845400 | 19210 | #define USB_OTG_HCCHAR_MC_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 19211 | #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ |
| AnnaBridge | 172:65be27845400 | 19212 | #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ |
| AnnaBridge | 172:65be27845400 | 19213 | #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 19214 | #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 19215 | |
| AnnaBridge | 172:65be27845400 | 19216 | #define USB_OTG_HCCHAR_DAD_Pos (22U) |
| AnnaBridge | 172:65be27845400 | 19217 | #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ |
| AnnaBridge | 172:65be27845400 | 19218 | #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ |
| AnnaBridge | 172:65be27845400 | 19219 | #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ |
| AnnaBridge | 172:65be27845400 | 19220 | #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ |
| AnnaBridge | 172:65be27845400 | 19221 | #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ |
| AnnaBridge | 172:65be27845400 | 19222 | #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ |
| AnnaBridge | 172:65be27845400 | 19223 | #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 19224 | #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 19225 | #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 19226 | #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 19227 | #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 19228 | #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ |
| AnnaBridge | 172:65be27845400 | 19229 | #define USB_OTG_HCCHAR_CHDIS_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 19230 | #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 19231 | #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ |
| AnnaBridge | 172:65be27845400 | 19232 | #define USB_OTG_HCCHAR_CHENA_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 19233 | #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 19234 | #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ |
| AnnaBridge | 172:65be27845400 | 19235 | |
| AnnaBridge | 172:65be27845400 | 19236 | /******************** Bit definition for USB_OTG_HCSPLT register ********************/ |
| AnnaBridge | 172:65be27845400 | 19237 | |
| AnnaBridge | 172:65be27845400 | 19238 | #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19239 | #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ |
| AnnaBridge | 172:65be27845400 | 19240 | #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ |
| AnnaBridge | 172:65be27845400 | 19241 | #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19242 | #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19243 | #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 19244 | #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19245 | #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19246 | #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 19247 | #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19248 | |
| AnnaBridge | 172:65be27845400 | 19249 | #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 19250 | #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ |
| AnnaBridge | 172:65be27845400 | 19251 | #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ |
| AnnaBridge | 172:65be27845400 | 19252 | #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 19253 | #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19254 | #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 19255 | #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 19256 | #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 19257 | #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 19258 | #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 19259 | |
| AnnaBridge | 172:65be27845400 | 19260 | #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 19261 | #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ |
| AnnaBridge | 172:65be27845400 | 19262 | #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ |
| AnnaBridge | 172:65be27845400 | 19263 | #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 19264 | #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 19265 | #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 19266 | #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ |
| AnnaBridge | 172:65be27845400 | 19267 | #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ |
| AnnaBridge | 172:65be27845400 | 19268 | #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 19269 | #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 19270 | #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ |
| AnnaBridge | 172:65be27845400 | 19271 | |
| AnnaBridge | 172:65be27845400 | 19272 | /******************** Bit definition for USB_OTG_HCINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 19273 | #define USB_OTG_HCINT_XFRC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19274 | #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19275 | #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ |
| AnnaBridge | 172:65be27845400 | 19276 | #define USB_OTG_HCINT_CHH_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19277 | #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19278 | #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ |
| AnnaBridge | 172:65be27845400 | 19279 | #define USB_OTG_HCINT_AHBERR_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 19280 | #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 19281 | #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ |
| AnnaBridge | 172:65be27845400 | 19282 | #define USB_OTG_HCINT_STALL_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19283 | #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19284 | #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ |
| AnnaBridge | 172:65be27845400 | 19285 | #define USB_OTG_HCINT_NAK_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19286 | #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19287 | #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ |
| AnnaBridge | 172:65be27845400 | 19288 | #define USB_OTG_HCINT_ACK_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 19289 | #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 19290 | #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ |
| AnnaBridge | 172:65be27845400 | 19291 | #define USB_OTG_HCINT_NYET_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19292 | #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19293 | #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ |
| AnnaBridge | 172:65be27845400 | 19294 | #define USB_OTG_HCINT_TXERR_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 19295 | #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 19296 | #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ |
| AnnaBridge | 172:65be27845400 | 19297 | #define USB_OTG_HCINT_BBERR_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 19298 | #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19299 | #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ |
| AnnaBridge | 172:65be27845400 | 19300 | #define USB_OTG_HCINT_FRMOR_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 19301 | #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 19302 | #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ |
| AnnaBridge | 172:65be27845400 | 19303 | #define USB_OTG_HCINT_DTERR_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 19304 | #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 19305 | #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ |
| AnnaBridge | 172:65be27845400 | 19306 | |
| AnnaBridge | 172:65be27845400 | 19307 | /******************** Bit definition for USB_OTG_DIEPINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 19308 | #define USB_OTG_DIEPINT_XFRC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19309 | #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19310 | #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
| AnnaBridge | 172:65be27845400 | 19311 | #define USB_OTG_DIEPINT_EPDISD_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19312 | #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19313 | #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
| AnnaBridge | 172:65be27845400 | 19314 | #define USB_OTG_DIEPINT_TOC_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19315 | #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19316 | #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ |
| AnnaBridge | 172:65be27845400 | 19317 | #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19318 | #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19319 | #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ |
| AnnaBridge | 172:65be27845400 | 19320 | #define USB_OTG_DIEPINT_INEPNE_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19321 | #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19322 | #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ |
| AnnaBridge | 172:65be27845400 | 19323 | #define USB_OTG_DIEPINT_TXFE_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 19324 | #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 19325 | #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ |
| AnnaBridge | 172:65be27845400 | 19326 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 19327 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19328 | #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ |
| AnnaBridge | 172:65be27845400 | 19329 | #define USB_OTG_DIEPINT_BNA_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 19330 | #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 19331 | #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ |
| AnnaBridge | 172:65be27845400 | 19332 | #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) |
| AnnaBridge | 172:65be27845400 | 19333 | #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ |
| AnnaBridge | 172:65be27845400 | 19334 | #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ |
| AnnaBridge | 172:65be27845400 | 19335 | #define USB_OTG_DIEPINT_BERR_Pos (12U) |
| AnnaBridge | 172:65be27845400 | 19336 | #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ |
| AnnaBridge | 172:65be27845400 | 19337 | #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ |
| AnnaBridge | 172:65be27845400 | 19338 | #define USB_OTG_DIEPINT_NAK_Pos (13U) |
| AnnaBridge | 172:65be27845400 | 19339 | #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ |
| AnnaBridge | 172:65be27845400 | 19340 | #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ |
| AnnaBridge | 172:65be27845400 | 19341 | |
| AnnaBridge | 172:65be27845400 | 19342 | /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ |
| AnnaBridge | 172:65be27845400 | 19343 | #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19344 | #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19345 | #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ |
| AnnaBridge | 172:65be27845400 | 19346 | #define USB_OTG_HCINTMSK_CHHM_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19347 | #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19348 | #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ |
| AnnaBridge | 172:65be27845400 | 19349 | #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) |
| AnnaBridge | 172:65be27845400 | 19350 | #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ |
| AnnaBridge | 172:65be27845400 | 19351 | #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ |
| AnnaBridge | 172:65be27845400 | 19352 | #define USB_OTG_HCINTMSK_STALLM_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19353 | #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19354 | #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19355 | #define USB_OTG_HCINTMSK_NAKM_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19356 | #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19357 | #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19358 | #define USB_OTG_HCINTMSK_ACKM_Pos (5U) |
| AnnaBridge | 172:65be27845400 | 19359 | #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ |
| AnnaBridge | 172:65be27845400 | 19360 | #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19361 | #define USB_OTG_HCINTMSK_NYET_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19362 | #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19363 | #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ |
| AnnaBridge | 172:65be27845400 | 19364 | #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) |
| AnnaBridge | 172:65be27845400 | 19365 | #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ |
| AnnaBridge | 172:65be27845400 | 19366 | #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ |
| AnnaBridge | 172:65be27845400 | 19367 | #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) |
| AnnaBridge | 172:65be27845400 | 19368 | #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ |
| AnnaBridge | 172:65be27845400 | 19369 | #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ |
| AnnaBridge | 172:65be27845400 | 19370 | #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) |
| AnnaBridge | 172:65be27845400 | 19371 | #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ |
| AnnaBridge | 172:65be27845400 | 19372 | #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ |
| AnnaBridge | 172:65be27845400 | 19373 | #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) |
| AnnaBridge | 172:65be27845400 | 19374 | #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ |
| AnnaBridge | 172:65be27845400 | 19375 | #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ |
| AnnaBridge | 172:65be27845400 | 19376 | |
| AnnaBridge | 172:65be27845400 | 19377 | /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ |
| AnnaBridge | 172:65be27845400 | 19378 | |
| AnnaBridge | 172:65be27845400 | 19379 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19380 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 172:65be27845400 | 19381 | #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| AnnaBridge | 172:65be27845400 | 19382 | #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 19383 | #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| AnnaBridge | 172:65be27845400 | 19384 | #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
| AnnaBridge | 172:65be27845400 | 19385 | #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 19386 | #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ |
| AnnaBridge | 172:65be27845400 | 19387 | #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ |
| AnnaBridge | 172:65be27845400 | 19388 | /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ |
| AnnaBridge | 172:65be27845400 | 19389 | #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19390 | #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 172:65be27845400 | 19391 | #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| AnnaBridge | 172:65be27845400 | 19392 | #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 19393 | #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| AnnaBridge | 172:65be27845400 | 19394 | #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ |
| AnnaBridge | 172:65be27845400 | 19395 | #define USB_OTG_HCTSIZ_DOPING_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 19396 | #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 19397 | #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ |
| AnnaBridge | 172:65be27845400 | 19398 | #define USB_OTG_HCTSIZ_DPID_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 19399 | #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ |
| AnnaBridge | 172:65be27845400 | 19400 | #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ |
| AnnaBridge | 172:65be27845400 | 19401 | #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 19402 | #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 19403 | |
| AnnaBridge | 172:65be27845400 | 19404 | /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ |
| AnnaBridge | 172:65be27845400 | 19405 | #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19406 | #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 19407 | #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ |
| AnnaBridge | 172:65be27845400 | 19408 | |
| AnnaBridge | 172:65be27845400 | 19409 | /******************** Bit definition for USB_OTG_HCDMA register ********************/ |
| AnnaBridge | 172:65be27845400 | 19410 | #define USB_OTG_HCDMA_DMAADDR_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19411 | #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
| AnnaBridge | 172:65be27845400 | 19412 | #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ |
| AnnaBridge | 172:65be27845400 | 19413 | |
| AnnaBridge | 172:65be27845400 | 19414 | /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ |
| AnnaBridge | 172:65be27845400 | 19415 | #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19416 | #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 19417 | #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */ |
| AnnaBridge | 172:65be27845400 | 19418 | |
| AnnaBridge | 172:65be27845400 | 19419 | /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ |
| AnnaBridge | 172:65be27845400 | 19420 | #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19421 | #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ |
| AnnaBridge | 172:65be27845400 | 19422 | #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ |
| AnnaBridge | 172:65be27845400 | 19423 | #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) |
| AnnaBridge | 172:65be27845400 | 19424 | #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ |
| AnnaBridge | 172:65be27845400 | 19425 | #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ |
| AnnaBridge | 172:65be27845400 | 19426 | |
| AnnaBridge | 172:65be27845400 | 19427 | /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ |
| AnnaBridge | 172:65be27845400 | 19428 | |
| AnnaBridge | 172:65be27845400 | 19429 | #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19430 | #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
| AnnaBridge | 172:65be27845400 | 19431 | #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ |
| AnnaBridge | 172:65be27845400 | 19432 | #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) |
| AnnaBridge | 172:65be27845400 | 19433 | #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
| AnnaBridge | 172:65be27845400 | 19434 | #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
| AnnaBridge | 172:65be27845400 | 19435 | #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) |
| AnnaBridge | 172:65be27845400 | 19436 | #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
| AnnaBridge | 172:65be27845400 | 19437 | #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ |
| AnnaBridge | 172:65be27845400 | 19438 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| AnnaBridge | 172:65be27845400 | 19439 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
| AnnaBridge | 172:65be27845400 | 19440 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
| AnnaBridge | 172:65be27845400 | 19441 | #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 19442 | #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 19443 | #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
| AnnaBridge | 172:65be27845400 | 19444 | #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) |
| AnnaBridge | 172:65be27845400 | 19445 | #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
| AnnaBridge | 172:65be27845400 | 19446 | #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ |
| AnnaBridge | 172:65be27845400 | 19447 | #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
| AnnaBridge | 172:65be27845400 | 19448 | #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
| AnnaBridge | 172:65be27845400 | 19449 | #define USB_OTG_DOEPCTL_SNPM_Pos (20U) |
| AnnaBridge | 172:65be27845400 | 19450 | #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ |
| AnnaBridge | 172:65be27845400 | 19451 | #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ |
| AnnaBridge | 172:65be27845400 | 19452 | #define USB_OTG_DOEPCTL_STALL_Pos (21U) |
| AnnaBridge | 172:65be27845400 | 19453 | #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ |
| AnnaBridge | 172:65be27845400 | 19454 | #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ |
| AnnaBridge | 172:65be27845400 | 19455 | #define USB_OTG_DOEPCTL_CNAK_Pos (26U) |
| AnnaBridge | 172:65be27845400 | 19456 | #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
| AnnaBridge | 172:65be27845400 | 19457 | #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ |
| AnnaBridge | 172:65be27845400 | 19458 | #define USB_OTG_DOEPCTL_SNAK_Pos (27U) |
| AnnaBridge | 172:65be27845400 | 19459 | #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
| AnnaBridge | 172:65be27845400 | 19460 | #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ |
| AnnaBridge | 172:65be27845400 | 19461 | #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) |
| AnnaBridge | 172:65be27845400 | 19462 | #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 19463 | #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
| AnnaBridge | 172:65be27845400 | 19464 | #define USB_OTG_DOEPCTL_EPENA_Pos (31U) |
| AnnaBridge | 172:65be27845400 | 19465 | #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
| AnnaBridge | 172:65be27845400 | 19466 | #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ |
| AnnaBridge | 172:65be27845400 | 19467 | |
| AnnaBridge | 172:65be27845400 | 19468 | /******************** Bit definition for USB_OTG_DOEPINT register ********************/ |
| AnnaBridge | 172:65be27845400 | 19469 | #define USB_OTG_DOEPINT_XFRC_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19470 | #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19471 | #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
| AnnaBridge | 172:65be27845400 | 19472 | #define USB_OTG_DOEPINT_EPDISD_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19473 | #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19474 | #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
| AnnaBridge | 172:65be27845400 | 19475 | #define USB_OTG_DOEPINT_STUP_Pos (3U) |
| AnnaBridge | 172:65be27845400 | 19476 | #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ |
| AnnaBridge | 172:65be27845400 | 19477 | #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ |
| AnnaBridge | 172:65be27845400 | 19478 | #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19479 | #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19480 | #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ |
| AnnaBridge | 172:65be27845400 | 19481 | #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) |
| AnnaBridge | 172:65be27845400 | 19482 | #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ |
| AnnaBridge | 172:65be27845400 | 19483 | #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ |
| AnnaBridge | 172:65be27845400 | 19484 | #define USB_OTG_DOEPINT_NYET_Pos (14U) |
| AnnaBridge | 172:65be27845400 | 19485 | #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ |
| AnnaBridge | 172:65be27845400 | 19486 | #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ |
| AnnaBridge | 172:65be27845400 | 19487 | |
| AnnaBridge | 172:65be27845400 | 19488 | /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ |
| AnnaBridge | 172:65be27845400 | 19489 | |
| AnnaBridge | 172:65be27845400 | 19490 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19491 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| AnnaBridge | 172:65be27845400 | 19492 | #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| AnnaBridge | 172:65be27845400 | 19493 | #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) |
| AnnaBridge | 172:65be27845400 | 19494 | #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| AnnaBridge | 172:65be27845400 | 19495 | #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
| AnnaBridge | 172:65be27845400 | 19496 | |
| AnnaBridge | 172:65be27845400 | 19497 | #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) |
| AnnaBridge | 172:65be27845400 | 19498 | #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ |
| AnnaBridge | 172:65be27845400 | 19499 | #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ |
| AnnaBridge | 172:65be27845400 | 19500 | #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ |
| AnnaBridge | 172:65be27845400 | 19501 | #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ |
| AnnaBridge | 172:65be27845400 | 19502 | |
| AnnaBridge | 172:65be27845400 | 19503 | /******************** Bit definition for PCGCCTL register ********************/ |
| AnnaBridge | 172:65be27845400 | 19504 | #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) |
| AnnaBridge | 172:65be27845400 | 19505 | #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ |
| AnnaBridge | 172:65be27845400 | 19506 | #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ |
| AnnaBridge | 172:65be27845400 | 19507 | #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) |
| AnnaBridge | 172:65be27845400 | 19508 | #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ |
| AnnaBridge | 172:65be27845400 | 19509 | #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ |
| AnnaBridge | 172:65be27845400 | 19510 | #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) |
| AnnaBridge | 172:65be27845400 | 19511 | #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ |
| AnnaBridge | 172:65be27845400 | 19512 | #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ |
| AnnaBridge | 172:65be27845400 | 19513 | |
| AnnaBridge | 172:65be27845400 | 19514 | |
| AnnaBridge | 172:65be27845400 | 19515 | /** |
| AnnaBridge | 172:65be27845400 | 19516 | * @} |
| AnnaBridge | 172:65be27845400 | 19517 | */ |
| AnnaBridge | 172:65be27845400 | 19518 | |
| AnnaBridge | 172:65be27845400 | 19519 | /** |
| AnnaBridge | 172:65be27845400 | 19520 | * @} |
| AnnaBridge | 172:65be27845400 | 19521 | */ |
| AnnaBridge | 172:65be27845400 | 19522 | |
| AnnaBridge | 172:65be27845400 | 19523 | /** @addtogroup Exported_macros |
| AnnaBridge | 172:65be27845400 | 19524 | * @{ |
| AnnaBridge | 172:65be27845400 | 19525 | */ |
| AnnaBridge | 172:65be27845400 | 19526 | |
| AnnaBridge | 172:65be27845400 | 19527 | /******************************* ADC Instances ********************************/ |
| AnnaBridge | 172:65be27845400 | 19528 | #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| AnnaBridge | 172:65be27845400 | 19529 | |
| AnnaBridge | 172:65be27845400 | 19530 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) |
| AnnaBridge | 172:65be27845400 | 19531 | |
| AnnaBridge | 172:65be27845400 | 19532 | /******************************** CAN Instances ******************************/ |
| AnnaBridge | 172:65be27845400 | 19533 | #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) |
| AnnaBridge | 172:65be27845400 | 19534 | |
| AnnaBridge | 172:65be27845400 | 19535 | /******************************** COMP Instances ******************************/ |
| AnnaBridge | 172:65be27845400 | 19536 | #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ |
| AnnaBridge | 172:65be27845400 | 19537 | ((INSTANCE) == COMP2)) |
| AnnaBridge | 172:65be27845400 | 19538 | |
| AnnaBridge | 172:65be27845400 | 19539 | #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) |
| AnnaBridge | 172:65be27845400 | 19540 | |
| AnnaBridge | 172:65be27845400 | 19541 | /******************** COMP Instances with window mode capability **************/ |
| AnnaBridge | 172:65be27845400 | 19542 | #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| AnnaBridge | 172:65be27845400 | 19543 | |
| AnnaBridge | 172:65be27845400 | 19544 | /******************************* CRC Instances ********************************/ |
| AnnaBridge | 172:65be27845400 | 19545 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| AnnaBridge | 172:65be27845400 | 19546 | |
| AnnaBridge | 172:65be27845400 | 19547 | /******************************* DAC Instances ********************************/ |
| AnnaBridge | 172:65be27845400 | 19548 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| AnnaBridge | 172:65be27845400 | 19549 | |
| AnnaBridge | 172:65be27845400 | 19550 | /****************************** DFSDM Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19551 | #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ |
| AnnaBridge | 172:65be27845400 | 19552 | ((INSTANCE) == DFSDM1_Filter1) || \ |
| AnnaBridge | 172:65be27845400 | 19553 | ((INSTANCE) == DFSDM1_Filter2) || \ |
| AnnaBridge | 172:65be27845400 | 19554 | ((INSTANCE) == DFSDM1_Filter3)) |
| AnnaBridge | 172:65be27845400 | 19555 | |
| AnnaBridge | 172:65be27845400 | 19556 | #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \ |
| AnnaBridge | 172:65be27845400 | 19557 | ((INSTANCE) == DFSDM1_Channel1) || \ |
| AnnaBridge | 172:65be27845400 | 19558 | ((INSTANCE) == DFSDM1_Channel2) || \ |
| AnnaBridge | 172:65be27845400 | 19559 | ((INSTANCE) == DFSDM1_Channel3) || \ |
| AnnaBridge | 172:65be27845400 | 19560 | ((INSTANCE) == DFSDM1_Channel4) || \ |
| AnnaBridge | 172:65be27845400 | 19561 | ((INSTANCE) == DFSDM1_Channel5) || \ |
| AnnaBridge | 172:65be27845400 | 19562 | ((INSTANCE) == DFSDM1_Channel6) || \ |
| AnnaBridge | 172:65be27845400 | 19563 | ((INSTANCE) == DFSDM1_Channel7)) |
| AnnaBridge | 172:65be27845400 | 19564 | |
| AnnaBridge | 172:65be27845400 | 19565 | /******************************* DCMI Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19566 | #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI) |
| AnnaBridge | 172:65be27845400 | 19567 | |
| AnnaBridge | 172:65be27845400 | 19568 | /******************************* DMA2D Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19569 | #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D) |
| AnnaBridge | 172:65be27845400 | 19570 | |
| AnnaBridge | 172:65be27845400 | 19571 | /******************************** DMA Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19572 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| AnnaBridge | 172:65be27845400 | 19573 | ((INSTANCE) == DMA1_Channel2) || \ |
| AnnaBridge | 172:65be27845400 | 19574 | ((INSTANCE) == DMA1_Channel3) || \ |
| AnnaBridge | 172:65be27845400 | 19575 | ((INSTANCE) == DMA1_Channel4) || \ |
| AnnaBridge | 172:65be27845400 | 19576 | ((INSTANCE) == DMA1_Channel5) || \ |
| AnnaBridge | 172:65be27845400 | 19577 | ((INSTANCE) == DMA1_Channel6) || \ |
| AnnaBridge | 172:65be27845400 | 19578 | ((INSTANCE) == DMA1_Channel7) || \ |
| AnnaBridge | 172:65be27845400 | 19579 | ((INSTANCE) == DMA2_Channel1) || \ |
| AnnaBridge | 172:65be27845400 | 19580 | ((INSTANCE) == DMA2_Channel2) || \ |
| AnnaBridge | 172:65be27845400 | 19581 | ((INSTANCE) == DMA2_Channel3) || \ |
| AnnaBridge | 172:65be27845400 | 19582 | ((INSTANCE) == DMA2_Channel4) || \ |
| AnnaBridge | 172:65be27845400 | 19583 | ((INSTANCE) == DMA2_Channel5) || \ |
| AnnaBridge | 172:65be27845400 | 19584 | ((INSTANCE) == DMA2_Channel6) || \ |
| AnnaBridge | 172:65be27845400 | 19585 | ((INSTANCE) == DMA2_Channel7)) |
| AnnaBridge | 172:65be27845400 | 19586 | |
| AnnaBridge | 172:65be27845400 | 19587 | /******************************* GPIO Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19588 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| AnnaBridge | 172:65be27845400 | 19589 | ((INSTANCE) == GPIOB) || \ |
| AnnaBridge | 172:65be27845400 | 19590 | ((INSTANCE) == GPIOC) || \ |
| AnnaBridge | 172:65be27845400 | 19591 | ((INSTANCE) == GPIOD) || \ |
| AnnaBridge | 172:65be27845400 | 19592 | ((INSTANCE) == GPIOE) || \ |
| AnnaBridge | 172:65be27845400 | 19593 | ((INSTANCE) == GPIOF) || \ |
| AnnaBridge | 172:65be27845400 | 19594 | ((INSTANCE) == GPIOG) || \ |
| AnnaBridge | 172:65be27845400 | 19595 | ((INSTANCE) == GPIOH) || \ |
| AnnaBridge | 172:65be27845400 | 19596 | ((INSTANCE) == GPIOI)) |
| AnnaBridge | 172:65be27845400 | 19597 | |
| AnnaBridge | 172:65be27845400 | 19598 | /******************************* GPIO AF Instances ****************************/ |
| AnnaBridge | 172:65be27845400 | 19599 | /* On L4, all GPIO Bank support AF */ |
| AnnaBridge | 172:65be27845400 | 19600 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| AnnaBridge | 172:65be27845400 | 19601 | |
| AnnaBridge | 172:65be27845400 | 19602 | /**************************** GPIO Lock Instances *****************************/ |
| AnnaBridge | 172:65be27845400 | 19603 | /* On L4, all GPIO Bank support the Lock mechanism */ |
| AnnaBridge | 172:65be27845400 | 19604 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| AnnaBridge | 172:65be27845400 | 19605 | |
| AnnaBridge | 172:65be27845400 | 19606 | /******************************** I2C Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19607 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| AnnaBridge | 172:65be27845400 | 19608 | ((INSTANCE) == I2C2) || \ |
| AnnaBridge | 172:65be27845400 | 19609 | ((INSTANCE) == I2C3) || \ |
| AnnaBridge | 172:65be27845400 | 19610 | ((INSTANCE) == I2C4)) |
| AnnaBridge | 172:65be27845400 | 19611 | |
| AnnaBridge | 172:65be27845400 | 19612 | /****************** I2C Instances : wakeup capability from stop modes *********/ |
| AnnaBridge | 172:65be27845400 | 19613 | #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| AnnaBridge | 172:65be27845400 | 19614 | |
| AnnaBridge | 172:65be27845400 | 19615 | /******************************* HCD Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19616 | #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
| AnnaBridge | 172:65be27845400 | 19617 | |
| AnnaBridge | 172:65be27845400 | 19618 | /****************************** OPAMP Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19619 | #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ |
| AnnaBridge | 172:65be27845400 | 19620 | ((INSTANCE) == OPAMP2)) |
| AnnaBridge | 172:65be27845400 | 19621 | |
| AnnaBridge | 172:65be27845400 | 19622 | #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| AnnaBridge | 172:65be27845400 | 19623 | |
| AnnaBridge | 172:65be27845400 | 19624 | /******************************* OSPI Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19625 | #define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1) || \ |
| AnnaBridge | 172:65be27845400 | 19626 | ((INSTANCE) == OCTOSPI2)) |
| AnnaBridge | 172:65be27845400 | 19627 | |
| AnnaBridge | 172:65be27845400 | 19628 | /******************************* PCD Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19629 | #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
| AnnaBridge | 172:65be27845400 | 19630 | |
| AnnaBridge | 172:65be27845400 | 19631 | /******************************* RNG Instances ********************************/ |
| AnnaBridge | 172:65be27845400 | 19632 | #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| AnnaBridge | 172:65be27845400 | 19633 | |
| AnnaBridge | 172:65be27845400 | 19634 | /****************************** RTC Instances *********************************/ |
| AnnaBridge | 172:65be27845400 | 19635 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| AnnaBridge | 172:65be27845400 | 19636 | |
| AnnaBridge | 172:65be27845400 | 19637 | /******************************** SAI Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19638 | #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \ |
| AnnaBridge | 172:65be27845400 | 19639 | ((INSTANCE) == SAI1_Block_B) || \ |
| AnnaBridge | 172:65be27845400 | 19640 | ((INSTANCE) == SAI2_Block_A) || \ |
| AnnaBridge | 172:65be27845400 | 19641 | ((INSTANCE) == SAI2_Block_B)) |
| AnnaBridge | 172:65be27845400 | 19642 | |
| AnnaBridge | 172:65be27845400 | 19643 | /****************************** SDMMC Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19644 | #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1) |
| AnnaBridge | 172:65be27845400 | 19645 | |
| AnnaBridge | 172:65be27845400 | 19646 | /****************************** SMBUS Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19647 | #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| AnnaBridge | 172:65be27845400 | 19648 | ((INSTANCE) == I2C2) || \ |
| AnnaBridge | 172:65be27845400 | 19649 | ((INSTANCE) == I2C3) || \ |
| AnnaBridge | 172:65be27845400 | 19650 | ((INSTANCE) == I2C4)) |
| AnnaBridge | 172:65be27845400 | 19651 | |
| AnnaBridge | 172:65be27845400 | 19652 | /******************************** SPI Instances *******************************/ |
| AnnaBridge | 172:65be27845400 | 19653 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| AnnaBridge | 172:65be27845400 | 19654 | ((INSTANCE) == SPI2) || \ |
| AnnaBridge | 172:65be27845400 | 19655 | ((INSTANCE) == SPI3)) |
| AnnaBridge | 172:65be27845400 | 19656 | |
| AnnaBridge | 172:65be27845400 | 19657 | /****************** LPTIM Instances : All supported instances *****************/ |
| AnnaBridge | 172:65be27845400 | 19658 | #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19659 | ((INSTANCE) == LPTIM2)) |
| AnnaBridge | 172:65be27845400 | 19660 | |
| AnnaBridge | 172:65be27845400 | 19661 | /****************** TIM Instances : All supported instances *******************/ |
| AnnaBridge | 172:65be27845400 | 19662 | #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19663 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19664 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19665 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19666 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19667 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 172:65be27845400 | 19668 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 172:65be27845400 | 19669 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19670 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19671 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19672 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19673 | |
| AnnaBridge | 172:65be27845400 | 19674 | /****************** TIM Instances : supporting 32 bits counter ****************/ |
| AnnaBridge | 172:65be27845400 | 19675 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19676 | ((INSTANCE) == TIM5)) |
| AnnaBridge | 172:65be27845400 | 19677 | |
| AnnaBridge | 172:65be27845400 | 19678 | /****************** TIM Instances : supporting the break function *************/ |
| AnnaBridge | 172:65be27845400 | 19679 | #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19680 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19681 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19682 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19683 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19684 | |
| AnnaBridge | 172:65be27845400 | 19685 | /************** TIM Instances : supporting Break source selection *************/ |
| AnnaBridge | 172:65be27845400 | 19686 | #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19687 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19688 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19689 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19690 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19691 | |
| AnnaBridge | 172:65be27845400 | 19692 | /****************** TIM Instances : supporting 2 break inputs *****************/ |
| AnnaBridge | 172:65be27845400 | 19693 | #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19694 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19695 | |
| AnnaBridge | 172:65be27845400 | 19696 | /************* TIM Instances : at least 1 capture/compare channel *************/ |
| AnnaBridge | 172:65be27845400 | 19697 | #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19698 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19699 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19700 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19701 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19702 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19703 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19704 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19705 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19706 | |
| AnnaBridge | 172:65be27845400 | 19707 | /************ TIM Instances : at least 2 capture/compare channels *************/ |
| AnnaBridge | 172:65be27845400 | 19708 | #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19709 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19710 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19711 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19712 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19713 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19714 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 19715 | |
| AnnaBridge | 172:65be27845400 | 19716 | /************ TIM Instances : at least 3 capture/compare channels *************/ |
| AnnaBridge | 172:65be27845400 | 19717 | #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19718 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19719 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19720 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19721 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19722 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19723 | |
| AnnaBridge | 172:65be27845400 | 19724 | /************ TIM Instances : at least 4 capture/compare channels *************/ |
| AnnaBridge | 172:65be27845400 | 19725 | #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19726 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19727 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19728 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19729 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19730 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19731 | |
| AnnaBridge | 172:65be27845400 | 19732 | /****************** TIM Instances : at least 5 capture/compare channels *******/ |
| AnnaBridge | 172:65be27845400 | 19733 | #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19734 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19735 | |
| AnnaBridge | 172:65be27845400 | 19736 | /****************** TIM Instances : at least 6 capture/compare channels *******/ |
| AnnaBridge | 172:65be27845400 | 19737 | #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19738 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19739 | |
| AnnaBridge | 172:65be27845400 | 19740 | /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ |
| AnnaBridge | 172:65be27845400 | 19741 | #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19742 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19743 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19744 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19745 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19746 | |
| AnnaBridge | 172:65be27845400 | 19747 | /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ |
| AnnaBridge | 172:65be27845400 | 19748 | #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19749 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19750 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19751 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19752 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19753 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 172:65be27845400 | 19754 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 172:65be27845400 | 19755 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19756 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19757 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19758 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19759 | |
| AnnaBridge | 172:65be27845400 | 19760 | /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ |
| AnnaBridge | 172:65be27845400 | 19761 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19762 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19763 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19764 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19765 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19766 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19767 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19768 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19769 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19770 | |
| AnnaBridge | 172:65be27845400 | 19771 | /******************** TIM Instances : DMA burst feature ***********************/ |
| AnnaBridge | 172:65be27845400 | 19772 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19773 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19774 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19775 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19776 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19777 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19778 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19779 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19780 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19781 | |
| AnnaBridge | 172:65be27845400 | 19782 | /******************* TIM Instances : output(s) available **********************/ |
| AnnaBridge | 172:65be27845400 | 19783 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
| AnnaBridge | 172:65be27845400 | 19784 | ((((INSTANCE) == TIM1) && \ |
| AnnaBridge | 172:65be27845400 | 19785 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19786 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19787 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 19788 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| AnnaBridge | 172:65be27845400 | 19789 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| AnnaBridge | 172:65be27845400 | 19790 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
| AnnaBridge | 172:65be27845400 | 19791 | || \ |
| AnnaBridge | 172:65be27845400 | 19792 | (((INSTANCE) == TIM2) && \ |
| AnnaBridge | 172:65be27845400 | 19793 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19794 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19795 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 19796 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 172:65be27845400 | 19797 | || \ |
| AnnaBridge | 172:65be27845400 | 19798 | (((INSTANCE) == TIM3) && \ |
| AnnaBridge | 172:65be27845400 | 19799 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19800 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19801 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 19802 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 172:65be27845400 | 19803 | || \ |
| AnnaBridge | 172:65be27845400 | 19804 | (((INSTANCE) == TIM4) && \ |
| AnnaBridge | 172:65be27845400 | 19805 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19806 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19807 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 19808 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 172:65be27845400 | 19809 | || \ |
| AnnaBridge | 172:65be27845400 | 19810 | (((INSTANCE) == TIM5) && \ |
| AnnaBridge | 172:65be27845400 | 19811 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19812 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19813 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 19814 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| AnnaBridge | 172:65be27845400 | 19815 | || \ |
| AnnaBridge | 172:65be27845400 | 19816 | (((INSTANCE) == TIM8) && \ |
| AnnaBridge | 172:65be27845400 | 19817 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19818 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19819 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 172:65be27845400 | 19820 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| AnnaBridge | 172:65be27845400 | 19821 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| AnnaBridge | 172:65be27845400 | 19822 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
| AnnaBridge | 172:65be27845400 | 19823 | || \ |
| AnnaBridge | 172:65be27845400 | 19824 | (((INSTANCE) == TIM15) && \ |
| AnnaBridge | 172:65be27845400 | 19825 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19826 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| AnnaBridge | 172:65be27845400 | 19827 | || \ |
| AnnaBridge | 172:65be27845400 | 19828 | (((INSTANCE) == TIM16) && \ |
| AnnaBridge | 172:65be27845400 | 19829 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| AnnaBridge | 172:65be27845400 | 19830 | || \ |
| AnnaBridge | 172:65be27845400 | 19831 | (((INSTANCE) == TIM17) && \ |
| AnnaBridge | 172:65be27845400 | 19832 | (((CHANNEL) == TIM_CHANNEL_1)))) |
| AnnaBridge | 172:65be27845400 | 19833 | |
| AnnaBridge | 172:65be27845400 | 19834 | /****************** TIM Instances : supporting complementary output(s) ********/ |
| AnnaBridge | 172:65be27845400 | 19835 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
| AnnaBridge | 172:65be27845400 | 19836 | ((((INSTANCE) == TIM1) && \ |
| AnnaBridge | 172:65be27845400 | 19837 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19838 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19839 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| AnnaBridge | 172:65be27845400 | 19840 | || \ |
| AnnaBridge | 172:65be27845400 | 19841 | (((INSTANCE) == TIM8) && \ |
| AnnaBridge | 172:65be27845400 | 19842 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 19843 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 172:65be27845400 | 19844 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| AnnaBridge | 172:65be27845400 | 19845 | || \ |
| AnnaBridge | 172:65be27845400 | 19846 | (((INSTANCE) == TIM15) && \ |
| AnnaBridge | 172:65be27845400 | 19847 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
| AnnaBridge | 172:65be27845400 | 19848 | || \ |
| AnnaBridge | 172:65be27845400 | 19849 | (((INSTANCE) == TIM16) && \ |
| AnnaBridge | 172:65be27845400 | 19850 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
| AnnaBridge | 172:65be27845400 | 19851 | || \ |
| AnnaBridge | 172:65be27845400 | 19852 | (((INSTANCE) == TIM17) && \ |
| AnnaBridge | 172:65be27845400 | 19853 | ((CHANNEL) == TIM_CHANNEL_1))) |
| AnnaBridge | 172:65be27845400 | 19854 | |
| AnnaBridge | 172:65be27845400 | 19855 | /****************** TIM Instances : supporting clock division *****************/ |
| AnnaBridge | 172:65be27845400 | 19856 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19857 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19858 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19859 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19860 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19861 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19862 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19863 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19864 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19865 | |
| AnnaBridge | 172:65be27845400 | 19866 | /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ |
| AnnaBridge | 172:65be27845400 | 19867 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19868 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19869 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19870 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19871 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19872 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19873 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 19874 | |
| AnnaBridge | 172:65be27845400 | 19875 | /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ |
| AnnaBridge | 172:65be27845400 | 19876 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19877 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19878 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19879 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19880 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19881 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19882 | |
| AnnaBridge | 172:65be27845400 | 19883 | /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ |
| AnnaBridge | 172:65be27845400 | 19884 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19885 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19886 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19887 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19888 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19889 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19890 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 19891 | |
| AnnaBridge | 172:65be27845400 | 19892 | /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ |
| AnnaBridge | 172:65be27845400 | 19893 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19894 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19895 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19896 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19897 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19898 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19899 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 19900 | |
| AnnaBridge | 172:65be27845400 | 19901 | /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ |
| AnnaBridge | 172:65be27845400 | 19902 | #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19903 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19904 | |
| AnnaBridge | 172:65be27845400 | 19905 | /****************** TIM Instances : supporting commutation event generation ***/ |
| AnnaBridge | 172:65be27845400 | 19906 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19907 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19908 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19909 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19910 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19911 | |
| AnnaBridge | 172:65be27845400 | 19912 | /****************** TIM Instances : supporting counting mode selection ********/ |
| AnnaBridge | 172:65be27845400 | 19913 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19914 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19915 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19916 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19917 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19918 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19919 | |
| AnnaBridge | 172:65be27845400 | 19920 | /****************** TIM Instances : supporting encoder interface **************/ |
| AnnaBridge | 172:65be27845400 | 19921 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19922 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19923 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19924 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19925 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19926 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19927 | |
| AnnaBridge | 172:65be27845400 | 19928 | /****************** TIM Instances : supporting Hall sensor interface **********/ |
| AnnaBridge | 172:65be27845400 | 19929 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19930 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19931 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19932 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19933 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19934 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19935 | |
| AnnaBridge | 172:65be27845400 | 19936 | /**************** TIM Instances : external trigger input available ************/ |
| AnnaBridge | 172:65be27845400 | 19937 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19938 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19939 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19940 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19941 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19942 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19943 | |
| AnnaBridge | 172:65be27845400 | 19944 | /************* TIM Instances : supporting ETR source selection ***************/ |
| AnnaBridge | 172:65be27845400 | 19945 | #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19946 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19947 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19948 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19949 | |
| AnnaBridge | 172:65be27845400 | 19950 | /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ |
| AnnaBridge | 172:65be27845400 | 19951 | #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19952 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19953 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19954 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19955 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19956 | ((INSTANCE) == TIM6) || \ |
| AnnaBridge | 172:65be27845400 | 19957 | ((INSTANCE) == TIM7) || \ |
| AnnaBridge | 172:65be27845400 | 19958 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19959 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 19960 | |
| AnnaBridge | 172:65be27845400 | 19961 | /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ |
| AnnaBridge | 172:65be27845400 | 19962 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19963 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19964 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19965 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19966 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19967 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19968 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 19969 | |
| AnnaBridge | 172:65be27845400 | 19970 | /****************** TIM Instances : supporting OCxREF clear *******************/ |
| AnnaBridge | 172:65be27845400 | 19971 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19972 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19973 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19974 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 19975 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 19976 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 19977 | |
| AnnaBridge | 172:65be27845400 | 19978 | /****************** TIM Instances : remapping capability **********************/ |
| AnnaBridge | 172:65be27845400 | 19979 | #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19980 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 19981 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 19982 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19983 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19984 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19985 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19986 | |
| AnnaBridge | 172:65be27845400 | 19987 | /****************** TIM Instances : supporting repetition counter *************/ |
| AnnaBridge | 172:65be27845400 | 19988 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19989 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 19990 | ((INSTANCE) == TIM15) || \ |
| AnnaBridge | 172:65be27845400 | 19991 | ((INSTANCE) == TIM16) || \ |
| AnnaBridge | 172:65be27845400 | 19992 | ((INSTANCE) == TIM17)) |
| AnnaBridge | 172:65be27845400 | 19993 | |
| AnnaBridge | 172:65be27845400 | 19994 | /****************** TIM Instances : supporting synchronization ****************/ |
| AnnaBridge | 172:65be27845400 | 19995 | #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) |
| AnnaBridge | 172:65be27845400 | 19996 | |
| AnnaBridge | 172:65be27845400 | 19997 | /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ |
| AnnaBridge | 172:65be27845400 | 19998 | #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 19999 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 20000 | |
| AnnaBridge | 172:65be27845400 | 20001 | /******************* TIM Instances : Timer input XOR function *****************/ |
| AnnaBridge | 172:65be27845400 | 20002 | #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 20003 | ((INSTANCE) == TIM2) || \ |
| AnnaBridge | 172:65be27845400 | 20004 | ((INSTANCE) == TIM3) || \ |
| AnnaBridge | 172:65be27845400 | 20005 | ((INSTANCE) == TIM4) || \ |
| AnnaBridge | 172:65be27845400 | 20006 | ((INSTANCE) == TIM5) || \ |
| AnnaBridge | 172:65be27845400 | 20007 | ((INSTANCE) == TIM8) || \ |
| AnnaBridge | 172:65be27845400 | 20008 | ((INSTANCE) == TIM15)) |
| AnnaBridge | 172:65be27845400 | 20009 | |
| AnnaBridge | 172:65be27845400 | 20010 | /****************** TIM Instances : Advanced timer instances *******************/ |
| AnnaBridge | 172:65be27845400 | 20011 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| AnnaBridge | 172:65be27845400 | 20012 | ((INSTANCE) == TIM8)) |
| AnnaBridge | 172:65be27845400 | 20013 | |
| AnnaBridge | 172:65be27845400 | 20014 | /****************************** TSC Instances *********************************/ |
| AnnaBridge | 172:65be27845400 | 20015 | #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) |
| AnnaBridge | 172:65be27845400 | 20016 | |
| AnnaBridge | 172:65be27845400 | 20017 | /******************** USART Instances : Synchronous mode **********************/ |
| AnnaBridge | 172:65be27845400 | 20018 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20019 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20020 | ((INSTANCE) == USART3)) |
| AnnaBridge | 172:65be27845400 | 20021 | |
| AnnaBridge | 172:65be27845400 | 20022 | /******************** UART Instances : Asynchronous mode **********************/ |
| AnnaBridge | 172:65be27845400 | 20023 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20024 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20025 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20026 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20027 | ((INSTANCE) == UART5)) |
| AnnaBridge | 172:65be27845400 | 20028 | |
| AnnaBridge | 172:65be27845400 | 20029 | /*********************** UART Instances : FIFO mode ***************************/ |
| AnnaBridge | 172:65be27845400 | 20030 | #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20031 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20032 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20033 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20034 | ((INSTANCE) == UART5) || \ |
| AnnaBridge | 172:65be27845400 | 20035 | ((INSTANCE) == LPUART1)) |
| AnnaBridge | 172:65be27845400 | 20036 | |
| AnnaBridge | 172:65be27845400 | 20037 | /*********************** UART Instances : SPI Slave mode **********************/ |
| AnnaBridge | 172:65be27845400 | 20038 | #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20039 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20040 | ((INSTANCE) == USART3)) |
| AnnaBridge | 172:65be27845400 | 20041 | |
| AnnaBridge | 172:65be27845400 | 20042 | /****************** UART Instances : Auto Baud Rate detection ****************/ |
| AnnaBridge | 172:65be27845400 | 20043 | #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20044 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20045 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20046 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20047 | ((INSTANCE) == UART5)) |
| AnnaBridge | 172:65be27845400 | 20048 | |
| AnnaBridge | 172:65be27845400 | 20049 | /****************** UART Instances : Driver Enable *****************/ |
| AnnaBridge | 172:65be27845400 | 20050 | #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20051 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20052 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20053 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20054 | ((INSTANCE) == UART5) || \ |
| AnnaBridge | 172:65be27845400 | 20055 | ((INSTANCE) == LPUART1)) |
| AnnaBridge | 172:65be27845400 | 20056 | |
| AnnaBridge | 172:65be27845400 | 20057 | /******************** UART Instances : Half-Duplex mode **********************/ |
| AnnaBridge | 172:65be27845400 | 20058 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20059 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20060 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20061 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20062 | ((INSTANCE) == UART5) || \ |
| AnnaBridge | 172:65be27845400 | 20063 | ((INSTANCE) == LPUART1)) |
| AnnaBridge | 172:65be27845400 | 20064 | |
| AnnaBridge | 172:65be27845400 | 20065 | /****************** UART Instances : Hardware Flow control ********************/ |
| AnnaBridge | 172:65be27845400 | 20066 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20067 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20068 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20069 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20070 | ((INSTANCE) == UART5) || \ |
| AnnaBridge | 172:65be27845400 | 20071 | ((INSTANCE) == LPUART1)) |
| AnnaBridge | 172:65be27845400 | 20072 | |
| AnnaBridge | 172:65be27845400 | 20073 | /******************** UART Instances : LIN mode **********************/ |
| AnnaBridge | 172:65be27845400 | 20074 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20075 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20076 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20077 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20078 | ((INSTANCE) == UART5)) |
| AnnaBridge | 172:65be27845400 | 20079 | |
| AnnaBridge | 172:65be27845400 | 20080 | /******************** UART Instances : Wake-up from Stop mode **********************/ |
| AnnaBridge | 172:65be27845400 | 20081 | #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20082 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20083 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20084 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20085 | ((INSTANCE) == UART5) || \ |
| AnnaBridge | 172:65be27845400 | 20086 | ((INSTANCE) == LPUART1)) |
| AnnaBridge | 172:65be27845400 | 20087 | |
| AnnaBridge | 172:65be27845400 | 20088 | /*********************** UART Instances : IRDA mode ***************************/ |
| AnnaBridge | 172:65be27845400 | 20089 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20090 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20091 | ((INSTANCE) == USART3) || \ |
| AnnaBridge | 172:65be27845400 | 20092 | ((INSTANCE) == UART4) || \ |
| AnnaBridge | 172:65be27845400 | 20093 | ((INSTANCE) == UART5)) |
| AnnaBridge | 172:65be27845400 | 20094 | |
| AnnaBridge | 172:65be27845400 | 20095 | /********************* USART Instances : Smard card mode ***********************/ |
| AnnaBridge | 172:65be27845400 | 20096 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| AnnaBridge | 172:65be27845400 | 20097 | ((INSTANCE) == USART2) || \ |
| AnnaBridge | 172:65be27845400 | 20098 | ((INSTANCE) == USART3)) |
| AnnaBridge | 172:65be27845400 | 20099 | |
| AnnaBridge | 172:65be27845400 | 20100 | /******************** LPUART Instance *****************************************/ |
| AnnaBridge | 172:65be27845400 | 20101 | #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| AnnaBridge | 172:65be27845400 | 20102 | |
| AnnaBridge | 172:65be27845400 | 20103 | /****************************** IWDG Instances ********************************/ |
| AnnaBridge | 172:65be27845400 | 20104 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| AnnaBridge | 172:65be27845400 | 20105 | |
| AnnaBridge | 172:65be27845400 | 20106 | /****************************** WWDG Instances ********************************/ |
| AnnaBridge | 172:65be27845400 | 20107 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
| AnnaBridge | 172:65be27845400 | 20108 | |
| AnnaBridge | 172:65be27845400 | 20109 | /** |
| AnnaBridge | 172:65be27845400 | 20110 | * @} |
| AnnaBridge | 172:65be27845400 | 20111 | */ |
| AnnaBridge | 172:65be27845400 | 20112 | |
| AnnaBridge | 172:65be27845400 | 20113 | |
| AnnaBridge | 172:65be27845400 | 20114 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 20115 | /* For a painless codes migration between the STM32L4xx device product */ |
| AnnaBridge | 172:65be27845400 | 20116 | /* lines, the aliases defined below are put in place to overcome the */ |
| AnnaBridge | 172:65be27845400 | 20117 | /* differences in the interrupt handlers and IRQn definitions. */ |
| AnnaBridge | 172:65be27845400 | 20118 | /* No need to update developed interrupt code when moving across */ |
| AnnaBridge | 172:65be27845400 | 20119 | /* product lines within the same STM32L4 Family */ |
| AnnaBridge | 172:65be27845400 | 20120 | /******************************************************************************/ |
| AnnaBridge | 172:65be27845400 | 20121 | |
| AnnaBridge | 172:65be27845400 | 20122 | /* Aliases for __IRQn */ |
| AnnaBridge | 172:65be27845400 | 20123 | #define ADC1_2_IRQn ADC1_IRQn |
| AnnaBridge | 172:65be27845400 | 20124 | #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn |
| AnnaBridge | 172:65be27845400 | 20125 | #define TIM8_IRQn TIM8_UP_IRQn |
| AnnaBridge | 172:65be27845400 | 20126 | #define HASH_RNG_IRQn RNG_IRQn |
| AnnaBridge | 172:65be27845400 | 20127 | #define HASH_CRS_IRQn CRS_IRQn |
| AnnaBridge | 172:65be27845400 | 20128 | #define DFSDM0_IRQn DFSDM1_FLT0_IRQn |
| AnnaBridge | 172:65be27845400 | 20129 | #define DFSDM1_IRQn DFSDM1_FLT1_IRQn |
| AnnaBridge | 172:65be27845400 | 20130 | #define DFSDM2_IRQn DFSDM1_FLT2_IRQn |
| AnnaBridge | 172:65be27845400 | 20131 | #define DFSDM3_IRQn DFSDM1_FLT3_IRQn |
| AnnaBridge | 172:65be27845400 | 20132 | |
| AnnaBridge | 172:65be27845400 | 20133 | /* Aliases for __IRQHandler */ |
| AnnaBridge | 172:65be27845400 | 20134 | #define ADC1_2_IRQHandler ADC1_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20135 | #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20136 | #define TIM8_IRQHandler TIM8_UP_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20137 | #define HASH_RNG_IRQHandler RNG_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20138 | #define HASH_CRS_IRQHandler CRS_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20139 | #define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20140 | #define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20141 | #define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20142 | #define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler |
| AnnaBridge | 172:65be27845400 | 20143 | |
| AnnaBridge | 172:65be27845400 | 20144 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 20145 | } |
| AnnaBridge | 172:65be27845400 | 20146 | #endif /* __cplusplus */ |
| AnnaBridge | 172:65be27845400 | 20147 | |
| AnnaBridge | 172:65be27845400 | 20148 | #endif /* __STM32L4R5xx_H */ |
| AnnaBridge | 172:65be27845400 | 20149 | |
| AnnaBridge | 172:65be27845400 | 20150 | /** |
| AnnaBridge | 172:65be27845400 | 20151 | * @} |
| AnnaBridge | 172:65be27845400 | 20152 | */ |
| AnnaBridge | 172:65be27845400 | 20153 | |
| AnnaBridge | 172:65be27845400 | 20154 | /** |
| AnnaBridge | 172:65be27845400 | 20155 | * @} |
| AnnaBridge | 172:65be27845400 | 20156 | */ |
| AnnaBridge | 172:65be27845400 | 20157 | |
| AnnaBridge | 172:65be27845400 | 20158 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
