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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_ll_tim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_ll_tim.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of TIM LL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_LL_TIM_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_LL_TIM_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx.h"
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	172:65be27845400	48	* @{
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	/** @defgroup TIM_LL TIM
AnnaBridge	172:65be27845400	54	* @{
AnnaBridge	172:65be27845400	55	*/
AnnaBridge	172:65be27845400	56
AnnaBridge	172:65be27845400	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	172:65be27845400	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	172:65be27845400	60	* @{
AnnaBridge	172:65be27845400	61	*/
AnnaBridge	172:65be27845400	62	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	172:65be27845400	63	{
AnnaBridge	172:65be27845400	64	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	172:65be27845400	65	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	172:65be27845400	66	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	172:65be27845400	67	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	172:65be27845400	68	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	172:65be27845400	69	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	172:65be27845400	70	0x04U, /* 6: TIMx_CH4 */
AnnaBridge	172:65be27845400	71	0x3CU, /* 7: TIMx_CH5 */
AnnaBridge	172:65be27845400	72	0x3CU /* 8: TIMx_CH6 */
AnnaBridge	172:65be27845400	73	};
AnnaBridge	172:65be27845400	74
AnnaBridge	172:65be27845400	75	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	172:65be27845400	76	{
AnnaBridge	172:65be27845400	77	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	172:65be27845400	78	0U, /* 1: - NA */
AnnaBridge	172:65be27845400	79	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	172:65be27845400	80	0U, /* 3: - NA */
AnnaBridge	172:65be27845400	81	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	172:65be27845400	82	0U, /* 5: - NA */
AnnaBridge	172:65be27845400	83	8U, /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	172:65be27845400	84	0U, /* 7: OC5M, OC5FE, OC5PE */
AnnaBridge	172:65be27845400	85	8U /* 8: OC6M, OC6FE, OC6PE */
AnnaBridge	172:65be27845400	86	};
AnnaBridge	172:65be27845400	87
AnnaBridge	172:65be27845400	88	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	172:65be27845400	89	{
AnnaBridge	172:65be27845400	90	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	172:65be27845400	91	0U, /* 1: - NA */
AnnaBridge	172:65be27845400	92	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	172:65be27845400	93	0U, /* 3: - NA */
AnnaBridge	172:65be27845400	94	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	172:65be27845400	95	0U, /* 5: - NA */
AnnaBridge	172:65be27845400	96	8U, /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	172:65be27845400	97	0U, /* 7: - NA */
AnnaBridge	172:65be27845400	98	0U /* 8: - NA */
AnnaBridge	172:65be27845400	99	};
AnnaBridge	172:65be27845400	100
AnnaBridge	172:65be27845400	101	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	172:65be27845400	102	{
AnnaBridge	172:65be27845400	103	0U, /* 0: CC1P */
AnnaBridge	172:65be27845400	104	2U, /* 1: CC1NP */
AnnaBridge	172:65be27845400	105	4U, /* 2: CC2P */
AnnaBridge	172:65be27845400	106	6U, /* 3: CC2NP */
AnnaBridge	172:65be27845400	107	8U, /* 4: CC3P */
AnnaBridge	172:65be27845400	108	10U, /* 5: CC3NP */
AnnaBridge	172:65be27845400	109	12U, /* 6: CC4P */
AnnaBridge	172:65be27845400	110	16U, /* 7: CC5P */
AnnaBridge	172:65be27845400	111	20U /* 8: CC6P */
AnnaBridge	172:65be27845400	112	};
AnnaBridge	172:65be27845400	113
AnnaBridge	172:65be27845400	114	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	172:65be27845400	115	{
AnnaBridge	172:65be27845400	116	0U, /* 0: OIS1 */
AnnaBridge	172:65be27845400	117	1U, /* 1: OIS1N */
AnnaBridge	172:65be27845400	118	2U, /* 2: OIS2 */
AnnaBridge	172:65be27845400	119	3U, /* 3: OIS2N */
AnnaBridge	172:65be27845400	120	4U, /* 4: OIS3 */
AnnaBridge	172:65be27845400	121	5U, /* 5: OIS3N */
AnnaBridge	172:65be27845400	122	6U, /* 6: OIS4 */
AnnaBridge	172:65be27845400	123	8U, /* 7: OIS5 */
AnnaBridge	172:65be27845400	124	10U /* 8: OIS6 */
AnnaBridge	172:65be27845400	125	};
AnnaBridge	172:65be27845400	126	/**
AnnaBridge	172:65be27845400	127	* @}
AnnaBridge	172:65be27845400	128	*/
AnnaBridge	172:65be27845400	129
AnnaBridge	172:65be27845400	130
AnnaBridge	172:65be27845400	131	/* Private constants ---------------------------------------------------------*/
AnnaBridge	172:65be27845400	132	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	172:65be27845400	133	* @{
AnnaBridge	172:65be27845400	134	*/
AnnaBridge	172:65be27845400	135
AnnaBridge	172:65be27845400	136	/* Defines used for the bit position in the register and perform offsets */
AnnaBridge	172:65be27845400	137	#define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source)
AnnaBridge	172:65be27845400	138
AnnaBridge	172:65be27845400	139	/* Generic bit definitions for TIMx_OR2 register */
AnnaBridge	172:65be27845400	140	#define TIMx_OR2_BKINE TIM1_OR2_BKINE /!< BRK BKIN input enable /
AnnaBridge	172:65be27845400	141	#define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /!< BRK COMP1 enable /
AnnaBridge	172:65be27845400	142	#define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /!< BRK COMP2 enable /
AnnaBridge	172:65be27845400	143	#if defined(DFSDM1_Channel0)
AnnaBridge	172:65be27845400	144	#define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /!< BRK DFSDM1_BREAK[0] enable /
AnnaBridge	172:65be27845400	145	#endif /* DFSDM1_Channel0 */
AnnaBridge	172:65be27845400	146	#define TIMx_OR2_BKINP TIM1_OR2_BKINP /!< BRK BKIN input polarity /
AnnaBridge	172:65be27845400	147	#define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /!< BRK COMP1 input polarity /
AnnaBridge	172:65be27845400	148	#define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /!< BRK COMP2 input polarity /
AnnaBridge	172:65be27845400	149	#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /!< TIMx ETR source selection /
AnnaBridge	172:65be27845400	150
AnnaBridge	172:65be27845400	151	/* Generic bit definitions for TIMx_OR3 register */
AnnaBridge	172:65be27845400	152	#define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /!< BRK2 BKIN2 input enable /
AnnaBridge	172:65be27845400	153	#define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /!< BRK2 COMP1 enable /
AnnaBridge	172:65be27845400	154	#define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /!< BRK2 COMP2 enable /
AnnaBridge	172:65be27845400	155	#if defined(DFSDM1_Channel0)
AnnaBridge	172:65be27845400	156	#define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /!< BRK2 DFSDM1_BREAK[1] enable /
AnnaBridge	172:65be27845400	157	#endif /* DFSDM1_Channel0 */
AnnaBridge	172:65be27845400	158	#define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /!< BRK2 BKIN2 input polarity /
AnnaBridge	172:65be27845400	159	#define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /!< BRK2 COMP1 input polarity /
AnnaBridge	172:65be27845400	160	#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /!< BRK2 COMP2 input polarity /
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	/* Remap mask definitions */
AnnaBridge	172:65be27845400	163	#define TIMx_OR1_RMP_SHIFT 16U
AnnaBridge	172:65be27845400	164	#define TIMx_OR1_RMP_MASK 0x0000FFFFU
AnnaBridge	172:65be27845400	165	#if defined(ADC3)
AnnaBridge	172:65be27845400	166	#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	167	#else
AnnaBridge	172:65be27845400	168	#define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	169	#endif /* ADC3 */
AnnaBridge	172:65be27845400	170	#define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP \| TIM2_OR1_ETR1_RMP \| TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	171	#define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	172	#if defined(ADC2) && defined(ADC3)
AnnaBridge	172:65be27845400	173	#define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	174	#else
AnnaBridge	172:65be27845400	175	#define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	176	#endif /* ADC2 & ADC3 */
AnnaBridge	172:65be27845400	177	#define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	178	#define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	179	#define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT)
AnnaBridge	172:65be27845400	180
AnnaBridge	172:65be27845400	181	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	172:65be27845400	182	#define DT_DELAY_1 ((uint8_t)0x7F)
AnnaBridge	172:65be27845400	183	#define DT_DELAY_2 ((uint8_t)0x3F)
AnnaBridge	172:65be27845400	184	#define DT_DELAY_3 ((uint8_t)0x1F)
AnnaBridge	172:65be27845400	185	#define DT_DELAY_4 ((uint8_t)0x1F)
AnnaBridge	172:65be27845400	186
AnnaBridge	172:65be27845400	187	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	172:65be27845400	188	#define DT_RANGE_1 ((uint8_t)0x00)
AnnaBridge	172:65be27845400	189	#define DT_RANGE_2 ((uint8_t)0x80)
AnnaBridge	172:65be27845400	190	#define DT_RANGE_3 ((uint8_t)0xC0)
AnnaBridge	172:65be27845400	191	#define DT_RANGE_4 ((uint8_t)0xE0)
AnnaBridge	172:65be27845400	192
AnnaBridge	172:65be27845400	193	/** Legacy definitions for compatibility purpose
AnnaBridge	172:65be27845400	194	@cond 0
AnnaBridge	172:65be27845400	195	*/
AnnaBridge	172:65be27845400	196	#if defined(DFSDM1_Channel0)
AnnaBridge	172:65be27845400	197	#define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E
AnnaBridge	172:65be27845400	198	#define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E
AnnaBridge	172:65be27845400	199	#endif /* DFSDM1_Channel0 */
AnnaBridge	172:65be27845400	200	/**
AnnaBridge	172:65be27845400	201	@endcond
AnnaBridge	172:65be27845400	202	*/
AnnaBridge	172:65be27845400	203
AnnaBridge	172:65be27845400	204	/**
AnnaBridge	172:65be27845400	205	* @}
AnnaBridge	172:65be27845400	206	*/
AnnaBridge	172:65be27845400	207
AnnaBridge	172:65be27845400	208	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	209	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	172:65be27845400	210	* @{
AnnaBridge	172:65be27845400	211	*/
AnnaBridge	172:65be27845400	212	/** @brief Convert channel id into channel index.
AnnaBridge	172:65be27845400	213	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	214	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	215	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	216	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	217	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	218	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	219	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	220	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	221	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	222	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	223	* @retval none
AnnaBridge	172:65be27845400	224	*/
AnnaBridge	172:65be27845400	225	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	172:65be27845400	226	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	172:65be27845400	227	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	172:65be27845400	228	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	172:65be27845400	229	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	172:65be27845400	230	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	172:65be27845400	231	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
AnnaBridge	172:65be27845400	232	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
AnnaBridge	172:65be27845400	233	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
AnnaBridge	172:65be27845400	234
AnnaBridge	172:65be27845400	235	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	172:65be27845400	236	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	172:65be27845400	237	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	238	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	239	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	240	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	241	* @retval none
AnnaBridge	172:65be27845400	242	*/
AnnaBridge	172:65be27845400	243	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	172:65be27845400	244	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	172:65be27845400	245	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	172:65be27845400	246	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	172:65be27845400	247	/**
AnnaBridge	172:65be27845400	248	* @}
AnnaBridge	172:65be27845400	249	*/
AnnaBridge	172:65be27845400	250
AnnaBridge	172:65be27845400	251
AnnaBridge	172:65be27845400	252	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	253	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	254	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	172:65be27845400	255	* @{
AnnaBridge	172:65be27845400	256	*/
AnnaBridge	172:65be27845400	257
AnnaBridge	172:65be27845400	258	/**
AnnaBridge	172:65be27845400	259	* @brief TIM Time Base configuration structure definition.
AnnaBridge	172:65be27845400	260	*/
AnnaBridge	172:65be27845400	261	typedef struct
AnnaBridge	172:65be27845400	262	{
AnnaBridge	172:65be27845400	263	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	172:65be27845400	264	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	172:65be27845400	265
AnnaBridge	172:65be27845400	266	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	172:65be27845400	267
AnnaBridge	172:65be27845400	268	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	172:65be27845400	269	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	172:65be27845400	270
AnnaBridge	172:65be27845400	271	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	172:65be27845400	272
AnnaBridge	172:65be27845400	273	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	172:65be27845400	274	Auto-Reload Register at the next update event.
AnnaBridge	172:65be27845400	275	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	172:65be27845400	276	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	277
AnnaBridge	172:65be27845400	278	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	172:65be27845400	279
AnnaBridge	172:65be27845400	280	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	172:65be27845400	281	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	172:65be27845400	282
AnnaBridge	172:65be27845400	283	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	172:65be27845400	284
AnnaBridge	172:65be27845400	285	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	172:65be27845400	286	reaches zero, an update event is generated and counting restarts
AnnaBridge	172:65be27845400	287	from the RCR value (N).
AnnaBridge	172:65be27845400	288	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	172:65be27845400	289	- the number of PWM periods in edge-aligned mode
AnnaBridge	172:65be27845400	290	- the number of half PWM period in center-aligned mode
AnnaBridge	172:65be27845400	291	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	172:65be27845400	292
AnnaBridge	172:65be27845400	293	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	172:65be27845400	294	} LL_TIM_InitTypeDef;
AnnaBridge	172:65be27845400	295
AnnaBridge	172:65be27845400	296	/**
AnnaBridge	172:65be27845400	297	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	172:65be27845400	298	*/
AnnaBridge	172:65be27845400	299	typedef struct
AnnaBridge	172:65be27845400	300	{
AnnaBridge	172:65be27845400	301	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	172:65be27845400	302	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	172:65be27845400	303
AnnaBridge	172:65be27845400	304	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	172:65be27845400	307	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	172:65be27845400	308
AnnaBridge	172:65be27845400	309	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	172:65be27845400	310
AnnaBridge	172:65be27845400	311	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	172:65be27845400	312	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	172:65be27845400	313
AnnaBridge	172:65be27845400	314	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	172:65be27845400	315
AnnaBridge	172:65be27845400	316	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	172:65be27845400	317	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	172:65be27845400	318
AnnaBridge	172:65be27845400	319	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	172:65be27845400	320
AnnaBridge	172:65be27845400	321	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	172:65be27845400	322	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	172:65be27845400	323
AnnaBridge	172:65be27845400	324	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	172:65be27845400	325
AnnaBridge	172:65be27845400	326	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	172:65be27845400	327	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	172:65be27845400	328
AnnaBridge	172:65be27845400	329	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	172:65be27845400	330
AnnaBridge	172:65be27845400	331
AnnaBridge	172:65be27845400	332	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	172:65be27845400	333	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	172:65be27845400	334
AnnaBridge	172:65be27845400	335	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	172:65be27845400	336
AnnaBridge	172:65be27845400	337	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	172:65be27845400	338	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	172:65be27845400	339
AnnaBridge	172:65be27845400	340	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	172:65be27845400	341	} LL_TIM_OC_InitTypeDef;
AnnaBridge	172:65be27845400	342
AnnaBridge	172:65be27845400	343	/**
AnnaBridge	172:65be27845400	344	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	172:65be27845400	345	*/
AnnaBridge	172:65be27845400	346
AnnaBridge	172:65be27845400	347	typedef struct
AnnaBridge	172:65be27845400	348	{
AnnaBridge	172:65be27845400	349
AnnaBridge	172:65be27845400	350	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	172:65be27845400	351	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	352
AnnaBridge	172:65be27845400	353	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	354
AnnaBridge	172:65be27845400	355	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	172:65be27845400	356	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	172:65be27845400	359
AnnaBridge	172:65be27845400	360	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	172:65be27845400	361	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	362
AnnaBridge	172:65be27845400	363	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	364
AnnaBridge	172:65be27845400	365	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	172:65be27845400	366	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	367
AnnaBridge	172:65be27845400	368	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	369	} LL_TIM_IC_InitTypeDef;
AnnaBridge	172:65be27845400	370
AnnaBridge	172:65be27845400	371
AnnaBridge	172:65be27845400	372	/**
AnnaBridge	172:65be27845400	373	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	172:65be27845400	374	*/
AnnaBridge	172:65be27845400	375	typedef struct
AnnaBridge	172:65be27845400	376	{
AnnaBridge	172:65be27845400	377	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	172:65be27845400	378	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	172:65be27845400	379
AnnaBridge	172:65be27845400	380	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	172:65be27845400	381
AnnaBridge	172:65be27845400	382	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	172:65be27845400	383	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	384
AnnaBridge	172:65be27845400	385	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	386
AnnaBridge	172:65be27845400	387	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	172:65be27845400	388	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	172:65be27845400	389
AnnaBridge	172:65be27845400	390	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	172:65be27845400	393	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	394
AnnaBridge	172:65be27845400	395	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	396
AnnaBridge	172:65be27845400	397	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	172:65be27845400	398	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	399
AnnaBridge	172:65be27845400	400	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	401
AnnaBridge	172:65be27845400	402	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	172:65be27845400	403	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	404
AnnaBridge	172:65be27845400	405	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	406
AnnaBridge	172:65be27845400	407	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	172:65be27845400	408	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	172:65be27845400	409
AnnaBridge	172:65be27845400	410	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	172:65be27845400	411
AnnaBridge	172:65be27845400	412	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	172:65be27845400	413	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	414
AnnaBridge	172:65be27845400	415	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	416
AnnaBridge	172:65be27845400	417	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	172:65be27845400	418	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	419
AnnaBridge	172:65be27845400	420	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	421
AnnaBridge	172:65be27845400	422	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	172:65be27845400	423
AnnaBridge	172:65be27845400	424	/**
AnnaBridge	172:65be27845400	425	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	172:65be27845400	426	*/
AnnaBridge	172:65be27845400	427	typedef struct
AnnaBridge	172:65be27845400	428	{
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	172:65be27845400	431	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	172:65be27845400	432
AnnaBridge	172:65be27845400	433	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	172:65be27845400	434
AnnaBridge	172:65be27845400	435	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	172:65be27845400	436	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	172:65be27845400	437	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	172:65be27845400	438	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	172:65be27845400	439
AnnaBridge	172:65be27845400	440	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	172:65be27845400	441
AnnaBridge	172:65be27845400	442	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	172:65be27845400	443	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	172:65be27845400	444
AnnaBridge	172:65be27845400	445	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	172:65be27845400	446
AnnaBridge	172:65be27845400	447	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	172:65be27845400	448	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	172:65be27845400	449	a change occurs on the Hall inputs.
AnnaBridge	172:65be27845400	450	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	172:65be27845400	451
AnnaBridge	172:65be27845400	452	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	172:65be27845400	453	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	172:65be27845400	454
AnnaBridge	172:65be27845400	455	/**
AnnaBridge	172:65be27845400	456	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	172:65be27845400	457	*/
AnnaBridge	172:65be27845400	458	typedef struct
AnnaBridge	172:65be27845400	459	{
AnnaBridge	172:65be27845400	460	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	172:65be27845400	461	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	172:65be27845400	462
AnnaBridge	172:65be27845400	463	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	172:65be27845400	464
AnnaBridge	172:65be27845400	465	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	172:65be27845400	466
AnnaBridge	172:65be27845400	467	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	172:65be27845400	468	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	172:65be27845400	469
AnnaBridge	172:65be27845400	470	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	172:65be27845400	471
AnnaBridge	172:65be27845400	472	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	172:65be27845400	473
AnnaBridge	172:65be27845400	474	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	172:65be27845400	475	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	172:65be27845400	476
AnnaBridge	172:65be27845400	477	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	172:65be27845400	478	has been written, their content is frozen until the next reset.*/
AnnaBridge	172:65be27845400	479
AnnaBridge	172:65be27845400	480	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	172:65be27845400	481	switching-on of the outputs.
AnnaBridge	172:65be27845400	482	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	172:65be27845400	483
AnnaBridge	172:65be27845400	484	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	172:65be27845400	485
AnnaBridge	172:65be27845400	486	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	172:65be27845400	487
AnnaBridge	172:65be27845400	488	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	172:65be27845400	489	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	172:65be27845400	490
AnnaBridge	172:65be27845400	491	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	172:65be27845400	492
AnnaBridge	172:65be27845400	493	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	494
AnnaBridge	172:65be27845400	495	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	172:65be27845400	496	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	172:65be27845400	497
AnnaBridge	172:65be27845400	498	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	172:65be27845400	499
AnnaBridge	172:65be27845400	500	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	501
AnnaBridge	172:65be27845400	502	uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
AnnaBridge	172:65be27845400	503	This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
AnnaBridge	172:65be27845400	504
AnnaBridge	172:65be27845400	505	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	172:65be27845400	506
AnnaBridge	172:65be27845400	507	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	508
AnnaBridge	172:65be27845400	509	uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
AnnaBridge	172:65be27845400	510	This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
AnnaBridge	172:65be27845400	511
AnnaBridge	172:65be27845400	512	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
AnnaBridge	172:65be27845400	513
AnnaBridge	172:65be27845400	514	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	515
AnnaBridge	172:65be27845400	516	uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
AnnaBridge	172:65be27845400	517	This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
AnnaBridge	172:65be27845400	518
AnnaBridge	172:65be27845400	519	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	172:65be27845400	520
AnnaBridge	172:65be27845400	521	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	522
AnnaBridge	172:65be27845400	523	uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
AnnaBridge	172:65be27845400	524	This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
AnnaBridge	172:65be27845400	525
AnnaBridge	172:65be27845400	526	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
AnnaBridge	172:65be27845400	527
AnnaBridge	172:65be27845400	528	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	529
AnnaBridge	172:65be27845400	530	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	172:65be27845400	531	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	172:65be27845400	532
AnnaBridge	172:65be27845400	533	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	172:65be27845400	534
AnnaBridge	172:65be27845400	535	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	172:65be27845400	536	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	172:65be27845400	537
AnnaBridge	172:65be27845400	538	/**
AnnaBridge	172:65be27845400	539	* @}
AnnaBridge	172:65be27845400	540	*/
AnnaBridge	172:65be27845400	541	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	542
AnnaBridge	172:65be27845400	543	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	544	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	172:65be27845400	545	* @{
AnnaBridge	172:65be27845400	546	*/
AnnaBridge	172:65be27845400	547
AnnaBridge	172:65be27845400	548	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	172:65be27845400	549	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	172:65be27845400	550	* @{
AnnaBridge	172:65be27845400	551	*/
AnnaBridge	172:65be27845400	552	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	172:65be27845400	553	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	172:65be27845400	554	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	172:65be27845400	555	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	172:65be27845400	556	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	172:65be27845400	557	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /!< Capture/compare 5 interrupt flag /
AnnaBridge	172:65be27845400	558	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /!< Capture/compare 6 interrupt flag /
AnnaBridge	172:65be27845400	559	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	172:65be27845400	560	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	172:65be27845400	561	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	172:65be27845400	562	#define LL_TIM_SR_B2IF TIM_SR_B2IF /!< Second break interrupt flag /
AnnaBridge	172:65be27845400	563	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	172:65be27845400	564	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	172:65be27845400	565	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	172:65be27845400	566	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	172:65be27845400	567	#define LL_TIM_SR_SBIF TIM_SR_SBIF /!< System Break interrupt flag /
AnnaBridge	172:65be27845400	568	/**
AnnaBridge	172:65be27845400	569	* @}
AnnaBridge	172:65be27845400	570	*/
AnnaBridge	172:65be27845400	571
AnnaBridge	172:65be27845400	572	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	573	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	172:65be27845400	574	* @{
AnnaBridge	172:65be27845400	575	*/
AnnaBridge	172:65be27845400	576	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	172:65be27845400	577	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	172:65be27845400	578	/**
AnnaBridge	172:65be27845400	579	* @}
AnnaBridge	172:65be27845400	580	*/
AnnaBridge	172:65be27845400	581
AnnaBridge	172:65be27845400	582	/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
AnnaBridge	172:65be27845400	583	* @{
AnnaBridge	172:65be27845400	584	*/
AnnaBridge	172:65be27845400	585	#define LL_TIM_BREAK2_DISABLE 0x00000000U /!< Break2 function disabled /
AnnaBridge	172:65be27845400	586	#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /!< Break2 function enabled /
AnnaBridge	172:65be27845400	587	/**
AnnaBridge	172:65be27845400	588	* @}
AnnaBridge	172:65be27845400	589	*/
AnnaBridge	172:65be27845400	590
AnnaBridge	172:65be27845400	591	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	172:65be27845400	592	* @{
AnnaBridge	172:65be27845400	593	*/
AnnaBridge	172:65be27845400	594	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	172:65be27845400	595	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	172:65be27845400	596	/**
AnnaBridge	172:65be27845400	597	* @}
AnnaBridge	172:65be27845400	598	*/
AnnaBridge	172:65be27845400	599	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	600
AnnaBridge	172:65be27845400	601	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	172:65be27845400	602	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	172:65be27845400	603	* @{
AnnaBridge	172:65be27845400	604	*/
AnnaBridge	172:65be27845400	605	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	172:65be27845400	606	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	172:65be27845400	607	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	172:65be27845400	608	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	172:65be27845400	609	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	172:65be27845400	610	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	172:65be27845400	611	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	172:65be27845400	612	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	172:65be27845400	613	/**
AnnaBridge	172:65be27845400	614	* @}
AnnaBridge	172:65be27845400	615	*/
AnnaBridge	172:65be27845400	616
AnnaBridge	172:65be27845400	617	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	172:65be27845400	618	* @{
AnnaBridge	172:65be27845400	619	*/
AnnaBridge	172:65be27845400	620	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	172:65be27845400	621	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	172:65be27845400	622	/**
AnnaBridge	172:65be27845400	623	* @}
AnnaBridge	172:65be27845400	624	*/
AnnaBridge	172:65be27845400	625
AnnaBridge	172:65be27845400	626	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	172:65be27845400	627	* @{
AnnaBridge	172:65be27845400	628	*/
AnnaBridge	172:65be27845400	629	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	172:65be27845400	630	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	172:65be27845400	631	/**
AnnaBridge	172:65be27845400	632	* @}
AnnaBridge	172:65be27845400	633	*/
AnnaBridge	172:65be27845400	634
AnnaBridge	172:65be27845400	635	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	172:65be27845400	636	* @{
AnnaBridge	172:65be27845400	637	*/
AnnaBridge	172:65be27845400	638	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	172:65be27845400	639	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	172:65be27845400	640	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	172:65be27845400	641	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	172:65be27845400	642	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	172:65be27845400	643	/**
AnnaBridge	172:65be27845400	644	* @}
AnnaBridge	172:65be27845400	645	*/
AnnaBridge	172:65be27845400	646
AnnaBridge	172:65be27845400	647	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	172:65be27845400	648	* @{
AnnaBridge	172:65be27845400	649	*/
AnnaBridge	172:65be27845400	650	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	172:65be27845400	651	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	172:65be27845400	652	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	172:65be27845400	653	/**
AnnaBridge	172:65be27845400	654	* @}
AnnaBridge	172:65be27845400	655	*/
AnnaBridge	172:65be27845400	656
AnnaBridge	172:65be27845400	657	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	172:65be27845400	658	* @{
AnnaBridge	172:65be27845400	659	*/
AnnaBridge	172:65be27845400	660	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	172:65be27845400	661	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	172:65be27845400	662	/**
AnnaBridge	172:65be27845400	663	* @}
AnnaBridge	172:65be27845400	664	*/
AnnaBridge	172:65be27845400	665
AnnaBridge	172:65be27845400	666	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	172:65be27845400	667	* @{
AnnaBridge	172:65be27845400	668	*/
AnnaBridge	172:65be27845400	669	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	172:65be27845400	670	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	172:65be27845400	671	/**
AnnaBridge	172:65be27845400	672	* @}
AnnaBridge	172:65be27845400	673	*/
AnnaBridge	172:65be27845400	674
AnnaBridge	172:65be27845400	675	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	172:65be27845400	676	* @{
AnnaBridge	172:65be27845400	677	*/
AnnaBridge	172:65be27845400	678	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	172:65be27845400	679	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	172:65be27845400	680	/**
AnnaBridge	172:65be27845400	681	* @}
AnnaBridge	172:65be27845400	682	*/
AnnaBridge	172:65be27845400	683
AnnaBridge	172:65be27845400	684	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	172:65be27845400	685	* @{
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	172:65be27845400	688	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	172:65be27845400	689	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	172:65be27845400	690	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	172:65be27845400	691	/**
AnnaBridge	172:65be27845400	692	* @}
AnnaBridge	172:65be27845400	693	*/
AnnaBridge	172:65be27845400	694
AnnaBridge	172:65be27845400	695	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	172:65be27845400	696	* @{
AnnaBridge	172:65be27845400	697	*/
AnnaBridge	172:65be27845400	698	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	172:65be27845400	699	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	172:65be27845400	700	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	172:65be27845400	701	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	172:65be27845400	702	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	172:65be27845400	703	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	172:65be27845400	704	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	172:65be27845400	705	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
AnnaBridge	172:65be27845400	706	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
AnnaBridge	172:65be27845400	707	/**
AnnaBridge	172:65be27845400	708	* @}
AnnaBridge	172:65be27845400	709	*/
AnnaBridge	172:65be27845400	710
AnnaBridge	172:65be27845400	711	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	712	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	172:65be27845400	713	* @{
AnnaBridge	172:65be27845400	714	*/
AnnaBridge	172:65be27845400	715	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	172:65be27845400	716	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	172:65be27845400	717	/**
AnnaBridge	172:65be27845400	718	* @}
AnnaBridge	172:65be27845400	719	*/
AnnaBridge	172:65be27845400	720	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	721
AnnaBridge	172:65be27845400	722	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	172:65be27845400	723	* @{
AnnaBridge	172:65be27845400	724	*/
AnnaBridge	172:65be27845400	725	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	172:65be27845400	726	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	172:65be27845400	727	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	172:65be27845400	728	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	172:65be27845400	729	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	172:65be27845400	730	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	172:65be27845400	731	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	172:65be27845400	732	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	172:65be27845400	733	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
AnnaBridge	172:65be27845400	734	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
AnnaBridge	172:65be27845400	735	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
AnnaBridge	172:65be27845400	736	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
AnnaBridge	172:65be27845400	737	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
AnnaBridge	172:65be27845400	738	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
AnnaBridge	172:65be27845400	739	/**
AnnaBridge	172:65be27845400	740	* @}
AnnaBridge	172:65be27845400	741	*/
AnnaBridge	172:65be27845400	742
AnnaBridge	172:65be27845400	743	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	172:65be27845400	744	* @{
AnnaBridge	172:65be27845400	745	*/
AnnaBridge	172:65be27845400	746	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	172:65be27845400	747	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	172:65be27845400	748	/**
AnnaBridge	172:65be27845400	749	* @}
AnnaBridge	172:65be27845400	750	*/
AnnaBridge	172:65be27845400	751
AnnaBridge	172:65be27845400	752	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	172:65be27845400	753	* @{
AnnaBridge	172:65be27845400	754	*/
AnnaBridge	172:65be27845400	755	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	172:65be27845400	756	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	172:65be27845400	757	/**
AnnaBridge	172:65be27845400	758	* @}
AnnaBridge	172:65be27845400	759	*/
AnnaBridge	172:65be27845400	760
AnnaBridge	172:65be27845400	761	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
AnnaBridge	172:65be27845400	762	* @{
AnnaBridge	172:65be27845400	763	*/
AnnaBridge	172:65be27845400	764	#define LL_TIM_GROUPCH5_NONE 0x00000000U /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
AnnaBridge	172:65be27845400	765	#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
AnnaBridge	172:65be27845400	766	#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
AnnaBridge	172:65be27845400	767	#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
AnnaBridge	172:65be27845400	768	/**
AnnaBridge	172:65be27845400	769	* @}
AnnaBridge	172:65be27845400	770	*/
AnnaBridge	172:65be27845400	771
AnnaBridge	172:65be27845400	772	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	172:65be27845400	773	* @{
AnnaBridge	172:65be27845400	774	*/
AnnaBridge	172:65be27845400	775	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	172:65be27845400	776	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	172:65be27845400	777	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	172:65be27845400	778	/**
AnnaBridge	172:65be27845400	779	* @}
AnnaBridge	172:65be27845400	780	*/
AnnaBridge	172:65be27845400	781
AnnaBridge	172:65be27845400	782	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	172:65be27845400	783	* @{
AnnaBridge	172:65be27845400	784	*/
AnnaBridge	172:65be27845400	785	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	172:65be27845400	786	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	172:65be27845400	787	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	172:65be27845400	788	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	172:65be27845400	789	/**
AnnaBridge	172:65be27845400	790	* @}
AnnaBridge	172:65be27845400	791	*/
AnnaBridge	172:65be27845400	792
AnnaBridge	172:65be27845400	793	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	172:65be27845400	794	* @{
AnnaBridge	172:65be27845400	795	*/
AnnaBridge	172:65be27845400	796	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	172:65be27845400	797	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	798	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	799	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	800	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	801	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	802	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	803	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	804	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	172:65be27845400	805	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	806	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	807	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	808	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	809	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	810	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	811	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	812	/**
AnnaBridge	172:65be27845400	813	* @}
AnnaBridge	172:65be27845400	814	*/
AnnaBridge	172:65be27845400	815
AnnaBridge	172:65be27845400	816	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	172:65be27845400	817	* @{
AnnaBridge	172:65be27845400	818	*/
AnnaBridge	172:65be27845400	819	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	172:65be27845400	820	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	172:65be27845400	821	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	172:65be27845400	822	/**
AnnaBridge	172:65be27845400	823	* @}
AnnaBridge	172:65be27845400	824	*/
AnnaBridge	172:65be27845400	825
AnnaBridge	172:65be27845400	826	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	172:65be27845400	827	* @{
AnnaBridge	172:65be27845400	828	*/
AnnaBridge	172:65be27845400	829	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	172:65be27845400	830	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected input/
AnnaBridge	172:65be27845400	831	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	172:65be27845400	832	/**
AnnaBridge	172:65be27845400	833	* @}
AnnaBridge	172:65be27845400	834	*/
AnnaBridge	172:65be27845400	835
AnnaBridge	172:65be27845400	836	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	172:65be27845400	837	* @{
AnnaBridge	172:65be27845400	838	*/
AnnaBridge	172:65be27845400	839	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	172:65be27845400	840	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	172:65be27845400	841	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input /
AnnaBridge	172:65be27845400	842	/**
AnnaBridge	172:65be27845400	843	* @}
AnnaBridge	172:65be27845400	844	*/
AnnaBridge	172:65be27845400	845
AnnaBridge	172:65be27845400	846	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	172:65be27845400	847	* @{
AnnaBridge	172:65be27845400	848	*/
AnnaBridge	172:65be27845400	849	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	172:65be27845400	850	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	172:65be27845400	851	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	172:65be27845400	852	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	172:65be27845400	853	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	172:65be27845400	854	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	172:65be27845400	855	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	172:65be27845400	856	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	172:65be27845400	857	/**
AnnaBridge	172:65be27845400	858	* @}
AnnaBridge	172:65be27845400	859	*/
AnnaBridge	172:65be27845400	860
AnnaBridge	172:65be27845400	861	/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
AnnaBridge	172:65be27845400	862	* @{
AnnaBridge	172:65be27845400	863	*/
AnnaBridge	172:65be27845400	864	#define LL_TIM_TRGO2_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
AnnaBridge	172:65be27845400	865	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
AnnaBridge	172:65be27845400	866	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
AnnaBridge	172:65be27845400	867	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
AnnaBridge	172:65be27845400	868	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	869	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	870	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	871	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	872	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	873	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
AnnaBridge	172:65be27845400	874	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	875	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	876	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	877	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	878	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	879	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
AnnaBridge	172:65be27845400	880	/**
AnnaBridge	172:65be27845400	881	* @}
AnnaBridge	172:65be27845400	882	*/
AnnaBridge	172:65be27845400	883
AnnaBridge	172:65be27845400	884	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	172:65be27845400	885	* @{
AnnaBridge	172:65be27845400	886	*/
AnnaBridge	172:65be27845400	887	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	172:65be27845400	888	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	172:65be27845400	889	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	172:65be27845400	890	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	172:65be27845400	891	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
AnnaBridge	172:65be27845400	892	/**
AnnaBridge	172:65be27845400	893	* @}
AnnaBridge	172:65be27845400	894	*/
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	172:65be27845400	897	* @{
AnnaBridge	172:65be27845400	898	*/
AnnaBridge	172:65be27845400	899	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	172:65be27845400	900	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	172:65be27845400	901	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	172:65be27845400	902	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	172:65be27845400	903	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	172:65be27845400	904	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	172:65be27845400	905	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	172:65be27845400	906	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	172:65be27845400	907	/**
AnnaBridge	172:65be27845400	908	* @}
AnnaBridge	172:65be27845400	909	*/
AnnaBridge	172:65be27845400	910
AnnaBridge	172:65be27845400	911	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	172:65be27845400	912	* @{
AnnaBridge	172:65be27845400	913	*/
AnnaBridge	172:65be27845400	914	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	172:65be27845400	915	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	172:65be27845400	916	/**
AnnaBridge	172:65be27845400	917	* @}
AnnaBridge	172:65be27845400	918	*/
AnnaBridge	172:65be27845400	919
AnnaBridge	172:65be27845400	920	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	172:65be27845400	921	* @{
AnnaBridge	172:65be27845400	922	*/
AnnaBridge	172:65be27845400	923	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	172:65be27845400	924	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	172:65be27845400	925	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	172:65be27845400	926	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	172:65be27845400	927	/**
AnnaBridge	172:65be27845400	928	* @}
AnnaBridge	172:65be27845400	929	*/
AnnaBridge	172:65be27845400	930
AnnaBridge	172:65be27845400	931	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	172:65be27845400	932	* @{
AnnaBridge	172:65be27845400	933	*/
AnnaBridge	172:65be27845400	934	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	172:65be27845400	935	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	936	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	937	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	938	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	939	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	940	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	941	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	942	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	943	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	944	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	945	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	946	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	947	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	948	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	949	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	950	/**
AnnaBridge	172:65be27845400	951	* @}
AnnaBridge	172:65be27845400	952	*/
AnnaBridge	172:65be27845400	953
AnnaBridge	172:65be27845400	954	/** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source
AnnaBridge	172:65be27845400	955	* @{
AnnaBridge	172:65be27845400	956	*/
AnnaBridge	172:65be27845400	957	#define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /!< ETR legacy mode /
AnnaBridge	172:65be27845400	958	#define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /!< COMP1 output connected to ETR input /
AnnaBridge	172:65be27845400	959	#define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /!< COMP2 output connected to ETR input /
AnnaBridge	172:65be27845400	960	/**
AnnaBridge	172:65be27845400	961	* @}
AnnaBridge	172:65be27845400	962	*/
AnnaBridge	172:65be27845400	963
AnnaBridge	172:65be27845400	964	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	172:65be27845400	965	* @{
AnnaBridge	172:65be27845400	966	*/
AnnaBridge	172:65be27845400	967	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	172:65be27845400	968	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	172:65be27845400	969	/**
AnnaBridge	172:65be27845400	970	* @}
AnnaBridge	172:65be27845400	971	*/
AnnaBridge	172:65be27845400	972
AnnaBridge	172:65be27845400	973	/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
AnnaBridge	172:65be27845400	974	* @{
AnnaBridge	172:65be27845400	975	*/
AnnaBridge	172:65be27845400	976	#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	172:65be27845400	977	#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	978	#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	979	#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	980	#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	981	#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	982	#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	983	#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	984	#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	172:65be27845400	985	#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	986	#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	987	#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	988	#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	989	#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	990	#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	991	#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	992	/**
AnnaBridge	172:65be27845400	993	* @}
AnnaBridge	172:65be27845400	994	*/
AnnaBridge	172:65be27845400	995
AnnaBridge	172:65be27845400	996	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
AnnaBridge	172:65be27845400	997	* @{
AnnaBridge	172:65be27845400	998	*/
AnnaBridge	172:65be27845400	999	#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /!< Break input BRK2 is active low /
AnnaBridge	172:65be27845400	1000	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
AnnaBridge	172:65be27845400	1001	/**
AnnaBridge	172:65be27845400	1002	* @}
AnnaBridge	172:65be27845400	1003	*/
AnnaBridge	172:65be27845400	1004
AnnaBridge	172:65be27845400	1005	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
AnnaBridge	172:65be27845400	1006	* @{
AnnaBridge	172:65be27845400	1007	*/
AnnaBridge	172:65be27845400	1008	#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /!< No filter, BRK acts asynchronously /
AnnaBridge	172:65be27845400	1009	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	172:65be27845400	1010	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	172:65be27845400	1011	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	172:65be27845400	1012	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	172:65be27845400	1013	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	172:65be27845400	1014	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	172:65be27845400	1015	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	172:65be27845400	1016	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	172:65be27845400	1017	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	172:65be27845400	1018	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	172:65be27845400	1019	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	172:65be27845400	1020	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	172:65be27845400	1021	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	172:65be27845400	1022	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	172:65be27845400	1023	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	172:65be27845400	1024	/**
AnnaBridge	172:65be27845400	1025	* @}
AnnaBridge	172:65be27845400	1026	*/
AnnaBridge	172:65be27845400	1027
AnnaBridge	172:65be27845400	1028	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	172:65be27845400	1029	* @{
AnnaBridge	172:65be27845400	1030	*/
AnnaBridge	172:65be27845400	1031	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	172:65be27845400	1032	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	172:65be27845400	1033	/**
AnnaBridge	172:65be27845400	1034	* @}
AnnaBridge	172:65be27845400	1035	*/
AnnaBridge	172:65be27845400	1036
AnnaBridge	172:65be27845400	1037	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	172:65be27845400	1038	* @{
AnnaBridge	172:65be27845400	1039	*/
AnnaBridge	172:65be27845400	1040	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	172:65be27845400	1041	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	172:65be27845400	1042	/**
AnnaBridge	172:65be27845400	1043	* @}
AnnaBridge	172:65be27845400	1044	*/
AnnaBridge	172:65be27845400	1045
AnnaBridge	172:65be27845400	1046	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
AnnaBridge	172:65be27845400	1047	* @{
AnnaBridge	172:65be27845400	1048	*/
AnnaBridge	172:65be27845400	1049	#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /!< TIMx_BKIN input /
AnnaBridge	172:65be27845400	1050	#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /!< TIMx_BKIN2 input /
AnnaBridge	172:65be27845400	1051	/**
AnnaBridge	172:65be27845400	1052	* @}
AnnaBridge	172:65be27845400	1053	*/
AnnaBridge	172:65be27845400	1054
AnnaBridge	172:65be27845400	1055	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
AnnaBridge	172:65be27845400	1056	* @{
AnnaBridge	172:65be27845400	1057	*/
AnnaBridge	172:65be27845400	1058	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /!< BKIN input from AF controller /
AnnaBridge	172:65be27845400	1059	#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /!< internal signal: COMP1 output /
AnnaBridge	172:65be27845400	1060	#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /!< internal signal: COMP2 output /
AnnaBridge	172:65be27845400	1061	#define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /!< internal signal: DFSDM1 break output /
AnnaBridge	172:65be27845400	1062	/**
AnnaBridge	172:65be27845400	1063	* @}
AnnaBridge	172:65be27845400	1064	*/
AnnaBridge	172:65be27845400	1065
AnnaBridge	172:65be27845400	1066	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
AnnaBridge	172:65be27845400	1067	* @{
AnnaBridge	172:65be27845400	1068	*/
AnnaBridge	172:65be27845400	1069	#define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /!< BRK BKIN input is active low /
AnnaBridge	172:65be27845400	1070	#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /!< BRK BKIN input is active high /
AnnaBridge	172:65be27845400	1071	/**
AnnaBridge	172:65be27845400	1072	* @}
AnnaBridge	172:65be27845400	1073	*/
AnnaBridge	172:65be27845400	1074
AnnaBridge	172:65be27845400	1075	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	172:65be27845400	1076	* @{
AnnaBridge	172:65be27845400	1077	*/
AnnaBridge	172:65be27845400	1078	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1079	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1080	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1081	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1082	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1083	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1084	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1085	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1086	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1087	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1088	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1089	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1090	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1091	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1092	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1093	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1094	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1095	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1096	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1097	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1098	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1099	#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR1 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1100	#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_OR2 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1101	#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_OR3 register is the DMA base address for DMA burst /
AnnaBridge	172:65be27845400	1102	/**
AnnaBridge	172:65be27845400	1103	* @}
AnnaBridge	172:65be27845400	1104	*/
AnnaBridge	172:65be27845400	1105
AnnaBridge	172:65be27845400	1106	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	172:65be27845400	1107	* @{
AnnaBridge	172:65be27845400	1108	*/
AnnaBridge	172:65be27845400	1109	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1110	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1111	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1112	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1113	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1114	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1115	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1116	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1117	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1118	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1119	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1120	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1121	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1122	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1123	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1124	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1125	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1126	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	172:65be27845400	1127	/**
AnnaBridge	172:65be27845400	1128	* @}
AnnaBridge	172:65be27845400	1129	*/
AnnaBridge	172:65be27845400	1130
AnnaBridge	172:65be27845400	1131	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap
AnnaBridge	172:65be27845400	1132	* @{
AnnaBridge	172:65be27845400	1133	*/
AnnaBridge	172:65be27845400	1134	#define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /!< TIM1_ETR is not connected to ADC1 analog watchdog x /
AnnaBridge	172:65be27845400	1135	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 1 /
AnnaBridge	172:65be27845400	1136	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 2 /
AnnaBridge	172:65be27845400	1137	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 3 /
AnnaBridge	172:65be27845400	1138	/**
AnnaBridge	172:65be27845400	1139	* @}
AnnaBridge	172:65be27845400	1140	*/
AnnaBridge	172:65be27845400	1141
AnnaBridge	172:65be27845400	1142	#if defined(ADC3)
AnnaBridge	172:65be27845400	1143	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap
AnnaBridge	172:65be27845400	1144	* @{
AnnaBridge	172:65be27845400	1145	*/
AnnaBridge	172:65be27845400	1146	#define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /!< TIM1_ETR is not connected to ADC3 analog watchdog x/
AnnaBridge	172:65be27845400	1147	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 1 /
AnnaBridge	172:65be27845400	1148	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 2 /
AnnaBridge	172:65be27845400	1149	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 3 /
AnnaBridge	172:65be27845400	1150	/**
AnnaBridge	172:65be27845400	1151	* @}
AnnaBridge	172:65be27845400	1152	*/
AnnaBridge	172:65be27845400	1153	#endif /* ADC3 */
AnnaBridge	172:65be27845400	1154
AnnaBridge	172:65be27845400	1155	/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
AnnaBridge	172:65be27845400	1156	* @{
AnnaBridge	172:65be27845400	1157	*/
AnnaBridge	172:65be27845400	1158	#define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /!< TIM1 input capture 1 is connected to GPIO /
AnnaBridge	172:65be27845400	1159	#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1 input capture 1 is connected to COMP1 output /
AnnaBridge	172:65be27845400	1160	/**
AnnaBridge	172:65be27845400	1161	* @}
AnnaBridge	172:65be27845400	1162	*/
AnnaBridge	172:65be27845400	1163
AnnaBridge	172:65be27845400	1164	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
AnnaBridge	172:65be27845400	1165	* @{
AnnaBridge	172:65be27845400	1166	*/
AnnaBridge	172:65be27845400	1167	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1168	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /!< TIM2_ITR1 is connected to TIM8_TRGO /
AnnaBridge	172:65be27845400	1169	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
AnnaBridge	172:65be27845400	1170	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| */
AnnaBridge	172:65be27845400	1171	/* STM32L496xx \|\| STM32L4A6xx \|\| */
AnnaBridge	172:65be27845400	1172	/* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1173	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx)
AnnaBridge	172:65be27845400	1174	#define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */
AnnaBridge	172:65be27845400	1175	#define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */
AnnaBridge	172:65be27845400	1176	#endif /* STM32L431xx \|\| STM32L432xx \|\| STM32L442xx \|\| STM32L433xx \|\| STM32L443xx \|\| */
AnnaBridge	172:65be27845400	1177	/* STM32L451xx \|\| STM32L452xx \|\| STM32L462xx */
AnnaBridge	172:65be27845400	1178	#define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /!< TIM2_ETR is connected to GPIO /
AnnaBridge	172:65be27845400	1179	#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ETR is connected to LSE /
AnnaBridge	172:65be27845400	1180	/**
AnnaBridge	172:65be27845400	1181	* @}
AnnaBridge	172:65be27845400	1182	*/
AnnaBridge	172:65be27845400	1183
AnnaBridge	172:65be27845400	1184	/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
AnnaBridge	172:65be27845400	1185	* @{
AnnaBridge	172:65be27845400	1186	*/
AnnaBridge	172:65be27845400	1187	#define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /!< TIM2 input capture 4 is connected to GPIO /
AnnaBridge	172:65be27845400	1188	#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP1_OUT /
AnnaBridge	172:65be27845400	1189	#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP2_OUT /
AnnaBridge	172:65be27845400	1190	#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT /
AnnaBridge	172:65be27845400	1191	/**
AnnaBridge	172:65be27845400	1192	* @}
AnnaBridge	172:65be27845400	1193	*/
AnnaBridge	172:65be27845400	1194
AnnaBridge	172:65be27845400	1195	#if defined(TIM3)
AnnaBridge	172:65be27845400	1196	/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
AnnaBridge	172:65be27845400	1197	* @{
AnnaBridge	172:65be27845400	1198	*/
AnnaBridge	172:65be27845400	1199	#define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /!< TIM3 input capture 1 is connected to GPIO /
AnnaBridge	172:65be27845400	1200	#define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP1_OUT /
AnnaBridge	172:65be27845400	1201	#define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP2_OUT /
AnnaBridge	172:65be27845400	1202	#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT /
AnnaBridge	172:65be27845400	1203	/**
AnnaBridge	172:65be27845400	1204	* @}
AnnaBridge	172:65be27845400	1205	*/
AnnaBridge	172:65be27845400	1206	#endif /* TIM3 */
AnnaBridge	172:65be27845400	1207
AnnaBridge	172:65be27845400	1208	#if defined(TIM8)
AnnaBridge	172:65be27845400	1209	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap
AnnaBridge	172:65be27845400	1210	* @{
AnnaBridge	172:65be27845400	1211	*/
AnnaBridge	172:65be27845400	1212	#define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /!< TIM8_ETR is not connected to ADC2 analog watchdog x /
AnnaBridge	172:65be27845400	1213	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog /
AnnaBridge	172:65be27845400	1214	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 2 /
AnnaBridge	172:65be27845400	1215	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 3 /
AnnaBridge	172:65be27845400	1216	/**
AnnaBridge	172:65be27845400	1217	* @}
AnnaBridge	172:65be27845400	1218	*/
AnnaBridge	172:65be27845400	1219
AnnaBridge	172:65be27845400	1220	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap
AnnaBridge	172:65be27845400	1221	* @{
AnnaBridge	172:65be27845400	1222	*/
AnnaBridge	172:65be27845400	1223	#define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /!< TIM8_ETR is not connected to ADC3 analog watchdog x /
AnnaBridge	172:65be27845400	1224	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 1 /
AnnaBridge	172:65be27845400	1225	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 2 /
AnnaBridge	172:65be27845400	1226	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 3 /
AnnaBridge	172:65be27845400	1227	/**
AnnaBridge	172:65be27845400	1228	* @}
AnnaBridge	172:65be27845400	1229	*/
AnnaBridge	172:65be27845400	1230
AnnaBridge	172:65be27845400	1231	/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap
AnnaBridge	172:65be27845400	1232	* @{
AnnaBridge	172:65be27845400	1233	*/
AnnaBridge	172:65be27845400	1234	#define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /!< TIM8 input capture 1 is connected to GPIO /
AnnaBridge	172:65be27845400	1235	#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8 input capture 1 is connected to COMP2 output /
AnnaBridge	172:65be27845400	1236	/**
AnnaBridge	172:65be27845400	1237	* @}
AnnaBridge	172:65be27845400	1238	*/
AnnaBridge	172:65be27845400	1239	#endif /* TIM8 */
AnnaBridge	172:65be27845400	1240
AnnaBridge	172:65be27845400	1241	/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
AnnaBridge	172:65be27845400	1242	* @{
AnnaBridge	172:65be27845400	1243	*/
AnnaBridge	172:65be27845400	1244	#define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /!< TIM15 input capture 1 is connected to GPIO /
AnnaBridge	172:65be27845400	1245	#define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP \| TIM15_OR1_RMP_MASK) /!< TIM15 input capture 1 is connected to LSE /
AnnaBridge	172:65be27845400	1246	/**
AnnaBridge	172:65be27845400	1247	* @}
AnnaBridge	172:65be27845400	1248	*/
AnnaBridge	172:65be27845400	1249
AnnaBridge	172:65be27845400	1250	/** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
AnnaBridge	172:65be27845400	1251	* @{
AnnaBridge	172:65be27845400	1252	*/
AnnaBridge	172:65be27845400	1253	#define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /!< No redirection/
AnnaBridge	172:65be27845400	1254	#define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 \| TIM15_OR1_RMP_MASK) /!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
AnnaBridge	172:65be27845400	1255	#define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 \| TIM15_OR1_RMP_MASK) /!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y/
AnnaBridge	172:65be27845400	1256	#define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE \| TIM15_OR1_RMP_MASK) /!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
AnnaBridge	172:65be27845400	1257	/**
AnnaBridge	172:65be27845400	1258	* @}
AnnaBridge	172:65be27845400	1259	*/
AnnaBridge	172:65be27845400	1260
AnnaBridge	172:65be27845400	1261	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
AnnaBridge	172:65be27845400	1262	* @{
AnnaBridge	172:65be27845400	1263	*/
AnnaBridge	172:65be27845400	1264	#define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /!< TIM16 input capture 1 is connected to GPIO /
AnnaBridge	172:65be27845400	1265	#define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSI /
AnnaBridge	172:65be27845400	1266	#define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSE /
AnnaBridge	172:65be27845400	1267	#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to RTC wakeup interrupt /
AnnaBridge	172:65be27845400	1268	#if defined TIM16_OR1_TI1_RMP_2
AnnaBridge	172:65be27845400	1269	#define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to MSI /
AnnaBridge	172:65be27845400	1270	#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to HSE/32 /
AnnaBridge	172:65be27845400	1271	#define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 \| TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to MCO /
AnnaBridge	172:65be27845400	1272	#endif
AnnaBridge	172:65be27845400	1273	/**
AnnaBridge	172:65be27845400	1274	* @}
AnnaBridge	172:65be27845400	1275	*/
AnnaBridge	172:65be27845400	1276
AnnaBridge	172:65be27845400	1277	#if defined(TIM17)
AnnaBridge	172:65be27845400	1278	/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
AnnaBridge	172:65be27845400	1279	* @{
AnnaBridge	172:65be27845400	1280	*/
AnnaBridge	172:65be27845400	1281	#define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /!< TIM17 input capture 1 is connected to GPIO /
AnnaBridge	172:65be27845400	1282	#define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MSI /
AnnaBridge	172:65be27845400	1283	#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to HSE/32 /
AnnaBridge	172:65be27845400	1284	#define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MCO /
AnnaBridge	172:65be27845400	1285	/**
AnnaBridge	172:65be27845400	1286	* @}
AnnaBridge	172:65be27845400	1287	*/
AnnaBridge	172:65be27845400	1288	#endif /* TIM17 */
AnnaBridge	172:65be27845400	1289
AnnaBridge	172:65be27845400	1290	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
AnnaBridge	172:65be27845400	1291	* @{
AnnaBridge	172:65be27845400	1292	*/
AnnaBridge	172:65be27845400	1293	#define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /!< OCREF_CLR_INT is not connected /
AnnaBridge	172:65be27845400	1294	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
AnnaBridge	172:65be27845400	1295	/**
AnnaBridge	172:65be27845400	1296	* @}
AnnaBridge	172:65be27845400	1297	*/
AnnaBridge	172:65be27845400	1298
AnnaBridge	172:65be27845400	1299	/** Legacy definitions for compatibility purpose
AnnaBridge	172:65be27845400	1300	@cond 0
AnnaBridge	172:65be27845400	1301	*/
AnnaBridge	172:65be27845400	1302	#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	172:65be27845400	1303	/**
AnnaBridge	172:65be27845400	1304	@endcond
AnnaBridge	172:65be27845400	1305	*/
AnnaBridge	172:65be27845400	1306	/**
AnnaBridge	172:65be27845400	1307	* @}
AnnaBridge	172:65be27845400	1308	*/
AnnaBridge	172:65be27845400	1309
AnnaBridge	172:65be27845400	1310	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1311	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	172:65be27845400	1312	* @{
AnnaBridge	172:65be27845400	1313	*/
AnnaBridge	172:65be27845400	1314
AnnaBridge	172:65be27845400	1315	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	172:65be27845400	1316	* @{
AnnaBridge	172:65be27845400	1317	*/
AnnaBridge	172:65be27845400	1318	/**
AnnaBridge	172:65be27845400	1319	* @brief Write a value in TIM register.
AnnaBridge	172:65be27845400	1320	* @param __INSTANCE__ TIM Instance
AnnaBridge	172:65be27845400	1321	* @param __REG__ Register to be written
AnnaBridge	172:65be27845400	1322	* @param __VALUE__ Value to be written in the register
AnnaBridge	172:65be27845400	1323	* @retval None
AnnaBridge	172:65be27845400	1324	*/
AnnaBridge	172:65be27845400	1325	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	172:65be27845400	1326
AnnaBridge	172:65be27845400	1327	/**
AnnaBridge	172:65be27845400	1328	* @brief Read a value in TIM register.
AnnaBridge	172:65be27845400	1329	* @param __INSTANCE__ TIM Instance
AnnaBridge	172:65be27845400	1330	* @param __REG__ Register to be read
AnnaBridge	172:65be27845400	1331	* @retval Register value
AnnaBridge	172:65be27845400	1332	*/
AnnaBridge	172:65be27845400	1333	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	172:65be27845400	1334	/**
AnnaBridge	172:65be27845400	1335	* @}
AnnaBridge	172:65be27845400	1336	*/
AnnaBridge	172:65be27845400	1337
AnnaBridge	172:65be27845400	1338	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	172:65be27845400	1339	* @{
AnnaBridge	172:65be27845400	1340	*/
AnnaBridge	172:65be27845400	1341
AnnaBridge	172:65be27845400	1342	/**
AnnaBridge	172:65be27845400	1343	* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
AnnaBridge	172:65be27845400	1344	* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
AnnaBridge	172:65be27845400	1345	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
AnnaBridge	172:65be27845400	1346	* to TIMx_CNT register bit 31)
AnnaBridge	172:65be27845400	1347	* @param __CNT__ Counter value
AnnaBridge	172:65be27845400	1348	* @retval UIF status bit
AnnaBridge	172:65be27845400	1349	*/
AnnaBridge	172:65be27845400	1350	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
AnnaBridge	172:65be27845400	1351	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
AnnaBridge	172:65be27845400	1352
AnnaBridge	172:65be27845400	1353	/**
AnnaBridge	172:65be27845400	1354	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	172:65be27845400	1355	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	172:65be27845400	1356	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1357	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1358	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	1359	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	1360	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	1361	* @param __DT__ deadtime duration (in ns)
AnnaBridge	172:65be27845400	1362	* @retval DTG[0:7]
AnnaBridge	172:65be27845400	1363	*/
AnnaBridge	172:65be27845400	1364	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	172:65be27845400	1365	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	172:65be27845400	1366	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
AnnaBridge	172:65be27845400	1367	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
AnnaBridge	172:65be27845400	1368	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
AnnaBridge	172:65be27845400	1369	0U)
AnnaBridge	172:65be27845400	1370
AnnaBridge	172:65be27845400	1371	/**
AnnaBridge	172:65be27845400	1372	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	172:65be27845400	1373	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	172:65be27845400	1374	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1375	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	172:65be27845400	1376	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1377	*/
AnnaBridge	172:65be27845400	1378	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	172:65be27845400	1379	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	172:65be27845400	1380
AnnaBridge	172:65be27845400	1381	/**
AnnaBridge	172:65be27845400	1382	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	172:65be27845400	1383	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	172:65be27845400	1384	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1385	* @param __PSC__ prescaler
AnnaBridge	172:65be27845400	1386	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	172:65be27845400	1387	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1388	*/
AnnaBridge	172:65be27845400	1389	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	172:65be27845400	1390	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	172:65be27845400	1391
AnnaBridge	172:65be27845400	1392	/**
AnnaBridge	172:65be27845400	1393	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	172:65be27845400	1394	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	172:65be27845400	1395	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1396	* @param __PSC__ prescaler
AnnaBridge	172:65be27845400	1397	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	172:65be27845400	1398	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1399	*/
AnnaBridge	172:65be27845400	1400	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	172:65be27845400	1401	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	172:65be27845400	1402	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	172:65be27845400	1403
AnnaBridge	172:65be27845400	1404	/**
AnnaBridge	172:65be27845400	1405	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	172:65be27845400	1406	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	172:65be27845400	1407	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	172:65be27845400	1408	* @param __PSC__ prescaler
AnnaBridge	172:65be27845400	1409	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	172:65be27845400	1410	* @param __PULSE__ pulse duration (in us)
AnnaBridge	172:65be27845400	1411	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	1412	*/
AnnaBridge	172:65be27845400	1413	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	172:65be27845400	1414	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	172:65be27845400	1415	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	172:65be27845400	1416
AnnaBridge	172:65be27845400	1417	/**
AnnaBridge	172:65be27845400	1418	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	172:65be27845400	1419	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	172:65be27845400	1420	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1421	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	172:65be27845400	1422	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	172:65be27845400	1423	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	172:65be27845400	1424	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	1425	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	172:65be27845400	1426	*/
AnnaBridge	172:65be27845400	1427	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	172:65be27845400	1428	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	172:65be27845400	1429
AnnaBridge	172:65be27845400	1430
AnnaBridge	172:65be27845400	1431	/**
AnnaBridge	172:65be27845400	1432	* @}
AnnaBridge	172:65be27845400	1433	*/
AnnaBridge	172:65be27845400	1434
AnnaBridge	172:65be27845400	1435
AnnaBridge	172:65be27845400	1436	/**
AnnaBridge	172:65be27845400	1437	* @}
AnnaBridge	172:65be27845400	1438	*/
AnnaBridge	172:65be27845400	1439
AnnaBridge	172:65be27845400	1440	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	1441	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	172:65be27845400	1442	* @{
AnnaBridge	172:65be27845400	1443	*/
AnnaBridge	172:65be27845400	1444
AnnaBridge	172:65be27845400	1445	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	172:65be27845400	1446	* @{
AnnaBridge	172:65be27845400	1447	*/
AnnaBridge	172:65be27845400	1448	/**
AnnaBridge	172:65be27845400	1449	* @brief Enable timer counter.
AnnaBridge	172:65be27845400	1450	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	172:65be27845400	1451	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1452	* @retval None
AnnaBridge	172:65be27845400	1453	*/
AnnaBridge	172:65be27845400	1454	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1455	{
AnnaBridge	172:65be27845400	1456	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	172:65be27845400	1457	}
AnnaBridge	172:65be27845400	1458
AnnaBridge	172:65be27845400	1459	/**
AnnaBridge	172:65be27845400	1460	* @brief Disable timer counter.
AnnaBridge	172:65be27845400	1461	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	172:65be27845400	1462	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1463	* @retval None
AnnaBridge	172:65be27845400	1464	*/
AnnaBridge	172:65be27845400	1465	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1466	{
AnnaBridge	172:65be27845400	1467	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	172:65be27845400	1468	}
AnnaBridge	172:65be27845400	1469
AnnaBridge	172:65be27845400	1470	/**
AnnaBridge	172:65be27845400	1471	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	172:65be27845400	1472	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	172:65be27845400	1473	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1474	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1475	*/
AnnaBridge	172:65be27845400	1476	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1477	{
AnnaBridge	172:65be27845400	1478	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	172:65be27845400	1479	}
AnnaBridge	172:65be27845400	1480
AnnaBridge	172:65be27845400	1481	/**
AnnaBridge	172:65be27845400	1482	* @brief Enable update event generation.
AnnaBridge	172:65be27845400	1483	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	172:65be27845400	1484	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1485	* @retval None
AnnaBridge	172:65be27845400	1486	*/
AnnaBridge	172:65be27845400	1487	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1488	{
AnnaBridge	172:65be27845400	1489	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	172:65be27845400	1490	}
AnnaBridge	172:65be27845400	1491
AnnaBridge	172:65be27845400	1492	/**
AnnaBridge	172:65be27845400	1493	* @brief Disable update event generation.
AnnaBridge	172:65be27845400	1494	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	172:65be27845400	1495	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1496	* @retval None
AnnaBridge	172:65be27845400	1497	*/
AnnaBridge	172:65be27845400	1498	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1499	{
AnnaBridge	172:65be27845400	1500	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	172:65be27845400	1501	}
AnnaBridge	172:65be27845400	1502
AnnaBridge	172:65be27845400	1503	/**
AnnaBridge	172:65be27845400	1504	* @brief Indicates whether update event generation is enabled.
AnnaBridge	172:65be27845400	1505	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	172:65be27845400	1506	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1507	* @retval Inverted state of bit (0 or 1).
AnnaBridge	172:65be27845400	1508	*/
AnnaBridge	172:65be27845400	1509	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1510	{
AnnaBridge	172:65be27845400	1511	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
AnnaBridge	172:65be27845400	1512	}
AnnaBridge	172:65be27845400	1513
AnnaBridge	172:65be27845400	1514	/**
AnnaBridge	172:65be27845400	1515	* @brief Set update event source
AnnaBridge	172:65be27845400	1516	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	172:65be27845400	1517	* generate an update interrupt or DMA request if enabled:
AnnaBridge	172:65be27845400	1518	* - Counter overflow/underflow
AnnaBridge	172:65be27845400	1519	* - Setting the UG bit
AnnaBridge	172:65be27845400	1520	* - Update generation through the slave mode controller
AnnaBridge	172:65be27845400	1521	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	172:65be27845400	1522	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	172:65be27845400	1523	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	172:65be27845400	1524	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1525	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1526	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	172:65be27845400	1527	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	172:65be27845400	1528	* @retval None
AnnaBridge	172:65be27845400	1529	*/
AnnaBridge	172:65be27845400	1530	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	172:65be27845400	1531	{
AnnaBridge	172:65be27845400	1532	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	172:65be27845400	1533	}
AnnaBridge	172:65be27845400	1534
AnnaBridge	172:65be27845400	1535	/**
AnnaBridge	172:65be27845400	1536	* @brief Get actual event update source
AnnaBridge	172:65be27845400	1537	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	172:65be27845400	1538	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1539	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1540	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	172:65be27845400	1541	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	172:65be27845400	1542	*/
AnnaBridge	172:65be27845400	1543	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1544	{
AnnaBridge	172:65be27845400	1545	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	172:65be27845400	1546	}
AnnaBridge	172:65be27845400	1547
AnnaBridge	172:65be27845400	1548	/**
AnnaBridge	172:65be27845400	1549	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	172:65be27845400	1550	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	172:65be27845400	1551	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1552	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1553	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	172:65be27845400	1554	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	172:65be27845400	1555	* @retval None
AnnaBridge	172:65be27845400	1556	*/
AnnaBridge	172:65be27845400	1557	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	172:65be27845400	1558	{
AnnaBridge	172:65be27845400	1559	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	172:65be27845400	1560	}
AnnaBridge	172:65be27845400	1561
AnnaBridge	172:65be27845400	1562	/**
AnnaBridge	172:65be27845400	1563	* @brief Get actual one pulse mode.
AnnaBridge	172:65be27845400	1564	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	172:65be27845400	1565	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1566	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1567	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	172:65be27845400	1568	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	172:65be27845400	1569	*/
AnnaBridge	172:65be27845400	1570	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1571	{
AnnaBridge	172:65be27845400	1572	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	172:65be27845400	1573	}
AnnaBridge	172:65be27845400	1574
AnnaBridge	172:65be27845400	1575	/**
AnnaBridge	172:65be27845400	1576	* @brief Set the timer counter counting mode.
AnnaBridge	172:65be27845400	1577	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	172:65be27845400	1578	* check whether or not the counter mode selection feature is supported
AnnaBridge	172:65be27845400	1579	* by a timer instance.
AnnaBridge	172:65be27845400	1580	* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
AnnaBridge	172:65be27845400	1581	* requires a timer reset to avoid unexpected direction
AnnaBridge	172:65be27845400	1582	* due to DIR bit readonly in center aligned mode.
AnnaBridge	172:65be27845400	1583	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	172:65be27845400	1584	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	172:65be27845400	1585	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1586	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1587	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	172:65be27845400	1588	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	172:65be27845400	1589	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	172:65be27845400	1590	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	172:65be27845400	1591	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	172:65be27845400	1592	* @retval None
AnnaBridge	172:65be27845400	1593	*/
AnnaBridge	172:65be27845400	1594	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	172:65be27845400	1595	{
AnnaBridge	172:65be27845400	1596	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	172:65be27845400	1597	}
AnnaBridge	172:65be27845400	1598
AnnaBridge	172:65be27845400	1599	/**
AnnaBridge	172:65be27845400	1600	* @brief Get actual counter mode.
AnnaBridge	172:65be27845400	1601	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	172:65be27845400	1602	* check whether or not the counter mode selection feature is supported
AnnaBridge	172:65be27845400	1603	* by a timer instance.
AnnaBridge	172:65be27845400	1604	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	172:65be27845400	1605	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	172:65be27845400	1606	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1607	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1608	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	172:65be27845400	1609	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	172:65be27845400	1610	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	172:65be27845400	1611	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	172:65be27845400	1612	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	172:65be27845400	1613	*/
AnnaBridge	172:65be27845400	1614	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1615	{
AnnaBridge	172:65be27845400	1616	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	172:65be27845400	1617	}
AnnaBridge	172:65be27845400	1618
AnnaBridge	172:65be27845400	1619	/**
AnnaBridge	172:65be27845400	1620	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	172:65be27845400	1621	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	172:65be27845400	1622	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1623	* @retval None
AnnaBridge	172:65be27845400	1624	*/
AnnaBridge	172:65be27845400	1625	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1626	{
AnnaBridge	172:65be27845400	1627	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	172:65be27845400	1628	}
AnnaBridge	172:65be27845400	1629
AnnaBridge	172:65be27845400	1630	/**
AnnaBridge	172:65be27845400	1631	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	172:65be27845400	1632	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	172:65be27845400	1633	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1634	* @retval None
AnnaBridge	172:65be27845400	1635	*/
AnnaBridge	172:65be27845400	1636	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1637	{
AnnaBridge	172:65be27845400	1638	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	172:65be27845400	1639	}
AnnaBridge	172:65be27845400	1640
AnnaBridge	172:65be27845400	1641	/**
AnnaBridge	172:65be27845400	1642	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	172:65be27845400	1643	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	172:65be27845400	1644	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1645	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	1646	*/
AnnaBridge	172:65be27845400	1647	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1648	{
AnnaBridge	172:65be27845400	1649	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	172:65be27845400	1650	}
AnnaBridge	172:65be27845400	1651
AnnaBridge	172:65be27845400	1652	/**
AnnaBridge	172:65be27845400	1653	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	172:65be27845400	1654	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1655	* whether or not the clock division feature is supported by the timer
AnnaBridge	172:65be27845400	1656	* instance.
AnnaBridge	172:65be27845400	1657	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	172:65be27845400	1658	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1659	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1660	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	1661	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	1662	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	1663	* @retval None
AnnaBridge	172:65be27845400	1664	*/
AnnaBridge	172:65be27845400	1665	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	172:65be27845400	1666	{
AnnaBridge	172:65be27845400	1667	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	172:65be27845400	1668	}
AnnaBridge	172:65be27845400	1669
AnnaBridge	172:65be27845400	1670	/**
AnnaBridge	172:65be27845400	1671	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	172:65be27845400	1672	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1673	* whether or not the clock division feature is supported by the timer
AnnaBridge	172:65be27845400	1674	* instance.
AnnaBridge	172:65be27845400	1675	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	172:65be27845400	1676	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1677	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1678	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	172:65be27845400	1679	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	172:65be27845400	1680	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	172:65be27845400	1681	*/
AnnaBridge	172:65be27845400	1682	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1683	{
AnnaBridge	172:65be27845400	1684	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	172:65be27845400	1685	}
AnnaBridge	172:65be27845400	1686
AnnaBridge	172:65be27845400	1687	/**
AnnaBridge	172:65be27845400	1688	* @brief Set the counter value.
AnnaBridge	172:65be27845400	1689	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1690	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1691	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	172:65be27845400	1692	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1693	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	172:65be27845400	1694	* @retval None
AnnaBridge	172:65be27845400	1695	*/
AnnaBridge	172:65be27845400	1696	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	172:65be27845400	1697	{
AnnaBridge	172:65be27845400	1698	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	172:65be27845400	1699	}
AnnaBridge	172:65be27845400	1700
AnnaBridge	172:65be27845400	1701	/**
AnnaBridge	172:65be27845400	1702	* @brief Get the counter value.
AnnaBridge	172:65be27845400	1703	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1704	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1705	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	172:65be27845400	1706	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1707	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	172:65be27845400	1708	*/
AnnaBridge	172:65be27845400	1709	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1710	{
AnnaBridge	172:65be27845400	1711	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	172:65be27845400	1712	}
AnnaBridge	172:65be27845400	1713
AnnaBridge	172:65be27845400	1714	/**
AnnaBridge	172:65be27845400	1715	* @brief Get the current direction of the counter
AnnaBridge	172:65be27845400	1716	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	172:65be27845400	1717	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1718	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1719	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	172:65be27845400	1720	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	172:65be27845400	1721	*/
AnnaBridge	172:65be27845400	1722	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1723	{
AnnaBridge	172:65be27845400	1724	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	172:65be27845400	1725	}
AnnaBridge	172:65be27845400	1726
AnnaBridge	172:65be27845400	1727	/**
AnnaBridge	172:65be27845400	1728	* @brief Set the prescaler value.
AnnaBridge	172:65be27845400	1729	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	172:65be27845400	1730	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	172:65be27845400	1731	* prescaler ratio is taken into account at the next update event.
AnnaBridge	172:65be27845400	1732	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	172:65be27845400	1733	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	172:65be27845400	1734	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1735	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	1736	* @retval None
AnnaBridge	172:65be27845400	1737	*/
AnnaBridge	172:65be27845400	1738	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	172:65be27845400	1739	{
AnnaBridge	172:65be27845400	1740	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	172:65be27845400	1741	}
AnnaBridge	172:65be27845400	1742
AnnaBridge	172:65be27845400	1743	/**
AnnaBridge	172:65be27845400	1744	* @brief Get the prescaler value.
AnnaBridge	172:65be27845400	1745	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	172:65be27845400	1746	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1747	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	1748	*/
AnnaBridge	172:65be27845400	1749	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1750	{
AnnaBridge	172:65be27845400	1751	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	172:65be27845400	1752	}
AnnaBridge	172:65be27845400	1753
AnnaBridge	172:65be27845400	1754	/**
AnnaBridge	172:65be27845400	1755	* @brief Set the auto-reload value.
AnnaBridge	172:65be27845400	1756	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	172:65be27845400	1757	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1758	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1759	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	172:65be27845400	1760	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	172:65be27845400	1761	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1762	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	1763	* @retval None
AnnaBridge	172:65be27845400	1764	*/
AnnaBridge	172:65be27845400	1765	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	172:65be27845400	1766	{
AnnaBridge	172:65be27845400	1767	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	172:65be27845400	1768	}
AnnaBridge	172:65be27845400	1769
AnnaBridge	172:65be27845400	1770	/**
AnnaBridge	172:65be27845400	1771	* @brief Get the auto-reload value.
AnnaBridge	172:65be27845400	1772	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	172:65be27845400	1773	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1774	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	1775	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1776	* @retval Auto-reload value
AnnaBridge	172:65be27845400	1777	*/
AnnaBridge	172:65be27845400	1778	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1779	{
AnnaBridge	172:65be27845400	1780	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	172:65be27845400	1781	}
AnnaBridge	172:65be27845400	1782
AnnaBridge	172:65be27845400	1783	/**
AnnaBridge	172:65be27845400	1784	* @brief Set the repetition counter value.
AnnaBridge	172:65be27845400	1785	* @note For advanced timer instances RepetitionCounter can be up to 65535.
AnnaBridge	172:65be27845400	1786	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1787	* whether or not a timer instance supports a repetition counter.
AnnaBridge	172:65be27845400	1788	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	172:65be27845400	1789	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1790	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	172:65be27845400	1791	* @retval None
AnnaBridge	172:65be27845400	1792	*/
AnnaBridge	172:65be27845400	1793	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	172:65be27845400	1794	{
AnnaBridge	172:65be27845400	1795	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	172:65be27845400	1796	}
AnnaBridge	172:65be27845400	1797
AnnaBridge	172:65be27845400	1798	/**
AnnaBridge	172:65be27845400	1799	* @brief Get the repetition counter value.
AnnaBridge	172:65be27845400	1800	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1801	* whether or not a timer instance supports a repetition counter.
AnnaBridge	172:65be27845400	1802	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	172:65be27845400	1803	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1804	* @retval Repetition counter value
AnnaBridge	172:65be27845400	1805	*/
AnnaBridge	172:65be27845400	1806	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1807	{
AnnaBridge	172:65be27845400	1808	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	172:65be27845400	1809	}
AnnaBridge	172:65be27845400	1810
AnnaBridge	172:65be27845400	1811	/**
AnnaBridge	172:65be27845400	1812	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
AnnaBridge	172:65be27845400	1813	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
AnnaBridge	172:65be27845400	1814	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
AnnaBridge	172:65be27845400	1815	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1816	* @retval None
AnnaBridge	172:65be27845400	1817	*/
AnnaBridge	172:65be27845400	1818	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1819	{
AnnaBridge	172:65be27845400	1820	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	172:65be27845400	1821	}
AnnaBridge	172:65be27845400	1822
AnnaBridge	172:65be27845400	1823	/**
AnnaBridge	172:65be27845400	1824	* @brief Disable update interrupt flag (UIF) remapping.
AnnaBridge	172:65be27845400	1825	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
AnnaBridge	172:65be27845400	1826	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1827	* @retval None
AnnaBridge	172:65be27845400	1828	*/
AnnaBridge	172:65be27845400	1829	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1830	{
AnnaBridge	172:65be27845400	1831	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
AnnaBridge	172:65be27845400	1832	}
AnnaBridge	172:65be27845400	1833
AnnaBridge	172:65be27845400	1834	/**
AnnaBridge	172:65be27845400	1835	* @}
AnnaBridge	172:65be27845400	1836	*/
AnnaBridge	172:65be27845400	1837
AnnaBridge	172:65be27845400	1838	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	172:65be27845400	1839	* @{
AnnaBridge	172:65be27845400	1840	*/
AnnaBridge	172:65be27845400	1841	/**
AnnaBridge	172:65be27845400	1842	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	172:65be27845400	1843	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	172:65be27845400	1844	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	172:65be27845400	1845	* @note Only on channels that have a complementary output.
AnnaBridge	172:65be27845400	1846	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1847	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	172:65be27845400	1848	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	172:65be27845400	1849	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1850	* @retval None
AnnaBridge	172:65be27845400	1851	*/
AnnaBridge	172:65be27845400	1852	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1853	{
AnnaBridge	172:65be27845400	1854	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	172:65be27845400	1855	}
AnnaBridge	172:65be27845400	1856
AnnaBridge	172:65be27845400	1857	/**
AnnaBridge	172:65be27845400	1858	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	172:65be27845400	1859	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1860	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	172:65be27845400	1861	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	172:65be27845400	1862	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1863	* @retval None
AnnaBridge	172:65be27845400	1864	*/
AnnaBridge	172:65be27845400	1865	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1866	{
AnnaBridge	172:65be27845400	1867	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	172:65be27845400	1868	}
AnnaBridge	172:65be27845400	1869
AnnaBridge	172:65be27845400	1870	/**
AnnaBridge	172:65be27845400	1871	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	172:65be27845400	1872	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	1873	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	172:65be27845400	1874	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	172:65be27845400	1875	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1876	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1877	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	172:65be27845400	1878	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	172:65be27845400	1879	* @retval None
AnnaBridge	172:65be27845400	1880	*/
AnnaBridge	172:65be27845400	1881	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	172:65be27845400	1882	{
AnnaBridge	172:65be27845400	1883	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	172:65be27845400	1884	}
AnnaBridge	172:65be27845400	1885
AnnaBridge	172:65be27845400	1886	/**
AnnaBridge	172:65be27845400	1887	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	172:65be27845400	1888	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	172:65be27845400	1889	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1890	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1891	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	172:65be27845400	1892	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	172:65be27845400	1893	* @retval None
AnnaBridge	172:65be27845400	1894	*/
AnnaBridge	172:65be27845400	1895	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	172:65be27845400	1896	{
AnnaBridge	172:65be27845400	1897	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	172:65be27845400	1898	}
AnnaBridge	172:65be27845400	1899
AnnaBridge	172:65be27845400	1900	/**
AnnaBridge	172:65be27845400	1901	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	172:65be27845400	1902	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	172:65be27845400	1903	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1904	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	1905	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	172:65be27845400	1906	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	172:65be27845400	1907	*/
AnnaBridge	172:65be27845400	1908	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	1909	{
AnnaBridge	172:65be27845400	1910	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	172:65be27845400	1911	}
AnnaBridge	172:65be27845400	1912
AnnaBridge	172:65be27845400	1913	/**
AnnaBridge	172:65be27845400	1914	* @brief Set the lock level to freeze the
AnnaBridge	172:65be27845400	1915	* configuration of several capture/compare parameters.
AnnaBridge	172:65be27845400	1916	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	1917	* the lock mechanism is supported by a timer instance.
AnnaBridge	172:65be27845400	1918	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	172:65be27845400	1919	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1920	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1921	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	172:65be27845400	1922	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	172:65be27845400	1923	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	172:65be27845400	1924	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	172:65be27845400	1925	* @retval None
AnnaBridge	172:65be27845400	1926	*/
AnnaBridge	172:65be27845400	1927	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	172:65be27845400	1928	{
AnnaBridge	172:65be27845400	1929	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	172:65be27845400	1930	}
AnnaBridge	172:65be27845400	1931
AnnaBridge	172:65be27845400	1932	/**
AnnaBridge	172:65be27845400	1933	* @brief Enable capture/compare channels.
AnnaBridge	172:65be27845400	1934	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1935	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1936	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1937	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1938	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1939	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1940	* CCER CC4E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1941	* CCER CC5E LL_TIM_CC_EnableChannel\n
AnnaBridge	172:65be27845400	1942	* CCER CC6E LL_TIM_CC_EnableChannel
AnnaBridge	172:65be27845400	1943	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1944	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1945	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1946	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1947	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1948	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1949	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1950	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1951	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1952	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1953	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1954	* @retval None
AnnaBridge	172:65be27845400	1955	*/
AnnaBridge	172:65be27845400	1956	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	172:65be27845400	1957	{
AnnaBridge	172:65be27845400	1958	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	172:65be27845400	1959	}
AnnaBridge	172:65be27845400	1960
AnnaBridge	172:65be27845400	1961	/**
AnnaBridge	172:65be27845400	1962	* @brief Disable capture/compare channels.
AnnaBridge	172:65be27845400	1963	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1964	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1965	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1966	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1967	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1968	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1969	* CCER CC4E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1970	* CCER CC5E LL_TIM_CC_DisableChannel\n
AnnaBridge	172:65be27845400	1971	* CCER CC6E LL_TIM_CC_DisableChannel
AnnaBridge	172:65be27845400	1972	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	1973	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	1974	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	1975	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	1976	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	1977	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	1978	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	1979	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	1980	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	1981	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	1982	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	1983	* @retval None
AnnaBridge	172:65be27845400	1984	*/
AnnaBridge	172:65be27845400	1985	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	172:65be27845400	1986	{
AnnaBridge	172:65be27845400	1987	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	172:65be27845400	1988	}
AnnaBridge	172:65be27845400	1989
AnnaBridge	172:65be27845400	1990	/**
AnnaBridge	172:65be27845400	1991	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	172:65be27845400	1992	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1993	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1994	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1995	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1996	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1997	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1998	* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	1999	* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	172:65be27845400	2000	* CCER CC6E LL_TIM_CC_IsEnabledChannel
AnnaBridge	172:65be27845400	2001	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2002	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	172:65be27845400	2003	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2004	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2005	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2006	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2007	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2008	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2009	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2010	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2011	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2012	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2013	*/
AnnaBridge	172:65be27845400	2014	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	172:65be27845400	2015	{
AnnaBridge	172:65be27845400	2016	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	172:65be27845400	2017	}
AnnaBridge	172:65be27845400	2018
AnnaBridge	172:65be27845400	2019	/**
AnnaBridge	172:65be27845400	2020	* @}
AnnaBridge	172:65be27845400	2021	*/
AnnaBridge	172:65be27845400	2022
AnnaBridge	172:65be27845400	2023	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	172:65be27845400	2024	* @{
AnnaBridge	172:65be27845400	2025	*/
AnnaBridge	172:65be27845400	2026	/**
AnnaBridge	172:65be27845400	2027	* @brief Configure an output channel.
AnnaBridge	172:65be27845400	2028	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2029	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2030	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2031	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2032	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2033	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2034	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2035	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2036	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2037	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2038	* CCER CC5P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2039	* CCER CC6P LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2040	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2041	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2042	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2043	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2044	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
AnnaBridge	172:65be27845400	2045	* CR2 OIS6 LL_TIM_OC_ConfigOutput
AnnaBridge	172:65be27845400	2046	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2047	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2048	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2049	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2050	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2051	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2052	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2053	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2054	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	172:65be27845400	2055	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	172:65be27845400	2056	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	172:65be27845400	2057	* @retval None
AnnaBridge	172:65be27845400	2058	*/
AnnaBridge	172:65be27845400	2059	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	172:65be27845400	2060	{
AnnaBridge	172:65be27845400	2061	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2062	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2063	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2064	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	172:65be27845400	2065	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2066	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	172:65be27845400	2067	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	172:65be27845400	2068	}
AnnaBridge	172:65be27845400	2069
AnnaBridge	172:65be27845400	2070	/**
AnnaBridge	172:65be27845400	2071	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	172:65be27845400	2072	* OCx and OCxN (when relevant) are derived.
AnnaBridge	172:65be27845400	2073	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	2074	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	2075	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	2076	* CCMR2 OC4M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	2077	* CCMR3 OC5M LL_TIM_OC_SetMode\n
AnnaBridge	172:65be27845400	2078	* CCMR3 OC6M LL_TIM_OC_SetMode
AnnaBridge	172:65be27845400	2079	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2080	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2081	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2082	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2083	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2084	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2085	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2086	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2087	* @param Mode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2088	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	172:65be27845400	2089	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	172:65be27845400	2090	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	172:65be27845400	2091	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	172:65be27845400	2092	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	172:65be27845400	2093	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	172:65be27845400	2094	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	172:65be27845400	2095	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	172:65be27845400	2096	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	172:65be27845400	2097	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	172:65be27845400	2098	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	172:65be27845400	2099	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	172:65be27845400	2100	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	172:65be27845400	2101	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	172:65be27845400	2102	* @retval None
AnnaBridge	172:65be27845400	2103	*/
AnnaBridge	172:65be27845400	2104	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	172:65be27845400	2105	{
AnnaBridge	172:65be27845400	2106	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2107	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2108	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	172:65be27845400	2109	}
AnnaBridge	172:65be27845400	2110
AnnaBridge	172:65be27845400	2111	/**
AnnaBridge	172:65be27845400	2112	* @brief Get the output compare mode of an output channel.
AnnaBridge	172:65be27845400	2113	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	2114	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	2115	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	2116	* CCMR2 OC4M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	2117	* CCMR3 OC5M LL_TIM_OC_GetMode\n
AnnaBridge	172:65be27845400	2118	* CCMR3 OC6M LL_TIM_OC_GetMode
AnnaBridge	172:65be27845400	2119	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2120	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2121	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2122	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2123	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2124	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2125	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2126	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2127	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2128	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	172:65be27845400	2129	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	172:65be27845400	2130	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	172:65be27845400	2131	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	172:65be27845400	2132	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	172:65be27845400	2133	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	172:65be27845400	2134	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	172:65be27845400	2135	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	172:65be27845400	2136	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
AnnaBridge	172:65be27845400	2137	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
AnnaBridge	172:65be27845400	2138	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
AnnaBridge	172:65be27845400	2139	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
AnnaBridge	172:65be27845400	2140	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
AnnaBridge	172:65be27845400	2141	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
AnnaBridge	172:65be27845400	2142	*/
AnnaBridge	172:65be27845400	2143	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2144	{
AnnaBridge	172:65be27845400	2145	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2146	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2147	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	172:65be27845400	2148	}
AnnaBridge	172:65be27845400	2149
AnnaBridge	172:65be27845400	2150	/**
AnnaBridge	172:65be27845400	2151	* @brief Set the polarity of an output channel.
AnnaBridge	172:65be27845400	2152	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2153	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2154	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2155	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2156	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2157	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2158	* CCER CC4P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2159	* CCER CC5P LL_TIM_OC_SetPolarity\n
AnnaBridge	172:65be27845400	2160	* CCER CC6P LL_TIM_OC_SetPolarity
AnnaBridge	172:65be27845400	2161	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2162	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2163	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2164	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2165	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2166	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2167	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2168	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2169	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2170	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2171	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2172	* @param Polarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2173	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	172:65be27845400	2174	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	172:65be27845400	2175	* @retval None
AnnaBridge	172:65be27845400	2176	*/
AnnaBridge	172:65be27845400	2177	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	172:65be27845400	2178	{
AnnaBridge	172:65be27845400	2179	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2180	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2181	}
AnnaBridge	172:65be27845400	2182
AnnaBridge	172:65be27845400	2183	/**
AnnaBridge	172:65be27845400	2184	* @brief Get the polarity of an output channel.
AnnaBridge	172:65be27845400	2185	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2186	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2187	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2188	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2189	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2190	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2191	* CCER CC4P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2192	* CCER CC5P LL_TIM_OC_GetPolarity\n
AnnaBridge	172:65be27845400	2193	* CCER CC6P LL_TIM_OC_GetPolarity
AnnaBridge	172:65be27845400	2194	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2195	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2196	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2197	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2198	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2199	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2200	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2201	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2202	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2203	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2204	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2205	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2206	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	172:65be27845400	2207	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	172:65be27845400	2208	*/
AnnaBridge	172:65be27845400	2209	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2210	{
AnnaBridge	172:65be27845400	2211	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2212	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2213	}
AnnaBridge	172:65be27845400	2214
AnnaBridge	172:65be27845400	2215	/**
AnnaBridge	172:65be27845400	2216	* @brief Set the IDLE state of an output channel
AnnaBridge	172:65be27845400	2217	* @note This function is significant only for the timer instances
AnnaBridge	172:65be27845400	2218	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	172:65be27845400	2219	* can be used to check whether or not a timer instance provides
AnnaBridge	172:65be27845400	2220	* a break input.
AnnaBridge	172:65be27845400	2221	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2222	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2223	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2224	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2225	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2226	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2227	* CR2 OIS4 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2228	* CR2 OIS5 LL_TIM_OC_SetIdleState\n
AnnaBridge	172:65be27845400	2229	* CR2 OIS6 LL_TIM_OC_SetIdleState
AnnaBridge	172:65be27845400	2230	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2231	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2232	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2233	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2234	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2235	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2236	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2237	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2238	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2239	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2240	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2241	* @param IdleState This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2242	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	172:65be27845400	2243	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	172:65be27845400	2244	* @retval None
AnnaBridge	172:65be27845400	2245	*/
AnnaBridge	172:65be27845400	2246	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	172:65be27845400	2247	{
AnnaBridge	172:65be27845400	2248	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2249	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	172:65be27845400	2250	}
AnnaBridge	172:65be27845400	2251
AnnaBridge	172:65be27845400	2252	/**
AnnaBridge	172:65be27845400	2253	* @brief Get the IDLE state of an output channel
AnnaBridge	172:65be27845400	2254	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2255	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2256	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2257	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2258	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2259	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2260	* CR2 OIS4 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2261	* CR2 OIS5 LL_TIM_OC_GetIdleState\n
AnnaBridge	172:65be27845400	2262	* CR2 OIS6 LL_TIM_OC_GetIdleState
AnnaBridge	172:65be27845400	2263	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2264	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2265	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2266	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	172:65be27845400	2267	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2268	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	172:65be27845400	2269	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2270	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	172:65be27845400	2271	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2272	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2273	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2274	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2275	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	172:65be27845400	2276	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	172:65be27845400	2277	*/
AnnaBridge	172:65be27845400	2278	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2279	{
AnnaBridge	172:65be27845400	2280	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2281	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	172:65be27845400	2282	}
AnnaBridge	172:65be27845400	2283
AnnaBridge	172:65be27845400	2284	/**
AnnaBridge	172:65be27845400	2285	* @brief Enable fast mode for the output channel.
AnnaBridge	172:65be27845400	2286	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	172:65be27845400	2287	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2288	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2289	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2290	* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2291	* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
AnnaBridge	172:65be27845400	2292	* CCMR3 OC6FE LL_TIM_OC_EnableFast
AnnaBridge	172:65be27845400	2293	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2294	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2295	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2296	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2297	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2298	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2299	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2300	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2301	* @retval None
AnnaBridge	172:65be27845400	2302	*/
AnnaBridge	172:65be27845400	2303	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2304	{
AnnaBridge	172:65be27845400	2305	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2306	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2307	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2308
AnnaBridge	172:65be27845400	2309	}
AnnaBridge	172:65be27845400	2310
AnnaBridge	172:65be27845400	2311	/**
AnnaBridge	172:65be27845400	2312	* @brief Disable fast mode for the output channel.
AnnaBridge	172:65be27845400	2313	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2314	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2315	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2316	* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2317	* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
AnnaBridge	172:65be27845400	2318	* CCMR3 OC6FE LL_TIM_OC_DisableFast
AnnaBridge	172:65be27845400	2319	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2320	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2321	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2322	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2323	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2324	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2325	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2326	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2327	* @retval None
AnnaBridge	172:65be27845400	2328	*/
AnnaBridge	172:65be27845400	2329	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2330	{
AnnaBridge	172:65be27845400	2331	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2332	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2333	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2334
AnnaBridge	172:65be27845400	2335	}
AnnaBridge	172:65be27845400	2336
AnnaBridge	172:65be27845400	2337	/**
AnnaBridge	172:65be27845400	2338	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	172:65be27845400	2339	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2340	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2341	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2342	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2343	* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	172:65be27845400	2344	* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
AnnaBridge	172:65be27845400	2345	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2346	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2347	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2348	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2349	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2350	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2351	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2352	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2353	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2354	*/
AnnaBridge	172:65be27845400	2355	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2356	{
AnnaBridge	172:65be27845400	2357	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2358	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2359	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	172:65be27845400	2360	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	172:65be27845400	2361	}
AnnaBridge	172:65be27845400	2362
AnnaBridge	172:65be27845400	2363	/**
AnnaBridge	172:65be27845400	2364	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	172:65be27845400	2365	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2366	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2367	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2368	* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2369	* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
AnnaBridge	172:65be27845400	2370	* CCMR3 OC6PE LL_TIM_OC_EnablePreload
AnnaBridge	172:65be27845400	2371	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2372	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2373	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2374	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2375	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2376	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2377	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2378	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2379	* @retval None
AnnaBridge	172:65be27845400	2380	*/
AnnaBridge	172:65be27845400	2381	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2382	{
AnnaBridge	172:65be27845400	2383	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2384	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2385	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2386	}
AnnaBridge	172:65be27845400	2387
AnnaBridge	172:65be27845400	2388	/**
AnnaBridge	172:65be27845400	2389	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	172:65be27845400	2390	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2391	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2392	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2393	* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2394	* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
AnnaBridge	172:65be27845400	2395	* CCMR3 OC6PE LL_TIM_OC_DisablePreload
AnnaBridge	172:65be27845400	2396	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2397	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2398	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2399	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2400	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2401	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2402	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2403	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2404	* @retval None
AnnaBridge	172:65be27845400	2405	*/
AnnaBridge	172:65be27845400	2406	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2407	{
AnnaBridge	172:65be27845400	2408	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2409	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2410	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2411	}
AnnaBridge	172:65be27845400	2412
AnnaBridge	172:65be27845400	2413	/**
AnnaBridge	172:65be27845400	2414	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	172:65be27845400	2415	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2416	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2417	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2418	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2419	* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	172:65be27845400	2420	* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
AnnaBridge	172:65be27845400	2421	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2422	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2423	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2424	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2425	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2426	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2427	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2428	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2429	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2430	*/
AnnaBridge	172:65be27845400	2431	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2432	{
AnnaBridge	172:65be27845400	2433	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2434	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2435	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	172:65be27845400	2436	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	172:65be27845400	2437	}
AnnaBridge	172:65be27845400	2438
AnnaBridge	172:65be27845400	2439	/**
AnnaBridge	172:65be27845400	2440	* @brief Enable clearing the output channel on an external event.
AnnaBridge	172:65be27845400	2441	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	172:65be27845400	2442	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	2443	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	172:65be27845400	2444	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2445	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2446	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2447	* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2448	* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
AnnaBridge	172:65be27845400	2449	* CCMR3 OC6CE LL_TIM_OC_EnableClear
AnnaBridge	172:65be27845400	2450	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2451	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2452	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2453	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2454	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2455	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2456	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2457	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2458	* @retval None
AnnaBridge	172:65be27845400	2459	*/
AnnaBridge	172:65be27845400	2460	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2461	{
AnnaBridge	172:65be27845400	2462	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2463	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2464	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2465	}
AnnaBridge	172:65be27845400	2466
AnnaBridge	172:65be27845400	2467	/**
AnnaBridge	172:65be27845400	2468	* @brief Disable clearing the output channel on an external event.
AnnaBridge	172:65be27845400	2469	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	2470	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	172:65be27845400	2471	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2472	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2473	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2474	* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2475	* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
AnnaBridge	172:65be27845400	2476	* CCMR3 OC6CE LL_TIM_OC_DisableClear
AnnaBridge	172:65be27845400	2477	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2478	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2479	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2480	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2481	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2482	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2483	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2484	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2485	* @retval None
AnnaBridge	172:65be27845400	2486	*/
AnnaBridge	172:65be27845400	2487	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2488	{
AnnaBridge	172:65be27845400	2489	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2490	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2491	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	172:65be27845400	2492	}
AnnaBridge	172:65be27845400	2493
AnnaBridge	172:65be27845400	2494	/**
AnnaBridge	172:65be27845400	2495	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	172:65be27845400	2496	* @note This function enables clearing the output channel on an external event.
AnnaBridge	172:65be27845400	2497	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	172:65be27845400	2498	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	2499	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	172:65be27845400	2500	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2501	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2502	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2503	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2504	* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	172:65be27845400	2505	* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
AnnaBridge	172:65be27845400	2506	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2507	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2508	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2509	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2510	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2511	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2512	* @arg @ref LL_TIM_CHANNEL_CH5
AnnaBridge	172:65be27845400	2513	* @arg @ref LL_TIM_CHANNEL_CH6
AnnaBridge	172:65be27845400	2514	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	2515	*/
AnnaBridge	172:65be27845400	2516	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2517	{
AnnaBridge	172:65be27845400	2518	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2519	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2520	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	172:65be27845400	2521	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	172:65be27845400	2522	}
AnnaBridge	172:65be27845400	2523
AnnaBridge	172:65be27845400	2524	/**
AnnaBridge	172:65be27845400	2525	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
AnnaBridge	172:65be27845400	2526	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2527	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	172:65be27845400	2528	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	172:65be27845400	2529	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	172:65be27845400	2530	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2531	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	172:65be27845400	2532	* @retval None
AnnaBridge	172:65be27845400	2533	*/
AnnaBridge	172:65be27845400	2534	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	172:65be27845400	2535	{
AnnaBridge	172:65be27845400	2536	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	172:65be27845400	2537	}
AnnaBridge	172:65be27845400	2538
AnnaBridge	172:65be27845400	2539	/**
AnnaBridge	172:65be27845400	2540	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	172:65be27845400	2541	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2542	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2543	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2544	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2545	* output channel 1 is supported by a timer instance.
AnnaBridge	172:65be27845400	2546	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	172:65be27845400	2547	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2548	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2549	* @retval None
AnnaBridge	172:65be27845400	2550	*/
AnnaBridge	172:65be27845400	2551	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2552	{
AnnaBridge	172:65be27845400	2553	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	172:65be27845400	2554	}
AnnaBridge	172:65be27845400	2555
AnnaBridge	172:65be27845400	2556	/**
AnnaBridge	172:65be27845400	2557	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	172:65be27845400	2558	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2559	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2560	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2561	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2562	* output channel 2 is supported by a timer instance.
AnnaBridge	172:65be27845400	2563	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	172:65be27845400	2564	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2565	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2566	* @retval None
AnnaBridge	172:65be27845400	2567	*/
AnnaBridge	172:65be27845400	2568	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2569	{
AnnaBridge	172:65be27845400	2570	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	172:65be27845400	2571	}
AnnaBridge	172:65be27845400	2572
AnnaBridge	172:65be27845400	2573	/**
AnnaBridge	172:65be27845400	2574	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	172:65be27845400	2575	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2576	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2577	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2578	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2579	* output channel is supported by a timer instance.
AnnaBridge	172:65be27845400	2580	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	172:65be27845400	2581	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2582	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2583	* @retval None
AnnaBridge	172:65be27845400	2584	*/
AnnaBridge	172:65be27845400	2585	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2586	{
AnnaBridge	172:65be27845400	2587	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	172:65be27845400	2588	}
AnnaBridge	172:65be27845400	2589
AnnaBridge	172:65be27845400	2590	/**
AnnaBridge	172:65be27845400	2591	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	172:65be27845400	2592	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2593	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2594	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2595	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2596	* output channel 4 is supported by a timer instance.
AnnaBridge	172:65be27845400	2597	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	172:65be27845400	2598	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2599	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2600	* @retval None
AnnaBridge	172:65be27845400	2601	*/
AnnaBridge	172:65be27845400	2602	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2603	{
AnnaBridge	172:65be27845400	2604	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	172:65be27845400	2605	}
AnnaBridge	172:65be27845400	2606
AnnaBridge	172:65be27845400	2607	/**
AnnaBridge	172:65be27845400	2608	* @brief Set compare value for output channel 5 (TIMx_CCR5).
AnnaBridge	172:65be27845400	2609	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2610	* output channel 5 is supported by a timer instance.
AnnaBridge	172:65be27845400	2611	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
AnnaBridge	172:65be27845400	2612	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2613	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2614	* @retval None
AnnaBridge	172:65be27845400	2615	*/
AnnaBridge	172:65be27845400	2616	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2617	{
AnnaBridge	172:65be27845400	2618	WRITE_REG(TIMx->CCR5, CompareValue);
AnnaBridge	172:65be27845400	2619	}
AnnaBridge	172:65be27845400	2620
AnnaBridge	172:65be27845400	2621	/**
AnnaBridge	172:65be27845400	2622	* @brief Set compare value for output channel 6 (TIMx_CCR6).
AnnaBridge	172:65be27845400	2623	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2624	* output channel 6 is supported by a timer instance.
AnnaBridge	172:65be27845400	2625	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
AnnaBridge	172:65be27845400	2626	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2627	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	172:65be27845400	2628	* @retval None
AnnaBridge	172:65be27845400	2629	*/
AnnaBridge	172:65be27845400	2630	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	172:65be27845400	2631	{
AnnaBridge	172:65be27845400	2632	WRITE_REG(TIMx->CCR6, CompareValue);
AnnaBridge	172:65be27845400	2633	}
AnnaBridge	172:65be27845400	2634
AnnaBridge	172:65be27845400	2635	/**
AnnaBridge	172:65be27845400	2636	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	172:65be27845400	2637	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2638	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2639	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2640	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2641	* output channel 1 is supported by a timer instance.
AnnaBridge	172:65be27845400	2642	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	172:65be27845400	2643	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2644	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2645	*/
AnnaBridge	172:65be27845400	2646	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2647	{
AnnaBridge	172:65be27845400	2648	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	172:65be27845400	2649	}
AnnaBridge	172:65be27845400	2650
AnnaBridge	172:65be27845400	2651	/**
AnnaBridge	172:65be27845400	2652	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	172:65be27845400	2653	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2654	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2655	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2656	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2657	* output channel 2 is supported by a timer instance.
AnnaBridge	172:65be27845400	2658	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	172:65be27845400	2659	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2660	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2661	*/
AnnaBridge	172:65be27845400	2662	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2663	{
AnnaBridge	172:65be27845400	2664	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	172:65be27845400	2665	}
AnnaBridge	172:65be27845400	2666
AnnaBridge	172:65be27845400	2667	/**
AnnaBridge	172:65be27845400	2668	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	172:65be27845400	2669	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2670	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2671	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2672	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2673	* output channel 3 is supported by a timer instance.
AnnaBridge	172:65be27845400	2674	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	172:65be27845400	2675	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2676	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2677	*/
AnnaBridge	172:65be27845400	2678	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2679	{
AnnaBridge	172:65be27845400	2680	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	172:65be27845400	2681	}
AnnaBridge	172:65be27845400	2682
AnnaBridge	172:65be27845400	2683	/**
AnnaBridge	172:65be27845400	2684	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	172:65be27845400	2685	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	2686	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2687	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	2688	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2689	* output channel 4 is supported by a timer instance.
AnnaBridge	172:65be27845400	2690	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	172:65be27845400	2691	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2692	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2693	*/
AnnaBridge	172:65be27845400	2694	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2695	{
AnnaBridge	172:65be27845400	2696	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	172:65be27845400	2697	}
AnnaBridge	172:65be27845400	2698
AnnaBridge	172:65be27845400	2699	/**
AnnaBridge	172:65be27845400	2700	* @brief Get compare value (TIMx_CCR5) set for output channel 5.
AnnaBridge	172:65be27845400	2701	* @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2702	* output channel 5 is supported by a timer instance.
AnnaBridge	172:65be27845400	2703	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
AnnaBridge	172:65be27845400	2704	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2705	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2706	*/
AnnaBridge	172:65be27845400	2707	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2708	{
AnnaBridge	172:65be27845400	2709	return (uint32_t)(READ_REG(TIMx->CCR5));
AnnaBridge	172:65be27845400	2710	}
AnnaBridge	172:65be27845400	2711
AnnaBridge	172:65be27845400	2712	/**
AnnaBridge	172:65be27845400	2713	* @brief Get compare value (TIMx_CCR6) set for output channel 6.
AnnaBridge	172:65be27845400	2714	* @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	2715	* output channel 6 is supported by a timer instance.
AnnaBridge	172:65be27845400	2716	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
AnnaBridge	172:65be27845400	2717	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2718	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	2719	*/
AnnaBridge	172:65be27845400	2720	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	2721	{
AnnaBridge	172:65be27845400	2722	return (uint32_t)(READ_REG(TIMx->CCR6));
AnnaBridge	172:65be27845400	2723	}
AnnaBridge	172:65be27845400	2724
AnnaBridge	172:65be27845400	2725	/**
AnnaBridge	172:65be27845400	2726	* @brief Select on which reference signal the OC5REF is combined to.
AnnaBridge	172:65be27845400	2727	* @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	2728	* whether or not a timer instance supports the combined 3-phase PWM mode.
AnnaBridge	172:65be27845400	2729	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	172:65be27845400	2730	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
AnnaBridge	172:65be27845400	2731	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
AnnaBridge	172:65be27845400	2732	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2733	* @param GroupCH5 This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2734	* @arg @ref LL_TIM_GROUPCH5_NONE
AnnaBridge	172:65be27845400	2735	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
AnnaBridge	172:65be27845400	2736	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
AnnaBridge	172:65be27845400	2737	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
AnnaBridge	172:65be27845400	2738	* @retval None
AnnaBridge	172:65be27845400	2739	*/
AnnaBridge	172:65be27845400	2740	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
AnnaBridge	172:65be27845400	2741	{
AnnaBridge	172:65be27845400	2742	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
AnnaBridge	172:65be27845400	2743	}
AnnaBridge	172:65be27845400	2744
AnnaBridge	172:65be27845400	2745	/**
AnnaBridge	172:65be27845400	2746	* @}
AnnaBridge	172:65be27845400	2747	*/
AnnaBridge	172:65be27845400	2748
AnnaBridge	172:65be27845400	2749	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	172:65be27845400	2750	* @{
AnnaBridge	172:65be27845400	2751	*/
AnnaBridge	172:65be27845400	2752	/**
AnnaBridge	172:65be27845400	2753	* @brief Configure input channel.
AnnaBridge	172:65be27845400	2754	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2755	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2756	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2757	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2758	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2759	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2760	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2761	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2762	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2763	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2764	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2765	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2766	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2767	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2768	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2769	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2770	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2771	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2772	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	172:65be27845400	2773	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	172:65be27845400	2774	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2775	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2776	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2777	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2778	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2779	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2780	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	172:65be27845400	2781	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	172:65be27845400	2782	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	2783	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	2784	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	172:65be27845400	2785	* @retval None
AnnaBridge	172:65be27845400	2786	*/
AnnaBridge	172:65be27845400	2787	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	172:65be27845400	2788	{
AnnaBridge	172:65be27845400	2789	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2790	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2791	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	172:65be27845400	2792	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2793	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	172:65be27845400	2794	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2795	}
AnnaBridge	172:65be27845400	2796
AnnaBridge	172:65be27845400	2797	/**
AnnaBridge	172:65be27845400	2798	* @brief Set the active input.
AnnaBridge	172:65be27845400	2799	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	172:65be27845400	2800	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	172:65be27845400	2801	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	172:65be27845400	2802	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	172:65be27845400	2803	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2804	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2805	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2806	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2807	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2808	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2809	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2810	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	172:65be27845400	2811	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	172:65be27845400	2812	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	172:65be27845400	2813	* @retval None
AnnaBridge	172:65be27845400	2814	*/
AnnaBridge	172:65be27845400	2815	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	172:65be27845400	2816	{
AnnaBridge	172:65be27845400	2817	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2818	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2819	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2820	}
AnnaBridge	172:65be27845400	2821
AnnaBridge	172:65be27845400	2822	/**
AnnaBridge	172:65be27845400	2823	* @brief Get the current active input.
AnnaBridge	172:65be27845400	2824	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	172:65be27845400	2825	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	172:65be27845400	2826	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	172:65be27845400	2827	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	172:65be27845400	2828	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2829	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2830	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2831	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2832	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2833	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2834	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2835	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	172:65be27845400	2836	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	172:65be27845400	2837	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	172:65be27845400	2838	*/
AnnaBridge	172:65be27845400	2839	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2840	{
AnnaBridge	172:65be27845400	2841	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2842	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2843	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	172:65be27845400	2844	}
AnnaBridge	172:65be27845400	2845
AnnaBridge	172:65be27845400	2846	/**
AnnaBridge	172:65be27845400	2847	* @brief Set the prescaler of input channel.
AnnaBridge	172:65be27845400	2848	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	172:65be27845400	2849	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	172:65be27845400	2850	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	172:65be27845400	2851	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	172:65be27845400	2852	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2853	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2854	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2855	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2856	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2857	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2858	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2859	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	172:65be27845400	2860	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	172:65be27845400	2861	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	172:65be27845400	2862	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	2863	* @retval None
AnnaBridge	172:65be27845400	2864	*/
AnnaBridge	172:65be27845400	2865	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	172:65be27845400	2866	{
AnnaBridge	172:65be27845400	2867	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2868	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2869	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2870	}
AnnaBridge	172:65be27845400	2871
AnnaBridge	172:65be27845400	2872	/**
AnnaBridge	172:65be27845400	2873	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	172:65be27845400	2874	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	172:65be27845400	2875	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	172:65be27845400	2876	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	172:65be27845400	2877	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	172:65be27845400	2878	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2879	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2880	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2881	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2882	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2883	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2884	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2885	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	172:65be27845400	2886	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	172:65be27845400	2887	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	172:65be27845400	2888	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	172:65be27845400	2889	*/
AnnaBridge	172:65be27845400	2890	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2891	{
AnnaBridge	172:65be27845400	2892	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2893	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2894	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	172:65be27845400	2895	}
AnnaBridge	172:65be27845400	2896
AnnaBridge	172:65be27845400	2897	/**
AnnaBridge	172:65be27845400	2898	* @brief Set the input filter duration.
AnnaBridge	172:65be27845400	2899	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	172:65be27845400	2900	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	172:65be27845400	2901	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	172:65be27845400	2902	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	172:65be27845400	2903	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2904	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2905	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2906	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2907	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2908	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2909	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2910	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	172:65be27845400	2911	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	2912	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	2913	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	2914	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	2915	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	2916	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	2917	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	2918	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	2919	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	2920	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	2921	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	2922	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	2923	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	2924	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	2925	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	2926	* @retval None
AnnaBridge	172:65be27845400	2927	*/
AnnaBridge	172:65be27845400	2928	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	172:65be27845400	2929	{
AnnaBridge	172:65be27845400	2930	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2931	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2932	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	172:65be27845400	2933	}
AnnaBridge	172:65be27845400	2934
AnnaBridge	172:65be27845400	2935	/**
AnnaBridge	172:65be27845400	2936	* @brief Get the input filter duration.
AnnaBridge	172:65be27845400	2937	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	172:65be27845400	2938	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	172:65be27845400	2939	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	172:65be27845400	2940	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	172:65be27845400	2941	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2942	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2943	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2944	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2945	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2946	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2947	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	2948	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	172:65be27845400	2949	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	2950	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	2951	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	2952	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	2953	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	2954	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	2955	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	2956	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	2957	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	2958	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	2959	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	2960	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	2961	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	2962	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	2963	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	2964	*/
AnnaBridge	172:65be27845400	2965	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	2966	{
AnnaBridge	172:65be27845400	2967	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2968	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	172:65be27845400	2969	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	172:65be27845400	2970	}
AnnaBridge	172:65be27845400	2971
AnnaBridge	172:65be27845400	2972	/**
AnnaBridge	172:65be27845400	2973	* @brief Set the input channel polarity.
AnnaBridge	172:65be27845400	2974	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2975	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2976	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2977	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2978	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2979	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2980	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	172:65be27845400	2981	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	172:65be27845400	2982	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	2983	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2984	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	2985	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	2986	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	2987	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	2988	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2989	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	172:65be27845400	2990	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	172:65be27845400	2991	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	172:65be27845400	2992	* @retval None
AnnaBridge	172:65be27845400	2993	*/
AnnaBridge	172:65be27845400	2994	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	172:65be27845400	2995	{
AnnaBridge	172:65be27845400	2996	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	2997	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	172:65be27845400	2998	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	2999	}
AnnaBridge	172:65be27845400	3000
AnnaBridge	172:65be27845400	3001	/**
AnnaBridge	172:65be27845400	3002	* @brief Get the current input channel polarity.
AnnaBridge	172:65be27845400	3003	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3004	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3005	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3006	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3007	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3008	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3009	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	172:65be27845400	3010	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	172:65be27845400	3011	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3012	* @param Channel This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3013	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	172:65be27845400	3014	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	172:65be27845400	3015	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	172:65be27845400	3016	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	172:65be27845400	3017	* @retval Returned value can be one of the following values:
AnnaBridge	172:65be27845400	3018	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	172:65be27845400	3019	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	172:65be27845400	3020	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	172:65be27845400	3021	*/
AnnaBridge	172:65be27845400	3022	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	172:65be27845400	3023	{
AnnaBridge	172:65be27845400	3024	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	172:65be27845400	3025	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	172:65be27845400	3026	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	172:65be27845400	3027	}
AnnaBridge	172:65be27845400	3028
AnnaBridge	172:65be27845400	3029	/**
AnnaBridge	172:65be27845400	3030	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	172:65be27845400	3031	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3032	* a timer instance provides an XOR input.
AnnaBridge	172:65be27845400	3033	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	172:65be27845400	3034	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3035	* @retval None
AnnaBridge	172:65be27845400	3036	*/
AnnaBridge	172:65be27845400	3037	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3038	{
AnnaBridge	172:65be27845400	3039	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	172:65be27845400	3040	}
AnnaBridge	172:65be27845400	3041
AnnaBridge	172:65be27845400	3042	/**
AnnaBridge	172:65be27845400	3043	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	172:65be27845400	3044	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3045	* a timer instance provides an XOR input.
AnnaBridge	172:65be27845400	3046	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	172:65be27845400	3047	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3048	* @retval None
AnnaBridge	172:65be27845400	3049	*/
AnnaBridge	172:65be27845400	3050	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3051	{
AnnaBridge	172:65be27845400	3052	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	172:65be27845400	3053	}
AnnaBridge	172:65be27845400	3054
AnnaBridge	172:65be27845400	3055	/**
AnnaBridge	172:65be27845400	3056	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	172:65be27845400	3057	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3058	* a timer instance provides an XOR input.
AnnaBridge	172:65be27845400	3059	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	172:65be27845400	3060	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3061	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3062	*/
AnnaBridge	172:65be27845400	3063	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3064	{
AnnaBridge	172:65be27845400	3065	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	172:65be27845400	3066	}
AnnaBridge	172:65be27845400	3067
AnnaBridge	172:65be27845400	3068	/**
AnnaBridge	172:65be27845400	3069	* @brief Get captured value for input channel 1.
AnnaBridge	172:65be27845400	3070	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	3071	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3072	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	3073	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3074	* input channel 1 is supported by a timer instance.
AnnaBridge	172:65be27845400	3075	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	172:65be27845400	3076	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3077	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	3078	*/
AnnaBridge	172:65be27845400	3079	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3080	{
AnnaBridge	172:65be27845400	3081	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	172:65be27845400	3082	}
AnnaBridge	172:65be27845400	3083
AnnaBridge	172:65be27845400	3084	/**
AnnaBridge	172:65be27845400	3085	* @brief Get captured value for input channel 2.
AnnaBridge	172:65be27845400	3086	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	3087	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3088	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	3089	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3090	* input channel 2 is supported by a timer instance.
AnnaBridge	172:65be27845400	3091	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	172:65be27845400	3092	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3093	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	3094	*/
AnnaBridge	172:65be27845400	3095	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3096	{
AnnaBridge	172:65be27845400	3097	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	172:65be27845400	3098	}
AnnaBridge	172:65be27845400	3099
AnnaBridge	172:65be27845400	3100	/**
AnnaBridge	172:65be27845400	3101	* @brief Get captured value for input channel 3.
AnnaBridge	172:65be27845400	3102	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	3103	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3104	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	3105	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3106	* input channel 3 is supported by a timer instance.
AnnaBridge	172:65be27845400	3107	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	172:65be27845400	3108	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3109	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	3110	*/
AnnaBridge	172:65be27845400	3111	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3112	{
AnnaBridge	172:65be27845400	3113	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	172:65be27845400	3114	}
AnnaBridge	172:65be27845400	3115
AnnaBridge	172:65be27845400	3116	/**
AnnaBridge	172:65be27845400	3117	* @brief Get captured value for input channel 4.
AnnaBridge	172:65be27845400	3118	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	172:65be27845400	3119	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3120	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	172:65be27845400	3121	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3122	* input channel 4 is supported by a timer instance.
AnnaBridge	172:65be27845400	3123	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	172:65be27845400	3124	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3125	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	172:65be27845400	3126	*/
AnnaBridge	172:65be27845400	3127	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3128	{
AnnaBridge	172:65be27845400	3129	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	172:65be27845400	3130	}
AnnaBridge	172:65be27845400	3131
AnnaBridge	172:65be27845400	3132	/**
AnnaBridge	172:65be27845400	3133	* @}
AnnaBridge	172:65be27845400	3134	*/
AnnaBridge	172:65be27845400	3135
AnnaBridge	172:65be27845400	3136	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	172:65be27845400	3137	* @{
AnnaBridge	172:65be27845400	3138	*/
AnnaBridge	172:65be27845400	3139	/**
AnnaBridge	172:65be27845400	3140	* @brief Enable external clock mode 2.
AnnaBridge	172:65be27845400	3141	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	172:65be27845400	3142	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3143	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	3144	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	172:65be27845400	3145	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3146	* @retval None
AnnaBridge	172:65be27845400	3147	*/
AnnaBridge	172:65be27845400	3148	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3149	{
AnnaBridge	172:65be27845400	3150	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	172:65be27845400	3151	}
AnnaBridge	172:65be27845400	3152
AnnaBridge	172:65be27845400	3153	/**
AnnaBridge	172:65be27845400	3154	* @brief Disable external clock mode 2.
AnnaBridge	172:65be27845400	3155	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3156	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	3157	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	172:65be27845400	3158	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3159	* @retval None
AnnaBridge	172:65be27845400	3160	*/
AnnaBridge	172:65be27845400	3161	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3162	{
AnnaBridge	172:65be27845400	3163	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	172:65be27845400	3164	}
AnnaBridge	172:65be27845400	3165
AnnaBridge	172:65be27845400	3166	/**
AnnaBridge	172:65be27845400	3167	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	172:65be27845400	3168	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3169	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	3170	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	172:65be27845400	3171	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3172	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3173	*/
AnnaBridge	172:65be27845400	3174	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3175	{
AnnaBridge	172:65be27845400	3176	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	172:65be27845400	3177	}
AnnaBridge	172:65be27845400	3178
AnnaBridge	172:65be27845400	3179	/**
AnnaBridge	172:65be27845400	3180	* @brief Set the clock source of the counter clock.
AnnaBridge	172:65be27845400	3181	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	172:65be27845400	3182	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	172:65be27845400	3183	* function. This timer input must be configured by calling
AnnaBridge	172:65be27845400	3184	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	172:65be27845400	3185	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3186	* whether or not a timer instance supports external clock mode1.
AnnaBridge	172:65be27845400	3187	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3188	* whether or not a timer instance supports external clock mode2.
AnnaBridge	172:65be27845400	3189	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	172:65be27845400	3190	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	172:65be27845400	3191	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3192	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3193	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	172:65be27845400	3194	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	172:65be27845400	3195	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	172:65be27845400	3196	* @retval None
AnnaBridge	172:65be27845400	3197	*/
AnnaBridge	172:65be27845400	3198	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	172:65be27845400	3199	{
AnnaBridge	172:65be27845400	3200	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	172:65be27845400	3201	}
AnnaBridge	172:65be27845400	3202
AnnaBridge	172:65be27845400	3203	/**
AnnaBridge	172:65be27845400	3204	* @brief Set the encoder interface mode.
AnnaBridge	172:65be27845400	3205	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3206	* whether or not a timer instance supports the encoder mode.
AnnaBridge	172:65be27845400	3207	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	172:65be27845400	3208	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3209	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3210	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	172:65be27845400	3211	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	172:65be27845400	3212	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	172:65be27845400	3213	* @retval None
AnnaBridge	172:65be27845400	3214	*/
AnnaBridge	172:65be27845400	3215	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	172:65be27845400	3216	{
AnnaBridge	172:65be27845400	3217	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	172:65be27845400	3218	}
AnnaBridge	172:65be27845400	3219
AnnaBridge	172:65be27845400	3220	/**
AnnaBridge	172:65be27845400	3221	* @}
AnnaBridge	172:65be27845400	3222	*/
AnnaBridge	172:65be27845400	3223
AnnaBridge	172:65be27845400	3224	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	172:65be27845400	3225	* @{
AnnaBridge	172:65be27845400	3226	*/
AnnaBridge	172:65be27845400	3227	/**
AnnaBridge	172:65be27845400	3228	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	172:65be27845400	3229	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3230	* whether or not a timer instance can operate as a master timer.
AnnaBridge	172:65be27845400	3231	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	172:65be27845400	3232	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3233	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3234	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	172:65be27845400	3235	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	172:65be27845400	3236	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	172:65be27845400	3237	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	172:65be27845400	3238	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	172:65be27845400	3239	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	172:65be27845400	3240	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	172:65be27845400	3241	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	172:65be27845400	3242	* @retval None
AnnaBridge	172:65be27845400	3243	*/
AnnaBridge	172:65be27845400	3244	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	172:65be27845400	3245	{
AnnaBridge	172:65be27845400	3246	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	172:65be27845400	3247	}
AnnaBridge	172:65be27845400	3248
AnnaBridge	172:65be27845400	3249	/**
AnnaBridge	172:65be27845400	3250	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
AnnaBridge	172:65be27845400	3251	* @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
AnnaBridge	172:65be27845400	3252	* whether or not a timer instance can be used for ADC synchronization.
AnnaBridge	172:65be27845400	3253	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
AnnaBridge	172:65be27845400	3254	* @param TIMx Timer Instance
AnnaBridge	172:65be27845400	3255	* @param ADCSynchronization This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3256	* @arg @ref LL_TIM_TRGO2_RESET
AnnaBridge	172:65be27845400	3257	* @arg @ref LL_TIM_TRGO2_ENABLE
AnnaBridge	172:65be27845400	3258	* @arg @ref LL_TIM_TRGO2_UPDATE
AnnaBridge	172:65be27845400	3259	* @arg @ref LL_TIM_TRGO2_CC1F
AnnaBridge	172:65be27845400	3260	* @arg @ref LL_TIM_TRGO2_OC1
AnnaBridge	172:65be27845400	3261	* @arg @ref LL_TIM_TRGO2_OC2
AnnaBridge	172:65be27845400	3262	* @arg @ref LL_TIM_TRGO2_OC3
AnnaBridge	172:65be27845400	3263	* @arg @ref LL_TIM_TRGO2_OC4
AnnaBridge	172:65be27845400	3264	* @arg @ref LL_TIM_TRGO2_OC5
AnnaBridge	172:65be27845400	3265	* @arg @ref LL_TIM_TRGO2_OC6
AnnaBridge	172:65be27845400	3266	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
AnnaBridge	172:65be27845400	3267	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
AnnaBridge	172:65be27845400	3268	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
AnnaBridge	172:65be27845400	3269	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
AnnaBridge	172:65be27845400	3270	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
AnnaBridge	172:65be27845400	3271	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
AnnaBridge	172:65be27845400	3272	* @retval None
AnnaBridge	172:65be27845400	3273	*/
AnnaBridge	172:65be27845400	3274	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
AnnaBridge	172:65be27845400	3275	{
AnnaBridge	172:65be27845400	3276	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
AnnaBridge	172:65be27845400	3277	}
AnnaBridge	172:65be27845400	3278
AnnaBridge	172:65be27845400	3279	/**
AnnaBridge	172:65be27845400	3280	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	172:65be27845400	3281	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3282	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3283	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	172:65be27845400	3284	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3285	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3286	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	172:65be27845400	3287	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	172:65be27845400	3288	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	172:65be27845400	3289	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	172:65be27845400	3290	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
AnnaBridge	172:65be27845400	3291	* @retval None
AnnaBridge	172:65be27845400	3292	*/
AnnaBridge	172:65be27845400	3293	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	172:65be27845400	3294	{
AnnaBridge	172:65be27845400	3295	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	172:65be27845400	3296	}
AnnaBridge	172:65be27845400	3297
AnnaBridge	172:65be27845400	3298	/**
AnnaBridge	172:65be27845400	3299	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	172:65be27845400	3300	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3301	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3302	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	172:65be27845400	3303	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3304	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3305	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	172:65be27845400	3306	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	172:65be27845400	3307	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	172:65be27845400	3308	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	172:65be27845400	3309	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	172:65be27845400	3310	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	172:65be27845400	3311	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	172:65be27845400	3312	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	172:65be27845400	3313	* @retval None
AnnaBridge	172:65be27845400	3314	*/
AnnaBridge	172:65be27845400	3315	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	172:65be27845400	3316	{
AnnaBridge	172:65be27845400	3317	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	172:65be27845400	3318	}
AnnaBridge	172:65be27845400	3319
AnnaBridge	172:65be27845400	3320	/**
AnnaBridge	172:65be27845400	3321	* @brief Enable the Master/Slave mode.
AnnaBridge	172:65be27845400	3322	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3323	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3324	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	172:65be27845400	3325	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3326	* @retval None
AnnaBridge	172:65be27845400	3327	*/
AnnaBridge	172:65be27845400	3328	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3329	{
AnnaBridge	172:65be27845400	3330	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	172:65be27845400	3331	}
AnnaBridge	172:65be27845400	3332
AnnaBridge	172:65be27845400	3333	/**
AnnaBridge	172:65be27845400	3334	* @brief Disable the Master/Slave mode.
AnnaBridge	172:65be27845400	3335	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3336	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3337	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	172:65be27845400	3338	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3339	* @retval None
AnnaBridge	172:65be27845400	3340	*/
AnnaBridge	172:65be27845400	3341	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3342	{
AnnaBridge	172:65be27845400	3343	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	172:65be27845400	3344	}
AnnaBridge	172:65be27845400	3345
AnnaBridge	172:65be27845400	3346	/**
AnnaBridge	172:65be27845400	3347	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	172:65be27845400	3348	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3349	* a timer instance can operate as a slave timer.
AnnaBridge	172:65be27845400	3350	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	172:65be27845400	3351	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3352	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3353	*/
AnnaBridge	172:65be27845400	3354	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3355	{
AnnaBridge	172:65be27845400	3356	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	172:65be27845400	3357	}
AnnaBridge	172:65be27845400	3358
AnnaBridge	172:65be27845400	3359	/**
AnnaBridge	172:65be27845400	3360	* @brief Configure the external trigger (ETR) input.
AnnaBridge	172:65be27845400	3361	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3362	* a timer instance provides an external trigger input.
AnnaBridge	172:65be27845400	3363	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	172:65be27845400	3364	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	172:65be27845400	3365	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	172:65be27845400	3366	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3367	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3368	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	172:65be27845400	3369	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	172:65be27845400	3370	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3371	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	172:65be27845400	3372	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	172:65be27845400	3373	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	172:65be27845400	3374	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	172:65be27845400	3375	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3376	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	172:65be27845400	3377	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	3378	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	3379	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	3380	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	3381	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	3382	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	3383	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	3384	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	3385	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	3386	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	3387	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	3388	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	3389	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	3390	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	3391	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	3392	* @retval None
AnnaBridge	172:65be27845400	3393	*/
AnnaBridge	172:65be27845400	3394	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	172:65be27845400	3395	uint32_t ETRFilter)
AnnaBridge	172:65be27845400	3396	{
AnnaBridge	172:65be27845400	3397	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	172:65be27845400	3398	}
AnnaBridge	172:65be27845400	3399
AnnaBridge	172:65be27845400	3400	/**
AnnaBridge	172:65be27845400	3401	* @brief Select the external trigger (ETR) input source.
AnnaBridge	172:65be27845400	3402	* @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	172:65be27845400	3403	* not a timer instance supports ETR source selection.
AnnaBridge	172:65be27845400	3404	* @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
AnnaBridge	172:65be27845400	3405	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3406	* @param ETRSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3407	* @arg @ref LL_TIM_ETRSOURCE_LEGACY
AnnaBridge	172:65be27845400	3408	* @arg @ref LL_TIM_ETRSOURCE_COMP1
AnnaBridge	172:65be27845400	3409	* @arg @ref LL_TIM_ETRSOURCE_COMP2
AnnaBridge	172:65be27845400	3410	* @retval None
AnnaBridge	172:65be27845400	3411	*/
AnnaBridge	172:65be27845400	3412	__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
AnnaBridge	172:65be27845400	3413	{
AnnaBridge	172:65be27845400	3414
AnnaBridge	172:65be27845400	3415	MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
AnnaBridge	172:65be27845400	3416	}
AnnaBridge	172:65be27845400	3417
AnnaBridge	172:65be27845400	3418	/**
AnnaBridge	172:65be27845400	3419	* @}
AnnaBridge	172:65be27845400	3420	*/
AnnaBridge	172:65be27845400	3421
AnnaBridge	172:65be27845400	3422	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	172:65be27845400	3423	* @{
AnnaBridge	172:65be27845400	3424	*/
AnnaBridge	172:65be27845400	3425	/**
AnnaBridge	172:65be27845400	3426	* @brief Enable the break function.
AnnaBridge	172:65be27845400	3427	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3428	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3429	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	172:65be27845400	3430	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3431	* @retval None
AnnaBridge	172:65be27845400	3432	*/
AnnaBridge	172:65be27845400	3433	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3434	{
AnnaBridge	172:65be27845400	3435	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	172:65be27845400	3436	}
AnnaBridge	172:65be27845400	3437
AnnaBridge	172:65be27845400	3438	/**
AnnaBridge	172:65be27845400	3439	* @brief Disable the break function.
AnnaBridge	172:65be27845400	3440	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	172:65be27845400	3441	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3442	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3443	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3444	* @retval None
AnnaBridge	172:65be27845400	3445	*/
AnnaBridge	172:65be27845400	3446	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3447	{
AnnaBridge	172:65be27845400	3448	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	172:65be27845400	3449	}
AnnaBridge	172:65be27845400	3450
AnnaBridge	172:65be27845400	3451	/**
AnnaBridge	172:65be27845400	3452	* @brief Configure the break input.
AnnaBridge	172:65be27845400	3453	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3454	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3455	* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
AnnaBridge	172:65be27845400	3456	* BDTR BKF LL_TIM_ConfigBRK
AnnaBridge	172:65be27845400	3457	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3458	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3459	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	172:65be27845400	3460	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	172:65be27845400	3461	* @param BreakFilter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3462	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
AnnaBridge	172:65be27845400	3463	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	3464	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	3465	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	3466	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	3467	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	3468	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	3469	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	3470	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	3471	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	3472	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	3473	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	3474	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	3475	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	3476	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	3477	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	3478	* @retval None
AnnaBridge	172:65be27845400	3479	*/
AnnaBridge	172:65be27845400	3480	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
AnnaBridge	172:65be27845400	3481	{
AnnaBridge	172:65be27845400	3482	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
AnnaBridge	172:65be27845400	3483	}
AnnaBridge	172:65be27845400	3484
AnnaBridge	172:65be27845400	3485	/**
AnnaBridge	172:65be27845400	3486	* @brief Enable the break 2 function.
AnnaBridge	172:65be27845400	3487	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3488	* a timer instance provides a second break input.
AnnaBridge	172:65be27845400	3489	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
AnnaBridge	172:65be27845400	3490	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3491	* @retval None
AnnaBridge	172:65be27845400	3492	*/
AnnaBridge	172:65be27845400	3493	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3494	{
AnnaBridge	172:65be27845400	3495	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	172:65be27845400	3496	}
AnnaBridge	172:65be27845400	3497
AnnaBridge	172:65be27845400	3498	/**
AnnaBridge	172:65be27845400	3499	* @brief Disable the break 2 function.
AnnaBridge	172:65be27845400	3500	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3501	* a timer instance provides a second break input.
AnnaBridge	172:65be27845400	3502	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
AnnaBridge	172:65be27845400	3503	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3504	* @retval None
AnnaBridge	172:65be27845400	3505	*/
AnnaBridge	172:65be27845400	3506	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3507	{
AnnaBridge	172:65be27845400	3508	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
AnnaBridge	172:65be27845400	3509	}
AnnaBridge	172:65be27845400	3510
AnnaBridge	172:65be27845400	3511	/**
AnnaBridge	172:65be27845400	3512	* @brief Configure the break 2 input.
AnnaBridge	172:65be27845400	3513	* @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3514	* a timer instance provides a second break input.
AnnaBridge	172:65be27845400	3515	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
AnnaBridge	172:65be27845400	3516	* BDTR BK2F LL_TIM_ConfigBRK2
AnnaBridge	172:65be27845400	3517	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3518	* @param Break2Polarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3519	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
AnnaBridge	172:65be27845400	3520	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
AnnaBridge	172:65be27845400	3521	* @param Break2Filter This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3522	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
AnnaBridge	172:65be27845400	3523	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
AnnaBridge	172:65be27845400	3524	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
AnnaBridge	172:65be27845400	3525	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
AnnaBridge	172:65be27845400	3526	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
AnnaBridge	172:65be27845400	3527	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
AnnaBridge	172:65be27845400	3528	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
AnnaBridge	172:65be27845400	3529	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
AnnaBridge	172:65be27845400	3530	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
AnnaBridge	172:65be27845400	3531	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
AnnaBridge	172:65be27845400	3532	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
AnnaBridge	172:65be27845400	3533	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
AnnaBridge	172:65be27845400	3534	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
AnnaBridge	172:65be27845400	3535	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
AnnaBridge	172:65be27845400	3536	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
AnnaBridge	172:65be27845400	3537	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
AnnaBridge	172:65be27845400	3538	* @retval None
AnnaBridge	172:65be27845400	3539	*/
AnnaBridge	172:65be27845400	3540	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
AnnaBridge	172:65be27845400	3541	{
AnnaBridge	172:65be27845400	3542	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
AnnaBridge	172:65be27845400	3543	}
AnnaBridge	172:65be27845400	3544
AnnaBridge	172:65be27845400	3545	/**
AnnaBridge	172:65be27845400	3546	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	172:65be27845400	3547	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3548	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3549	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	172:65be27845400	3550	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	172:65be27845400	3551	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3552	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3553	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	172:65be27845400	3554	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	172:65be27845400	3555	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3556	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	172:65be27845400	3557	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	172:65be27845400	3558	* @retval None
AnnaBridge	172:65be27845400	3559	*/
AnnaBridge	172:65be27845400	3560	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	172:65be27845400	3561	{
AnnaBridge	172:65be27845400	3562	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	172:65be27845400	3563	}
AnnaBridge	172:65be27845400	3564
AnnaBridge	172:65be27845400	3565	/**
AnnaBridge	172:65be27845400	3566	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	172:65be27845400	3567	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3568	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3569	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	172:65be27845400	3570	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3571	* @retval None
AnnaBridge	172:65be27845400	3572	*/
AnnaBridge	172:65be27845400	3573	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3574	{
AnnaBridge	172:65be27845400	3575	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	172:65be27845400	3576	}
AnnaBridge	172:65be27845400	3577
AnnaBridge	172:65be27845400	3578	/**
AnnaBridge	172:65be27845400	3579	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	172:65be27845400	3580	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3581	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3582	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	172:65be27845400	3583	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3584	* @retval None
AnnaBridge	172:65be27845400	3585	*/
AnnaBridge	172:65be27845400	3586	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3587	{
AnnaBridge	172:65be27845400	3588	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	172:65be27845400	3589	}
AnnaBridge	172:65be27845400	3590
AnnaBridge	172:65be27845400	3591	/**
AnnaBridge	172:65be27845400	3592	* @brief Indicate whether automatic output is enabled.
AnnaBridge	172:65be27845400	3593	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3594	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3595	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	172:65be27845400	3596	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3597	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3598	*/
AnnaBridge	172:65be27845400	3599	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3600	{
AnnaBridge	172:65be27845400	3601	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
AnnaBridge	172:65be27845400	3602	}
AnnaBridge	172:65be27845400	3603
AnnaBridge	172:65be27845400	3604	/**
AnnaBridge	172:65be27845400	3605	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	172:65be27845400	3606	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	172:65be27845400	3607	* software and is reset in case of break or break2 event
AnnaBridge	172:65be27845400	3608	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3609	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3610	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	172:65be27845400	3611	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3612	* @retval None
AnnaBridge	172:65be27845400	3613	*/
AnnaBridge	172:65be27845400	3614	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3615	{
AnnaBridge	172:65be27845400	3616	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	172:65be27845400	3617	}
AnnaBridge	172:65be27845400	3618
AnnaBridge	172:65be27845400	3619	/**
AnnaBridge	172:65be27845400	3620	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	172:65be27845400	3621	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	172:65be27845400	3622	* software and is reset in case of break or break2 event.
AnnaBridge	172:65be27845400	3623	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3624	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3625	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	172:65be27845400	3626	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3627	* @retval None
AnnaBridge	172:65be27845400	3628	*/
AnnaBridge	172:65be27845400	3629	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3630	{
AnnaBridge	172:65be27845400	3631	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	172:65be27845400	3632	}
AnnaBridge	172:65be27845400	3633
AnnaBridge	172:65be27845400	3634	/**
AnnaBridge	172:65be27845400	3635	* @brief Indicates whether outputs are enabled.
AnnaBridge	172:65be27845400	3636	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3637	* a timer instance provides a break input.
AnnaBridge	172:65be27845400	3638	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	172:65be27845400	3639	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3640	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	3641	*/
AnnaBridge	172:65be27845400	3642	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	3643	{
AnnaBridge	172:65be27845400	3644	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
AnnaBridge	172:65be27845400	3645	}
AnnaBridge	172:65be27845400	3646
AnnaBridge	172:65be27845400	3647	/**
AnnaBridge	172:65be27845400	3648	* @brief Enable the signals connected to the designated timer break input.
AnnaBridge	172:65be27845400	3649	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	3650	* or not a timer instance allows for break input selection.
AnnaBridge	172:65be27845400	3651	* @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3652	* OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3653	* OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3654	* OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3655	* OR3 BK2INE LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3656	* OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3657	* OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n
AnnaBridge	172:65be27845400	3658	* OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource
AnnaBridge	172:65be27845400	3659	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3660	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3661	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	172:65be27845400	3662	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	172:65be27845400	3663	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3664	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	172:65be27845400	3665	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	172:65be27845400	3666	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	172:65be27845400	3667	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	172:65be27845400	3668	* @retval None
AnnaBridge	172:65be27845400	3669	*/
AnnaBridge	172:65be27845400	3670	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
AnnaBridge	172:65be27845400	3671	{
AnnaBridge	172:65be27845400	3672	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
AnnaBridge	172:65be27845400	3673	SET_BIT(*pReg , Source);
AnnaBridge	172:65be27845400	3674	}
AnnaBridge	172:65be27845400	3675
AnnaBridge	172:65be27845400	3676	/**
AnnaBridge	172:65be27845400	3677	* @brief Disable the signals connected to the designated timer break input.
AnnaBridge	172:65be27845400	3678	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	3679	* or not a timer instance allows for break input selection.
AnnaBridge	172:65be27845400	3680	* @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3681	* OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3682	* OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3683	* OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3684	* OR3 BK2INE LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3685	* OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3686	* OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n
AnnaBridge	172:65be27845400	3687	* OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource
AnnaBridge	172:65be27845400	3688	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3689	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3690	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	172:65be27845400	3691	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	172:65be27845400	3692	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3693	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	172:65be27845400	3694	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	172:65be27845400	3695	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	172:65be27845400	3696	* @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
AnnaBridge	172:65be27845400	3697	* @retval None
AnnaBridge	172:65be27845400	3698	*/
AnnaBridge	172:65be27845400	3699	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
AnnaBridge	172:65be27845400	3700	{
AnnaBridge	172:65be27845400	3701	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
AnnaBridge	172:65be27845400	3702	CLEAR_BIT(*pReg, Source);
AnnaBridge	172:65be27845400	3703	}
AnnaBridge	172:65be27845400	3704
AnnaBridge	172:65be27845400	3705	/**
AnnaBridge	172:65be27845400	3706	* @brief Set the polarity of the break signal for the timer break input.
AnnaBridge	172:65be27845400	3707	* @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
AnnaBridge	172:65be27845400	3708	* or not a timer instance allows for break input selection.
AnnaBridge	172:65be27845400	3709	* @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3710	* OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3711	* OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3712	* OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3713	* OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
AnnaBridge	172:65be27845400	3714	* OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity
AnnaBridge	172:65be27845400	3715	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3716	* @param BreakInput This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3717	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
AnnaBridge	172:65be27845400	3718	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
AnnaBridge	172:65be27845400	3719	* @param Source This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3720	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
AnnaBridge	172:65be27845400	3721	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
AnnaBridge	172:65be27845400	3722	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
AnnaBridge	172:65be27845400	3723	* @param Polarity This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3724	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
AnnaBridge	172:65be27845400	3725	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
AnnaBridge	172:65be27845400	3726	* @retval None
AnnaBridge	172:65be27845400	3727	*/
AnnaBridge	172:65be27845400	3728	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
AnnaBridge	172:65be27845400	3729	uint32_t Polarity)
AnnaBridge	172:65be27845400	3730	{
AnnaBridge	172:65be27845400	3731	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
AnnaBridge	172:65be27845400	3732	MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE)));
AnnaBridge	172:65be27845400	3733	}
AnnaBridge	172:65be27845400	3734	/**
AnnaBridge	172:65be27845400	3735	* @}
AnnaBridge	172:65be27845400	3736	*/
AnnaBridge	172:65be27845400	3737
AnnaBridge	172:65be27845400	3738	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	172:65be27845400	3739	* @{
AnnaBridge	172:65be27845400	3740	*/
AnnaBridge	172:65be27845400	3741	/**
AnnaBridge	172:65be27845400	3742	* @brief Configures the timer DMA burst feature.
AnnaBridge	172:65be27845400	3743	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	172:65be27845400	3744	* not a timer instance supports the DMA burst mode.
AnnaBridge	172:65be27845400	3745	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	172:65be27845400	3746	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	172:65be27845400	3747	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3748	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3749	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	172:65be27845400	3750	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	172:65be27845400	3751	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	172:65be27845400	3752	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	172:65be27845400	3753	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	172:65be27845400	3754	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	172:65be27845400	3755	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	172:65be27845400	3756	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	172:65be27845400	3757	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	172:65be27845400	3758	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	172:65be27845400	3759	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	172:65be27845400	3760	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	172:65be27845400	3761	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	172:65be27845400	3762	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	172:65be27845400	3763	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	172:65be27845400	3764	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	172:65be27845400	3765	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	172:65be27845400	3766	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	172:65be27845400	3767	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
AnnaBridge	172:65be27845400	3768	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
AnnaBridge	172:65be27845400	3769	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
AnnaBridge	172:65be27845400	3770	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
AnnaBridge	172:65be27845400	3771	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
AnnaBridge	172:65be27845400	3772	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
AnnaBridge	172:65be27845400	3773	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3774	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	172:65be27845400	3775	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	172:65be27845400	3776	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	172:65be27845400	3777	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	172:65be27845400	3778	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	172:65be27845400	3779	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	172:65be27845400	3780	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	172:65be27845400	3781	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	172:65be27845400	3782	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	172:65be27845400	3783	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	172:65be27845400	3784	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	172:65be27845400	3785	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	172:65be27845400	3786	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	172:65be27845400	3787	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	172:65be27845400	3788	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	172:65be27845400	3789	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	172:65be27845400	3790	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	172:65be27845400	3791	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	172:65be27845400	3792	* @retval None
AnnaBridge	172:65be27845400	3793	*/
AnnaBridge	172:65be27845400	3794	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	172:65be27845400	3795	{
AnnaBridge	172:65be27845400	3796	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	172:65be27845400	3797	}
AnnaBridge	172:65be27845400	3798
AnnaBridge	172:65be27845400	3799	/**
AnnaBridge	172:65be27845400	3800	* @}
AnnaBridge	172:65be27845400	3801	*/
AnnaBridge	172:65be27845400	3802
AnnaBridge	172:65be27845400	3803	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	172:65be27845400	3804	* @{
AnnaBridge	172:65be27845400	3805	*/
AnnaBridge	172:65be27845400	3806	/**
AnnaBridge	172:65be27845400	3807	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	172:65be27845400	3808	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	172:65be27845400	3809	* a some timer inputs can be remapped.
AnnaBridge	172:65be27845400	3810	@if STM32L486xx
AnnaBridge	172:65be27845400	3811	* @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3812	* TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3813	* TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3814	* TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3815	* TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3816	* TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3817	* TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3818	* TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3819	* TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3820	* TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3821	* TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3822	* TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3823	* TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3824	* TIM17_OR1 TI1_RMP LL_TIM_SetRemap
AnnaBridge	172:65be27845400	3825	@endif
AnnaBridge	172:65be27845400	3826	@if STM32L443xx
AnnaBridge	172:65be27845400	3827	* @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3828	* TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3829	* TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3830	* TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3831	* TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3832	* TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3833	* TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3834	* TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3835	* TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
AnnaBridge	172:65be27845400	3836	@endif
AnnaBridge	172:65be27845400	3837	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	3838	* @param Remap Remap param depends on the TIMx. Description available only
AnnaBridge	172:65be27845400	3839	* in CHM version of the User Manual (not in .pdf).
AnnaBridge	172:65be27845400	3840	* Otherwise see Reference Manual description of OR registers.
AnnaBridge	172:65be27845400	3841	*
AnnaBridge	172:65be27845400	3842	* Below description summarizes "Timer Instance" and "Remap" param combinations:
AnnaBridge	172:65be27845400	3843	*
AnnaBridge	172:65be27845400	3844	@if STM32L486xx
AnnaBridge	172:65be27845400	3845	* TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
AnnaBridge	172:65be27845400	3846	*
AnnaBridge	172:65be27845400	3847	* . . ADC1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3848	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
AnnaBridge	172:65be27845400	3849	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
AnnaBridge	172:65be27845400	3850	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
AnnaBridge	172:65be27845400	3851	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
AnnaBridge	172:65be27845400	3852	*
AnnaBridge	172:65be27845400	3853	* . . ADC3_RMP can be one of the following values
AnnaBridge	172:65be27845400	3854	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
AnnaBridge	172:65be27845400	3855	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
AnnaBridge	172:65be27845400	3856	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
AnnaBridge	172:65be27845400	3857	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
AnnaBridge	172:65be27845400	3858	*
AnnaBridge	172:65be27845400	3859	* . . TI1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3860	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3861	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
AnnaBridge	172:65be27845400	3862	*
AnnaBridge	172:65be27845400	3863	* TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
AnnaBridge	172:65be27845400	3864	*
AnnaBridge	172:65be27845400	3865	* ITR1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3866	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
AnnaBridge	172:65be27845400	3867	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
AnnaBridge	172:65be27845400	3868	*
AnnaBridge	172:65be27845400	3869	* . . ETR1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3870	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
AnnaBridge	172:65be27845400	3871	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
AnnaBridge	172:65be27845400	3872	*
AnnaBridge	172:65be27845400	3873	* . . TI4_RMP can be one of the following values
AnnaBridge	172:65be27845400	3874	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
AnnaBridge	172:65be27845400	3875	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
AnnaBridge	172:65be27845400	3876	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
AnnaBridge	172:65be27845400	3877	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
AnnaBridge	172:65be27845400	3878	*
AnnaBridge	172:65be27845400	3879	* TIM3: one of the following values
AnnaBridge	172:65be27845400	3880	*
AnnaBridge	172:65be27845400	3881	* @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3882	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
AnnaBridge	172:65be27845400	3883	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
AnnaBridge	172:65be27845400	3884	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
AnnaBridge	172:65be27845400	3885	*
AnnaBridge	172:65be27845400	3886	* TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
AnnaBridge	172:65be27845400	3887	*
AnnaBridge	172:65be27845400	3888	* . . ADC1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3889	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
AnnaBridge	172:65be27845400	3890	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
AnnaBridge	172:65be27845400	3891	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
AnnaBridge	172:65be27845400	3892	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
AnnaBridge	172:65be27845400	3893	*
AnnaBridge	172:65be27845400	3894	* . . ADC3_RMP can be one of the following values
AnnaBridge	172:65be27845400	3895	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
AnnaBridge	172:65be27845400	3896	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
AnnaBridge	172:65be27845400	3897	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
AnnaBridge	172:65be27845400	3898	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
AnnaBridge	172:65be27845400	3899	*
AnnaBridge	172:65be27845400	3900	* . . TI1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3901	* @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3902	* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
AnnaBridge	172:65be27845400	3903	*
AnnaBridge	172:65be27845400	3904	* TIM15: any combination of TI1_RMP, ENCODER_MODE where
AnnaBridge	172:65be27845400	3905	*
AnnaBridge	172:65be27845400	3906	* . . TI1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3907	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3908	* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
AnnaBridge	172:65be27845400	3909	*
AnnaBridge	172:65be27845400	3910	* . . ENCODER_MODE can be one of the following values
AnnaBridge	172:65be27845400	3911	* @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
AnnaBridge	172:65be27845400	3912	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
AnnaBridge	172:65be27845400	3913	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
AnnaBridge	172:65be27845400	3914	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
AnnaBridge	172:65be27845400	3915	*
AnnaBridge	172:65be27845400	3916	* TIM16: one of the following values
AnnaBridge	172:65be27845400	3917	*
AnnaBridge	172:65be27845400	3918	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3919	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
AnnaBridge	172:65be27845400	3920	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
AnnaBridge	172:65be27845400	3921	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
AnnaBridge	172:65be27845400	3922	* @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
AnnaBridge	172:65be27845400	3923	* @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
AnnaBridge	172:65be27845400	3924	* @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
AnnaBridge	172:65be27845400	3925	*
AnnaBridge	172:65be27845400	3926	* TIM17: one of the following values
AnnaBridge	172:65be27845400	3927	*
AnnaBridge	172:65be27845400	3928	* @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3929	* @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
AnnaBridge	172:65be27845400	3930	* @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
AnnaBridge	172:65be27845400	3931	* @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
AnnaBridge	172:65be27845400	3932	@endif
AnnaBridge	172:65be27845400	3933	@if STM32L443xx
AnnaBridge	172:65be27845400	3934	* TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
AnnaBridge	172:65be27845400	3935	*
AnnaBridge	172:65be27845400	3936	* . . ADC1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3937	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
AnnaBridge	172:65be27845400	3938	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
AnnaBridge	172:65be27845400	3939	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
AnnaBridge	172:65be27845400	3940	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
AnnaBridge	172:65be27845400	3941	*
AnnaBridge	172:65be27845400	3942	* . . TI1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3943	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3944	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
AnnaBridge	172:65be27845400	3945	*
AnnaBridge	172:65be27845400	3946	* TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
AnnaBridge	172:65be27845400	3947	*
AnnaBridge	172:65be27845400	3948	* ITR1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3949	* @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE
AnnaBridge	172:65be27845400	3950	* @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF
AnnaBridge	172:65be27845400	3951	*
AnnaBridge	172:65be27845400	3952	* . . ETR1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3953	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
AnnaBridge	172:65be27845400	3954	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
AnnaBridge	172:65be27845400	3955	*
AnnaBridge	172:65be27845400	3956	* . . TI4_RMP can be one of the following values
AnnaBridge	172:65be27845400	3957	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
AnnaBridge	172:65be27845400	3958	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
AnnaBridge	172:65be27845400	3959	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
AnnaBridge	172:65be27845400	3960	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
AnnaBridge	172:65be27845400	3961	*
AnnaBridge	172:65be27845400	3962	* TIM15: any combination of TI1_RMP, ENCODER_MODE where
AnnaBridge	172:65be27845400	3963	*
AnnaBridge	172:65be27845400	3964	* . . TI1_RMP can be one of the following values
AnnaBridge	172:65be27845400	3965	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3966	* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
AnnaBridge	172:65be27845400	3967	*
AnnaBridge	172:65be27845400	3968	* . . ENCODER_MODE can be one of the following values
AnnaBridge	172:65be27845400	3969	* @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
AnnaBridge	172:65be27845400	3970	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
AnnaBridge	172:65be27845400	3971	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
AnnaBridge	172:65be27845400	3972	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
AnnaBridge	172:65be27845400	3973	*
AnnaBridge	172:65be27845400	3974	* TIM16: one of the following values
AnnaBridge	172:65be27845400	3975	*
AnnaBridge	172:65be27845400	3976	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
AnnaBridge	172:65be27845400	3977	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
AnnaBridge	172:65be27845400	3978	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
AnnaBridge	172:65be27845400	3979	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
AnnaBridge	172:65be27845400	3980	* @arg @ref LL_TIM_TIM16_TI1_RMP_MSI
AnnaBridge	172:65be27845400	3981	* @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
AnnaBridge	172:65be27845400	3982	* @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
AnnaBridge	172:65be27845400	3983	@endif
AnnaBridge	172:65be27845400	3984	* @retval None
AnnaBridge	172:65be27845400	3985	*/
AnnaBridge	172:65be27845400	3986	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	172:65be27845400	3987	{
AnnaBridge	172:65be27845400	3988	MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
AnnaBridge	172:65be27845400	3989	}
AnnaBridge	172:65be27845400	3990
AnnaBridge	172:65be27845400	3991	/**
AnnaBridge	172:65be27845400	3992	* @}
AnnaBridge	172:65be27845400	3993	*/
AnnaBridge	172:65be27845400	3994
AnnaBridge	172:65be27845400	3995	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
AnnaBridge	172:65be27845400	3996	* @{
AnnaBridge	172:65be27845400	3997	*/
AnnaBridge	172:65be27845400	3998	/**
AnnaBridge	172:65be27845400	3999	* @brief Set the OCREF clear input source
AnnaBridge	172:65be27845400	4000	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
AnnaBridge	172:65be27845400	4001	* @note This function can only be used in Output compare and PWM modes.
AnnaBridge	172:65be27845400	4002	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
AnnaBridge	172:65be27845400	4003	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4004	* @param OCRefClearInputSource This parameter can be one of the following values:
AnnaBridge	172:65be27845400	4005	* @arg @ref LL_TIM_OCREF_CLR_INT_NC
AnnaBridge	172:65be27845400	4006	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
AnnaBridge	172:65be27845400	4007	* @retval None
AnnaBridge	172:65be27845400	4008	*/
AnnaBridge	172:65be27845400	4009	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
AnnaBridge	172:65be27845400	4010	{
AnnaBridge	172:65be27845400	4011	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
AnnaBridge	172:65be27845400	4012	}
AnnaBridge	172:65be27845400	4013	/**
AnnaBridge	172:65be27845400	4014	* @}
AnnaBridge	172:65be27845400	4015	*/
AnnaBridge	172:65be27845400	4016
AnnaBridge	172:65be27845400	4017	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	172:65be27845400	4018	* @{
AnnaBridge	172:65be27845400	4019	*/
AnnaBridge	172:65be27845400	4020	/**
AnnaBridge	172:65be27845400	4021	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	172:65be27845400	4022	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	172:65be27845400	4023	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4024	* @retval None
AnnaBridge	172:65be27845400	4025	*/
AnnaBridge	172:65be27845400	4026	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4027	{
AnnaBridge	172:65be27845400	4028	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	172:65be27845400	4029	}
AnnaBridge	172:65be27845400	4030
AnnaBridge	172:65be27845400	4031	/**
AnnaBridge	172:65be27845400	4032	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	172:65be27845400	4033	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	172:65be27845400	4034	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4035	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4036	*/
AnnaBridge	172:65be27845400	4037	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4038	{
AnnaBridge	172:65be27845400	4039	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	172:65be27845400	4040	}
AnnaBridge	172:65be27845400	4041
AnnaBridge	172:65be27845400	4042	/**
AnnaBridge	172:65be27845400	4043	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	172:65be27845400	4044	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	172:65be27845400	4045	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4046	* @retval None
AnnaBridge	172:65be27845400	4047	*/
AnnaBridge	172:65be27845400	4048	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4049	{
AnnaBridge	172:65be27845400	4050	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	172:65be27845400	4051	}
AnnaBridge	172:65be27845400	4052
AnnaBridge	172:65be27845400	4053	/**
AnnaBridge	172:65be27845400	4054	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	172:65be27845400	4055	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	172:65be27845400	4056	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4057	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4058	*/
AnnaBridge	172:65be27845400	4059	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4060	{
AnnaBridge	172:65be27845400	4061	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	172:65be27845400	4062	}
AnnaBridge	172:65be27845400	4063
AnnaBridge	172:65be27845400	4064	/**
AnnaBridge	172:65be27845400	4065	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	172:65be27845400	4066	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	172:65be27845400	4067	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4068	* @retval None
AnnaBridge	172:65be27845400	4069	*/
AnnaBridge	172:65be27845400	4070	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4071	{
AnnaBridge	172:65be27845400	4072	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	172:65be27845400	4073	}
AnnaBridge	172:65be27845400	4074
AnnaBridge	172:65be27845400	4075	/**
AnnaBridge	172:65be27845400	4076	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	172:65be27845400	4077	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	172:65be27845400	4078	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4079	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4080	*/
AnnaBridge	172:65be27845400	4081	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4082	{
AnnaBridge	172:65be27845400	4083	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	172:65be27845400	4084	}
AnnaBridge	172:65be27845400	4085
AnnaBridge	172:65be27845400	4086	/**
AnnaBridge	172:65be27845400	4087	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	172:65be27845400	4088	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	172:65be27845400	4089	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4090	* @retval None
AnnaBridge	172:65be27845400	4091	*/
AnnaBridge	172:65be27845400	4092	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4093	{
AnnaBridge	172:65be27845400	4094	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	172:65be27845400	4095	}
AnnaBridge	172:65be27845400	4096
AnnaBridge	172:65be27845400	4097	/**
AnnaBridge	172:65be27845400	4098	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	172:65be27845400	4099	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	172:65be27845400	4100	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4101	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4102	*/
AnnaBridge	172:65be27845400	4103	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4104	{
AnnaBridge	172:65be27845400	4105	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	172:65be27845400	4106	}
AnnaBridge	172:65be27845400	4107
AnnaBridge	172:65be27845400	4108	/**
AnnaBridge	172:65be27845400	4109	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	172:65be27845400	4110	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	172:65be27845400	4111	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4112	* @retval None
AnnaBridge	172:65be27845400	4113	*/
AnnaBridge	172:65be27845400	4114	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4115	{
AnnaBridge	172:65be27845400	4116	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	172:65be27845400	4117	}
AnnaBridge	172:65be27845400	4118
AnnaBridge	172:65be27845400	4119	/**
AnnaBridge	172:65be27845400	4120	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	172:65be27845400	4121	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	172:65be27845400	4122	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4123	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4124	*/
AnnaBridge	172:65be27845400	4125	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4126	{
AnnaBridge	172:65be27845400	4127	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	172:65be27845400	4128	}
AnnaBridge	172:65be27845400	4129
AnnaBridge	172:65be27845400	4130	/**
AnnaBridge	172:65be27845400	4131	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
AnnaBridge	172:65be27845400	4132	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
AnnaBridge	172:65be27845400	4133	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4134	* @retval None
AnnaBridge	172:65be27845400	4135	*/
AnnaBridge	172:65be27845400	4136	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4137	{
AnnaBridge	172:65be27845400	4138	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
AnnaBridge	172:65be27845400	4139	}
AnnaBridge	172:65be27845400	4140
AnnaBridge	172:65be27845400	4141	/**
AnnaBridge	172:65be27845400	4142	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
AnnaBridge	172:65be27845400	4143	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
AnnaBridge	172:65be27845400	4144	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4145	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4146	*/
AnnaBridge	172:65be27845400	4147	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4148	{
AnnaBridge	172:65be27845400	4149	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
AnnaBridge	172:65be27845400	4150	}
AnnaBridge	172:65be27845400	4151
AnnaBridge	172:65be27845400	4152	/**
AnnaBridge	172:65be27845400	4153	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
AnnaBridge	172:65be27845400	4154	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
AnnaBridge	172:65be27845400	4155	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4156	* @retval None
AnnaBridge	172:65be27845400	4157	*/
AnnaBridge	172:65be27845400	4158	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4159	{
AnnaBridge	172:65be27845400	4160	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
AnnaBridge	172:65be27845400	4161	}
AnnaBridge	172:65be27845400	4162
AnnaBridge	172:65be27845400	4163	/**
AnnaBridge	172:65be27845400	4164	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
AnnaBridge	172:65be27845400	4165	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
AnnaBridge	172:65be27845400	4166	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4167	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4168	*/
AnnaBridge	172:65be27845400	4169	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4170	{
AnnaBridge	172:65be27845400	4171	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
AnnaBridge	172:65be27845400	4172	}
AnnaBridge	172:65be27845400	4173
AnnaBridge	172:65be27845400	4174	/**
AnnaBridge	172:65be27845400	4175	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	172:65be27845400	4176	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	172:65be27845400	4177	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4178	* @retval None
AnnaBridge	172:65be27845400	4179	*/
AnnaBridge	172:65be27845400	4180	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4181	{
AnnaBridge	172:65be27845400	4182	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	172:65be27845400	4183	}
AnnaBridge	172:65be27845400	4184
AnnaBridge	172:65be27845400	4185	/**
AnnaBridge	172:65be27845400	4186	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	172:65be27845400	4187	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	172:65be27845400	4188	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4189	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4190	*/
AnnaBridge	172:65be27845400	4191	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4192	{
AnnaBridge	172:65be27845400	4193	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
AnnaBridge	172:65be27845400	4194	}
AnnaBridge	172:65be27845400	4195
AnnaBridge	172:65be27845400	4196	/**
AnnaBridge	172:65be27845400	4197	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	172:65be27845400	4198	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	172:65be27845400	4199	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4200	* @retval None
AnnaBridge	172:65be27845400	4201	*/
AnnaBridge	172:65be27845400	4202	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4203	{
AnnaBridge	172:65be27845400	4204	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	172:65be27845400	4205	}
AnnaBridge	172:65be27845400	4206
AnnaBridge	172:65be27845400	4207	/**
AnnaBridge	172:65be27845400	4208	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	172:65be27845400	4209	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	172:65be27845400	4210	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4211	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4212	*/
AnnaBridge	172:65be27845400	4213	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4214	{
AnnaBridge	172:65be27845400	4215	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	172:65be27845400	4216	}
AnnaBridge	172:65be27845400	4217
AnnaBridge	172:65be27845400	4218	/**
AnnaBridge	172:65be27845400	4219	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	172:65be27845400	4220	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	172:65be27845400	4221	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4222	* @retval None
AnnaBridge	172:65be27845400	4223	*/
AnnaBridge	172:65be27845400	4224	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4225	{
AnnaBridge	172:65be27845400	4226	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	172:65be27845400	4227	}
AnnaBridge	172:65be27845400	4228
AnnaBridge	172:65be27845400	4229	/**
AnnaBridge	172:65be27845400	4230	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	172:65be27845400	4231	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	172:65be27845400	4232	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4233	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4234	*/
AnnaBridge	172:65be27845400	4235	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4236	{
AnnaBridge	172:65be27845400	4237	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
AnnaBridge	172:65be27845400	4238	}
AnnaBridge	172:65be27845400	4239
AnnaBridge	172:65be27845400	4240	/**
AnnaBridge	172:65be27845400	4241	* @brief Clear the break 2 interrupt flag (B2IF).
AnnaBridge	172:65be27845400	4242	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
AnnaBridge	172:65be27845400	4243	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4244	* @retval None
AnnaBridge	172:65be27845400	4245	*/
AnnaBridge	172:65be27845400	4246	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4247	{
AnnaBridge	172:65be27845400	4248	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
AnnaBridge	172:65be27845400	4249	}
AnnaBridge	172:65be27845400	4250
AnnaBridge	172:65be27845400	4251	/**
AnnaBridge	172:65be27845400	4252	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
AnnaBridge	172:65be27845400	4253	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
AnnaBridge	172:65be27845400	4254	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4255	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4256	*/
AnnaBridge	172:65be27845400	4257	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4258	{
AnnaBridge	172:65be27845400	4259	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
AnnaBridge	172:65be27845400	4260	}
AnnaBridge	172:65be27845400	4261
AnnaBridge	172:65be27845400	4262	/**
AnnaBridge	172:65be27845400	4263	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	172:65be27845400	4264	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	172:65be27845400	4265	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4266	* @retval None
AnnaBridge	172:65be27845400	4267	*/
AnnaBridge	172:65be27845400	4268	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4269	{
AnnaBridge	172:65be27845400	4270	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	172:65be27845400	4271	}
AnnaBridge	172:65be27845400	4272
AnnaBridge	172:65be27845400	4273	/**
AnnaBridge	172:65be27845400	4274	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	172:65be27845400	4275	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	172:65be27845400	4276	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4277	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4278	*/
AnnaBridge	172:65be27845400	4279	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4280	{
AnnaBridge	172:65be27845400	4281	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	172:65be27845400	4282	}
AnnaBridge	172:65be27845400	4283
AnnaBridge	172:65be27845400	4284	/**
AnnaBridge	172:65be27845400	4285	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	172:65be27845400	4286	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	172:65be27845400	4287	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4288	* @retval None
AnnaBridge	172:65be27845400	4289	*/
AnnaBridge	172:65be27845400	4290	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4291	{
AnnaBridge	172:65be27845400	4292	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	172:65be27845400	4293	}
AnnaBridge	172:65be27845400	4294
AnnaBridge	172:65be27845400	4295	/**
AnnaBridge	172:65be27845400	4296	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	172:65be27845400	4297	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	172:65be27845400	4298	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4299	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4300	*/
AnnaBridge	172:65be27845400	4301	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4302	{
AnnaBridge	172:65be27845400	4303	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	172:65be27845400	4304	}
AnnaBridge	172:65be27845400	4305
AnnaBridge	172:65be27845400	4306	/**
AnnaBridge	172:65be27845400	4307	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	172:65be27845400	4308	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	172:65be27845400	4309	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4310	* @retval None
AnnaBridge	172:65be27845400	4311	*/
AnnaBridge	172:65be27845400	4312	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4313	{
AnnaBridge	172:65be27845400	4314	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	172:65be27845400	4315	}
AnnaBridge	172:65be27845400	4316
AnnaBridge	172:65be27845400	4317	/**
AnnaBridge	172:65be27845400	4318	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	172:65be27845400	4319	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	172:65be27845400	4320	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4321	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4322	*/
AnnaBridge	172:65be27845400	4323	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4324	{
AnnaBridge	172:65be27845400	4325	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	172:65be27845400	4326	}
AnnaBridge	172:65be27845400	4327
AnnaBridge	172:65be27845400	4328	/**
AnnaBridge	172:65be27845400	4329	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	172:65be27845400	4330	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	172:65be27845400	4331	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4332	* @retval None
AnnaBridge	172:65be27845400	4333	*/
AnnaBridge	172:65be27845400	4334	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4335	{
AnnaBridge	172:65be27845400	4336	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	172:65be27845400	4337	}
AnnaBridge	172:65be27845400	4338
AnnaBridge	172:65be27845400	4339	/**
AnnaBridge	172:65be27845400	4340	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	172:65be27845400	4341	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	172:65be27845400	4342	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4343	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4344	*/
AnnaBridge	172:65be27845400	4345	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4346	{
AnnaBridge	172:65be27845400	4347	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	172:65be27845400	4348	}
AnnaBridge	172:65be27845400	4349
AnnaBridge	172:65be27845400	4350	/**
AnnaBridge	172:65be27845400	4351	* @brief Clear the system break interrupt flag (SBIF).
AnnaBridge	172:65be27845400	4352	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
AnnaBridge	172:65be27845400	4353	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4354	* @retval None
AnnaBridge	172:65be27845400	4355	*/
AnnaBridge	172:65be27845400	4356	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4357	{
AnnaBridge	172:65be27845400	4358	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
AnnaBridge	172:65be27845400	4359	}
AnnaBridge	172:65be27845400	4360
AnnaBridge	172:65be27845400	4361	/**
AnnaBridge	172:65be27845400	4362	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
AnnaBridge	172:65be27845400	4363	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
AnnaBridge	172:65be27845400	4364	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4365	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4366	*/
AnnaBridge	172:65be27845400	4367	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4368	{
AnnaBridge	172:65be27845400	4369	return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
AnnaBridge	172:65be27845400	4370	}
AnnaBridge	172:65be27845400	4371
AnnaBridge	172:65be27845400	4372	/**
AnnaBridge	172:65be27845400	4373	* @}
AnnaBridge	172:65be27845400	4374	*/
AnnaBridge	172:65be27845400	4375
AnnaBridge	172:65be27845400	4376	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	172:65be27845400	4377	* @{
AnnaBridge	172:65be27845400	4378	*/
AnnaBridge	172:65be27845400	4379	/**
AnnaBridge	172:65be27845400	4380	* @brief Enable update interrupt (UIE).
AnnaBridge	172:65be27845400	4381	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	172:65be27845400	4382	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4383	* @retval None
AnnaBridge	172:65be27845400	4384	*/
AnnaBridge	172:65be27845400	4385	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4386	{
AnnaBridge	172:65be27845400	4387	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	172:65be27845400	4388	}
AnnaBridge	172:65be27845400	4389
AnnaBridge	172:65be27845400	4390	/**
AnnaBridge	172:65be27845400	4391	* @brief Disable update interrupt (UIE).
AnnaBridge	172:65be27845400	4392	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	172:65be27845400	4393	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4394	* @retval None
AnnaBridge	172:65be27845400	4395	*/
AnnaBridge	172:65be27845400	4396	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4397	{
AnnaBridge	172:65be27845400	4398	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	172:65be27845400	4399	}
AnnaBridge	172:65be27845400	4400
AnnaBridge	172:65be27845400	4401	/**
AnnaBridge	172:65be27845400	4402	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	172:65be27845400	4403	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	172:65be27845400	4404	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4405	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4406	*/
AnnaBridge	172:65be27845400	4407	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4408	{
AnnaBridge	172:65be27845400	4409	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	172:65be27845400	4410	}
AnnaBridge	172:65be27845400	4411
AnnaBridge	172:65be27845400	4412	/**
AnnaBridge	172:65be27845400	4413	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	172:65be27845400	4414	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	172:65be27845400	4415	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4416	* @retval None
AnnaBridge	172:65be27845400	4417	*/
AnnaBridge	172:65be27845400	4418	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4419	{
AnnaBridge	172:65be27845400	4420	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	172:65be27845400	4421	}
AnnaBridge	172:65be27845400	4422
AnnaBridge	172:65be27845400	4423	/**
AnnaBridge	172:65be27845400	4424	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	172:65be27845400	4425	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	172:65be27845400	4426	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4427	* @retval None
AnnaBridge	172:65be27845400	4428	*/
AnnaBridge	172:65be27845400	4429	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4430	{
AnnaBridge	172:65be27845400	4431	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	172:65be27845400	4432	}
AnnaBridge	172:65be27845400	4433
AnnaBridge	172:65be27845400	4434	/**
AnnaBridge	172:65be27845400	4435	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	172:65be27845400	4436	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	172:65be27845400	4437	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4438	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4439	*/
AnnaBridge	172:65be27845400	4440	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4441	{
AnnaBridge	172:65be27845400	4442	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	172:65be27845400	4443	}
AnnaBridge	172:65be27845400	4444
AnnaBridge	172:65be27845400	4445	/**
AnnaBridge	172:65be27845400	4446	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	172:65be27845400	4447	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	172:65be27845400	4448	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4449	* @retval None
AnnaBridge	172:65be27845400	4450	*/
AnnaBridge	172:65be27845400	4451	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4452	{
AnnaBridge	172:65be27845400	4453	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	172:65be27845400	4454	}
AnnaBridge	172:65be27845400	4455
AnnaBridge	172:65be27845400	4456	/**
AnnaBridge	172:65be27845400	4457	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	172:65be27845400	4458	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	172:65be27845400	4459	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4460	* @retval None
AnnaBridge	172:65be27845400	4461	*/
AnnaBridge	172:65be27845400	4462	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4463	{
AnnaBridge	172:65be27845400	4464	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	172:65be27845400	4465	}
AnnaBridge	172:65be27845400	4466
AnnaBridge	172:65be27845400	4467	/**
AnnaBridge	172:65be27845400	4468	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	172:65be27845400	4469	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	172:65be27845400	4470	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4471	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4472	*/
AnnaBridge	172:65be27845400	4473	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4474	{
AnnaBridge	172:65be27845400	4475	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	172:65be27845400	4476	}
AnnaBridge	172:65be27845400	4477
AnnaBridge	172:65be27845400	4478	/**
AnnaBridge	172:65be27845400	4479	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	172:65be27845400	4480	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	172:65be27845400	4481	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4482	* @retval None
AnnaBridge	172:65be27845400	4483	*/
AnnaBridge	172:65be27845400	4484	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4485	{
AnnaBridge	172:65be27845400	4486	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	172:65be27845400	4487	}
AnnaBridge	172:65be27845400	4488
AnnaBridge	172:65be27845400	4489	/**
AnnaBridge	172:65be27845400	4490	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	172:65be27845400	4491	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	172:65be27845400	4492	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4493	* @retval None
AnnaBridge	172:65be27845400	4494	*/
AnnaBridge	172:65be27845400	4495	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4496	{
AnnaBridge	172:65be27845400	4497	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	172:65be27845400	4498	}
AnnaBridge	172:65be27845400	4499
AnnaBridge	172:65be27845400	4500	/**
AnnaBridge	172:65be27845400	4501	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	172:65be27845400	4502	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	172:65be27845400	4503	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4504	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4505	*/
AnnaBridge	172:65be27845400	4506	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4507	{
AnnaBridge	172:65be27845400	4508	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	172:65be27845400	4509	}
AnnaBridge	172:65be27845400	4510
AnnaBridge	172:65be27845400	4511	/**
AnnaBridge	172:65be27845400	4512	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	172:65be27845400	4513	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	172:65be27845400	4514	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4515	* @retval None
AnnaBridge	172:65be27845400	4516	*/
AnnaBridge	172:65be27845400	4517	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4518	{
AnnaBridge	172:65be27845400	4519	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	172:65be27845400	4520	}
AnnaBridge	172:65be27845400	4521
AnnaBridge	172:65be27845400	4522	/**
AnnaBridge	172:65be27845400	4523	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	172:65be27845400	4524	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	172:65be27845400	4525	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4526	* @retval None
AnnaBridge	172:65be27845400	4527	*/
AnnaBridge	172:65be27845400	4528	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4529	{
AnnaBridge	172:65be27845400	4530	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	172:65be27845400	4531	}
AnnaBridge	172:65be27845400	4532
AnnaBridge	172:65be27845400	4533	/**
AnnaBridge	172:65be27845400	4534	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	172:65be27845400	4535	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	172:65be27845400	4536	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4537	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4538	*/
AnnaBridge	172:65be27845400	4539	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4540	{
AnnaBridge	172:65be27845400	4541	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	172:65be27845400	4542	}
AnnaBridge	172:65be27845400	4543
AnnaBridge	172:65be27845400	4544	/**
AnnaBridge	172:65be27845400	4545	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	172:65be27845400	4546	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	172:65be27845400	4547	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4548	* @retval None
AnnaBridge	172:65be27845400	4549	*/
AnnaBridge	172:65be27845400	4550	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4551	{
AnnaBridge	172:65be27845400	4552	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	172:65be27845400	4553	}
AnnaBridge	172:65be27845400	4554
AnnaBridge	172:65be27845400	4555	/**
AnnaBridge	172:65be27845400	4556	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	172:65be27845400	4557	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	172:65be27845400	4558	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4559	* @retval None
AnnaBridge	172:65be27845400	4560	*/
AnnaBridge	172:65be27845400	4561	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4562	{
AnnaBridge	172:65be27845400	4563	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	172:65be27845400	4564	}
AnnaBridge	172:65be27845400	4565
AnnaBridge	172:65be27845400	4566	/**
AnnaBridge	172:65be27845400	4567	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	172:65be27845400	4568	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	172:65be27845400	4569	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4570	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4571	*/
AnnaBridge	172:65be27845400	4572	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4573	{
AnnaBridge	172:65be27845400	4574	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
AnnaBridge	172:65be27845400	4575	}
AnnaBridge	172:65be27845400	4576
AnnaBridge	172:65be27845400	4577	/**
AnnaBridge	172:65be27845400	4578	* @brief Enable trigger interrupt (TIE).
AnnaBridge	172:65be27845400	4579	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	172:65be27845400	4580	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4581	* @retval None
AnnaBridge	172:65be27845400	4582	*/
AnnaBridge	172:65be27845400	4583	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4584	{
AnnaBridge	172:65be27845400	4585	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	172:65be27845400	4586	}
AnnaBridge	172:65be27845400	4587
AnnaBridge	172:65be27845400	4588	/**
AnnaBridge	172:65be27845400	4589	* @brief Disable trigger interrupt (TIE).
AnnaBridge	172:65be27845400	4590	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	172:65be27845400	4591	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4592	* @retval None
AnnaBridge	172:65be27845400	4593	*/
AnnaBridge	172:65be27845400	4594	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4595	{
AnnaBridge	172:65be27845400	4596	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	172:65be27845400	4597	}
AnnaBridge	172:65be27845400	4598
AnnaBridge	172:65be27845400	4599	/**
AnnaBridge	172:65be27845400	4600	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	172:65be27845400	4601	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	172:65be27845400	4602	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4603	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4604	*/
AnnaBridge	172:65be27845400	4605	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4606	{
AnnaBridge	172:65be27845400	4607	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	172:65be27845400	4608	}
AnnaBridge	172:65be27845400	4609
AnnaBridge	172:65be27845400	4610	/**
AnnaBridge	172:65be27845400	4611	* @brief Enable break interrupt (BIE).
AnnaBridge	172:65be27845400	4612	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	172:65be27845400	4613	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4614	* @retval None
AnnaBridge	172:65be27845400	4615	*/
AnnaBridge	172:65be27845400	4616	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4617	{
AnnaBridge	172:65be27845400	4618	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	172:65be27845400	4619	}
AnnaBridge	172:65be27845400	4620
AnnaBridge	172:65be27845400	4621	/**
AnnaBridge	172:65be27845400	4622	* @brief Disable break interrupt (BIE).
AnnaBridge	172:65be27845400	4623	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	172:65be27845400	4624	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4625	* @retval None
AnnaBridge	172:65be27845400	4626	*/
AnnaBridge	172:65be27845400	4627	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4628	{
AnnaBridge	172:65be27845400	4629	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	172:65be27845400	4630	}
AnnaBridge	172:65be27845400	4631
AnnaBridge	172:65be27845400	4632	/**
AnnaBridge	172:65be27845400	4633	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	172:65be27845400	4634	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	172:65be27845400	4635	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4636	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4637	*/
AnnaBridge	172:65be27845400	4638	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4639	{
AnnaBridge	172:65be27845400	4640	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
AnnaBridge	172:65be27845400	4641	}
AnnaBridge	172:65be27845400	4642
AnnaBridge	172:65be27845400	4643	/**
AnnaBridge	172:65be27845400	4644	* @}
AnnaBridge	172:65be27845400	4645	*/
AnnaBridge	172:65be27845400	4646
AnnaBridge	172:65be27845400	4647	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	172:65be27845400	4648	* @{
AnnaBridge	172:65be27845400	4649	*/
AnnaBridge	172:65be27845400	4650	/**
AnnaBridge	172:65be27845400	4651	* @brief Enable update DMA request (UDE).
AnnaBridge	172:65be27845400	4652	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	172:65be27845400	4653	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4654	* @retval None
AnnaBridge	172:65be27845400	4655	*/
AnnaBridge	172:65be27845400	4656	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4657	{
AnnaBridge	172:65be27845400	4658	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	172:65be27845400	4659	}
AnnaBridge	172:65be27845400	4660
AnnaBridge	172:65be27845400	4661	/**
AnnaBridge	172:65be27845400	4662	* @brief Disable update DMA request (UDE).
AnnaBridge	172:65be27845400	4663	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	172:65be27845400	4664	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4665	* @retval None
AnnaBridge	172:65be27845400	4666	*/
AnnaBridge	172:65be27845400	4667	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4668	{
AnnaBridge	172:65be27845400	4669	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	172:65be27845400	4670	}
AnnaBridge	172:65be27845400	4671
AnnaBridge	172:65be27845400	4672	/**
AnnaBridge	172:65be27845400	4673	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	172:65be27845400	4674	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	172:65be27845400	4675	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4676	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4677	*/
AnnaBridge	172:65be27845400	4678	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4679	{
AnnaBridge	172:65be27845400	4680	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	172:65be27845400	4681	}
AnnaBridge	172:65be27845400	4682
AnnaBridge	172:65be27845400	4683	/**
AnnaBridge	172:65be27845400	4684	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	172:65be27845400	4685	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	172:65be27845400	4686	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4687	* @retval None
AnnaBridge	172:65be27845400	4688	*/
AnnaBridge	172:65be27845400	4689	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4690	{
AnnaBridge	172:65be27845400	4691	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	172:65be27845400	4692	}
AnnaBridge	172:65be27845400	4693
AnnaBridge	172:65be27845400	4694	/**
AnnaBridge	172:65be27845400	4695	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	172:65be27845400	4696	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	172:65be27845400	4697	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4698	* @retval None
AnnaBridge	172:65be27845400	4699	*/
AnnaBridge	172:65be27845400	4700	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4701	{
AnnaBridge	172:65be27845400	4702	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	172:65be27845400	4703	}
AnnaBridge	172:65be27845400	4704
AnnaBridge	172:65be27845400	4705	/**
AnnaBridge	172:65be27845400	4706	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	172:65be27845400	4707	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	172:65be27845400	4708	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4709	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4710	*/
AnnaBridge	172:65be27845400	4711	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4712	{
AnnaBridge	172:65be27845400	4713	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	172:65be27845400	4714	}
AnnaBridge	172:65be27845400	4715
AnnaBridge	172:65be27845400	4716	/**
AnnaBridge	172:65be27845400	4717	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	172:65be27845400	4718	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	172:65be27845400	4719	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4720	* @retval None
AnnaBridge	172:65be27845400	4721	*/
AnnaBridge	172:65be27845400	4722	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4723	{
AnnaBridge	172:65be27845400	4724	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	172:65be27845400	4725	}
AnnaBridge	172:65be27845400	4726
AnnaBridge	172:65be27845400	4727	/**
AnnaBridge	172:65be27845400	4728	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	172:65be27845400	4729	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	172:65be27845400	4730	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4731	* @retval None
AnnaBridge	172:65be27845400	4732	*/
AnnaBridge	172:65be27845400	4733	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4734	{
AnnaBridge	172:65be27845400	4735	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	172:65be27845400	4736	}
AnnaBridge	172:65be27845400	4737
AnnaBridge	172:65be27845400	4738	/**
AnnaBridge	172:65be27845400	4739	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	172:65be27845400	4740	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	172:65be27845400	4741	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4742	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4743	*/
AnnaBridge	172:65be27845400	4744	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4745	{
AnnaBridge	172:65be27845400	4746	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	172:65be27845400	4747	}
AnnaBridge	172:65be27845400	4748
AnnaBridge	172:65be27845400	4749	/**
AnnaBridge	172:65be27845400	4750	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	172:65be27845400	4751	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	172:65be27845400	4752	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4753	* @retval None
AnnaBridge	172:65be27845400	4754	*/
AnnaBridge	172:65be27845400	4755	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4756	{
AnnaBridge	172:65be27845400	4757	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	172:65be27845400	4758	}
AnnaBridge	172:65be27845400	4759
AnnaBridge	172:65be27845400	4760	/**
AnnaBridge	172:65be27845400	4761	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	172:65be27845400	4762	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	172:65be27845400	4763	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4764	* @retval None
AnnaBridge	172:65be27845400	4765	*/
AnnaBridge	172:65be27845400	4766	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4767	{
AnnaBridge	172:65be27845400	4768	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	172:65be27845400	4769	}
AnnaBridge	172:65be27845400	4770
AnnaBridge	172:65be27845400	4771	/**
AnnaBridge	172:65be27845400	4772	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	172:65be27845400	4773	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	172:65be27845400	4774	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4775	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4776	*/
AnnaBridge	172:65be27845400	4777	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4778	{
AnnaBridge	172:65be27845400	4779	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	172:65be27845400	4780	}
AnnaBridge	172:65be27845400	4781
AnnaBridge	172:65be27845400	4782	/**
AnnaBridge	172:65be27845400	4783	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	172:65be27845400	4784	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	172:65be27845400	4785	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4786	* @retval None
AnnaBridge	172:65be27845400	4787	*/
AnnaBridge	172:65be27845400	4788	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4789	{
AnnaBridge	172:65be27845400	4790	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	172:65be27845400	4791	}
AnnaBridge	172:65be27845400	4792
AnnaBridge	172:65be27845400	4793	/**
AnnaBridge	172:65be27845400	4794	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	172:65be27845400	4795	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	172:65be27845400	4796	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4797	* @retval None
AnnaBridge	172:65be27845400	4798	*/
AnnaBridge	172:65be27845400	4799	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4800	{
AnnaBridge	172:65be27845400	4801	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	172:65be27845400	4802	}
AnnaBridge	172:65be27845400	4803
AnnaBridge	172:65be27845400	4804	/**
AnnaBridge	172:65be27845400	4805	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	172:65be27845400	4806	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	172:65be27845400	4807	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4808	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4809	*/
AnnaBridge	172:65be27845400	4810	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4811	{
AnnaBridge	172:65be27845400	4812	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	172:65be27845400	4813	}
AnnaBridge	172:65be27845400	4814
AnnaBridge	172:65be27845400	4815	/**
AnnaBridge	172:65be27845400	4816	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	172:65be27845400	4817	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	172:65be27845400	4818	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4819	* @retval None
AnnaBridge	172:65be27845400	4820	*/
AnnaBridge	172:65be27845400	4821	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4822	{
AnnaBridge	172:65be27845400	4823	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	172:65be27845400	4824	}
AnnaBridge	172:65be27845400	4825
AnnaBridge	172:65be27845400	4826	/**
AnnaBridge	172:65be27845400	4827	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	172:65be27845400	4828	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	172:65be27845400	4829	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4830	* @retval None
AnnaBridge	172:65be27845400	4831	*/
AnnaBridge	172:65be27845400	4832	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4833	{
AnnaBridge	172:65be27845400	4834	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	172:65be27845400	4835	}
AnnaBridge	172:65be27845400	4836
AnnaBridge	172:65be27845400	4837	/**
AnnaBridge	172:65be27845400	4838	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	172:65be27845400	4839	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	172:65be27845400	4840	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4841	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4842	*/
AnnaBridge	172:65be27845400	4843	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4844	{
AnnaBridge	172:65be27845400	4845	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
AnnaBridge	172:65be27845400	4846	}
AnnaBridge	172:65be27845400	4847
AnnaBridge	172:65be27845400	4848	/**
AnnaBridge	172:65be27845400	4849	* @brief Enable trigger interrupt (TDE).
AnnaBridge	172:65be27845400	4850	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	172:65be27845400	4851	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4852	* @retval None
AnnaBridge	172:65be27845400	4853	*/
AnnaBridge	172:65be27845400	4854	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4855	{
AnnaBridge	172:65be27845400	4856	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	172:65be27845400	4857	}
AnnaBridge	172:65be27845400	4858
AnnaBridge	172:65be27845400	4859	/**
AnnaBridge	172:65be27845400	4860	* @brief Disable trigger interrupt (TDE).
AnnaBridge	172:65be27845400	4861	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	172:65be27845400	4862	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4863	* @retval None
AnnaBridge	172:65be27845400	4864	*/
AnnaBridge	172:65be27845400	4865	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4866	{
AnnaBridge	172:65be27845400	4867	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	172:65be27845400	4868	}
AnnaBridge	172:65be27845400	4869
AnnaBridge	172:65be27845400	4870	/**
AnnaBridge	172:65be27845400	4871	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	172:65be27845400	4872	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	172:65be27845400	4873	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4874	* @retval State of bit (1 or 0).
AnnaBridge	172:65be27845400	4875	*/
AnnaBridge	172:65be27845400	4876	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4877	{
AnnaBridge	172:65be27845400	4878	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	172:65be27845400	4879	}
AnnaBridge	172:65be27845400	4880
AnnaBridge	172:65be27845400	4881	/**
AnnaBridge	172:65be27845400	4882	* @}
AnnaBridge	172:65be27845400	4883	*/
AnnaBridge	172:65be27845400	4884
AnnaBridge	172:65be27845400	4885	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	172:65be27845400	4886	* @{
AnnaBridge	172:65be27845400	4887	*/
AnnaBridge	172:65be27845400	4888	/**
AnnaBridge	172:65be27845400	4889	* @brief Generate an update event.
AnnaBridge	172:65be27845400	4890	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	172:65be27845400	4891	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4892	* @retval None
AnnaBridge	172:65be27845400	4893	*/
AnnaBridge	172:65be27845400	4894	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4895	{
AnnaBridge	172:65be27845400	4896	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	172:65be27845400	4897	}
AnnaBridge	172:65be27845400	4898
AnnaBridge	172:65be27845400	4899	/**
AnnaBridge	172:65be27845400	4900	* @brief Generate Capture/Compare 1 event.
AnnaBridge	172:65be27845400	4901	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	172:65be27845400	4902	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4903	* @retval None
AnnaBridge	172:65be27845400	4904	*/
AnnaBridge	172:65be27845400	4905	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4906	{
AnnaBridge	172:65be27845400	4907	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	172:65be27845400	4908	}
AnnaBridge	172:65be27845400	4909
AnnaBridge	172:65be27845400	4910	/**
AnnaBridge	172:65be27845400	4911	* @brief Generate Capture/Compare 2 event.
AnnaBridge	172:65be27845400	4912	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	172:65be27845400	4913	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4914	* @retval None
AnnaBridge	172:65be27845400	4915	*/
AnnaBridge	172:65be27845400	4916	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4917	{
AnnaBridge	172:65be27845400	4918	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	172:65be27845400	4919	}
AnnaBridge	172:65be27845400	4920
AnnaBridge	172:65be27845400	4921	/**
AnnaBridge	172:65be27845400	4922	* @brief Generate Capture/Compare 3 event.
AnnaBridge	172:65be27845400	4923	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	172:65be27845400	4924	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4925	* @retval None
AnnaBridge	172:65be27845400	4926	*/
AnnaBridge	172:65be27845400	4927	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4928	{
AnnaBridge	172:65be27845400	4929	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	172:65be27845400	4930	}
AnnaBridge	172:65be27845400	4931
AnnaBridge	172:65be27845400	4932	/**
AnnaBridge	172:65be27845400	4933	* @brief Generate Capture/Compare 4 event.
AnnaBridge	172:65be27845400	4934	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	172:65be27845400	4935	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4936	* @retval None
AnnaBridge	172:65be27845400	4937	*/
AnnaBridge	172:65be27845400	4938	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4939	{
AnnaBridge	172:65be27845400	4940	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	172:65be27845400	4941	}
AnnaBridge	172:65be27845400	4942
AnnaBridge	172:65be27845400	4943	/**
AnnaBridge	172:65be27845400	4944	* @brief Generate commutation event.
AnnaBridge	172:65be27845400	4945	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	172:65be27845400	4946	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4947	* @retval None
AnnaBridge	172:65be27845400	4948	*/
AnnaBridge	172:65be27845400	4949	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4950	{
AnnaBridge	172:65be27845400	4951	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	172:65be27845400	4952	}
AnnaBridge	172:65be27845400	4953
AnnaBridge	172:65be27845400	4954	/**
AnnaBridge	172:65be27845400	4955	* @brief Generate trigger event.
AnnaBridge	172:65be27845400	4956	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	172:65be27845400	4957	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4958	* @retval None
AnnaBridge	172:65be27845400	4959	*/
AnnaBridge	172:65be27845400	4960	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4961	{
AnnaBridge	172:65be27845400	4962	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	172:65be27845400	4963	}
AnnaBridge	172:65be27845400	4964
AnnaBridge	172:65be27845400	4965	/**
AnnaBridge	172:65be27845400	4966	* @brief Generate break event.
AnnaBridge	172:65be27845400	4967	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	172:65be27845400	4968	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4969	* @retval None
AnnaBridge	172:65be27845400	4970	*/
AnnaBridge	172:65be27845400	4971	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4972	{
AnnaBridge	172:65be27845400	4973	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	172:65be27845400	4974	}
AnnaBridge	172:65be27845400	4975
AnnaBridge	172:65be27845400	4976	/**
AnnaBridge	172:65be27845400	4977	* @brief Generate break 2 event.
AnnaBridge	172:65be27845400	4978	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
AnnaBridge	172:65be27845400	4979	* @param TIMx Timer instance
AnnaBridge	172:65be27845400	4980	* @retval None
AnnaBridge	172:65be27845400	4981	*/
AnnaBridge	172:65be27845400	4982	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
AnnaBridge	172:65be27845400	4983	{
AnnaBridge	172:65be27845400	4984	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
AnnaBridge	172:65be27845400	4985	}
AnnaBridge	172:65be27845400	4986
AnnaBridge	172:65be27845400	4987	/**
AnnaBridge	172:65be27845400	4988	* @}
AnnaBridge	172:65be27845400	4989	*/
AnnaBridge	172:65be27845400	4990
AnnaBridge	172:65be27845400	4991	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	172:65be27845400	4992	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	172:65be27845400	4993	* @{
AnnaBridge	172:65be27845400	4994	*/
AnnaBridge	172:65be27845400	4995
AnnaBridge	172:65be27845400	4996	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	172:65be27845400	4997	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	172:65be27845400	4998	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	172:65be27845400	4999	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	172:65be27845400	5000	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	172:65be27845400	5001	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	172:65be27845400	5002	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	172:65be27845400	5003	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	172:65be27845400	5004	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	172:65be27845400	5005	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	172:65be27845400	5006	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	172:65be27845400	5007	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	172:65be27845400	5008	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	172:65be27845400	5009	/**
AnnaBridge	172:65be27845400	5010	* @}
AnnaBridge	172:65be27845400	5011	*/
AnnaBridge	172:65be27845400	5012	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	172:65be27845400	5013
AnnaBridge	172:65be27845400	5014	/**
AnnaBridge	172:65be27845400	5015	* @}
AnnaBridge	172:65be27845400	5016	*/
AnnaBridge	172:65be27845400	5017
AnnaBridge	172:65be27845400	5018	/**
AnnaBridge	172:65be27845400	5019	* @}
AnnaBridge	172:65be27845400	5020	*/
AnnaBridge	172:65be27845400	5021
AnnaBridge	172:65be27845400	5022	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
AnnaBridge	172:65be27845400	5023
AnnaBridge	172:65be27845400	5024	/**
AnnaBridge	172:65be27845400	5025	* @}
AnnaBridge	172:65be27845400	5026	*/
AnnaBridge	172:65be27845400	5027
AnnaBridge	172:65be27845400	5028	#ifdef __cplusplus
AnnaBridge	172:65be27845400	5029	}
AnnaBridge	172:65be27845400	5030	#endif
AnnaBridge	172:65be27845400	5031
AnnaBridge	172:65be27845400	5032	#endif /* __STM32L4xx_LL_TIM_H */
AnnaBridge	172:65be27845400	5033	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/