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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32l4xx_hal_rcc_ex.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of RCC HAL Extended module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	12	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	172:65be27845400	14	* this list of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	172:65be27845400	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	172:65be27845400	17	* and/or other materials provided with the distribution.
AnnaBridge	172:65be27845400	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	172:65be27845400	19	* may be used to endorse or promote products derived from this software
AnnaBridge	172:65be27845400	20	* without specific prior written permission.
AnnaBridge	172:65be27845400	21	*
AnnaBridge	172:65be27845400	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	172:65be27845400	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	172:65be27845400	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	172:65be27845400	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	172:65be27845400	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	172:65be27845400	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	172:65be27845400	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	172:65be27845400	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	172:65be27845400	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	32	*
AnnaBridge	172:65be27845400	33	******************************************************************************
AnnaBridge	172:65be27845400	34	*/
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	37	#ifndef __STM32L4xx_HAL_RCC_EX_H
AnnaBridge	172:65be27845400	38	#define __STM32L4xx_HAL_RCC_EX_H
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	#ifdef __cplusplus
AnnaBridge	172:65be27845400	41	extern "C" {
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	172:65be27845400	48	* @{
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50
AnnaBridge	172:65be27845400	51	/** @addtogroup RCCEx
AnnaBridge	172:65be27845400	52	* @{
AnnaBridge	172:65be27845400	53	*/
AnnaBridge	172:65be27845400	54
AnnaBridge	172:65be27845400	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	56
AnnaBridge	172:65be27845400	57	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	172:65be27845400	58	* @{
AnnaBridge	172:65be27845400	59	*/
AnnaBridge	172:65be27845400	60
AnnaBridge	172:65be27845400	61	/**
AnnaBridge	172:65be27845400	62	* @brief PLLSAI1 Clock structure definition
AnnaBridge	172:65be27845400	63	*/
AnnaBridge	172:65be27845400	64	typedef struct
AnnaBridge	172:65be27845400	65	{
AnnaBridge	172:65be27845400	66
AnnaBridge	172:65be27845400	67	uint32_t PLLSAI1Source; /*!< PLLSAI1Source: PLLSAI1 entry clock source.
AnnaBridge	172:65be27845400	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	172:65be27845400	69
AnnaBridge	172:65be27845400	70	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	71	uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
AnnaBridge	172:65be27845400	72	This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	73	#else
AnnaBridge	172:65be27845400	74	uint32_t PLLSAI1M; /*!< PLLSAI1M: specifies the division factor for PLLSAI1 input clock.
AnnaBridge	172:65be27845400	75	This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
AnnaBridge	172:65be27845400	76	#endif
AnnaBridge	172:65be27845400	77
AnnaBridge	172:65be27845400	78	uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
AnnaBridge	172:65be27845400	79	This parameter must be a number between 8 and 86 or 127 depending on devices. */
AnnaBridge	172:65be27845400	80
AnnaBridge	172:65be27845400	81	uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
AnnaBridge	172:65be27845400	82	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	172:65be27845400	83
AnnaBridge	172:65be27845400	84	uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge	172:65be27845400	85	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
AnnaBridge	172:65be27845400	86
AnnaBridge	172:65be27845400	87	uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
AnnaBridge	172:65be27845400	88	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge	172:65be27845400	89
AnnaBridge	172:65be27845400	90	uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
AnnaBridge	172:65be27845400	91	This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
AnnaBridge	172:65be27845400	92	}RCC_PLLSAI1InitTypeDef;
AnnaBridge	172:65be27845400	93
AnnaBridge	172:65be27845400	94	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	95
AnnaBridge	172:65be27845400	96	/**
AnnaBridge	172:65be27845400	97	* @brief PLLSAI2 Clock structure definition
AnnaBridge	172:65be27845400	98	*/
AnnaBridge	172:65be27845400	99	typedef struct
AnnaBridge	172:65be27845400	100	{
AnnaBridge	172:65be27845400	101
AnnaBridge	172:65be27845400	102	uint32_t PLLSAI2Source; /*!< PLLSAI2Source: PLLSAI2 entry clock source.
AnnaBridge	172:65be27845400	103	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	106	uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
AnnaBridge	172:65be27845400	107	This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	172:65be27845400	108	#else
AnnaBridge	172:65be27845400	109	uint32_t PLLSAI2M; /*!< PLLSAI2M: specifies the division factor for PLLSAI2 input clock.
AnnaBridge	172:65be27845400	110	This parameter must be a number between Min_Data = 1 and Max_Data = 8 */
AnnaBridge	172:65be27845400	111	#endif
AnnaBridge	172:65be27845400	112
AnnaBridge	172:65be27845400	113	uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
AnnaBridge	172:65be27845400	114	This parameter must be a number between 8 and 86 or 127 depending on devices. */
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
AnnaBridge	172:65be27845400	117	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	172:65be27845400	118
AnnaBridge	172:65be27845400	119	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	172:65be27845400	120	uint32_t PLLSAI2Q; /*!< PLLSAI2Q: specifies the division factor for DSI clock.
AnnaBridge	172:65be27845400	121	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
AnnaBridge	172:65be27845400	122	#endif
AnnaBridge	172:65be27845400	123
AnnaBridge	172:65be27845400	124	uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
AnnaBridge	172:65be27845400	125	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
AnnaBridge	172:65be27845400	126
AnnaBridge	172:65be27845400	127	uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
AnnaBridge	172:65be27845400	128	This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
AnnaBridge	172:65be27845400	129	}RCC_PLLSAI2InitTypeDef;
AnnaBridge	172:65be27845400	130
AnnaBridge	172:65be27845400	131	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	132
AnnaBridge	172:65be27845400	133	/**
AnnaBridge	172:65be27845400	134	* @brief RCC extended clocks structure definition
AnnaBridge	172:65be27845400	135	*/
AnnaBridge	172:65be27845400	136	typedef struct
AnnaBridge	172:65be27845400	137	{
AnnaBridge	172:65be27845400	138	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	172:65be27845400	139	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	172:65be27845400	140
AnnaBridge	172:65be27845400	141	RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
AnnaBridge	172:65be27845400	142	This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
AnnaBridge	172:65be27845400	143
AnnaBridge	172:65be27845400	144	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	145
AnnaBridge	172:65be27845400	146	RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
AnnaBridge	172:65be27845400	147	This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
AnnaBridge	172:65be27845400	148
AnnaBridge	172:65be27845400	149	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	150
AnnaBridge	172:65be27845400	151	uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
AnnaBridge	172:65be27845400	152	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
AnnaBridge	172:65be27845400	153
AnnaBridge	172:65be27845400	154	uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
AnnaBridge	172:65be27845400	155	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	#if defined(USART3)
AnnaBridge	172:65be27845400	158
AnnaBridge	172:65be27845400	159	uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
AnnaBridge	172:65be27845400	160	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	#endif /* USART3 */
AnnaBridge	172:65be27845400	163
AnnaBridge	172:65be27845400	164	#if defined(UART4)
AnnaBridge	172:65be27845400	165
AnnaBridge	172:65be27845400	166	uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
AnnaBridge	172:65be27845400	167	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
AnnaBridge	172:65be27845400	168
AnnaBridge	172:65be27845400	169	#endif /* UART4 */
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	#if defined(UART5)
AnnaBridge	172:65be27845400	172
AnnaBridge	172:65be27845400	173	uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
AnnaBridge	172:65be27845400	174	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
AnnaBridge	172:65be27845400	175
AnnaBridge	172:65be27845400	176	#endif /* UART5 */
AnnaBridge	172:65be27845400	177
AnnaBridge	172:65be27845400	178	uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
AnnaBridge	172:65be27845400	179	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge	172:65be27845400	180
AnnaBridge	172:65be27845400	181	uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
AnnaBridge	172:65be27845400	182	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
AnnaBridge	172:65be27845400	183
AnnaBridge	172:65be27845400	184	#if defined(I2C2)
AnnaBridge	172:65be27845400	185
AnnaBridge	172:65be27845400	186	uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
AnnaBridge	172:65be27845400	187	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
AnnaBridge	172:65be27845400	188
AnnaBridge	172:65be27845400	189	#endif /* I2C2 */
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
AnnaBridge	172:65be27845400	192	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
AnnaBridge	172:65be27845400	193
AnnaBridge	172:65be27845400	194	#if defined(I2C4)
AnnaBridge	172:65be27845400	195
AnnaBridge	172:65be27845400	196	uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
AnnaBridge	172:65be27845400	197	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge	172:65be27845400	198
AnnaBridge	172:65be27845400	199	#endif /* I2C4 */
AnnaBridge	172:65be27845400	200
AnnaBridge	172:65be27845400	201	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
AnnaBridge	172:65be27845400	202	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	172:65be27845400	203
AnnaBridge	172:65be27845400	204	uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
AnnaBridge	172:65be27845400	205	This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
AnnaBridge	172:65be27845400	206
AnnaBridge	172:65be27845400	207	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
AnnaBridge	172:65be27845400	208	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge	172:65be27845400	209
AnnaBridge	172:65be27845400	210	#if defined(SAI2)
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
AnnaBridge	172:65be27845400	213	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
AnnaBridge	172:65be27845400	214
AnnaBridge	172:65be27845400	215	#endif /* SAI2 */
AnnaBridge	172:65be27845400	216
AnnaBridge	172:65be27845400	217	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	172:65be27845400	218
AnnaBridge	172:65be27845400	219	uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
AnnaBridge	172:65be27845400	220	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	172:65be27845400	221
AnnaBridge	172:65be27845400	222	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	172:65be27845400	223
AnnaBridge	172:65be27845400	224	#if defined(SDMMC1)
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
AnnaBridge	172:65be27845400	227	This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
AnnaBridge	172:65be27845400	228
AnnaBridge	172:65be27845400	229	#endif /* SDMMC1 */
AnnaBridge	172:65be27845400	230
AnnaBridge	172:65be27845400	231	uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
AnnaBridge	172:65be27845400	232	This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
AnnaBridge	172:65be27845400	233
AnnaBridge	172:65be27845400	234	uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
AnnaBridge	172:65be27845400	235	This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
AnnaBridge	172:65be27845400	236
AnnaBridge	172:65be27845400	237	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	238
AnnaBridge	172:65be27845400	239	uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
AnnaBridge	172:65be27845400	240	This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
AnnaBridge	172:65be27845400	241
AnnaBridge	172:65be27845400	242	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	243
AnnaBridge	172:65be27845400	244	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	245
AnnaBridge	172:65be27845400	246	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 clock source.
AnnaBridge	172:65be27845400	247	This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
AnnaBridge	172:65be27845400	248
AnnaBridge	172:65be27845400	249	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	250	uint32_t Dfsdm1AudioClockSelection; /*!< Specifies DFSDM1 audio clock source.
AnnaBridge	172:65be27845400	251	This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
AnnaBridge	172:65be27845400	252
AnnaBridge	172:65be27845400	253	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	254
AnnaBridge	172:65be27845400	255	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	256
AnnaBridge	172:65be27845400	257	#if defined(LTDC)
AnnaBridge	172:65be27845400	258
AnnaBridge	172:65be27845400	259	uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source.
AnnaBridge	172:65be27845400	260	This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */
AnnaBridge	172:65be27845400	261
AnnaBridge	172:65be27845400	262	#endif /* LTDC */
AnnaBridge	172:65be27845400	263
AnnaBridge	172:65be27845400	264	#if defined(DSI)
AnnaBridge	172:65be27845400	265
AnnaBridge	172:65be27845400	266	uint32_t DsiClockSelection; /*!< Specifies DSI clock source.
AnnaBridge	172:65be27845400	267	This parameter can be a value of @ref RCCEx_DSI_Clock_Source */
AnnaBridge	172:65be27845400	268
AnnaBridge	172:65be27845400	269	#endif /* DSI */
AnnaBridge	172:65be27845400	270
AnnaBridge	172:65be27845400	271	#if defined(OCTOSPI1) \|\| defined(OCTOSPI2)
AnnaBridge	172:65be27845400	272
AnnaBridge	172:65be27845400	273	uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source.
AnnaBridge	172:65be27845400	274	This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */
AnnaBridge	172:65be27845400	275
AnnaBridge	172:65be27845400	276	#endif
AnnaBridge	172:65be27845400	277
AnnaBridge	172:65be27845400	278	uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
AnnaBridge	172:65be27845400	279	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	172:65be27845400	280	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	172:65be27845400	281
AnnaBridge	172:65be27845400	282	#if defined(CRS)
AnnaBridge	172:65be27845400	283
AnnaBridge	172:65be27845400	284	/**
AnnaBridge	172:65be27845400	285	* @brief RCC_CRS Init structure definition
AnnaBridge	172:65be27845400	286	*/
AnnaBridge	172:65be27845400	287	typedef struct
AnnaBridge	172:65be27845400	288	{
AnnaBridge	172:65be27845400	289	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge	172:65be27845400	290	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge	172:65be27845400	291
AnnaBridge	172:65be27845400	292	uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge	172:65be27845400	293	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge	172:65be27845400	296	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge	172:65be27845400	299	It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
AnnaBridge	172:65be27845400	300	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge	172:65be27845400	301
AnnaBridge	172:65be27845400	302	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge	172:65be27845400	303	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge	172:65be27845400	304
AnnaBridge	172:65be27845400	305	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge	172:65be27845400	306	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge	172:65be27845400	307
AnnaBridge	172:65be27845400	308	}RCC_CRSInitTypeDef;
AnnaBridge	172:65be27845400	309
AnnaBridge	172:65be27845400	310	/**
AnnaBridge	172:65be27845400	311	* @brief RCC_CRS Synchronization structure definition
AnnaBridge	172:65be27845400	312	*/
AnnaBridge	172:65be27845400	313	typedef struct
AnnaBridge	172:65be27845400	314	{
AnnaBridge	172:65be27845400	315	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge	172:65be27845400	316	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	172:65be27845400	317
AnnaBridge	172:65be27845400	318	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge	172:65be27845400	319	This parameter must be a number between 0 and 0x3F */
AnnaBridge	172:65be27845400	320
AnnaBridge	172:65be27845400	321	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge	172:65be27845400	322	value latched in the time of the last SYNC event.
AnnaBridge	172:65be27845400	323	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge	172:65be27845400	326	frequency error counter latched in the time of the last SYNC event.
AnnaBridge	172:65be27845400	327	It shows whether the actual frequency is below or above the target.
AnnaBridge	172:65be27845400	328	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge	172:65be27845400	329
AnnaBridge	172:65be27845400	330	}RCC_CRSSynchroInfoTypeDef;
AnnaBridge	172:65be27845400	331
AnnaBridge	172:65be27845400	332	#endif /* CRS */
AnnaBridge	172:65be27845400	333	/**
AnnaBridge	172:65be27845400	334	* @}
AnnaBridge	172:65be27845400	335	*/
AnnaBridge	172:65be27845400	336
AnnaBridge	172:65be27845400	337	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	338	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	172:65be27845400	339	* @{
AnnaBridge	172:65be27845400	340	*/
AnnaBridge	172:65be27845400	341
AnnaBridge	172:65be27845400	342	/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
AnnaBridge	172:65be27845400	343	* @{
AnnaBridge	172:65be27845400	344	*/
AnnaBridge	172:65be27845400	345	#define RCC_LSCOSOURCE_LSI 0x00000000U /!< LSI selection for low speed clock output /
AnnaBridge	172:65be27845400	346	#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock output /
AnnaBridge	172:65be27845400	347	/**
AnnaBridge	172:65be27845400	348	* @}
AnnaBridge	172:65be27845400	349	*/
AnnaBridge	172:65be27845400	350
AnnaBridge	172:65be27845400	351	/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
AnnaBridge	172:65be27845400	352	* @{
AnnaBridge	172:65be27845400	353	*/
AnnaBridge	172:65be27845400	354	#define RCC_PERIPHCLK_USART1 0x00000001U
AnnaBridge	172:65be27845400	355	#define RCC_PERIPHCLK_USART2 0x00000002U
AnnaBridge	172:65be27845400	356	#if defined(USART3)
AnnaBridge	172:65be27845400	357	#define RCC_PERIPHCLK_USART3 0x00000004U
AnnaBridge	172:65be27845400	358	#endif
AnnaBridge	172:65be27845400	359	#if defined(UART4)
AnnaBridge	172:65be27845400	360	#define RCC_PERIPHCLK_UART4 0x00000008U
AnnaBridge	172:65be27845400	361	#endif
AnnaBridge	172:65be27845400	362	#if defined(UART5)
AnnaBridge	172:65be27845400	363	#define RCC_PERIPHCLK_UART5 0x00000010U
AnnaBridge	172:65be27845400	364	#endif
AnnaBridge	172:65be27845400	365	#define RCC_PERIPHCLK_LPUART1 0x00000020U
AnnaBridge	172:65be27845400	366	#define RCC_PERIPHCLK_I2C1 0x00000040U
AnnaBridge	172:65be27845400	367	#if defined(I2C2)
AnnaBridge	172:65be27845400	368	#define RCC_PERIPHCLK_I2C2 0x00000080U
AnnaBridge	172:65be27845400	369	#endif
AnnaBridge	172:65be27845400	370	#define RCC_PERIPHCLK_I2C3 0x00000100U
AnnaBridge	172:65be27845400	371	#define RCC_PERIPHCLK_LPTIM1 0x00000200U
AnnaBridge	172:65be27845400	372	#define RCC_PERIPHCLK_LPTIM2 0x00000400U
AnnaBridge	172:65be27845400	373	#define RCC_PERIPHCLK_SAI1 0x00000800U
AnnaBridge	172:65be27845400	374	#if defined(SAI2)
AnnaBridge	172:65be27845400	375	#define RCC_PERIPHCLK_SAI2 0x00001000U
AnnaBridge	172:65be27845400	376	#endif
AnnaBridge	172:65be27845400	377	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	172:65be27845400	378	#define RCC_PERIPHCLK_USB 0x00002000U
AnnaBridge	172:65be27845400	379	#endif
AnnaBridge	172:65be27845400	380	#define RCC_PERIPHCLK_ADC 0x00004000U
AnnaBridge	172:65be27845400	381	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	382	#define RCC_PERIPHCLK_SWPMI1 0x00008000U
AnnaBridge	172:65be27845400	383	#endif
AnnaBridge	172:65be27845400	384	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	385	#define RCC_PERIPHCLK_DFSDM1 0x00010000U
AnnaBridge	172:65be27845400	386	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	387	#define RCC_PERIPHCLK_DFSDM1AUDIO 0x00200000U
AnnaBridge	172:65be27845400	388	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	389	#endif
AnnaBridge	172:65be27845400	390	#define RCC_PERIPHCLK_RTC 0x00020000U
AnnaBridge	172:65be27845400	391	#define RCC_PERIPHCLK_RNG 0x00040000U
AnnaBridge	172:65be27845400	392	#if defined(SDMMC1)
AnnaBridge	172:65be27845400	393	#define RCC_PERIPHCLK_SDMMC1 0x00080000U
AnnaBridge	172:65be27845400	394	#endif
AnnaBridge	172:65be27845400	395	#if defined(I2C4)
AnnaBridge	172:65be27845400	396	#define RCC_PERIPHCLK_I2C4 0x00100000U
AnnaBridge	172:65be27845400	397	#endif
AnnaBridge	172:65be27845400	398	#if defined(LTDC)
AnnaBridge	172:65be27845400	399	#define RCC_PERIPHCLK_LTDC 0x00400000U
AnnaBridge	172:65be27845400	400	#endif
AnnaBridge	172:65be27845400	401	#if defined(DSI)
AnnaBridge	172:65be27845400	402	#define RCC_PERIPHCLK_DSI 0x00800000U
AnnaBridge	172:65be27845400	403	#endif
AnnaBridge	172:65be27845400	404	#if defined(OCTOSPI1) \|\| defined(OCTOSPI2)
AnnaBridge	172:65be27845400	405	#define RCC_PERIPHCLK_OSPI 0x01000000U
AnnaBridge	172:65be27845400	406	#endif
AnnaBridge	172:65be27845400	407	/**
AnnaBridge	172:65be27845400	408	* @}
AnnaBridge	172:65be27845400	409	*/
AnnaBridge	172:65be27845400	410
AnnaBridge	172:65be27845400	411
AnnaBridge	172:65be27845400	412	/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
AnnaBridge	172:65be27845400	413	* @{
AnnaBridge	172:65be27845400	414	*/
AnnaBridge	172:65be27845400	415	#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	172:65be27845400	416	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
AnnaBridge	172:65be27845400	417	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
AnnaBridge	172:65be27845400	418	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
AnnaBridge	172:65be27845400	419	/**
AnnaBridge	172:65be27845400	420	* @}
AnnaBridge	172:65be27845400	421	*/
AnnaBridge	172:65be27845400	422
AnnaBridge	172:65be27845400	423	/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
AnnaBridge	172:65be27845400	424	* @{
AnnaBridge	172:65be27845400	425	*/
AnnaBridge	172:65be27845400	426	#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	427	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
AnnaBridge	172:65be27845400	428	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
AnnaBridge	172:65be27845400	429	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
AnnaBridge	172:65be27845400	430	/**
AnnaBridge	172:65be27845400	431	* @}
AnnaBridge	172:65be27845400	432	*/
AnnaBridge	172:65be27845400	433
AnnaBridge	172:65be27845400	434	#if defined(USART3)
AnnaBridge	172:65be27845400	435	/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
AnnaBridge	172:65be27845400	436	* @{
AnnaBridge	172:65be27845400	437	*/
AnnaBridge	172:65be27845400	438	#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	439	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
AnnaBridge	172:65be27845400	440	#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
AnnaBridge	172:65be27845400	441	#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 \| RCC_CCIPR_USART3SEL_1)
AnnaBridge	172:65be27845400	442	/**
AnnaBridge	172:65be27845400	443	* @}
AnnaBridge	172:65be27845400	444	*/
AnnaBridge	172:65be27845400	445	#endif /* USART3 */
AnnaBridge	172:65be27845400	446
AnnaBridge	172:65be27845400	447	#if defined(UART4)
AnnaBridge	172:65be27845400	448	/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
AnnaBridge	172:65be27845400	449	* @{
AnnaBridge	172:65be27845400	450	*/
AnnaBridge	172:65be27845400	451	#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	452	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
AnnaBridge	172:65be27845400	453	#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
AnnaBridge	172:65be27845400	454	#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 \| RCC_CCIPR_UART4SEL_1)
AnnaBridge	172:65be27845400	455	/**
AnnaBridge	172:65be27845400	456	* @}
AnnaBridge	172:65be27845400	457	*/
AnnaBridge	172:65be27845400	458	#endif /* UART4 */
AnnaBridge	172:65be27845400	459
AnnaBridge	172:65be27845400	460	#if defined(UART5)
AnnaBridge	172:65be27845400	461	/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
AnnaBridge	172:65be27845400	462	* @{
AnnaBridge	172:65be27845400	463	*/
AnnaBridge	172:65be27845400	464	#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	465	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
AnnaBridge	172:65be27845400	466	#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
AnnaBridge	172:65be27845400	467	#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 \| RCC_CCIPR_UART5SEL_1)
AnnaBridge	172:65be27845400	468	/**
AnnaBridge	172:65be27845400	469	* @}
AnnaBridge	172:65be27845400	470	*/
AnnaBridge	172:65be27845400	471	#endif /* UART5 */
AnnaBridge	172:65be27845400	472
AnnaBridge	172:65be27845400	473	/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
AnnaBridge	172:65be27845400	474	* @{
AnnaBridge	172:65be27845400	475	*/
AnnaBridge	172:65be27845400	476	#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	477	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
AnnaBridge	172:65be27845400	478	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
AnnaBridge	172:65be27845400	479	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
AnnaBridge	172:65be27845400	480	/**
AnnaBridge	172:65be27845400	481	* @}
AnnaBridge	172:65be27845400	482	*/
AnnaBridge	172:65be27845400	483
AnnaBridge	172:65be27845400	484	/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
AnnaBridge	172:65be27845400	485	* @{
AnnaBridge	172:65be27845400	486	*/
AnnaBridge	172:65be27845400	487	#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	488	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
AnnaBridge	172:65be27845400	489	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
AnnaBridge	172:65be27845400	490	/**
AnnaBridge	172:65be27845400	491	* @}
AnnaBridge	172:65be27845400	492	*/
AnnaBridge	172:65be27845400	493
AnnaBridge	172:65be27845400	494	#if defined(I2C2)
AnnaBridge	172:65be27845400	495	/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
AnnaBridge	172:65be27845400	496	* @{
AnnaBridge	172:65be27845400	497	*/
AnnaBridge	172:65be27845400	498	#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	499	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
AnnaBridge	172:65be27845400	500	#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
AnnaBridge	172:65be27845400	501	/**
AnnaBridge	172:65be27845400	502	* @}
AnnaBridge	172:65be27845400	503	*/
AnnaBridge	172:65be27845400	504	#endif /* I2C2 */
AnnaBridge	172:65be27845400	505
AnnaBridge	172:65be27845400	506	/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
AnnaBridge	172:65be27845400	507	* @{
AnnaBridge	172:65be27845400	508	*/
AnnaBridge	172:65be27845400	509	#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	510	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
AnnaBridge	172:65be27845400	511	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
AnnaBridge	172:65be27845400	512	/**
AnnaBridge	172:65be27845400	513	* @}
AnnaBridge	172:65be27845400	514	*/
AnnaBridge	172:65be27845400	515
AnnaBridge	172:65be27845400	516	#if defined(I2C4)
AnnaBridge	172:65be27845400	517	/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
AnnaBridge	172:65be27845400	518	* @{
AnnaBridge	172:65be27845400	519	*/
AnnaBridge	172:65be27845400	520	#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	521	#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
AnnaBridge	172:65be27845400	522	#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
AnnaBridge	172:65be27845400	523	/**
AnnaBridge	172:65be27845400	524	* @}
AnnaBridge	172:65be27845400	525	*/
AnnaBridge	172:65be27845400	526	#endif /* I2C4 */
AnnaBridge	172:65be27845400	527
AnnaBridge	172:65be27845400	528	/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
AnnaBridge	172:65be27845400	529	* @{
AnnaBridge	172:65be27845400	530	*/
AnnaBridge	172:65be27845400	531	#define RCC_SAI1CLKSOURCE_PLLSAI1 0x00000000U
AnnaBridge	172:65be27845400	532	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	533	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	534	#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI1SEL_0
AnnaBridge	172:65be27845400	535	#else
AnnaBridge	172:65be27845400	536	#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
AnnaBridge	172:65be27845400	537	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	538	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	539	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	540	#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR2_SAI1SEL_1
AnnaBridge	172:65be27845400	541	#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 \| RCC_CCIPR2_SAI1SEL_0)
AnnaBridge	172:65be27845400	542	#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2
AnnaBridge	172:65be27845400	543	#else
AnnaBridge	172:65be27845400	544	#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
AnnaBridge	172:65be27845400	545	#define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
AnnaBridge	172:65be27845400	546	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	547	/**
AnnaBridge	172:65be27845400	548	* @}
AnnaBridge	172:65be27845400	549	*/
AnnaBridge	172:65be27845400	550
AnnaBridge	172:65be27845400	551	#if defined(SAI2)
AnnaBridge	172:65be27845400	552	/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
AnnaBridge	172:65be27845400	553	* @{
AnnaBridge	172:65be27845400	554	*/
AnnaBridge	172:65be27845400	555	#define RCC_SAI2CLKSOURCE_PLLSAI1 0x00000000U
AnnaBridge	172:65be27845400	556	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	557	#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR2_SAI2SEL_0
AnnaBridge	172:65be27845400	558	#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR2_SAI2SEL_1
AnnaBridge	172:65be27845400	559	#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 \| RCC_CCIPR2_SAI2SEL_0)
AnnaBridge	172:65be27845400	560	#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2
AnnaBridge	172:65be27845400	561	#else
AnnaBridge	172:65be27845400	562	#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
AnnaBridge	172:65be27845400	563	#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
AnnaBridge	172:65be27845400	564	#define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
AnnaBridge	172:65be27845400	565	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	566	/**
AnnaBridge	172:65be27845400	567	* @}
AnnaBridge	172:65be27845400	568	*/
AnnaBridge	172:65be27845400	569	#endif /* SAI2 */
AnnaBridge	172:65be27845400	570
AnnaBridge	172:65be27845400	571	/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
AnnaBridge	172:65be27845400	572	* @{
AnnaBridge	172:65be27845400	573	*/
AnnaBridge	172:65be27845400	574	#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	575	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
AnnaBridge	172:65be27845400	576	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
AnnaBridge	172:65be27845400	577	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
AnnaBridge	172:65be27845400	578	/**
AnnaBridge	172:65be27845400	579	* @}
AnnaBridge	172:65be27845400	580	*/
AnnaBridge	172:65be27845400	581
AnnaBridge	172:65be27845400	582	/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
AnnaBridge	172:65be27845400	583	* @{
AnnaBridge	172:65be27845400	584	*/
AnnaBridge	172:65be27845400	585	#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	586	#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
AnnaBridge	172:65be27845400	587	#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
AnnaBridge	172:65be27845400	588	#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
AnnaBridge	172:65be27845400	589	/**
AnnaBridge	172:65be27845400	590	* @}
AnnaBridge	172:65be27845400	591	*/
AnnaBridge	172:65be27845400	592
AnnaBridge	172:65be27845400	593	#if defined(SDMMC1)
AnnaBridge	172:65be27845400	594	/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
AnnaBridge	172:65be27845400	595	* @{
AnnaBridge	172:65be27845400	596	*/
AnnaBridge	172:65be27845400	597	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	598	#define RCC_SDMMC1CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock selected as SDMMC1 clock /
AnnaBridge	172:65be27845400	599	#else
AnnaBridge	172:65be27845400	600	#define RCC_SDMMC1CLKSOURCE_NONE 0x00000000U /!< No clock selected as SDMMC1 clock /
AnnaBridge	172:65be27845400	601	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	602	#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 "Q" clock selected as SDMMC1 clock /
AnnaBridge	172:65be27845400	603	#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL "Q" clock selected as SDMMC1 clock /
AnnaBridge	172:65be27845400	604	#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock selected as SDMMC1 clock /
AnnaBridge	172:65be27845400	605	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	172:65be27845400	606	#define RCC_SDMMC1CLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /!< PLL "P" clock selected as SDMMC1 kernel clock /
AnnaBridge	172:65be27845400	607	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	172:65be27845400	608	/**
AnnaBridge	172:65be27845400	609	* @}
AnnaBridge	172:65be27845400	610	*/
AnnaBridge	172:65be27845400	611	#endif /* SDMMC1 */
AnnaBridge	172:65be27845400	612
AnnaBridge	172:65be27845400	613	/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
AnnaBridge	172:65be27845400	614	* @{
AnnaBridge	172:65be27845400	615	*/
AnnaBridge	172:65be27845400	616	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	617	#define RCC_RNGCLKSOURCE_HSI48 0x00000000U
AnnaBridge	172:65be27845400	618	#else
AnnaBridge	172:65be27845400	619	#define RCC_RNGCLKSOURCE_NONE 0x00000000U
AnnaBridge	172:65be27845400	620	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	621	#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
AnnaBridge	172:65be27845400	622	#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
AnnaBridge	172:65be27845400	623	#define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
AnnaBridge	172:65be27845400	624	/**
AnnaBridge	172:65be27845400	625	* @}
AnnaBridge	172:65be27845400	626	*/
AnnaBridge	172:65be27845400	627
AnnaBridge	172:65be27845400	628	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	172:65be27845400	629	/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
AnnaBridge	172:65be27845400	630	* @{
AnnaBridge	172:65be27845400	631	*/
AnnaBridge	172:65be27845400	632	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	633	#define RCC_USBCLKSOURCE_HSI48 0x00000000U
AnnaBridge	172:65be27845400	634	#else
AnnaBridge	172:65be27845400	635	#define RCC_USBCLKSOURCE_NONE 0x00000000U
AnnaBridge	172:65be27845400	636	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	637	#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
AnnaBridge	172:65be27845400	638	#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
AnnaBridge	172:65be27845400	639	#define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
AnnaBridge	172:65be27845400	640	/**
AnnaBridge	172:65be27845400	641	* @}
AnnaBridge	172:65be27845400	642	*/
AnnaBridge	172:65be27845400	643	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	172:65be27845400	644
AnnaBridge	172:65be27845400	645	/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
AnnaBridge	172:65be27845400	646	* @{
AnnaBridge	172:65be27845400	647	*/
AnnaBridge	172:65be27845400	648	#define RCC_ADCCLKSOURCE_NONE 0x00000000U
AnnaBridge	172:65be27845400	649	#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
AnnaBridge	172:65be27845400	650	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	172:65be27845400	651	#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
AnnaBridge	172:65be27845400	652	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	653	#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
AnnaBridge	172:65be27845400	654	/**
AnnaBridge	172:65be27845400	655	* @}
AnnaBridge	172:65be27845400	656	*/
AnnaBridge	172:65be27845400	657
AnnaBridge	172:65be27845400	658	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	659	/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
AnnaBridge	172:65be27845400	660	* @{
AnnaBridge	172:65be27845400	661	*/
AnnaBridge	172:65be27845400	662	#define RCC_SWPMI1CLKSOURCE_PCLK1 0x00000000U
AnnaBridge	172:65be27845400	663	#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
AnnaBridge	172:65be27845400	664	/**
AnnaBridge	172:65be27845400	665	* @}
AnnaBridge	172:65be27845400	666	*/
AnnaBridge	172:65be27845400	667	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	668
AnnaBridge	172:65be27845400	669	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	670	/** @defgroup RCCEx_DFSDM1_Clock_Source DFSDM1 Clock Source
AnnaBridge	172:65be27845400	671	* @{
AnnaBridge	172:65be27845400	672	*/
AnnaBridge	172:65be27845400	673	#define RCC_DFSDM1CLKSOURCE_PCLK2 0x00000000U
AnnaBridge	172:65be27845400	674	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	675	#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL
AnnaBridge	172:65be27845400	676	#else
AnnaBridge	172:65be27845400	677	#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL
AnnaBridge	172:65be27845400	678	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	679	/**
AnnaBridge	172:65be27845400	680	* @}
AnnaBridge	172:65be27845400	681	*/
AnnaBridge	172:65be27845400	682
AnnaBridge	172:65be27845400	683	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	684	/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source DFSDM1 Audio Clock Source
AnnaBridge	172:65be27845400	685	* @{
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 0x00000000U
AnnaBridge	172:65be27845400	688	#define RCC_DFSDM1AUDIOCLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0
AnnaBridge	172:65be27845400	689	#define RCC_DFSDM1AUDIOCLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1
AnnaBridge	172:65be27845400	690	/**
AnnaBridge	172:65be27845400	691	* @}
AnnaBridge	172:65be27845400	692	*/
AnnaBridge	172:65be27845400	693	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	694	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	695
AnnaBridge	172:65be27845400	696	#if defined(LTDC)
AnnaBridge	172:65be27845400	697	/** @defgroup RCCEx_LTDC_Clock_Source LTDC Clock Source
AnnaBridge	172:65be27845400	698	* @{
AnnaBridge	172:65be27845400	699	*/
AnnaBridge	172:65be27845400	700	#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 0x00000000U
AnnaBridge	172:65be27845400	701	#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0
AnnaBridge	172:65be27845400	702	#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1
AnnaBridge	172:65be27845400	703	#define RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 RCC_CCIPR2_PLLSAI2DIVR
AnnaBridge	172:65be27845400	704	/**
AnnaBridge	172:65be27845400	705	* @}
AnnaBridge	172:65be27845400	706	*/
AnnaBridge	172:65be27845400	707	#endif /* LTDC */
AnnaBridge	172:65be27845400	708
AnnaBridge	172:65be27845400	709	#if defined(DSI)
AnnaBridge	172:65be27845400	710	/** @defgroup RCCEx_DSI_Clock_Source DSI Clock Source
AnnaBridge	172:65be27845400	711	* @{
AnnaBridge	172:65be27845400	712	*/
AnnaBridge	172:65be27845400	713	#define RCC_DSICLKSOURCE_DSIPHY 0x00000000U
AnnaBridge	172:65be27845400	714	#define RCC_DSICLKSOURCE_PLLSAI2 RCC_CCIPR2_DSISEL
AnnaBridge	172:65be27845400	715	/**
AnnaBridge	172:65be27845400	716	* @}
AnnaBridge	172:65be27845400	717	*/
AnnaBridge	172:65be27845400	718	#endif /* DSI */
AnnaBridge	172:65be27845400	719
AnnaBridge	172:65be27845400	720	#if defined(OCTOSPI1) \|\| defined(OCTOSPI2)
AnnaBridge	172:65be27845400	721	/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source
AnnaBridge	172:65be27845400	722	* @{
AnnaBridge	172:65be27845400	723	*/
AnnaBridge	172:65be27845400	724	#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U
AnnaBridge	172:65be27845400	725	#define RCC_OSPICLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0
AnnaBridge	172:65be27845400	726	#define RCC_OSPICLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1
AnnaBridge	172:65be27845400	727	/**
AnnaBridge	172:65be27845400	728	* @}
AnnaBridge	172:65be27845400	729	*/
AnnaBridge	172:65be27845400	730	#endif /* OCTOSPI1 \|\| OCTOSPI2 */
AnnaBridge	172:65be27845400	731
AnnaBridge	172:65be27845400	732	/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
AnnaBridge	172:65be27845400	733	* @{
AnnaBridge	172:65be27845400	734	*/
AnnaBridge	172:65be27845400	735	#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /!< External interrupt line 19 connected to the LSE CSS EXTI Line /
AnnaBridge	172:65be27845400	736	/**
AnnaBridge	172:65be27845400	737	* @}
AnnaBridge	172:65be27845400	738	*/
AnnaBridge	172:65be27845400	739
AnnaBridge	172:65be27845400	740	#if defined(CRS)
AnnaBridge	172:65be27845400	741
AnnaBridge	172:65be27845400	742	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
AnnaBridge	172:65be27845400	743	* @{
AnnaBridge	172:65be27845400	744	*/
AnnaBridge	172:65be27845400	745	#define RCC_CRS_NONE 0x00000000U
AnnaBridge	172:65be27845400	746	#define RCC_CRS_TIMEOUT 0x00000001U
AnnaBridge	172:65be27845400	747	#define RCC_CRS_SYNCOK 0x00000002U
AnnaBridge	172:65be27845400	748	#define RCC_CRS_SYNCWARN 0x00000004U
AnnaBridge	172:65be27845400	749	#define RCC_CRS_SYNCERR 0x00000008U
AnnaBridge	172:65be27845400	750	#define RCC_CRS_SYNCMISS 0x00000010U
AnnaBridge	172:65be27845400	751	#define RCC_CRS_TRIMOVF 0x00000020U
AnnaBridge	172:65be27845400	752	/**
AnnaBridge	172:65be27845400	753	* @}
AnnaBridge	172:65be27845400	754	*/
AnnaBridge	172:65be27845400	755
AnnaBridge	172:65be27845400	756	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
AnnaBridge	172:65be27845400	757	* @{
AnnaBridge	172:65be27845400	758	*/
AnnaBridge	172:65be27845400	759	#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /!< Synchro Signal source GPIO /
AnnaBridge	172:65be27845400	760	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
AnnaBridge	172:65be27845400	761	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
AnnaBridge	172:65be27845400	762	/**
AnnaBridge	172:65be27845400	763	* @}
AnnaBridge	172:65be27845400	764	*/
AnnaBridge	172:65be27845400	765
AnnaBridge	172:65be27845400	766	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
AnnaBridge	172:65be27845400	767	* @{
AnnaBridge	172:65be27845400	768	*/
AnnaBridge	172:65be27845400	769	#define RCC_CRS_SYNC_DIV1 0x00000000U /!< Synchro Signal not divided (default) /
AnnaBridge	172:65be27845400	770	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
AnnaBridge	172:65be27845400	771	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
AnnaBridge	172:65be27845400	772	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
AnnaBridge	172:65be27845400	773	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
AnnaBridge	172:65be27845400	774	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
AnnaBridge	172:65be27845400	775	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
AnnaBridge	172:65be27845400	776	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
AnnaBridge	172:65be27845400	777	/**
AnnaBridge	172:65be27845400	778	* @}
AnnaBridge	172:65be27845400	779	*/
AnnaBridge	172:65be27845400	780
AnnaBridge	172:65be27845400	781	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
AnnaBridge	172:65be27845400	782	* @{
AnnaBridge	172:65be27845400	783	*/
AnnaBridge	172:65be27845400	784	#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /!< Synchro Active on rising edge (default) /
AnnaBridge	172:65be27845400	785	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
AnnaBridge	172:65be27845400	786	/**
AnnaBridge	172:65be27845400	787	* @}
AnnaBridge	172:65be27845400	788	*/
AnnaBridge	172:65be27845400	789
AnnaBridge	172:65be27845400	790	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
AnnaBridge	172:65be27845400	791	* @{
AnnaBridge	172:65be27845400	792	*/
AnnaBridge	172:65be27845400	793	#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds
AnnaBridge	172:65be27845400	794	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge	172:65be27845400	795	/**
AnnaBridge	172:65be27845400	796	* @}
AnnaBridge	172:65be27845400	797	*/
AnnaBridge	172:65be27845400	798
AnnaBridge	172:65be27845400	799	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
AnnaBridge	172:65be27845400	800	* @{
AnnaBridge	172:65be27845400	801	*/
AnnaBridge	172:65be27845400	802	#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /!< Default Frequency error limit /
AnnaBridge	172:65be27845400	803	/**
AnnaBridge	172:65be27845400	804	* @}
AnnaBridge	172:65be27845400	805	*/
AnnaBridge	172:65be27845400	806
AnnaBridge	172:65be27845400	807	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
AnnaBridge	172:65be27845400	808	* @{
AnnaBridge	172:65be27845400	809	*/
AnnaBridge	172:65be27845400	810	#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge	172:65be27845400	811	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge	172:65be27845400	812	corresponds to a higher output frequency */
AnnaBridge	172:65be27845400	813	/**
AnnaBridge	172:65be27845400	814	* @}
AnnaBridge	172:65be27845400	815	*/
AnnaBridge	172:65be27845400	816
AnnaBridge	172:65be27845400	817	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
AnnaBridge	172:65be27845400	818	* @{
AnnaBridge	172:65be27845400	819	*/
AnnaBridge	172:65be27845400	820	#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /!< Upcounting direction, the actual frequency is above the target /
AnnaBridge	172:65be27845400	821	#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /!< Downcounting direction, the actual frequency is below the target /
AnnaBridge	172:65be27845400	822	/**
AnnaBridge	172:65be27845400	823	* @}
AnnaBridge	172:65be27845400	824	*/
AnnaBridge	172:65be27845400	825
AnnaBridge	172:65be27845400	826	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
AnnaBridge	172:65be27845400	827	* @{
AnnaBridge	172:65be27845400	828	*/
AnnaBridge	172:65be27845400	829	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
AnnaBridge	172:65be27845400	830	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
AnnaBridge	172:65be27845400	831	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
AnnaBridge	172:65be27845400	832	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
AnnaBridge	172:65be27845400	833	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
AnnaBridge	172:65be27845400	834	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
AnnaBridge	172:65be27845400	835	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
AnnaBridge	172:65be27845400	836
AnnaBridge	172:65be27845400	837	/**
AnnaBridge	172:65be27845400	838	* @}
AnnaBridge	172:65be27845400	839	*/
AnnaBridge	172:65be27845400	840
AnnaBridge	172:65be27845400	841	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
AnnaBridge	172:65be27845400	842	* @{
AnnaBridge	172:65be27845400	843	*/
AnnaBridge	172:65be27845400	844	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
AnnaBridge	172:65be27845400	845	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
AnnaBridge	172:65be27845400	846	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
AnnaBridge	172:65be27845400	847	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
AnnaBridge	172:65be27845400	848	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
AnnaBridge	172:65be27845400	849	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
AnnaBridge	172:65be27845400	850	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
AnnaBridge	172:65be27845400	851
AnnaBridge	172:65be27845400	852	/**
AnnaBridge	172:65be27845400	853	* @}
AnnaBridge	172:65be27845400	854	*/
AnnaBridge	172:65be27845400	855
AnnaBridge	172:65be27845400	856	#endif /* CRS */
AnnaBridge	172:65be27845400	857
AnnaBridge	172:65be27845400	858	/**
AnnaBridge	172:65be27845400	859	* @}
AnnaBridge	172:65be27845400	860	*/
AnnaBridge	172:65be27845400	861
AnnaBridge	172:65be27845400	862	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	172:65be27845400	863	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	172:65be27845400	864	* @{
AnnaBridge	172:65be27845400	865	*/
AnnaBridge	172:65be27845400	866
AnnaBridge	172:65be27845400	867
AnnaBridge	172:65be27845400	868	/**
AnnaBridge	172:65be27845400	869	* @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
AnnaBridge	172:65be27845400	870	*
AnnaBridge	172:65be27845400	871	* @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge	172:65be27845400	872	* @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	873	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	874	*
AnnaBridge	172:65be27845400	875	@if STM32L4S9xx
AnnaBridge	172:65be27845400	876	* @param __PLLSAI1M__ specifies the division factor of PLLSAI1 input clock.
AnnaBridge	172:65be27845400	877	* This parameter must be a number between Min_Data = 1 and Max_Data = 16.
AnnaBridge	172:65be27845400	878	*
AnnaBridge	172:65be27845400	879	@endif
AnnaBridge	172:65be27845400	880	* @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
AnnaBridge	172:65be27845400	881	* This parameter must be a number between 8 and 86.
AnnaBridge	172:65be27845400	882	* @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	883	* output frequency is between 64 and 344 MHz.
AnnaBridge	172:65be27845400	884	* PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
AnnaBridge	172:65be27845400	885	*
AnnaBridge	172:65be27845400	886	* @param __PLLSAI1P__ specifies the division factor for SAI clock.
AnnaBridge	172:65be27845400	887	* This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
AnnaBridge	172:65be27845400	888	* else (2 to 31).
AnnaBridge	172:65be27845400	889	* SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
AnnaBridge	172:65be27845400	890	*
AnnaBridge	172:65be27845400	891	* @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge	172:65be27845400	892	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	893	* USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
AnnaBridge	172:65be27845400	894	*
AnnaBridge	172:65be27845400	895	* @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
AnnaBridge	172:65be27845400	896	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	897	* ADC clock frequency = f(PLLSAI1) / PLLSAI1R
AnnaBridge	172:65be27845400	898	*
AnnaBridge	172:65be27845400	899	* @retval None
AnnaBridge	172:65be27845400	900	*/
AnnaBridge	172:65be27845400	901	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	902
AnnaBridge	172:65be27845400	903	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	904
AnnaBridge	172:65be27845400	905	#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
AnnaBridge	172:65be27845400	906	WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) \| \
AnnaBridge	172:65be27845400	907	((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) \| \
AnnaBridge	172:65be27845400	908	((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) \| \
AnnaBridge	172:65be27845400	909	((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) \| \
AnnaBridge	172:65be27845400	910	(((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos))
AnnaBridge	172:65be27845400	911
AnnaBridge	172:65be27845400	912	#else
AnnaBridge	172:65be27845400	913
AnnaBridge	172:65be27845400	914	#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
AnnaBridge	172:65be27845400	915	WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) \| \
AnnaBridge	172:65be27845400	916	(((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) \| \
AnnaBridge	172:65be27845400	917	((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) \| \
AnnaBridge	172:65be27845400	918	((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) \| \
AnnaBridge	172:65be27845400	919	(((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos))
AnnaBridge	172:65be27845400	920
AnnaBridge	172:65be27845400	921	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	922
AnnaBridge	172:65be27845400	923	#else
AnnaBridge	172:65be27845400	924
AnnaBridge	172:65be27845400	925	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	926
AnnaBridge	172:65be27845400	927	#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
AnnaBridge	172:65be27845400	928	WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) \| \
AnnaBridge	172:65be27845400	929	((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) \| \
AnnaBridge	172:65be27845400	930	((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) \| \
AnnaBridge	172:65be27845400	931	((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	172:65be27845400	932
AnnaBridge	172:65be27845400	933	#else
AnnaBridge	172:65be27845400	934
AnnaBridge	172:65be27845400	935	#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
AnnaBridge	172:65be27845400	936	WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) \| \
AnnaBridge	172:65be27845400	937	(((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) \| \
AnnaBridge	172:65be27845400	938	((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) \| \
AnnaBridge	172:65be27845400	939	((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos))
AnnaBridge	172:65be27845400	940
AnnaBridge	172:65be27845400	941	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	172:65be27845400	944
AnnaBridge	172:65be27845400	945	/**
AnnaBridge	172:65be27845400	946	* @brief Macro to configure the PLLSAI1 clock multiplication factor N.
AnnaBridge	172:65be27845400	947	*
AnnaBridge	172:65be27845400	948	* @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge	172:65be27845400	949	* @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	950	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	951	*
AnnaBridge	172:65be27845400	952	* @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
AnnaBridge	172:65be27845400	953	* This parameter must be a number between 8 and 86.
AnnaBridge	172:65be27845400	954	* @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	955	* output frequency is between 64 and 344 MHz.
AnnaBridge	172:65be27845400	956	* Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
AnnaBridge	172:65be27845400	957	*
AnnaBridge	172:65be27845400	958	* @retval None
AnnaBridge	172:65be27845400	959	*/
AnnaBridge	172:65be27845400	960	#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
AnnaBridge	172:65be27845400	961	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
AnnaBridge	172:65be27845400	962
AnnaBridge	172:65be27845400	963	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965	/** @brief Macro to configure the PLLSAI1 input clock division factor M.
AnnaBridge	172:65be27845400	966	*
AnnaBridge	172:65be27845400	967	* @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge	172:65be27845400	968	* @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	969	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	970	*
AnnaBridge	172:65be27845400	971	* @param __PLLSAI1M__ specifies the division factor for PLLSAI1 clock.
AnnaBridge	172:65be27845400	972	* This parameter must be a number between Min_Data = 1 and Max_Data = 16.
AnnaBridge	172:65be27845400	973	*
AnnaBridge	172:65be27845400	974	* @retval None
AnnaBridge	172:65be27845400	975	*/
AnnaBridge	172:65be27845400	976
AnnaBridge	172:65be27845400	977	#define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \
AnnaBridge	172:65be27845400	978	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos)
AnnaBridge	172:65be27845400	979
AnnaBridge	172:65be27845400	980	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	172:65be27845400	981
AnnaBridge	172:65be27845400	982	/** @brief Macro to configure the PLLSAI1 clock division factor P.
AnnaBridge	172:65be27845400	983	*
AnnaBridge	172:65be27845400	984	* @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge	172:65be27845400	985	* @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	986	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	987	*
AnnaBridge	172:65be27845400	988	* @param __PLLSAI1P__ specifies the division factor for SAI clock.
AnnaBridge	172:65be27845400	989	* This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
AnnaBridge	172:65be27845400	990	* else (2 to 31).
AnnaBridge	172:65be27845400	991	* Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
AnnaBridge	172:65be27845400	992	*
AnnaBridge	172:65be27845400	993	* @retval None
AnnaBridge	172:65be27845400	994	*/
AnnaBridge	172:65be27845400	995	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	996
AnnaBridge	172:65be27845400	997	#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
AnnaBridge	172:65be27845400	998	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)
AnnaBridge	172:65be27845400	999
AnnaBridge	172:65be27845400	1000	#else
AnnaBridge	172:65be27845400	1001
AnnaBridge	172:65be27845400	1002	#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
AnnaBridge	172:65be27845400	1003	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
AnnaBridge	172:65be27845400	1004
AnnaBridge	172:65be27845400	1005	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	1006
AnnaBridge	172:65be27845400	1007	/** @brief Macro to configure the PLLSAI1 clock division factor Q.
AnnaBridge	172:65be27845400	1008	*
AnnaBridge	172:65be27845400	1009	* @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge	172:65be27845400	1010	* @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1011	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1012	*
AnnaBridge	172:65be27845400	1013	* @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge	172:65be27845400	1014	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	1015	* Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
AnnaBridge	172:65be27845400	1016	*
AnnaBridge	172:65be27845400	1017	* @retval None
AnnaBridge	172:65be27845400	1018	*/
AnnaBridge	172:65be27845400	1019	#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
AnnaBridge	172:65be27845400	1020	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
AnnaBridge	172:65be27845400	1021
AnnaBridge	172:65be27845400	1022	/** @brief Macro to configure the PLLSAI1 clock division factor R.
AnnaBridge	172:65be27845400	1023	*
AnnaBridge	172:65be27845400	1024	* @note This function must be used only when the PLLSAI1 is disabled.
AnnaBridge	172:65be27845400	1025	* @note PLLSAI1 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1026	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1027	*
AnnaBridge	172:65be27845400	1028	* @param __PLLSAI1R__ specifies the division factor for ADC clock.
AnnaBridge	172:65be27845400	1029	* This parameter must be in the range (2, 4, 6 or 8)
AnnaBridge	172:65be27845400	1030	* Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
AnnaBridge	172:65be27845400	1031	*
AnnaBridge	172:65be27845400	1032	* @retval None
AnnaBridge	172:65be27845400	1033	*/
AnnaBridge	172:65be27845400	1034	#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
AnnaBridge	172:65be27845400	1035	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
AnnaBridge	172:65be27845400	1036
AnnaBridge	172:65be27845400	1037	/**
AnnaBridge	172:65be27845400	1038	* @brief Macros to enable or disable the PLLSAI1.
AnnaBridge	172:65be27845400	1039	* @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	1040	* @retval None
AnnaBridge	172:65be27845400	1041	*/
AnnaBridge	172:65be27845400	1042
AnnaBridge	172:65be27845400	1043	#define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
AnnaBridge	172:65be27845400	1044
AnnaBridge	172:65be27845400	1045	#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
AnnaBridge	172:65be27845400	1046
AnnaBridge	172:65be27845400	1047	/**
AnnaBridge	172:65be27845400	1048	* @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
AnnaBridge	172:65be27845400	1049	* @note Enabling and disabling those clocks can be done without the need to stop the PLL.
AnnaBridge	172:65be27845400	1050	* This is mainly used to save Power.
AnnaBridge	172:65be27845400	1051	* @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
AnnaBridge	172:65be27845400	1052	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	1053	* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1054	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1055	* @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge	172:65be27845400	1056	* the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
AnnaBridge	172:65be27845400	1057	* @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
AnnaBridge	172:65be27845400	1058	* @retval None
AnnaBridge	172:65be27845400	1059	*/
AnnaBridge	172:65be27845400	1060
AnnaBridge	172:65be27845400	1061	#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
AnnaBridge	172:65be27845400	1062
AnnaBridge	172:65be27845400	1063	#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
AnnaBridge	172:65be27845400	1064
AnnaBridge	172:65be27845400	1065	/**
AnnaBridge	172:65be27845400	1066	* @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
AnnaBridge	172:65be27845400	1067	* @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
AnnaBridge	172:65be27845400	1068	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1069	* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1070	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1071	* @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
AnnaBridge	172:65be27845400	1072	* the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
AnnaBridge	172:65be27845400	1073	* @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
AnnaBridge	172:65be27845400	1074	* @retval SET / RESET
AnnaBridge	172:65be27845400	1075	*/
AnnaBridge	172:65be27845400	1076	#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
AnnaBridge	172:65be27845400	1077
AnnaBridge	172:65be27845400	1078	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	1079
AnnaBridge	172:65be27845400	1080	/**
AnnaBridge	172:65be27845400	1081	* @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
AnnaBridge	172:65be27845400	1082	*
AnnaBridge	172:65be27845400	1083	* @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge	172:65be27845400	1084	* @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1085	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1086	*
AnnaBridge	172:65be27845400	1087	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1088	* @param __PLLSAI2M__ specifies the division factor of PLLSAI2 input clock.
AnnaBridge	172:65be27845400	1089	* This parameter must be a number between Min_Data = 1 and Max_Data = 16.
AnnaBridge	172:65be27845400	1090	*
AnnaBridge	172:65be27845400	1091	@endif
AnnaBridge	172:65be27845400	1092	* @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
AnnaBridge	172:65be27845400	1093	* This parameter must be a number between 8 and 86.
AnnaBridge	172:65be27845400	1094	* @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	1095	* output frequency is between 64 and 344 MHz.
AnnaBridge	172:65be27845400	1096	*
AnnaBridge	172:65be27845400	1097	* @param __PLLSAI2P__ specifies the division factor for SAI clock.
AnnaBridge	172:65be27845400	1098	* This parameter must be a number in the range (7 or 17) for STM32L47xxx/L48xxx
AnnaBridge	172:65be27845400	1099	* else (2 to 31).
AnnaBridge	172:65be27845400	1100	* SAI2 clock frequency = f(PLLSAI2) / PLLSAI2P
AnnaBridge	172:65be27845400	1101	*
AnnaBridge	172:65be27845400	1102	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1103	* @param __PLLSAI2Q__ specifies the division factor for DSI clock.
AnnaBridge	172:65be27845400	1104	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	1105	* DSI clock frequency = f(PLLSAI2) / PLLSAI2Q
AnnaBridge	172:65be27845400	1106	*
AnnaBridge	172:65be27845400	1107	@endif
AnnaBridge	172:65be27845400	1108	* @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
AnnaBridge	172:65be27845400	1109	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	1110	*
AnnaBridge	172:65be27845400	1111	* @retval None
AnnaBridge	172:65be27845400	1112	*/
AnnaBridge	172:65be27845400	1113
AnnaBridge	172:65be27845400	1114	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	1115
AnnaBridge	172:65be27845400	1116	# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	172:65be27845400	1117
AnnaBridge	172:65be27845400	1118	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \
AnnaBridge	172:65be27845400	1119	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) \| \
AnnaBridge	172:65be27845400	1120	((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) \| \
AnnaBridge	172:65be27845400	1121	((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) \| \
AnnaBridge	172:65be27845400	1122	((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) \| \
AnnaBridge	172:65be27845400	1123	(((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos))
AnnaBridge	172:65be27845400	1124
AnnaBridge	172:65be27845400	1125	# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	1126
AnnaBridge	172:65be27845400	1127	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
AnnaBridge	172:65be27845400	1128	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) \| \
AnnaBridge	172:65be27845400	1129	((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) \| \
AnnaBridge	172:65be27845400	1130	((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) \| \
AnnaBridge	172:65be27845400	1131	(((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos))
AnnaBridge	172:65be27845400	1132
AnnaBridge	172:65be27845400	1133	# else
AnnaBridge	172:65be27845400	1134
AnnaBridge	172:65be27845400	1135	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
AnnaBridge	172:65be27845400	1136	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) \| \
AnnaBridge	172:65be27845400	1137	(((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) \| \
AnnaBridge	172:65be27845400	1138	((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) \| \
AnnaBridge	172:65be27845400	1139	(((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos))
AnnaBridge	172:65be27845400	1140
AnnaBridge	172:65be27845400	1141	# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	172:65be27845400	1142
AnnaBridge	172:65be27845400	1143	#else
AnnaBridge	172:65be27845400	1144
AnnaBridge	172:65be27845400	1145	# if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT) && defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	172:65be27845400	1146
AnnaBridge	172:65be27845400	1147	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2Q__, __PLLSAI2R__) \
AnnaBridge	172:65be27845400	1148	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) \| \
AnnaBridge	172:65be27845400	1149	((((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) \| \
AnnaBridge	172:65be27845400	1150	((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) \| \
AnnaBridge	172:65be27845400	1151	((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	172:65be27845400	1152
AnnaBridge	172:65be27845400	1153	# elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	1154
AnnaBridge	172:65be27845400	1155	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
AnnaBridge	172:65be27845400	1156	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) \| \
AnnaBridge	172:65be27845400	1157	((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) \| \
AnnaBridge	172:65be27845400	1158	((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	172:65be27845400	1159
AnnaBridge	172:65be27845400	1160	# else
AnnaBridge	172:65be27845400	1161
AnnaBridge	172:65be27845400	1162	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
AnnaBridge	172:65be27845400	1163	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) \| \
AnnaBridge	172:65be27845400	1164	(((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) \| \
AnnaBridge	172:65be27845400	1165	((((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos))
AnnaBridge	172:65be27845400	1166
AnnaBridge	172:65be27845400	1167	# endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT && RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	172:65be27845400	1168
AnnaBridge	172:65be27845400	1169	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	172:65be27845400	1170
AnnaBridge	172:65be27845400	1171
AnnaBridge	172:65be27845400	1172	/**
AnnaBridge	172:65be27845400	1173	* @brief Macro to configure the PLLSAI2 clock multiplication factor N.
AnnaBridge	172:65be27845400	1174	*
AnnaBridge	172:65be27845400	1175	* @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge	172:65be27845400	1176	* @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1177	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1178	*
AnnaBridge	172:65be27845400	1179	* @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
AnnaBridge	172:65be27845400	1180	* This parameter must be a number between 8 and 86.
AnnaBridge	172:65be27845400	1181	* @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	1182	* output frequency is between 64 and 344 MHz.
AnnaBridge	172:65be27845400	1183	* PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
AnnaBridge	172:65be27845400	1184	*
AnnaBridge	172:65be27845400	1185	* @retval None
AnnaBridge	172:65be27845400	1186	*/
AnnaBridge	172:65be27845400	1187	#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
AnnaBridge	172:65be27845400	1188	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
AnnaBridge	172:65be27845400	1189
AnnaBridge	172:65be27845400	1190	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	1191
AnnaBridge	172:65be27845400	1192	/** @brief Macro to configure the PLLSAI2 input clock division factor M.
AnnaBridge	172:65be27845400	1193	*
AnnaBridge	172:65be27845400	1194	* @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge	172:65be27845400	1195	* @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1196	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1197	*
AnnaBridge	172:65be27845400	1198	* @param __PLLSAI2M__ specifies the division factor for PLLSAI2 clock.
AnnaBridge	172:65be27845400	1199	* This parameter must be a number between Min_Data = 1 and Max_Data = 16.
AnnaBridge	172:65be27845400	1200	*
AnnaBridge	172:65be27845400	1201	* @retval None
AnnaBridge	172:65be27845400	1202	*/
AnnaBridge	172:65be27845400	1203
AnnaBridge	172:65be27845400	1204	#define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \
AnnaBridge	172:65be27845400	1205	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos)
AnnaBridge	172:65be27845400	1206
AnnaBridge	172:65be27845400	1207	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	172:65be27845400	1208
AnnaBridge	172:65be27845400	1209	/** @brief Macro to configure the PLLSAI2 clock division factor P.
AnnaBridge	172:65be27845400	1210	*
AnnaBridge	172:65be27845400	1211	* @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge	172:65be27845400	1212	* @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1213	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1214	*
AnnaBridge	172:65be27845400	1215	* @param __PLLSAI2P__ specifies the division factor.
AnnaBridge	172:65be27845400	1216	* This parameter must be a number in the range (7 or 17).
AnnaBridge	172:65be27845400	1217	* Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
AnnaBridge	172:65be27845400	1218	*
AnnaBridge	172:65be27845400	1219	* @retval None
AnnaBridge	172:65be27845400	1220	*/
AnnaBridge	172:65be27845400	1221	#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
AnnaBridge	172:65be27845400	1222	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
AnnaBridge	172:65be27845400	1223
AnnaBridge	172:65be27845400	1224	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	172:65be27845400	1225
AnnaBridge	172:65be27845400	1226	/** @brief Macro to configure the PLLSAI2 clock division factor Q.
AnnaBridge	172:65be27845400	1227	*
AnnaBridge	172:65be27845400	1228	* @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge	172:65be27845400	1229	* @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1230	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1231	*
AnnaBridge	172:65be27845400	1232	* @param __PLLSAI2Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
AnnaBridge	172:65be27845400	1233	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	1234	* Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI2) / PLLSAI2Q
AnnaBridge	172:65be27845400	1235	*
AnnaBridge	172:65be27845400	1236	* @retval None
AnnaBridge	172:65be27845400	1237	*/
AnnaBridge	172:65be27845400	1238	#define __HAL_RCC_PLLSAI2_DIVQ_CONFIG(__PLLSAI2Q__) \
AnnaBridge	172:65be27845400	1239	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q, (((__PLLSAI2Q__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2Q_Pos)
AnnaBridge	172:65be27845400	1240
AnnaBridge	172:65be27845400	1241	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	172:65be27845400	1242
AnnaBridge	172:65be27845400	1243	/** @brief Macro to configure the PLLSAI2 clock division factor R.
AnnaBridge	172:65be27845400	1244	*
AnnaBridge	172:65be27845400	1245	* @note This function must be used only when the PLLSAI2 is disabled.
AnnaBridge	172:65be27845400	1246	* @note PLLSAI2 clock source is common with the main PLL (configured through
AnnaBridge	172:65be27845400	1247	* __HAL_RCC_PLL_CONFIG() macro)
AnnaBridge	172:65be27845400	1248	*
AnnaBridge	172:65be27845400	1249	* @param __PLLSAI2R__ specifies the division factor.
AnnaBridge	172:65be27845400	1250	* This parameter must be in the range (2, 4, 6 or 8).
AnnaBridge	172:65be27845400	1251	* Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2R__
AnnaBridge	172:65be27845400	1252	*
AnnaBridge	172:65be27845400	1253	* @retval None
AnnaBridge	172:65be27845400	1254	*/
AnnaBridge	172:65be27845400	1255	#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
AnnaBridge	172:65be27845400	1256	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
AnnaBridge	172:65be27845400	1257
AnnaBridge	172:65be27845400	1258	/**
AnnaBridge	172:65be27845400	1259	* @brief Macros to enable or disable the PLLSAI2.
AnnaBridge	172:65be27845400	1260	* @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	1261	* @retval None
AnnaBridge	172:65be27845400	1262	*/
AnnaBridge	172:65be27845400	1263
AnnaBridge	172:65be27845400	1264	#define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
AnnaBridge	172:65be27845400	1265
AnnaBridge	172:65be27845400	1266	#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
AnnaBridge	172:65be27845400	1267
AnnaBridge	172:65be27845400	1268	/**
AnnaBridge	172:65be27845400	1269	* @brief Macros to enable or disable each clock output (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
AnnaBridge	172:65be27845400	1270	* @note Enabling and disabling those clocks can be done without the need to stop the PLL.
AnnaBridge	172:65be27845400	1271	* This is mainly used to save Power.
AnnaBridge	172:65be27845400	1272	* @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
AnnaBridge	172:65be27845400	1273	* This parameter can be one or a combination of the following values:
AnnaBridge	172:65be27845400	1274	@if STM32L486xx
AnnaBridge	172:65be27845400	1275	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1276	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1277	* @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
AnnaBridge	172:65be27845400	1278	@endif
AnnaBridge	172:65be27845400	1279	@if STM32L4A6xx
AnnaBridge	172:65be27845400	1280	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1281	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1282	* @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
AnnaBridge	172:65be27845400	1283	@endif
AnnaBridge	172:65be27845400	1284	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1285	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1286	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1287	* @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral.
AnnaBridge	172:65be27845400	1288	@endif
AnnaBridge	172:65be27845400	1289	* @retval None
AnnaBridge	172:65be27845400	1290	*/
AnnaBridge	172:65be27845400	1291
AnnaBridge	172:65be27845400	1292	#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
AnnaBridge	172:65be27845400	1293
AnnaBridge	172:65be27845400	1294	#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
AnnaBridge	172:65be27845400	1295
AnnaBridge	172:65be27845400	1296	/**
AnnaBridge	172:65be27845400	1297	* @brief Macro to get clock output enable status (PLLSAI2_SAI2, PLLSAI2_ADC2 and RCC_PLLSAI2_DSICLK).
AnnaBridge	172:65be27845400	1298	* @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
AnnaBridge	172:65be27845400	1299	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1300	@if STM32L486xx
AnnaBridge	172:65be27845400	1301	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1302	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1303	* @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
AnnaBridge	172:65be27845400	1304	@endif
AnnaBridge	172:65be27845400	1305	@if STM32L4A6xx
AnnaBridge	172:65be27845400	1306	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1307	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1308	* @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
AnnaBridge	172:65be27845400	1309	@endif
AnnaBridge	172:65be27845400	1310	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1311	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
AnnaBridge	172:65be27845400	1312	* high-quality audio performance on SAI interface in case.
AnnaBridge	172:65be27845400	1313	* @arg @ref RCC_PLLSAI2_DSICLK Clock used to clock DSI peripheral.
AnnaBridge	172:65be27845400	1314	@endif
AnnaBridge	172:65be27845400	1315	* @retval SET / RESET
AnnaBridge	172:65be27845400	1316	*/
AnnaBridge	172:65be27845400	1317	#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
AnnaBridge	172:65be27845400	1318
AnnaBridge	172:65be27845400	1319	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	1320
AnnaBridge	172:65be27845400	1321	/**
AnnaBridge	172:65be27845400	1322	* @brief Macro to configure the SAI1 clock source.
AnnaBridge	172:65be27845400	1323	* @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
AnnaBridge	172:65be27845400	1324	* from the PLLSAI1, system PLL or external clock (through a dedicated pin).
AnnaBridge	172:65be27845400	1325	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1326	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge	172:65be27845400	1327	@if STM32L486xx
AnnaBridge	172:65be27845400	1328	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge	172:65be27845400	1329	@endif
AnnaBridge	172:65be27845400	1330	* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
AnnaBridge	172:65be27845400	1331	* @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
AnnaBridge	172:65be27845400	1332	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1333	* @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16
AnnaBridge	172:65be27845400	1334	@endif
AnnaBridge	172:65be27845400	1335	*
AnnaBridge	172:65be27845400	1336	@if STM32L443xx
AnnaBridge	172:65be27845400	1337	* @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLLSAI2.
AnnaBridge	172:65be27845400	1338	@endif
AnnaBridge	172:65be27845400	1339	*
AnnaBridge	172:65be27845400	1340	* @retval None
AnnaBridge	172:65be27845400	1341	*/
AnnaBridge	172:65be27845400	1342	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1343	#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
AnnaBridge	172:65be27845400	1344	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1345	#else
AnnaBridge	172:65be27845400	1346	#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
AnnaBridge	172:65be27845400	1347	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1348	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1349
AnnaBridge	172:65be27845400	1350	/** @brief Macro to get the SAI1 clock source.
AnnaBridge	172:65be27845400	1351	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1352	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge	172:65be27845400	1353	@if STM32L486xx
AnnaBridge	172:65be27845400	1354	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) for devices with PLLSAI2
AnnaBridge	172:65be27845400	1355	@endif
AnnaBridge	172:65be27845400	1356	* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK if PLLSAI2 exists, else PLLSAI2CLK)
AnnaBridge	172:65be27845400	1357	* @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
AnnaBridge	172:65be27845400	1358	*
AnnaBridge	172:65be27845400	1359	* @note Despite returned values RCC_SAI1CLKSOURCE_PLLSAI1 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1
AnnaBridge	172:65be27845400	1360	* clock source when PLLs are disabled for devices without PLLSAI2.
AnnaBridge	172:65be27845400	1361	*
AnnaBridge	172:65be27845400	1362	*/
AnnaBridge	172:65be27845400	1363	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1364	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))
AnnaBridge	172:65be27845400	1365	#else
AnnaBridge	172:65be27845400	1366	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
AnnaBridge	172:65be27845400	1367	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1368
AnnaBridge	172:65be27845400	1369	#if defined(SAI2)
AnnaBridge	172:65be27845400	1370
AnnaBridge	172:65be27845400	1371	/**
AnnaBridge	172:65be27845400	1372	* @brief Macro to configure the SAI2 clock source.
AnnaBridge	172:65be27845400	1373	* @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
AnnaBridge	172:65be27845400	1374	* from the PLLSAI2, system PLL or external clock (through a dedicated pin).
AnnaBridge	172:65be27845400	1375	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1376	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge	172:65be27845400	1377	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
AnnaBridge	172:65be27845400	1378	* @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
AnnaBridge	172:65be27845400	1379	* @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
AnnaBridge	172:65be27845400	1380	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1381	* @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16
AnnaBridge	172:65be27845400	1382	@endif
AnnaBridge	172:65be27845400	1383	*
AnnaBridge	172:65be27845400	1384	* @retval None
AnnaBridge	172:65be27845400	1385	*/
AnnaBridge	172:65be27845400	1386	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1387	#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
AnnaBridge	172:65be27845400	1388	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (__SAI2_CLKSOURCE__))
AnnaBridge	172:65be27845400	1389	#else
AnnaBridge	172:65be27845400	1390	#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
AnnaBridge	172:65be27845400	1391	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (__SAI2_CLKSOURCE__))
AnnaBridge	172:65be27845400	1392	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1393
AnnaBridge	172:65be27845400	1394	/** @brief Macro to get the SAI2 clock source.
AnnaBridge	172:65be27845400	1395	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1396	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
AnnaBridge	172:65be27845400	1397	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
AnnaBridge	172:65be27845400	1398	* @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
AnnaBridge	172:65be27845400	1399	* @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
AnnaBridge	172:65be27845400	1400	*/
AnnaBridge	172:65be27845400	1401	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1402	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))
AnnaBridge	172:65be27845400	1403	#else
AnnaBridge	172:65be27845400	1404	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))
AnnaBridge	172:65be27845400	1405	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1406
AnnaBridge	172:65be27845400	1407	#endif /* SAI2 */
AnnaBridge	172:65be27845400	1408
AnnaBridge	172:65be27845400	1409	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	172:65be27845400	1410	*
AnnaBridge	172:65be27845400	1411	* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
AnnaBridge	172:65be27845400	1412	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1413	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
AnnaBridge	172:65be27845400	1414	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	172:65be27845400	1415	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	172:65be27845400	1416	* @retval None
AnnaBridge	172:65be27845400	1417	*/
AnnaBridge	172:65be27845400	1418	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1419	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1420
AnnaBridge	172:65be27845400	1421	/** @brief Macro to get the I2C1 clock source.
AnnaBridge	172:65be27845400	1422	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1423	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
AnnaBridge	172:65be27845400	1424	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	172:65be27845400	1425	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	172:65be27845400	1426	*/
AnnaBridge	172:65be27845400	1427	#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
AnnaBridge	172:65be27845400	1428
AnnaBridge	172:65be27845400	1429	#if defined(I2C2)
AnnaBridge	172:65be27845400	1430
AnnaBridge	172:65be27845400	1431	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	172:65be27845400	1432	*
AnnaBridge	172:65be27845400	1433	* @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
AnnaBridge	172:65be27845400	1434	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1435	* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
AnnaBridge	172:65be27845400	1436	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	172:65be27845400	1437	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	172:65be27845400	1438	* @retval None
AnnaBridge	172:65be27845400	1439	*/
AnnaBridge	172:65be27845400	1440	#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1441	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
AnnaBridge	172:65be27845400	1442
AnnaBridge	172:65be27845400	1443	/** @brief Macro to get the I2C2 clock source.
AnnaBridge	172:65be27845400	1444	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1445	* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
AnnaBridge	172:65be27845400	1446	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
AnnaBridge	172:65be27845400	1447	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
AnnaBridge	172:65be27845400	1448	*/
AnnaBridge	172:65be27845400	1449	#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
AnnaBridge	172:65be27845400	1450
AnnaBridge	172:65be27845400	1451	#endif /* I2C2 */
AnnaBridge	172:65be27845400	1452
AnnaBridge	172:65be27845400	1453	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	172:65be27845400	1454	*
AnnaBridge	172:65be27845400	1455	* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
AnnaBridge	172:65be27845400	1456	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1457	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
AnnaBridge	172:65be27845400	1458	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	172:65be27845400	1459	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	172:65be27845400	1460	* @retval None
AnnaBridge	172:65be27845400	1461	*/
AnnaBridge	172:65be27845400	1462	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1463	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
AnnaBridge	172:65be27845400	1464
AnnaBridge	172:65be27845400	1465	/** @brief Macro to get the I2C3 clock source.
AnnaBridge	172:65be27845400	1466	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1467	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
AnnaBridge	172:65be27845400	1468	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
AnnaBridge	172:65be27845400	1469	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
AnnaBridge	172:65be27845400	1470	*/
AnnaBridge	172:65be27845400	1471	#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
AnnaBridge	172:65be27845400	1472
AnnaBridge	172:65be27845400	1473	#if defined(I2C4)
AnnaBridge	172:65be27845400	1474
AnnaBridge	172:65be27845400	1475	/** @brief Macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge	172:65be27845400	1476	*
AnnaBridge	172:65be27845400	1477	* @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
AnnaBridge	172:65be27845400	1478	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1479	* @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
AnnaBridge	172:65be27845400	1480	* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
AnnaBridge	172:65be27845400	1481	* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
AnnaBridge	172:65be27845400	1482	* @retval None
AnnaBridge	172:65be27845400	1483	*/
AnnaBridge	172:65be27845400	1484	#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1485	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
AnnaBridge	172:65be27845400	1486
AnnaBridge	172:65be27845400	1487	/** @brief Macro to get the I2C4 clock source.
AnnaBridge	172:65be27845400	1488	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1489	* @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
AnnaBridge	172:65be27845400	1490	* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
AnnaBridge	172:65be27845400	1491	* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
AnnaBridge	172:65be27845400	1492	*/
AnnaBridge	172:65be27845400	1493	#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
AnnaBridge	172:65be27845400	1494
AnnaBridge	172:65be27845400	1495	#endif /* I2C4 */
AnnaBridge	172:65be27845400	1496
AnnaBridge	172:65be27845400	1497
AnnaBridge	172:65be27845400	1498	/** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge	172:65be27845400	1499	*
AnnaBridge	172:65be27845400	1500	* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
AnnaBridge	172:65be27845400	1501	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1502	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	172:65be27845400	1503	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	172:65be27845400	1504	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1505	* @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock
AnnaBridge	172:65be27845400	1506	* @retval None
AnnaBridge	172:65be27845400	1507	*/
AnnaBridge	172:65be27845400	1508	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1509	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1510
AnnaBridge	172:65be27845400	1511	/** @brief Macro to get the USART1 clock source.
AnnaBridge	172:65be27845400	1512	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1513	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
AnnaBridge	172:65be27845400	1514	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	172:65be27845400	1515	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1516	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	172:65be27845400	1517	*/
AnnaBridge	172:65be27845400	1518	#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
AnnaBridge	172:65be27845400	1519
AnnaBridge	172:65be27845400	1520	/** @brief Macro to configure the USART2 clock (USART2CLK).
AnnaBridge	172:65be27845400	1521	*
AnnaBridge	172:65be27845400	1522	* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
AnnaBridge	172:65be27845400	1523	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1524	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	172:65be27845400	1525	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	172:65be27845400	1526	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1527	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	172:65be27845400	1528	* @retval None
AnnaBridge	172:65be27845400	1529	*/
AnnaBridge	172:65be27845400	1530	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1531	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
AnnaBridge	172:65be27845400	1532
AnnaBridge	172:65be27845400	1533	/** @brief Macro to get the USART2 clock source.
AnnaBridge	172:65be27845400	1534	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1535	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
AnnaBridge	172:65be27845400	1536	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
AnnaBridge	172:65be27845400	1537	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1538	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
AnnaBridge	172:65be27845400	1539	*/
AnnaBridge	172:65be27845400	1540	#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
AnnaBridge	172:65be27845400	1541
AnnaBridge	172:65be27845400	1542	#if defined(USART3)
AnnaBridge	172:65be27845400	1543
AnnaBridge	172:65be27845400	1544	/** @brief Macro to configure the USART3 clock (USART3CLK).
AnnaBridge	172:65be27845400	1545	*
AnnaBridge	172:65be27845400	1546	* @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
AnnaBridge	172:65be27845400	1547	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1548	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge	172:65be27845400	1549	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge	172:65be27845400	1550	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1551	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge	172:65be27845400	1552	* @retval None
AnnaBridge	172:65be27845400	1553	*/
AnnaBridge	172:65be27845400	1554	#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1555	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
AnnaBridge	172:65be27845400	1556
AnnaBridge	172:65be27845400	1557	/** @brief Macro to get the USART3 clock source.
AnnaBridge	172:65be27845400	1558	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1559	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
AnnaBridge	172:65be27845400	1560	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
AnnaBridge	172:65be27845400	1561	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1562	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
AnnaBridge	172:65be27845400	1563	*/
AnnaBridge	172:65be27845400	1564	#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
AnnaBridge	172:65be27845400	1565
AnnaBridge	172:65be27845400	1566	#endif /* USART3 */
AnnaBridge	172:65be27845400	1567
AnnaBridge	172:65be27845400	1568	#if defined(UART4)
AnnaBridge	172:65be27845400	1569
AnnaBridge	172:65be27845400	1570	/** @brief Macro to configure the UART4 clock (UART4CLK).
AnnaBridge	172:65be27845400	1571	*
AnnaBridge	172:65be27845400	1572	* @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
AnnaBridge	172:65be27845400	1573	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1574	* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge	172:65be27845400	1575	* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge	172:65be27845400	1576	* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1577	* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge	172:65be27845400	1578	* @retval None
AnnaBridge	172:65be27845400	1579	*/
AnnaBridge	172:65be27845400	1580	#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1581	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
AnnaBridge	172:65be27845400	1582
AnnaBridge	172:65be27845400	1583	/** @brief Macro to get the UART4 clock source.
AnnaBridge	172:65be27845400	1584	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1585	* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
AnnaBridge	172:65be27845400	1586	* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
AnnaBridge	172:65be27845400	1587	* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1588	* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
AnnaBridge	172:65be27845400	1589	*/
AnnaBridge	172:65be27845400	1590	#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
AnnaBridge	172:65be27845400	1591
AnnaBridge	172:65be27845400	1592	#endif /* UART4 */
AnnaBridge	172:65be27845400	1593
AnnaBridge	172:65be27845400	1594	#if defined(UART5)
AnnaBridge	172:65be27845400	1595
AnnaBridge	172:65be27845400	1596	/** @brief Macro to configure the UART5 clock (UART5CLK).
AnnaBridge	172:65be27845400	1597	*
AnnaBridge	172:65be27845400	1598	* @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
AnnaBridge	172:65be27845400	1599	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1600	* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge	172:65be27845400	1601	* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge	172:65be27845400	1602	* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1603	* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge	172:65be27845400	1604	* @retval None
AnnaBridge	172:65be27845400	1605	*/
AnnaBridge	172:65be27845400	1606	#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1607	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
AnnaBridge	172:65be27845400	1608
AnnaBridge	172:65be27845400	1609	/** @brief Macro to get the UART5 clock source.
AnnaBridge	172:65be27845400	1610	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1611	* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
AnnaBridge	172:65be27845400	1612	* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
AnnaBridge	172:65be27845400	1613	* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1614	* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
AnnaBridge	172:65be27845400	1615	*/
AnnaBridge	172:65be27845400	1616	#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
AnnaBridge	172:65be27845400	1617
AnnaBridge	172:65be27845400	1618	#endif /* UART5 */
AnnaBridge	172:65be27845400	1619
AnnaBridge	172:65be27845400	1620	/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
AnnaBridge	172:65be27845400	1621	*
AnnaBridge	172:65be27845400	1622	* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
AnnaBridge	172:65be27845400	1623	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1624	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge	172:65be27845400	1625	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
AnnaBridge	172:65be27845400	1626	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1627	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	172:65be27845400	1628	* @retval None
AnnaBridge	172:65be27845400	1629	*/
AnnaBridge	172:65be27845400	1630	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1631	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1632
AnnaBridge	172:65be27845400	1633	/** @brief Macro to get the LPUART1 clock source.
AnnaBridge	172:65be27845400	1634	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1635	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge	172:65be27845400	1636	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
AnnaBridge	172:65be27845400	1637	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1638	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	172:65be27845400	1639	*/
AnnaBridge	172:65be27845400	1640	#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
AnnaBridge	172:65be27845400	1641
AnnaBridge	172:65be27845400	1642	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
AnnaBridge	172:65be27845400	1643	*
AnnaBridge	172:65be27845400	1644	* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
AnnaBridge	172:65be27845400	1645	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1646	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1647	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1648	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1649	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1650	* @retval None
AnnaBridge	172:65be27845400	1651	*/
AnnaBridge	172:65be27845400	1652	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1653	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1654
AnnaBridge	172:65be27845400	1655	/** @brief Macro to get the LPTIM1 clock source.
AnnaBridge	172:65be27845400	1656	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1657	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge	172:65be27845400	1658	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
AnnaBridge	172:65be27845400	1659	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1660	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	172:65be27845400	1661	*/
AnnaBridge	172:65be27845400	1662	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
AnnaBridge	172:65be27845400	1663
AnnaBridge	172:65be27845400	1664	/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
AnnaBridge	172:65be27845400	1665	*
AnnaBridge	172:65be27845400	1666	* @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
AnnaBridge	172:65be27845400	1667	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1668	* @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock
AnnaBridge	172:65be27845400	1669	* @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
AnnaBridge	172:65be27845400	1670	* @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
AnnaBridge	172:65be27845400	1671	* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
AnnaBridge	172:65be27845400	1672	* @retval None
AnnaBridge	172:65be27845400	1673	*/
AnnaBridge	172:65be27845400	1674	#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1675	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (__LPTIM2_CLKSOURCE__))
AnnaBridge	172:65be27845400	1676
AnnaBridge	172:65be27845400	1677	/** @brief Macro to get the LPTIM2 clock source.
AnnaBridge	172:65be27845400	1678	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1679	* @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
AnnaBridge	172:65be27845400	1680	* @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
AnnaBridge	172:65be27845400	1681	* @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1682	* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
AnnaBridge	172:65be27845400	1683	*/
AnnaBridge	172:65be27845400	1684	#define __HAL_RCC_GET_LPTIM2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))
AnnaBridge	172:65be27845400	1685
AnnaBridge	172:65be27845400	1686	#if defined(SDMMC1)
AnnaBridge	172:65be27845400	1687
AnnaBridge	172:65be27845400	1688	/** @brief Macro to configure the SDMMC1 clock.
AnnaBridge	172:65be27845400	1689	*
AnnaBridge	172:65be27845400	1690	@if STM32L486xx
AnnaBridge	172:65be27845400	1691	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge	172:65be27845400	1692	@endif
AnnaBridge	172:65be27845400	1693	*
AnnaBridge	172:65be27845400	1694	@if STM32L443xx
AnnaBridge	172:65be27845400	1695	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge	172:65be27845400	1696	@endif
AnnaBridge	172:65be27845400	1697	*
AnnaBridge	172:65be27845400	1698	* @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
AnnaBridge	172:65be27845400	1699	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1700	@if STM32L486xx
AnnaBridge	172:65be27845400	1701	* @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
AnnaBridge	172:65be27845400	1702	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1703	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1704	@endif
AnnaBridge	172:65be27845400	1705	@if STM32L443xx
AnnaBridge	172:65be27845400	1706	* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge	172:65be27845400	1707	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1708	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1709	@endif
AnnaBridge	172:65be27845400	1710	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1711	* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge	172:65be27845400	1712	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1713	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" Clock selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1714	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" Clock selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1715	@endif
AnnaBridge	172:65be27845400	1716	* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" Clock selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1717	* @retval None
AnnaBridge	172:65be27845400	1718	*/
AnnaBridge	172:65be27845400	1719	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	172:65be27845400	1720	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1721	do \
AnnaBridge	172:65be27845400	1722	{ \
AnnaBridge	172:65be27845400	1723	if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \
AnnaBridge	172:65be27845400	1724	{ \
AnnaBridge	172:65be27845400	1725	SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
AnnaBridge	172:65be27845400	1726	} \
AnnaBridge	172:65be27845400	1727	else \
AnnaBridge	172:65be27845400	1728	{ \
AnnaBridge	172:65be27845400	1729	CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \
AnnaBridge	172:65be27845400	1730	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__)); \
AnnaBridge	172:65be27845400	1731	} \
AnnaBridge	172:65be27845400	1732	} while(0)
AnnaBridge	172:65be27845400	1733	#else
AnnaBridge	172:65be27845400	1734	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1735	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__SDMMC1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1736	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	172:65be27845400	1737
AnnaBridge	172:65be27845400	1738	/** @brief Macro to get the SDMMC1 clock.
AnnaBridge	172:65be27845400	1739	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1740	@if STM32L486xx
AnnaBridge	172:65be27845400	1741	* @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock for devices without HSI48
AnnaBridge	172:65be27845400	1742	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1743	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1744	@endif
AnnaBridge	172:65be27845400	1745	@if STM32L443xx
AnnaBridge	172:65be27845400	1746	* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge	172:65be27845400	1747	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1748	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1749	@endif
AnnaBridge	172:65be27845400	1750	@if STM32L4S9xx
AnnaBridge	172:65be27845400	1751	* @arg @ref RCC_SDMMC1CLKSOURCE_HSI48 HSI48 selected as SDMMC1 clock for devices with HSI48
AnnaBridge	172:65be27845400	1752	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1753	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1754	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 kernel clock
AnnaBridge	172:65be27845400	1755	@endif
AnnaBridge	172:65be27845400	1756	* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
AnnaBridge	172:65be27845400	1757	*/
AnnaBridge	172:65be27845400	1758	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	172:65be27845400	1759	#define __HAL_RCC_GET_SDMMC1_SOURCE() \
AnnaBridge	172:65be27845400	1760	((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != RESET) ? RCC_SDMMC1CLKSOURCE_PLLP : (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
AnnaBridge	172:65be27845400	1761	#else
AnnaBridge	172:65be27845400	1762	#define __HAL_RCC_GET_SDMMC1_SOURCE() \
AnnaBridge	172:65be27845400	1763	(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
AnnaBridge	172:65be27845400	1764	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	172:65be27845400	1765
AnnaBridge	172:65be27845400	1766	#endif /* SDMMC1 */
AnnaBridge	172:65be27845400	1767
AnnaBridge	172:65be27845400	1768	/** @brief Macro to configure the RNG clock.
AnnaBridge	172:65be27845400	1769	*
AnnaBridge	172:65be27845400	1770	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge	172:65be27845400	1771	*
AnnaBridge	172:65be27845400	1772	* @param __RNG_CLKSOURCE__ specifies the RNG clock source.
AnnaBridge	172:65be27845400	1773	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1774	@if STM32L486xx
AnnaBridge	172:65be27845400	1775	* @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
AnnaBridge	172:65be27845400	1776	@endif
AnnaBridge	172:65be27845400	1777	@if STM32L443xx
AnnaBridge	172:65be27845400	1778	* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge	172:65be27845400	1779	@endif
AnnaBridge	172:65be27845400	1780	* @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
AnnaBridge	172:65be27845400	1781	* @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
AnnaBridge	172:65be27845400	1782	* @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
AnnaBridge	172:65be27845400	1783	* @retval None
AnnaBridge	172:65be27845400	1784	*/
AnnaBridge	172:65be27845400	1785	#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1786	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
AnnaBridge	172:65be27845400	1787
AnnaBridge	172:65be27845400	1788	/** @brief Macro to get the RNG clock.
AnnaBridge	172:65be27845400	1789	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1790	@if STM32L486xx
AnnaBridge	172:65be27845400	1791	* @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock for devices without HSI48
AnnaBridge	172:65be27845400	1792	@endif
AnnaBridge	172:65be27845400	1793	@if STM32L443xx
AnnaBridge	172:65be27845400	1794	* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock clock for devices with HSI48
AnnaBridge	172:65be27845400	1795	@endif
AnnaBridge	172:65be27845400	1796	* @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
AnnaBridge	172:65be27845400	1797	* @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
AnnaBridge	172:65be27845400	1798	* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
AnnaBridge	172:65be27845400	1799	*/
AnnaBridge	172:65be27845400	1800	#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
AnnaBridge	172:65be27845400	1801
AnnaBridge	172:65be27845400	1802	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	172:65be27845400	1803
AnnaBridge	172:65be27845400	1804	/** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge	172:65be27845400	1805	*
AnnaBridge	172:65be27845400	1806	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
AnnaBridge	172:65be27845400	1807	*
AnnaBridge	172:65be27845400	1808	* @param __USB_CLKSOURCE__ specifies the USB clock source.
AnnaBridge	172:65be27845400	1809	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1810	@if STM32L486xx
AnnaBridge	172:65be27845400	1811	* @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
AnnaBridge	172:65be27845400	1812	@endif
AnnaBridge	172:65be27845400	1813	@if STM32L443xx
AnnaBridge	172:65be27845400	1814	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge	172:65be27845400	1815	@endif
AnnaBridge	172:65be27845400	1816	* @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
AnnaBridge	172:65be27845400	1817	* @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
AnnaBridge	172:65be27845400	1818	* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
AnnaBridge	172:65be27845400	1819	* @retval None
AnnaBridge	172:65be27845400	1820	*/
AnnaBridge	172:65be27845400	1821	#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1822	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
AnnaBridge	172:65be27845400	1823
AnnaBridge	172:65be27845400	1824	/** @brief Macro to get the USB clock source.
AnnaBridge	172:65be27845400	1825	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1826	@if STM32L486xx
AnnaBridge	172:65be27845400	1827	* @arg @ref RCC_USBCLKSOURCE_NONE No clock selected as 48MHz clock for devices without HSI48
AnnaBridge	172:65be27845400	1828	@endif
AnnaBridge	172:65be27845400	1829	@if STM32L443xx
AnnaBridge	172:65be27845400	1830	* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
AnnaBridge	172:65be27845400	1831	@endif
AnnaBridge	172:65be27845400	1832	* @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
AnnaBridge	172:65be27845400	1833	* @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
AnnaBridge	172:65be27845400	1834	* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
AnnaBridge	172:65be27845400	1835	*/
AnnaBridge	172:65be27845400	1836	#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
AnnaBridge	172:65be27845400	1837
AnnaBridge	172:65be27845400	1838	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	172:65be27845400	1839
AnnaBridge	172:65be27845400	1840	/** @brief Macro to configure the ADC interface clock.
AnnaBridge	172:65be27845400	1841	* @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
AnnaBridge	172:65be27845400	1842	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1843	* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
AnnaBridge	172:65be27845400	1844	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
AnnaBridge	172:65be27845400	1845	@if STM32L486xx
AnnaBridge	172:65be27845400	1846	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge	172:65be27845400	1847	@endif
AnnaBridge	172:65be27845400	1848	* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
AnnaBridge	172:65be27845400	1849	* @retval None
AnnaBridge	172:65be27845400	1850	*/
AnnaBridge	172:65be27845400	1851	#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1852	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (__ADC_CLKSOURCE__))
AnnaBridge	172:65be27845400	1853
AnnaBridge	172:65be27845400	1854	/** @brief Macro to get the ADC clock source.
AnnaBridge	172:65be27845400	1855	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1856	* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
AnnaBridge	172:65be27845400	1857	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
AnnaBridge	172:65be27845400	1858	@if STM32L486xx
AnnaBridge	172:65be27845400	1859	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock for STM32L47x/STM32L48x/STM32L49x/STM32L4Ax devices
AnnaBridge	172:65be27845400	1860	@endif
AnnaBridge	172:65be27845400	1861	* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
AnnaBridge	172:65be27845400	1862	*/
AnnaBridge	172:65be27845400	1863	#define __HAL_RCC_GET_ADC_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))
AnnaBridge	172:65be27845400	1864
AnnaBridge	172:65be27845400	1865	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	1866
AnnaBridge	172:65be27845400	1867	/** @brief Macro to configure the SWPMI1 clock.
AnnaBridge	172:65be27845400	1868	* @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
AnnaBridge	172:65be27845400	1869	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1870	* @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	1871	* @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	1872	* @retval None
AnnaBridge	172:65be27845400	1873	*/
AnnaBridge	172:65be27845400	1874	#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1875	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (__SWPMI1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1876
AnnaBridge	172:65be27845400	1877	/** @brief Macro to get the SWPMI1 clock source.
AnnaBridge	172:65be27845400	1878	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1879	* @arg @ref RCC_SWPMI1CLKSOURCE_PCLK1 PCLK1 Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	1880	* @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	1881	*/
AnnaBridge	172:65be27845400	1882	#define __HAL_RCC_GET_SWPMI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))
AnnaBridge	172:65be27845400	1883
AnnaBridge	172:65be27845400	1884	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	1885
AnnaBridge	172:65be27845400	1886	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	1887	/** @brief Macro to configure the DFSDM1 clock.
AnnaBridge	172:65be27845400	1888	* @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
AnnaBridge	172:65be27845400	1889	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1890	* @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	1891	* @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	1892	* @retval None
AnnaBridge	172:65be27845400	1893	*/
AnnaBridge	172:65be27845400	1894	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1895	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1896	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1897	#else
AnnaBridge	172:65be27845400	1898	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1899	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, (__DFSDM1_CLKSOURCE__))
AnnaBridge	172:65be27845400	1900	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1901
AnnaBridge	172:65be27845400	1902	/** @brief Macro to get the DFSDM1 clock source.
AnnaBridge	172:65be27845400	1903	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1904	* @arg @ref RCC_DFSDM1CLKSOURCE_PCLK2 PCLK2 Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	1905	* @arg @ref RCC_DFSDM1CLKSOURCE_SYSCLK System Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	1906	*/
AnnaBridge	172:65be27845400	1907	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1908	#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL))
AnnaBridge	172:65be27845400	1909	#else
AnnaBridge	172:65be27845400	1910	#define __HAL_RCC_GET_DFSDM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL))
AnnaBridge	172:65be27845400	1911	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1912
AnnaBridge	172:65be27845400	1913	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	1914
AnnaBridge	172:65be27845400	1915	/** @brief Macro to configure the DFSDM1 audio clock.
AnnaBridge	172:65be27845400	1916	* @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 audio clock source.
AnnaBridge	172:65be27845400	1917	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1918	* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock
AnnaBridge	172:65be27845400	1919	* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock
AnnaBridge	172:65be27845400	1920	* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock
AnnaBridge	172:65be27845400	1921	* @retval None
AnnaBridge	172:65be27845400	1922	*/
AnnaBridge	172:65be27845400	1923	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1924	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, (__DFSDM1AUDIO_CLKSOURCE__))
AnnaBridge	172:65be27845400	1925
AnnaBridge	172:65be27845400	1926	/** @brief Macro to get the DFSDM1 audio clock source.
AnnaBridge	172:65be27845400	1927	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1928	* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_SAI1 SAI1 clock selected as DFSDM1 audio clock
AnnaBridge	172:65be27845400	1929	* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_HSI HSI clock selected as DFSDM1 audio clock
AnnaBridge	172:65be27845400	1930	* @arg @ref RCC_DFSDM1AUDIOCLKSOURCE_MSI MSI clock selected as DFSDM1 audio clock
AnnaBridge	172:65be27845400	1931	*/
AnnaBridge	172:65be27845400	1932	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL))
AnnaBridge	172:65be27845400	1933
AnnaBridge	172:65be27845400	1934	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	1935
AnnaBridge	172:65be27845400	1936	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	1937
AnnaBridge	172:65be27845400	1938	#if defined(LTDC)
AnnaBridge	172:65be27845400	1939
AnnaBridge	172:65be27845400	1940	/** @brief Macro to configure the LTDC clock.
AnnaBridge	172:65be27845400	1941	* @param __LTDC_CLKSOURCE__ specifies the DSI clock source.
AnnaBridge	172:65be27845400	1942	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1943	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1944	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1945	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1946	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1947	* @retval None
AnnaBridge	172:65be27845400	1948	*/
AnnaBridge	172:65be27845400	1949	#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1950	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, (__LTDC_CLKSOURCE__))
AnnaBridge	172:65be27845400	1951
AnnaBridge	172:65be27845400	1952	/** @brief Macro to get the LTDC clock source.
AnnaBridge	172:65be27845400	1953	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1954	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV2 PLLSAI2 divider R divided by 2 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1955	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV4 PLLSAI2 divider R divided by 4 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1956	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV8 PLLSAI2 divider R divided by 8 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1957	* @arg @ref RCC_LTDCCLKSOURCE_PLLSAI2_DIV16 PLLSAI2 divider R divided by 16 clock selected as LTDC clock
AnnaBridge	172:65be27845400	1958	*/
AnnaBridge	172:65be27845400	1959	#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR))
AnnaBridge	172:65be27845400	1960
AnnaBridge	172:65be27845400	1961	#endif /* LTDC */
AnnaBridge	172:65be27845400	1962
AnnaBridge	172:65be27845400	1963	#if defined(DSI)
AnnaBridge	172:65be27845400	1964
AnnaBridge	172:65be27845400	1965	/** @brief Macro to configure the DSI clock.
AnnaBridge	172:65be27845400	1966	* @param __DSI_CLKSOURCE__ specifies the DSI clock source.
AnnaBridge	172:65be27845400	1967	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1968	* @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
AnnaBridge	172:65be27845400	1969	* @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock
AnnaBridge	172:65be27845400	1970	* @retval None
AnnaBridge	172:65be27845400	1971	*/
AnnaBridge	172:65be27845400	1972	#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1973	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, (__DSI_CLKSOURCE__))
AnnaBridge	172:65be27845400	1974
AnnaBridge	172:65be27845400	1975	/** @brief Macro to get the DSI clock source.
AnnaBridge	172:65be27845400	1976	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1977	* @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock
AnnaBridge	172:65be27845400	1978	* @arg @ref RCC_DSICLKSOURCE_PLLSAI2 PLLSAI2 R divider clock selected as DSI clock
AnnaBridge	172:65be27845400	1979	*/
AnnaBridge	172:65be27845400	1980	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSISEL))
AnnaBridge	172:65be27845400	1981
AnnaBridge	172:65be27845400	1982	#endif /* DSI */
AnnaBridge	172:65be27845400	1983
AnnaBridge	172:65be27845400	1984	#if defined(OCTOSPI1) \|\| defined(OCTOSPI2)
AnnaBridge	172:65be27845400	1985
AnnaBridge	172:65be27845400	1986	/** @brief Macro to configure the OctoSPI clock.
AnnaBridge	172:65be27845400	1987	* @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source.
AnnaBridge	172:65be27845400	1988	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1989	* @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock
AnnaBridge	172:65be27845400	1990	* @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock
AnnaBridge	172:65be27845400	1991	* @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock
AnnaBridge	172:65be27845400	1992	* @retval None
AnnaBridge	172:65be27845400	1993	*/
AnnaBridge	172:65be27845400	1994	#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \
AnnaBridge	172:65be27845400	1995	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (__OSPI_CLKSOURCE__))
AnnaBridge	172:65be27845400	1996
AnnaBridge	172:65be27845400	1997	/** @brief Macro to get the OctoSPI clock source.
AnnaBridge	172:65be27845400	1998	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1999	* @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock
AnnaBridge	172:65be27845400	2000	* @arg @ref RCC_OSPICLKSOURCE_MSI MSI clock selected as OctoSPI clock
AnnaBridge	172:65be27845400	2001	* @arg @ref RCC_OSPICLKSOURCE_PLL PLL Q divider clock selected as OctoSPI clock
AnnaBridge	172:65be27845400	2002	*/
AnnaBridge	172:65be27845400	2003	#define __HAL_RCC_GET_OSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OSPISEL))
AnnaBridge	172:65be27845400	2004
AnnaBridge	172:65be27845400	2005	#endif /* OCTOSPI1 \|\| OCTOSPI2 */
AnnaBridge	172:65be27845400	2006
AnnaBridge	172:65be27845400	2007	/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	172:65be27845400	2008	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	172:65be27845400	2009	* @{
AnnaBridge	172:65be27845400	2010	*/
AnnaBridge	172:65be27845400	2011
AnnaBridge	172:65be27845400	2012	/** @brief Enable PLLSAI1RDY interrupt.
AnnaBridge	172:65be27845400	2013	* @retval None
AnnaBridge	172:65be27845400	2014	*/
AnnaBridge	172:65be27845400	2015	#define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
AnnaBridge	172:65be27845400	2016
AnnaBridge	172:65be27845400	2017	/** @brief Disable PLLSAI1RDY interrupt.
AnnaBridge	172:65be27845400	2018	* @retval None
AnnaBridge	172:65be27845400	2019	*/
AnnaBridge	172:65be27845400	2020	#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
AnnaBridge	172:65be27845400	2021
AnnaBridge	172:65be27845400	2022	/** @brief Clear the PLLSAI1RDY interrupt pending bit.
AnnaBridge	172:65be27845400	2023	* @retval None
AnnaBridge	172:65be27845400	2024	*/
AnnaBridge	172:65be27845400	2025	#define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
AnnaBridge	172:65be27845400	2026
AnnaBridge	172:65be27845400	2027	/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
AnnaBridge	172:65be27845400	2028	* @retval TRUE or FALSE.
AnnaBridge	172:65be27845400	2029	*/
AnnaBridge	172:65be27845400	2030	#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
AnnaBridge	172:65be27845400	2031
AnnaBridge	172:65be27845400	2032	/** @brief Check whether the PLLSAI1RDY flag is set or not.
AnnaBridge	172:65be27845400	2033	* @retval TRUE or FALSE.
AnnaBridge	172:65be27845400	2034	*/
AnnaBridge	172:65be27845400	2035	#define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
AnnaBridge	172:65be27845400	2036
AnnaBridge	172:65be27845400	2037	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	2038
AnnaBridge	172:65be27845400	2039	/** @brief Enable PLLSAI2RDY interrupt.
AnnaBridge	172:65be27845400	2040	* @retval None
AnnaBridge	172:65be27845400	2041	*/
AnnaBridge	172:65be27845400	2042	#define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
AnnaBridge	172:65be27845400	2043
AnnaBridge	172:65be27845400	2044	/** @brief Disable PLLSAI2RDY interrupt.
AnnaBridge	172:65be27845400	2045	* @retval None
AnnaBridge	172:65be27845400	2046	*/
AnnaBridge	172:65be27845400	2047	#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
AnnaBridge	172:65be27845400	2048
AnnaBridge	172:65be27845400	2049	/** @brief Clear the PLLSAI2RDY interrupt pending bit.
AnnaBridge	172:65be27845400	2050	* @retval None
AnnaBridge	172:65be27845400	2051	*/
AnnaBridge	172:65be27845400	2052	#define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
AnnaBridge	172:65be27845400	2053
AnnaBridge	172:65be27845400	2054	/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
AnnaBridge	172:65be27845400	2055	* @retval TRUE or FALSE.
AnnaBridge	172:65be27845400	2056	*/
AnnaBridge	172:65be27845400	2057	#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
AnnaBridge	172:65be27845400	2058
AnnaBridge	172:65be27845400	2059	/** @brief Check whether the PLLSAI2RDY flag is set or not.
AnnaBridge	172:65be27845400	2060	* @retval TRUE or FALSE.
AnnaBridge	172:65be27845400	2061	*/
AnnaBridge	172:65be27845400	2062	#define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
AnnaBridge	172:65be27845400	2063
AnnaBridge	172:65be27845400	2064	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	2065
AnnaBridge	172:65be27845400	2066
AnnaBridge	172:65be27845400	2067	/**
AnnaBridge	172:65be27845400	2068	* @brief Enable the RCC LSE CSS Extended Interrupt Line.
AnnaBridge	172:65be27845400	2069	* @retval None
AnnaBridge	172:65be27845400	2070	*/
AnnaBridge	172:65be27845400	2071	#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2072
AnnaBridge	172:65be27845400	2073	/**
AnnaBridge	172:65be27845400	2074	* @brief Disable the RCC LSE CSS Extended Interrupt Line.
AnnaBridge	172:65be27845400	2075	* @retval None
AnnaBridge	172:65be27845400	2076	*/
AnnaBridge	172:65be27845400	2077	#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2078
AnnaBridge	172:65be27845400	2079	/**
AnnaBridge	172:65be27845400	2080	* @brief Enable the RCC LSE CSS Event Line.
AnnaBridge	172:65be27845400	2081	* @retval None.
AnnaBridge	172:65be27845400	2082	*/
AnnaBridge	172:65be27845400	2083	#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2084
AnnaBridge	172:65be27845400	2085	/**
AnnaBridge	172:65be27845400	2086	* @brief Disable the RCC LSE CSS Event Line.
AnnaBridge	172:65be27845400	2087	* @retval None.
AnnaBridge	172:65be27845400	2088	*/
AnnaBridge	172:65be27845400	2089	#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2090
AnnaBridge	172:65be27845400	2091
AnnaBridge	172:65be27845400	2092	/**
AnnaBridge	172:65be27845400	2093	* @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
AnnaBridge	172:65be27845400	2094	* @retval None.
AnnaBridge	172:65be27845400	2095	*/
AnnaBridge	172:65be27845400	2096	#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2097
AnnaBridge	172:65be27845400	2098
AnnaBridge	172:65be27845400	2099	/**
AnnaBridge	172:65be27845400	2100	* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
AnnaBridge	172:65be27845400	2101	* @retval None.
AnnaBridge	172:65be27845400	2102	*/
AnnaBridge	172:65be27845400	2103	#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2104
AnnaBridge	172:65be27845400	2105
AnnaBridge	172:65be27845400	2106	/**
AnnaBridge	172:65be27845400	2107	* @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
AnnaBridge	172:65be27845400	2108	* @retval None.
AnnaBridge	172:65be27845400	2109	*/
AnnaBridge	172:65be27845400	2110	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2111
AnnaBridge	172:65be27845400	2112	/**
AnnaBridge	172:65be27845400	2113	* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
AnnaBridge	172:65be27845400	2114	* @retval None.
AnnaBridge	172:65be27845400	2115	*/
AnnaBridge	172:65be27845400	2116	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2117
AnnaBridge	172:65be27845400	2118	/**
AnnaBridge	172:65be27845400	2119	* @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
AnnaBridge	172:65be27845400	2120	* @retval None.
AnnaBridge	172:65be27845400	2121	*/
AnnaBridge	172:65be27845400	2122	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
AnnaBridge	172:65be27845400	2123	do { \
AnnaBridge	172:65be27845400	2124	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
AnnaBridge	172:65be27845400	2125	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
AnnaBridge	172:65be27845400	2126	} while(0)
AnnaBridge	172:65be27845400	2127
AnnaBridge	172:65be27845400	2128	/**
AnnaBridge	172:65be27845400	2129	* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
AnnaBridge	172:65be27845400	2130	* @retval None.
AnnaBridge	172:65be27845400	2131	*/
AnnaBridge	172:65be27845400	2132	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
AnnaBridge	172:65be27845400	2133	do { \
AnnaBridge	172:65be27845400	2134	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
AnnaBridge	172:65be27845400	2135	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
AnnaBridge	172:65be27845400	2136	} while(0)
AnnaBridge	172:65be27845400	2137
AnnaBridge	172:65be27845400	2138	/**
AnnaBridge	172:65be27845400	2139	* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
AnnaBridge	172:65be27845400	2140	* @retval EXTI RCC LSE CSS Line Status.
AnnaBridge	172:65be27845400	2141	*/
AnnaBridge	172:65be27845400	2142	#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2143
AnnaBridge	172:65be27845400	2144	/**
AnnaBridge	172:65be27845400	2145	* @brief Clear the RCC LSE CSS EXTI flag.
AnnaBridge	172:65be27845400	2146	* @retval None.
AnnaBridge	172:65be27845400	2147	*/
AnnaBridge	172:65be27845400	2148	#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2149
AnnaBridge	172:65be27845400	2150	/**
AnnaBridge	172:65be27845400	2151	* @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
AnnaBridge	172:65be27845400	2152	* @retval None.
AnnaBridge	172:65be27845400	2153	*/
AnnaBridge	172:65be27845400	2154	#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
AnnaBridge	172:65be27845400	2155
AnnaBridge	172:65be27845400	2156
AnnaBridge	172:65be27845400	2157	#if defined(CRS)
AnnaBridge	172:65be27845400	2158
AnnaBridge	172:65be27845400	2159	/**
AnnaBridge	172:65be27845400	2160	* @brief Enable the specified CRS interrupts.
AnnaBridge	172:65be27845400	2161	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
AnnaBridge	172:65be27845400	2162	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	2163	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2164	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2165	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2166	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2167	* @retval None
AnnaBridge	172:65be27845400	2168	*/
AnnaBridge	172:65be27845400	2169	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	172:65be27845400	2170
AnnaBridge	172:65be27845400	2171	/**
AnnaBridge	172:65be27845400	2172	* @brief Disable the specified CRS interrupts.
AnnaBridge	172:65be27845400	2173	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
AnnaBridge	172:65be27845400	2174	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	2175	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2176	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2177	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2178	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2179	* @retval None
AnnaBridge	172:65be27845400	2180	*/
AnnaBridge	172:65be27845400	2181	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	172:65be27845400	2182
AnnaBridge	172:65be27845400	2183	/** @brief Check whether the CRS interrupt has occurred or not.
AnnaBridge	172:65be27845400	2184	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
AnnaBridge	172:65be27845400	2185	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2186	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2187	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2188	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2189	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2190	* @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge	172:65be27845400	2191	*/
AnnaBridge	172:65be27845400	2192	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET)
AnnaBridge	172:65be27845400	2193
AnnaBridge	172:65be27845400	2194	/** @brief Clear the CRS interrupt pending bits
AnnaBridge	172:65be27845400	2195	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	2196	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	2197	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2198	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2199	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2200	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2201	* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
AnnaBridge	172:65be27845400	2202	* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
AnnaBridge	172:65be27845400	2203	* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
AnnaBridge	172:65be27845400	2204	*/
AnnaBridge	172:65be27845400	2205	/* CRS IT Error Mask */
AnnaBridge	172:65be27845400	2206	#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS)
AnnaBridge	172:65be27845400	2207
AnnaBridge	172:65be27845400	2208	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
AnnaBridge	172:65be27845400	2209	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != RESET) \
AnnaBridge	172:65be27845400	2210	{ \
AnnaBridge	172:65be27845400	2211	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
AnnaBridge	172:65be27845400	2212	} \
AnnaBridge	172:65be27845400	2213	else \
AnnaBridge	172:65be27845400	2214	{ \
AnnaBridge	172:65be27845400	2215	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
AnnaBridge	172:65be27845400	2216	} \
AnnaBridge	172:65be27845400	2217	} while(0)
AnnaBridge	172:65be27845400	2218
AnnaBridge	172:65be27845400	2219	/**
AnnaBridge	172:65be27845400	2220	* @brief Check whether the specified CRS flag is set or not.
AnnaBridge	172:65be27845400	2221	* @param __FLAG__ specifies the flag to check.
AnnaBridge	172:65be27845400	2222	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2223	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	172:65be27845400	2224	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	172:65be27845400	2225	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	172:65be27845400	2226	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	172:65be27845400	2227	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	172:65be27845400	2228	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	172:65be27845400	2229	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	172:65be27845400	2230	* @retval The new state of _FLAG_ (TRUE or FALSE).
AnnaBridge	172:65be27845400	2231	*/
AnnaBridge	172:65be27845400	2232	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	2233
AnnaBridge	172:65be27845400	2234	/**
AnnaBridge	172:65be27845400	2235	* @brief Clear the CRS specified FLAG.
AnnaBridge	172:65be27845400	2236	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	172:65be27845400	2237	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2238	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	172:65be27845400	2239	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	172:65be27845400	2240	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	172:65be27845400	2241	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	172:65be27845400	2242	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	172:65be27845400	2243	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	172:65be27845400	2244	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	172:65be27845400	2245	* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
AnnaBridge	172:65be27845400	2246	* @retval None
AnnaBridge	172:65be27845400	2247	*/
AnnaBridge	172:65be27845400	2248
AnnaBridge	172:65be27845400	2249	/* CRS Flag Error Mask */
AnnaBridge	172:65be27845400	2250	#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS)
AnnaBridge	172:65be27845400	2251
AnnaBridge	172:65be27845400	2252	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
AnnaBridge	172:65be27845400	2253	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != RESET) \
AnnaBridge	172:65be27845400	2254	{ \
AnnaBridge	172:65be27845400	2255	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
AnnaBridge	172:65be27845400	2256	} \
AnnaBridge	172:65be27845400	2257	else \
AnnaBridge	172:65be27845400	2258	{ \
AnnaBridge	172:65be27845400	2259	WRITE_REG(CRS->ICR, (__FLAG__)); \
AnnaBridge	172:65be27845400	2260	} \
AnnaBridge	172:65be27845400	2261	} while(0)
AnnaBridge	172:65be27845400	2262
AnnaBridge	172:65be27845400	2263	#endif /* CRS */
AnnaBridge	172:65be27845400	2264
AnnaBridge	172:65be27845400	2265	/**
AnnaBridge	172:65be27845400	2266	* @}
AnnaBridge	172:65be27845400	2267	*/
AnnaBridge	172:65be27845400	2268
AnnaBridge	172:65be27845400	2269	#if defined(CRS)
AnnaBridge	172:65be27845400	2270
AnnaBridge	172:65be27845400	2271	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
AnnaBridge	172:65be27845400	2272	* @{
AnnaBridge	172:65be27845400	2273	*/
AnnaBridge	172:65be27845400	2274	/**
AnnaBridge	172:65be27845400	2275	* @brief Enable the oscillator clock for frequency error counter.
AnnaBridge	172:65be27845400	2276	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	172:65be27845400	2277	* @retval None
AnnaBridge	172:65be27845400	2278	*/
AnnaBridge	172:65be27845400	2279	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	172:65be27845400	2280
AnnaBridge	172:65be27845400	2281	/**
AnnaBridge	172:65be27845400	2282	* @brief Disable the oscillator clock for frequency error counter.
AnnaBridge	172:65be27845400	2283	* @retval None
AnnaBridge	172:65be27845400	2284	*/
AnnaBridge	172:65be27845400	2285	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	172:65be27845400	2286
AnnaBridge	172:65be27845400	2287	/**
AnnaBridge	172:65be27845400	2288	* @brief Enable the automatic hardware adjustement of TRIM bits.
AnnaBridge	172:65be27845400	2289	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	172:65be27845400	2290	* @retval None
AnnaBridge	172:65be27845400	2291	*/
AnnaBridge	172:65be27845400	2292	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	172:65be27845400	2293
AnnaBridge	172:65be27845400	2294	/**
AnnaBridge	172:65be27845400	2295	* @brief Enable or disable the automatic hardware adjustement of TRIM bits.
AnnaBridge	172:65be27845400	2296	* @retval None
AnnaBridge	172:65be27845400	2297	*/
AnnaBridge	172:65be27845400	2298	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	172:65be27845400	2299
AnnaBridge	172:65be27845400	2300	/**
AnnaBridge	172:65be27845400	2301	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge	172:65be27845400	2302	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge	172:65be27845400	2303	* of the synchronization source after prescaling. It is then decreased by one in order to
AnnaBridge	172:65be27845400	2304	* reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge	172:65be27845400	2305	* RELOAD = (fTARGET / fSYNC) -1
AnnaBridge	172:65be27845400	2306	* @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge	172:65be27845400	2307	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge	172:65be27845400	2308	* @retval None
AnnaBridge	172:65be27845400	2309	*/
AnnaBridge	172:65be27845400	2310	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge	172:65be27845400	2311
AnnaBridge	172:65be27845400	2312	/**
AnnaBridge	172:65be27845400	2313	* @}
AnnaBridge	172:65be27845400	2314	*/
AnnaBridge	172:65be27845400	2315
AnnaBridge	172:65be27845400	2316	#endif /* CRS */
AnnaBridge	172:65be27845400	2317
AnnaBridge	172:65be27845400	2318	/**
AnnaBridge	172:65be27845400	2319	* @}
AnnaBridge	172:65be27845400	2320	*/
AnnaBridge	172:65be27845400	2321
AnnaBridge	172:65be27845400	2322	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	2323	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	172:65be27845400	2324	* @{
AnnaBridge	172:65be27845400	2325	*/
AnnaBridge	172:65be27845400	2326
AnnaBridge	172:65be27845400	2327	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	172:65be27845400	2328	* @{
AnnaBridge	172:65be27845400	2329	*/
AnnaBridge	172:65be27845400	2330
AnnaBridge	172:65be27845400	2331	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	172:65be27845400	2332	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	172:65be27845400	2333	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	172:65be27845400	2334
AnnaBridge	172:65be27845400	2335	/**
AnnaBridge	172:65be27845400	2336	* @}
AnnaBridge	172:65be27845400	2337	*/
AnnaBridge	172:65be27845400	2338
AnnaBridge	172:65be27845400	2339	/** @addtogroup RCCEx_Exported_Functions_Group2
AnnaBridge	172:65be27845400	2340	* @{
AnnaBridge	172:65be27845400	2341	*/
AnnaBridge	172:65be27845400	2342
AnnaBridge	172:65be27845400	2343	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
AnnaBridge	172:65be27845400	2344	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
AnnaBridge	172:65be27845400	2345
AnnaBridge	172:65be27845400	2346	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	2347
AnnaBridge	172:65be27845400	2348	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
AnnaBridge	172:65be27845400	2349	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
AnnaBridge	172:65be27845400	2350
AnnaBridge	172:65be27845400	2351	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	2352
AnnaBridge	172:65be27845400	2353	void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
AnnaBridge	172:65be27845400	2354	void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
AnnaBridge	172:65be27845400	2355	void HAL_RCCEx_EnableLSECSS(void);
AnnaBridge	172:65be27845400	2356	void HAL_RCCEx_DisableLSECSS(void);
AnnaBridge	172:65be27845400	2357	void HAL_RCCEx_EnableLSECSS_IT(void);
AnnaBridge	172:65be27845400	2358	void HAL_RCCEx_LSECSS_IRQHandler(void);
AnnaBridge	172:65be27845400	2359	void HAL_RCCEx_LSECSS_Callback(void);
AnnaBridge	172:65be27845400	2360	void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
AnnaBridge	172:65be27845400	2361	void HAL_RCCEx_DisableLSCO(void);
AnnaBridge	172:65be27845400	2362	void HAL_RCCEx_EnableMSIPLLMode(void);
AnnaBridge	172:65be27845400	2363	void HAL_RCCEx_DisableMSIPLLMode(void);
AnnaBridge	172:65be27845400	2364
AnnaBridge	172:65be27845400	2365	/**
AnnaBridge	172:65be27845400	2366	* @}
AnnaBridge	172:65be27845400	2367	*/
AnnaBridge	172:65be27845400	2368
AnnaBridge	172:65be27845400	2369	#if defined(CRS)
AnnaBridge	172:65be27845400	2370
AnnaBridge	172:65be27845400	2371	/** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge	172:65be27845400	2372	* @{
AnnaBridge	172:65be27845400	2373	*/
AnnaBridge	172:65be27845400	2374
AnnaBridge	172:65be27845400	2375	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge	172:65be27845400	2376	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge	172:65be27845400	2377	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge	172:65be27845400	2378	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge	172:65be27845400	2379	void HAL_RCCEx_CRS_IRQHandler(void);
AnnaBridge	172:65be27845400	2380	void HAL_RCCEx_CRS_SyncOkCallback(void);
AnnaBridge	172:65be27845400	2381	void HAL_RCCEx_CRS_SyncWarnCallback(void);
AnnaBridge	172:65be27845400	2382	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
AnnaBridge	172:65be27845400	2383	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
AnnaBridge	172:65be27845400	2384
AnnaBridge	172:65be27845400	2385	/**
AnnaBridge	172:65be27845400	2386	* @}
AnnaBridge	172:65be27845400	2387	*/
AnnaBridge	172:65be27845400	2388
AnnaBridge	172:65be27845400	2389	#endif /* CRS */
AnnaBridge	172:65be27845400	2390
AnnaBridge	172:65be27845400	2391	/**
AnnaBridge	172:65be27845400	2392	* @}
AnnaBridge	172:65be27845400	2393	*/
AnnaBridge	172:65be27845400	2394
AnnaBridge	172:65be27845400	2395	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	2396	/** @addtogroup RCCEx_Private_Macros
AnnaBridge	172:65be27845400	2397	* @{
AnnaBridge	172:65be27845400	2398	*/
AnnaBridge	172:65be27845400	2399
AnnaBridge	172:65be27845400	2400	#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	2401	((__SOURCE__) == RCC_LSCOSOURCE_LSE))
AnnaBridge	172:65be27845400	2402
AnnaBridge	172:65be27845400	2403	#if defined(STM32L431xx)
AnnaBridge	172:65be27845400	2404
AnnaBridge	172:65be27845400	2405	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2406	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2407	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2408	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2409	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2410	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2411	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2412	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2413	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2414	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2415	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2416	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2417	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
AnnaBridge	172:65be27845400	2418	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2419	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2420	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2421
AnnaBridge	172:65be27845400	2422	#elif defined(STM32L432xx) \|\| defined(STM32L442xx)
AnnaBridge	172:65be27845400	2423
AnnaBridge	172:65be27845400	2424	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2425	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2426	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2427	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2428	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2429	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2430	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2431	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2432	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2433	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2434	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2435	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
AnnaBridge	172:65be27845400	2436	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2437	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG))
AnnaBridge	172:65be27845400	2438
AnnaBridge	172:65be27845400	2439	#elif defined(STM32L433xx) \|\| defined(STM32L443xx)
AnnaBridge	172:65be27845400	2440
AnnaBridge	172:65be27845400	2441	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2442	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2443	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2444	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2445	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2446	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2447	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2448	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2449	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2450	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2451	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2452	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2453	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2454	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
AnnaBridge	172:65be27845400	2455	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2456	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2457	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2458
AnnaBridge	172:65be27845400	2459	#elif defined(STM32L451xx)
AnnaBridge	172:65be27845400	2460
AnnaBridge	172:65be27845400	2461	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2462	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2463	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2464	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2465	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2466	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2467	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2468	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2469	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2470	(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	172:65be27845400	2471	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2472	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2473	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2474	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2475	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2476	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2477	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2478	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2479
AnnaBridge	172:65be27845400	2480	#elif defined(STM32L452xx) \|\| defined(STM32L462xx)
AnnaBridge	172:65be27845400	2481
AnnaBridge	172:65be27845400	2482	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2483	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2484	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2485	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2486	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2487	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2488	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2489	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2490	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2491	(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	172:65be27845400	2492	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2493	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2494	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2495	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2496	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2497	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2498	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2499	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2500	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2501
AnnaBridge	172:65be27845400	2502	#elif defined(STM32L471xx)
AnnaBridge	172:65be27845400	2503
AnnaBridge	172:65be27845400	2504	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2505	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2506	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2507	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2508	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2509	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	172:65be27845400	2510	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2511	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2512	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2513	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2514	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2515	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2516	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2517	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	172:65be27845400	2518	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2519	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
AnnaBridge	172:65be27845400	2520	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2521	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2522	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2523	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2524
AnnaBridge	172:65be27845400	2525	#elif defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	172:65be27845400	2526
AnnaBridge	172:65be27845400	2527	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2528	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2529	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2530	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2531	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2532	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	172:65be27845400	2533	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2534	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2535	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2536	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2537	(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	172:65be27845400	2538	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2539	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2540	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2541	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	172:65be27845400	2542	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2543	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2544	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
AnnaBridge	172:65be27845400	2545	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2546	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2547	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2548	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2549
AnnaBridge	172:65be27845400	2550	#elif defined(STM32L4R5xx) \|\| defined(STM32L4S5xx)
AnnaBridge	172:65be27845400	2551
AnnaBridge	172:65be27845400	2552	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2553	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2554	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2555	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2556	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2557	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	172:65be27845400	2558	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2559	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2560	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2561	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2562	(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	172:65be27845400	2563	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2564	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2565	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2566	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	172:65be27845400	2567	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2568	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2569	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2570	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) \|\| \
AnnaBridge	172:65be27845400	2571	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2572	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2573	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	172:65be27845400	2574	(((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI))
AnnaBridge	172:65be27845400	2575
AnnaBridge	172:65be27845400	2576	#elif defined(STM32L4R7xx) \|\| defined(STM32L4S7xx)
AnnaBridge	172:65be27845400	2577
AnnaBridge	172:65be27845400	2578	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2579	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2580	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2581	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2582	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2583	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	172:65be27845400	2584	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2585	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2586	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2587	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2588	(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	172:65be27845400	2589	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2590	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2591	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2592	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	172:65be27845400	2593	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2594	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2595	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2596	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) \|\| \
AnnaBridge	172:65be27845400	2597	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2598	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2599	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	172:65be27845400	2600	(((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) \|\| \
AnnaBridge	172:65be27845400	2601	(((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
AnnaBridge	172:65be27845400	2602
AnnaBridge	172:65be27845400	2603	#elif defined(STM32L4R9xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	2604
AnnaBridge	172:65be27845400	2605	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2606	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2607	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2608	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2609	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2610	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	172:65be27845400	2611	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2612	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2613	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2614	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2615	(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
AnnaBridge	172:65be27845400	2616	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2617	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2618	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2619	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	172:65be27845400	2620	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2621	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2622	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2623	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) \|\| \
AnnaBridge	172:65be27845400	2624	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2625	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2626	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
AnnaBridge	172:65be27845400	2627	(((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) \|\| \
AnnaBridge	172:65be27845400	2628	(((__SELECTION__) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
AnnaBridge	172:65be27845400	2629	(((__SELECTION__) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI))
AnnaBridge	172:65be27845400	2630
AnnaBridge	172:65be27845400	2631	#else
AnnaBridge	172:65be27845400	2632
AnnaBridge	172:65be27845400	2633	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	172:65be27845400	2634	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
AnnaBridge	172:65be27845400	2635	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
AnnaBridge	172:65be27845400	2636	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
AnnaBridge	172:65be27845400	2637	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
AnnaBridge	172:65be27845400	2638	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
AnnaBridge	172:65be27845400	2639	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
AnnaBridge	172:65be27845400	2640	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
AnnaBridge	172:65be27845400	2641	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
AnnaBridge	172:65be27845400	2642	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
AnnaBridge	172:65be27845400	2643	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
AnnaBridge	172:65be27845400	2644	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
AnnaBridge	172:65be27845400	2645	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
AnnaBridge	172:65be27845400	2646	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
AnnaBridge	172:65be27845400	2647	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
AnnaBridge	172:65be27845400	2648	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	172:65be27845400	2649	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
AnnaBridge	172:65be27845400	2650	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
AnnaBridge	172:65be27845400	2651	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	172:65be27845400	2652	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
AnnaBridge	172:65be27845400	2653	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
AnnaBridge	172:65be27845400	2654
AnnaBridge	172:65be27845400	2655	#endif /* STM32L431xx */
AnnaBridge	172:65be27845400	2656
AnnaBridge	172:65be27845400	2657	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2658	(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	172:65be27845400	2659	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2660	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2661	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2662
AnnaBridge	172:65be27845400	2663	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2664	(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2665	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2666	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2667	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2668
AnnaBridge	172:65be27845400	2669	#if defined(USART3)
AnnaBridge	172:65be27845400	2670
AnnaBridge	172:65be27845400	2671	#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2672	(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2673	((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2674	((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2675	((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2676
AnnaBridge	172:65be27845400	2677	#endif /* USART3 */
AnnaBridge	172:65be27845400	2678
AnnaBridge	172:65be27845400	2679	#if defined(UART4)
AnnaBridge	172:65be27845400	2680
AnnaBridge	172:65be27845400	2681	#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2682	(((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2683	((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2684	((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2685	((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2686
AnnaBridge	172:65be27845400	2687	#endif /* UART4 */
AnnaBridge	172:65be27845400	2688
AnnaBridge	172:65be27845400	2689	#if defined(UART5)
AnnaBridge	172:65be27845400	2690
AnnaBridge	172:65be27845400	2691	#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2692	(((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2693	((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2694	((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2695	((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2696
AnnaBridge	172:65be27845400	2697	#endif /* UART5 */
AnnaBridge	172:65be27845400	2698
AnnaBridge	172:65be27845400	2699	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2700	(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2701	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2702	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2703	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2704
AnnaBridge	172:65be27845400	2705	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2706	(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2707	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	172:65be27845400	2708	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2709
AnnaBridge	172:65be27845400	2710	#if defined(I2C2)
AnnaBridge	172:65be27845400	2711
AnnaBridge	172:65be27845400	2712	#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2713	(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2714	((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	172:65be27845400	2715	((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2716
AnnaBridge	172:65be27845400	2717	#endif /* I2C2 */
AnnaBridge	172:65be27845400	2718
AnnaBridge	172:65be27845400	2719	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2720	(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2721	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	172:65be27845400	2722	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2723
AnnaBridge	172:65be27845400	2724	#if defined(I2C4)
AnnaBridge	172:65be27845400	2725
AnnaBridge	172:65be27845400	2726	#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2727	(((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2728	((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)\|\| \
AnnaBridge	172:65be27845400	2729	((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2730
AnnaBridge	172:65be27845400	2731	#endif /* I2C4 */
AnnaBridge	172:65be27845400	2732
AnnaBridge	172:65be27845400	2733	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	2734
AnnaBridge	172:65be27845400	2735	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	2736	#define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2737	(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2738	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) \|\| \
AnnaBridge	172:65be27845400	2739	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2740	((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) \|\| \
AnnaBridge	172:65be27845400	2741	((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2742	#else
AnnaBridge	172:65be27845400	2743	#define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2744	(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2745	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) \|\| \
AnnaBridge	172:65be27845400	2746	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2747	((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2748	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	2749
AnnaBridge	172:65be27845400	2750	#else
AnnaBridge	172:65be27845400	2751
AnnaBridge	172:65be27845400	2752	#define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2753	(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2754	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2755	((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2756
AnnaBridge	172:65be27845400	2757	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	2758
AnnaBridge	172:65be27845400	2759	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	2760
AnnaBridge	172:65be27845400	2761	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	2762	#define IS_RCC_SAI2CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2763	(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2764	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) \|\| \
AnnaBridge	172:65be27845400	2765	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2766	((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) \|\| \
AnnaBridge	172:65be27845400	2767	((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2768	#else
AnnaBridge	172:65be27845400	2769	#define IS_RCC_SAI2CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2770	(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2771	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) \|\| \
AnnaBridge	172:65be27845400	2772	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2773	((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2774	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	2775
AnnaBridge	172:65be27845400	2776	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	2777
AnnaBridge	172:65be27845400	2778	#define IS_RCC_LPTIM1CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2779	(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2780	((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	2781	((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2782	((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
AnnaBridge	172:65be27845400	2783
AnnaBridge	172:65be27845400	2784	#define IS_RCC_LPTIM2CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2785	(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2786	((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	2787	((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2788	((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
AnnaBridge	172:65be27845400	2789
AnnaBridge	172:65be27845400	2790	#if defined(SDMMC1)
AnnaBridge	172:65be27845400	2791	#if defined(RCC_HSI48_SUPPORT) && defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	172:65be27845400	2792
AnnaBridge	172:65be27845400	2793	#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2794	(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \|\| \
AnnaBridge	172:65be27845400	2795	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) \|\| \
AnnaBridge	172:65be27845400	2796	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2797	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2798	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2799
AnnaBridge	172:65be27845400	2800	#elif defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	2801
AnnaBridge	172:65be27845400	2802	#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2803	(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) \|\| \
AnnaBridge	172:65be27845400	2804	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2805	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2806	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2807	#else
AnnaBridge	172:65be27845400	2808
AnnaBridge	172:65be27845400	2809	#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2810	(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	2811	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2812	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2813	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2814
AnnaBridge	172:65be27845400	2815	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	2816	#endif /* SDMMC1 */
AnnaBridge	172:65be27845400	2817
AnnaBridge	172:65be27845400	2818	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	2819
AnnaBridge	172:65be27845400	2820	#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2821	(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) \|\| \
AnnaBridge	172:65be27845400	2822	((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2823	((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2824	((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2825
AnnaBridge	172:65be27845400	2826	#else
AnnaBridge	172:65be27845400	2827
AnnaBridge	172:65be27845400	2828	#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2829	(((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	2830	((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2831	((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2832	((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2833
AnnaBridge	172:65be27845400	2834	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	2835
AnnaBridge	172:65be27845400	2836	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	172:65be27845400	2837	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	172:65be27845400	2838
AnnaBridge	172:65be27845400	2839	#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2840	(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
AnnaBridge	172:65be27845400	2841	((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2842	((__SOURCE__) == RCC_USBCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2843	((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2844
AnnaBridge	172:65be27845400	2845	#else
AnnaBridge	172:65be27845400	2846
AnnaBridge	172:65be27845400	2847	#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2848	(((__SOURCE__) == RCC_USBCLKSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	2849	((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2850	((__SOURCE__) == RCC_USBCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2851	((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2852
AnnaBridge	172:65be27845400	2853	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	172:65be27845400	2854	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	172:65be27845400	2855
AnnaBridge	172:65be27845400	2856	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx) \|\| defined(STM32L496xx) \|\| defined(STM32L4A6xx)
AnnaBridge	172:65be27845400	2857
AnnaBridge	172:65be27845400	2858	#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2859	(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	2860	((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2861	((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) \|\| \
AnnaBridge	172:65be27845400	2862	((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
AnnaBridge	172:65be27845400	2863
AnnaBridge	172:65be27845400	2864	#else
AnnaBridge	172:65be27845400	2865
AnnaBridge	172:65be27845400	2866	#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2867	(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	2868	((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) \|\| \
AnnaBridge	172:65be27845400	2869	((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
AnnaBridge	172:65be27845400	2870
AnnaBridge	172:65be27845400	2871	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx \|\| STM32L496xx \|\| STM32L4A6xx */
AnnaBridge	172:65be27845400	2872
AnnaBridge	172:65be27845400	2873	#if defined(SWPMI1)
AnnaBridge	172:65be27845400	2874
AnnaBridge	172:65be27845400	2875	#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2876	(((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	172:65be27845400	2877	((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2878
AnnaBridge	172:65be27845400	2879	#endif /* SWPMI1 */
AnnaBridge	172:65be27845400	2880
AnnaBridge	172:65be27845400	2881	#if defined(DFSDM1_Filter0)
AnnaBridge	172:65be27845400	2882
AnnaBridge	172:65be27845400	2883	#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2884	(((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) \|\| \
AnnaBridge	172:65be27845400	2885	((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
AnnaBridge	172:65be27845400	2886
AnnaBridge	172:65be27845400	2887	#if defined(STM32L4R5xx) \|\| defined(STM32L4R7xx) \|\| defined(STM32L4R9xx) \|\| defined(STM32L4S5xx) \|\| defined(STM32L4S7xx) \|\| defined(STM32L4S9xx)
AnnaBridge	172:65be27845400	2888
AnnaBridge	172:65be27845400	2889	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2890	(((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) \|\| \
AnnaBridge	172:65be27845400	2891	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2892	((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI))
AnnaBridge	172:65be27845400	2893
AnnaBridge	172:65be27845400	2894	#endif /* STM32L4R5xx \|\| STM32L4R7xx \|\| STM32L4R9xx \|\| STM32L4S5xx \|\| STM32L4S7xx \|\| STM32L4S9xx */
AnnaBridge	172:65be27845400	2895
AnnaBridge	172:65be27845400	2896	#endif /* DFSDM1_Filter0 */
AnnaBridge	172:65be27845400	2897
AnnaBridge	172:65be27845400	2898	#if defined(LTDC)
AnnaBridge	172:65be27845400	2899
AnnaBridge	172:65be27845400	2900	#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2901	(((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV2) \|\| \
AnnaBridge	172:65be27845400	2902	((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV4) \|\| \
AnnaBridge	172:65be27845400	2903	((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV8) \|\| \
AnnaBridge	172:65be27845400	2904	((__SOURCE__) == RCC_LTDCCLKSOURCE_PLLSAI2_DIV16))
AnnaBridge	172:65be27845400	2905
AnnaBridge	172:65be27845400	2906	#endif /* LTDC */
AnnaBridge	172:65be27845400	2907
AnnaBridge	172:65be27845400	2908	#if defined(DSI)
AnnaBridge	172:65be27845400	2909
AnnaBridge	172:65be27845400	2910	#define IS_RCC_DSICLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2911	(((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY) \|\| \
AnnaBridge	172:65be27845400	2912	((__SOURCE__) == RCC_DSICLKSOURCE_PLLSAI2))
AnnaBridge	172:65be27845400	2913
AnnaBridge	172:65be27845400	2914	#endif /* DSI */
AnnaBridge	172:65be27845400	2915
AnnaBridge	172:65be27845400	2916	#if defined(OCTOSPI1) \|\| defined(OCTOSPI2)
AnnaBridge	172:65be27845400	2917
AnnaBridge	172:65be27845400	2918	#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
AnnaBridge	172:65be27845400	2919	(((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) \|\| \
AnnaBridge	172:65be27845400	2920	((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) \|\| \
AnnaBridge	172:65be27845400	2921	((__SOURCE__) == RCC_OSPICLKSOURCE_PLL))
AnnaBridge	172:65be27845400	2922
AnnaBridge	172:65be27845400	2923	#endif /* OCTOSPI1 \|\| OCTOSPI2 */
AnnaBridge	172:65be27845400	2924
AnnaBridge	172:65be27845400	2925	#define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
AnnaBridge	172:65be27845400	2926
AnnaBridge	172:65be27845400	2927	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	2928	#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
AnnaBridge	172:65be27845400	2929	#else
AnnaBridge	172:65be27845400	2930	#define IS_RCC_PLLSAI1M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge	172:65be27845400	2931	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	172:65be27845400	2932
AnnaBridge	172:65be27845400	2933	#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge	172:65be27845400	2934
AnnaBridge	172:65be27845400	2935	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	2936	#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge	172:65be27845400	2937	#else
AnnaBridge	172:65be27845400	2938	#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
AnnaBridge	172:65be27845400	2939	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	2940
AnnaBridge	172:65be27845400	2941	#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	172:65be27845400	2942	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	172:65be27845400	2943
AnnaBridge	172:65be27845400	2944	#define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	172:65be27845400	2945	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	172:65be27845400	2946
AnnaBridge	172:65be27845400	2947	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	172:65be27845400	2948
AnnaBridge	172:65be27845400	2949	#define IS_RCC_PLLSAI2SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__)
AnnaBridge	172:65be27845400	2950
AnnaBridge	172:65be27845400	2951	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	172:65be27845400	2952	#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
AnnaBridge	172:65be27845400	2953	#else
AnnaBridge	172:65be27845400	2954	#define IS_RCC_PLLSAI2M_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U))
AnnaBridge	172:65be27845400	2955	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	172:65be27845400	2956
AnnaBridge	172:65be27845400	2957	#define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U))
AnnaBridge	172:65be27845400	2958
AnnaBridge	172:65be27845400	2959	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	172:65be27845400	2960	#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
AnnaBridge	172:65be27845400	2961	#else
AnnaBridge	172:65be27845400	2962	#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7U) \|\| ((__VALUE__) == 17U))
AnnaBridge	172:65be27845400	2963	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	172:65be27845400	2964
AnnaBridge	172:65be27845400	2965	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	172:65be27845400	2966	#define IS_RCC_PLLSAI2Q_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	172:65be27845400	2967	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	172:65be27845400	2968	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	172:65be27845400	2969
AnnaBridge	172:65be27845400	2970	#define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2U) \|\| ((__VALUE__) == 4U) \|\| \
AnnaBridge	172:65be27845400	2971	((__VALUE__) == 6U) \|\| ((__VALUE__) == 8U))
AnnaBridge	172:65be27845400	2972
AnnaBridge	172:65be27845400	2973	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	172:65be27845400	2974
AnnaBridge	172:65be27845400	2975	#if defined(CRS)
AnnaBridge	172:65be27845400	2976
AnnaBridge	172:65be27845400	2977	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
AnnaBridge	172:65be27845400	2978	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2979	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
AnnaBridge	172:65be27845400	2980
AnnaBridge	172:65be27845400	2981	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\| \
AnnaBridge	172:65be27845400	2982	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
AnnaBridge	172:65be27845400	2983	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
AnnaBridge	172:65be27845400	2984	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
AnnaBridge	172:65be27845400	2985
AnnaBridge	172:65be27845400	2986	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
AnnaBridge	172:65be27845400	2987	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge	172:65be27845400	2988
AnnaBridge	172:65be27845400	2989	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
AnnaBridge	172:65be27845400	2990
AnnaBridge	172:65be27845400	2991	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
AnnaBridge	172:65be27845400	2992
AnnaBridge	172:65be27845400	2993	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
AnnaBridge	172:65be27845400	2994
AnnaBridge	172:65be27845400	2995	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
AnnaBridge	172:65be27845400	2996	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge	172:65be27845400	2997
AnnaBridge	172:65be27845400	2998	#endif /* CRS */
AnnaBridge	172:65be27845400	2999
AnnaBridge	172:65be27845400	3000	/**
AnnaBridge	172:65be27845400	3001	* @}
AnnaBridge	172:65be27845400	3002	*/
AnnaBridge	172:65be27845400	3003
AnnaBridge	172:65be27845400	3004	/**
AnnaBridge	172:65be27845400	3005	* @}
AnnaBridge	172:65be27845400	3006	*/
AnnaBridge	172:65be27845400	3007
AnnaBridge	172:65be27845400	3008	/**
AnnaBridge	172:65be27845400	3009	* @}
AnnaBridge	172:65be27845400	3010	*/
AnnaBridge	172:65be27845400	3011
AnnaBridge	172:65be27845400	3012	#ifdef __cplusplus
AnnaBridge	172:65be27845400	3013	}
AnnaBridge	172:65be27845400	3014	#endif
AnnaBridge	172:65be27845400	3015
AnnaBridge	172:65be27845400	3016	#endif /* __STM32L4xx_HAL_RCC_EX_H */
AnnaBridge	172:65be27845400	3017
AnnaBridge	172:65be27845400	3018	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/