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TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal_nor.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_hal_nor.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of NOR HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 12 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 14 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 17 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 19 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 20 * without specific prior written permission.
AnnaBridge 172:65be27845400 21 *
AnnaBridge 172:65be27845400 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 32 *
AnnaBridge 172:65be27845400 33 ******************************************************************************
AnnaBridge 172:65be27845400 34 */
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 37 #ifndef __STM32L4xx_HAL_NOR_H
AnnaBridge 172:65be27845400 38 #define __STM32L4xx_HAL_NOR_H
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 #ifdef __cplusplus
AnnaBridge 172:65be27845400 41 extern "C" {
AnnaBridge 172:65be27845400 42 #endif
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 172:65be27845400 45 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 172:65be27845400 46 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 47
AnnaBridge 172:65be27845400 48 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 49 #include "stm32l4xx_ll_fmc.h"
AnnaBridge 172:65be27845400 50
AnnaBridge 172:65be27845400 51
AnnaBridge 172:65be27845400 52 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 172:65be27845400 53 * @{
AnnaBridge 172:65be27845400 54 */
AnnaBridge 172:65be27845400 55
AnnaBridge 172:65be27845400 56 /** @addtogroup NOR
AnnaBridge 172:65be27845400 57 * @{
AnnaBridge 172:65be27845400 58 */
AnnaBridge 172:65be27845400 59
AnnaBridge 172:65be27845400 60 /** @addtogroup NOR_Private_Constants
AnnaBridge 172:65be27845400 61 * @{
AnnaBridge 172:65be27845400 62 */
AnnaBridge 172:65be27845400 63
AnnaBridge 172:65be27845400 64 /* NOR device IDs addresses */
AnnaBridge 172:65be27845400 65 #define MC_ADDRESS ((uint16_t)0x0000)
AnnaBridge 172:65be27845400 66 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
AnnaBridge 172:65be27845400 67 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
AnnaBridge 172:65be27845400 68 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
AnnaBridge 172:65be27845400 69
AnnaBridge 172:65be27845400 70 /* NOR CFI IDs addresses */
AnnaBridge 172:65be27845400 71 #define CFI1_ADDRESS ((uint16_t)0x10)
AnnaBridge 172:65be27845400 72 #define CFI2_ADDRESS ((uint16_t)0x11)
AnnaBridge 172:65be27845400 73 #define CFI3_ADDRESS ((uint16_t)0x12)
AnnaBridge 172:65be27845400 74 #define CFI4_ADDRESS ((uint16_t)0x13)
AnnaBridge 172:65be27845400 75
AnnaBridge 172:65be27845400 76 /* NOR memory data width */
AnnaBridge 172:65be27845400 77 #define NOR_MEMORY_8B ((uint8_t)0x0)
AnnaBridge 172:65be27845400 78 #define NOR_MEMORY_16B ((uint8_t)0x1)
AnnaBridge 172:65be27845400 79
AnnaBridge 172:65be27845400 80 /* NOR memory device read/write start address */
AnnaBridge 172:65be27845400 81 #define NOR_MEMORY_ADRESS1 FMC_BANK1_1
AnnaBridge 172:65be27845400 82 #define NOR_MEMORY_ADRESS2 FMC_BANK1_2
AnnaBridge 172:65be27845400 83 #define NOR_MEMORY_ADRESS3 FMC_BANK1_3
AnnaBridge 172:65be27845400 84 #define NOR_MEMORY_ADRESS4 FMC_BANK1_4
AnnaBridge 172:65be27845400 85
AnnaBridge 172:65be27845400 86 /**
AnnaBridge 172:65be27845400 87 * @}
AnnaBridge 172:65be27845400 88 */
AnnaBridge 172:65be27845400 89
AnnaBridge 172:65be27845400 90 /** @addtogroup NOR_Private_Macros
AnnaBridge 172:65be27845400 91 * @{
AnnaBridge 172:65be27845400 92 */
AnnaBridge 172:65be27845400 93
AnnaBridge 172:65be27845400 94 /**
AnnaBridge 172:65be27845400 95 * @brief NOR memory address shifting.
AnnaBridge 172:65be27845400 96 * @param __NOR_ADDRESS: NOR base address
AnnaBridge 172:65be27845400 97 * @param __NOR_MEMORY_WIDTH_: NOR memory width
AnnaBridge 172:65be27845400 98 * @param __ADDRESS__: NOR memory address
AnnaBridge 172:65be27845400 99 * @retval NOR shifted address value
AnnaBridge 172:65be27845400 100 */
AnnaBridge 172:65be27845400 101 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
AnnaBridge 172:65be27845400 102 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
AnnaBridge 172:65be27845400 103 ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
AnnaBridge 172:65be27845400 104 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
AnnaBridge 172:65be27845400 105
AnnaBridge 172:65be27845400 106 /**
AnnaBridge 172:65be27845400 107 * @brief NOR memory write data to specified address.
AnnaBridge 172:65be27845400 108 * @param __ADDRESS__: NOR memory address
AnnaBridge 172:65be27845400 109 * @param __DATA__: Data to write
AnnaBridge 172:65be27845400 110 * @retval None
AnnaBridge 172:65be27845400 111 */
AnnaBridge 172:65be27845400 112 #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
AnnaBridge 172:65be27845400 113
AnnaBridge 172:65be27845400 114 /**
AnnaBridge 172:65be27845400 115 * @}
AnnaBridge 172:65be27845400 116 */
AnnaBridge 172:65be27845400 117
AnnaBridge 172:65be27845400 118 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 172:65be27845400 119 /** @defgroup NOR_Exported_Types NOR Exported Types
AnnaBridge 172:65be27845400 120 * @{
AnnaBridge 172:65be27845400 121 */
AnnaBridge 172:65be27845400 122
AnnaBridge 172:65be27845400 123 /**
AnnaBridge 172:65be27845400 124 * @brief HAL SRAM State structures definition
AnnaBridge 172:65be27845400 125 */
AnnaBridge 172:65be27845400 126 typedef enum
AnnaBridge 172:65be27845400 127 {
AnnaBridge 172:65be27845400 128 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
AnnaBridge 172:65be27845400 129 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
AnnaBridge 172:65be27845400 130 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
AnnaBridge 172:65be27845400 131 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
AnnaBridge 172:65be27845400 132 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
AnnaBridge 172:65be27845400 133 }HAL_NOR_StateTypeDef;
AnnaBridge 172:65be27845400 134
AnnaBridge 172:65be27845400 135 /**
AnnaBridge 172:65be27845400 136 * @brief FMC NOR Status typedef
AnnaBridge 172:65be27845400 137 */
AnnaBridge 172:65be27845400 138 typedef enum
AnnaBridge 172:65be27845400 139 {
AnnaBridge 172:65be27845400 140 HAL_NOR_STATUS_SUCCESS = 0,
AnnaBridge 172:65be27845400 141 HAL_NOR_STATUS_ONGOING,
AnnaBridge 172:65be27845400 142 HAL_NOR_STATUS_ERROR,
AnnaBridge 172:65be27845400 143 HAL_NOR_STATUS_TIMEOUT
AnnaBridge 172:65be27845400 144 }HAL_NOR_StatusTypeDef;
AnnaBridge 172:65be27845400 145
AnnaBridge 172:65be27845400 146 /**
AnnaBridge 172:65be27845400 147 * @brief FMC NOR ID typedef
AnnaBridge 172:65be27845400 148 */
AnnaBridge 172:65be27845400 149 typedef struct
AnnaBridge 172:65be27845400 150 {
AnnaBridge 172:65be27845400 151 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
AnnaBridge 172:65be27845400 152
AnnaBridge 172:65be27845400 153 uint16_t Device_Code1;
AnnaBridge 172:65be27845400 154
AnnaBridge 172:65be27845400 155 uint16_t Device_Code2;
AnnaBridge 172:65be27845400 156
AnnaBridge 172:65be27845400 157 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
AnnaBridge 172:65be27845400 158 These codes can be accessed by performing read operations with specific
AnnaBridge 172:65be27845400 159 control signals and addresses set.They can also be accessed by issuing
AnnaBridge 172:65be27845400 160 an Auto Select command. */
AnnaBridge 172:65be27845400 161 }NOR_IDTypeDef;
AnnaBridge 172:65be27845400 162
AnnaBridge 172:65be27845400 163 /**
AnnaBridge 172:65be27845400 164 * @brief FMC NOR CFI typedef
AnnaBridge 172:65be27845400 165 */
AnnaBridge 172:65be27845400 166 typedef struct
AnnaBridge 172:65be27845400 167 {
AnnaBridge 172:65be27845400 168 uint16_t CFI_1;
AnnaBridge 172:65be27845400 169
AnnaBridge 172:65be27845400 170 uint16_t CFI_2;
AnnaBridge 172:65be27845400 171
AnnaBridge 172:65be27845400 172 uint16_t CFI_3;
AnnaBridge 172:65be27845400 173
AnnaBridge 172:65be27845400 174 uint16_t CFI_4; /*!< Defines the information stored in the memory's Common flash interface
AnnaBridge 172:65be27845400 175 which contains a description of various electrical and timing parameters,
AnnaBridge 172:65be27845400 176 density information and functions supported by the memory. */
AnnaBridge 172:65be27845400 177 }NOR_CFITypeDef;
AnnaBridge 172:65be27845400 178
AnnaBridge 172:65be27845400 179 /**
AnnaBridge 172:65be27845400 180 * @brief NOR handle Structure definition
AnnaBridge 172:65be27845400 181 */
AnnaBridge 172:65be27845400 182 typedef struct
AnnaBridge 172:65be27845400 183 {
AnnaBridge 172:65be27845400 184 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
AnnaBridge 172:65be27845400 185
AnnaBridge 172:65be27845400 186 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
AnnaBridge 172:65be27845400 187
AnnaBridge 172:65be27845400 188 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
AnnaBridge 172:65be27845400 189
AnnaBridge 172:65be27845400 190 HAL_LockTypeDef Lock; /*!< NOR locking object */
AnnaBridge 172:65be27845400 191
AnnaBridge 172:65be27845400 192 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
AnnaBridge 172:65be27845400 193
AnnaBridge 172:65be27845400 194 }NOR_HandleTypeDef;
AnnaBridge 172:65be27845400 195
AnnaBridge 172:65be27845400 196 /**
AnnaBridge 172:65be27845400 197 * @}
AnnaBridge 172:65be27845400 198 */
AnnaBridge 172:65be27845400 199
AnnaBridge 172:65be27845400 200 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 201 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 202 /** @defgroup NOR_Exported_Macros NOR Exported Macros
AnnaBridge 172:65be27845400 203 * @{
AnnaBridge 172:65be27845400 204 */
AnnaBridge 172:65be27845400 205
AnnaBridge 172:65be27845400 206 /** @brief Reset NOR handle state.
AnnaBridge 172:65be27845400 207 * @param __HANDLE__: NOR handle
AnnaBridge 172:65be27845400 208 * @retval None
AnnaBridge 172:65be27845400 209 */
AnnaBridge 172:65be27845400 210 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
AnnaBridge 172:65be27845400 211
AnnaBridge 172:65be27845400 212 /**
AnnaBridge 172:65be27845400 213 * @}
AnnaBridge 172:65be27845400 214 */
AnnaBridge 172:65be27845400 215
AnnaBridge 172:65be27845400 216 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 217 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
AnnaBridge 172:65be27845400 218 * @{
AnnaBridge 172:65be27845400 219 */
AnnaBridge 172:65be27845400 220
AnnaBridge 172:65be27845400 221 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 172:65be27845400 222 * @{
AnnaBridge 172:65be27845400 223 */
AnnaBridge 172:65be27845400 224
AnnaBridge 172:65be27845400 225 /* Initialization/de-initialization functions ********************************/
AnnaBridge 172:65be27845400 226 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
AnnaBridge 172:65be27845400 227 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 228 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 229 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 230 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
AnnaBridge 172:65be27845400 231
AnnaBridge 172:65be27845400 232 /**
AnnaBridge 172:65be27845400 233 * @}
AnnaBridge 172:65be27845400 234 */
AnnaBridge 172:65be27845400 235
AnnaBridge 172:65be27845400 236 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
AnnaBridge 172:65be27845400 237 * @{
AnnaBridge 172:65be27845400 238 */
AnnaBridge 172:65be27845400 239
AnnaBridge 172:65be27845400 240 /* I/O operation functions ***************************************************/
AnnaBridge 172:65be27845400 241 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
AnnaBridge 172:65be27845400 242 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 243 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
AnnaBridge 172:65be27845400 244 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
AnnaBridge 172:65be27845400 245
AnnaBridge 172:65be27845400 246 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
AnnaBridge 172:65be27845400 247 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
AnnaBridge 172:65be27845400 248
AnnaBridge 172:65be27845400 249 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
AnnaBridge 172:65be27845400 250 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
AnnaBridge 172:65be27845400 251 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
AnnaBridge 172:65be27845400 252
AnnaBridge 172:65be27845400 253 /**
AnnaBridge 172:65be27845400 254 * @}
AnnaBridge 172:65be27845400 255 */
AnnaBridge 172:65be27845400 256
AnnaBridge 172:65be27845400 257 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge 172:65be27845400 258 * @{
AnnaBridge 172:65be27845400 259 */
AnnaBridge 172:65be27845400 260
AnnaBridge 172:65be27845400 261 /* NOR Control functions *****************************************************/
AnnaBridge 172:65be27845400 262 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 263 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 264
AnnaBridge 172:65be27845400 265 /**
AnnaBridge 172:65be27845400 266 * @}
AnnaBridge 172:65be27845400 267 */
AnnaBridge 172:65be27845400 268
AnnaBridge 172:65be27845400 269 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 172:65be27845400 270 * @{
AnnaBridge 172:65be27845400 271 */
AnnaBridge 172:65be27845400 272
AnnaBridge 172:65be27845400 273 /* NOR State functions ********************************************************/
AnnaBridge 172:65be27845400 274 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
AnnaBridge 172:65be27845400 275 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
AnnaBridge 172:65be27845400 276
AnnaBridge 172:65be27845400 277 /**
AnnaBridge 172:65be27845400 278 * @}
AnnaBridge 172:65be27845400 279 */
AnnaBridge 172:65be27845400 280
AnnaBridge 172:65be27845400 281 /**
AnnaBridge 172:65be27845400 282 * @}
AnnaBridge 172:65be27845400 283 */
AnnaBridge 172:65be27845400 284
AnnaBridge 172:65be27845400 285 /**
AnnaBridge 172:65be27845400 286 * @}
AnnaBridge 172:65be27845400 287 */
AnnaBridge 172:65be27845400 288
AnnaBridge 172:65be27845400 289 /**
AnnaBridge 172:65be27845400 290 * @}
AnnaBridge 172:65be27845400 291 */
AnnaBridge 172:65be27845400 292
AnnaBridge 172:65be27845400 293 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
AnnaBridge 172:65be27845400 294 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 172:65be27845400 295 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 296
AnnaBridge 172:65be27845400 297 #ifdef __cplusplus
AnnaBridge 172:65be27845400 298 }
AnnaBridge 172:65be27845400 299 #endif
AnnaBridge 172:65be27845400 300
AnnaBridge 172:65be27845400 301 #endif /* __STM32L4xx_HAL_NOR_H */
AnnaBridge 172:65be27845400 302
AnnaBridge 172:65be27845400 303 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/