mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_L4R5ZI_P/TOOLCHAIN_ARM_STD/stm32l4xx_hal_dfsdm.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32l4xx_hal_dfsdm.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of DFSDM HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 172:65be27845400 10 *
AnnaBridge 172:65be27845400 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 172:65be27845400 12 * are permitted provided that the following conditions are met:
AnnaBridge 172:65be27845400 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 172:65be27845400 14 * this list of conditions and the following disclaimer.
AnnaBridge 172:65be27845400 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 172:65be27845400 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 172:65be27845400 17 * and/or other materials provided with the distribution.
AnnaBridge 172:65be27845400 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 172:65be27845400 19 * may be used to endorse or promote products derived from this software
AnnaBridge 172:65be27845400 20 * without specific prior written permission.
AnnaBridge 172:65be27845400 21 *
AnnaBridge 172:65be27845400 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 172:65be27845400 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 172:65be27845400 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 172:65be27845400 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 172:65be27845400 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 172:65be27845400 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 172:65be27845400 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 172:65be27845400 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 172:65be27845400 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 172:65be27845400 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 172:65be27845400 32 *
AnnaBridge 172:65be27845400 33 ******************************************************************************
AnnaBridge 172:65be27845400 34 */
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 37 #ifndef __STM32L4xx_HAL_DFSDM_H
AnnaBridge 172:65be27845400 38 #define __STM32L4xx_HAL_DFSDM_H
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 #ifdef __cplusplus
AnnaBridge 172:65be27845400 41 extern "C" {
AnnaBridge 172:65be27845400 42 #endif
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 172:65be27845400 45 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \
AnnaBridge 172:65be27845400 46 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 172:65be27845400 47 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 48
AnnaBridge 172:65be27845400 49 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 50 #include "stm32l4xx_hal_def.h"
AnnaBridge 172:65be27845400 51
AnnaBridge 172:65be27845400 52 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 172:65be27845400 53 * @{
AnnaBridge 172:65be27845400 54 */
AnnaBridge 172:65be27845400 55
AnnaBridge 172:65be27845400 56 /** @addtogroup DFSDM
AnnaBridge 172:65be27845400 57 * @{
AnnaBridge 172:65be27845400 58 */
AnnaBridge 172:65be27845400 59
AnnaBridge 172:65be27845400 60 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 61 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types
AnnaBridge 172:65be27845400 62 * @{
AnnaBridge 172:65be27845400 63 */
AnnaBridge 172:65be27845400 64
AnnaBridge 172:65be27845400 65 /**
AnnaBridge 172:65be27845400 66 * @brief HAL DFSDM Channel states definition
AnnaBridge 172:65be27845400 67 */
AnnaBridge 172:65be27845400 68 typedef enum
AnnaBridge 172:65be27845400 69 {
AnnaBridge 172:65be27845400 70 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
AnnaBridge 172:65be27845400 71 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
AnnaBridge 172:65be27845400 72 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
AnnaBridge 172:65be27845400 73 }HAL_DFSDM_Channel_StateTypeDef;
AnnaBridge 172:65be27845400 74
AnnaBridge 172:65be27845400 75 /**
AnnaBridge 172:65be27845400 76 * @brief DFSDM channel output clock structure definition
AnnaBridge 172:65be27845400 77 */
AnnaBridge 172:65be27845400 78 typedef struct
AnnaBridge 172:65be27845400 79 {
AnnaBridge 172:65be27845400 80 FunctionalState Activation; /*!< Output clock enable/disable */
AnnaBridge 172:65be27845400 81 uint32_t Selection; /*!< Output clock is system clock or audio clock.
AnnaBridge 172:65be27845400 82 This parameter can be a value of @ref DFSDM_Channel_OuputClock */
AnnaBridge 172:65be27845400 83 uint32_t Divider; /*!< Output clock divider.
AnnaBridge 172:65be27845400 84 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
AnnaBridge 172:65be27845400 85 }DFSDM_Channel_OutputClockTypeDef;
AnnaBridge 172:65be27845400 86
AnnaBridge 172:65be27845400 87 /**
AnnaBridge 172:65be27845400 88 * @brief DFSDM channel input structure definition
AnnaBridge 172:65be27845400 89 */
AnnaBridge 172:65be27845400 90 typedef struct
AnnaBridge 172:65be27845400 91 {
AnnaBridge 172:65be27845400 92 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
AnnaBridge 172:65be27845400 93 ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx,
AnnaBridge 172:65be27845400 94 STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx,
AnnaBridge 172:65be27845400 95 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products.
AnnaBridge 172:65be27845400 96 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
AnnaBridge 172:65be27845400 97 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
AnnaBridge 172:65be27845400 98 This parameter can be a value of @ref DFSDM_Channel_DataPacking */
AnnaBridge 172:65be27845400 99 uint32_t Pins; /*!< Input pins are taken from same or following channel.
AnnaBridge 172:65be27845400 100 This parameter can be a value of @ref DFSDM_Channel_InputPins */
AnnaBridge 172:65be27845400 101 }DFSDM_Channel_InputTypeDef;
AnnaBridge 172:65be27845400 102
AnnaBridge 172:65be27845400 103 /**
AnnaBridge 172:65be27845400 104 * @brief DFSDM channel serial interface structure definition
AnnaBridge 172:65be27845400 105 */
AnnaBridge 172:65be27845400 106 typedef struct
AnnaBridge 172:65be27845400 107 {
AnnaBridge 172:65be27845400 108 uint32_t Type; /*!< SPI or Manchester modes.
AnnaBridge 172:65be27845400 109 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
AnnaBridge 172:65be27845400 110 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
AnnaBridge 172:65be27845400 111 This parameter can be a value of @ref DFSDM_Channel_SpiClock */
AnnaBridge 172:65be27845400 112 }DFSDM_Channel_SerialInterfaceTypeDef;
AnnaBridge 172:65be27845400 113
AnnaBridge 172:65be27845400 114 /**
AnnaBridge 172:65be27845400 115 * @brief DFSDM channel analog watchdog structure definition
AnnaBridge 172:65be27845400 116 */
AnnaBridge 172:65be27845400 117 typedef struct
AnnaBridge 172:65be27845400 118 {
AnnaBridge 172:65be27845400 119 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
AnnaBridge 172:65be27845400 120 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
AnnaBridge 172:65be27845400 121 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
AnnaBridge 172:65be27845400 122 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
AnnaBridge 172:65be27845400 123 }DFSDM_Channel_AwdTypeDef;
AnnaBridge 172:65be27845400 124
AnnaBridge 172:65be27845400 125 /**
AnnaBridge 172:65be27845400 126 * @brief DFSDM channel init structure definition
AnnaBridge 172:65be27845400 127 */
AnnaBridge 172:65be27845400 128 typedef struct
AnnaBridge 172:65be27845400 129 {
AnnaBridge 172:65be27845400 130 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
AnnaBridge 172:65be27845400 131 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
AnnaBridge 172:65be27845400 132 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
AnnaBridge 172:65be27845400 133 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
AnnaBridge 172:65be27845400 134 int32_t Offset; /*!< DFSDM channel offset.
AnnaBridge 172:65be27845400 135 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
AnnaBridge 172:65be27845400 136 uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
AnnaBridge 172:65be27845400 137 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge 172:65be27845400 138 }DFSDM_Channel_InitTypeDef;
AnnaBridge 172:65be27845400 139
AnnaBridge 172:65be27845400 140 /**
AnnaBridge 172:65be27845400 141 * @brief DFSDM channel handle structure definition
AnnaBridge 172:65be27845400 142 */
AnnaBridge 172:65be27845400 143 typedef struct
AnnaBridge 172:65be27845400 144 {
AnnaBridge 172:65be27845400 145 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
AnnaBridge 172:65be27845400 146 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
AnnaBridge 172:65be27845400 147 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
AnnaBridge 172:65be27845400 148 }DFSDM_Channel_HandleTypeDef;
AnnaBridge 172:65be27845400 149
AnnaBridge 172:65be27845400 150 /**
AnnaBridge 172:65be27845400 151 * @brief HAL DFSDM Filter states definition
AnnaBridge 172:65be27845400 152 */
AnnaBridge 172:65be27845400 153 typedef enum
AnnaBridge 172:65be27845400 154 {
AnnaBridge 172:65be27845400 155 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
AnnaBridge 172:65be27845400 156 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
AnnaBridge 172:65be27845400 157 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
AnnaBridge 172:65be27845400 158 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
AnnaBridge 172:65be27845400 159 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
AnnaBridge 172:65be27845400 160 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
AnnaBridge 172:65be27845400 161 }HAL_DFSDM_Filter_StateTypeDef;
AnnaBridge 172:65be27845400 162
AnnaBridge 172:65be27845400 163 /**
AnnaBridge 172:65be27845400 164 * @brief DFSDM filter regular conversion parameters structure definition
AnnaBridge 172:65be27845400 165 */
AnnaBridge 172:65be27845400 166 typedef struct
AnnaBridge 172:65be27845400 167 {
AnnaBridge 172:65be27845400 168 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
AnnaBridge 172:65be27845400 169 This parameter can be a value of @ref DFSDM_Filter_Trigger */
AnnaBridge 172:65be27845400 170 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
AnnaBridge 172:65be27845400 171 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
AnnaBridge 172:65be27845400 172 }DFSDM_Filter_RegularParamTypeDef;
AnnaBridge 172:65be27845400 173
AnnaBridge 172:65be27845400 174 /**
AnnaBridge 172:65be27845400 175 * @brief DFSDM filter injected conversion parameters structure definition
AnnaBridge 172:65be27845400 176 */
AnnaBridge 172:65be27845400 177 typedef struct
AnnaBridge 172:65be27845400 178 {
AnnaBridge 172:65be27845400 179 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
AnnaBridge 172:65be27845400 180 This parameter can be a value of @ref DFSDM_Filter_Trigger */
AnnaBridge 172:65be27845400 181 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
AnnaBridge 172:65be27845400 182 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
AnnaBridge 172:65be27845400 183 uint32_t ExtTrigger; /*!< External trigger.
AnnaBridge 172:65be27845400 184 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
AnnaBridge 172:65be27845400 185 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
AnnaBridge 172:65be27845400 186 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
AnnaBridge 172:65be27845400 187 }DFSDM_Filter_InjectedParamTypeDef;
AnnaBridge 172:65be27845400 188
AnnaBridge 172:65be27845400 189 /**
AnnaBridge 172:65be27845400 190 * @brief DFSDM filter parameters structure definition
AnnaBridge 172:65be27845400 191 */
AnnaBridge 172:65be27845400 192 typedef struct
AnnaBridge 172:65be27845400 193 {
AnnaBridge 172:65be27845400 194 uint32_t SincOrder; /*!< Sinc filter order.
AnnaBridge 172:65be27845400 195 This parameter can be a value of @ref DFSDM_Filter_SincOrder */
AnnaBridge 172:65be27845400 196 uint32_t Oversampling; /*!< Filter oversampling ratio.
AnnaBridge 172:65be27845400 197 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
AnnaBridge 172:65be27845400 198 uint32_t IntOversampling; /*!< Integrator oversampling ratio.
AnnaBridge 172:65be27845400 199 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
AnnaBridge 172:65be27845400 200 }DFSDM_Filter_FilterParamTypeDef;
AnnaBridge 172:65be27845400 201
AnnaBridge 172:65be27845400 202 /**
AnnaBridge 172:65be27845400 203 * @brief DFSDM filter init structure definition
AnnaBridge 172:65be27845400 204 */
AnnaBridge 172:65be27845400 205 typedef struct
AnnaBridge 172:65be27845400 206 {
AnnaBridge 172:65be27845400 207 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
AnnaBridge 172:65be27845400 208 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
AnnaBridge 172:65be27845400 209 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
AnnaBridge 172:65be27845400 210 }DFSDM_Filter_InitTypeDef;
AnnaBridge 172:65be27845400 211
AnnaBridge 172:65be27845400 212 /**
AnnaBridge 172:65be27845400 213 * @brief DFSDM filter handle structure definition
AnnaBridge 172:65be27845400 214 */
AnnaBridge 172:65be27845400 215 typedef struct
AnnaBridge 172:65be27845400 216 {
AnnaBridge 172:65be27845400 217 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
AnnaBridge 172:65be27845400 218 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
AnnaBridge 172:65be27845400 219 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
AnnaBridge 172:65be27845400 220 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
AnnaBridge 172:65be27845400 221 uint32_t RegularContMode; /*!< Regular conversion continuous mode */
AnnaBridge 172:65be27845400 222 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
AnnaBridge 172:65be27845400 223 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
AnnaBridge 172:65be27845400 224 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
AnnaBridge 172:65be27845400 225 FunctionalState InjectedScanMode; /*!< Injected scanning mode */
AnnaBridge 172:65be27845400 226 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
AnnaBridge 172:65be27845400 227 uint32_t InjConvRemaining; /*!< Injected conversions remaining */
AnnaBridge 172:65be27845400 228 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
AnnaBridge 172:65be27845400 229 uint32_t ErrorCode; /*!< DFSDM filter error code */
AnnaBridge 172:65be27845400 230 }DFSDM_Filter_HandleTypeDef;
AnnaBridge 172:65be27845400 231
AnnaBridge 172:65be27845400 232 /**
AnnaBridge 172:65be27845400 233 * @brief DFSDM filter analog watchdog parameters structure definition
AnnaBridge 172:65be27845400 234 */
AnnaBridge 172:65be27845400 235 typedef struct
AnnaBridge 172:65be27845400 236 {
AnnaBridge 172:65be27845400 237 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
AnnaBridge 172:65be27845400 238 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
AnnaBridge 172:65be27845400 239 uint32_t Channel; /*!< Analog watchdog channel selection.
AnnaBridge 172:65be27845400 240 This parameter can be a values combination of @ref DFSDM_Channel_Selection */
AnnaBridge 172:65be27845400 241 int32_t HighThreshold; /*!< High threshold for the analog watchdog.
AnnaBridge 172:65be27845400 242 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
AnnaBridge 172:65be27845400 243 int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
AnnaBridge 172:65be27845400 244 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
AnnaBridge 172:65be27845400 245 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
AnnaBridge 172:65be27845400 246 This parameter can be a values combination of @ref DFSDM_BreakSignals */
AnnaBridge 172:65be27845400 247 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
AnnaBridge 172:65be27845400 248 This parameter can be a values combination of @ref DFSDM_BreakSignals */
AnnaBridge 172:65be27845400 249 }DFSDM_Filter_AwdParamTypeDef;
AnnaBridge 172:65be27845400 250
AnnaBridge 172:65be27845400 251 /**
AnnaBridge 172:65be27845400 252 * @}
AnnaBridge 172:65be27845400 253 */
AnnaBridge 172:65be27845400 254 /* End of exported types -----------------------------------------------------*/
AnnaBridge 172:65be27845400 255
AnnaBridge 172:65be27845400 256 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 257 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
AnnaBridge 172:65be27845400 258 * @{
AnnaBridge 172:65be27845400 259 */
AnnaBridge 172:65be27845400 260
AnnaBridge 172:65be27845400 261 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
AnnaBridge 172:65be27845400 262 * @{
AnnaBridge 172:65be27845400 263 */
AnnaBridge 172:65be27845400 264 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
AnnaBridge 172:65be27845400 265 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
AnnaBridge 172:65be27845400 266 /**
AnnaBridge 172:65be27845400 267 * @}
AnnaBridge 172:65be27845400 268 */
AnnaBridge 172:65be27845400 269
AnnaBridge 172:65be27845400 270 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
AnnaBridge 172:65be27845400 271 * @{
AnnaBridge 172:65be27845400 272 */
AnnaBridge 172:65be27845400 273 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
AnnaBridge 172:65be27845400 274 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 172:65be27845400 275 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 172:65be27845400 276 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 277 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */
AnnaBridge 172:65be27845400 278 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 279 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
AnnaBridge 172:65be27845400 280 /**
AnnaBridge 172:65be27845400 281 * @}
AnnaBridge 172:65be27845400 282 */
AnnaBridge 172:65be27845400 283
AnnaBridge 172:65be27845400 284 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
AnnaBridge 172:65be27845400 285 * @{
AnnaBridge 172:65be27845400 286 */
AnnaBridge 172:65be27845400 287 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */
AnnaBridge 172:65be27845400 288 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
AnnaBridge 172:65be27845400 289 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
AnnaBridge 172:65be27845400 290 /**
AnnaBridge 172:65be27845400 291 * @}
AnnaBridge 172:65be27845400 292 */
AnnaBridge 172:65be27845400 293
AnnaBridge 172:65be27845400 294 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
AnnaBridge 172:65be27845400 295 * @{
AnnaBridge 172:65be27845400 296 */
AnnaBridge 172:65be27845400 297 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
AnnaBridge 172:65be27845400 298 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
AnnaBridge 172:65be27845400 299 /**
AnnaBridge 172:65be27845400 300 * @}
AnnaBridge 172:65be27845400 301 */
AnnaBridge 172:65be27845400 302
AnnaBridge 172:65be27845400 303 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
AnnaBridge 172:65be27845400 304 * @{
AnnaBridge 172:65be27845400 305 */
AnnaBridge 172:65be27845400 306 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */
AnnaBridge 172:65be27845400 307 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
AnnaBridge 172:65be27845400 308 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
AnnaBridge 172:65be27845400 309 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
AnnaBridge 172:65be27845400 310 /**
AnnaBridge 172:65be27845400 311 * @}
AnnaBridge 172:65be27845400 312 */
AnnaBridge 172:65be27845400 313
AnnaBridge 172:65be27845400 314 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
AnnaBridge 172:65be27845400 315 * @{
AnnaBridge 172:65be27845400 316 */
AnnaBridge 172:65be27845400 317 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */
AnnaBridge 172:65be27845400 318 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
AnnaBridge 172:65be27845400 319 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
AnnaBridge 172:65be27845400 320 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
AnnaBridge 172:65be27845400 321 /**
AnnaBridge 172:65be27845400 322 * @}
AnnaBridge 172:65be27845400 323 */
AnnaBridge 172:65be27845400 324
AnnaBridge 172:65be27845400 325 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
AnnaBridge 172:65be27845400 326 * @{
AnnaBridge 172:65be27845400 327 */
AnnaBridge 172:65be27845400 328 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
AnnaBridge 172:65be27845400 329 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
AnnaBridge 172:65be27845400 330 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
AnnaBridge 172:65be27845400 331 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
AnnaBridge 172:65be27845400 332 /**
AnnaBridge 172:65be27845400 333 * @}
AnnaBridge 172:65be27845400 334 */
AnnaBridge 172:65be27845400 335
AnnaBridge 172:65be27845400 336 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
AnnaBridge 172:65be27845400 337 * @{
AnnaBridge 172:65be27845400 338 */
AnnaBridge 172:65be27845400 339 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */
AnnaBridge 172:65be27845400 340 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
AnnaBridge 172:65be27845400 341 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
AnnaBridge 172:65be27845400 342 /**
AnnaBridge 172:65be27845400 343 * @}
AnnaBridge 172:65be27845400 344 */
AnnaBridge 172:65be27845400 345
AnnaBridge 172:65be27845400 346 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
AnnaBridge 172:65be27845400 347 * @{
AnnaBridge 172:65be27845400 348 */
AnnaBridge 172:65be27845400 349 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 172:65be27845400 350 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 351 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 352 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 353 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
AnnaBridge 172:65be27845400 354 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
AnnaBridge 172:65be27845400 355 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 356 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 357 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 358 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 359 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 360 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 361 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 362 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 363 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 364 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 365 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
AnnaBridge 172:65be27845400 366 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 367 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 368 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 369 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
AnnaBridge 172:65be27845400 370 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 371 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
AnnaBridge 172:65be27845400 372 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */
AnnaBridge 172:65be27845400 373 #else
AnnaBridge 172:65be27845400 374 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 375 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 376 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 377 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */
AnnaBridge 172:65be27845400 378 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */
AnnaBridge 172:65be27845400 379 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */
AnnaBridge 172:65be27845400 380 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */
AnnaBridge 172:65be27845400 381 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */
AnnaBridge 172:65be27845400 382 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */
AnnaBridge 172:65be27845400 383 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 384 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */
AnnaBridge 172:65be27845400 385 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
AnnaBridge 172:65be27845400 386 /**
AnnaBridge 172:65be27845400 387 * @}
AnnaBridge 172:65be27845400 388 */
AnnaBridge 172:65be27845400 389
AnnaBridge 172:65be27845400 390 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
AnnaBridge 172:65be27845400 391 * @{
AnnaBridge 172:65be27845400 392 */
AnnaBridge 172:65be27845400 393 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
AnnaBridge 172:65be27845400 394 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
AnnaBridge 172:65be27845400 395 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
AnnaBridge 172:65be27845400 396 /**
AnnaBridge 172:65be27845400 397 * @}
AnnaBridge 172:65be27845400 398 */
AnnaBridge 172:65be27845400 399
AnnaBridge 172:65be27845400 400 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
AnnaBridge 172:65be27845400 401 * @{
AnnaBridge 172:65be27845400 402 */
AnnaBridge 172:65be27845400 403 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
AnnaBridge 172:65be27845400 404 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
AnnaBridge 172:65be27845400 405 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
AnnaBridge 172:65be27845400 406 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
AnnaBridge 172:65be27845400 407 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
AnnaBridge 172:65be27845400 408 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
AnnaBridge 172:65be27845400 409 /**
AnnaBridge 172:65be27845400 410 * @}
AnnaBridge 172:65be27845400 411 */
AnnaBridge 172:65be27845400 412
AnnaBridge 172:65be27845400 413 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
AnnaBridge 172:65be27845400 414 * @{
AnnaBridge 172:65be27845400 415 */
AnnaBridge 172:65be27845400 416 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */
AnnaBridge 172:65be27845400 417 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
AnnaBridge 172:65be27845400 418 /**
AnnaBridge 172:65be27845400 419 * @}
AnnaBridge 172:65be27845400 420 */
AnnaBridge 172:65be27845400 421
AnnaBridge 172:65be27845400 422 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
AnnaBridge 172:65be27845400 423 * @{
AnnaBridge 172:65be27845400 424 */
AnnaBridge 172:65be27845400 425 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
AnnaBridge 172:65be27845400 426 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
AnnaBridge 172:65be27845400 427 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
AnnaBridge 172:65be27845400 428 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
AnnaBridge 172:65be27845400 429 /**
AnnaBridge 172:65be27845400 430 * @}
AnnaBridge 172:65be27845400 431 */
AnnaBridge 172:65be27845400 432
AnnaBridge 172:65be27845400 433 /** @defgroup DFSDM_BreakSignals DFSDM break signals
AnnaBridge 172:65be27845400 434 * @{
AnnaBridge 172:65be27845400 435 */
AnnaBridge 172:65be27845400 436 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
AnnaBridge 172:65be27845400 437 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */
AnnaBridge 172:65be27845400 438 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */
AnnaBridge 172:65be27845400 439 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */
AnnaBridge 172:65be27845400 440 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */
AnnaBridge 172:65be27845400 441 /**
AnnaBridge 172:65be27845400 442 * @}
AnnaBridge 172:65be27845400 443 */
AnnaBridge 172:65be27845400 444
AnnaBridge 172:65be27845400 445 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
AnnaBridge 172:65be27845400 446 * @{
AnnaBridge 172:65be27845400 447 */
AnnaBridge 172:65be27845400 448 /* DFSDM Channels ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 449 /* The DFSDM channels are defined as follows:
AnnaBridge 172:65be27845400 450 - in 16-bit LSB the channel mask is set
AnnaBridge 172:65be27845400 451 - in 16-bit MSB the channel number is set
AnnaBridge 172:65be27845400 452 e.g. for channel 5 definition:
AnnaBridge 172:65be27845400 453 - the channel mask is 0x00000020 (bit 5 is set)
AnnaBridge 172:65be27845400 454 - the channel number 5 is 0x00050000
AnnaBridge 172:65be27845400 455 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
AnnaBridge 172:65be27845400 456 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 172:65be27845400 457 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
AnnaBridge 172:65be27845400 458 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
AnnaBridge 172:65be27845400 459 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
AnnaBridge 172:65be27845400 460 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
AnnaBridge 172:65be27845400 461 #else
AnnaBridge 172:65be27845400 462 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
AnnaBridge 172:65be27845400 463 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
AnnaBridge 172:65be27845400 464 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
AnnaBridge 172:65be27845400 465 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
AnnaBridge 172:65be27845400 466 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
AnnaBridge 172:65be27845400 467 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
AnnaBridge 172:65be27845400 468 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
AnnaBridge 172:65be27845400 469 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
AnnaBridge 172:65be27845400 470 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
AnnaBridge 172:65be27845400 471 /**
AnnaBridge 172:65be27845400 472 * @}
AnnaBridge 172:65be27845400 473 */
AnnaBridge 172:65be27845400 474
AnnaBridge 172:65be27845400 475 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
AnnaBridge 172:65be27845400 476 * @{
AnnaBridge 172:65be27845400 477 */
AnnaBridge 172:65be27845400 478 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
AnnaBridge 172:65be27845400 479 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */
AnnaBridge 172:65be27845400 480 /**
AnnaBridge 172:65be27845400 481 * @}
AnnaBridge 172:65be27845400 482 */
AnnaBridge 172:65be27845400 483
AnnaBridge 172:65be27845400 484 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
AnnaBridge 172:65be27845400 485 * @{
AnnaBridge 172:65be27845400 486 */
AnnaBridge 172:65be27845400 487 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
AnnaBridge 172:65be27845400 488 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
AnnaBridge 172:65be27845400 489 /**
AnnaBridge 172:65be27845400 490 * @}
AnnaBridge 172:65be27845400 491 */
AnnaBridge 172:65be27845400 492
AnnaBridge 172:65be27845400 493 /**
AnnaBridge 172:65be27845400 494 * @}
AnnaBridge 172:65be27845400 495 */
AnnaBridge 172:65be27845400 496 /* End of exported constants -------------------------------------------------*/
AnnaBridge 172:65be27845400 497
AnnaBridge 172:65be27845400 498 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 172:65be27845400 499 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
AnnaBridge 172:65be27845400 500 * @{
AnnaBridge 172:65be27845400 501 */
AnnaBridge 172:65be27845400 502
AnnaBridge 172:65be27845400 503 /** @brief Reset DFSDM channel handle state.
AnnaBridge 172:65be27845400 504 * @param __HANDLE__ DFSDM channel handle.
AnnaBridge 172:65be27845400 505 * @retval None
AnnaBridge 172:65be27845400 506 */
AnnaBridge 172:65be27845400 507 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
AnnaBridge 172:65be27845400 508
AnnaBridge 172:65be27845400 509 /** @brief Reset DFSDM filter handle state.
AnnaBridge 172:65be27845400 510 * @param __HANDLE__ DFSDM filter handle.
AnnaBridge 172:65be27845400 511 * @retval None
AnnaBridge 172:65be27845400 512 */
AnnaBridge 172:65be27845400 513 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
AnnaBridge 172:65be27845400 514
AnnaBridge 172:65be27845400 515 /**
AnnaBridge 172:65be27845400 516 * @}
AnnaBridge 172:65be27845400 517 */
AnnaBridge 172:65be27845400 518 /* End of exported macros ----------------------------------------------------*/
AnnaBridge 172:65be27845400 519
AnnaBridge 172:65be27845400 520 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 521 /* Include DFSDM HAL Extension module */
AnnaBridge 172:65be27845400 522 #include "stm32l4xx_hal_dfsdm_ex.h"
AnnaBridge 172:65be27845400 523 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 524
AnnaBridge 172:65be27845400 525 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 526 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
AnnaBridge 172:65be27845400 527 * @{
AnnaBridge 172:65be27845400 528 */
AnnaBridge 172:65be27845400 529
AnnaBridge 172:65be27845400 530 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
AnnaBridge 172:65be27845400 531 * @{
AnnaBridge 172:65be27845400 532 */
AnnaBridge 172:65be27845400 533 /* Channel initialization and de-initialization functions *********************/
AnnaBridge 172:65be27845400 534 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 535 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 536 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 537 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 538 /**
AnnaBridge 172:65be27845400 539 * @}
AnnaBridge 172:65be27845400 540 */
AnnaBridge 172:65be27845400 541
AnnaBridge 172:65be27845400 542 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
AnnaBridge 172:65be27845400 543 * @{
AnnaBridge 172:65be27845400 544 */
AnnaBridge 172:65be27845400 545 /* Channel operation functions ************************************************/
AnnaBridge 172:65be27845400 546 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 547 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 548 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 549 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 550
AnnaBridge 172:65be27845400 551 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
AnnaBridge 172:65be27845400 552 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
AnnaBridge 172:65be27845400 553 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 554 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 555
AnnaBridge 172:65be27845400 556 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 557 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
AnnaBridge 172:65be27845400 558
AnnaBridge 172:65be27845400 559 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
AnnaBridge 172:65be27845400 560 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
AnnaBridge 172:65be27845400 561
AnnaBridge 172:65be27845400 562 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 563 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 564 /**
AnnaBridge 172:65be27845400 565 * @}
AnnaBridge 172:65be27845400 566 */
AnnaBridge 172:65be27845400 567
AnnaBridge 172:65be27845400 568 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
AnnaBridge 172:65be27845400 569 * @{
AnnaBridge 172:65be27845400 570 */
AnnaBridge 172:65be27845400 571 /* Channel state function *****************************************************/
AnnaBridge 172:65be27845400 572 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
AnnaBridge 172:65be27845400 573 /**
AnnaBridge 172:65be27845400 574 * @}
AnnaBridge 172:65be27845400 575 */
AnnaBridge 172:65be27845400 576
AnnaBridge 172:65be27845400 577 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
AnnaBridge 172:65be27845400 578 * @{
AnnaBridge 172:65be27845400 579 */
AnnaBridge 172:65be27845400 580 /* Filter initialization and de-initialization functions *********************/
AnnaBridge 172:65be27845400 581 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 582 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 583 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 584 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 585 /**
AnnaBridge 172:65be27845400 586 * @}
AnnaBridge 172:65be27845400 587 */
AnnaBridge 172:65be27845400 588
AnnaBridge 172:65be27845400 589 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
AnnaBridge 172:65be27845400 590 * @{
AnnaBridge 172:65be27845400 591 */
AnnaBridge 172:65be27845400 592 /* Filter control functions *********************/
AnnaBridge 172:65be27845400 593 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
AnnaBridge 172:65be27845400 594 uint32_t Channel,
AnnaBridge 172:65be27845400 595 uint32_t ContinuousMode);
AnnaBridge 172:65be27845400 596 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
AnnaBridge 172:65be27845400 597 uint32_t Channel);
AnnaBridge 172:65be27845400 598 /**
AnnaBridge 172:65be27845400 599 * @}
AnnaBridge 172:65be27845400 600 */
AnnaBridge 172:65be27845400 601
AnnaBridge 172:65be27845400 602 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
AnnaBridge 172:65be27845400 603 * @{
AnnaBridge 172:65be27845400 604 */
AnnaBridge 172:65be27845400 605 /* Filter operation functions *********************/
AnnaBridge 172:65be27845400 606 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 607 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 608 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
AnnaBridge 172:65be27845400 609 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
AnnaBridge 172:65be27845400 610 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 611 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 612 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 613 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 614 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 615 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
AnnaBridge 172:65be27845400 616 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
AnnaBridge 172:65be27845400 617 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 618 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 619 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 620 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
AnnaBridge 172:65be27845400 621 DFSDM_Filter_AwdParamTypeDef* awdParam);
AnnaBridge 172:65be27845400 622 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 623 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
AnnaBridge 172:65be27845400 624 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 625
AnnaBridge 172:65be27845400 626 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
AnnaBridge 172:65be27845400 627 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
AnnaBridge 172:65be27845400 628 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
AnnaBridge 172:65be27845400 629 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
AnnaBridge 172:65be27845400 630 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 631
AnnaBridge 172:65be27845400 632 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 633
AnnaBridge 172:65be27845400 634 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
AnnaBridge 172:65be27845400 635 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
AnnaBridge 172:65be27845400 636
AnnaBridge 172:65be27845400 637 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 638 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 639 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 640 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 641 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
AnnaBridge 172:65be27845400 642 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 643 /**
AnnaBridge 172:65be27845400 644 * @}
AnnaBridge 172:65be27845400 645 */
AnnaBridge 172:65be27845400 646
AnnaBridge 172:65be27845400 647 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
AnnaBridge 172:65be27845400 648 * @{
AnnaBridge 172:65be27845400 649 */
AnnaBridge 172:65be27845400 650 /* Filter state functions *****************************************************/
AnnaBridge 172:65be27845400 651 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 652 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
AnnaBridge 172:65be27845400 653 /**
AnnaBridge 172:65be27845400 654 * @}
AnnaBridge 172:65be27845400 655 */
AnnaBridge 172:65be27845400 656
AnnaBridge 172:65be27845400 657 /**
AnnaBridge 172:65be27845400 658 * @}
AnnaBridge 172:65be27845400 659 */
AnnaBridge 172:65be27845400 660 /* End of exported functions -------------------------------------------------*/
AnnaBridge 172:65be27845400 661
AnnaBridge 172:65be27845400 662 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 663 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros
AnnaBridge 172:65be27845400 664 * @{
AnnaBridge 172:65be27845400 665 */
AnnaBridge 172:65be27845400 666 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
AnnaBridge 172:65be27845400 667 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
AnnaBridge 172:65be27845400 668 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
AnnaBridge 172:65be27845400 669 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 172:65be27845400 670 defined(STM32L496xx) || defined(STM32L4A6xx) || \
AnnaBridge 172:65be27845400 671 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 672 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
AnnaBridge 172:65be27845400 673 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
AnnaBridge 172:65be27845400 674 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
AnnaBridge 172:65be27845400 675 #else
AnnaBridge 172:65be27845400 676 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
AnnaBridge 172:65be27845400 677 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
AnnaBridge 172:65be27845400 678 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
AnnaBridge 172:65be27845400 679 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 172:65be27845400 680 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 681 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
AnnaBridge 172:65be27845400 682 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
AnnaBridge 172:65be27845400 683 ((MODE) == DFSDM_CHANNEL_DUAL_MODE))
AnnaBridge 172:65be27845400 684 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
AnnaBridge 172:65be27845400 685 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
AnnaBridge 172:65be27845400 686 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
AnnaBridge 172:65be27845400 687 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
AnnaBridge 172:65be27845400 688 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
AnnaBridge 172:65be27845400 689 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
AnnaBridge 172:65be27845400 690 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
AnnaBridge 172:65be27845400 691 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
AnnaBridge 172:65be27845400 692 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
AnnaBridge 172:65be27845400 693 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
AnnaBridge 172:65be27845400 694 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
AnnaBridge 172:65be27845400 695 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
AnnaBridge 172:65be27845400 696 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
AnnaBridge 172:65be27845400 697 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
AnnaBridge 172:65be27845400 698 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
AnnaBridge 172:65be27845400 699 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
AnnaBridge 172:65be27845400 700 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
AnnaBridge 172:65be27845400 701 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
AnnaBridge 172:65be27845400 702 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
AnnaBridge 172:65be27845400 703 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
AnnaBridge 172:65be27845400 704 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
AnnaBridge 172:65be27845400 705 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
AnnaBridge 172:65be27845400 706 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
AnnaBridge 172:65be27845400 707 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 172:65be27845400 708 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
AnnaBridge 172:65be27845400 709 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
AnnaBridge 172:65be27845400 710 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
AnnaBridge 172:65be27845400 711 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
AnnaBridge 172:65be27845400 712 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
AnnaBridge 172:65be27845400 713 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
AnnaBridge 172:65be27845400 714 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
AnnaBridge 172:65be27845400 715 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
AnnaBridge 172:65be27845400 716 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
AnnaBridge 172:65be27845400 717 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
AnnaBridge 172:65be27845400 718 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
AnnaBridge 172:65be27845400 719 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
AnnaBridge 172:65be27845400 720 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
AnnaBridge 172:65be27845400 721 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
AnnaBridge 172:65be27845400 722 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
AnnaBridge 172:65be27845400 723 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
AnnaBridge 172:65be27845400 724 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
AnnaBridge 172:65be27845400 725 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
AnnaBridge 172:65be27845400 726 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
AnnaBridge 172:65be27845400 727 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
AnnaBridge 172:65be27845400 728 #else
AnnaBridge 172:65be27845400 729 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
AnnaBridge 172:65be27845400 730 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
AnnaBridge 172:65be27845400 731 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
AnnaBridge 172:65be27845400 732 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
AnnaBridge 172:65be27845400 733 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
AnnaBridge 172:65be27845400 734 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
AnnaBridge 172:65be27845400 735 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
AnnaBridge 172:65be27845400 736 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
AnnaBridge 172:65be27845400 737 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
AnnaBridge 172:65be27845400 738 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
AnnaBridge 172:65be27845400 739 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15))
AnnaBridge 172:65be27845400 740 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
AnnaBridge 172:65be27845400 741 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
AnnaBridge 172:65be27845400 742 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
AnnaBridge 172:65be27845400 743 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
AnnaBridge 172:65be27845400 744 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
AnnaBridge 172:65be27845400 745 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
AnnaBridge 172:65be27845400 746 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
AnnaBridge 172:65be27845400 747 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
AnnaBridge 172:65be27845400 748 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
AnnaBridge 172:65be27845400 749 ((ORDER) == DFSDM_FILTER_SINC5_ORDER))
AnnaBridge 172:65be27845400 750 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
AnnaBridge 172:65be27845400 751 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
AnnaBridge 172:65be27845400 752 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
AnnaBridge 172:65be27845400 753 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
AnnaBridge 172:65be27845400 754 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
AnnaBridge 172:65be27845400 755 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
AnnaBridge 172:65be27845400 756 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx)
AnnaBridge 172:65be27845400 757 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
AnnaBridge 172:65be27845400 758 ((CHANNEL) == DFSDM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 759 ((CHANNEL) == DFSDM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 760 ((CHANNEL) == DFSDM_CHANNEL_3))
AnnaBridge 172:65be27845400 761 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x0003000FU))
AnnaBridge 172:65be27845400 762 #else
AnnaBridge 172:65be27845400 763 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
AnnaBridge 172:65be27845400 764 ((CHANNEL) == DFSDM_CHANNEL_1) || \
AnnaBridge 172:65be27845400 765 ((CHANNEL) == DFSDM_CHANNEL_2) || \
AnnaBridge 172:65be27845400 766 ((CHANNEL) == DFSDM_CHANNEL_3) || \
AnnaBridge 172:65be27845400 767 ((CHANNEL) == DFSDM_CHANNEL_4) || \
AnnaBridge 172:65be27845400 768 ((CHANNEL) == DFSDM_CHANNEL_5) || \
AnnaBridge 172:65be27845400 769 ((CHANNEL) == DFSDM_CHANNEL_6) || \
AnnaBridge 172:65be27845400 770 ((CHANNEL) == DFSDM_CHANNEL_7))
AnnaBridge 172:65be27845400 771 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
AnnaBridge 172:65be27845400 772 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */
AnnaBridge 172:65be27845400 773 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
AnnaBridge 172:65be27845400 774 ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
AnnaBridge 172:65be27845400 775 /**
AnnaBridge 172:65be27845400 776 * @}
AnnaBridge 172:65be27845400 777 */
AnnaBridge 172:65be27845400 778 /* End of private macros -----------------------------------------------------*/
AnnaBridge 172:65be27845400 779
AnnaBridge 172:65be27845400 780 /**
AnnaBridge 172:65be27845400 781 * @}
AnnaBridge 172:65be27845400 782 */
AnnaBridge 172:65be27845400 783
AnnaBridge 172:65be27845400 784 /**
AnnaBridge 172:65be27845400 785 * @}
AnnaBridge 172:65be27845400 786 */
AnnaBridge 172:65be27845400 787 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */
AnnaBridge 172:65be27845400 788 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */
AnnaBridge 172:65be27845400 789 /* STM32L496xx || STM32L4A6xx || */
AnnaBridge 172:65be27845400 790 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
AnnaBridge 172:65be27845400 791
AnnaBridge 172:65be27845400 792 #ifdef __cplusplus
AnnaBridge 172:65be27845400 793 }
AnnaBridge 172:65be27845400 794 #endif
AnnaBridge 172:65be27845400 795
AnnaBridge 172:65be27845400 796 #endif /* __STM32L4xx_HAL_DFSDM_H */
AnnaBridge 172:65be27845400 797
AnnaBridge 172:65be27845400 798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/