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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_STD/stm32h7xx_ll_dmamux.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32h7xx_ll_dmamux.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief Header file of DMAMUX LL module. |
| AnnaBridge | 172:65be27845400 | 6 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 7 | * @attention |
| AnnaBridge | 172:65be27845400 | 8 | * |
| AnnaBridge | 172:65be27845400 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. |
| AnnaBridge | 172:65be27845400 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 172:65be27845400 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 172:65be27845400 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 172:65be27845400 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 172:65be27845400 | 16 | * |
| AnnaBridge | 172:65be27845400 | 17 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 18 | */ |
| AnnaBridge | 172:65be27845400 | 19 | |
| AnnaBridge | 172:65be27845400 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 21 | #ifndef STM32H7xx_LL_DMAMUX_H |
| AnnaBridge | 172:65be27845400 | 22 | #define STM32H7xx_LL_DMAMUX_H |
| AnnaBridge | 172:65be27845400 | 23 | |
| AnnaBridge | 172:65be27845400 | 24 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 25 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 26 | #endif |
| AnnaBridge | 172:65be27845400 | 27 | |
| AnnaBridge | 172:65be27845400 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 29 | #include "stm32h7xx.h" |
| AnnaBridge | 172:65be27845400 | 30 | |
| AnnaBridge | 172:65be27845400 | 31 | /** @addtogroup STM32H7xx_LL_Driver |
| AnnaBridge | 172:65be27845400 | 32 | * @{ |
| AnnaBridge | 172:65be27845400 | 33 | */ |
| AnnaBridge | 172:65be27845400 | 34 | |
| AnnaBridge | 172:65be27845400 | 35 | #if defined (DMAMUX1) || defined (DMAMUX2) |
| AnnaBridge | 172:65be27845400 | 36 | |
| AnnaBridge | 172:65be27845400 | 37 | /** @defgroup DMAMUX_LL DMAMUX |
| AnnaBridge | 172:65be27845400 | 38 | * @{ |
| AnnaBridge | 172:65be27845400 | 39 | */ |
| AnnaBridge | 172:65be27845400 | 40 | |
| AnnaBridge | 172:65be27845400 | 41 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 42 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 43 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 44 | /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants |
| AnnaBridge | 172:65be27845400 | 45 | * @{ |
| AnnaBridge | 172:65be27845400 | 46 | */ |
| AnnaBridge | 172:65be27845400 | 47 | /* Define used to get DMAMUX CCR register size */ |
| AnnaBridge | 172:65be27845400 | 48 | #define DMAMUX_CCR_SIZE 0x00000004U |
| AnnaBridge | 172:65be27845400 | 49 | |
| AnnaBridge | 172:65be27845400 | 50 | /* Define used to get DMAMUX RGCR register size */ |
| AnnaBridge | 172:65be27845400 | 51 | #define DMAMUX_RGCR_SIZE 0x00000004U |
| AnnaBridge | 172:65be27845400 | 52 | |
| AnnaBridge | 172:65be27845400 | 53 | /* Define used to get DMAMUX RequestGenerator offset */ |
| AnnaBridge | 172:65be27845400 | 54 | #define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE) |
| AnnaBridge | 172:65be27845400 | 55 | /* Define used to get DMAMUX Channel Status offset */ |
| AnnaBridge | 172:65be27845400 | 56 | #define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE) |
| AnnaBridge | 172:65be27845400 | 57 | /* Define used to get DMAMUX RequestGenerator status offset */ |
| AnnaBridge | 172:65be27845400 | 58 | #define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE) |
| AnnaBridge | 172:65be27845400 | 59 | |
| AnnaBridge | 172:65be27845400 | 60 | /** |
| AnnaBridge | 172:65be27845400 | 61 | * @} |
| AnnaBridge | 172:65be27845400 | 62 | */ |
| AnnaBridge | 172:65be27845400 | 63 | |
| AnnaBridge | 172:65be27845400 | 64 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 65 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 66 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 67 | /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants |
| AnnaBridge | 172:65be27845400 | 68 | * @{ |
| AnnaBridge | 172:65be27845400 | 69 | */ |
| AnnaBridge | 172:65be27845400 | 70 | /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines |
| AnnaBridge | 172:65be27845400 | 71 | * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function |
| AnnaBridge | 172:65be27845400 | 72 | * @{ |
| AnnaBridge | 172:65be27845400 | 73 | */ |
| AnnaBridge | 172:65be27845400 | 74 | #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ |
| AnnaBridge | 172:65be27845400 | 75 | #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ |
| AnnaBridge | 172:65be27845400 | 76 | #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ |
| AnnaBridge | 172:65be27845400 | 77 | #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ |
| AnnaBridge | 172:65be27845400 | 78 | #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ |
| AnnaBridge | 172:65be27845400 | 79 | #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ |
| AnnaBridge | 172:65be27845400 | 80 | #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ |
| AnnaBridge | 172:65be27845400 | 81 | #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ |
| AnnaBridge | 172:65be27845400 | 82 | #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ |
| AnnaBridge | 172:65be27845400 | 83 | #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ |
| AnnaBridge | 172:65be27845400 | 84 | #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ |
| AnnaBridge | 172:65be27845400 | 85 | #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ |
| AnnaBridge | 172:65be27845400 | 86 | #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ |
| AnnaBridge | 172:65be27845400 | 87 | #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ |
| AnnaBridge | 172:65be27845400 | 88 | #define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ |
| AnnaBridge | 172:65be27845400 | 89 | #define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ |
| AnnaBridge | 172:65be27845400 | 90 | #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 91 | #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 92 | #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 93 | #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 94 | #define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 95 | #define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 96 | #define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 97 | #define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 98 | /** |
| AnnaBridge | 172:65be27845400 | 99 | * @} |
| AnnaBridge | 172:65be27845400 | 100 | */ |
| AnnaBridge | 172:65be27845400 | 101 | |
| AnnaBridge | 172:65be27845400 | 102 | /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines |
| AnnaBridge | 172:65be27845400 | 103 | * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function |
| AnnaBridge | 172:65be27845400 | 104 | * @{ |
| AnnaBridge | 172:65be27845400 | 105 | */ |
| AnnaBridge | 172:65be27845400 | 106 | #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ |
| AnnaBridge | 172:65be27845400 | 107 | #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ |
| AnnaBridge | 172:65be27845400 | 108 | #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ |
| AnnaBridge | 172:65be27845400 | 109 | #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ |
| AnnaBridge | 172:65be27845400 | 110 | #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ |
| AnnaBridge | 172:65be27845400 | 111 | #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ |
| AnnaBridge | 172:65be27845400 | 112 | #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ |
| AnnaBridge | 172:65be27845400 | 113 | #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ |
| AnnaBridge | 172:65be27845400 | 114 | #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ |
| AnnaBridge | 172:65be27845400 | 115 | #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ |
| AnnaBridge | 172:65be27845400 | 116 | #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ |
| AnnaBridge | 172:65be27845400 | 117 | #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ |
| AnnaBridge | 172:65be27845400 | 118 | #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ |
| AnnaBridge | 172:65be27845400 | 119 | #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ |
| AnnaBridge | 172:65be27845400 | 120 | #define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ |
| AnnaBridge | 172:65be27845400 | 121 | #define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ |
| AnnaBridge | 172:65be27845400 | 122 | #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 123 | #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 124 | #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 125 | #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 126 | #define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 127 | #define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 128 | #define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 129 | #define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ |
| AnnaBridge | 172:65be27845400 | 130 | /** |
| AnnaBridge | 172:65be27845400 | 131 | * @} |
| AnnaBridge | 172:65be27845400 | 132 | */ |
| AnnaBridge | 172:65be27845400 | 133 | |
| AnnaBridge | 172:65be27845400 | 134 | /** @defgroup DMAMUX_LL_EC_IT IT Defines |
| AnnaBridge | 172:65be27845400 | 135 | * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions |
| AnnaBridge | 172:65be27845400 | 136 | * @{ |
| AnnaBridge | 172:65be27845400 | 137 | */ |
| AnnaBridge | 172:65be27845400 | 138 | #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ |
| AnnaBridge | 172:65be27845400 | 139 | #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ |
| AnnaBridge | 172:65be27845400 | 140 | /** |
| AnnaBridge | 172:65be27845400 | 141 | * @} |
| AnnaBridge | 172:65be27845400 | 142 | */ |
| AnnaBridge | 172:65be27845400 | 143 | |
| AnnaBridge | 172:65be27845400 | 144 | /** @defgroup DMAMUX_Request_selection DMAMUX Request selection |
| AnnaBridge | 172:65be27845400 | 145 | * @brief DMA Request selection |
| AnnaBridge | 172:65be27845400 | 146 | * @{ |
| AnnaBridge | 172:65be27845400 | 147 | */ |
| AnnaBridge | 172:65be27845400 | 148 | /* D2 Domain : DMAMUX1 requests */ |
| AnnaBridge | 172:65be27845400 | 149 | #define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */ |
| AnnaBridge | 172:65be27845400 | 150 | #define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ |
| AnnaBridge | 172:65be27845400 | 151 | #define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ |
| AnnaBridge | 172:65be27845400 | 152 | #define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ |
| AnnaBridge | 172:65be27845400 | 153 | #define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ |
| AnnaBridge | 172:65be27845400 | 154 | #define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ |
| AnnaBridge | 172:65be27845400 | 155 | #define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ |
| AnnaBridge | 172:65be27845400 | 156 | #define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ |
| AnnaBridge | 172:65be27845400 | 157 | #define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ |
| AnnaBridge | 172:65be27845400 | 158 | #define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */ |
| AnnaBridge | 172:65be27845400 | 159 | #define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */ |
| AnnaBridge | 172:65be27845400 | 160 | #define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 161 | #define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ |
| AnnaBridge | 172:65be27845400 | 162 | #define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ |
| AnnaBridge | 172:65be27845400 | 163 | #define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ |
| AnnaBridge | 172:65be27845400 | 164 | #define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ |
| AnnaBridge | 172:65be27845400 | 165 | #define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ |
| AnnaBridge | 172:65be27845400 | 166 | #define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ |
| AnnaBridge | 172:65be27845400 | 167 | #define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 168 | #define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ |
| AnnaBridge | 172:65be27845400 | 169 | #define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ |
| AnnaBridge | 172:65be27845400 | 170 | #define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ |
| AnnaBridge | 172:65be27845400 | 171 | #define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ |
| AnnaBridge | 172:65be27845400 | 172 | #define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 173 | #define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ |
| AnnaBridge | 172:65be27845400 | 174 | #define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ |
| AnnaBridge | 172:65be27845400 | 175 | #define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ |
| AnnaBridge | 172:65be27845400 | 176 | #define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ |
| AnnaBridge | 172:65be27845400 | 177 | #define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ |
| AnnaBridge | 172:65be27845400 | 178 | #define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 179 | #define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ |
| AnnaBridge | 172:65be27845400 | 180 | #define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ |
| AnnaBridge | 172:65be27845400 | 181 | #define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ |
| AnnaBridge | 172:65be27845400 | 182 | #define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ |
| AnnaBridge | 172:65be27845400 | 183 | #define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ |
| AnnaBridge | 172:65be27845400 | 184 | #define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ |
| AnnaBridge | 172:65be27845400 | 185 | #define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ |
| AnnaBridge | 172:65be27845400 | 186 | #define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ |
| AnnaBridge | 172:65be27845400 | 187 | #define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ |
| AnnaBridge | 172:65be27845400 | 188 | #define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ |
| AnnaBridge | 172:65be27845400 | 189 | #define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ |
| AnnaBridge | 172:65be27845400 | 190 | #define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ |
| AnnaBridge | 172:65be27845400 | 191 | #define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ |
| AnnaBridge | 172:65be27845400 | 192 | #define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ |
| AnnaBridge | 172:65be27845400 | 193 | #define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ |
| AnnaBridge | 172:65be27845400 | 194 | #define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ |
| AnnaBridge | 172:65be27845400 | 195 | #define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ |
| AnnaBridge | 172:65be27845400 | 196 | #define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 197 | #define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ |
| AnnaBridge | 172:65be27845400 | 198 | #define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ |
| AnnaBridge | 172:65be27845400 | 199 | #define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ |
| AnnaBridge | 172:65be27845400 | 200 | #define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ |
| AnnaBridge | 172:65be27845400 | 201 | #define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ |
| AnnaBridge | 172:65be27845400 | 202 | #define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ |
| AnnaBridge | 172:65be27845400 | 203 | #define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 204 | #define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ |
| AnnaBridge | 172:65be27845400 | 205 | #define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ |
| AnnaBridge | 172:65be27845400 | 206 | #define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ |
| AnnaBridge | 172:65be27845400 | 207 | #define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ |
| AnnaBridge | 172:65be27845400 | 208 | #define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ |
| AnnaBridge | 172:65be27845400 | 209 | #define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ |
| AnnaBridge | 172:65be27845400 | 210 | #define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ |
| AnnaBridge | 172:65be27845400 | 211 | #define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ |
| AnnaBridge | 172:65be27845400 | 212 | #define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ |
| AnnaBridge | 172:65be27845400 | 213 | #define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ |
| AnnaBridge | 172:65be27845400 | 214 | #define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ |
| AnnaBridge | 172:65be27845400 | 215 | #define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ |
| AnnaBridge | 172:65be27845400 | 216 | #define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ |
| AnnaBridge | 172:65be27845400 | 217 | #define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ |
| AnnaBridge | 172:65be27845400 | 218 | #define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ |
| AnnaBridge | 172:65be27845400 | 219 | #define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ |
| AnnaBridge | 172:65be27845400 | 220 | #define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ |
| AnnaBridge | 172:65be27845400 | 221 | #define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ |
| AnnaBridge | 172:65be27845400 | 222 | #define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ |
| AnnaBridge | 172:65be27845400 | 223 | #define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */ |
| AnnaBridge | 172:65be27845400 | 224 | #define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ |
| AnnaBridge | 172:65be27845400 | 225 | #define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ |
| AnnaBridge | 172:65be27845400 | 226 | #define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ |
| AnnaBridge | 172:65be27845400 | 227 | #define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ |
| AnnaBridge | 172:65be27845400 | 228 | #define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ |
| AnnaBridge | 172:65be27845400 | 229 | #define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ |
| AnnaBridge | 172:65be27845400 | 230 | #define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ |
| AnnaBridge | 172:65be27845400 | 231 | #define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ |
| AnnaBridge | 172:65be27845400 | 232 | #define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ |
| AnnaBridge | 172:65be27845400 | 233 | #define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ |
| AnnaBridge | 172:65be27845400 | 234 | #define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ |
| AnnaBridge | 172:65be27845400 | 235 | #define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ |
| AnnaBridge | 172:65be27845400 | 236 | #define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ |
| AnnaBridge | 172:65be27845400 | 237 | #define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ |
| AnnaBridge | 172:65be27845400 | 238 | #define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ |
| AnnaBridge | 172:65be27845400 | 239 | #define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ |
| AnnaBridge | 172:65be27845400 | 240 | #define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ |
| AnnaBridge | 172:65be27845400 | 241 | #define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ |
| AnnaBridge | 172:65be27845400 | 242 | #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ |
| AnnaBridge | 172:65be27845400 | 243 | #define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ |
| AnnaBridge | 172:65be27845400 | 244 | #define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */ |
| AnnaBridge | 172:65be27845400 | 245 | #define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */ |
| AnnaBridge | 172:65be27845400 | 246 | #define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */ |
| AnnaBridge | 172:65be27845400 | 247 | #define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */ |
| AnnaBridge | 172:65be27845400 | 248 | #define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */ |
| AnnaBridge | 172:65be27845400 | 249 | #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ |
| AnnaBridge | 172:65be27845400 | 250 | #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ |
| AnnaBridge | 172:65be27845400 | 251 | #define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ |
| AnnaBridge | 172:65be27845400 | 252 | #define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ |
| AnnaBridge | 172:65be27845400 | 253 | #define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 254 | #define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ |
| AnnaBridge | 172:65be27845400 | 255 | #define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ |
| AnnaBridge | 172:65be27845400 | 256 | #define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ |
| AnnaBridge | 172:65be27845400 | 257 | #define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 258 | #define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ |
| AnnaBridge | 172:65be27845400 | 259 | #define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ |
| AnnaBridge | 172:65be27845400 | 260 | #define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ |
| AnnaBridge | 172:65be27845400 | 261 | #define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ |
| AnnaBridge | 172:65be27845400 | 262 | #define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ |
| AnnaBridge | 172:65be27845400 | 263 | #define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */ |
| AnnaBridge | 172:65be27845400 | 264 | /* D3 Domain : DMAMUX2 requests */ |
| AnnaBridge | 172:65be27845400 | 265 | #define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */ |
| AnnaBridge | 172:65be27845400 | 266 | #define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ |
| AnnaBridge | 172:65be27845400 | 267 | #define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ |
| AnnaBridge | 172:65be27845400 | 268 | #define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ |
| AnnaBridge | 172:65be27845400 | 269 | #define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ |
| AnnaBridge | 172:65be27845400 | 270 | #define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ |
| AnnaBridge | 172:65be27845400 | 271 | #define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ |
| AnnaBridge | 172:65be27845400 | 272 | #define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ |
| AnnaBridge | 172:65be27845400 | 273 | #define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ |
| AnnaBridge | 172:65be27845400 | 274 | #define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ |
| AnnaBridge | 172:65be27845400 | 275 | #define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ |
| AnnaBridge | 172:65be27845400 | 276 | #define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ |
| AnnaBridge | 172:65be27845400 | 277 | #define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ |
| AnnaBridge | 172:65be27845400 | 278 | #define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ |
| AnnaBridge | 172:65be27845400 | 279 | #define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ |
| AnnaBridge | 172:65be27845400 | 280 | #define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ |
| AnnaBridge | 172:65be27845400 | 281 | #define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ |
| AnnaBridge | 172:65be27845400 | 282 | #define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */ |
| AnnaBridge | 172:65be27845400 | 283 | /** |
| AnnaBridge | 172:65be27845400 | 284 | * @} |
| AnnaBridge | 172:65be27845400 | 285 | */ |
| AnnaBridge | 172:65be27845400 | 286 | |
| AnnaBridge | 172:65be27845400 | 287 | |
| AnnaBridge | 172:65be27845400 | 288 | /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel |
| AnnaBridge | 172:65be27845400 | 289 | * @{ |
| AnnaBridge | 172:65be27845400 | 290 | */ |
| AnnaBridge | 172:65be27845400 | 291 | #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */ |
| AnnaBridge | 172:65be27845400 | 292 | #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */ |
| AnnaBridge | 172:65be27845400 | 293 | #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */ |
| AnnaBridge | 172:65be27845400 | 294 | #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */ |
| AnnaBridge | 172:65be27845400 | 295 | #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */ |
| AnnaBridge | 172:65be27845400 | 296 | #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */ |
| AnnaBridge | 172:65be27845400 | 297 | #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */ |
| AnnaBridge | 172:65be27845400 | 298 | #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */ |
| AnnaBridge | 172:65be27845400 | 299 | #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */ |
| AnnaBridge | 172:65be27845400 | 300 | #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */ |
| AnnaBridge | 172:65be27845400 | 301 | #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */ |
| AnnaBridge | 172:65be27845400 | 302 | #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */ |
| AnnaBridge | 172:65be27845400 | 303 | #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */ |
| AnnaBridge | 172:65be27845400 | 304 | #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */ |
| AnnaBridge | 172:65be27845400 | 305 | #define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */ |
| AnnaBridge | 172:65be27845400 | 306 | #define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */ |
| AnnaBridge | 172:65be27845400 | 307 | /** |
| AnnaBridge | 172:65be27845400 | 308 | * @} |
| AnnaBridge | 172:65be27845400 | 309 | */ |
| AnnaBridge | 172:65be27845400 | 310 | |
| AnnaBridge | 172:65be27845400 | 311 | /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity |
| AnnaBridge | 172:65be27845400 | 312 | * @{ |
| AnnaBridge | 172:65be27845400 | 313 | */ |
| AnnaBridge | 172:65be27845400 | 314 | #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ |
| AnnaBridge | 172:65be27845400 | 315 | #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ |
| AnnaBridge | 172:65be27845400 | 316 | #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ |
| AnnaBridge | 172:65be27845400 | 317 | #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ |
| AnnaBridge | 172:65be27845400 | 318 | /** |
| AnnaBridge | 172:65be27845400 | 319 | * @} |
| AnnaBridge | 172:65be27845400 | 320 | */ |
| AnnaBridge | 172:65be27845400 | 321 | |
| AnnaBridge | 172:65be27845400 | 322 | /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event |
| AnnaBridge | 172:65be27845400 | 323 | * @{ |
| AnnaBridge | 172:65be27845400 | 324 | */ |
| AnnaBridge | 172:65be27845400 | 325 | #define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel0 Event */ |
| AnnaBridge | 172:65be27845400 | 326 | #define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel1 Event */ |
| AnnaBridge | 172:65be27845400 | 327 | #define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel2 Event */ |
| AnnaBridge | 172:65be27845400 | 328 | #define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< D2 Domain synchronization Signal is LPTIM1 OUT */ |
| AnnaBridge | 172:65be27845400 | 329 | #define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< D2 Domain synchronization Signal is LPTIM2 OUT */ |
| AnnaBridge | 172:65be27845400 | 330 | #define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< D2 Domain synchronization Signal is LPTIM3 OUT */ |
| AnnaBridge | 172:65be27845400 | 331 | #define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< D2 Domain synchronization Signal is EXTI0 IT */ |
| AnnaBridge | 172:65be27845400 | 332 | #define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< D2 Domain synchronization Signal is TIM12 TRGO */ |
| AnnaBridge | 172:65be27845400 | 333 | |
| AnnaBridge | 172:65be27845400 | 334 | #define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel0 Event */ |
| AnnaBridge | 172:65be27845400 | 335 | #define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel1 Event */ |
| AnnaBridge | 172:65be27845400 | 336 | #define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel2 Event */ |
| AnnaBridge | 172:65be27845400 | 337 | #define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel3 Event */ |
| AnnaBridge | 172:65be27845400 | 338 | #define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel4 Event */ |
| AnnaBridge | 172:65be27845400 | 339 | #define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel5 Event */ |
| AnnaBridge | 172:65be27845400 | 340 | #define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< D3 Domain synchronization Signal is LPUART1 RX Wakeup */ |
| AnnaBridge | 172:65be27845400 | 341 | #define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< D3 Domain synchronization Signal is LPUART1 TX Wakeup */ |
| AnnaBridge | 172:65be27845400 | 342 | #define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< D3 Domain synchronization Signal is LPTIM2 output */ |
| AnnaBridge | 172:65be27845400 | 343 | #define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< D3 Domain synchronization Signal is LPTIM3 output */ |
| AnnaBridge | 172:65be27845400 | 344 | #define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< D3 Domain synchronization Signal is I2C4 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 345 | #define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< D3 Domain synchronization Signal is SPI6 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 346 | #define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< D3 Domain synchronization Signal is Comparator 1 output */ |
| AnnaBridge | 172:65be27845400 | 347 | #define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< D3 Domain synchronization Signal is RTC Wakeup */ |
| AnnaBridge | 172:65be27845400 | 348 | #define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< D3 Domain synchronization Signal is EXTI0 IT */ |
| AnnaBridge | 172:65be27845400 | 349 | #define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< D3 Domain synchronization Signal is EXTI2 IT */ |
| AnnaBridge | 172:65be27845400 | 350 | |
| AnnaBridge | 172:65be27845400 | 351 | /** |
| AnnaBridge | 172:65be27845400 | 352 | * @} |
| AnnaBridge | 172:65be27845400 | 353 | */ |
| AnnaBridge | 172:65be27845400 | 354 | |
| AnnaBridge | 172:65be27845400 | 355 | /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel |
| AnnaBridge | 172:65be27845400 | 356 | * @{ |
| AnnaBridge | 172:65be27845400 | 357 | */ |
| AnnaBridge | 172:65be27845400 | 358 | #define LL_DMAMUX_REQ_GEN_0 0x00000000U |
| AnnaBridge | 172:65be27845400 | 359 | #define LL_DMAMUX_REQ_GEN_1 0x00000001U |
| AnnaBridge | 172:65be27845400 | 360 | #define LL_DMAMUX_REQ_GEN_2 0x00000002U |
| AnnaBridge | 172:65be27845400 | 361 | #define LL_DMAMUX_REQ_GEN_3 0x00000003U |
| AnnaBridge | 172:65be27845400 | 362 | #define LL_DMAMUX_REQ_GEN_4 0x00000004U |
| AnnaBridge | 172:65be27845400 | 363 | #define LL_DMAMUX_REQ_GEN_5 0x00000005U |
| AnnaBridge | 172:65be27845400 | 364 | #define LL_DMAMUX_REQ_GEN_6 0x00000006U |
| AnnaBridge | 172:65be27845400 | 365 | #define LL_DMAMUX_REQ_GEN_7 0x00000007U |
| AnnaBridge | 172:65be27845400 | 366 | /** |
| AnnaBridge | 172:65be27845400 | 367 | * @} |
| AnnaBridge | 172:65be27845400 | 368 | */ |
| AnnaBridge | 172:65be27845400 | 369 | |
| AnnaBridge | 172:65be27845400 | 370 | /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity |
| AnnaBridge | 172:65be27845400 | 371 | * @{ |
| AnnaBridge | 172:65be27845400 | 372 | */ |
| AnnaBridge | 172:65be27845400 | 373 | #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ |
| AnnaBridge | 172:65be27845400 | 374 | #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ |
| AnnaBridge | 172:65be27845400 | 375 | #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ |
| AnnaBridge | 172:65be27845400 | 376 | #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ |
| AnnaBridge | 172:65be27845400 | 377 | /** |
| AnnaBridge | 172:65be27845400 | 378 | * @} |
| AnnaBridge | 172:65be27845400 | 379 | */ |
| AnnaBridge | 172:65be27845400 | 380 | |
| AnnaBridge | 172:65be27845400 | 381 | /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation |
| AnnaBridge | 172:65be27845400 | 382 | * @{ |
| AnnaBridge | 172:65be27845400 | 383 | */ |
| AnnaBridge | 172:65be27845400 | 384 | #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< D2 domain Request generator Signal is DMAMUX1 Channel0 Event */ |
| AnnaBridge | 172:65be27845400 | 385 | #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< D2 domain Request generator Signal is DMAMUX1 Channel1 Event */ |
| AnnaBridge | 172:65be27845400 | 386 | #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< D2 domain Request generator Signal is DMAMUX1 Channel2 Event */ |
| AnnaBridge | 172:65be27845400 | 387 | #define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< D2 domain Request generator Signal is LPTIM1 OUT */ |
| AnnaBridge | 172:65be27845400 | 388 | #define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< D2 domain Request generator Signal is LPTIM2 OUT */ |
| AnnaBridge | 172:65be27845400 | 389 | #define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< D2 domain Request generator Signal is LPTIM3 OUT */ |
| AnnaBridge | 172:65be27845400 | 390 | #define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< D2 domain Request generator Signal is EXTI0 IT */ |
| AnnaBridge | 172:65be27845400 | 391 | #define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< D2 domain Request generator Signal is TIM12 TRGO */ |
| AnnaBridge | 172:65be27845400 | 392 | |
| AnnaBridge | 172:65be27845400 | 393 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< D3 domain Request generator Signal is DMAMUX2 Channel0 Event */ |
| AnnaBridge | 172:65be27845400 | 394 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< D3 domain Request generator Signal is DMAMUX2 Channel1 Event */ |
| AnnaBridge | 172:65be27845400 | 395 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< D3 domain Request generator Signal is DMAMUX2 Channel2 Event */ |
| AnnaBridge | 172:65be27845400 | 396 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< D3 domain Request generator Signal is DMAMUX2 Channel3 Event */ |
| AnnaBridge | 172:65be27845400 | 397 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< D3 domain Request generator Signal is DMAMUX2 Channel4 Event */ |
| AnnaBridge | 172:65be27845400 | 398 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< D3 domain Request generator Signal is DMAMUX2 Channel5 Event */ |
| AnnaBridge | 172:65be27845400 | 399 | #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< D3 domain Request generator Signal is DMAMUX2 Channel6 Event */ |
| AnnaBridge | 172:65be27845400 | 400 | #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< D3 domain Request generator Signal is LPUART1 RX Wakeup */ |
| AnnaBridge | 172:65be27845400 | 401 | #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< D3 domain Request generator Signal is LPUART1 TX Wakeup */ |
| AnnaBridge | 172:65be27845400 | 402 | #define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< D3 domain Request generator Signal is LPTIM2 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 403 | #define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< D3 domain Request generator Signal is LPTIM2 OUT */ |
| AnnaBridge | 172:65be27845400 | 404 | #define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< D3 domain Request generator Signal is LPTIM3 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 405 | #define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< D3 domain Request generator Signal is LPTIM3 OUT */ |
| AnnaBridge | 172:65be27845400 | 406 | #define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< D3 domain Request generator Signal is LPTIM4 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 407 | #define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< D3 domain Request generator Signal is LPTIM5 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 408 | #define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< D3 domain Request generator Signal is I2C4 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 409 | #define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< D3 domain Request generator Signal is SPI6 Wakeup */ |
| AnnaBridge | 172:65be27845400 | 410 | #define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< D3 domain Request generator Signal is Comparator 1 output */ |
| AnnaBridge | 172:65be27845400 | 411 | #define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< D3 domain Request generator Signal is Comparator 2 output */ |
| AnnaBridge | 172:65be27845400 | 412 | #define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< D3 domain Request generator Signal is RTC Wakeup */ |
| AnnaBridge | 172:65be27845400 | 413 | #define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< D3 domain Request generator Signal is EXTI0 */ |
| AnnaBridge | 172:65be27845400 | 414 | #define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< D3 domain Request generator Signal is EXTI2 */ |
| AnnaBridge | 172:65be27845400 | 415 | #define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< D3 domain Request generator Signal is I2C4 IT Event */ |
| AnnaBridge | 172:65be27845400 | 416 | #define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< D3 domain Request generator Signal is SPI6 IT */ |
| AnnaBridge | 172:65be27845400 | 417 | #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< D3 domain Request generator Signal is LPUART1 Tx IT */ |
| AnnaBridge | 172:65be27845400 | 418 | #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< D3 domain Request generator Signal is LPUART1 Rx IT */ |
| AnnaBridge | 172:65be27845400 | 419 | #define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< D3 domain Request generator Signal is ADC3 IT */ |
| AnnaBridge | 172:65be27845400 | 420 | #define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< D3 domain Request generator Signal is ADC3 Analog Watchdog 1 output */ |
| AnnaBridge | 172:65be27845400 | 421 | #define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< D3 domain Request generator Signal is BDMA Channel 0 IT */ |
| AnnaBridge | 172:65be27845400 | 422 | #define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< D3 domain Request generator Signal is BDMA Channel 1 IT */ |
| AnnaBridge | 172:65be27845400 | 423 | /** |
| AnnaBridge | 172:65be27845400 | 424 | * @} |
| AnnaBridge | 172:65be27845400 | 425 | */ |
| AnnaBridge | 172:65be27845400 | 426 | |
| AnnaBridge | 172:65be27845400 | 427 | /** |
| AnnaBridge | 172:65be27845400 | 428 | * @} |
| AnnaBridge | 172:65be27845400 | 429 | */ |
| AnnaBridge | 172:65be27845400 | 430 | |
| AnnaBridge | 172:65be27845400 | 431 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 432 | /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros |
| AnnaBridge | 172:65be27845400 | 433 | * @{ |
| AnnaBridge | 172:65be27845400 | 434 | */ |
| AnnaBridge | 172:65be27845400 | 435 | |
| AnnaBridge | 172:65be27845400 | 436 | /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros |
| AnnaBridge | 172:65be27845400 | 437 | * @{ |
| AnnaBridge | 172:65be27845400 | 438 | */ |
| AnnaBridge | 172:65be27845400 | 439 | /** |
| AnnaBridge | 172:65be27845400 | 440 | * @brief Write a value in DMAMUX register |
| AnnaBridge | 172:65be27845400 | 441 | * @param __INSTANCE__ DMAMUX Instance |
| AnnaBridge | 172:65be27845400 | 442 | * @param __REG__ Register to be written |
| AnnaBridge | 172:65be27845400 | 443 | * @param __VALUE__ Value to be written in the register |
| AnnaBridge | 172:65be27845400 | 444 | * @retval None |
| AnnaBridge | 172:65be27845400 | 445 | */ |
| AnnaBridge | 172:65be27845400 | 446 | #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| AnnaBridge | 172:65be27845400 | 447 | |
| AnnaBridge | 172:65be27845400 | 448 | /** |
| AnnaBridge | 172:65be27845400 | 449 | * @brief Read a value in DMAMUX register |
| AnnaBridge | 172:65be27845400 | 450 | * @param __INSTANCE__ DMAMUX Instance |
| AnnaBridge | 172:65be27845400 | 451 | * @param __REG__ Register to be read |
| AnnaBridge | 172:65be27845400 | 452 | * @retval Register value |
| AnnaBridge | 172:65be27845400 | 453 | */ |
| AnnaBridge | 172:65be27845400 | 454 | #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| AnnaBridge | 172:65be27845400 | 455 | /** |
| AnnaBridge | 172:65be27845400 | 456 | * @} |
| AnnaBridge | 172:65be27845400 | 457 | */ |
| AnnaBridge | 172:65be27845400 | 458 | |
| AnnaBridge | 172:65be27845400 | 459 | /** |
| AnnaBridge | 172:65be27845400 | 460 | * @} |
| AnnaBridge | 172:65be27845400 | 461 | */ |
| AnnaBridge | 172:65be27845400 | 462 | |
| AnnaBridge | 172:65be27845400 | 463 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 464 | /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions |
| AnnaBridge | 172:65be27845400 | 465 | * @{ |
| AnnaBridge | 172:65be27845400 | 466 | */ |
| AnnaBridge | 172:65be27845400 | 467 | |
| AnnaBridge | 172:65be27845400 | 468 | /** @defgroup DMAMUX_LL_EF_Configuration Configuration |
| AnnaBridge | 172:65be27845400 | 469 | * @{ |
| AnnaBridge | 172:65be27845400 | 470 | */ |
| AnnaBridge | 172:65be27845400 | 471 | /** |
| AnnaBridge | 172:65be27845400 | 472 | * @brief Set DMAMUX request ID for DMAMUX Channel x. |
| AnnaBridge | 172:65be27845400 | 473 | * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. |
| AnnaBridge | 172:65be27845400 | 474 | * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. |
| AnnaBridge | 172:65be27845400 | 475 | * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. |
| AnnaBridge | 172:65be27845400 | 476 | * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID |
| AnnaBridge | 172:65be27845400 | 477 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 478 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 479 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 480 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 481 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 482 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 483 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 484 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 485 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 486 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 487 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 488 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 489 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 490 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 491 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 492 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 493 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 494 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 495 | * @param Request This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 496 | * @arg @ref LL_DMAMUX1_REQ_MEM2MEM |
| AnnaBridge | 172:65be27845400 | 497 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 |
| AnnaBridge | 172:65be27845400 | 498 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 |
| AnnaBridge | 172:65be27845400 | 499 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 |
| AnnaBridge | 172:65be27845400 | 500 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 |
| AnnaBridge | 172:65be27845400 | 501 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 |
| AnnaBridge | 172:65be27845400 | 502 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 |
| AnnaBridge | 172:65be27845400 | 503 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 |
| AnnaBridge | 172:65be27845400 | 504 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 |
| AnnaBridge | 172:65be27845400 | 505 | * @arg @ref LL_DMAMUX1_REQ_ADC1 |
| AnnaBridge | 172:65be27845400 | 506 | * @arg @ref LL_DMAMUX1_REQ_ADC2 |
| AnnaBridge | 172:65be27845400 | 507 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 |
| AnnaBridge | 172:65be27845400 | 508 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 |
| AnnaBridge | 172:65be27845400 | 509 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 |
| AnnaBridge | 172:65be27845400 | 510 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 |
| AnnaBridge | 172:65be27845400 | 511 | * @arg @ref LL_DMAMUX1_REQ_TIM1_UP |
| AnnaBridge | 172:65be27845400 | 512 | * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG |
| AnnaBridge | 172:65be27845400 | 513 | * @arg @ref LL_DMAMUX1_REQ_TIM1_COM |
| AnnaBridge | 172:65be27845400 | 514 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 |
| AnnaBridge | 172:65be27845400 | 515 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 |
| AnnaBridge | 172:65be27845400 | 516 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 |
| AnnaBridge | 172:65be27845400 | 517 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 |
| AnnaBridge | 172:65be27845400 | 518 | * @arg @ref LL_DMAMUX1_REQ_TIM2_UP |
| AnnaBridge | 172:65be27845400 | 519 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 |
| AnnaBridge | 172:65be27845400 | 520 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 |
| AnnaBridge | 172:65be27845400 | 521 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 |
| AnnaBridge | 172:65be27845400 | 522 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 |
| AnnaBridge | 172:65be27845400 | 523 | * @arg @ref LL_DMAMUX1_REQ_TIM3_UP |
| AnnaBridge | 172:65be27845400 | 524 | * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG |
| AnnaBridge | 172:65be27845400 | 525 | * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 |
| AnnaBridge | 172:65be27845400 | 526 | * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 |
| AnnaBridge | 172:65be27845400 | 527 | * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 |
| AnnaBridge | 172:65be27845400 | 528 | * @arg @ref LL_DMAMUX1_REQ_TIM4_UP |
| AnnaBridge | 172:65be27845400 | 529 | * @arg @ref LL_DMAMUX1_REQ_I2C1_RX |
| AnnaBridge | 172:65be27845400 | 530 | * @arg @ref LL_DMAMUX1_REQ_I2C1_TX |
| AnnaBridge | 172:65be27845400 | 531 | * @arg @ref LL_DMAMUX1_REQ_I2C2_RX |
| AnnaBridge | 172:65be27845400 | 532 | * @arg @ref LL_DMAMUX1_REQ_I2C2_TX |
| AnnaBridge | 172:65be27845400 | 533 | * @arg @ref LL_DMAMUX1_REQ_SPI1_RX |
| AnnaBridge | 172:65be27845400 | 534 | * @arg @ref LL_DMAMUX1_REQ_SPI1_TX |
| AnnaBridge | 172:65be27845400 | 535 | * @arg @ref LL_DMAMUX1_REQ_SPI2_RX |
| AnnaBridge | 172:65be27845400 | 536 | * @arg @ref LL_DMAMUX1_REQ_SPI2_TX |
| AnnaBridge | 172:65be27845400 | 537 | * @arg @ref LL_DMAMUX1_REQ_USART1_RX |
| AnnaBridge | 172:65be27845400 | 538 | * @arg @ref LL_DMAMUX1_REQ_USART1_TX |
| AnnaBridge | 172:65be27845400 | 539 | * @arg @ref LL_DMAMUX1_REQ_USART2_RX |
| AnnaBridge | 172:65be27845400 | 540 | * @arg @ref LL_DMAMUX1_REQ_USART2_TX |
| AnnaBridge | 172:65be27845400 | 541 | * @arg @ref LL_DMAMUX1_REQ_USART3_RX |
| AnnaBridge | 172:65be27845400 | 542 | * @arg @ref LL_DMAMUX1_REQ_USART3_TX |
| AnnaBridge | 172:65be27845400 | 543 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 |
| AnnaBridge | 172:65be27845400 | 544 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 |
| AnnaBridge | 172:65be27845400 | 545 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 |
| AnnaBridge | 172:65be27845400 | 546 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 |
| AnnaBridge | 172:65be27845400 | 547 | * @arg @ref LL_DMAMUX1_REQ_TIM8_UP |
| AnnaBridge | 172:65be27845400 | 548 | * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG |
| AnnaBridge | 172:65be27845400 | 549 | * @arg @ref LL_DMAMUX1_REQ_TIM8_COM |
| AnnaBridge | 172:65be27845400 | 550 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 |
| AnnaBridge | 172:65be27845400 | 551 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 |
| AnnaBridge | 172:65be27845400 | 552 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 |
| AnnaBridge | 172:65be27845400 | 553 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 |
| AnnaBridge | 172:65be27845400 | 554 | * @arg @ref LL_DMAMUX1_REQ_TIM5_UP |
| AnnaBridge | 172:65be27845400 | 555 | * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG |
| AnnaBridge | 172:65be27845400 | 556 | * @arg @ref LL_DMAMUX1_REQ_SPI3_RX |
| AnnaBridge | 172:65be27845400 | 557 | * @arg @ref LL_DMAMUX1_REQ_SPI3_TX |
| AnnaBridge | 172:65be27845400 | 558 | * @arg @ref LL_DMAMUX1_REQ_UART4_RX |
| AnnaBridge | 172:65be27845400 | 559 | * @arg @ref LL_DMAMUX1_REQ_UART4_TX |
| AnnaBridge | 172:65be27845400 | 560 | * @arg @ref LL_DMAMUX1_REQ_UART5_RX |
| AnnaBridge | 172:65be27845400 | 561 | * @arg @ref LL_DMAMUX1_REQ_UART5_TX |
| AnnaBridge | 172:65be27845400 | 562 | * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 |
| AnnaBridge | 172:65be27845400 | 563 | * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 |
| AnnaBridge | 172:65be27845400 | 564 | * @arg @ref LL_DMAMUX1_REQ_TIM6_UP |
| AnnaBridge | 172:65be27845400 | 565 | * @arg @ref LL_DMAMUX1_REQ_TIM7_UP |
| AnnaBridge | 172:65be27845400 | 566 | * @arg @ref LL_DMAMUX1_REQ_USART6_RX |
| AnnaBridge | 172:65be27845400 | 567 | * @arg @ref LL_DMAMUX1_REQ_USART6_TX |
| AnnaBridge | 172:65be27845400 | 568 | * @arg @ref LL_DMAMUX1_REQ_I2C3_RX |
| AnnaBridge | 172:65be27845400 | 569 | * @arg @ref LL_DMAMUX1_REQ_I2C3_TX |
| AnnaBridge | 172:65be27845400 | 570 | * @arg @ref LL_DMAMUX1_REQ_DCMI |
| AnnaBridge | 172:65be27845400 | 571 | * @arg @ref LL_DMAMUX1_REQ_CRYP_IN |
| AnnaBridge | 172:65be27845400 | 572 | * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT |
| AnnaBridge | 172:65be27845400 | 573 | * @arg @ref LL_DMAMUX1_REQ_HASH_IN |
| AnnaBridge | 172:65be27845400 | 574 | * @arg @ref LL_DMAMUX1_REQ_UART7_RX |
| AnnaBridge | 172:65be27845400 | 575 | * @arg @ref LL_DMAMUX1_REQ_UART7_TX |
| AnnaBridge | 172:65be27845400 | 576 | * @arg @ref LL_DMAMUX1_REQ_UART8_RX |
| AnnaBridge | 172:65be27845400 | 577 | * @arg @ref LL_DMAMUX1_REQ_UART8_TX |
| AnnaBridge | 172:65be27845400 | 578 | * @arg @ref LL_DMAMUX1_REQ_SPI4_RX |
| AnnaBridge | 172:65be27845400 | 579 | * @arg @ref LL_DMAMUX1_REQ_SPI4_TX |
| AnnaBridge | 172:65be27845400 | 580 | * @arg @ref LL_DMAMUX1_REQ_SPI5_RX |
| AnnaBridge | 172:65be27845400 | 581 | * @arg @ref LL_DMAMUX1_REQ_SPI5_TX |
| AnnaBridge | 172:65be27845400 | 582 | * @arg @ref LL_DMAMUX1_REQ_SAI1_A |
| AnnaBridge | 172:65be27845400 | 583 | * @arg @ref LL_DMAMUX1_REQ_SAI1_B |
| AnnaBridge | 172:65be27845400 | 584 | * @arg @ref LL_DMAMUX1_REQ_SAI2_A |
| AnnaBridge | 172:65be27845400 | 585 | * @arg @ref LL_DMAMUX1_REQ_SAI2_B |
| AnnaBridge | 172:65be27845400 | 586 | * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX |
| AnnaBridge | 172:65be27845400 | 587 | * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX |
| AnnaBridge | 172:65be27845400 | 588 | * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT |
| AnnaBridge | 172:65be27845400 | 589 | * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS |
| AnnaBridge | 172:65be27845400 | 590 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER |
| AnnaBridge | 172:65be27845400 | 591 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A |
| AnnaBridge | 172:65be27845400 | 592 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B |
| AnnaBridge | 172:65be27845400 | 593 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C |
| AnnaBridge | 172:65be27845400 | 594 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D |
| AnnaBridge | 172:65be27845400 | 595 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E |
| AnnaBridge | 172:65be27845400 | 596 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 |
| AnnaBridge | 172:65be27845400 | 597 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 |
| AnnaBridge | 172:65be27845400 | 598 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 |
| AnnaBridge | 172:65be27845400 | 599 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 |
| AnnaBridge | 172:65be27845400 | 600 | * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 |
| AnnaBridge | 172:65be27845400 | 601 | * @arg @ref LL_DMAMUX1_REQ_TIM15_UP |
| AnnaBridge | 172:65be27845400 | 602 | * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG |
| AnnaBridge | 172:65be27845400 | 603 | * @arg @ref LL_DMAMUX1_REQ_TIM15_COM |
| AnnaBridge | 172:65be27845400 | 604 | * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 |
| AnnaBridge | 172:65be27845400 | 605 | * @arg @ref LL_DMAMUX1_REQ_TIM16_UP |
| AnnaBridge | 172:65be27845400 | 606 | * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 |
| AnnaBridge | 172:65be27845400 | 607 | * @arg @ref LL_DMAMUX1_REQ_TIM17_UP |
| AnnaBridge | 172:65be27845400 | 608 | * @arg @ref LL_DMAMUX1_REQ_SAI3_A |
| AnnaBridge | 172:65be27845400 | 609 | * @arg @ref LL_DMAMUX1_REQ_SAI3_B |
| AnnaBridge | 172:65be27845400 | 610 | * @arg @ref LL_DMAMUX1_REQ_ADC3 |
| AnnaBridge | 172:65be27845400 | 611 | * @arg @ref LL_DMAMUX2_REQ_MEM2MEM |
| AnnaBridge | 172:65be27845400 | 612 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 |
| AnnaBridge | 172:65be27845400 | 613 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 |
| AnnaBridge | 172:65be27845400 | 614 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 |
| AnnaBridge | 172:65be27845400 | 615 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 |
| AnnaBridge | 172:65be27845400 | 616 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 |
| AnnaBridge | 172:65be27845400 | 617 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 |
| AnnaBridge | 172:65be27845400 | 618 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 |
| AnnaBridge | 172:65be27845400 | 619 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 |
| AnnaBridge | 172:65be27845400 | 620 | * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX |
| AnnaBridge | 172:65be27845400 | 621 | * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX |
| AnnaBridge | 172:65be27845400 | 622 | * @arg @ref LL_DMAMUX2_REQ_SPI6_RX |
| AnnaBridge | 172:65be27845400 | 623 | * @arg @ref LL_DMAMUX2_REQ_SPI6_TX |
| AnnaBridge | 172:65be27845400 | 624 | * @arg @ref LL_DMAMUX2_REQ_I2C4_RX |
| AnnaBridge | 172:65be27845400 | 625 | * @arg @ref LL_DMAMUX2_REQ_I2C4_TX |
| AnnaBridge | 172:65be27845400 | 626 | * @arg @ref LL_DMAMUX2_REQ_SAI4_A |
| AnnaBridge | 172:65be27845400 | 627 | * @arg @ref LL_DMAMUX2_REQ_SAI4_B |
| AnnaBridge | 172:65be27845400 | 628 | * @arg @ref LL_DMAMUX2_REQ_ADC3 |
| AnnaBridge | 172:65be27845400 | 629 | * @retval None |
| AnnaBridge | 172:65be27845400 | 630 | */ |
| AnnaBridge | 172:65be27845400 | 631 | __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) |
| AnnaBridge | 172:65be27845400 | 632 | { |
| AnnaBridge | 172:65be27845400 | 633 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 634 | |
| AnnaBridge | 172:65be27845400 | 635 | MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); |
| AnnaBridge | 172:65be27845400 | 636 | } |
| AnnaBridge | 172:65be27845400 | 637 | |
| AnnaBridge | 172:65be27845400 | 638 | /** |
| AnnaBridge | 172:65be27845400 | 639 | * @brief Get DMAMUX request ID for DMAMUX Channel x. |
| AnnaBridge | 172:65be27845400 | 640 | * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. |
| AnnaBridge | 172:65be27845400 | 641 | * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. |
| AnnaBridge | 172:65be27845400 | 642 | * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. |
| AnnaBridge | 172:65be27845400 | 643 | * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID |
| AnnaBridge | 172:65be27845400 | 644 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 645 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 646 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 647 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 648 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 649 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 650 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 651 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 652 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 653 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 654 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 655 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 656 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 657 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 658 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 659 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 660 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 661 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 662 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 663 | * @arg @ref LL_DMAMUX1_REQ_MEM2MEM |
| AnnaBridge | 172:65be27845400 | 664 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 |
| AnnaBridge | 172:65be27845400 | 665 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 |
| AnnaBridge | 172:65be27845400 | 666 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 |
| AnnaBridge | 172:65be27845400 | 667 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 |
| AnnaBridge | 172:65be27845400 | 668 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 |
| AnnaBridge | 172:65be27845400 | 669 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 |
| AnnaBridge | 172:65be27845400 | 670 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 |
| AnnaBridge | 172:65be27845400 | 671 | * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 |
| AnnaBridge | 172:65be27845400 | 672 | * @arg @ref LL_DMAMUX1_REQ_ADC1 |
| AnnaBridge | 172:65be27845400 | 673 | * @arg @ref LL_DMAMUX1_REQ_ADC2 |
| AnnaBridge | 172:65be27845400 | 674 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 |
| AnnaBridge | 172:65be27845400 | 675 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 |
| AnnaBridge | 172:65be27845400 | 676 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 |
| AnnaBridge | 172:65be27845400 | 677 | * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 |
| AnnaBridge | 172:65be27845400 | 678 | * @arg @ref LL_DMAMUX1_REQ_TIM1_UP |
| AnnaBridge | 172:65be27845400 | 679 | * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG |
| AnnaBridge | 172:65be27845400 | 680 | * @arg @ref LL_DMAMUX1_REQ_TIM1_COM |
| AnnaBridge | 172:65be27845400 | 681 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 |
| AnnaBridge | 172:65be27845400 | 682 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 |
| AnnaBridge | 172:65be27845400 | 683 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 |
| AnnaBridge | 172:65be27845400 | 684 | * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 |
| AnnaBridge | 172:65be27845400 | 685 | * @arg @ref LL_DMAMUX1_REQ_TIM2_UP |
| AnnaBridge | 172:65be27845400 | 686 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 |
| AnnaBridge | 172:65be27845400 | 687 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 |
| AnnaBridge | 172:65be27845400 | 688 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 |
| AnnaBridge | 172:65be27845400 | 689 | * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 |
| AnnaBridge | 172:65be27845400 | 690 | * @arg @ref LL_DMAMUX1_REQ_TIM3_UP |
| AnnaBridge | 172:65be27845400 | 691 | * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG |
| AnnaBridge | 172:65be27845400 | 692 | * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 |
| AnnaBridge | 172:65be27845400 | 693 | * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 |
| AnnaBridge | 172:65be27845400 | 694 | * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 |
| AnnaBridge | 172:65be27845400 | 695 | * @arg @ref LL_DMAMUX1_REQ_TIM4_UP |
| AnnaBridge | 172:65be27845400 | 696 | * @arg @ref LL_DMAMUX1_REQ_I2C1_RX |
| AnnaBridge | 172:65be27845400 | 697 | * @arg @ref LL_DMAMUX1_REQ_I2C1_TX |
| AnnaBridge | 172:65be27845400 | 698 | * @arg @ref LL_DMAMUX1_REQ_I2C2_RX |
| AnnaBridge | 172:65be27845400 | 699 | * @arg @ref LL_DMAMUX1_REQ_I2C2_TX |
| AnnaBridge | 172:65be27845400 | 700 | * @arg @ref LL_DMAMUX1_REQ_SPI1_RX |
| AnnaBridge | 172:65be27845400 | 701 | * @arg @ref LL_DMAMUX1_REQ_SPI1_TX |
| AnnaBridge | 172:65be27845400 | 702 | * @arg @ref LL_DMAMUX1_REQ_SPI2_RX |
| AnnaBridge | 172:65be27845400 | 703 | * @arg @ref LL_DMAMUX1_REQ_SPI2_TX |
| AnnaBridge | 172:65be27845400 | 704 | * @arg @ref LL_DMAMUX1_REQ_USART1_RX |
| AnnaBridge | 172:65be27845400 | 705 | * @arg @ref LL_DMAMUX1_REQ_USART1_TX |
| AnnaBridge | 172:65be27845400 | 706 | * @arg @ref LL_DMAMUX1_REQ_USART2_RX |
| AnnaBridge | 172:65be27845400 | 707 | * @arg @ref LL_DMAMUX1_REQ_USART2_TX |
| AnnaBridge | 172:65be27845400 | 708 | * @arg @ref LL_DMAMUX1_REQ_USART3_RX |
| AnnaBridge | 172:65be27845400 | 709 | * @arg @ref LL_DMAMUX1_REQ_USART3_TX |
| AnnaBridge | 172:65be27845400 | 710 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 |
| AnnaBridge | 172:65be27845400 | 711 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 |
| AnnaBridge | 172:65be27845400 | 712 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 |
| AnnaBridge | 172:65be27845400 | 713 | * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 |
| AnnaBridge | 172:65be27845400 | 714 | * @arg @ref LL_DMAMUX1_REQ_TIM8_UP |
| AnnaBridge | 172:65be27845400 | 715 | * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG |
| AnnaBridge | 172:65be27845400 | 716 | * @arg @ref LL_DMAMUX1_REQ_TIM8_COM |
| AnnaBridge | 172:65be27845400 | 717 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 |
| AnnaBridge | 172:65be27845400 | 718 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 |
| AnnaBridge | 172:65be27845400 | 719 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 |
| AnnaBridge | 172:65be27845400 | 720 | * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 |
| AnnaBridge | 172:65be27845400 | 721 | * @arg @ref LL_DMAMUX1_REQ_TIM5_UP |
| AnnaBridge | 172:65be27845400 | 722 | * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG |
| AnnaBridge | 172:65be27845400 | 723 | * @arg @ref LL_DMAMUX1_REQ_SPI3_RX |
| AnnaBridge | 172:65be27845400 | 724 | * @arg @ref LL_DMAMUX1_REQ_SPI3_TX |
| AnnaBridge | 172:65be27845400 | 725 | * @arg @ref LL_DMAMUX1_REQ_UART4_RX |
| AnnaBridge | 172:65be27845400 | 726 | * @arg @ref LL_DMAMUX1_REQ_UART4_TX |
| AnnaBridge | 172:65be27845400 | 727 | * @arg @ref LL_DMAMUX1_REQ_UART5_RX |
| AnnaBridge | 172:65be27845400 | 728 | * @arg @ref LL_DMAMUX1_REQ_UART5_TX |
| AnnaBridge | 172:65be27845400 | 729 | * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 |
| AnnaBridge | 172:65be27845400 | 730 | * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 |
| AnnaBridge | 172:65be27845400 | 731 | * @arg @ref LL_DMAMUX1_REQ_TIM6_UP |
| AnnaBridge | 172:65be27845400 | 732 | * @arg @ref LL_DMAMUX1_REQ_TIM7_UP |
| AnnaBridge | 172:65be27845400 | 733 | * @arg @ref LL_DMAMUX1_REQ_USART6_RX |
| AnnaBridge | 172:65be27845400 | 734 | * @arg @ref LL_DMAMUX1_REQ_USART6_TX |
| AnnaBridge | 172:65be27845400 | 735 | * @arg @ref LL_DMAMUX1_REQ_I2C3_RX |
| AnnaBridge | 172:65be27845400 | 736 | * @arg @ref LL_DMAMUX1_REQ_I2C3_TX |
| AnnaBridge | 172:65be27845400 | 737 | * @arg @ref LL_DMAMUX1_REQ_DCMI |
| AnnaBridge | 172:65be27845400 | 738 | * @arg @ref LL_DMAMUX1_REQ_CRYP_IN |
| AnnaBridge | 172:65be27845400 | 739 | * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT |
| AnnaBridge | 172:65be27845400 | 740 | * @arg @ref LL_DMAMUX1_REQ_HASH_IN |
| AnnaBridge | 172:65be27845400 | 741 | * @arg @ref LL_DMAMUX1_REQ_UART7_RX |
| AnnaBridge | 172:65be27845400 | 742 | * @arg @ref LL_DMAMUX1_REQ_UART7_TX |
| AnnaBridge | 172:65be27845400 | 743 | * @arg @ref LL_DMAMUX1_REQ_UART8_RX |
| AnnaBridge | 172:65be27845400 | 744 | * @arg @ref LL_DMAMUX1_REQ_UART8_TX |
| AnnaBridge | 172:65be27845400 | 745 | * @arg @ref LL_DMAMUX1_REQ_SPI4_RX |
| AnnaBridge | 172:65be27845400 | 746 | * @arg @ref LL_DMAMUX1_REQ_SPI4_TX |
| AnnaBridge | 172:65be27845400 | 747 | * @arg @ref LL_DMAMUX1_REQ_SPI5_RX |
| AnnaBridge | 172:65be27845400 | 748 | * @arg @ref LL_DMAMUX1_REQ_SPI5_TX |
| AnnaBridge | 172:65be27845400 | 749 | * @arg @ref LL_DMAMUX1_REQ_SAI1_A |
| AnnaBridge | 172:65be27845400 | 750 | * @arg @ref LL_DMAMUX1_REQ_SAI1_B |
| AnnaBridge | 172:65be27845400 | 751 | * @arg @ref LL_DMAMUX1_REQ_SAI2_A |
| AnnaBridge | 172:65be27845400 | 752 | * @arg @ref LL_DMAMUX1_REQ_SAI2_B |
| AnnaBridge | 172:65be27845400 | 753 | * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX |
| AnnaBridge | 172:65be27845400 | 754 | * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX |
| AnnaBridge | 172:65be27845400 | 755 | * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT |
| AnnaBridge | 172:65be27845400 | 756 | * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS |
| AnnaBridge | 172:65be27845400 | 757 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER |
| AnnaBridge | 172:65be27845400 | 758 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A |
| AnnaBridge | 172:65be27845400 | 759 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B |
| AnnaBridge | 172:65be27845400 | 760 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C |
| AnnaBridge | 172:65be27845400 | 761 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D |
| AnnaBridge | 172:65be27845400 | 762 | * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E |
| AnnaBridge | 172:65be27845400 | 763 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 |
| AnnaBridge | 172:65be27845400 | 764 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 |
| AnnaBridge | 172:65be27845400 | 765 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 |
| AnnaBridge | 172:65be27845400 | 766 | * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 |
| AnnaBridge | 172:65be27845400 | 767 | * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 |
| AnnaBridge | 172:65be27845400 | 768 | * @arg @ref LL_DMAMUX1_REQ_TIM15_UP |
| AnnaBridge | 172:65be27845400 | 769 | * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG |
| AnnaBridge | 172:65be27845400 | 770 | * @arg @ref LL_DMAMUX1_REQ_TIM15_COM |
| AnnaBridge | 172:65be27845400 | 771 | * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 |
| AnnaBridge | 172:65be27845400 | 772 | * @arg @ref LL_DMAMUX1_REQ_TIM16_UP |
| AnnaBridge | 172:65be27845400 | 773 | * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 |
| AnnaBridge | 172:65be27845400 | 774 | * @arg @ref LL_DMAMUX1_REQ_TIM17_UP |
| AnnaBridge | 172:65be27845400 | 775 | * @arg @ref LL_DMAMUX1_REQ_SAI3_A |
| AnnaBridge | 172:65be27845400 | 776 | * @arg @ref LL_DMAMUX1_REQ_SAI3_B |
| AnnaBridge | 172:65be27845400 | 777 | * @arg @ref LL_DMAMUX1_REQ_ADC3 |
| AnnaBridge | 172:65be27845400 | 778 | * @arg @ref LL_DMAMUX2_REQ_MEM2MEM |
| AnnaBridge | 172:65be27845400 | 779 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 |
| AnnaBridge | 172:65be27845400 | 780 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 |
| AnnaBridge | 172:65be27845400 | 781 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 |
| AnnaBridge | 172:65be27845400 | 782 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 |
| AnnaBridge | 172:65be27845400 | 783 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 |
| AnnaBridge | 172:65be27845400 | 784 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 |
| AnnaBridge | 172:65be27845400 | 785 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 |
| AnnaBridge | 172:65be27845400 | 786 | * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 |
| AnnaBridge | 172:65be27845400 | 787 | * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX |
| AnnaBridge | 172:65be27845400 | 788 | * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX |
| AnnaBridge | 172:65be27845400 | 789 | * @arg @ref LL_DMAMUX2_REQ_SPI6_RX |
| AnnaBridge | 172:65be27845400 | 790 | * @arg @ref LL_DMAMUX2_REQ_SPI6_TX |
| AnnaBridge | 172:65be27845400 | 791 | * @arg @ref LL_DMAMUX2_REQ_I2C4_RX |
| AnnaBridge | 172:65be27845400 | 792 | * @arg @ref LL_DMAMUX2_REQ_I2C4_TX |
| AnnaBridge | 172:65be27845400 | 793 | * @arg @ref LL_DMAMUX2_REQ_SAI4_A |
| AnnaBridge | 172:65be27845400 | 794 | * @arg @ref LL_DMAMUX2_REQ_SAI4_B |
| AnnaBridge | 172:65be27845400 | 795 | * @arg @ref LL_DMAMUX2_REQ_ADC3 |
| AnnaBridge | 172:65be27845400 | 796 | */ |
| AnnaBridge | 172:65be27845400 | 797 | __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 798 | { |
| AnnaBridge | 172:65be27845400 | 799 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 800 | |
| AnnaBridge | 172:65be27845400 | 801 | return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); |
| AnnaBridge | 172:65be27845400 | 802 | } |
| AnnaBridge | 172:65be27845400 | 803 | |
| AnnaBridge | 172:65be27845400 | 804 | /** |
| AnnaBridge | 172:65be27845400 | 805 | * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. |
| AnnaBridge | 172:65be27845400 | 806 | * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb |
| AnnaBridge | 172:65be27845400 | 807 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 808 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 809 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 810 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 811 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 812 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 813 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 814 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 815 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 816 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 817 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 818 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 819 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 820 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 821 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 822 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 823 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 824 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 825 | * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. |
| AnnaBridge | 172:65be27845400 | 826 | * @retval None |
| AnnaBridge | 172:65be27845400 | 827 | */ |
| AnnaBridge | 172:65be27845400 | 828 | __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) |
| AnnaBridge | 172:65be27845400 | 829 | { |
| AnnaBridge | 172:65be27845400 | 830 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 831 | |
| AnnaBridge | 172:65be27845400 | 832 | MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos); |
| AnnaBridge | 172:65be27845400 | 833 | } |
| AnnaBridge | 172:65be27845400 | 834 | |
| AnnaBridge | 172:65be27845400 | 835 | /** |
| AnnaBridge | 172:65be27845400 | 836 | * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. |
| AnnaBridge | 172:65be27845400 | 837 | * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb |
| AnnaBridge | 172:65be27845400 | 838 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 839 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 840 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 841 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 842 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 843 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 844 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 845 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 846 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 847 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 848 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 849 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 850 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 851 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 852 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 853 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 854 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 855 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 856 | * @retval Between Min_Data = 1 and Max_Data = 32 |
| AnnaBridge | 172:65be27845400 | 857 | */ |
| AnnaBridge | 172:65be27845400 | 858 | __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 859 | { |
| AnnaBridge | 172:65be27845400 | 860 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 861 | |
| AnnaBridge | 172:65be27845400 | 862 | return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); |
| AnnaBridge | 172:65be27845400 | 863 | } |
| AnnaBridge | 172:65be27845400 | 864 | |
| AnnaBridge | 172:65be27845400 | 865 | /** |
| AnnaBridge | 172:65be27845400 | 866 | * @brief Set the polarity of the signal on which the DMA request is synchronized. |
| AnnaBridge | 172:65be27845400 | 867 | * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity |
| AnnaBridge | 172:65be27845400 | 868 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 869 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 870 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 871 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 872 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 873 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 874 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 875 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 876 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 877 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 878 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 879 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 880 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 881 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 882 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 883 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 884 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 885 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 886 | * @param Polarity This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 887 | * @arg @ref LL_DMAMUX_SYNC_NO_EVENT |
| AnnaBridge | 172:65be27845400 | 888 | * @arg @ref LL_DMAMUX_SYNC_POL_RISING |
| AnnaBridge | 172:65be27845400 | 889 | * @arg @ref LL_DMAMUX_SYNC_POL_FALLING |
| AnnaBridge | 172:65be27845400 | 890 | * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING |
| AnnaBridge | 172:65be27845400 | 891 | * @retval None |
| AnnaBridge | 172:65be27845400 | 892 | */ |
| AnnaBridge | 172:65be27845400 | 893 | __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) |
| AnnaBridge | 172:65be27845400 | 894 | { |
| AnnaBridge | 172:65be27845400 | 895 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 896 | |
| AnnaBridge | 172:65be27845400 | 897 | MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity); |
| AnnaBridge | 172:65be27845400 | 898 | } |
| AnnaBridge | 172:65be27845400 | 899 | |
| AnnaBridge | 172:65be27845400 | 900 | /** |
| AnnaBridge | 172:65be27845400 | 901 | * @brief Get the polarity of the signal on which the DMA request is synchronized. |
| AnnaBridge | 172:65be27845400 | 902 | * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity |
| AnnaBridge | 172:65be27845400 | 903 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 904 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 905 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 906 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 907 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 908 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 909 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 910 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 911 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 912 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 913 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 914 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 915 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 916 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 917 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 918 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 919 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 920 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 921 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 922 | * @arg @ref LL_DMAMUX_SYNC_NO_EVENT |
| AnnaBridge | 172:65be27845400 | 923 | * @arg @ref LL_DMAMUX_SYNC_POL_RISING |
| AnnaBridge | 172:65be27845400 | 924 | * @arg @ref LL_DMAMUX_SYNC_POL_FALLING |
| AnnaBridge | 172:65be27845400 | 925 | * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING |
| AnnaBridge | 172:65be27845400 | 926 | */ |
| AnnaBridge | 172:65be27845400 | 927 | __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 928 | { |
| AnnaBridge | 172:65be27845400 | 929 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 930 | |
| AnnaBridge | 172:65be27845400 | 931 | return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL)); |
| AnnaBridge | 172:65be27845400 | 932 | } |
| AnnaBridge | 172:65be27845400 | 933 | |
| AnnaBridge | 172:65be27845400 | 934 | /** |
| AnnaBridge | 172:65be27845400 | 935 | * @brief Enable the Event Generation on DMAMUX channel x. |
| AnnaBridge | 172:65be27845400 | 936 | * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration |
| AnnaBridge | 172:65be27845400 | 937 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 938 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 939 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 940 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 941 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 942 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 943 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 944 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 945 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 946 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 947 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 948 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 949 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 950 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 951 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 952 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 953 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 954 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 955 | * @retval None |
| AnnaBridge | 172:65be27845400 | 956 | */ |
| AnnaBridge | 172:65be27845400 | 957 | __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 958 | { |
| AnnaBridge | 172:65be27845400 | 959 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 960 | |
| AnnaBridge | 172:65be27845400 | 961 | SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); |
| AnnaBridge | 172:65be27845400 | 962 | } |
| AnnaBridge | 172:65be27845400 | 963 | |
| AnnaBridge | 172:65be27845400 | 964 | /** |
| AnnaBridge | 172:65be27845400 | 965 | * @brief Disable the Event Generation on DMAMUX channel x. |
| AnnaBridge | 172:65be27845400 | 966 | * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration |
| AnnaBridge | 172:65be27845400 | 967 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 968 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 969 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 970 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 971 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 972 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 973 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 974 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 975 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 976 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 977 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 978 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 979 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 980 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 981 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 982 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 983 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 984 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 985 | * @retval None |
| AnnaBridge | 172:65be27845400 | 986 | */ |
| AnnaBridge | 172:65be27845400 | 987 | __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 988 | { |
| AnnaBridge | 172:65be27845400 | 989 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 990 | |
| AnnaBridge | 172:65be27845400 | 991 | CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); |
| AnnaBridge | 172:65be27845400 | 992 | } |
| AnnaBridge | 172:65be27845400 | 993 | |
| AnnaBridge | 172:65be27845400 | 994 | /** |
| AnnaBridge | 172:65be27845400 | 995 | * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. |
| AnnaBridge | 172:65be27845400 | 996 | * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration |
| AnnaBridge | 172:65be27845400 | 997 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 998 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 999 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 1000 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 1001 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 1002 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 1003 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 1004 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 1005 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 1006 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 1007 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 1008 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 1009 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 1010 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 1011 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 1012 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 1013 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 1014 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 1015 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1016 | */ |
| AnnaBridge | 172:65be27845400 | 1017 | __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 1018 | { |
| AnnaBridge | 172:65be27845400 | 1019 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1020 | |
| AnnaBridge | 172:65be27845400 | 1021 | return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1022 | } |
| AnnaBridge | 172:65be27845400 | 1023 | |
| AnnaBridge | 172:65be27845400 | 1024 | /** |
| AnnaBridge | 172:65be27845400 | 1025 | * @brief Enable the synchronization mode. |
| AnnaBridge | 172:65be27845400 | 1026 | * @rmtoll CxCR SE LL_DMAMUX_EnableSync |
| AnnaBridge | 172:65be27845400 | 1027 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1028 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1029 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 1030 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 1031 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 1032 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 1033 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 1034 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 1035 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 1036 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 1037 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 1038 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 1039 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 1040 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 1041 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 1042 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 1043 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 1044 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 1045 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1046 | */ |
| AnnaBridge | 172:65be27845400 | 1047 | __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 1048 | { |
| AnnaBridge | 172:65be27845400 | 1049 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1050 | |
| AnnaBridge | 172:65be27845400 | 1051 | SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); |
| AnnaBridge | 172:65be27845400 | 1052 | } |
| AnnaBridge | 172:65be27845400 | 1053 | |
| AnnaBridge | 172:65be27845400 | 1054 | /** |
| AnnaBridge | 172:65be27845400 | 1055 | * @brief Disable the synchronization mode. |
| AnnaBridge | 172:65be27845400 | 1056 | * @rmtoll CxCR SE LL_DMAMUX_DisableSync |
| AnnaBridge | 172:65be27845400 | 1057 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1058 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1059 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 1060 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 1061 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 1062 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 1063 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 1064 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 1065 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 1066 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 1067 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 1068 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 1069 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 1070 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 1071 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 1072 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 1073 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 1074 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 1075 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1076 | */ |
| AnnaBridge | 172:65be27845400 | 1077 | __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 1078 | { |
| AnnaBridge | 172:65be27845400 | 1079 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1080 | |
| AnnaBridge | 172:65be27845400 | 1081 | CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); |
| AnnaBridge | 172:65be27845400 | 1082 | } |
| AnnaBridge | 172:65be27845400 | 1083 | |
| AnnaBridge | 172:65be27845400 | 1084 | /** |
| AnnaBridge | 172:65be27845400 | 1085 | * @brief Check if the synchronization mode is enabled or disabled. |
| AnnaBridge | 172:65be27845400 | 1086 | * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync |
| AnnaBridge | 172:65be27845400 | 1087 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1088 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1089 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 1090 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 1091 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 1092 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 1093 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 1094 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 1095 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 1096 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 1097 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 1098 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 1099 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 1100 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 1101 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 1102 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 1103 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 1104 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 1105 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1106 | */ |
| AnnaBridge | 172:65be27845400 | 1107 | __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 1108 | { |
| AnnaBridge | 172:65be27845400 | 1109 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1110 | |
| AnnaBridge | 172:65be27845400 | 1111 | return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1112 | } |
| AnnaBridge | 172:65be27845400 | 1113 | |
| AnnaBridge | 172:65be27845400 | 1114 | /** |
| AnnaBridge | 172:65be27845400 | 1115 | * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. |
| AnnaBridge | 172:65be27845400 | 1116 | * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID |
| AnnaBridge | 172:65be27845400 | 1117 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1118 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1119 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 1120 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 1121 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 1122 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 1123 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 1124 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 1125 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 1126 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 1127 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 1128 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 1129 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 1130 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 1131 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 1132 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 1133 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 1134 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 1135 | * @param SyncID This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1136 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1137 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1138 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1139 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT |
| AnnaBridge | 172:65be27845400 | 1140 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1141 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1142 | * @arg @ref LL_DMAMUX1_SYNC_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1143 | * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO |
| AnnaBridge | 172:65be27845400 | 1144 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1145 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1146 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1147 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT |
| AnnaBridge | 172:65be27845400 | 1148 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT |
| AnnaBridge | 172:65be27845400 | 1149 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT |
| AnnaBridge | 172:65be27845400 | 1150 | * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP |
| AnnaBridge | 172:65be27845400 | 1151 | * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP |
| AnnaBridge | 172:65be27845400 | 1152 | * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1153 | * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1154 | * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP |
| AnnaBridge | 172:65be27845400 | 1155 | * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP |
| AnnaBridge | 172:65be27845400 | 1156 | * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT |
| AnnaBridge | 172:65be27845400 | 1157 | * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP |
| AnnaBridge | 172:65be27845400 | 1158 | * @arg @ref LL_DMAMUX2_SYNC_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1159 | * @arg @ref LL_DMAMUX2_SYNC_EXTI2 |
| AnnaBridge | 172:65be27845400 | 1160 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1161 | */ |
| AnnaBridge | 172:65be27845400 | 1162 | __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) |
| AnnaBridge | 172:65be27845400 | 1163 | { |
| AnnaBridge | 172:65be27845400 | 1164 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1165 | |
| AnnaBridge | 172:65be27845400 | 1166 | MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); |
| AnnaBridge | 172:65be27845400 | 1167 | } |
| AnnaBridge | 172:65be27845400 | 1168 | |
| AnnaBridge | 172:65be27845400 | 1169 | /** |
| AnnaBridge | 172:65be27845400 | 1170 | * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. |
| AnnaBridge | 172:65be27845400 | 1171 | * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID |
| AnnaBridge | 172:65be27845400 | 1172 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1173 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1174 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 1175 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 1176 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 1177 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 1178 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 1179 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 1180 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 1181 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 1182 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 1183 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 1184 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 1185 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 1186 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 1187 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 1188 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 1189 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 1190 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1191 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1192 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1193 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1194 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT |
| AnnaBridge | 172:65be27845400 | 1195 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1196 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1197 | * @arg @ref LL_DMAMUX1_SYNC_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1198 | * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO |
| AnnaBridge | 172:65be27845400 | 1199 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1200 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1201 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1202 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT |
| AnnaBridge | 172:65be27845400 | 1203 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT |
| AnnaBridge | 172:65be27845400 | 1204 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT |
| AnnaBridge | 172:65be27845400 | 1205 | * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP |
| AnnaBridge | 172:65be27845400 | 1206 | * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP |
| AnnaBridge | 172:65be27845400 | 1207 | * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1208 | * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1209 | * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP |
| AnnaBridge | 172:65be27845400 | 1210 | * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP |
| AnnaBridge | 172:65be27845400 | 1211 | * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT |
| AnnaBridge | 172:65be27845400 | 1212 | * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP |
| AnnaBridge | 172:65be27845400 | 1213 | * @arg @ref LL_DMAMUX2_SYNC_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1214 | * @arg @ref LL_DMAMUX2_SYNC_EXTI2 |
| AnnaBridge | 172:65be27845400 | 1215 | */ |
| AnnaBridge | 172:65be27845400 | 1216 | __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 1217 | { |
| AnnaBridge | 172:65be27845400 | 1218 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1219 | |
| AnnaBridge | 172:65be27845400 | 1220 | return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID)); |
| AnnaBridge | 172:65be27845400 | 1221 | } |
| AnnaBridge | 172:65be27845400 | 1222 | |
| AnnaBridge | 172:65be27845400 | 1223 | /** |
| AnnaBridge | 172:65be27845400 | 1224 | * @brief Enable the Request Generator. |
| AnnaBridge | 172:65be27845400 | 1225 | * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen |
| AnnaBridge | 172:65be27845400 | 1226 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1227 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1228 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1229 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1230 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1231 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1232 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1233 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1234 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1235 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1236 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1237 | */ |
| AnnaBridge | 172:65be27845400 | 1238 | __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 1239 | { |
| AnnaBridge | 172:65be27845400 | 1240 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1241 | |
| AnnaBridge | 172:65be27845400 | 1242 | SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); |
| AnnaBridge | 172:65be27845400 | 1243 | } |
| AnnaBridge | 172:65be27845400 | 1244 | |
| AnnaBridge | 172:65be27845400 | 1245 | /** |
| AnnaBridge | 172:65be27845400 | 1246 | * @brief Disable the Request Generator. |
| AnnaBridge | 172:65be27845400 | 1247 | * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen |
| AnnaBridge | 172:65be27845400 | 1248 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1249 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1250 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1251 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1252 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1253 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1254 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1255 | */ |
| AnnaBridge | 172:65be27845400 | 1256 | __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 1257 | { |
| AnnaBridge | 172:65be27845400 | 1258 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1259 | |
| AnnaBridge | 172:65be27845400 | 1260 | CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); |
| AnnaBridge | 172:65be27845400 | 1261 | } |
| AnnaBridge | 172:65be27845400 | 1262 | |
| AnnaBridge | 172:65be27845400 | 1263 | /** |
| AnnaBridge | 172:65be27845400 | 1264 | * @brief Check if the Request Generator is enabled or disabled. |
| AnnaBridge | 172:65be27845400 | 1265 | * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen |
| AnnaBridge | 172:65be27845400 | 1266 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1267 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1268 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1269 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1270 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1271 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1272 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1273 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1274 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1275 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1276 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1277 | */ |
| AnnaBridge | 172:65be27845400 | 1278 | __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 1279 | { |
| AnnaBridge | 172:65be27845400 | 1280 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1281 | |
| AnnaBridge | 172:65be27845400 | 1282 | return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1283 | } |
| AnnaBridge | 172:65be27845400 | 1284 | |
| AnnaBridge | 172:65be27845400 | 1285 | /** |
| AnnaBridge | 172:65be27845400 | 1286 | * @brief Set the polarity of the signal on which the DMA request is generated. |
| AnnaBridge | 172:65be27845400 | 1287 | * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity |
| AnnaBridge | 172:65be27845400 | 1288 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1289 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1290 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1291 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1292 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1293 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1294 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1295 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1296 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1297 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1298 | * @param Polarity This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1299 | * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT |
| AnnaBridge | 172:65be27845400 | 1300 | * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING |
| AnnaBridge | 172:65be27845400 | 1301 | * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING |
| AnnaBridge | 172:65be27845400 | 1302 | * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING |
| AnnaBridge | 172:65be27845400 | 1303 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1304 | */ |
| AnnaBridge | 172:65be27845400 | 1305 | __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) |
| AnnaBridge | 172:65be27845400 | 1306 | { |
| AnnaBridge | 172:65be27845400 | 1307 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1308 | |
| AnnaBridge | 172:65be27845400 | 1309 | MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); |
| AnnaBridge | 172:65be27845400 | 1310 | } |
| AnnaBridge | 172:65be27845400 | 1311 | |
| AnnaBridge | 172:65be27845400 | 1312 | /** |
| AnnaBridge | 172:65be27845400 | 1313 | * @brief Get the polarity of the signal on which the DMA request is generated. |
| AnnaBridge | 172:65be27845400 | 1314 | * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity |
| AnnaBridge | 172:65be27845400 | 1315 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1316 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1317 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1318 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1319 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1320 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1321 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1322 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1323 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1324 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1325 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1326 | * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT |
| AnnaBridge | 172:65be27845400 | 1327 | * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING |
| AnnaBridge | 172:65be27845400 | 1328 | * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING |
| AnnaBridge | 172:65be27845400 | 1329 | * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING |
| AnnaBridge | 172:65be27845400 | 1330 | */ |
| AnnaBridge | 172:65be27845400 | 1331 | __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 1332 | { |
| AnnaBridge | 172:65be27845400 | 1333 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1334 | |
| AnnaBridge | 172:65be27845400 | 1335 | return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL)); |
| AnnaBridge | 172:65be27845400 | 1336 | } |
| AnnaBridge | 172:65be27845400 | 1337 | |
| AnnaBridge | 172:65be27845400 | 1338 | /** |
| AnnaBridge | 172:65be27845400 | 1339 | * @brief Set the number of DMA request that will be autorized after a generation event. |
| AnnaBridge | 172:65be27845400 | 1340 | * @note This field can only be written when Generator is disabled. |
| AnnaBridge | 172:65be27845400 | 1341 | * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb |
| AnnaBridge | 172:65be27845400 | 1342 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1343 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1344 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1345 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1346 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1347 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1348 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1349 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1350 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1351 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1352 | * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. |
| AnnaBridge | 172:65be27845400 | 1353 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1354 | */ |
| AnnaBridge | 172:65be27845400 | 1355 | __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) |
| AnnaBridge | 172:65be27845400 | 1356 | { |
| AnnaBridge | 172:65be27845400 | 1357 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1358 | |
| AnnaBridge | 172:65be27845400 | 1359 | MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); |
| AnnaBridge | 172:65be27845400 | 1360 | } |
| AnnaBridge | 172:65be27845400 | 1361 | |
| AnnaBridge | 172:65be27845400 | 1362 | /** |
| AnnaBridge | 172:65be27845400 | 1363 | * @brief Get the number of DMA request that will be autorized after a generation event. |
| AnnaBridge | 172:65be27845400 | 1364 | * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb |
| AnnaBridge | 172:65be27845400 | 1365 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1366 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1367 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1368 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1369 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1370 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1371 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1372 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1373 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1374 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1375 | * @retval Between Min_Data = 1 and Max_Data = 32 |
| AnnaBridge | 172:65be27845400 | 1376 | */ |
| AnnaBridge | 172:65be27845400 | 1377 | __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 1378 | { |
| AnnaBridge | 172:65be27845400 | 1379 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1380 | |
| AnnaBridge | 172:65be27845400 | 1381 | return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); |
| AnnaBridge | 172:65be27845400 | 1382 | } |
| AnnaBridge | 172:65be27845400 | 1383 | |
| AnnaBridge | 172:65be27845400 | 1384 | /** |
| AnnaBridge | 172:65be27845400 | 1385 | * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. |
| AnnaBridge | 172:65be27845400 | 1386 | * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID |
| AnnaBridge | 172:65be27845400 | 1387 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1388 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1389 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1390 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1391 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1392 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1393 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1394 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1395 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1396 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1397 | * @param RequestSignalID This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1398 | * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1399 | * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1400 | * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1401 | * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT |
| AnnaBridge | 172:65be27845400 | 1402 | * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1403 | * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1404 | * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1405 | * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO |
| AnnaBridge | 172:65be27845400 | 1406 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1407 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1408 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1409 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT |
| AnnaBridge | 172:65be27845400 | 1410 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT |
| AnnaBridge | 172:65be27845400 | 1411 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT |
| AnnaBridge | 172:65be27845400 | 1412 | * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT |
| AnnaBridge | 172:65be27845400 | 1413 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP |
| AnnaBridge | 172:65be27845400 | 1414 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP |
| AnnaBridge | 172:65be27845400 | 1415 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP |
| AnnaBridge | 172:65be27845400 | 1416 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1417 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP |
| AnnaBridge | 172:65be27845400 | 1418 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1419 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP |
| AnnaBridge | 172:65be27845400 | 1420 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP |
| AnnaBridge | 172:65be27845400 | 1421 | * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP |
| AnnaBridge | 172:65be27845400 | 1422 | * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP |
| AnnaBridge | 172:65be27845400 | 1423 | * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT |
| AnnaBridge | 172:65be27845400 | 1424 | * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT |
| AnnaBridge | 172:65be27845400 | 1425 | * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP |
| AnnaBridge | 172:65be27845400 | 1426 | * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1427 | * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2 |
| AnnaBridge | 172:65be27845400 | 1428 | * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT |
| AnnaBridge | 172:65be27845400 | 1429 | * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT |
| AnnaBridge | 172:65be27845400 | 1430 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT |
| AnnaBridge | 172:65be27845400 | 1431 | * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT |
| AnnaBridge | 172:65be27845400 | 1432 | * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT |
| AnnaBridge | 172:65be27845400 | 1433 | * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT |
| AnnaBridge | 172:65be27845400 | 1434 | * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT |
| AnnaBridge | 172:65be27845400 | 1435 | * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT |
| AnnaBridge | 172:65be27845400 | 1436 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1437 | */ |
| AnnaBridge | 172:65be27845400 | 1438 | __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) |
| AnnaBridge | 172:65be27845400 | 1439 | { |
| AnnaBridge | 172:65be27845400 | 1440 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1441 | |
| AnnaBridge | 172:65be27845400 | 1442 | MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); |
| AnnaBridge | 172:65be27845400 | 1443 | } |
| AnnaBridge | 172:65be27845400 | 1444 | |
| AnnaBridge | 172:65be27845400 | 1445 | /** |
| AnnaBridge | 172:65be27845400 | 1446 | * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. |
| AnnaBridge | 172:65be27845400 | 1447 | * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID |
| AnnaBridge | 172:65be27845400 | 1448 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1449 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1450 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 1451 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 1452 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 1453 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 1454 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 1455 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 1456 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 1457 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 1458 | * @retval Returned value can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 1459 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1460 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1461 | * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1462 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT |
| AnnaBridge | 172:65be27845400 | 1463 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1464 | * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1465 | * @arg @ref LL_DMAMUX1_SYNC_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1466 | * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO |
| AnnaBridge | 172:65be27845400 | 1467 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT |
| AnnaBridge | 172:65be27845400 | 1468 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT |
| AnnaBridge | 172:65be27845400 | 1469 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT |
| AnnaBridge | 172:65be27845400 | 1470 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT |
| AnnaBridge | 172:65be27845400 | 1471 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT |
| AnnaBridge | 172:65be27845400 | 1472 | * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT |
| AnnaBridge | 172:65be27845400 | 1473 | * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP |
| AnnaBridge | 172:65be27845400 | 1474 | * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP |
| AnnaBridge | 172:65be27845400 | 1475 | * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT |
| AnnaBridge | 172:65be27845400 | 1476 | * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT |
| AnnaBridge | 172:65be27845400 | 1477 | * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP |
| AnnaBridge | 172:65be27845400 | 1478 | * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP |
| AnnaBridge | 172:65be27845400 | 1479 | * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT |
| AnnaBridge | 172:65be27845400 | 1480 | * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP |
| AnnaBridge | 172:65be27845400 | 1481 | * @arg @ref LL_DMAMUX2_SYNC_EXTI0 |
| AnnaBridge | 172:65be27845400 | 1482 | * @arg @ref LL_DMAMUX2_SYNC_EXTI2 |
| AnnaBridge | 172:65be27845400 | 1483 | */ |
| AnnaBridge | 172:65be27845400 | 1484 | __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 1485 | { |
| AnnaBridge | 172:65be27845400 | 1486 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1487 | |
| AnnaBridge | 172:65be27845400 | 1488 | return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID)); |
| AnnaBridge | 172:65be27845400 | 1489 | } |
| AnnaBridge | 172:65be27845400 | 1490 | |
| AnnaBridge | 172:65be27845400 | 1491 | /** |
| AnnaBridge | 172:65be27845400 | 1492 | * @} |
| AnnaBridge | 172:65be27845400 | 1493 | */ |
| AnnaBridge | 172:65be27845400 | 1494 | |
| AnnaBridge | 172:65be27845400 | 1495 | /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management |
| AnnaBridge | 172:65be27845400 | 1496 | * @{ |
| AnnaBridge | 172:65be27845400 | 1497 | */ |
| AnnaBridge | 172:65be27845400 | 1498 | |
| AnnaBridge | 172:65be27845400 | 1499 | /** |
| AnnaBridge | 172:65be27845400 | 1500 | * @brief Get Synchronization Event Overrun Flag Channel 0. |
| AnnaBridge | 172:65be27845400 | 1501 | * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 |
| AnnaBridge | 172:65be27845400 | 1502 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1503 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1504 | */ |
| AnnaBridge | 172:65be27845400 | 1505 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1506 | { |
| AnnaBridge | 172:65be27845400 | 1507 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1508 | |
| AnnaBridge | 172:65be27845400 | 1509 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1510 | } |
| AnnaBridge | 172:65be27845400 | 1511 | |
| AnnaBridge | 172:65be27845400 | 1512 | /** |
| AnnaBridge | 172:65be27845400 | 1513 | * @brief Get Synchronization Event Overrun Flag Channel 1. |
| AnnaBridge | 172:65be27845400 | 1514 | * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 |
| AnnaBridge | 172:65be27845400 | 1515 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1516 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1517 | */ |
| AnnaBridge | 172:65be27845400 | 1518 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1519 | { |
| AnnaBridge | 172:65be27845400 | 1520 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1521 | |
| AnnaBridge | 172:65be27845400 | 1522 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1523 | } |
| AnnaBridge | 172:65be27845400 | 1524 | |
| AnnaBridge | 172:65be27845400 | 1525 | /** |
| AnnaBridge | 172:65be27845400 | 1526 | * @brief Get Synchronization Event Overrun Flag Channel 2. |
| AnnaBridge | 172:65be27845400 | 1527 | * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 |
| AnnaBridge | 172:65be27845400 | 1528 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1529 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1530 | */ |
| AnnaBridge | 172:65be27845400 | 1531 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1532 | { |
| AnnaBridge | 172:65be27845400 | 1533 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1534 | |
| AnnaBridge | 172:65be27845400 | 1535 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1536 | } |
| AnnaBridge | 172:65be27845400 | 1537 | |
| AnnaBridge | 172:65be27845400 | 1538 | /** |
| AnnaBridge | 172:65be27845400 | 1539 | * @brief Get Synchronization Event Overrun Flag Channel 3. |
| AnnaBridge | 172:65be27845400 | 1540 | * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 |
| AnnaBridge | 172:65be27845400 | 1541 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1542 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1543 | */ |
| AnnaBridge | 172:65be27845400 | 1544 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1545 | { |
| AnnaBridge | 172:65be27845400 | 1546 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1547 | |
| AnnaBridge | 172:65be27845400 | 1548 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1549 | } |
| AnnaBridge | 172:65be27845400 | 1550 | |
| AnnaBridge | 172:65be27845400 | 1551 | /** |
| AnnaBridge | 172:65be27845400 | 1552 | * @brief Get Synchronization Event Overrun Flag Channel 4. |
| AnnaBridge | 172:65be27845400 | 1553 | * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 |
| AnnaBridge | 172:65be27845400 | 1554 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1555 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1556 | */ |
| AnnaBridge | 172:65be27845400 | 1557 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1558 | { |
| AnnaBridge | 172:65be27845400 | 1559 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1560 | |
| AnnaBridge | 172:65be27845400 | 1561 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1562 | } |
| AnnaBridge | 172:65be27845400 | 1563 | |
| AnnaBridge | 172:65be27845400 | 1564 | /** |
| AnnaBridge | 172:65be27845400 | 1565 | * @brief Get Synchronization Event Overrun Flag Channel 5. |
| AnnaBridge | 172:65be27845400 | 1566 | * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 |
| AnnaBridge | 172:65be27845400 | 1567 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1568 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1569 | */ |
| AnnaBridge | 172:65be27845400 | 1570 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1571 | { |
| AnnaBridge | 172:65be27845400 | 1572 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1573 | |
| AnnaBridge | 172:65be27845400 | 1574 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1575 | } |
| AnnaBridge | 172:65be27845400 | 1576 | |
| AnnaBridge | 172:65be27845400 | 1577 | /** |
| AnnaBridge | 172:65be27845400 | 1578 | * @brief Get Synchronization Event Overrun Flag Channel 6. |
| AnnaBridge | 172:65be27845400 | 1579 | * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 |
| AnnaBridge | 172:65be27845400 | 1580 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1581 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1582 | */ |
| AnnaBridge | 172:65be27845400 | 1583 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1584 | { |
| AnnaBridge | 172:65be27845400 | 1585 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1586 | |
| AnnaBridge | 172:65be27845400 | 1587 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1588 | } |
| AnnaBridge | 172:65be27845400 | 1589 | |
| AnnaBridge | 172:65be27845400 | 1590 | /** |
| AnnaBridge | 172:65be27845400 | 1591 | * @brief Get Synchronization Event Overrun Flag Channel 7. |
| AnnaBridge | 172:65be27845400 | 1592 | * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 |
| AnnaBridge | 172:65be27845400 | 1593 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1594 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1595 | */ |
| AnnaBridge | 172:65be27845400 | 1596 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1597 | { |
| AnnaBridge | 172:65be27845400 | 1598 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1599 | |
| AnnaBridge | 172:65be27845400 | 1600 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1601 | } |
| AnnaBridge | 172:65be27845400 | 1602 | |
| AnnaBridge | 172:65be27845400 | 1603 | /** |
| AnnaBridge | 172:65be27845400 | 1604 | * @brief Get Synchronization Event Overrun Flag Channel 8. |
| AnnaBridge | 172:65be27845400 | 1605 | * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 |
| AnnaBridge | 172:65be27845400 | 1606 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1607 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1608 | */ |
| AnnaBridge | 172:65be27845400 | 1609 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1610 | { |
| AnnaBridge | 172:65be27845400 | 1611 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1612 | |
| AnnaBridge | 172:65be27845400 | 1613 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1614 | } |
| AnnaBridge | 172:65be27845400 | 1615 | |
| AnnaBridge | 172:65be27845400 | 1616 | /** |
| AnnaBridge | 172:65be27845400 | 1617 | * @brief Get Synchronization Event Overrun Flag Channel 9. |
| AnnaBridge | 172:65be27845400 | 1618 | * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 |
| AnnaBridge | 172:65be27845400 | 1619 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1620 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1621 | */ |
| AnnaBridge | 172:65be27845400 | 1622 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1623 | { |
| AnnaBridge | 172:65be27845400 | 1624 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1625 | |
| AnnaBridge | 172:65be27845400 | 1626 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1627 | } |
| AnnaBridge | 172:65be27845400 | 1628 | |
| AnnaBridge | 172:65be27845400 | 1629 | /** |
| AnnaBridge | 172:65be27845400 | 1630 | * @brief Get Synchronization Event Overrun Flag Channel 10. |
| AnnaBridge | 172:65be27845400 | 1631 | * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 |
| AnnaBridge | 172:65be27845400 | 1632 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1633 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1634 | */ |
| AnnaBridge | 172:65be27845400 | 1635 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1636 | { |
| AnnaBridge | 172:65be27845400 | 1637 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1638 | |
| AnnaBridge | 172:65be27845400 | 1639 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1640 | } |
| AnnaBridge | 172:65be27845400 | 1641 | |
| AnnaBridge | 172:65be27845400 | 1642 | /** |
| AnnaBridge | 172:65be27845400 | 1643 | * @brief Get Synchronization Event Overrun Flag Channel 11. |
| AnnaBridge | 172:65be27845400 | 1644 | * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 |
| AnnaBridge | 172:65be27845400 | 1645 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1646 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1647 | */ |
| AnnaBridge | 172:65be27845400 | 1648 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1649 | { |
| AnnaBridge | 172:65be27845400 | 1650 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1651 | |
| AnnaBridge | 172:65be27845400 | 1652 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1653 | } |
| AnnaBridge | 172:65be27845400 | 1654 | |
| AnnaBridge | 172:65be27845400 | 1655 | /** |
| AnnaBridge | 172:65be27845400 | 1656 | * @brief Get Synchronization Event Overrun Flag Channel 12. |
| AnnaBridge | 172:65be27845400 | 1657 | * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 |
| AnnaBridge | 172:65be27845400 | 1658 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1659 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1660 | */ |
| AnnaBridge | 172:65be27845400 | 1661 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1662 | { |
| AnnaBridge | 172:65be27845400 | 1663 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1664 | |
| AnnaBridge | 172:65be27845400 | 1665 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1666 | } |
| AnnaBridge | 172:65be27845400 | 1667 | |
| AnnaBridge | 172:65be27845400 | 1668 | /** |
| AnnaBridge | 172:65be27845400 | 1669 | * @brief Get Synchronization Event Overrun Flag Channel 13. |
| AnnaBridge | 172:65be27845400 | 1670 | * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 |
| AnnaBridge | 172:65be27845400 | 1671 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1672 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1673 | */ |
| AnnaBridge | 172:65be27845400 | 1674 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1675 | { |
| AnnaBridge | 172:65be27845400 | 1676 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1677 | |
| AnnaBridge | 172:65be27845400 | 1678 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1679 | } |
| AnnaBridge | 172:65be27845400 | 1680 | |
| AnnaBridge | 172:65be27845400 | 1681 | /** |
| AnnaBridge | 172:65be27845400 | 1682 | * @brief Get Synchronization Event Overrun Flag Channel 14. |
| AnnaBridge | 172:65be27845400 | 1683 | * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14 |
| AnnaBridge | 172:65be27845400 | 1684 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1685 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1686 | */ |
| AnnaBridge | 172:65be27845400 | 1687 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1688 | { |
| AnnaBridge | 172:65be27845400 | 1689 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1690 | |
| AnnaBridge | 172:65be27845400 | 1691 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1692 | } |
| AnnaBridge | 172:65be27845400 | 1693 | |
| AnnaBridge | 172:65be27845400 | 1694 | /** |
| AnnaBridge | 172:65be27845400 | 1695 | * @brief Get Synchronization Event Overrun Flag Channel 15. |
| AnnaBridge | 172:65be27845400 | 1696 | * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15 |
| AnnaBridge | 172:65be27845400 | 1697 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1698 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1699 | */ |
| AnnaBridge | 172:65be27845400 | 1700 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1701 | { |
| AnnaBridge | 172:65be27845400 | 1702 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1703 | |
| AnnaBridge | 172:65be27845400 | 1704 | return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1705 | } |
| AnnaBridge | 172:65be27845400 | 1706 | |
| AnnaBridge | 172:65be27845400 | 1707 | /** |
| AnnaBridge | 172:65be27845400 | 1708 | * @brief Get Request Generator 0 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1709 | * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 |
| AnnaBridge | 172:65be27845400 | 1710 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1711 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1712 | */ |
| AnnaBridge | 172:65be27845400 | 1713 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1714 | { |
| AnnaBridge | 172:65be27845400 | 1715 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1716 | |
| AnnaBridge | 172:65be27845400 | 1717 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1718 | } |
| AnnaBridge | 172:65be27845400 | 1719 | |
| AnnaBridge | 172:65be27845400 | 1720 | /** |
| AnnaBridge | 172:65be27845400 | 1721 | * @brief Get Request Generator 1 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1722 | * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 |
| AnnaBridge | 172:65be27845400 | 1723 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1724 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1725 | */ |
| AnnaBridge | 172:65be27845400 | 1726 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1727 | { |
| AnnaBridge | 172:65be27845400 | 1728 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1729 | |
| AnnaBridge | 172:65be27845400 | 1730 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1731 | } |
| AnnaBridge | 172:65be27845400 | 1732 | |
| AnnaBridge | 172:65be27845400 | 1733 | /** |
| AnnaBridge | 172:65be27845400 | 1734 | * @brief Get Request Generator 2 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1735 | * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 |
| AnnaBridge | 172:65be27845400 | 1736 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1737 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1738 | */ |
| AnnaBridge | 172:65be27845400 | 1739 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1740 | { |
| AnnaBridge | 172:65be27845400 | 1741 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1742 | |
| AnnaBridge | 172:65be27845400 | 1743 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1744 | } |
| AnnaBridge | 172:65be27845400 | 1745 | |
| AnnaBridge | 172:65be27845400 | 1746 | /** |
| AnnaBridge | 172:65be27845400 | 1747 | * @brief Get Request Generator 3 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1748 | * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 |
| AnnaBridge | 172:65be27845400 | 1749 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1750 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1751 | */ |
| AnnaBridge | 172:65be27845400 | 1752 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1753 | { |
| AnnaBridge | 172:65be27845400 | 1754 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1755 | |
| AnnaBridge | 172:65be27845400 | 1756 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1757 | } |
| AnnaBridge | 172:65be27845400 | 1758 | |
| AnnaBridge | 172:65be27845400 | 1759 | /** |
| AnnaBridge | 172:65be27845400 | 1760 | * @brief Get Request Generator 4 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1761 | * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4 |
| AnnaBridge | 172:65be27845400 | 1762 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1763 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1764 | */ |
| AnnaBridge | 172:65be27845400 | 1765 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1766 | { |
| AnnaBridge | 172:65be27845400 | 1767 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1768 | |
| AnnaBridge | 172:65be27845400 | 1769 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1770 | } |
| AnnaBridge | 172:65be27845400 | 1771 | |
| AnnaBridge | 172:65be27845400 | 1772 | /** |
| AnnaBridge | 172:65be27845400 | 1773 | * @brief Get Request Generator 5 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1774 | * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5 |
| AnnaBridge | 172:65be27845400 | 1775 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1776 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1777 | */ |
| AnnaBridge | 172:65be27845400 | 1778 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1779 | { |
| AnnaBridge | 172:65be27845400 | 1780 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1781 | |
| AnnaBridge | 172:65be27845400 | 1782 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1783 | } |
| AnnaBridge | 172:65be27845400 | 1784 | |
| AnnaBridge | 172:65be27845400 | 1785 | /** |
| AnnaBridge | 172:65be27845400 | 1786 | * @brief Get Request Generator 6 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1787 | * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6 |
| AnnaBridge | 172:65be27845400 | 1788 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1789 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1790 | */ |
| AnnaBridge | 172:65be27845400 | 1791 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1792 | { |
| AnnaBridge | 172:65be27845400 | 1793 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1794 | |
| AnnaBridge | 172:65be27845400 | 1795 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1796 | } |
| AnnaBridge | 172:65be27845400 | 1797 | |
| AnnaBridge | 172:65be27845400 | 1798 | /** |
| AnnaBridge | 172:65be27845400 | 1799 | * @brief Get Request Generator 7 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 1800 | * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7 |
| AnnaBridge | 172:65be27845400 | 1801 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1802 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 1803 | */ |
| AnnaBridge | 172:65be27845400 | 1804 | __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1805 | { |
| AnnaBridge | 172:65be27845400 | 1806 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1807 | |
| AnnaBridge | 172:65be27845400 | 1808 | return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 1809 | } |
| AnnaBridge | 172:65be27845400 | 1810 | |
| AnnaBridge | 172:65be27845400 | 1811 | /** |
| AnnaBridge | 172:65be27845400 | 1812 | * @brief Clear Synchronization Event Overrun Flag Channel 0. |
| AnnaBridge | 172:65be27845400 | 1813 | * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 |
| AnnaBridge | 172:65be27845400 | 1814 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1815 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1816 | */ |
| AnnaBridge | 172:65be27845400 | 1817 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1818 | { |
| AnnaBridge | 172:65be27845400 | 1819 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1820 | |
| AnnaBridge | 172:65be27845400 | 1821 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0); |
| AnnaBridge | 172:65be27845400 | 1822 | } |
| AnnaBridge | 172:65be27845400 | 1823 | |
| AnnaBridge | 172:65be27845400 | 1824 | /** |
| AnnaBridge | 172:65be27845400 | 1825 | * @brief Clear Synchronization Event Overrun Flag Channel 1. |
| AnnaBridge | 172:65be27845400 | 1826 | * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 |
| AnnaBridge | 172:65be27845400 | 1827 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1828 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1829 | */ |
| AnnaBridge | 172:65be27845400 | 1830 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1831 | { |
| AnnaBridge | 172:65be27845400 | 1832 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1833 | |
| AnnaBridge | 172:65be27845400 | 1834 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1); |
| AnnaBridge | 172:65be27845400 | 1835 | } |
| AnnaBridge | 172:65be27845400 | 1836 | |
| AnnaBridge | 172:65be27845400 | 1837 | /** |
| AnnaBridge | 172:65be27845400 | 1838 | * @brief Clear Synchronization Event Overrun Flag Channel 2. |
| AnnaBridge | 172:65be27845400 | 1839 | * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 |
| AnnaBridge | 172:65be27845400 | 1840 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1841 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1842 | */ |
| AnnaBridge | 172:65be27845400 | 1843 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1844 | { |
| AnnaBridge | 172:65be27845400 | 1845 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1846 | |
| AnnaBridge | 172:65be27845400 | 1847 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2); |
| AnnaBridge | 172:65be27845400 | 1848 | } |
| AnnaBridge | 172:65be27845400 | 1849 | |
| AnnaBridge | 172:65be27845400 | 1850 | /** |
| AnnaBridge | 172:65be27845400 | 1851 | * @brief Clear Synchronization Event Overrun Flag Channel 3. |
| AnnaBridge | 172:65be27845400 | 1852 | * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 |
| AnnaBridge | 172:65be27845400 | 1853 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1854 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1855 | */ |
| AnnaBridge | 172:65be27845400 | 1856 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1857 | { |
| AnnaBridge | 172:65be27845400 | 1858 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1859 | |
| AnnaBridge | 172:65be27845400 | 1860 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3); |
| AnnaBridge | 172:65be27845400 | 1861 | } |
| AnnaBridge | 172:65be27845400 | 1862 | |
| AnnaBridge | 172:65be27845400 | 1863 | /** |
| AnnaBridge | 172:65be27845400 | 1864 | * @brief Clear Synchronization Event Overrun Flag Channel 4. |
| AnnaBridge | 172:65be27845400 | 1865 | * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 |
| AnnaBridge | 172:65be27845400 | 1866 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1867 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1868 | */ |
| AnnaBridge | 172:65be27845400 | 1869 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1870 | { |
| AnnaBridge | 172:65be27845400 | 1871 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1872 | |
| AnnaBridge | 172:65be27845400 | 1873 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4); |
| AnnaBridge | 172:65be27845400 | 1874 | } |
| AnnaBridge | 172:65be27845400 | 1875 | |
| AnnaBridge | 172:65be27845400 | 1876 | /** |
| AnnaBridge | 172:65be27845400 | 1877 | * @brief Clear Synchronization Event Overrun Flag Channel 5. |
| AnnaBridge | 172:65be27845400 | 1878 | * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 |
| AnnaBridge | 172:65be27845400 | 1879 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1880 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1881 | */ |
| AnnaBridge | 172:65be27845400 | 1882 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1883 | { |
| AnnaBridge | 172:65be27845400 | 1884 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1885 | |
| AnnaBridge | 172:65be27845400 | 1886 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5); |
| AnnaBridge | 172:65be27845400 | 1887 | } |
| AnnaBridge | 172:65be27845400 | 1888 | |
| AnnaBridge | 172:65be27845400 | 1889 | /** |
| AnnaBridge | 172:65be27845400 | 1890 | * @brief Clear Synchronization Event Overrun Flag Channel 6. |
| AnnaBridge | 172:65be27845400 | 1891 | * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 |
| AnnaBridge | 172:65be27845400 | 1892 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1893 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1894 | */ |
| AnnaBridge | 172:65be27845400 | 1895 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1896 | { |
| AnnaBridge | 172:65be27845400 | 1897 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1898 | |
| AnnaBridge | 172:65be27845400 | 1899 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6); |
| AnnaBridge | 172:65be27845400 | 1900 | } |
| AnnaBridge | 172:65be27845400 | 1901 | |
| AnnaBridge | 172:65be27845400 | 1902 | /** |
| AnnaBridge | 172:65be27845400 | 1903 | * @brief Clear Synchronization Event Overrun Flag Channel 7. |
| AnnaBridge | 172:65be27845400 | 1904 | * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 |
| AnnaBridge | 172:65be27845400 | 1905 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1906 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1907 | */ |
| AnnaBridge | 172:65be27845400 | 1908 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1909 | { |
| AnnaBridge | 172:65be27845400 | 1910 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1911 | |
| AnnaBridge | 172:65be27845400 | 1912 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7); |
| AnnaBridge | 172:65be27845400 | 1913 | } |
| AnnaBridge | 172:65be27845400 | 1914 | |
| AnnaBridge | 172:65be27845400 | 1915 | /** |
| AnnaBridge | 172:65be27845400 | 1916 | * @brief Clear Synchronization Event Overrun Flag Channel 8. |
| AnnaBridge | 172:65be27845400 | 1917 | * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 |
| AnnaBridge | 172:65be27845400 | 1918 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1919 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1920 | */ |
| AnnaBridge | 172:65be27845400 | 1921 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1922 | { |
| AnnaBridge | 172:65be27845400 | 1923 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1924 | |
| AnnaBridge | 172:65be27845400 | 1925 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8); |
| AnnaBridge | 172:65be27845400 | 1926 | } |
| AnnaBridge | 172:65be27845400 | 1927 | |
| AnnaBridge | 172:65be27845400 | 1928 | /** |
| AnnaBridge | 172:65be27845400 | 1929 | * @brief Clear Synchronization Event Overrun Flag Channel 9. |
| AnnaBridge | 172:65be27845400 | 1930 | * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 |
| AnnaBridge | 172:65be27845400 | 1931 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1932 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1933 | */ |
| AnnaBridge | 172:65be27845400 | 1934 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1935 | { |
| AnnaBridge | 172:65be27845400 | 1936 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1937 | |
| AnnaBridge | 172:65be27845400 | 1938 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9); |
| AnnaBridge | 172:65be27845400 | 1939 | } |
| AnnaBridge | 172:65be27845400 | 1940 | |
| AnnaBridge | 172:65be27845400 | 1941 | /** |
| AnnaBridge | 172:65be27845400 | 1942 | * @brief Clear Synchronization Event Overrun Flag Channel 10. |
| AnnaBridge | 172:65be27845400 | 1943 | * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 |
| AnnaBridge | 172:65be27845400 | 1944 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1945 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1946 | */ |
| AnnaBridge | 172:65be27845400 | 1947 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1948 | { |
| AnnaBridge | 172:65be27845400 | 1949 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1950 | |
| AnnaBridge | 172:65be27845400 | 1951 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10); |
| AnnaBridge | 172:65be27845400 | 1952 | } |
| AnnaBridge | 172:65be27845400 | 1953 | |
| AnnaBridge | 172:65be27845400 | 1954 | /** |
| AnnaBridge | 172:65be27845400 | 1955 | * @brief Clear Synchronization Event Overrun Flag Channel 11. |
| AnnaBridge | 172:65be27845400 | 1956 | * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 |
| AnnaBridge | 172:65be27845400 | 1957 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1958 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1959 | */ |
| AnnaBridge | 172:65be27845400 | 1960 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1961 | { |
| AnnaBridge | 172:65be27845400 | 1962 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1963 | |
| AnnaBridge | 172:65be27845400 | 1964 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11); |
| AnnaBridge | 172:65be27845400 | 1965 | } |
| AnnaBridge | 172:65be27845400 | 1966 | |
| AnnaBridge | 172:65be27845400 | 1967 | /** |
| AnnaBridge | 172:65be27845400 | 1968 | * @brief Clear Synchronization Event Overrun Flag Channel 12. |
| AnnaBridge | 172:65be27845400 | 1969 | * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 |
| AnnaBridge | 172:65be27845400 | 1970 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1971 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1972 | */ |
| AnnaBridge | 172:65be27845400 | 1973 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1974 | { |
| AnnaBridge | 172:65be27845400 | 1975 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1976 | |
| AnnaBridge | 172:65be27845400 | 1977 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12); |
| AnnaBridge | 172:65be27845400 | 1978 | } |
| AnnaBridge | 172:65be27845400 | 1979 | |
| AnnaBridge | 172:65be27845400 | 1980 | /** |
| AnnaBridge | 172:65be27845400 | 1981 | * @brief Clear Synchronization Event Overrun Flag Channel 13. |
| AnnaBridge | 172:65be27845400 | 1982 | * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 |
| AnnaBridge | 172:65be27845400 | 1983 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1984 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1985 | */ |
| AnnaBridge | 172:65be27845400 | 1986 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 1987 | { |
| AnnaBridge | 172:65be27845400 | 1988 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 1989 | |
| AnnaBridge | 172:65be27845400 | 1990 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13); |
| AnnaBridge | 172:65be27845400 | 1991 | } |
| AnnaBridge | 172:65be27845400 | 1992 | |
| AnnaBridge | 172:65be27845400 | 1993 | /** |
| AnnaBridge | 172:65be27845400 | 1994 | * @brief Clear Synchronization Event Overrun Flag Channel 14. |
| AnnaBridge | 172:65be27845400 | 1995 | * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14 |
| AnnaBridge | 172:65be27845400 | 1996 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 1997 | * @retval None |
| AnnaBridge | 172:65be27845400 | 1998 | */ |
| AnnaBridge | 172:65be27845400 | 1999 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2000 | { |
| AnnaBridge | 172:65be27845400 | 2001 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2002 | |
| AnnaBridge | 172:65be27845400 | 2003 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14); |
| AnnaBridge | 172:65be27845400 | 2004 | } |
| AnnaBridge | 172:65be27845400 | 2005 | |
| AnnaBridge | 172:65be27845400 | 2006 | /** |
| AnnaBridge | 172:65be27845400 | 2007 | * @brief Clear Synchronization Event Overrun Flag Channel 15. |
| AnnaBridge | 172:65be27845400 | 2008 | * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15 |
| AnnaBridge | 172:65be27845400 | 2009 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2010 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2011 | */ |
| AnnaBridge | 172:65be27845400 | 2012 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2013 | { |
| AnnaBridge | 172:65be27845400 | 2014 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2015 | |
| AnnaBridge | 172:65be27845400 | 2016 | SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15); |
| AnnaBridge | 172:65be27845400 | 2017 | } |
| AnnaBridge | 172:65be27845400 | 2018 | |
| AnnaBridge | 172:65be27845400 | 2019 | /** |
| AnnaBridge | 172:65be27845400 | 2020 | * @brief Clear Request Generator 0 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2021 | * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 |
| AnnaBridge | 172:65be27845400 | 2022 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2023 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2024 | */ |
| AnnaBridge | 172:65be27845400 | 2025 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2026 | { |
| AnnaBridge | 172:65be27845400 | 2027 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2028 | |
| AnnaBridge | 172:65be27845400 | 2029 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0); |
| AnnaBridge | 172:65be27845400 | 2030 | } |
| AnnaBridge | 172:65be27845400 | 2031 | |
| AnnaBridge | 172:65be27845400 | 2032 | /** |
| AnnaBridge | 172:65be27845400 | 2033 | * @brief Clear Request Generator 1 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2034 | * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 |
| AnnaBridge | 172:65be27845400 | 2035 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2036 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2037 | */ |
| AnnaBridge | 172:65be27845400 | 2038 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2039 | { |
| AnnaBridge | 172:65be27845400 | 2040 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2041 | |
| AnnaBridge | 172:65be27845400 | 2042 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1); |
| AnnaBridge | 172:65be27845400 | 2043 | } |
| AnnaBridge | 172:65be27845400 | 2044 | |
| AnnaBridge | 172:65be27845400 | 2045 | /** |
| AnnaBridge | 172:65be27845400 | 2046 | * @brief Clear Request Generator 2 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2047 | * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 |
| AnnaBridge | 172:65be27845400 | 2048 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2049 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2050 | */ |
| AnnaBridge | 172:65be27845400 | 2051 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2052 | { |
| AnnaBridge | 172:65be27845400 | 2053 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2054 | |
| AnnaBridge | 172:65be27845400 | 2055 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2); |
| AnnaBridge | 172:65be27845400 | 2056 | } |
| AnnaBridge | 172:65be27845400 | 2057 | |
| AnnaBridge | 172:65be27845400 | 2058 | /** |
| AnnaBridge | 172:65be27845400 | 2059 | * @brief Clear Request Generator 3 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2060 | * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 |
| AnnaBridge | 172:65be27845400 | 2061 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2062 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2063 | */ |
| AnnaBridge | 172:65be27845400 | 2064 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2065 | { |
| AnnaBridge | 172:65be27845400 | 2066 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2067 | |
| AnnaBridge | 172:65be27845400 | 2068 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3); |
| AnnaBridge | 172:65be27845400 | 2069 | } |
| AnnaBridge | 172:65be27845400 | 2070 | |
| AnnaBridge | 172:65be27845400 | 2071 | /** |
| AnnaBridge | 172:65be27845400 | 2072 | * @brief Clear Request Generator 4 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2073 | * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4 |
| AnnaBridge | 172:65be27845400 | 2074 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2075 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2076 | */ |
| AnnaBridge | 172:65be27845400 | 2077 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2078 | { |
| AnnaBridge | 172:65be27845400 | 2079 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2080 | |
| AnnaBridge | 172:65be27845400 | 2081 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4); |
| AnnaBridge | 172:65be27845400 | 2082 | } |
| AnnaBridge | 172:65be27845400 | 2083 | |
| AnnaBridge | 172:65be27845400 | 2084 | /** |
| AnnaBridge | 172:65be27845400 | 2085 | * @brief Clear Request Generator 5 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2086 | * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5 |
| AnnaBridge | 172:65be27845400 | 2087 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2088 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2089 | */ |
| AnnaBridge | 172:65be27845400 | 2090 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2091 | { |
| AnnaBridge | 172:65be27845400 | 2092 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2093 | |
| AnnaBridge | 172:65be27845400 | 2094 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5); |
| AnnaBridge | 172:65be27845400 | 2095 | } |
| AnnaBridge | 172:65be27845400 | 2096 | |
| AnnaBridge | 172:65be27845400 | 2097 | /** |
| AnnaBridge | 172:65be27845400 | 2098 | * @brief Clear Request Generator 6 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2099 | * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6 |
| AnnaBridge | 172:65be27845400 | 2100 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2101 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2102 | */ |
| AnnaBridge | 172:65be27845400 | 2103 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2104 | { |
| AnnaBridge | 172:65be27845400 | 2105 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2106 | |
| AnnaBridge | 172:65be27845400 | 2107 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6); |
| AnnaBridge | 172:65be27845400 | 2108 | } |
| AnnaBridge | 172:65be27845400 | 2109 | |
| AnnaBridge | 172:65be27845400 | 2110 | /** |
| AnnaBridge | 172:65be27845400 | 2111 | * @brief Clear Request Generator 7 Trigger Event Overrun Flag. |
| AnnaBridge | 172:65be27845400 | 2112 | * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7 |
| AnnaBridge | 172:65be27845400 | 2113 | * @param DMAMUXx DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2114 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2115 | */ |
| AnnaBridge | 172:65be27845400 | 2116 | __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) |
| AnnaBridge | 172:65be27845400 | 2117 | { |
| AnnaBridge | 172:65be27845400 | 2118 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2119 | |
| AnnaBridge | 172:65be27845400 | 2120 | SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7); |
| AnnaBridge | 172:65be27845400 | 2121 | } |
| AnnaBridge | 172:65be27845400 | 2122 | |
| AnnaBridge | 172:65be27845400 | 2123 | /** |
| AnnaBridge | 172:65be27845400 | 2124 | * @} |
| AnnaBridge | 172:65be27845400 | 2125 | */ |
| AnnaBridge | 172:65be27845400 | 2126 | |
| AnnaBridge | 172:65be27845400 | 2127 | /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management |
| AnnaBridge | 172:65be27845400 | 2128 | * @{ |
| AnnaBridge | 172:65be27845400 | 2129 | */ |
| AnnaBridge | 172:65be27845400 | 2130 | |
| AnnaBridge | 172:65be27845400 | 2131 | /** |
| AnnaBridge | 172:65be27845400 | 2132 | * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. |
| AnnaBridge | 172:65be27845400 | 2133 | * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO |
| AnnaBridge | 172:65be27845400 | 2134 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2135 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 2136 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 2137 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 2138 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 2139 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 2140 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 2141 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 2142 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 2143 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 2144 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 2145 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 2146 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 2147 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 2148 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 2149 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 2150 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 2151 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 2152 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2153 | */ |
| AnnaBridge | 172:65be27845400 | 2154 | __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 2155 | { |
| AnnaBridge | 172:65be27845400 | 2156 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2157 | |
| AnnaBridge | 172:65be27845400 | 2158 | SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); |
| AnnaBridge | 172:65be27845400 | 2159 | } |
| AnnaBridge | 172:65be27845400 | 2160 | |
| AnnaBridge | 172:65be27845400 | 2161 | /** |
| AnnaBridge | 172:65be27845400 | 2162 | * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. |
| AnnaBridge | 172:65be27845400 | 2163 | * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO |
| AnnaBridge | 172:65be27845400 | 2164 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2165 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 2166 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 2167 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 2168 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 2169 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 2170 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 2171 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 2172 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 2173 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 2174 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 2175 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 2176 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 2177 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 2178 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 2179 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 2180 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 2181 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 2182 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2183 | */ |
| AnnaBridge | 172:65be27845400 | 2184 | __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 2185 | { |
| AnnaBridge | 172:65be27845400 | 2186 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2187 | |
| AnnaBridge | 172:65be27845400 | 2188 | CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); |
| AnnaBridge | 172:65be27845400 | 2189 | } |
| AnnaBridge | 172:65be27845400 | 2190 | |
| AnnaBridge | 172:65be27845400 | 2191 | /** |
| AnnaBridge | 172:65be27845400 | 2192 | * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. |
| AnnaBridge | 172:65be27845400 | 2193 | * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO |
| AnnaBridge | 172:65be27845400 | 2194 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2195 | * @param Channel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 2196 | * @arg @ref LL_DMAMUX_CHANNEL_0 |
| AnnaBridge | 172:65be27845400 | 2197 | * @arg @ref LL_DMAMUX_CHANNEL_1 |
| AnnaBridge | 172:65be27845400 | 2198 | * @arg @ref LL_DMAMUX_CHANNEL_2 |
| AnnaBridge | 172:65be27845400 | 2199 | * @arg @ref LL_DMAMUX_CHANNEL_3 |
| AnnaBridge | 172:65be27845400 | 2200 | * @arg @ref LL_DMAMUX_CHANNEL_4 |
| AnnaBridge | 172:65be27845400 | 2201 | * @arg @ref LL_DMAMUX_CHANNEL_5 |
| AnnaBridge | 172:65be27845400 | 2202 | * @arg @ref LL_DMAMUX_CHANNEL_6 |
| AnnaBridge | 172:65be27845400 | 2203 | * @arg @ref LL_DMAMUX_CHANNEL_7 |
| AnnaBridge | 172:65be27845400 | 2204 | * @arg @ref LL_DMAMUX_CHANNEL_8 |
| AnnaBridge | 172:65be27845400 | 2205 | * @arg @ref LL_DMAMUX_CHANNEL_9 |
| AnnaBridge | 172:65be27845400 | 2206 | * @arg @ref LL_DMAMUX_CHANNEL_10 |
| AnnaBridge | 172:65be27845400 | 2207 | * @arg @ref LL_DMAMUX_CHANNEL_11 |
| AnnaBridge | 172:65be27845400 | 2208 | * @arg @ref LL_DMAMUX_CHANNEL_12 |
| AnnaBridge | 172:65be27845400 | 2209 | * @arg @ref LL_DMAMUX_CHANNEL_13 |
| AnnaBridge | 172:65be27845400 | 2210 | * @arg @ref LL_DMAMUX_CHANNEL_14 |
| AnnaBridge | 172:65be27845400 | 2211 | * @arg @ref LL_DMAMUX_CHANNEL_15 |
| AnnaBridge | 172:65be27845400 | 2212 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 2213 | */ |
| AnnaBridge | 172:65be27845400 | 2214 | __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) |
| AnnaBridge | 172:65be27845400 | 2215 | { |
| AnnaBridge | 172:65be27845400 | 2216 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2217 | |
| AnnaBridge | 172:65be27845400 | 2218 | return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE)); |
| AnnaBridge | 172:65be27845400 | 2219 | } |
| AnnaBridge | 172:65be27845400 | 2220 | |
| AnnaBridge | 172:65be27845400 | 2221 | /** |
| AnnaBridge | 172:65be27845400 | 2222 | * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. |
| AnnaBridge | 172:65be27845400 | 2223 | * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO |
| AnnaBridge | 172:65be27845400 | 2224 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2225 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 2226 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 2227 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 2228 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 2229 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 2230 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 2231 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 2232 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 2233 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 2234 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2235 | */ |
| AnnaBridge | 172:65be27845400 | 2236 | __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 2237 | { |
| AnnaBridge | 172:65be27845400 | 2238 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2239 | |
| AnnaBridge | 172:65be27845400 | 2240 | SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); |
| AnnaBridge | 172:65be27845400 | 2241 | } |
| AnnaBridge | 172:65be27845400 | 2242 | |
| AnnaBridge | 172:65be27845400 | 2243 | /** |
| AnnaBridge | 172:65be27845400 | 2244 | * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. |
| AnnaBridge | 172:65be27845400 | 2245 | * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO |
| AnnaBridge | 172:65be27845400 | 2246 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2247 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 2248 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 2249 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 2250 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 2251 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 2252 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 2253 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 2254 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 2255 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 2256 | * @retval None |
| AnnaBridge | 172:65be27845400 | 2257 | */ |
| AnnaBridge | 172:65be27845400 | 2258 | __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 2259 | { |
| AnnaBridge | 172:65be27845400 | 2260 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2261 | |
| AnnaBridge | 172:65be27845400 | 2262 | CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); |
| AnnaBridge | 172:65be27845400 | 2263 | } |
| AnnaBridge | 172:65be27845400 | 2264 | |
| AnnaBridge | 172:65be27845400 | 2265 | /** |
| AnnaBridge | 172:65be27845400 | 2266 | * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. |
| AnnaBridge | 172:65be27845400 | 2267 | * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO |
| AnnaBridge | 172:65be27845400 | 2268 | * @param DMAMUXx DMAMUXx Instance |
| AnnaBridge | 172:65be27845400 | 2269 | * @param RequestGenChannel This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 2270 | * @arg @ref LL_DMAMUX_REQ_GEN_0 |
| AnnaBridge | 172:65be27845400 | 2271 | * @arg @ref LL_DMAMUX_REQ_GEN_1 |
| AnnaBridge | 172:65be27845400 | 2272 | * @arg @ref LL_DMAMUX_REQ_GEN_2 |
| AnnaBridge | 172:65be27845400 | 2273 | * @arg @ref LL_DMAMUX_REQ_GEN_3 |
| AnnaBridge | 172:65be27845400 | 2274 | * @arg @ref LL_DMAMUX_REQ_GEN_4 |
| AnnaBridge | 172:65be27845400 | 2275 | * @arg @ref LL_DMAMUX_REQ_GEN_5 |
| AnnaBridge | 172:65be27845400 | 2276 | * @arg @ref LL_DMAMUX_REQ_GEN_6 |
| AnnaBridge | 172:65be27845400 | 2277 | * @arg @ref LL_DMAMUX_REQ_GEN_7 |
| AnnaBridge | 172:65be27845400 | 2278 | * @retval State of bit (1 or 0). |
| AnnaBridge | 172:65be27845400 | 2279 | */ |
| AnnaBridge | 172:65be27845400 | 2280 | __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) |
| AnnaBridge | 172:65be27845400 | 2281 | { |
| AnnaBridge | 172:65be27845400 | 2282 | register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; |
| AnnaBridge | 172:65be27845400 | 2283 | |
| AnnaBridge | 172:65be27845400 | 2284 | return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); |
| AnnaBridge | 172:65be27845400 | 2285 | } |
| AnnaBridge | 172:65be27845400 | 2286 | |
| AnnaBridge | 172:65be27845400 | 2287 | /** |
| AnnaBridge | 172:65be27845400 | 2288 | * @} |
| AnnaBridge | 172:65be27845400 | 2289 | */ |
| AnnaBridge | 172:65be27845400 | 2290 | |
| AnnaBridge | 172:65be27845400 | 2291 | /** |
| AnnaBridge | 172:65be27845400 | 2292 | * @} |
| AnnaBridge | 172:65be27845400 | 2293 | */ |
| AnnaBridge | 172:65be27845400 | 2294 | |
| AnnaBridge | 172:65be27845400 | 2295 | /** |
| AnnaBridge | 172:65be27845400 | 2296 | * @} |
| AnnaBridge | 172:65be27845400 | 2297 | */ |
| AnnaBridge | 172:65be27845400 | 2298 | |
| AnnaBridge | 172:65be27845400 | 2299 | #endif /* DMAMUX1 || DMAMUX2 */ |
| AnnaBridge | 172:65be27845400 | 2300 | |
| AnnaBridge | 172:65be27845400 | 2301 | /** |
| AnnaBridge | 172:65be27845400 | 2302 | * @} |
| AnnaBridge | 172:65be27845400 | 2303 | */ |
| AnnaBridge | 172:65be27845400 | 2304 | |
| AnnaBridge | 172:65be27845400 | 2305 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 2306 | } |
| AnnaBridge | 172:65be27845400 | 2307 | #endif |
| AnnaBridge | 172:65be27845400 | 2308 | |
| AnnaBridge | 172:65be27845400 | 2309 | #endif /* __STM32H7xx_LL_DMAMUX_H */ |
| AnnaBridge | 172:65be27845400 | 2310 | |
| AnnaBridge | 172:65be27845400 | 2311 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
