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TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_STD/stm32f2xx_ll_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f2xx_ll_spi.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.2.1
AnnaBridge	145:64910690c574	6	* @date 14-April-2017
AnnaBridge	145:64910690c574	7	* @brief Header file of SPI LL module.
AnnaBridge	145:64910690c574	8	******************************************************************************
AnnaBridge	145:64910690c574	9	* @attention
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	12	*
AnnaBridge	145:64910690c574	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	14	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	19	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	21	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	22	* without specific prior written permission.
AnnaBridge	145:64910690c574	23	*
AnnaBridge	145:64910690c574	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	34	*
AnnaBridge	145:64910690c574	35	******************************************************************************
AnnaBridge	145:64910690c574	36	*/
AnnaBridge	145:64910690c574	37
AnnaBridge	145:64910690c574	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	39	#ifndef __STM32F2xx_LL_SPI_H
AnnaBridge	145:64910690c574	40	#define __STM32F2xx_LL_SPI_H
AnnaBridge	145:64910690c574	41
AnnaBridge	145:64910690c574	42	#ifdef __cplusplus
AnnaBridge	145:64910690c574	43	extern "C" {
AnnaBridge	145:64910690c574	44	#endif
AnnaBridge	145:64910690c574	45
AnnaBridge	145:64910690c574	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	47	#include "stm32f2xx.h"
AnnaBridge	145:64910690c574	48
AnnaBridge	145:64910690c574	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	145:64910690c574	50	* @{
AnnaBridge	145:64910690c574	51	*/
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3)
AnnaBridge	145:64910690c574	54
AnnaBridge	145:64910690c574	55	/** @defgroup SPI_LL SPI
AnnaBridge	145:64910690c574	56	* @{
AnnaBridge	145:64910690c574	57	*/
AnnaBridge	145:64910690c574	58
AnnaBridge	145:64910690c574	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	61	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	62
AnnaBridge	145:64910690c574	63	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	64	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	65	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	145:64910690c574	66	* @{
AnnaBridge	145:64910690c574	67	*/
AnnaBridge	145:64910690c574	68
AnnaBridge	145:64910690c574	69	/**
AnnaBridge	145:64910690c574	70	* @brief SPI Init structures definition
AnnaBridge	145:64910690c574	71	*/
AnnaBridge	145:64910690c574	72	typedef struct
AnnaBridge	145:64910690c574	73	{
AnnaBridge	145:64910690c574	74	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	145:64910690c574	75	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	145:64910690c574	76
AnnaBridge	145:64910690c574	77	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	145:64910690c574	78
AnnaBridge	145:64910690c574	79	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	145:64910690c574	80	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	145:64910690c574	81
AnnaBridge	145:64910690c574	82	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	145:64910690c574	83
AnnaBridge	145:64910690c574	84	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	145:64910690c574	85	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	145:64910690c574	86
AnnaBridge	145:64910690c574	87	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	145:64910690c574	88
AnnaBridge	145:64910690c574	89	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	145:64910690c574	90	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	145:64910690c574	91
AnnaBridge	145:64910690c574	92	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	145:64910690c574	93
AnnaBridge	145:64910690c574	94	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	145:64910690c574	95	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	145:64910690c574	96
AnnaBridge	145:64910690c574	97	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	145:64910690c574	98
AnnaBridge	145:64910690c574	99	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	145:64910690c574	100	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	145:64910690c574	101
AnnaBridge	145:64910690c574	102	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	145:64910690c574	103
AnnaBridge	145:64910690c574	104	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	145:64910690c574	105	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	145:64910690c574	106	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	145:64910690c574	107
AnnaBridge	145:64910690c574	108	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	145:64910690c574	109
AnnaBridge	145:64910690c574	110	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	145:64910690c574	111	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	145:64910690c574	112
AnnaBridge	145:64910690c574	113	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	145:64910690c574	114
AnnaBridge	145:64910690c574	115	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	145:64910690c574	116	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	145:64910690c574	117
AnnaBridge	145:64910690c574	118	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	145:64910690c574	119
AnnaBridge	145:64910690c574	120	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	145:64910690c574	121	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	145:64910690c574	122
AnnaBridge	145:64910690c574	123	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	} LL_SPI_InitTypeDef;
AnnaBridge	145:64910690c574	126
AnnaBridge	145:64910690c574	127	/**
AnnaBridge	145:64910690c574	128	* @}
AnnaBridge	145:64910690c574	129	*/
AnnaBridge	145:64910690c574	130	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	131
AnnaBridge	145:64910690c574	132	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	133	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	145:64910690c574	134	* @{
AnnaBridge	145:64910690c574	135	*/
AnnaBridge	145:64910690c574	136
AnnaBridge	145:64910690c574	137	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	138	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	145:64910690c574	139	* @{
AnnaBridge	145:64910690c574	140	*/
AnnaBridge	145:64910690c574	141	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	145:64910690c574	142	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	145:64910690c574	143	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	145:64910690c574	144	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	145:64910690c574	145	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	145:64910690c574	146	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	145:64910690c574	147	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	145:64910690c574	148	/**
AnnaBridge	145:64910690c574	149	* @}
AnnaBridge	145:64910690c574	150	*/
AnnaBridge	145:64910690c574	151
AnnaBridge	145:64910690c574	152	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	153	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	145:64910690c574	154	* @{
AnnaBridge	145:64910690c574	155	*/
AnnaBridge	145:64910690c574	156	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	145:64910690c574	157	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	145:64910690c574	158	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	145:64910690c574	159	/**
AnnaBridge	145:64910690c574	160	* @}
AnnaBridge	145:64910690c574	161	*/
AnnaBridge	145:64910690c574	162
AnnaBridge	145:64910690c574	163	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	145:64910690c574	164	* @{
AnnaBridge	145:64910690c574	165	*/
AnnaBridge	145:64910690c574	166	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	145:64910690c574	167	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	145:64910690c574	168	/**
AnnaBridge	145:64910690c574	169	* @}
AnnaBridge	145:64910690c574	170	*/
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	145:64910690c574	173	* @{
AnnaBridge	145:64910690c574	174	*/
AnnaBridge	145:64910690c574	175	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	145:64910690c574	176	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	145:64910690c574	177	/**
AnnaBridge	145:64910690c574	178	* @}
AnnaBridge	145:64910690c574	179	*/
AnnaBridge	145:64910690c574	180
AnnaBridge	145:64910690c574	181	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	145:64910690c574	182	* @{
AnnaBridge	145:64910690c574	183	*/
AnnaBridge	145:64910690c574	184	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	145:64910690c574	185	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	145:64910690c574	186	/**
AnnaBridge	145:64910690c574	187	* @}
AnnaBridge	145:64910690c574	188	*/
AnnaBridge	145:64910690c574	189
AnnaBridge	145:64910690c574	190	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	145:64910690c574	191	* @{
AnnaBridge	145:64910690c574	192	*/
AnnaBridge	145:64910690c574	193	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	145:64910690c574	194	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	145:64910690c574	195	/**
AnnaBridge	145:64910690c574	196	* @}
AnnaBridge	145:64910690c574	197	*/
AnnaBridge	145:64910690c574	198
AnnaBridge	145:64910690c574	199	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	145:64910690c574	200	* @{
AnnaBridge	145:64910690c574	201	*/
AnnaBridge	145:64910690c574	202	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	145:64910690c574	203	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	145:64910690c574	204	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	145:64910690c574	205	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	145:64910690c574	206	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	145:64910690c574	207	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	145:64910690c574	208	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	145:64910690c574	209	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	145:64910690c574	210	/**
AnnaBridge	145:64910690c574	211	* @}
AnnaBridge	145:64910690c574	212	*/
AnnaBridge	145:64910690c574	213
AnnaBridge	145:64910690c574	214	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	145:64910690c574	215	* @{
AnnaBridge	145:64910690c574	216	*/
AnnaBridge	145:64910690c574	217	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	145:64910690c574	218	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	145:64910690c574	219	/**
AnnaBridge	145:64910690c574	220	* @}
AnnaBridge	145:64910690c574	221	*/
AnnaBridge	145:64910690c574	222
AnnaBridge	145:64910690c574	223	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	145:64910690c574	224	* @{
AnnaBridge	145:64910690c574	225	*/
AnnaBridge	145:64910690c574	226	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	145:64910690c574	227	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	145:64910690c574	228	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	145:64910690c574	229	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	145:64910690c574	230	/**
AnnaBridge	145:64910690c574	231	* @}
AnnaBridge	145:64910690c574	232	*/
AnnaBridge	145:64910690c574	233
AnnaBridge	145:64910690c574	234	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	145:64910690c574	235	* @{
AnnaBridge	145:64910690c574	236	*/
AnnaBridge	145:64910690c574	237	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	145:64910690c574	238	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	145:64910690c574	239	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	145:64910690c574	240	/**
AnnaBridge	145:64910690c574	241	* @}
AnnaBridge	145:64910690c574	242	*/
AnnaBridge	145:64910690c574	243
AnnaBridge	145:64910690c574	244	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	145:64910690c574	245	* @{
AnnaBridge	145:64910690c574	246	*/
AnnaBridge	145:64910690c574	247	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
AnnaBridge	145:64910690c574	248	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	145:64910690c574	249	/**
AnnaBridge	145:64910690c574	250	* @}
AnnaBridge	145:64910690c574	251	*/
AnnaBridge	145:64910690c574	252	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	253
AnnaBridge	145:64910690c574	254	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	145:64910690c574	255	* @{
AnnaBridge	145:64910690c574	256	*/
AnnaBridge	145:64910690c574	257	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	145:64910690c574	258	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	145:64910690c574	259	/**
AnnaBridge	145:64910690c574	260	* @}
AnnaBridge	145:64910690c574	261	*/
AnnaBridge	145:64910690c574	262	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	263
AnnaBridge	145:64910690c574	264	/**
AnnaBridge	145:64910690c574	265	* @}
AnnaBridge	145:64910690c574	266	*/
AnnaBridge	145:64910690c574	267
AnnaBridge	145:64910690c574	268	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	269	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	145:64910690c574	270	* @{
AnnaBridge	145:64910690c574	271	*/
AnnaBridge	145:64910690c574	272
AnnaBridge	145:64910690c574	273	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	274	* @{
AnnaBridge	145:64910690c574	275	*/
AnnaBridge	145:64910690c574	276
AnnaBridge	145:64910690c574	277	/**
AnnaBridge	145:64910690c574	278	* @brief Write a value in SPI register
AnnaBridge	145:64910690c574	279	* @param __INSTANCE__ SPI Instance
AnnaBridge	145:64910690c574	280	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	281	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	282	* @retval None
AnnaBridge	145:64910690c574	283	*/
AnnaBridge	145:64910690c574	284	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	285
AnnaBridge	145:64910690c574	286	/**
AnnaBridge	145:64910690c574	287	* @brief Read a value in SPI register
AnnaBridge	145:64910690c574	288	* @param __INSTANCE__ SPI Instance
AnnaBridge	145:64910690c574	289	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	290	* @retval Register value
AnnaBridge	145:64910690c574	291	*/
AnnaBridge	145:64910690c574	292	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	293	/**
AnnaBridge	145:64910690c574	294	* @}
AnnaBridge	145:64910690c574	295	*/
AnnaBridge	145:64910690c574	296
AnnaBridge	145:64910690c574	297	/**
AnnaBridge	145:64910690c574	298	* @}
AnnaBridge	145:64910690c574	299	*/
AnnaBridge	145:64910690c574	300
AnnaBridge	145:64910690c574	301	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	302	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	145:64910690c574	303	* @{
AnnaBridge	145:64910690c574	304	*/
AnnaBridge	145:64910690c574	305
AnnaBridge	145:64910690c574	306	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	307	* @{
AnnaBridge	145:64910690c574	308	*/
AnnaBridge	145:64910690c574	309
AnnaBridge	145:64910690c574	310	/**
AnnaBridge	145:64910690c574	311	* @brief Enable SPI peripheral
AnnaBridge	145:64910690c574	312	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	145:64910690c574	313	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	314	* @retval None
AnnaBridge	145:64910690c574	315	*/
AnnaBridge	145:64910690c574	316	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	317	{
AnnaBridge	145:64910690c574	318	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	319	}
AnnaBridge	145:64910690c574	320
AnnaBridge	145:64910690c574	321	/**
AnnaBridge	145:64910690c574	322	* @brief Disable SPI peripheral
AnnaBridge	145:64910690c574	323	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	145:64910690c574	324	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	145:64910690c574	325	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	326	* @retval None
AnnaBridge	145:64910690c574	327	*/
AnnaBridge	145:64910690c574	328	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	329	{
AnnaBridge	145:64910690c574	330	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	331	}
AnnaBridge	145:64910690c574	332
AnnaBridge	145:64910690c574	333	/**
AnnaBridge	145:64910690c574	334	* @brief Check if SPI peripheral is enabled
AnnaBridge	145:64910690c574	335	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	145:64910690c574	336	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	337	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	338	*/
AnnaBridge	145:64910690c574	339	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	340	{
AnnaBridge	145:64910690c574	341	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	145:64910690c574	342	}
AnnaBridge	145:64910690c574	343
AnnaBridge	145:64910690c574	344	/**
AnnaBridge	145:64910690c574	345	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	145:64910690c574	346	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	347	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	145:64910690c574	348	* CR1 SSI LL_SPI_SetMode
AnnaBridge	145:64910690c574	349	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	350	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	351	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	145:64910690c574	352	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	145:64910690c574	353	* @retval None
AnnaBridge	145:64910690c574	354	*/
AnnaBridge	145:64910690c574	355	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	145:64910690c574	356	{
AnnaBridge	145:64910690c574	357	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	145:64910690c574	358	}
AnnaBridge	145:64910690c574	359
AnnaBridge	145:64910690c574	360	/**
AnnaBridge	145:64910690c574	361	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	145:64910690c574	362	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	145:64910690c574	363	* CR1 SSI LL_SPI_GetMode
AnnaBridge	145:64910690c574	364	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	365	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	366	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	145:64910690c574	367	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	145:64910690c574	368	*/
AnnaBridge	145:64910690c574	369	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	370	{
AnnaBridge	145:64910690c574	371	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	145:64910690c574	372	}
AnnaBridge	145:64910690c574	373
AnnaBridge	145:64910690c574	374	/**
AnnaBridge	145:64910690c574	375	* @brief Set serial protocol used
AnnaBridge	145:64910690c574	376	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	377	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	145:64910690c574	378	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	379	* @param Standard This parameter can be one of the following values:
AnnaBridge	145:64910690c574	380	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	145:64910690c574	381	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	145:64910690c574	382	* @retval None
AnnaBridge	145:64910690c574	383	*/
AnnaBridge	145:64910690c574	384	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	145:64910690c574	385	{
AnnaBridge	145:64910690c574	386	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	145:64910690c574	387	}
AnnaBridge	145:64910690c574	388
AnnaBridge	145:64910690c574	389	/**
AnnaBridge	145:64910690c574	390	* @brief Get serial protocol used
AnnaBridge	145:64910690c574	391	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	145:64910690c574	392	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	393	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	394	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	145:64910690c574	395	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	145:64910690c574	396	*/
AnnaBridge	145:64910690c574	397	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	398	{
AnnaBridge	145:64910690c574	399	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	145:64910690c574	400	}
AnnaBridge	145:64910690c574	401
AnnaBridge	145:64910690c574	402	/**
AnnaBridge	145:64910690c574	403	* @brief Set clock phase
AnnaBridge	145:64910690c574	404	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	405	* This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	406	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	145:64910690c574	407	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	408	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	145:64910690c574	409	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	145:64910690c574	410	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	145:64910690c574	411	* @retval None
AnnaBridge	145:64910690c574	412	*/
AnnaBridge	145:64910690c574	413	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	145:64910690c574	414	{
AnnaBridge	145:64910690c574	415	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	145:64910690c574	416	}
AnnaBridge	145:64910690c574	417
AnnaBridge	145:64910690c574	418	/**
AnnaBridge	145:64910690c574	419	* @brief Get clock phase
AnnaBridge	145:64910690c574	420	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	145:64910690c574	421	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	422	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	423	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	145:64910690c574	424	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	145:64910690c574	425	*/
AnnaBridge	145:64910690c574	426	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	427	{
AnnaBridge	145:64910690c574	428	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	145:64910690c574	429	}
AnnaBridge	145:64910690c574	430
AnnaBridge	145:64910690c574	431	/**
AnnaBridge	145:64910690c574	432	* @brief Set clock polarity
AnnaBridge	145:64910690c574	433	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	434	* This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	435	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	145:64910690c574	436	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	437	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	438	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	145:64910690c574	439	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	145:64910690c574	440	* @retval None
AnnaBridge	145:64910690c574	441	*/
AnnaBridge	145:64910690c574	442	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	145:64910690c574	443	{
AnnaBridge	145:64910690c574	444	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	145:64910690c574	445	}
AnnaBridge	145:64910690c574	446
AnnaBridge	145:64910690c574	447	/**
AnnaBridge	145:64910690c574	448	* @brief Get clock polarity
AnnaBridge	145:64910690c574	449	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	145:64910690c574	450	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	451	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	452	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	145:64910690c574	453	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	145:64910690c574	454	*/
AnnaBridge	145:64910690c574	455	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	456	{
AnnaBridge	145:64910690c574	457	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	145:64910690c574	458	}
AnnaBridge	145:64910690c574	459
AnnaBridge	145:64910690c574	460	/**
AnnaBridge	145:64910690c574	461	* @brief Set baud rate prescaler
AnnaBridge	145:64910690c574	462	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	145:64910690c574	463	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	145:64910690c574	464	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	465	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	145:64910690c574	466	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	145:64910690c574	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	145:64910690c574	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	145:64910690c574	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	145:64910690c574	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	145:64910690c574	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	145:64910690c574	472	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	145:64910690c574	473	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	145:64910690c574	474	* @retval None
AnnaBridge	145:64910690c574	475	*/
AnnaBridge	145:64910690c574	476	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	145:64910690c574	477	{
AnnaBridge	145:64910690c574	478	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	145:64910690c574	479	}
AnnaBridge	145:64910690c574	480
AnnaBridge	145:64910690c574	481	/**
AnnaBridge	145:64910690c574	482	* @brief Get baud rate prescaler
AnnaBridge	145:64910690c574	483	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	145:64910690c574	484	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	485	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	486	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	145:64910690c574	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	145:64910690c574	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	145:64910690c574	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	145:64910690c574	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	145:64910690c574	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	145:64910690c574	492	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	145:64910690c574	493	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	145:64910690c574	494	*/
AnnaBridge	145:64910690c574	495	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	496	{
AnnaBridge	145:64910690c574	497	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	145:64910690c574	498	}
AnnaBridge	145:64910690c574	499
AnnaBridge	145:64910690c574	500	/**
AnnaBridge	145:64910690c574	501	* @brief Set transfer bit order
AnnaBridge	145:64910690c574	502	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	503	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	145:64910690c574	504	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	505	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	145:64910690c574	506	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	145:64910690c574	507	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	145:64910690c574	508	* @retval None
AnnaBridge	145:64910690c574	509	*/
AnnaBridge	145:64910690c574	510	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	145:64910690c574	511	{
AnnaBridge	145:64910690c574	512	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	145:64910690c574	513	}
AnnaBridge	145:64910690c574	514
AnnaBridge	145:64910690c574	515	/**
AnnaBridge	145:64910690c574	516	* @brief Get transfer bit order
AnnaBridge	145:64910690c574	517	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	145:64910690c574	518	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	519	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	520	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	145:64910690c574	521	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	145:64910690c574	522	*/
AnnaBridge	145:64910690c574	523	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	524	{
AnnaBridge	145:64910690c574	525	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	145:64910690c574	526	}
AnnaBridge	145:64910690c574	527
AnnaBridge	145:64910690c574	528	/**
AnnaBridge	145:64910690c574	529	* @brief Set transfer direction mode
AnnaBridge	145:64910690c574	530	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	145:64910690c574	531	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	145:64910690c574	532	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	145:64910690c574	533	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	145:64910690c574	534	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	145:64910690c574	535	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	536	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	145:64910690c574	537	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	145:64910690c574	538	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	145:64910690c574	539	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	145:64910690c574	540	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	145:64910690c574	541	* @retval None
AnnaBridge	145:64910690c574	542	*/
AnnaBridge	145:64910690c574	543	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	145:64910690c574	544	{
AnnaBridge	145:64910690c574	545	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	145:64910690c574	546	}
AnnaBridge	145:64910690c574	547
AnnaBridge	145:64910690c574	548	/**
AnnaBridge	145:64910690c574	549	* @brief Get transfer direction mode
AnnaBridge	145:64910690c574	550	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	145:64910690c574	551	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	145:64910690c574	552	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	145:64910690c574	553	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	554	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	555	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	145:64910690c574	556	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	145:64910690c574	557	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	145:64910690c574	558	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	145:64910690c574	559	*/
AnnaBridge	145:64910690c574	560	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	561	{
AnnaBridge	145:64910690c574	562	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	145:64910690c574	563	}
AnnaBridge	145:64910690c574	564
AnnaBridge	145:64910690c574	565	/**
AnnaBridge	145:64910690c574	566	* @brief Set frame data width
AnnaBridge	145:64910690c574	567	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge	145:64910690c574	568	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	569	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	145:64910690c574	570	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	145:64910690c574	571	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	145:64910690c574	572	* @retval None
AnnaBridge	145:64910690c574	573	*/
AnnaBridge	145:64910690c574	574	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	145:64910690c574	575	{
AnnaBridge	145:64910690c574	576	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge	145:64910690c574	577	}
AnnaBridge	145:64910690c574	578
AnnaBridge	145:64910690c574	579	/**
AnnaBridge	145:64910690c574	580	* @brief Get frame data width
AnnaBridge	145:64910690c574	581	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge	145:64910690c574	582	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	583	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	584	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	145:64910690c574	585	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	145:64910690c574	586	*/
AnnaBridge	145:64910690c574	587	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	588	{
AnnaBridge	145:64910690c574	589	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge	145:64910690c574	590	}
AnnaBridge	145:64910690c574	591
AnnaBridge	145:64910690c574	592	/**
AnnaBridge	145:64910690c574	593	* @}
AnnaBridge	145:64910690c574	594	*/
AnnaBridge	145:64910690c574	595
AnnaBridge	145:64910690c574	596	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	145:64910690c574	597	* @{
AnnaBridge	145:64910690c574	598	*/
AnnaBridge	145:64910690c574	599
AnnaBridge	145:64910690c574	600	/**
AnnaBridge	145:64910690c574	601	* @brief Enable CRC
AnnaBridge	145:64910690c574	602	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	603	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	145:64910690c574	604	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	605	* @retval None
AnnaBridge	145:64910690c574	606	*/
AnnaBridge	145:64910690c574	607	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	608	{
AnnaBridge	145:64910690c574	609	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	145:64910690c574	610	}
AnnaBridge	145:64910690c574	611
AnnaBridge	145:64910690c574	612	/**
AnnaBridge	145:64910690c574	613	* @brief Disable CRC
AnnaBridge	145:64910690c574	614	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	615	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	145:64910690c574	616	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	617	* @retval None
AnnaBridge	145:64910690c574	618	*/
AnnaBridge	145:64910690c574	619	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	620	{
AnnaBridge	145:64910690c574	621	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	145:64910690c574	622	}
AnnaBridge	145:64910690c574	623
AnnaBridge	145:64910690c574	624	/**
AnnaBridge	145:64910690c574	625	* @brief Check if CRC is enabled
AnnaBridge	145:64910690c574	626	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	627	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	145:64910690c574	628	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	629	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	630	*/
AnnaBridge	145:64910690c574	631	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	632	{
AnnaBridge	145:64910690c574	633	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	145:64910690c574	634	}
AnnaBridge	145:64910690c574	635
AnnaBridge	145:64910690c574	636	/**
AnnaBridge	145:64910690c574	637	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	145:64910690c574	638	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	145:64910690c574	639	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	145:64910690c574	640	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	641	* @retval None
AnnaBridge	145:64910690c574	642	*/
AnnaBridge	145:64910690c574	643	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	644	{
AnnaBridge	145:64910690c574	645	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	145:64910690c574	646	}
AnnaBridge	145:64910690c574	647
AnnaBridge	145:64910690c574	648	/**
AnnaBridge	145:64910690c574	649	* @brief Set polynomial for CRC calculation
AnnaBridge	145:64910690c574	650	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	145:64910690c574	651	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	652	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	653	* @retval None
AnnaBridge	145:64910690c574	654	*/
AnnaBridge	145:64910690c574	655	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	145:64910690c574	656	{
AnnaBridge	145:64910690c574	657	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	145:64910690c574	658	}
AnnaBridge	145:64910690c574	659
AnnaBridge	145:64910690c574	660	/**
AnnaBridge	145:64910690c574	661	* @brief Get polynomial for CRC calculation
AnnaBridge	145:64910690c574	662	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	145:64910690c574	663	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	664	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	665	*/
AnnaBridge	145:64910690c574	666	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	667	{
AnnaBridge	145:64910690c574	668	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	145:64910690c574	669	}
AnnaBridge	145:64910690c574	670
AnnaBridge	145:64910690c574	671	/**
AnnaBridge	145:64910690c574	672	* @brief Get Rx CRC
AnnaBridge	145:64910690c574	673	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	145:64910690c574	674	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	675	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	676	*/
AnnaBridge	145:64910690c574	677	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	678	{
AnnaBridge	145:64910690c574	679	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	145:64910690c574	680	}
AnnaBridge	145:64910690c574	681
AnnaBridge	145:64910690c574	682	/**
AnnaBridge	145:64910690c574	683	* @brief Get Tx CRC
AnnaBridge	145:64910690c574	684	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	145:64910690c574	685	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	686	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	687	*/
AnnaBridge	145:64910690c574	688	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	689	{
AnnaBridge	145:64910690c574	690	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	145:64910690c574	691	}
AnnaBridge	145:64910690c574	692
AnnaBridge	145:64910690c574	693	/**
AnnaBridge	145:64910690c574	694	* @}
AnnaBridge	145:64910690c574	695	*/
AnnaBridge	145:64910690c574	696
AnnaBridge	145:64910690c574	697	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	145:64910690c574	698	* @{
AnnaBridge	145:64910690c574	699	*/
AnnaBridge	145:64910690c574	700
AnnaBridge	145:64910690c574	701	/**
AnnaBridge	145:64910690c574	702	* @brief Set NSS mode
AnnaBridge	145:64910690c574	703	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	145:64910690c574	704	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	145:64910690c574	705	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	145:64910690c574	706	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	707	* @param NSS This parameter can be one of the following values:
AnnaBridge	145:64910690c574	708	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	145:64910690c574	709	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	145:64910690c574	710	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	145:64910690c574	711	* @retval None
AnnaBridge	145:64910690c574	712	*/
AnnaBridge	145:64910690c574	713	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	145:64910690c574	714	{
AnnaBridge	145:64910690c574	715	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	145:64910690c574	716	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	145:64910690c574	717	}
AnnaBridge	145:64910690c574	718
AnnaBridge	145:64910690c574	719	/**
AnnaBridge	145:64910690c574	720	* @brief Get NSS mode
AnnaBridge	145:64910690c574	721	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	145:64910690c574	722	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	145:64910690c574	723	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	724	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	725	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	145:64910690c574	726	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	145:64910690c574	727	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	145:64910690c574	728	*/
AnnaBridge	145:64910690c574	729	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	730	{
AnnaBridge	145:64910690c574	731	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	145:64910690c574	732	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	145:64910690c574	733	return (Ssm \| Ssoe);
AnnaBridge	145:64910690c574	734	}
AnnaBridge	145:64910690c574	735
AnnaBridge	145:64910690c574	736	/**
AnnaBridge	145:64910690c574	737	* @}
AnnaBridge	145:64910690c574	738	*/
AnnaBridge	145:64910690c574	739
AnnaBridge	145:64910690c574	740	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	145:64910690c574	741	* @{
AnnaBridge	145:64910690c574	742	*/
AnnaBridge	145:64910690c574	743
AnnaBridge	145:64910690c574	744	/**
AnnaBridge	145:64910690c574	745	* @brief Check if Rx buffer is not empty
AnnaBridge	145:64910690c574	746	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	145:64910690c574	747	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	748	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	749	*/
AnnaBridge	145:64910690c574	750	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	751	{
AnnaBridge	145:64910690c574	752	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	145:64910690c574	753	}
AnnaBridge	145:64910690c574	754
AnnaBridge	145:64910690c574	755	/**
AnnaBridge	145:64910690c574	756	* @brief Check if Tx buffer is empty
AnnaBridge	145:64910690c574	757	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	145:64910690c574	758	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	759	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	760	*/
AnnaBridge	145:64910690c574	761	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	762	{
AnnaBridge	145:64910690c574	763	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	145:64910690c574	764	}
AnnaBridge	145:64910690c574	765
AnnaBridge	145:64910690c574	766	/**
AnnaBridge	145:64910690c574	767	* @brief Get CRC error flag
AnnaBridge	145:64910690c574	768	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	145:64910690c574	769	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	770	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	771	*/
AnnaBridge	145:64910690c574	772	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	773	{
AnnaBridge	145:64910690c574	774	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	145:64910690c574	775	}
AnnaBridge	145:64910690c574	776
AnnaBridge	145:64910690c574	777	/**
AnnaBridge	145:64910690c574	778	* @brief Get mode fault error flag
AnnaBridge	145:64910690c574	779	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	145:64910690c574	780	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	781	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	782	*/
AnnaBridge	145:64910690c574	783	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	784	{
AnnaBridge	145:64910690c574	785	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	145:64910690c574	786	}
AnnaBridge	145:64910690c574	787
AnnaBridge	145:64910690c574	788	/**
AnnaBridge	145:64910690c574	789	* @brief Get overrun error flag
AnnaBridge	145:64910690c574	790	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	145:64910690c574	791	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	792	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	793	*/
AnnaBridge	145:64910690c574	794	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	795	{
AnnaBridge	145:64910690c574	796	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	145:64910690c574	797	}
AnnaBridge	145:64910690c574	798
AnnaBridge	145:64910690c574	799	/**
AnnaBridge	145:64910690c574	800	* @brief Get busy flag
AnnaBridge	145:64910690c574	801	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	145:64910690c574	802	* -When the SPI is correctly disabled
AnnaBridge	145:64910690c574	803	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	145:64910690c574	804	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	145:64910690c574	805	* sent
AnnaBridge	145:64910690c574	806	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	145:64910690c574	807	* each data transfer.
AnnaBridge	145:64910690c574	808	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	145:64910690c574	809	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	810	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	811	*/
AnnaBridge	145:64910690c574	812	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	813	{
AnnaBridge	145:64910690c574	814	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	145:64910690c574	815	}
AnnaBridge	145:64910690c574	816
AnnaBridge	145:64910690c574	817	/**
AnnaBridge	145:64910690c574	818	* @brief Get frame format error flag
AnnaBridge	145:64910690c574	819	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	145:64910690c574	820	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	821	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	822	*/
AnnaBridge	145:64910690c574	823	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	824	{
AnnaBridge	145:64910690c574	825	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	145:64910690c574	826	}
AnnaBridge	145:64910690c574	827
AnnaBridge	145:64910690c574	828	/**
AnnaBridge	145:64910690c574	829	* @brief Clear CRC error flag
AnnaBridge	145:64910690c574	830	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	145:64910690c574	831	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	832	* @retval None
AnnaBridge	145:64910690c574	833	*/
AnnaBridge	145:64910690c574	834	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	835	{
AnnaBridge	145:64910690c574	836	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	145:64910690c574	837	}
AnnaBridge	145:64910690c574	838
AnnaBridge	145:64910690c574	839	/**
AnnaBridge	145:64910690c574	840	* @brief Clear mode fault error flag
AnnaBridge	145:64910690c574	841	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	145:64910690c574	842	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	145:64910690c574	843	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	145:64910690c574	844	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	845	* @retval None
AnnaBridge	145:64910690c574	846	*/
AnnaBridge	145:64910690c574	847	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	848	{
AnnaBridge	145:64910690c574	849	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	850	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	851	(void) tmpreg;
AnnaBridge	145:64910690c574	852	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	853	(void) tmpreg;
AnnaBridge	145:64910690c574	854	}
AnnaBridge	145:64910690c574	855
AnnaBridge	145:64910690c574	856	/**
AnnaBridge	145:64910690c574	857	* @brief Clear overrun error flag
AnnaBridge	145:64910690c574	858	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	145:64910690c574	859	* register followed by a read access to the SPIx_SR register
AnnaBridge	145:64910690c574	860	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	145:64910690c574	861	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	862	* @retval None
AnnaBridge	145:64910690c574	863	*/
AnnaBridge	145:64910690c574	864	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	865	{
AnnaBridge	145:64910690c574	866	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	867	tmpreg = SPIx->DR;
AnnaBridge	145:64910690c574	868	(void) tmpreg;
AnnaBridge	145:64910690c574	869	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	870	(void) tmpreg;
AnnaBridge	145:64910690c574	871	}
AnnaBridge	145:64910690c574	872
AnnaBridge	145:64910690c574	873	/**
AnnaBridge	145:64910690c574	874	* @brief Clear frame format error flag
AnnaBridge	145:64910690c574	875	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	145:64910690c574	876	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	145:64910690c574	877	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	878	* @retval None
AnnaBridge	145:64910690c574	879	*/
AnnaBridge	145:64910690c574	880	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	881	{
AnnaBridge	145:64910690c574	882	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	883	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	884	(void) tmpreg;
AnnaBridge	145:64910690c574	885	}
AnnaBridge	145:64910690c574	886
AnnaBridge	145:64910690c574	887	/**
AnnaBridge	145:64910690c574	888	* @}
AnnaBridge	145:64910690c574	889	*/
AnnaBridge	145:64910690c574	890
AnnaBridge	145:64910690c574	891	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	145:64910690c574	892	* @{
AnnaBridge	145:64910690c574	893	*/
AnnaBridge	145:64910690c574	894
AnnaBridge	145:64910690c574	895	/**
AnnaBridge	145:64910690c574	896	* @brief Enable error interrupt
AnnaBridge	145:64910690c574	897	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	145:64910690c574	898	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	145:64910690c574	899	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	900	* @retval None
AnnaBridge	145:64910690c574	901	*/
AnnaBridge	145:64910690c574	902	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	903	{
AnnaBridge	145:64910690c574	904	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	145:64910690c574	905	}
AnnaBridge	145:64910690c574	906
AnnaBridge	145:64910690c574	907	/**
AnnaBridge	145:64910690c574	908	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	145:64910690c574	909	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	145:64910690c574	910	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	911	* @retval None
AnnaBridge	145:64910690c574	912	*/
AnnaBridge	145:64910690c574	913	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	914	{
AnnaBridge	145:64910690c574	915	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	145:64910690c574	916	}
AnnaBridge	145:64910690c574	917
AnnaBridge	145:64910690c574	918	/**
AnnaBridge	145:64910690c574	919	* @brief Enable Tx buffer empty interrupt
AnnaBridge	145:64910690c574	920	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	145:64910690c574	921	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	922	* @retval None
AnnaBridge	145:64910690c574	923	*/
AnnaBridge	145:64910690c574	924	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	925	{
AnnaBridge	145:64910690c574	926	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	145:64910690c574	927	}
AnnaBridge	145:64910690c574	928
AnnaBridge	145:64910690c574	929	/**
AnnaBridge	145:64910690c574	930	* @brief Disable error interrupt
AnnaBridge	145:64910690c574	931	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	145:64910690c574	932	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	145:64910690c574	933	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	934	* @retval None
AnnaBridge	145:64910690c574	935	*/
AnnaBridge	145:64910690c574	936	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	937	{
AnnaBridge	145:64910690c574	938	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	145:64910690c574	939	}
AnnaBridge	145:64910690c574	940
AnnaBridge	145:64910690c574	941	/**
AnnaBridge	145:64910690c574	942	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	145:64910690c574	943	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	145:64910690c574	944	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	945	* @retval None
AnnaBridge	145:64910690c574	946	*/
AnnaBridge	145:64910690c574	947	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	948	{
AnnaBridge	145:64910690c574	949	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	145:64910690c574	950	}
AnnaBridge	145:64910690c574	951
AnnaBridge	145:64910690c574	952	/**
AnnaBridge	145:64910690c574	953	* @brief Disable Tx buffer empty interrupt
AnnaBridge	145:64910690c574	954	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	145:64910690c574	955	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	956	* @retval None
AnnaBridge	145:64910690c574	957	*/
AnnaBridge	145:64910690c574	958	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	959	{
AnnaBridge	145:64910690c574	960	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	145:64910690c574	961	}
AnnaBridge	145:64910690c574	962
AnnaBridge	145:64910690c574	963	/**
AnnaBridge	145:64910690c574	964	* @brief Check if error interrupt is enabled
AnnaBridge	145:64910690c574	965	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	145:64910690c574	966	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	967	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	968	*/
AnnaBridge	145:64910690c574	969	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	970	{
AnnaBridge	145:64910690c574	971	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	145:64910690c574	972	}
AnnaBridge	145:64910690c574	973
AnnaBridge	145:64910690c574	974	/**
AnnaBridge	145:64910690c574	975	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	145:64910690c574	976	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	145:64910690c574	977	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	978	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	979	*/
AnnaBridge	145:64910690c574	980	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	981	{
AnnaBridge	145:64910690c574	982	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	145:64910690c574	983	}
AnnaBridge	145:64910690c574	984
AnnaBridge	145:64910690c574	985	/**
AnnaBridge	145:64910690c574	986	* @brief Check if Tx buffer empty interrupt
AnnaBridge	145:64910690c574	987	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	145:64910690c574	988	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	989	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	990	*/
AnnaBridge	145:64910690c574	991	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	992	{
AnnaBridge	145:64910690c574	993	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	145:64910690c574	994	}
AnnaBridge	145:64910690c574	995
AnnaBridge	145:64910690c574	996	/**
AnnaBridge	145:64910690c574	997	* @}
AnnaBridge	145:64910690c574	998	*/
AnnaBridge	145:64910690c574	999
AnnaBridge	145:64910690c574	1000	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	145:64910690c574	1001	* @{
AnnaBridge	145:64910690c574	1002	*/
AnnaBridge	145:64910690c574	1003
AnnaBridge	145:64910690c574	1004	/**
AnnaBridge	145:64910690c574	1005	* @brief Enable DMA Rx
AnnaBridge	145:64910690c574	1006	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	145:64910690c574	1007	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1008	* @retval None
AnnaBridge	145:64910690c574	1009	*/
AnnaBridge	145:64910690c574	1010	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1011	{
AnnaBridge	145:64910690c574	1012	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	145:64910690c574	1013	}
AnnaBridge	145:64910690c574	1014
AnnaBridge	145:64910690c574	1015	/**
AnnaBridge	145:64910690c574	1016	* @brief Disable DMA Rx
AnnaBridge	145:64910690c574	1017	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	145:64910690c574	1018	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1019	* @retval None
AnnaBridge	145:64910690c574	1020	*/
AnnaBridge	145:64910690c574	1021	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1022	{
AnnaBridge	145:64910690c574	1023	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	145:64910690c574	1024	}
AnnaBridge	145:64910690c574	1025
AnnaBridge	145:64910690c574	1026	/**
AnnaBridge	145:64910690c574	1027	* @brief Check if DMA Rx is enabled
AnnaBridge	145:64910690c574	1028	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	145:64910690c574	1029	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1030	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1031	*/
AnnaBridge	145:64910690c574	1032	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1033	{
AnnaBridge	145:64910690c574	1034	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	145:64910690c574	1035	}
AnnaBridge	145:64910690c574	1036
AnnaBridge	145:64910690c574	1037	/**
AnnaBridge	145:64910690c574	1038	* @brief Enable DMA Tx
AnnaBridge	145:64910690c574	1039	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	145:64910690c574	1040	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1041	* @retval None
AnnaBridge	145:64910690c574	1042	*/
AnnaBridge	145:64910690c574	1043	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1044	{
AnnaBridge	145:64910690c574	1045	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	145:64910690c574	1046	}
AnnaBridge	145:64910690c574	1047
AnnaBridge	145:64910690c574	1048	/**
AnnaBridge	145:64910690c574	1049	* @brief Disable DMA Tx
AnnaBridge	145:64910690c574	1050	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	145:64910690c574	1051	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1052	* @retval None
AnnaBridge	145:64910690c574	1053	*/
AnnaBridge	145:64910690c574	1054	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1055	{
AnnaBridge	145:64910690c574	1056	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	145:64910690c574	1057	}
AnnaBridge	145:64910690c574	1058
AnnaBridge	145:64910690c574	1059	/**
AnnaBridge	145:64910690c574	1060	* @brief Check if DMA Tx is enabled
AnnaBridge	145:64910690c574	1061	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	145:64910690c574	1062	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1063	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1064	*/
AnnaBridge	145:64910690c574	1065	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1066	{
AnnaBridge	145:64910690c574	1067	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	145:64910690c574	1068	}
AnnaBridge	145:64910690c574	1069
AnnaBridge	145:64910690c574	1070	/**
AnnaBridge	145:64910690c574	1071	* @brief Get the data register address used for DMA transfer
AnnaBridge	145:64910690c574	1072	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	145:64910690c574	1073	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1074	* @retval Address of data register
AnnaBridge	145:64910690c574	1075	*/
AnnaBridge	145:64910690c574	1076	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1077	{
AnnaBridge	145:64910690c574	1078	return (uint32_t) & (SPIx->DR);
AnnaBridge	145:64910690c574	1079	}
AnnaBridge	145:64910690c574	1080
AnnaBridge	145:64910690c574	1081	/**
AnnaBridge	145:64910690c574	1082	* @}
AnnaBridge	145:64910690c574	1083	*/
AnnaBridge	145:64910690c574	1084
AnnaBridge	145:64910690c574	1085	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	145:64910690c574	1086	* @{
AnnaBridge	145:64910690c574	1087	*/
AnnaBridge	145:64910690c574	1088
AnnaBridge	145:64910690c574	1089	/**
AnnaBridge	145:64910690c574	1090	* @brief Read 8-Bits in the data register
AnnaBridge	145:64910690c574	1091	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	145:64910690c574	1092	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1093	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1094	*/
AnnaBridge	145:64910690c574	1095	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1096	{
AnnaBridge	145:64910690c574	1097	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	145:64910690c574	1098	}
AnnaBridge	145:64910690c574	1099
AnnaBridge	145:64910690c574	1100	/**
AnnaBridge	145:64910690c574	1101	* @brief Read 16-Bits in the data register
AnnaBridge	145:64910690c574	1102	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	145:64910690c574	1103	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1104	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1105	*/
AnnaBridge	145:64910690c574	1106	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1107	{
AnnaBridge	145:64910690c574	1108	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	145:64910690c574	1109	}
AnnaBridge	145:64910690c574	1110
AnnaBridge	145:64910690c574	1111	/**
AnnaBridge	145:64910690c574	1112	* @brief Write 8-Bits in the data register
AnnaBridge	145:64910690c574	1113	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	145:64910690c574	1114	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1115	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1116	* @retval None
AnnaBridge	145:64910690c574	1117	*/
AnnaBridge	145:64910690c574	1118	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	145:64910690c574	1119	{
AnnaBridge	145:64910690c574	1120	SPIx->DR = TxData;
AnnaBridge	145:64910690c574	1121	}
AnnaBridge	145:64910690c574	1122
AnnaBridge	145:64910690c574	1123	/**
AnnaBridge	145:64910690c574	1124	* @brief Write 16-Bits in the data register
AnnaBridge	145:64910690c574	1125	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	145:64910690c574	1126	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1127	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1128	* @retval None
AnnaBridge	145:64910690c574	1129	*/
AnnaBridge	145:64910690c574	1130	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	145:64910690c574	1131	{
AnnaBridge	145:64910690c574	1132	SPIx->DR = TxData;
AnnaBridge	145:64910690c574	1133	}
AnnaBridge	145:64910690c574	1134
AnnaBridge	145:64910690c574	1135	/**
AnnaBridge	145:64910690c574	1136	* @}
AnnaBridge	145:64910690c574	1137	*/
AnnaBridge	145:64910690c574	1138	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1139	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	1140	* @{
AnnaBridge	145:64910690c574	1141	*/
AnnaBridge	145:64910690c574	1142
AnnaBridge	145:64910690c574	1143	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	145:64910690c574	1144	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	145:64910690c574	1145	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	145:64910690c574	1146
AnnaBridge	145:64910690c574	1147	/**
AnnaBridge	145:64910690c574	1148	* @}
AnnaBridge	145:64910690c574	1149	*/
AnnaBridge	145:64910690c574	1150	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	1151	/**
AnnaBridge	145:64910690c574	1152	* @}
AnnaBridge	145:64910690c574	1153	*/
AnnaBridge	145:64910690c574	1154
AnnaBridge	145:64910690c574	1155	/**
AnnaBridge	145:64910690c574	1156	* @}
AnnaBridge	145:64910690c574	1157	*/
AnnaBridge	145:64910690c574	1158
AnnaBridge	145:64910690c574	1159	/** @defgroup I2S_LL I2S
AnnaBridge	145:64910690c574	1160	* @{
AnnaBridge	145:64910690c574	1161	*/
AnnaBridge	145:64910690c574	1162
AnnaBridge	145:64910690c574	1163	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	1164	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	1165	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1166
AnnaBridge	145:64910690c574	1167	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1168	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1169	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	145:64910690c574	1170	* @{
AnnaBridge	145:64910690c574	1171	*/
AnnaBridge	145:64910690c574	1172
AnnaBridge	145:64910690c574	1173	/**
AnnaBridge	145:64910690c574	1174	* @brief I2S Init structure definition
AnnaBridge	145:64910690c574	1175	*/
AnnaBridge	145:64910690c574	1176
AnnaBridge	145:64910690c574	1177	typedef struct
AnnaBridge	145:64910690c574	1178	{
AnnaBridge	145:64910690c574	1179	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	145:64910690c574	1180	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	145:64910690c574	1181
AnnaBridge	145:64910690c574	1182	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	145:64910690c574	1183
AnnaBridge	145:64910690c574	1184	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	145:64910690c574	1185	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	145:64910690c574	1186
AnnaBridge	145:64910690c574	1187	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	145:64910690c574	1188
AnnaBridge	145:64910690c574	1189
AnnaBridge	145:64910690c574	1190	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	145:64910690c574	1191	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	145:64910690c574	1192
AnnaBridge	145:64910690c574	1193	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	145:64910690c574	1194
AnnaBridge	145:64910690c574	1195
AnnaBridge	145:64910690c574	1196	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	145:64910690c574	1197	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	145:64910690c574	1198
AnnaBridge	145:64910690c574	1199	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	145:64910690c574	1200
AnnaBridge	145:64910690c574	1201
AnnaBridge	145:64910690c574	1202	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	145:64910690c574	1203	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	145:64910690c574	1204
AnnaBridge	145:64910690c574	1205	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	145:64910690c574	1206	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	145:64910690c574	1207
AnnaBridge	145:64910690c574	1208
AnnaBridge	145:64910690c574	1209	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	145:64910690c574	1210	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	145:64910690c574	1211
AnnaBridge	145:64910690c574	1212	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	145:64910690c574	1213
AnnaBridge	145:64910690c574	1214	} LL_I2S_InitTypeDef;
AnnaBridge	145:64910690c574	1215
AnnaBridge	145:64910690c574	1216	/**
AnnaBridge	145:64910690c574	1217	* @}
AnnaBridge	145:64910690c574	1218	*/
AnnaBridge	145:64910690c574	1219	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	1220
AnnaBridge	145:64910690c574	1221	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	1222	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	145:64910690c574	1223	* @{
AnnaBridge	145:64910690c574	1224	*/
AnnaBridge	145:64910690c574	1225
AnnaBridge	145:64910690c574	1226	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	1227	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	145:64910690c574	1228	* @{
AnnaBridge	145:64910690c574	1229	*/
AnnaBridge	145:64910690c574	1230	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	145:64910690c574	1231	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	145:64910690c574	1232	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	145:64910690c574	1233	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	145:64910690c574	1234	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	145:64910690c574	1235	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	145:64910690c574	1236	/**
AnnaBridge	145:64910690c574	1237	* @}
AnnaBridge	145:64910690c574	1238	*/
AnnaBridge	145:64910690c574	1239
AnnaBridge	145:64910690c574	1240	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	1241	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	145:64910690c574	1242	* @{
AnnaBridge	145:64910690c574	1243	*/
AnnaBridge	145:64910690c574	1244	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	145:64910690c574	1245	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	145:64910690c574	1246	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	145:64910690c574	1247	/**
AnnaBridge	145:64910690c574	1248	* @}
AnnaBridge	145:64910690c574	1249	*/
AnnaBridge	145:64910690c574	1250
AnnaBridge	145:64910690c574	1251	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	145:64910690c574	1252	* @{
AnnaBridge	145:64910690c574	1253	*/
AnnaBridge	145:64910690c574	1254	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	145:64910690c574	1255	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	145:64910690c574	1256	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	145:64910690c574	1257	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	145:64910690c574	1258	/**
AnnaBridge	145:64910690c574	1259	* @}
AnnaBridge	145:64910690c574	1260	*/
AnnaBridge	145:64910690c574	1261
AnnaBridge	145:64910690c574	1262	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	145:64910690c574	1263	* @{
AnnaBridge	145:64910690c574	1264	*/
AnnaBridge	145:64910690c574	1265	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
AnnaBridge	145:64910690c574	1266	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	145:64910690c574	1267	/**
AnnaBridge	145:64910690c574	1268	* @}
AnnaBridge	145:64910690c574	1269	*/
AnnaBridge	145:64910690c574	1270
AnnaBridge	145:64910690c574	1271	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	145:64910690c574	1272	* @{
AnnaBridge	145:64910690c574	1273	*/
AnnaBridge	145:64910690c574	1274	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
AnnaBridge	145:64910690c574	1275	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	145:64910690c574	1276	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	145:64910690c574	1277	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	145:64910690c574	1278	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	145:64910690c574	1279	/**
AnnaBridge	145:64910690c574	1280	* @}
AnnaBridge	145:64910690c574	1281	*/
AnnaBridge	145:64910690c574	1282
AnnaBridge	145:64910690c574	1283	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	145:64910690c574	1284	* @{
AnnaBridge	145:64910690c574	1285	*/
AnnaBridge	145:64910690c574	1286	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
AnnaBridge	145:64910690c574	1287	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	145:64910690c574	1288	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	145:64910690c574	1289	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	145:64910690c574	1290	/**
AnnaBridge	145:64910690c574	1291	* @}
AnnaBridge	145:64910690c574	1292	*/
AnnaBridge	145:64910690c574	1293
AnnaBridge	145:64910690c574	1294	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	145:64910690c574	1295	* @{
AnnaBridge	145:64910690c574	1296	*/
AnnaBridge	145:64910690c574	1297	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	145:64910690c574	1298	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	145:64910690c574	1299	/**
AnnaBridge	145:64910690c574	1300	* @}
AnnaBridge	145:64910690c574	1301	*/
AnnaBridge	145:64910690c574	1302
AnnaBridge	145:64910690c574	1303	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1304
AnnaBridge	145:64910690c574	1305	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	145:64910690c574	1306	* @{
AnnaBridge	145:64910690c574	1307	*/
AnnaBridge	145:64910690c574	1308	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
AnnaBridge	145:64910690c574	1309	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	145:64910690c574	1310	/**
AnnaBridge	145:64910690c574	1311	* @}
AnnaBridge	145:64910690c574	1312	*/
AnnaBridge	145:64910690c574	1313
AnnaBridge	145:64910690c574	1314	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	145:64910690c574	1315	* @{
AnnaBridge	145:64910690c574	1316	*/
AnnaBridge	145:64910690c574	1317
AnnaBridge	145:64910690c574	1318	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	145:64910690c574	1319	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	145:64910690c574	1320	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	145:64910690c574	1321	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	145:64910690c574	1322	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	145:64910690c574	1323	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	145:64910690c574	1324	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	145:64910690c574	1325	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	145:64910690c574	1326	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	145:64910690c574	1327	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	145:64910690c574	1328	/**
AnnaBridge	145:64910690c574	1329	* @}
AnnaBridge	145:64910690c574	1330	*/
AnnaBridge	145:64910690c574	1331	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	1332
AnnaBridge	145:64910690c574	1333	/**
AnnaBridge	145:64910690c574	1334	* @}
AnnaBridge	145:64910690c574	1335	*/
AnnaBridge	145:64910690c574	1336
AnnaBridge	145:64910690c574	1337	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1338	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	145:64910690c574	1339	* @{
AnnaBridge	145:64910690c574	1340	*/
AnnaBridge	145:64910690c574	1341
AnnaBridge	145:64910690c574	1342	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	1343	* @{
AnnaBridge	145:64910690c574	1344	*/
AnnaBridge	145:64910690c574	1345
AnnaBridge	145:64910690c574	1346	/**
AnnaBridge	145:64910690c574	1347	* @brief Write a value in I2S register
AnnaBridge	145:64910690c574	1348	* @param __INSTANCE__ I2S Instance
AnnaBridge	145:64910690c574	1349	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	1350	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	1351	* @retval None
AnnaBridge	145:64910690c574	1352	*/
AnnaBridge	145:64910690c574	1353	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	1354
AnnaBridge	145:64910690c574	1355	/**
AnnaBridge	145:64910690c574	1356	* @brief Read a value in I2S register
AnnaBridge	145:64910690c574	1357	* @param __INSTANCE__ I2S Instance
AnnaBridge	145:64910690c574	1358	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	1359	* @retval Register value
AnnaBridge	145:64910690c574	1360	*/
AnnaBridge	145:64910690c574	1361	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	1362	/**
AnnaBridge	145:64910690c574	1363	* @}
AnnaBridge	145:64910690c574	1364	*/
AnnaBridge	145:64910690c574	1365
AnnaBridge	145:64910690c574	1366	/**
AnnaBridge	145:64910690c574	1367	* @}
AnnaBridge	145:64910690c574	1368	*/
AnnaBridge	145:64910690c574	1369
AnnaBridge	145:64910690c574	1370
AnnaBridge	145:64910690c574	1371	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	1372
AnnaBridge	145:64910690c574	1373	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	145:64910690c574	1374	* @{
AnnaBridge	145:64910690c574	1375	*/
AnnaBridge	145:64910690c574	1376
AnnaBridge	145:64910690c574	1377	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	1378	* @{
AnnaBridge	145:64910690c574	1379	*/
AnnaBridge	145:64910690c574	1380
AnnaBridge	145:64910690c574	1381	/**
AnnaBridge	145:64910690c574	1382	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	145:64910690c574	1383	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	145:64910690c574	1384	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	145:64910690c574	1385	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1386	* @retval None
AnnaBridge	145:64910690c574	1387	*/
AnnaBridge	145:64910690c574	1388	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1389	{
AnnaBridge	145:64910690c574	1390	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	145:64910690c574	1391	}
AnnaBridge	145:64910690c574	1392
AnnaBridge	145:64910690c574	1393	/**
AnnaBridge	145:64910690c574	1394	* @brief Disable I2S peripheral
AnnaBridge	145:64910690c574	1395	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	145:64910690c574	1396	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1397	* @retval None
AnnaBridge	145:64910690c574	1398	*/
AnnaBridge	145:64910690c574	1399	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1400	{
AnnaBridge	145:64910690c574	1401	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	145:64910690c574	1402	}
AnnaBridge	145:64910690c574	1403
AnnaBridge	145:64910690c574	1404	/**
AnnaBridge	145:64910690c574	1405	* @brief Check if I2S peripheral is enabled
AnnaBridge	145:64910690c574	1406	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	145:64910690c574	1407	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1408	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1409	*/
AnnaBridge	145:64910690c574	1410	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1411	{
AnnaBridge	145:64910690c574	1412	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	145:64910690c574	1413	}
AnnaBridge	145:64910690c574	1414
AnnaBridge	145:64910690c574	1415	/**
AnnaBridge	145:64910690c574	1416	* @brief Set I2S data frame length
AnnaBridge	145:64910690c574	1417	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	145:64910690c574	1418	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	145:64910690c574	1419	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1420	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1421	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	145:64910690c574	1422	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	145:64910690c574	1423	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	145:64910690c574	1424	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	145:64910690c574	1425	* @retval None
AnnaBridge	145:64910690c574	1426	*/
AnnaBridge	145:64910690c574	1427	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	145:64910690c574	1428	{
AnnaBridge	145:64910690c574	1429	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	145:64910690c574	1430	}
AnnaBridge	145:64910690c574	1431
AnnaBridge	145:64910690c574	1432	/**
AnnaBridge	145:64910690c574	1433	* @brief Get I2S data frame length
AnnaBridge	145:64910690c574	1434	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	145:64910690c574	1435	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	145:64910690c574	1436	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1437	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1438	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	145:64910690c574	1439	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	145:64910690c574	1440	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	145:64910690c574	1441	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	145:64910690c574	1442	*/
AnnaBridge	145:64910690c574	1443	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1444	{
AnnaBridge	145:64910690c574	1445	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	145:64910690c574	1446	}
AnnaBridge	145:64910690c574	1447
AnnaBridge	145:64910690c574	1448	/**
AnnaBridge	145:64910690c574	1449	* @brief Set I2S clock polarity
AnnaBridge	145:64910690c574	1450	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	145:64910690c574	1451	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1452	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1453	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	145:64910690c574	1454	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	145:64910690c574	1455	* @retval None
AnnaBridge	145:64910690c574	1456	*/
AnnaBridge	145:64910690c574	1457	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	145:64910690c574	1458	{
AnnaBridge	145:64910690c574	1459	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	145:64910690c574	1460	}
AnnaBridge	145:64910690c574	1461
AnnaBridge	145:64910690c574	1462	/**
AnnaBridge	145:64910690c574	1463	* @brief Get I2S clock polarity
AnnaBridge	145:64910690c574	1464	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	145:64910690c574	1465	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1466	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1467	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	145:64910690c574	1468	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	145:64910690c574	1469	*/
AnnaBridge	145:64910690c574	1470	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1471	{
AnnaBridge	145:64910690c574	1472	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	145:64910690c574	1473	}
AnnaBridge	145:64910690c574	1474
AnnaBridge	145:64910690c574	1475	/**
AnnaBridge	145:64910690c574	1476	* @brief Set I2S standard protocol
AnnaBridge	145:64910690c574	1477	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	145:64910690c574	1478	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	145:64910690c574	1479	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1480	* @param Standard This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1481	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	145:64910690c574	1482	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	145:64910690c574	1483	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	145:64910690c574	1484	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	145:64910690c574	1485	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	145:64910690c574	1486	* @retval None
AnnaBridge	145:64910690c574	1487	*/
AnnaBridge	145:64910690c574	1488	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	145:64910690c574	1489	{
AnnaBridge	145:64910690c574	1490	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	145:64910690c574	1491	}
AnnaBridge	145:64910690c574	1492
AnnaBridge	145:64910690c574	1493	/**
AnnaBridge	145:64910690c574	1494	* @brief Get I2S standard protocol
AnnaBridge	145:64910690c574	1495	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	145:64910690c574	1496	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	145:64910690c574	1497	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1498	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1499	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	145:64910690c574	1500	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	145:64910690c574	1501	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	145:64910690c574	1502	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	145:64910690c574	1503	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	145:64910690c574	1504	*/
AnnaBridge	145:64910690c574	1505	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1506	{
AnnaBridge	145:64910690c574	1507	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	145:64910690c574	1508	}
AnnaBridge	145:64910690c574	1509
AnnaBridge	145:64910690c574	1510	/**
AnnaBridge	145:64910690c574	1511	* @brief Set I2S transfer mode
AnnaBridge	145:64910690c574	1512	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	145:64910690c574	1513	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1514	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1515	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	145:64910690c574	1516	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	145:64910690c574	1517	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	145:64910690c574	1518	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	145:64910690c574	1519	* @retval None
AnnaBridge	145:64910690c574	1520	*/
AnnaBridge	145:64910690c574	1521	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	145:64910690c574	1522	{
AnnaBridge	145:64910690c574	1523	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	145:64910690c574	1524	}
AnnaBridge	145:64910690c574	1525
AnnaBridge	145:64910690c574	1526	/**
AnnaBridge	145:64910690c574	1527	* @brief Get I2S transfer mode
AnnaBridge	145:64910690c574	1528	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	145:64910690c574	1529	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1530	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1531	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	145:64910690c574	1532	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	145:64910690c574	1533	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	145:64910690c574	1534	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	145:64910690c574	1535	*/
AnnaBridge	145:64910690c574	1536	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1537	{
AnnaBridge	145:64910690c574	1538	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	145:64910690c574	1539	}
AnnaBridge	145:64910690c574	1540
AnnaBridge	145:64910690c574	1541	/**
AnnaBridge	145:64910690c574	1542	* @brief Set I2S linear prescaler
AnnaBridge	145:64910690c574	1543	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	145:64910690c574	1544	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1545	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1546	* @retval None
AnnaBridge	145:64910690c574	1547	*/
AnnaBridge	145:64910690c574	1548	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	145:64910690c574	1549	{
AnnaBridge	145:64910690c574	1550	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	145:64910690c574	1551	}
AnnaBridge	145:64910690c574	1552
AnnaBridge	145:64910690c574	1553	/**
AnnaBridge	145:64910690c574	1554	* @brief Get I2S linear prescaler
AnnaBridge	145:64910690c574	1555	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	145:64910690c574	1556	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1557	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1558	*/
AnnaBridge	145:64910690c574	1559	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1560	{
AnnaBridge	145:64910690c574	1561	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	145:64910690c574	1562	}
AnnaBridge	145:64910690c574	1563
AnnaBridge	145:64910690c574	1564	/**
AnnaBridge	145:64910690c574	1565	* @brief Set I2S parity prescaler
AnnaBridge	145:64910690c574	1566	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	145:64910690c574	1567	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1568	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1569	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	145:64910690c574	1570	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	145:64910690c574	1571	* @retval None
AnnaBridge	145:64910690c574	1572	*/
AnnaBridge	145:64910690c574	1573	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	145:64910690c574	1574	{
AnnaBridge	145:64910690c574	1575	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	145:64910690c574	1576	}
AnnaBridge	145:64910690c574	1577
AnnaBridge	145:64910690c574	1578	/**
AnnaBridge	145:64910690c574	1579	* @brief Get I2S parity prescaler
AnnaBridge	145:64910690c574	1580	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	145:64910690c574	1581	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1582	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1583	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	145:64910690c574	1584	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	145:64910690c574	1585	*/
AnnaBridge	145:64910690c574	1586	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1587	{
AnnaBridge	145:64910690c574	1588	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	145:64910690c574	1589	}
AnnaBridge	145:64910690c574	1590
AnnaBridge	145:64910690c574	1591	/**
AnnaBridge	145:64910690c574	1592	* @brief Enable the master clock ouput (Pin MCK)
AnnaBridge	145:64910690c574	1593	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	145:64910690c574	1594	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1595	* @retval None
AnnaBridge	145:64910690c574	1596	*/
AnnaBridge	145:64910690c574	1597	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1598	{
AnnaBridge	145:64910690c574	1599	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	145:64910690c574	1600	}
AnnaBridge	145:64910690c574	1601
AnnaBridge	145:64910690c574	1602	/**
AnnaBridge	145:64910690c574	1603	* @brief Disable the master clock ouput (Pin MCK)
AnnaBridge	145:64910690c574	1604	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	145:64910690c574	1605	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1606	* @retval None
AnnaBridge	145:64910690c574	1607	*/
AnnaBridge	145:64910690c574	1608	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1609	{
AnnaBridge	145:64910690c574	1610	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	145:64910690c574	1611	}
AnnaBridge	145:64910690c574	1612
AnnaBridge	145:64910690c574	1613	/**
AnnaBridge	145:64910690c574	1614	* @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge	145:64910690c574	1615	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	145:64910690c574	1616	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1617	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1618	*/
AnnaBridge	145:64910690c574	1619	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1620	{
AnnaBridge	145:64910690c574	1621	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	145:64910690c574	1622	}
AnnaBridge	145:64910690c574	1623
AnnaBridge	145:64910690c574	1624	/**
AnnaBridge	145:64910690c574	1625	* @}
AnnaBridge	145:64910690c574	1626	*/
AnnaBridge	145:64910690c574	1627
AnnaBridge	145:64910690c574	1628	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	145:64910690c574	1629	* @{
AnnaBridge	145:64910690c574	1630	*/
AnnaBridge	145:64910690c574	1631
AnnaBridge	145:64910690c574	1632	/**
AnnaBridge	145:64910690c574	1633	* @brief Check if Rx buffer is not empty
AnnaBridge	145:64910690c574	1634	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	145:64910690c574	1635	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1636	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1637	*/
AnnaBridge	145:64910690c574	1638	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1639	{
AnnaBridge	145:64910690c574	1640	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	145:64910690c574	1641	}
AnnaBridge	145:64910690c574	1642
AnnaBridge	145:64910690c574	1643	/**
AnnaBridge	145:64910690c574	1644	* @brief Check if Tx buffer is empty
AnnaBridge	145:64910690c574	1645	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	145:64910690c574	1646	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1647	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1648	*/
AnnaBridge	145:64910690c574	1649	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1650	{
AnnaBridge	145:64910690c574	1651	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	145:64910690c574	1652	}
AnnaBridge	145:64910690c574	1653
AnnaBridge	145:64910690c574	1654	/**
AnnaBridge	145:64910690c574	1655	* @brief Get busy flag
AnnaBridge	145:64910690c574	1656	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	145:64910690c574	1657	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1658	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1659	*/
AnnaBridge	145:64910690c574	1660	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1661	{
AnnaBridge	145:64910690c574	1662	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	145:64910690c574	1663	}
AnnaBridge	145:64910690c574	1664
AnnaBridge	145:64910690c574	1665	/**
AnnaBridge	145:64910690c574	1666	* @brief Get overrun error flag
AnnaBridge	145:64910690c574	1667	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	145:64910690c574	1668	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1669	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1670	*/
AnnaBridge	145:64910690c574	1671	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1672	{
AnnaBridge	145:64910690c574	1673	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	145:64910690c574	1674	}
AnnaBridge	145:64910690c574	1675
AnnaBridge	145:64910690c574	1676	/**
AnnaBridge	145:64910690c574	1677	* @brief Get underrun error flag
AnnaBridge	145:64910690c574	1678	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	145:64910690c574	1679	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1680	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1681	*/
AnnaBridge	145:64910690c574	1682	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1683	{
AnnaBridge	145:64910690c574	1684	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	145:64910690c574	1685	}
AnnaBridge	145:64910690c574	1686
AnnaBridge	145:64910690c574	1687	/**
AnnaBridge	145:64910690c574	1688	* @brief Get frame format error flag
AnnaBridge	145:64910690c574	1689	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	145:64910690c574	1690	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1691	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1692	*/
AnnaBridge	145:64910690c574	1693	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1694	{
AnnaBridge	145:64910690c574	1695	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	145:64910690c574	1696	}
AnnaBridge	145:64910690c574	1697
AnnaBridge	145:64910690c574	1698	/**
AnnaBridge	145:64910690c574	1699	* @brief Get channel side flag.
AnnaBridge	145:64910690c574	1700	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	145:64910690c574	1701	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	145:64910690c574	1702	* It has no significance in PCM mode.
AnnaBridge	145:64910690c574	1703	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	145:64910690c574	1704	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1705	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1706	*/
AnnaBridge	145:64910690c574	1707	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1708	{
AnnaBridge	145:64910690c574	1709	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	145:64910690c574	1710	}
AnnaBridge	145:64910690c574	1711
AnnaBridge	145:64910690c574	1712	/**
AnnaBridge	145:64910690c574	1713	* @brief Clear overrun error flag
AnnaBridge	145:64910690c574	1714	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	145:64910690c574	1715	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1716	* @retval None
AnnaBridge	145:64910690c574	1717	*/
AnnaBridge	145:64910690c574	1718	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1719	{
AnnaBridge	145:64910690c574	1720	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	145:64910690c574	1721	}
AnnaBridge	145:64910690c574	1722
AnnaBridge	145:64910690c574	1723	/**
AnnaBridge	145:64910690c574	1724	* @brief Clear underrun error flag
AnnaBridge	145:64910690c574	1725	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	145:64910690c574	1726	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1727	* @retval None
AnnaBridge	145:64910690c574	1728	*/
AnnaBridge	145:64910690c574	1729	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1730	{
AnnaBridge	145:64910690c574	1731	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1732	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	1733	(void)tmpreg;
AnnaBridge	145:64910690c574	1734	}
AnnaBridge	145:64910690c574	1735
AnnaBridge	145:64910690c574	1736	/**
AnnaBridge	145:64910690c574	1737	* @brief Clear frame format error flag
AnnaBridge	145:64910690c574	1738	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge	145:64910690c574	1739	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1740	* @retval None
AnnaBridge	145:64910690c574	1741	*/
AnnaBridge	145:64910690c574	1742	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1743	{
AnnaBridge	145:64910690c574	1744	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	145:64910690c574	1745	}
AnnaBridge	145:64910690c574	1746
AnnaBridge	145:64910690c574	1747	/**
AnnaBridge	145:64910690c574	1748	* @}
AnnaBridge	145:64910690c574	1749	*/
AnnaBridge	145:64910690c574	1750
AnnaBridge	145:64910690c574	1751	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	145:64910690c574	1752	* @{
AnnaBridge	145:64910690c574	1753	*/
AnnaBridge	145:64910690c574	1754
AnnaBridge	145:64910690c574	1755	/**
AnnaBridge	145:64910690c574	1756	* @brief Enable error IT
AnnaBridge	145:64910690c574	1757	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	145:64910690c574	1758	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	145:64910690c574	1759	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1760	* @retval None
AnnaBridge	145:64910690c574	1761	*/
AnnaBridge	145:64910690c574	1762	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1763	{
AnnaBridge	145:64910690c574	1764	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	145:64910690c574	1765	}
AnnaBridge	145:64910690c574	1766
AnnaBridge	145:64910690c574	1767	/**
AnnaBridge	145:64910690c574	1768	* @brief Enable Rx buffer not empty IT
AnnaBridge	145:64910690c574	1769	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	145:64910690c574	1770	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1771	* @retval None
AnnaBridge	145:64910690c574	1772	*/
AnnaBridge	145:64910690c574	1773	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1774	{
AnnaBridge	145:64910690c574	1775	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	145:64910690c574	1776	}
AnnaBridge	145:64910690c574	1777
AnnaBridge	145:64910690c574	1778	/**
AnnaBridge	145:64910690c574	1779	* @brief Enable Tx buffer empty IT
AnnaBridge	145:64910690c574	1780	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	145:64910690c574	1781	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1782	* @retval None
AnnaBridge	145:64910690c574	1783	*/
AnnaBridge	145:64910690c574	1784	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1785	{
AnnaBridge	145:64910690c574	1786	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	145:64910690c574	1787	}
AnnaBridge	145:64910690c574	1788
AnnaBridge	145:64910690c574	1789	/**
AnnaBridge	145:64910690c574	1790	* @brief Disable error IT
AnnaBridge	145:64910690c574	1791	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	145:64910690c574	1792	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	145:64910690c574	1793	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1794	* @retval None
AnnaBridge	145:64910690c574	1795	*/
AnnaBridge	145:64910690c574	1796	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1797	{
AnnaBridge	145:64910690c574	1798	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	145:64910690c574	1799	}
AnnaBridge	145:64910690c574	1800
AnnaBridge	145:64910690c574	1801	/**
AnnaBridge	145:64910690c574	1802	* @brief Disable Rx buffer not empty IT
AnnaBridge	145:64910690c574	1803	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	145:64910690c574	1804	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1805	* @retval None
AnnaBridge	145:64910690c574	1806	*/
AnnaBridge	145:64910690c574	1807	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1808	{
AnnaBridge	145:64910690c574	1809	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	145:64910690c574	1810	}
AnnaBridge	145:64910690c574	1811
AnnaBridge	145:64910690c574	1812	/**
AnnaBridge	145:64910690c574	1813	* @brief Disable Tx buffer empty IT
AnnaBridge	145:64910690c574	1814	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	145:64910690c574	1815	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1816	* @retval None
AnnaBridge	145:64910690c574	1817	*/
AnnaBridge	145:64910690c574	1818	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1819	{
AnnaBridge	145:64910690c574	1820	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	145:64910690c574	1821	}
AnnaBridge	145:64910690c574	1822
AnnaBridge	145:64910690c574	1823	/**
AnnaBridge	145:64910690c574	1824	* @brief Check if ERR IT is enabled
AnnaBridge	145:64910690c574	1825	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	145:64910690c574	1826	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1827	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1828	*/
AnnaBridge	145:64910690c574	1829	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1830	{
AnnaBridge	145:64910690c574	1831	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	145:64910690c574	1832	}
AnnaBridge	145:64910690c574	1833
AnnaBridge	145:64910690c574	1834	/**
AnnaBridge	145:64910690c574	1835	* @brief Check if RXNE IT is enabled
AnnaBridge	145:64910690c574	1836	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	145:64910690c574	1837	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1838	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1839	*/
AnnaBridge	145:64910690c574	1840	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1841	{
AnnaBridge	145:64910690c574	1842	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	145:64910690c574	1843	}
AnnaBridge	145:64910690c574	1844
AnnaBridge	145:64910690c574	1845	/**
AnnaBridge	145:64910690c574	1846	* @brief Check if TXE IT is enabled
AnnaBridge	145:64910690c574	1847	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	145:64910690c574	1848	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1849	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1850	*/
AnnaBridge	145:64910690c574	1851	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1852	{
AnnaBridge	145:64910690c574	1853	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	145:64910690c574	1854	}
AnnaBridge	145:64910690c574	1855
AnnaBridge	145:64910690c574	1856	/**
AnnaBridge	145:64910690c574	1857	* @}
AnnaBridge	145:64910690c574	1858	*/
AnnaBridge	145:64910690c574	1859
AnnaBridge	145:64910690c574	1860	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	145:64910690c574	1861	* @{
AnnaBridge	145:64910690c574	1862	*/
AnnaBridge	145:64910690c574	1863
AnnaBridge	145:64910690c574	1864	/**
AnnaBridge	145:64910690c574	1865	* @brief Enable DMA Rx
AnnaBridge	145:64910690c574	1866	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	145:64910690c574	1867	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1868	* @retval None
AnnaBridge	145:64910690c574	1869	*/
AnnaBridge	145:64910690c574	1870	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1871	{
AnnaBridge	145:64910690c574	1872	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	145:64910690c574	1873	}
AnnaBridge	145:64910690c574	1874
AnnaBridge	145:64910690c574	1875	/**
AnnaBridge	145:64910690c574	1876	* @brief Disable DMA Rx
AnnaBridge	145:64910690c574	1877	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	145:64910690c574	1878	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1879	* @retval None
AnnaBridge	145:64910690c574	1880	*/
AnnaBridge	145:64910690c574	1881	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1882	{
AnnaBridge	145:64910690c574	1883	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	145:64910690c574	1884	}
AnnaBridge	145:64910690c574	1885
AnnaBridge	145:64910690c574	1886	/**
AnnaBridge	145:64910690c574	1887	* @brief Check if DMA Rx is enabled
AnnaBridge	145:64910690c574	1888	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	145:64910690c574	1889	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1890	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1891	*/
AnnaBridge	145:64910690c574	1892	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1893	{
AnnaBridge	145:64910690c574	1894	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	145:64910690c574	1895	}
AnnaBridge	145:64910690c574	1896
AnnaBridge	145:64910690c574	1897	/**
AnnaBridge	145:64910690c574	1898	* @brief Enable DMA Tx
AnnaBridge	145:64910690c574	1899	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	145:64910690c574	1900	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1901	* @retval None
AnnaBridge	145:64910690c574	1902	*/
AnnaBridge	145:64910690c574	1903	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1904	{
AnnaBridge	145:64910690c574	1905	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	145:64910690c574	1906	}
AnnaBridge	145:64910690c574	1907
AnnaBridge	145:64910690c574	1908	/**
AnnaBridge	145:64910690c574	1909	* @brief Disable DMA Tx
AnnaBridge	145:64910690c574	1910	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	145:64910690c574	1911	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1912	* @retval None
AnnaBridge	145:64910690c574	1913	*/
AnnaBridge	145:64910690c574	1914	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1915	{
AnnaBridge	145:64910690c574	1916	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	145:64910690c574	1917	}
AnnaBridge	145:64910690c574	1918
AnnaBridge	145:64910690c574	1919	/**
AnnaBridge	145:64910690c574	1920	* @brief Check if DMA Tx is enabled
AnnaBridge	145:64910690c574	1921	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	145:64910690c574	1922	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1923	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1924	*/
AnnaBridge	145:64910690c574	1925	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1926	{
AnnaBridge	145:64910690c574	1927	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	145:64910690c574	1928	}
AnnaBridge	145:64910690c574	1929
AnnaBridge	145:64910690c574	1930	/**
AnnaBridge	145:64910690c574	1931	* @}
AnnaBridge	145:64910690c574	1932	*/
AnnaBridge	145:64910690c574	1933
AnnaBridge	145:64910690c574	1934	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	145:64910690c574	1935	* @{
AnnaBridge	145:64910690c574	1936	*/
AnnaBridge	145:64910690c574	1937
AnnaBridge	145:64910690c574	1938	/**
AnnaBridge	145:64910690c574	1939	* @brief Read 16-Bits in data register
AnnaBridge	145:64910690c574	1940	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	145:64910690c574	1941	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1942	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1943	*/
AnnaBridge	145:64910690c574	1944	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1945	{
AnnaBridge	145:64910690c574	1946	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	145:64910690c574	1947	}
AnnaBridge	145:64910690c574	1948
AnnaBridge	145:64910690c574	1949	/**
AnnaBridge	145:64910690c574	1950	* @brief Write 16-Bits in data register
AnnaBridge	145:64910690c574	1951	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	145:64910690c574	1952	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1953	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1954	* @retval None
AnnaBridge	145:64910690c574	1955	*/
AnnaBridge	145:64910690c574	1956	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	145:64910690c574	1957	{
AnnaBridge	145:64910690c574	1958	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	145:64910690c574	1959	}
AnnaBridge	145:64910690c574	1960
AnnaBridge	145:64910690c574	1961	/**
AnnaBridge	145:64910690c574	1962	* @}
AnnaBridge	145:64910690c574	1963	*/
AnnaBridge	145:64910690c574	1964
AnnaBridge	145:64910690c574	1965	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1966	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	1967	* @{
AnnaBridge	145:64910690c574	1968	*/
AnnaBridge	145:64910690c574	1969
AnnaBridge	145:64910690c574	1970	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	145:64910690c574	1971	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	145:64910690c574	1972	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	145:64910690c574	1973	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	145:64910690c574	1974
AnnaBridge	145:64910690c574	1975	/**
AnnaBridge	145:64910690c574	1976	* @}
AnnaBridge	145:64910690c574	1977	*/
AnnaBridge	145:64910690c574	1978	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	1979
AnnaBridge	145:64910690c574	1980	/**
AnnaBridge	145:64910690c574	1981	* @}
AnnaBridge	145:64910690c574	1982	*/
AnnaBridge	145:64910690c574	1983
AnnaBridge	145:64910690c574	1984	/**
AnnaBridge	145:64910690c574	1985	* @}
AnnaBridge	145:64910690c574	1986	*/
AnnaBridge	145:64910690c574	1987
AnnaBridge	145:64910690c574	1988	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) */
AnnaBridge	145:64910690c574	1989
AnnaBridge	145:64910690c574	1990	/**
AnnaBridge	145:64910690c574	1991	* @}
AnnaBridge	145:64910690c574	1992	*/
AnnaBridge	145:64910690c574	1993
AnnaBridge	145:64910690c574	1994	#ifdef __cplusplus
AnnaBridge	145:64910690c574	1995	}
AnnaBridge	145:64910690c574	1996	#endif
AnnaBridge	145:64910690c574	1997
AnnaBridge	145:64910690c574	1998	#endif /* __STM32F2xx_LL_SPI_H */
AnnaBridge	145:64910690c574	1999
AnnaBridge	145:64910690c574	2000	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/