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TARGET_NCS36510/TOOLCHAIN_GCC_ARM/uart_16c550_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file uart_16c550_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief UART module hardware register map.
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor.
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 2615 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup uart_16c550
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 * <h1> Reference document(s) </h1>
AnnaBridge 171:3a7713b1edbc 31 * <p>
AnnaBridge 171:3a7713b1edbc 32 * <a href="../pdf/IPC7202_UART_APB_DS_v1P4.pdf" target="_blank">
AnnaBridge 171:3a7713b1edbc 33 * IPC7202 APB UART Design Specification v1.4 </a>
AnnaBridge 171:3a7713b1edbc 34 * </p>
AnnaBridge 171:3a7713b1edbc 35 */
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifndef UART_16C550_MAP_H_
AnnaBridge 171:3a7713b1edbc 38 #define UART_16C550_MAP_H_
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 43 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 44 #endif
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 #define DCTS (uint8_t)0x01
AnnaBridge 171:3a7713b1edbc 47 #define DDSR (uint8_t)0x02
AnnaBridge 171:3a7713b1edbc 48 #define TERI (uint8_t)0x04
AnnaBridge 171:3a7713b1edbc 49 #define DDCD (uint8_t)0x08
AnnaBridge 171:3a7713b1edbc 50 //#define CTS (uint8_t)0x10
AnnaBridge 171:3a7713b1edbc 51 #define DSR (uint8_t)0x20
AnnaBridge 171:3a7713b1edbc 52 #define RI (uint8_t)0x40
AnnaBridge 171:3a7713b1edbc 53 #define DCD (uint8_t)0x80
AnnaBridge 171:3a7713b1edbc 54 #define IER_PWRDNENACTIVE ((uint8_t)(1<<5))
AnnaBridge 171:3a7713b1edbc 55 #define IER_MSI ((uint8_t)(1<<3))
AnnaBridge 171:3a7713b1edbc 56 #define IER_RLSI ((uint8_t)(1<<2))
AnnaBridge 171:3a7713b1edbc 57 #define IER_THRI ((uint8_t)(1<<1))
AnnaBridge 171:3a7713b1edbc 58 #define IER_RDAI ((uint8_t)(1<<0))
AnnaBridge 171:3a7713b1edbc 59 #define FCR_RXFIFOTRIGGERLEVEL_1 ((uint8_t)(0x00))
AnnaBridge 171:3a7713b1edbc 60 #define FCR_RXFIFOTRIGGERLEVEL_4 ((uint8_t)(0x40))
AnnaBridge 171:3a7713b1edbc 61 #define FCR_RXFIFOTRIGGERLEVEL_8 ((uint8_t)(0x80))
AnnaBridge 171:3a7713b1edbc 62 #define FCR_RXFIFOTRIGGERLEVEL_14 ((uint8_t)(0xC0))
AnnaBridge 171:3a7713b1edbc 63 #define FCR_DMA_MODE_0 ((uint8_t)(0<<3))
AnnaBridge 171:3a7713b1edbc 64 #define FCR_DMA_MODE_1 ((uint8_t)(1<<3))
AnnaBridge 171:3a7713b1edbc 65 #define FCR_TXFIFO_RESET ((uint8_t)(1<<2))
AnnaBridge 171:3a7713b1edbc 66 #define FCR_RXFIFO_RESET ((uint8_t)(1<<1))
AnnaBridge 171:3a7713b1edbc 67 #define FCR_FIFO_ENABLE ((uint8_t)(1<<0))
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 /** UART HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 70 typedef struct {
AnnaBridge 171:3a7713b1edbc 71 /** Base address + 0x0: Receive, transmit and divisor_LSB offset */
AnnaBridge 171:3a7713b1edbc 72 union {
AnnaBridge 171:3a7713b1edbc 73 __I uint32_t RBR; /**< Received data (8 bits wide) / read only */
AnnaBridge 171:3a7713b1edbc 74 __O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */
AnnaBridge 171:3a7713b1edbc 76 };
AnnaBridge 171:3a7713b1edbc 77 /** Base address + 0x4: Interrupt enable and divisor_MSB offset */
AnnaBridge 171:3a7713b1edbc 78 union {
AnnaBridge 171:3a7713b1edbc 79 union {
AnnaBridge 171:3a7713b1edbc 80 struct {
AnnaBridge 171:3a7713b1edbc 81 __IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t PAD0 :1;
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t PAD1 :2;
AnnaBridge 171:3a7713b1edbc 88 } BITS;
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 90 } IER; /** Interrupt enable offset 0x04 */
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */
AnnaBridge 171:3a7713b1edbc 92 };
AnnaBridge 171:3a7713b1edbc 93 /** Base address + 0x8: Interrupt status and fifo control offset*/
AnnaBridge 171:3a7713b1edbc 94 union {
AnnaBridge 171:3a7713b1edbc 95 union {
AnnaBridge 171:3a7713b1edbc 96 struct {
AnnaBridge 171:3a7713b1edbc 97 __I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */
AnnaBridge 171:3a7713b1edbc 98 __I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/
AnnaBridge 171:3a7713b1edbc 99 __I uint32_t PAD0 :2;
AnnaBridge 171:3a7713b1edbc 100 __I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */
AnnaBridge 171:3a7713b1edbc 101 } BITS;
AnnaBridge 171:3a7713b1edbc 102 __I uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 103 } IIR; /** Interrupt status and fifo status offset 0x08 */
AnnaBridge 171:3a7713b1edbc 104 union {
AnnaBridge 171:3a7713b1edbc 105 struct {
AnnaBridge 171:3a7713b1edbc 106 __O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */
AnnaBridge 171:3a7713b1edbc 107 __O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */
AnnaBridge 171:3a7713b1edbc 108 __O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */
AnnaBridge 171:3a7713b1edbc 109 __O uint32_t DMA_SEL :1; /**< DMA mode select */
AnnaBridge 171:3a7713b1edbc 110 __O uint32_t PAD0 :2;
AnnaBridge 171:3a7713b1edbc 111 __O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */
AnnaBridge 171:3a7713b1edbc 112 } BITS;
AnnaBridge 171:3a7713b1edbc 113 __O uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 114 } FCR; /** Fifo control offset 0x08 */
AnnaBridge 171:3a7713b1edbc 115 };
AnnaBridge 171:3a7713b1edbc 116 /** Base address + 0xC: Line control offset */
AnnaBridge 171:3a7713b1edbc 117 union {
AnnaBridge 171:3a7713b1edbc 118 struct {
AnnaBridge 171:3a7713b1edbc 119 __IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */
AnnaBridge 171:3a7713b1edbc 120 __IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */
AnnaBridge 171:3a7713b1edbc 121 __IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */
AnnaBridge 171:3a7713b1edbc 122 __IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */
AnnaBridge 171:3a7713b1edbc 123 __IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */
AnnaBridge 171:3a7713b1edbc 124 } BITS;
AnnaBridge 171:3a7713b1edbc 125 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 126 } LCR; /** Line control offset 0x0C */
AnnaBridge 171:3a7713b1edbc 127 /** Base address + 0x10: Modem control offset */
AnnaBridge 171:3a7713b1edbc 128 union {
AnnaBridge 171:3a7713b1edbc 129 struct {
AnnaBridge 171:3a7713b1edbc 130 __IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */
AnnaBridge 171:3a7713b1edbc 131 __IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */
AnnaBridge 171:3a7713b1edbc 132 __IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */
AnnaBridge 171:3a7713b1edbc 133 __IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */
AnnaBridge 171:3a7713b1edbc 134 __IO uint32_t PAD0 :3;
AnnaBridge 171:3a7713b1edbc 135 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */
AnnaBridge 171:3a7713b1edbc 136 } BITS;
AnnaBridge 171:3a7713b1edbc 137 __IO uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 138 } MCR; /**< Modem control offset 0x10 */
AnnaBridge 171:3a7713b1edbc 139 /** Base address + 0x14: Line status offset */
AnnaBridge 171:3a7713b1edbc 140 union {
AnnaBridge 171:3a7713b1edbc 141 struct {
AnnaBridge 171:3a7713b1edbc 142 __O uint32_t READY :1; /**< Rx data available */
AnnaBridge 171:3a7713b1edbc 143 __O uint32_t OVERRUN_ERR :1; /**< Overrun error */
AnnaBridge 171:3a7713b1edbc 144 __O uint32_t PARITY_ERR :1; /**< Parity error */
AnnaBridge 171:3a7713b1edbc 145 __O uint32_t FRAME_ERR :1; /**< Framing error */
AnnaBridge 171:3a7713b1edbc 146 __O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */
AnnaBridge 171:3a7713b1edbc 147 __O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */
AnnaBridge 171:3a7713b1edbc 148 __O uint32_t TX_EMPTY :1; /**< Transmitter empty */
AnnaBridge 171:3a7713b1edbc 149 __O uint32_t FIFO_ERR :1; /**< Receive fifo error */
AnnaBridge 171:3a7713b1edbc 150 } BITS;
AnnaBridge 171:3a7713b1edbc 151 __O uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 152 } LSR; /**< Line status offset 0x14 */
AnnaBridge 171:3a7713b1edbc 153 /** Base address + 0x18: Modem status offset */
AnnaBridge 171:3a7713b1edbc 154 union {
AnnaBridge 171:3a7713b1edbc 155 struct {
AnnaBridge 171:3a7713b1edbc 156 __O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */
AnnaBridge 171:3a7713b1edbc 157 __O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */
AnnaBridge 171:3a7713b1edbc 158 __O uint32_t CHG_RIN :1; /**< RI change since last MSR read */
AnnaBridge 171:3a7713b1edbc 159 __O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */
AnnaBridge 171:3a7713b1edbc 160 __O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */
AnnaBridge 171:3a7713b1edbc 161 __O uint32_t CURR_DSRN :1; /**< DSR current state */
AnnaBridge 171:3a7713b1edbc 162 __O uint32_t CURR_RIN :1; /**< RI current state */
AnnaBridge 171:3a7713b1edbc 163 __O uint32_t CURR_DCDN :1; /**< DCD current state */
AnnaBridge 171:3a7713b1edbc 164 } BITS;
AnnaBridge 171:3a7713b1edbc 165 __O uint32_t WORD;
AnnaBridge 171:3a7713b1edbc 166 } MSR; /**< Modem status offset 0x18 */
AnnaBridge 171:3a7713b1edbc 167 /** Base address + 0x1C: Scratch offset*/
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t SCR; /**< Scratch pad register */
AnnaBridge 171:3a7713b1edbc 169 } Uart16C550Reg_t, *Uart16C550Reg_pt;
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 #endif /* UART_16C550_MAP_H_ */