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TARGET_NCS36510/TOOLCHAIN_GCC_ARM/objects.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file Objects.h
AnnaBridge 171:3a7713b1edbc 4 * @brief Implements an assertion.
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 0.1 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2015-11-06 $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup debug
AnnaBridge 171:3a7713b1edbc 28 */
AnnaBridge 171:3a7713b1edbc 29 #ifndef OBJECTS_H_
AnnaBridge 171:3a7713b1edbc 30 #define OBJECTS_H_
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 34 extern "C" {
AnnaBridge 171:3a7713b1edbc 35 #endif
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #include "gpio_map.h"
AnnaBridge 171:3a7713b1edbc 38 #include "uart_16c550_map.h"
AnnaBridge 171:3a7713b1edbc 39 #include "PinNames.h"
AnnaBridge 171:3a7713b1edbc 40 #include "PortNames.h"
AnnaBridge 171:3a7713b1edbc 41 #include "PeripheralNames.h"
AnnaBridge 171:3a7713b1edbc 42 #include "target_config.h"
AnnaBridge 171:3a7713b1edbc 43 #include "spi.h"
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 typedef enum {
AnnaBridge 171:3a7713b1edbc 46 FlowControlNone_1,
AnnaBridge 171:3a7713b1edbc 47 FlowControlRTS_1,
AnnaBridge 171:3a7713b1edbc 48 FlowControlCTS_1,
AnnaBridge 171:3a7713b1edbc 49 FlowControlRTSCTS_1
AnnaBridge 171:3a7713b1edbc 50 } FlowControl_1;
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 struct serial_s {
AnnaBridge 171:3a7713b1edbc 53 Uart16C550Reg_pt UARTREG;
AnnaBridge 171:3a7713b1edbc 54 FlowControl_1 FlowCtrl;
AnnaBridge 171:3a7713b1edbc 55 IRQn_Type IRQType;
AnnaBridge 171:3a7713b1edbc 56 int index;
AnnaBridge 171:3a7713b1edbc 57 };
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 typedef struct _gpio_t {
AnnaBridge 171:3a7713b1edbc 60 GpioReg_pt GPIOMEMBASE;
AnnaBridge 171:3a7713b1edbc 61 PinName gpioPin;
AnnaBridge 171:3a7713b1edbc 62 uint32_t gpioMask;
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 } gpio_t;
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /* TODO: This is currently a dummy structure; implementation will be done along
AnnaBridge 171:3a7713b1edbc 68 * with the sleep API implementation
AnnaBridge 171:3a7713b1edbc 69 */
AnnaBridge 171:3a7713b1edbc 70 typedef struct sleep_s {
AnnaBridge 171:3a7713b1edbc 71 uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
AnnaBridge 171:3a7713b1edbc 72 uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
AnnaBridge 171:3a7713b1edbc 73 } sleep_t;
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /* Table 1. Sleep
AnnaBridge 171:3a7713b1edbc 76 ___________________________________________________________________________________
AnnaBridge 171:3a7713b1edbc 77 | Sleep duration | Sleep Type |
AnnaBridge 171:3a7713b1edbc 78 |-------------------------------------------------------------------|---------------|
AnnaBridge 171:3a7713b1edbc 79 | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
AnnaBridge 171:3a7713b1edbc 80 | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
AnnaBridge 171:3a7713b1edbc 81 | > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
AnnaBridge 171:3a7713b1edbc 82 |___________________________________________________________________|_______________|
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 */
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 struct gpio_irq_s {
AnnaBridge 171:3a7713b1edbc 87 uint32_t pin;
AnnaBridge 171:3a7713b1edbc 88 uint32_t pinMask;
AnnaBridge 171:3a7713b1edbc 89 GpioReg_pt GPIOMEMBASE;
AnnaBridge 171:3a7713b1edbc 90 };
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 typedef struct {
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 /* options to configure the ADC */
AnnaBridge 171:3a7713b1edbc 95 uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
AnnaBridge 171:3a7713b1edbc 96 uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
AnnaBridge 171:3a7713b1edbc 97 uint8_t measurementType; /**< 1= Absolute 0= Differential */
AnnaBridge 171:3a7713b1edbc 98 uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
AnnaBridge 171:3a7713b1edbc 99 uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
AnnaBridge 171:3a7713b1edbc 100 uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
AnnaBridge 171:3a7713b1edbc 101 uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
AnnaBridge 171:3a7713b1edbc 102 uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
AnnaBridge 171:3a7713b1edbc 103 uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
AnnaBridge 171:3a7713b1edbc 104 uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 } analog_config_s;
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 struct analogin_s {
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 analog_config_s *adcConf;
AnnaBridge 171:3a7713b1edbc 111 AdcReg_pt adcReg;
AnnaBridge 171:3a7713b1edbc 112 PinName pin;
AnnaBridge 171:3a7713b1edbc 113 uint8_t pinFlag;
AnnaBridge 171:3a7713b1edbc 114 uint32_t ADC_Offset_Value;
AnnaBridge 171:3a7713b1edbc 115 };
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 struct pwmout_s {
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 PwmReg_pt pwmReg;
AnnaBridge 171:3a7713b1edbc 120 };
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 struct port_s {
AnnaBridge 171:3a7713b1edbc 123 GpioReg_pt GPIOMEMBASE;
AnnaBridge 171:3a7713b1edbc 124 PortName port;
AnnaBridge 171:3a7713b1edbc 125 uint32_t mask;
AnnaBridge 171:3a7713b1edbc 126 };
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 typedef enum {
AnnaBridge 171:3a7713b1edbc 129 littleEndian = 0,
AnnaBridge 171:3a7713b1edbc 130 bigEndian
AnnaBridge 171:3a7713b1edbc 131 } spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /** Type for the clock polarity. */
AnnaBridge 171:3a7713b1edbc 134 typedef enum {
AnnaBridge 171:3a7713b1edbc 135 activeLow = 0,
AnnaBridge 171:3a7713b1edbc 136 activeHigh
AnnaBridge 171:3a7713b1edbc 137 } spi_clockPolarity_t, *spi_clockPolarity_pt;
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /** Type for the clock phase. */
AnnaBridge 171:3a7713b1edbc 140 typedef enum {
AnnaBridge 171:3a7713b1edbc 141 risingEdge = 0,
AnnaBridge 171:3a7713b1edbc 142 fallingEdge
AnnaBridge 171:3a7713b1edbc 143 } spi_clockPhase_t, *spi_clockPhase_pt;
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 struct spi_s {
AnnaBridge 171:3a7713b1edbc 146 SpiIpc7207Reg_pt membase; /* Register address */
AnnaBridge 171:3a7713b1edbc 147 IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
AnnaBridge 171:3a7713b1edbc 148 uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
AnnaBridge 171:3a7713b1edbc 149 * - bit 7 = Receive FIFO Full
AnnaBridge 171:3a7713b1edbc 150 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
AnnaBridge 171:3a7713b1edbc 151 * - bit 5 = Receive FIFO Not Empty
AnnaBridge 171:3a7713b1edbc 152 * - bit 4 = Transmit FIFO Not Full
AnnaBridge 171:3a7713b1edbc 153 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
AnnaBridge 171:3a7713b1edbc 154 * - bit 2 = Transmit FIFO Empty
AnnaBridge 171:3a7713b1edbc 155 * - bit 1 = Transfer Error
AnnaBridge 171:3a7713b1edbc 156 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
AnnaBridge 171:3a7713b1edbc 157 * (unused option in current implementation / irq 6 and 7 used) */
AnnaBridge 171:3a7713b1edbc 158 uint8_t slaveSelectEnable; /* Slave Select enables (x4):
AnnaBridge 171:3a7713b1edbc 159 * - 0 (x4) = Slave select enable
AnnaBridge 171:3a7713b1edbc 160 * - 1 (x4) = Slave select disable */
AnnaBridge 171:3a7713b1edbc 161 uint8_t slaveSelectBurst; /* Slave Select burst mode:
AnnaBridge 171:3a7713b1edbc 162 * - NO_BURST_MODE = Burst mode disable
AnnaBridge 171:3a7713b1edbc 163 * - BURST_MODE = Burst mode enable */
AnnaBridge 171:3a7713b1edbc 164 uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves:
AnnaBridge 171:3a7713b1edbc 165 * - 0 (x4) = Slave select is active low
AnnaBridge 171:3a7713b1edbc 166 * - 1 (x4) = Slave select is active high */
AnnaBridge 171:3a7713b1edbc 167 uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
AnnaBridge 171:3a7713b1edbc 168 * - Value between 1 and 15
AnnaBridge 171:3a7713b1edbc 169 * (unused option in current implementation / not txWatermark irq used) */
AnnaBridge 171:3a7713b1edbc 170 uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
AnnaBridge 171:3a7713b1edbc 171 * - Value between 1 and 15
AnnaBridge 171:3a7713b1edbc 172 * * (unused option in current implementation / rxWatermark fixed to 1) */
AnnaBridge 171:3a7713b1edbc 173 spi_ipc7207_endian_t endian; /* Bits endianness:
AnnaBridge 171:3a7713b1edbc 174 * - LITTLE_ENDIAN = LSB first
AnnaBridge 171:3a7713b1edbc 175 * - BIG_ENDIAN = MSB first */
AnnaBridge 171:3a7713b1edbc 176 uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
AnnaBridge 171:3a7713b1edbc 177 * - 0 = opposite to SDO sampling edge
AnnaBridge 171:3a7713b1edbc 178 * - 1 = same as SDO sampling edge */
AnnaBridge 171:3a7713b1edbc 179 uint32_t baudrate; /* The expected baud rate. */
AnnaBridge 171:3a7713b1edbc 180 spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
AnnaBridge 171:3a7713b1edbc 181 spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
AnnaBridge 171:3a7713b1edbc 182 uint8_t wordSize; /* The size word size in number of bits. */
AnnaBridge 171:3a7713b1edbc 183 uint8_t Mode;
AnnaBridge 171:3a7713b1edbc 184 uint32_t event;
AnnaBridge 171:3a7713b1edbc 185 };
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 struct i2c_s {
AnnaBridge 171:3a7713b1edbc 188 uint32_t baudrate; /**< The expected baud rate. */
AnnaBridge 171:3a7713b1edbc 189 uint32_t I2cStatusFromInt;
AnnaBridge 171:3a7713b1edbc 190 uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
AnnaBridge 171:3a7713b1edbc 191 uint8_t irqEnable; /**< IRQs to be enabled */
AnnaBridge 171:3a7713b1edbc 192 I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
AnnaBridge 171:3a7713b1edbc 193 IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
AnnaBridge 171:3a7713b1edbc 194 //queue_pt rxQueue; /**< The receive queue for the device instance. */
AnnaBridge 171:3a7713b1edbc 195 };
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 struct trng_s {
AnnaBridge 171:3a7713b1edbc 198 RandReg_pt membase; /**< The memory base for the device's registers. */
AnnaBridge 171:3a7713b1edbc 199 };
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 202 }
AnnaBridge 171:3a7713b1edbc 203 #endif
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 #endif //OBJECTS_H_