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TARGET_NCS36510/TOOLCHAIN_GCC_ARM/memory_map.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file memory_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief Defines the silicon memory map. All peripheral devices shall be mapped in structures.
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 3525 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup bsp
AnnaBridge 171:3a7713b1edbc 28 @verbatim
AnnaBridge 171:3a7713b1edbc 29 +-----------------+
AnnaBridge 171:3a7713b1edbc 30 | | ,_________________________
AnnaBridge 171:3a7713b1edbc 31 | Private Per. | |PMUREG 0x4001D000|
AnnaBridge 171:3a7713b1edbc 32 0xE0000000 +-----------------+ |PADREG 0x4001C000|
AnnaBridge 171:3a7713b1edbc 33 | |_____________|CLOCKREG 0x4001B000|
AnnaBridge 171:3a7713b1edbc 34 | PERIPHERALS | |RFANAREG 0x40019000|
AnnaBridge 171:3a7713b1edbc 35 +-----------------+ |RESETREG 0x40018000|
AnnaBridge 171:3a7713b1edbc 36 | | |FLASHREG 0x40017000|
AnnaBridge 171:3a7713b1edbc 37 0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000|
AnnaBridge 171:3a7713b1edbc 38 +-----------------+ |ADCREG 0x40015000|
AnnaBridge 171:3a7713b1edbc 39 | | |MACHWREG 0x40014000|
AnnaBridge 171:3a7713b1edbc 40 |SRAM B 16K | |RANDREG 0x40011000|
AnnaBridge 171:3a7713b1edbc 41 0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000|
AnnaBridge 171:3a7713b1edbc 42 | | |RTCREG 0x4000F000|
AnnaBridge 171:3a7713b1edbc 43 0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000|
AnnaBridge 171:3a7713b1edbc 44 +-----------------+ |PWMREG 0x4000B000|
AnnaBridge 171:3a7713b1edbc 45 0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000|
AnnaBridge 171:3a7713b1edbc 46 +-----------------+ |UARTREG 0x40008000|
AnnaBridge 171:3a7713b1edbc 47 | 320K | |I2CREG 0x40007000|
AnnaBridge 171:3a7713b1edbc 48 0x00102000 |FLASHB | |SPIREG 0x40006000|
AnnaBridge 171:3a7713b1edbc 49 0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000|
AnnaBridge 171:3a7713b1edbc 50 +-----------------+ |TIM2REG 0x40002000|
AnnaBridge 171:3a7713b1edbc 51 | 320K | |TIM1REG 0x40001000|
AnnaBridge 171:3a7713b1edbc 52 0x00002000 |FLASHA | |TIM0REG 0x40000000|
AnnaBridge 171:3a7713b1edbc 53 0x00000000 |FLASHA Inf Block | '`''''''''''''''''''''''''
AnnaBridge 171:3a7713b1edbc 54 '`'''''''''''''''''
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 @endverbatim
AnnaBridge 171:3a7713b1edbc 57 */
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 #ifndef _MEMORY_MAP_H_
AnnaBridge 171:3a7713b1edbc 60 #define _MEMORY_MAP_H_
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /*************************************************************************************************
AnnaBridge 171:3a7713b1edbc 63 * *
AnnaBridge 171:3a7713b1edbc 64 * Header files *
AnnaBridge 171:3a7713b1edbc 65 * *
AnnaBridge 171:3a7713b1edbc 66 *************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 // Register maps of HW modules controlled with device drivers
AnnaBridge 171:3a7713b1edbc 73 #include "adc_sar_map.h"
AnnaBridge 171:3a7713b1edbc 74 #include "aes_map.h"
AnnaBridge 171:3a7713b1edbc 75 #include "flash_map.h"
AnnaBridge 171:3a7713b1edbc 76 #include "gpio_map.h"
AnnaBridge 171:3a7713b1edbc 77 #include "i2c_ipc7208_map.h"
AnnaBridge 171:3a7713b1edbc 78 #include "pwm_map.h"
AnnaBridge 171:3a7713b1edbc 79 #include "rtc_map.h"
AnnaBridge 171:3a7713b1edbc 80 #include "spi_ipc7207_map.h"
AnnaBridge 171:3a7713b1edbc 81 #include "timer_map.h"
AnnaBridge 171:3a7713b1edbc 82 #include "uart_16c550_map.h"
AnnaBridge 171:3a7713b1edbc 83 #include "wdt_map.h"
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 // Register maps of HW modules controlled with specific functions
AnnaBridge 171:3a7713b1edbc 86 #include "clock_map.h"
AnnaBridge 171:3a7713b1edbc 87 #include "crossbar_map.h"
AnnaBridge 171:3a7713b1edbc 88 #include "dma_map.h"
AnnaBridge 171:3a7713b1edbc 89 #include "macHw_map.h"
AnnaBridge 171:3a7713b1edbc 90 #include "pad_map.h"
AnnaBridge 171:3a7713b1edbc 91 #include "pmu_map.h"
AnnaBridge 171:3a7713b1edbc 92 #include "random_map.h"
AnnaBridge 171:3a7713b1edbc 93 #include "reset_map.h"
AnnaBridge 171:3a7713b1edbc 94 #include "rfAna_map.h"
AnnaBridge 171:3a7713b1edbc 95 #include "test_map.h"
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 // Trim structure map
AnnaBridge 171:3a7713b1edbc 98 #include "trim_map.h"
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /*************************************************************************************************
AnnaBridge 171:3a7713b1edbc 101 * *
AnnaBridge 171:3a7713b1edbc 102 * Symbolic Constants *
AnnaBridge 171:3a7713b1edbc 103 * *
AnnaBridge 171:3a7713b1edbc 104 *************************************************************************************************/
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /** Trim structure mapping
AnnaBridge 171:3a7713b1edbc 107 *
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109 #define TRIMREG_BASE ((uint32_t)0x1FA0)
AnnaBridge 171:3a7713b1edbc 110 #define TRIMREG ((TrimReg_t *)TRIMREG_BASE)
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /** User trim structure mapping
AnnaBridge 171:3a7713b1edbc 113 *
AnnaBridge 171:3a7713b1edbc 114 */
AnnaBridge 171:3a7713b1edbc 115 #define USRETRIMREG_BASE ((uint32_t)0x2800)
AnnaBridge 171:3a7713b1edbc 116 #define USERTRIMREG ((UserTrimReg_t *)USRETRIMREG_BASE)
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /** DMA HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 119 #define DMAREG_BASE ((uint32_t)0x24000400)
AnnaBridge 171:3a7713b1edbc 120 /** DMA HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 121 #define DMAREG ((DmaReg_pt)DMAREG_BASE)
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 /** MAC MATCH HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 124 #define MACMATCHREG_BASE ((uint32_t)0x24000100)
AnnaBridge 171:3a7713b1edbc 125 /** MAC MATCH HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 126 #define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /** MAC RX HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 129 #define MACRXREG_BASE ((uint32_t)0x24000080)
AnnaBridge 171:3a7713b1edbc 130 /** MAC RX HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 131 #define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /** MAC TX HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 134 #define MACTXREG_BASE ((uint32_t)0x24000000)
AnnaBridge 171:3a7713b1edbc 135 /** MAC TX HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 136 #define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 /** TEST Interface for flash HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 139 #define TESTNVMREG_BASE ((uint32_t)0x4001F140)
AnnaBridge 171:3a7713b1edbc 140 /** TEST Interface for flash HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 141 #define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /** Test Interface for digital HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 144 #define TESTDIGREG_BASE ((uint32_t)0x4001F100)
AnnaBridge 171:3a7713b1edbc 145 /** Test Interface for digital HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 146 #define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /** Test Interface HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 149 #define TESTREG_BASE ((uint32_t)0x4001F000)
AnnaBridge 171:3a7713b1edbc 150 /** Test Interface HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 151 #define TESTREG ((TestReg_pt)TESTREG_BASE)
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /** Device option HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 154 #define DEVOPTREG_BASE ((uint32_t)0x4001E000)
AnnaBridge 171:3a7713b1edbc 155 /** MAC TX HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 156 #define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /** PMU HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 159 #define PMUREG_BASE ((uint32_t)0x4001D000)
AnnaBridge 171:3a7713b1edbc 160 /** PMU HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 161 #define PMUREG ((PmuReg_pt)PMUREG_BASE)
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /** PAD Control HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 164 #define PADREG_BASE ((uint32_t)0x4001C000)
AnnaBridge 171:3a7713b1edbc 165 /** PAD Control HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 166 #define PADREG ((PadReg_pt)PADREG_BASE)
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 /** Clock Control HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 169 #define CLOCKREG_BASE ((uint32_t)0x4001B000)
AnnaBridge 171:3a7713b1edbc 170 /** Clock Control HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 171 #define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 /** Analogue Trim HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 174 #define RFANATRIMREG_BASE ((uint32_t)0x40019080)
AnnaBridge 171:3a7713b1edbc 175 /** Analogue Trim HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 176 #define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /** Analogue RF HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 179 #define RFANAREG_BASE ((uint32_t)0x40019000)
AnnaBridge 171:3a7713b1edbc 180 /** Analogue RF HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 181 #define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /** Reset Cause HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 184 #define RESETREG_BASE ((uint32_t)0x40018000)
AnnaBridge 171:3a7713b1edbc 185 /** Reset Cause HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 186 #define RESETREG ((ResetReg_pt)RESETREG_BASE)
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 /** FLASH Control HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 189 #define FLASHREG_BASE ((uint32_t)0x40017000)
AnnaBridge 171:3a7713b1edbc 190 /** FLASH Control HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 191 #define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /** AES Encryption HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 194 #define AESREG_BASE ((uint32_t)0x40016000)
AnnaBridge 171:3a7713b1edbc 195 /** AES Encryption HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 196 #define AESREG ((AesReg_pt)AESREG_BASE)
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /** SAR ADC HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 199 #define ADCREG_BASE ((uint32_t)0x40015000)
AnnaBridge 171:3a7713b1edbc 200 /** SAR ADC HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 201 #define ADCREG ((AdcReg_pt)ADCREG_BASE)
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /** Demodulator HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 204 #define DMDREG_BASE ((uint32_t)0x40014100)
AnnaBridge 171:3a7713b1edbc 205 /** Demodulator HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 206 #define DMDREG ((DmdReg_pt)DMDREG_BASE)
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /** MAC Control HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 209 #define MACHWREG_BASE ((uint32_t)0x40014000)
AnnaBridge 171:3a7713b1edbc 210 /** MAC Control HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 211 #define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /** Random Generator HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 214 #define RANDREG_BASE ((uint32_t)0x40011000)
AnnaBridge 171:3a7713b1edbc 215 /** Random Generator HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 216 #define RANDREG ((RandReg_pt)RANDREG_BASE)
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /** Cross Bar HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 219 #define CROSSBREG_BASE ((uint32_t)0x40010000)
AnnaBridge 171:3a7713b1edbc 220 /** Cross Bar HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 221 #define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 /** Real Time Clock HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 224 #define RTCREG_BASE ((uint32_t)0x4000F000)
AnnaBridge 171:3a7713b1edbc 225 /** Real Time Clock HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 226 #define RTCREG ((RtcReg_pt)RTCREG_BASE)
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 /** GPIO HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 229 #define GPIOREG_BASE ((uint32_t)0x4000C000)
AnnaBridge 171:3a7713b1edbc 230 /** GPIO HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 231 #define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /** PWM HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 234 #define PWMREG_BASE ((uint32_t)0x4000B000)
AnnaBridge 171:3a7713b1edbc 235 /** PWM HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 236 #define PWMREG ((PwmReg_pt)PWMREG_BASE)
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 /** Watchdog Timer HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 239 #define WDTREG_BASE ((uint32_t)0x4000A000)
AnnaBridge 171:3a7713b1edbc 240 /** Watchdog Timer HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 241 #define WDTREG ((WdtReg_pt)WDTREG_BASE)
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /** UART 2 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 244 #define UART2REG_BASE ((uint32_t)0x40008000)
AnnaBridge 171:3a7713b1edbc 245 /** UART 2 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 246 #define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /** I2C HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 249 #define I2C1REG_BASE ((uint32_t)0x40007000)
AnnaBridge 171:3a7713b1edbc 250 /** I2C HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 251 #define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /** SPI HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 254 #define SPI1REG_BASE ((uint32_t)0x40006000)
AnnaBridge 171:3a7713b1edbc 255 /** SPI HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 256 #define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 /** UART1 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 259 #define UART1REG_BASE ((uint32_t)0x40005000)
AnnaBridge 171:3a7713b1edbc 260 /** UART1 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 261 #define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 #define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /** Timer 2 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 266 #define TIM2REG_BASE ((uint32_t)0x40002000)
AnnaBridge 171:3a7713b1edbc 267 /** Timer 2 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 268 #define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /** Timer 1 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 271 #define TIM1REG_BASE ((uint32_t)0x40001000)
AnnaBridge 171:3a7713b1edbc 272 /** Timer 1 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 273 #define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /** Timer 0 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 276 #define TIM0REG_BASE ((uint32_t)0x40000000)
AnnaBridge 171:3a7713b1edbc 277 /** Timer 0 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 278 #define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 /** I2C2 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 281 #define I2C2REG_BASE ((uint32_t)0x4000D000)
AnnaBridge 171:3a7713b1edbc 282 /** I2C2 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 283 #define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 /** SPI2 HW Registers Offset */
AnnaBridge 171:3a7713b1edbc 286 #define SPI2REG_BASE ((uint32_t)0x40009000)
AnnaBridge 171:3a7713b1edbc 287 /** SPI2 HW Structure Overlay */
AnnaBridge 171:3a7713b1edbc 288 #define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
AnnaBridge 171:3a7713b1edbc 289
AnnaBridge 171:3a7713b1edbc 290 #endif /*_MEMORY_MAP_H_*/