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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_semc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /*
AnnaBridge 170:e95d10626187 2 * The Clear BSD License
AnnaBridge 161:aa5281ff4a02 3 * Copyright 2017 NXP
AnnaBridge 170:e95d10626187 4 * All rights reserved.
AnnaBridge 161:aa5281ff4a02 5 *
AnnaBridge 161:aa5281ff4a02 6 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 170:e95d10626187 7 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 170:e95d10626187 8 * that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 9 *
AnnaBridge 161:aa5281ff4a02 10 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 161:aa5281ff4a02 11 * of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 12 *
AnnaBridge 161:aa5281ff4a02 13 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 161:aa5281ff4a02 14 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 161:aa5281ff4a02 15 * other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 16 *
AnnaBridge 161:aa5281ff4a02 17 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 161:aa5281ff4a02 18 * contributors may be used to endorse or promote products derived from this
AnnaBridge 161:aa5281ff4a02 19 * software without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 20 *
AnnaBridge 170:e95d10626187 21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 161:aa5281ff4a02 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 161:aa5281ff4a02 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 161:aa5281ff4a02 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 161:aa5281ff4a02 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 161:aa5281ff4a02 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 161:aa5281ff4a02 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 161:aa5281ff4a02 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 161:aa5281ff4a02 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 161:aa5281ff4a02 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 32 */
AnnaBridge 161:aa5281ff4a02 33 #ifndef _FSL_SEMC_H_
AnnaBridge 161:aa5281ff4a02 34 #define _FSL_SEMC_H_
AnnaBridge 161:aa5281ff4a02 35
AnnaBridge 161:aa5281ff4a02 36 #include "fsl_common.h"
AnnaBridge 161:aa5281ff4a02 37
AnnaBridge 161:aa5281ff4a02 38 /*!
AnnaBridge 161:aa5281ff4a02 39 * @addtogroup semc
AnnaBridge 161:aa5281ff4a02 40 * @{
AnnaBridge 161:aa5281ff4a02 41 */
AnnaBridge 161:aa5281ff4a02 42
AnnaBridge 161:aa5281ff4a02 43 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 44 * Definitions
AnnaBridge 161:aa5281ff4a02 45 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 46
AnnaBridge 161:aa5281ff4a02 47 /*! @name Driver version */
AnnaBridge 161:aa5281ff4a02 48 /*@{*/
AnnaBridge 170:e95d10626187 49 /*! @brief SEMC driver version 2.0.1. */
AnnaBridge 170:e95d10626187 50 #define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
AnnaBridge 161:aa5281ff4a02 51 /*@}*/
AnnaBridge 161:aa5281ff4a02 52
AnnaBridge 161:aa5281ff4a02 53 /*! @brief SEMC status. */
AnnaBridge 161:aa5281ff4a02 54 enum _semc_status
AnnaBridge 161:aa5281ff4a02 55 {
AnnaBridge 161:aa5281ff4a02 56 kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0),
AnnaBridge 161:aa5281ff4a02 57 kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1),
AnnaBridge 161:aa5281ff4a02 58 kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2),
AnnaBridge 161:aa5281ff4a02 59 kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3),
AnnaBridge 161:aa5281ff4a02 60 kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4),
AnnaBridge 161:aa5281ff4a02 61 kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5),
AnnaBridge 161:aa5281ff4a02 62 kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6),
AnnaBridge 161:aa5281ff4a02 63 kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7),
AnnaBridge 161:aa5281ff4a02 64 kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8),
AnnaBridge 161:aa5281ff4a02 65 kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9),
AnnaBridge 161:aa5281ff4a02 66 kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10),
AnnaBridge 161:aa5281ff4a02 67 kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11),
AnnaBridge 161:aa5281ff4a02 68 };
AnnaBridge 161:aa5281ff4a02 69
AnnaBridge 161:aa5281ff4a02 70 /*! @brief SEMC memory device type. */
AnnaBridge 161:aa5281ff4a02 71 typedef enum _semc_mem_type {
AnnaBridge 161:aa5281ff4a02 72 kSEMC_MemType_SDRAM = 0, /*!< SDRAM */
AnnaBridge 161:aa5281ff4a02 73 kSEMC_MemType_SRAM, /*!< SRAM */
AnnaBridge 161:aa5281ff4a02 74 kSEMC_MemType_NOR, /*!< NOR */
AnnaBridge 161:aa5281ff4a02 75 kSEMC_MemType_NAND, /*!< NAND */
AnnaBridge 161:aa5281ff4a02 76 kSEMC_MemType_8080 /*!< 8080. */
AnnaBridge 161:aa5281ff4a02 77 } semc_mem_type_t;
AnnaBridge 161:aa5281ff4a02 78
AnnaBridge 161:aa5281ff4a02 79 /*! @brief SEMC WAIT/RDY polarity. */
AnnaBridge 161:aa5281ff4a02 80 typedef enum _semc_waitready_polarity {
AnnaBridge 161:aa5281ff4a02 81 kSEMC_LowActive = 0, /*!< Low active. */
AnnaBridge 161:aa5281ff4a02 82 kSEMC_HighActive, /*!< High active. */
AnnaBridge 161:aa5281ff4a02 83 } semc_waitready_polarity_t;
AnnaBridge 161:aa5281ff4a02 84
AnnaBridge 161:aa5281ff4a02 85 /*! @brief SEMC SDRAM Chip selection . */
AnnaBridge 161:aa5281ff4a02 86 typedef enum _semc_sdram_cs {
AnnaBridge 161:aa5281ff4a02 87 kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */
AnnaBridge 161:aa5281ff4a02 88 kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */
AnnaBridge 161:aa5281ff4a02 89 kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */
AnnaBridge 161:aa5281ff4a02 90 kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */
AnnaBridge 161:aa5281ff4a02 91 } semc_sdram_cs_t;
AnnaBridge 161:aa5281ff4a02 92
AnnaBridge 161:aa5281ff4a02 93 /*! @brief SEMC NAND device type. */
AnnaBridge 170:e95d10626187 94 typedef enum _semc_nand_access_type {
AnnaBridge 170:e95d10626187 95 kSEMC_NAND_ACCESS_BY_AXI = 0,
AnnaBridge 170:e95d10626187 96 kSEMC_NAND_ACCESS_BY_IPCMD,
AnnaBridge 170:e95d10626187 97 } semc_nand_access_type_t;
AnnaBridge 161:aa5281ff4a02 98
AnnaBridge 161:aa5281ff4a02 99 /*! @brief SEMC interrupts . */
AnnaBridge 161:aa5281ff4a02 100 typedef enum _semc_interrupt_enable {
AnnaBridge 161:aa5281ff4a02 101 kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */
AnnaBridge 161:aa5281ff4a02 102 kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */
AnnaBridge 161:aa5281ff4a02 103 kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */
AnnaBridge 161:aa5281ff4a02 104 kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */
AnnaBridge 161:aa5281ff4a02 105 } semc_interrupt_enable_t;
AnnaBridge 161:aa5281ff4a02 106
AnnaBridge 161:aa5281ff4a02 107 /*! @brief SEMC IP command data size in bytes. */
AnnaBridge 161:aa5281ff4a02 108 typedef enum _semc_ipcmd_datasize {
AnnaBridge 161:aa5281ff4a02 109 kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */
AnnaBridge 161:aa5281ff4a02 110 kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */
AnnaBridge 161:aa5281ff4a02 111 kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */
AnnaBridge 161:aa5281ff4a02 112 kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */
AnnaBridge 161:aa5281ff4a02 113 } semc_ipcmd_datasize_t;
AnnaBridge 161:aa5281ff4a02 114
AnnaBridge 161:aa5281ff4a02 115 /*! @brief SEMC auto-refresh timing. */
AnnaBridge 161:aa5281ff4a02 116 typedef enum _semc_refresh_time {
AnnaBridge 161:aa5281ff4a02 117 kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
AnnaBridge 161:aa5281ff4a02 118 kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
AnnaBridge 161:aa5281ff4a02 119 kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
AnnaBridge 161:aa5281ff4a02 120 } semc_refresh_time_t;
AnnaBridge 161:aa5281ff4a02 121
AnnaBridge 161:aa5281ff4a02 122 /*! @brief CAS latency */
AnnaBridge 161:aa5281ff4a02 123 typedef enum _semc_caslatency {
AnnaBridge 161:aa5281ff4a02 124 kSEMC_LatencyOne = 1, /*!< Latency 1. */
AnnaBridge 161:aa5281ff4a02 125 kSEMC_LatencyTwo, /*!< Latency 2. */
AnnaBridge 161:aa5281ff4a02 126 kSEMC_LatencyThree, /*!< Latency 3. */
AnnaBridge 161:aa5281ff4a02 127 } semc_caslatency_t;
AnnaBridge 161:aa5281ff4a02 128
AnnaBridge 161:aa5281ff4a02 129 /*! @brief SEMC sdram column address bit number. */
AnnaBridge 161:aa5281ff4a02 130 typedef enum _semc_sdram_column_bit_num {
AnnaBridge 161:aa5281ff4a02 131 kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */
AnnaBridge 161:aa5281ff4a02 132 kSEMC_SdramColunm_11bit, /*!< 11 bit. */
AnnaBridge 161:aa5281ff4a02 133 kSEMC_SdramColunm_10bit, /*!< 10 bit. */
AnnaBridge 161:aa5281ff4a02 134 kSEMC_SdramColunm_9bit, /*!< 9 bit. */
AnnaBridge 161:aa5281ff4a02 135 } semc_sdram_column_bit_num_t;
AnnaBridge 161:aa5281ff4a02 136
AnnaBridge 161:aa5281ff4a02 137 /*! @brief SEMC sdram burst length. */
AnnaBridge 161:aa5281ff4a02 138 typedef enum _semc_sdram_burst_len {
AnnaBridge 161:aa5281ff4a02 139 kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/
AnnaBridge 161:aa5281ff4a02 140 kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/
AnnaBridge 161:aa5281ff4a02 141 kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/
AnnaBridge 161:aa5281ff4a02 142 kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/
AnnaBridge 161:aa5281ff4a02 143 } sem_sdram_burst_len_t;
AnnaBridge 161:aa5281ff4a02 144
AnnaBridge 161:aa5281ff4a02 145 /*! @brief SEMC nand column address bit number. */
AnnaBridge 161:aa5281ff4a02 146 typedef enum _semc_nand_column_bit_num {
AnnaBridge 161:aa5281ff4a02 147 kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */
AnnaBridge 161:aa5281ff4a02 148 kSEMC_NandColum_15bit, /*!< 15 bit. */
AnnaBridge 161:aa5281ff4a02 149 kSEMC_NandColum_14bit, /*!< 14 bit. */
AnnaBridge 161:aa5281ff4a02 150 kSEMC_NandColum_13bit, /*!< 13 bit. */
AnnaBridge 161:aa5281ff4a02 151 kSEMC_NandColum_12bit, /*!< 12 bit. */
AnnaBridge 161:aa5281ff4a02 152 kSEMC_NandColum_11bit, /*!< 11 bit. */
AnnaBridge 161:aa5281ff4a02 153 kSEMC_NandColum_10bit, /*!< 10 bit. */
AnnaBridge 161:aa5281ff4a02 154 kSEMC_NandColum_9bit, /*!< 9 bit. */
AnnaBridge 161:aa5281ff4a02 155 } semc_nand_column_bit_num_t;
AnnaBridge 161:aa5281ff4a02 156
AnnaBridge 161:aa5281ff4a02 157 /*! @brief SEMC nand burst length. */
AnnaBridge 161:aa5281ff4a02 158 typedef enum _semc_nand_burst_len {
AnnaBridge 161:aa5281ff4a02 159 kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/
AnnaBridge 161:aa5281ff4a02 160 kSEMC_Nand_BurstLen2, /*!< Burst length 2*/
AnnaBridge 161:aa5281ff4a02 161 kSEMC_Nand_BurstLen4, /*!< Burst length 4*/
AnnaBridge 161:aa5281ff4a02 162 kSEMC_Nand_BurstLen8, /*!< Burst length 8*/
AnnaBridge 161:aa5281ff4a02 163 kSEMC_Nand_BurstLen16, /*!< Burst length 16*/
AnnaBridge 161:aa5281ff4a02 164 kSEMC_Nand_BurstLen32, /*!< Burst length 32*/
AnnaBridge 161:aa5281ff4a02 165 kSEMC_Nand_BurstLen64 /*!< Burst length 64*/
AnnaBridge 161:aa5281ff4a02 166 } sem_nand_burst_len_t;
AnnaBridge 161:aa5281ff4a02 167
AnnaBridge 161:aa5281ff4a02 168 /*! @brief SEMC nor/sram column address bit number. */
AnnaBridge 161:aa5281ff4a02 169 typedef enum _semc_norsram_column_bit_num {
AnnaBridge 161:aa5281ff4a02 170 kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */
AnnaBridge 161:aa5281ff4a02 171 kSEMC_NorColum_11bit, /*!< 11 bit. */
AnnaBridge 161:aa5281ff4a02 172 kSEMC_NorColum_10bit, /*!< 10 bit. */
AnnaBridge 161:aa5281ff4a02 173 kSEMC_NorColum_9bit, /*!< 9 bit. */
AnnaBridge 161:aa5281ff4a02 174 kSEMC_NorColum_8bit, /*!< 8 bit. */
AnnaBridge 161:aa5281ff4a02 175 kSEMC_NorColum_7bit, /*!< 7 bit. */
AnnaBridge 161:aa5281ff4a02 176 kSEMC_NorColum_6bit, /*!< 6 bit. */
AnnaBridge 161:aa5281ff4a02 177 kSEMC_NorColum_5bit, /*!< 5 bit. */
AnnaBridge 161:aa5281ff4a02 178 kSEMC_NorColum_4bit, /*!< 4 bit. */
AnnaBridge 161:aa5281ff4a02 179 kSEMC_NorColum_3bit, /*!< 3 bit. */
AnnaBridge 161:aa5281ff4a02 180 kSEMC_NorColum_2bit /*!< 2 bit. */
AnnaBridge 161:aa5281ff4a02 181 } semc_norsram_column_bit_num_t;
AnnaBridge 161:aa5281ff4a02 182
AnnaBridge 161:aa5281ff4a02 183 /*! @brief SEMC nor/sram burst length. */
AnnaBridge 161:aa5281ff4a02 184 typedef enum _semc_norsram_burst_len {
AnnaBridge 161:aa5281ff4a02 185 kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/
AnnaBridge 161:aa5281ff4a02 186 kSEMC_Nor_BurstLen2, /*!< Burst length 2*/
AnnaBridge 161:aa5281ff4a02 187 kSEMC_Nor_BurstLen4, /*!< Burst length 4*/
AnnaBridge 161:aa5281ff4a02 188 kSEMC_Nor_BurstLen8, /*!< Burst length 8*/
AnnaBridge 161:aa5281ff4a02 189 kSEMC_Nor_BurstLen16, /*!< Burst length 16*/
AnnaBridge 161:aa5281ff4a02 190 kSEMC_Nor_BurstLen32, /*!< Burst length 32*/
AnnaBridge 161:aa5281ff4a02 191 kSEMC_Nor_BurstLen64 /*!< Burst length 64*/
AnnaBridge 161:aa5281ff4a02 192 } sem_norsram_burst_len_t;
AnnaBridge 161:aa5281ff4a02 193
AnnaBridge 161:aa5281ff4a02 194 /*! @brief SEMC dbi column address bit number. */
AnnaBridge 161:aa5281ff4a02 195 typedef enum _semc_dbi_column_bit_num {
AnnaBridge 161:aa5281ff4a02 196 kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */
AnnaBridge 161:aa5281ff4a02 197 kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */
AnnaBridge 161:aa5281ff4a02 198 kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */
AnnaBridge 161:aa5281ff4a02 199 kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */
AnnaBridge 161:aa5281ff4a02 200 kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */
AnnaBridge 161:aa5281ff4a02 201 kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */
AnnaBridge 161:aa5281ff4a02 202 kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */
AnnaBridge 161:aa5281ff4a02 203 kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */
AnnaBridge 161:aa5281ff4a02 204 kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */
AnnaBridge 161:aa5281ff4a02 205 kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */
AnnaBridge 161:aa5281ff4a02 206 kSEMC_Dbi_Colum_2bit /*!< 2 bit. */
AnnaBridge 161:aa5281ff4a02 207 } semc_dbi_column_bit_num_t;
AnnaBridge 161:aa5281ff4a02 208
AnnaBridge 161:aa5281ff4a02 209 /*! @brief SEMC dbi burst length. */
AnnaBridge 161:aa5281ff4a02 210 typedef enum _semc_dbi_burst_len {
AnnaBridge 161:aa5281ff4a02 211 kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/
AnnaBridge 161:aa5281ff4a02 212 kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/
AnnaBridge 161:aa5281ff4a02 213 kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/
AnnaBridge 161:aa5281ff4a02 214 kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/
AnnaBridge 161:aa5281ff4a02 215 kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/
AnnaBridge 161:aa5281ff4a02 216 kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/
AnnaBridge 161:aa5281ff4a02 217 kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/
AnnaBridge 161:aa5281ff4a02 218 } sem_dbi_burst_len_t;
AnnaBridge 161:aa5281ff4a02 219
AnnaBridge 161:aa5281ff4a02 220 /*! @brief SEMC IOMUXC. */
AnnaBridge 161:aa5281ff4a02 221 typedef enum _semc_iomux_pin {
AnnaBridge 161:aa5281ff4a02 222 kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */
AnnaBridge 161:aa5281ff4a02 223 kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */
AnnaBridge 161:aa5281ff4a02 224 kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/
AnnaBridge 161:aa5281ff4a02 225 kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */
AnnaBridge 161:aa5281ff4a02 226 kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
AnnaBridge 161:aa5281ff4a02 227 kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
AnnaBridge 161:aa5281ff4a02 228 } semc_iomux_pin;
AnnaBridge 161:aa5281ff4a02 229
AnnaBridge 161:aa5281ff4a02 230 /*! @brief SEMC NOR/PSRAM Address bit 27 A27. */
AnnaBridge 161:aa5281ff4a02 231 typedef enum _semc_iomux_nora27_pin {
AnnaBridge 161:aa5281ff4a02 232 kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */
AnnaBridge 161:aa5281ff4a02 233 kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */
AnnaBridge 161:aa5281ff4a02 234 kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */
AnnaBridge 161:aa5281ff4a02 235 } semc_iomux_nora27_pin;
AnnaBridge 161:aa5281ff4a02 236
AnnaBridge 161:aa5281ff4a02 237 /*! @brief SEMC port size. */
AnnaBridge 161:aa5281ff4a02 238 typedef enum _semc_port_size {
AnnaBridge 161:aa5281ff4a02 239 kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */
AnnaBridge 161:aa5281ff4a02 240 kSEMC_PortSize16Bit /*!< 16-Bit port size. */
AnnaBridge 161:aa5281ff4a02 241 } smec_port_size_t;
AnnaBridge 161:aa5281ff4a02 242
AnnaBridge 161:aa5281ff4a02 243 /*! @brief SEMC address mode. */
AnnaBridge 161:aa5281ff4a02 244 typedef enum _semc_addr_mode {
AnnaBridge 161:aa5281ff4a02 245 kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */
AnnaBridge 161:aa5281ff4a02 246 kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */
AnnaBridge 161:aa5281ff4a02 247 kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */
AnnaBridge 161:aa5281ff4a02 248 } semc_addr_mode_t;
AnnaBridge 161:aa5281ff4a02 249
AnnaBridge 161:aa5281ff4a02 250 /*! @brief SEMC DQS read strobe mode. */
AnnaBridge 161:aa5281ff4a02 251 typedef enum _semc_dqs_mode {
AnnaBridge 161:aa5281ff4a02 252 kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */
AnnaBridge 161:aa5281ff4a02 253 kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */
AnnaBridge 161:aa5281ff4a02 254 } semc_dqs_mode_t;
AnnaBridge 161:aa5281ff4a02 255
AnnaBridge 161:aa5281ff4a02 256 /*! @brief SEMC ADV signal active polarity. */
AnnaBridge 161:aa5281ff4a02 257 typedef enum _semc_adv_polarity {
AnnaBridge 161:aa5281ff4a02 258 kSEMC_AdvActiveLow = 0, /*!< Adv active low. */
AnnaBridge 161:aa5281ff4a02 259 kSEMC_AdvActivehigh, /*!< Adv active low. */
AnnaBridge 161:aa5281ff4a02 260 } semc_adv_polarity_t;
AnnaBridge 161:aa5281ff4a02 261
AnnaBridge 161:aa5281ff4a02 262 /*! @brief SEMC RDY signal active polarity. */
AnnaBridge 161:aa5281ff4a02 263 typedef enum _semc_rdy_polarity {
AnnaBridge 161:aa5281ff4a02 264 kSEMC_RdyActiveLow = 0, /*!< Adv active low. */
AnnaBridge 161:aa5281ff4a02 265 kSEMC_RdyActivehigh, /*!< Adv active low. */
AnnaBridge 161:aa5281ff4a02 266 } semc_rdy_polarity_t;
AnnaBridge 161:aa5281ff4a02 267
AnnaBridge 161:aa5281ff4a02 268 /*! @brief SEMC IP command for NAND: address mode. */
AnnaBridge 161:aa5281ff4a02 269 typedef enum _semc_ipcmd_nand_addrmode {
AnnaBridge 161:aa5281ff4a02 270 kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */
AnnaBridge 161:aa5281ff4a02 271 kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */
AnnaBridge 161:aa5281ff4a02 272 kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */
AnnaBridge 161:aa5281ff4a02 273 kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */
AnnaBridge 161:aa5281ff4a02 274 kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */
AnnaBridge 161:aa5281ff4a02 275 kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
AnnaBridge 161:aa5281ff4a02 276 } semc_ipcmd_nand_addrmode_t;
AnnaBridge 161:aa5281ff4a02 277
AnnaBridge 161:aa5281ff4a02 278 /*! @brief SEMC IP command for NAND： command mode. */
AnnaBridge 161:aa5281ff4a02 279 typedef enum _semc_ipcmd_nand_cmdmode {
AnnaBridge 170:e95d10626187 280 kSEMC_NANDCM_Command = 0x2U, /*!< command. */
AnnaBridge 161:aa5281ff4a02 281 kSEMC_NANDCM_CommandHold, /*!< Command hold. */
AnnaBridge 161:aa5281ff4a02 282 kSEMC_NANDCM_CommandAddress, /*!< Command address. */
AnnaBridge 161:aa5281ff4a02 283 kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */
AnnaBridge 161:aa5281ff4a02 284 kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */
AnnaBridge 161:aa5281ff4a02 285 kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */
AnnaBridge 161:aa5281ff4a02 286 kSEMC_NANDCM_CommandRead, /*!< Command read. */
AnnaBridge 161:aa5281ff4a02 287 kSEMC_NANDCM_CommandWrite, /*!< Command write. */
AnnaBridge 161:aa5281ff4a02 288 kSEMC_NANDCM_Read, /*!< Read. */
AnnaBridge 161:aa5281ff4a02 289 kSEMC_NANDCM_Write /*!< Write. */
AnnaBridge 161:aa5281ff4a02 290 } semc_ipcmd_nand_cmdmode_t;
AnnaBridge 161:aa5281ff4a02 291
AnnaBridge 161:aa5281ff4a02 292 /*! @brief SEMC NAND address option. */
AnnaBridge 161:aa5281ff4a02 293 typedef enum _semc_nand_address_option {
AnnaBridge 161:aa5281ff4a02 294 kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */
AnnaBridge 161:aa5281ff4a02 295 kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */
AnnaBridge 161:aa5281ff4a02 296 kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */
AnnaBridge 161:aa5281ff4a02 297 kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */
AnnaBridge 161:aa5281ff4a02 298 kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */
AnnaBridge 161:aa5281ff4a02 299 kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */
AnnaBridge 161:aa5281ff4a02 300 } semc_nand_address_option_t;
AnnaBridge 161:aa5281ff4a02 301
AnnaBridge 161:aa5281ff4a02 302 /*! @brief SEMC IP command for NOR. */
AnnaBridge 161:aa5281ff4a02 303 typedef enum _semc_ipcmd_nor_dbi {
AnnaBridge 161:aa5281ff4a02 304 kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */
AnnaBridge 161:aa5281ff4a02 305 kSEMC_NORDBICM_Write /*!< NOR write. */
AnnaBridge 161:aa5281ff4a02 306 } semc_ipcmd_nor_dbi_t;
AnnaBridge 161:aa5281ff4a02 307
AnnaBridge 161:aa5281ff4a02 308 /*! @brief SEMC IP command for SRAM. */
AnnaBridge 161:aa5281ff4a02 309 typedef enum _semc_ipcmd_sram {
AnnaBridge 161:aa5281ff4a02 310 kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */
AnnaBridge 161:aa5281ff4a02 311 kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */
AnnaBridge 161:aa5281ff4a02 312 kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */
AnnaBridge 161:aa5281ff4a02 313 kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */
AnnaBridge 161:aa5281ff4a02 314 } semc_ipcmd_sram_t;
AnnaBridge 161:aa5281ff4a02 315
AnnaBridge 161:aa5281ff4a02 316 /*! @brief SEMC IP command for SDARM. */
AnnaBridge 161:aa5281ff4a02 317 typedef enum _semc_ipcmd_sdram {
AnnaBridge 161:aa5281ff4a02 318 kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */
AnnaBridge 161:aa5281ff4a02 319 kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */
AnnaBridge 161:aa5281ff4a02 320 kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */
AnnaBridge 161:aa5281ff4a02 321 kSEMC_SDRAMCM_Active, /*!< SDRAM active. */
AnnaBridge 161:aa5281ff4a02 322 kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */
AnnaBridge 161:aa5281ff4a02 323 kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */
AnnaBridge 161:aa5281ff4a02 324 kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */
AnnaBridge 161:aa5281ff4a02 325 kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */
AnnaBridge 161:aa5281ff4a02 326 } semc_ipcmd_sdram_t;
AnnaBridge 161:aa5281ff4a02 327
AnnaBridge 161:aa5281ff4a02 328 /*! @brief SEMC SDRAM configuration structure.
AnnaBridge 161:aa5281ff4a02 329 *
AnnaBridge 161:aa5281ff4a02 330 * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes
AnnaBridge 161:aa5281ff4a02 331 * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function.
AnnaBridge 161:aa5281ff4a02 332 * Take refer to BR0~BR3 register in RM for details.
AnnaBridge 161:aa5281ff4a02 333 * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0,
AnnaBridge 161:aa5281ff4a02 334 * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0,
AnnaBridge 161:aa5281ff4a02 335 * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles.
AnnaBridge 161:aa5281ff4a02 336 * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are
AnnaBridge 161:aa5281ff4a02 337 * similar to prescalePeriod_N16Cycle.
AnnaBridge 161:aa5281ff4a02 338 *
AnnaBridge 161:aa5281ff4a02 339 */
AnnaBridge 161:aa5281ff4a02 340 typedef struct _semc_sdram_config
AnnaBridge 161:aa5281ff4a02 341 {
AnnaBridge 161:aa5281ff4a02 342 semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */
AnnaBridge 161:aa5281ff4a02 343 uint32_t address; /*!< The base address. */
AnnaBridge 161:aa5281ff4a02 344 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
AnnaBridge 161:aa5281ff4a02 345 smec_port_size_t portSize; /*!< Port size. */
AnnaBridge 161:aa5281ff4a02 346 sem_sdram_burst_len_t burstLen; /*!< Burst length. */
AnnaBridge 161:aa5281ff4a02 347 semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
AnnaBridge 161:aa5281ff4a02 348 semc_caslatency_t casLatency; /*!< CAS latency. */
AnnaBridge 161:aa5281ff4a02 349 uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */
AnnaBridge 170:e95d10626187 350 uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 351 uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 352 uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 353 uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 354 uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 355 uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 356 uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 357 uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */
AnnaBridge 161:aa5281ff4a02 358 uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */
AnnaBridge 161:aa5281ff4a02 359 uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */
AnnaBridge 161:aa5281ff4a02 360 uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */
AnnaBridge 161:aa5281ff4a02 361 uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */
AnnaBridge 161:aa5281ff4a02 362 uint8_t refreshBurstLen; /*!< Refresh burst length. */
AnnaBridge 161:aa5281ff4a02 363 } semc_sdram_config_t;
AnnaBridge 161:aa5281ff4a02 364
AnnaBridge 170:e95d10626187 365
AnnaBridge 170:e95d10626187 366 /*! @brief SEMC NAND device timing configuration structure. */
AnnaBridge 170:e95d10626187 367 typedef struct _semc_nand_timing_config
AnnaBridge 170:e95d10626187 368 {
AnnaBridge 170:e95d10626187 369 uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */
AnnaBridge 170:e95d10626187 370 uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */
AnnaBridge 170:e95d10626187 371 uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */
AnnaBridge 170:e95d10626187 372 uint8_t tWeLow_Ns; /*!< WE low time: tWP. */
AnnaBridge 170:e95d10626187 373 uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */
AnnaBridge 170:e95d10626187 374 uint8_t tReLow_Ns; /*!< RE low time: tRP. */
AnnaBridge 170:e95d10626187 375 uint8_t tReHigh_Ns; /*!< RE high time: tREH. */
AnnaBridge 170:e95d10626187 376 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */
AnnaBridge 170:e95d10626187 377 uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */
AnnaBridge 170:e95d10626187 378 uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */
AnnaBridge 170:e95d10626187 379 uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */
AnnaBridge 170:e95d10626187 380 uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */
AnnaBridge 170:e95d10626187 381 uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */
AnnaBridge 170:e95d10626187 382 } semc_nand_timing_config_t;
AnnaBridge 170:e95d10626187 383
AnnaBridge 170:e95d10626187 384
AnnaBridge 161:aa5281ff4a02 385 /*! @brief SEMC NAND configuration structure. */
AnnaBridge 161:aa5281ff4a02 386 typedef struct _semc_nand_config
AnnaBridge 161:aa5281ff4a02 387 {
AnnaBridge 161:aa5281ff4a02 388 semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */
AnnaBridge 161:aa5281ff4a02 389 uint32_t axiAddress; /*!< The base address for AXI nand. */
AnnaBridge 161:aa5281ff4a02 390 uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */
AnnaBridge 161:aa5281ff4a02 391 uint32_t ipgAddress; /*!< The base address for IPG nand . */
AnnaBridge 161:aa5281ff4a02 392 uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */
AnnaBridge 161:aa5281ff4a02 393 semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
AnnaBridge 161:aa5281ff4a02 394 bool edoModeEnabled; /*!< EDO mode enabled. */
AnnaBridge 161:aa5281ff4a02 395 semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
AnnaBridge 161:aa5281ff4a02 396 semc_nand_address_option_t arrayAddrOption; /*!< Address option. */
AnnaBridge 161:aa5281ff4a02 397 sem_nand_burst_len_t burstLen; /*!< Burst length. */
AnnaBridge 161:aa5281ff4a02 398 smec_port_size_t portSize; /*!< Port size. */
AnnaBridge 170:e95d10626187 399 semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */
AnnaBridge 161:aa5281ff4a02 400 } semc_nand_config_t;
AnnaBridge 161:aa5281ff4a02 401
AnnaBridge 161:aa5281ff4a02 402 /*! @brief SEMC NOR configuration structure. */
AnnaBridge 161:aa5281ff4a02 403 typedef struct _semc_nor_config
AnnaBridge 161:aa5281ff4a02 404 {
AnnaBridge 161:aa5281ff4a02 405 semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
AnnaBridge 161:aa5281ff4a02 406 semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
AnnaBridge 161:aa5281ff4a02 407 uint32_t address; /*!< The base address. */
AnnaBridge 161:aa5281ff4a02 408 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
AnnaBridge 161:aa5281ff4a02 409 uint8_t addrPortWidth; /*!< The address port width. */
AnnaBridge 161:aa5281ff4a02 410 semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */
AnnaBridge 161:aa5281ff4a02 411 semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */
AnnaBridge 161:aa5281ff4a02 412 semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
AnnaBridge 161:aa5281ff4a02 413 semc_addr_mode_t addrMode; /*!< Address mode. */
AnnaBridge 161:aa5281ff4a02 414 sem_norsram_burst_len_t burstLen; /*!< Burst length. */
AnnaBridge 161:aa5281ff4a02 415 smec_port_size_t portSize; /*!< Port size. */
AnnaBridge 161:aa5281ff4a02 416 uint8_t tCeSetup_Ns; /*!< The CE setup time. */
AnnaBridge 161:aa5281ff4a02 417 uint8_t tCeHold_Ns; /*!< The CE hold time. */
AnnaBridge 161:aa5281ff4a02 418 uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
AnnaBridge 161:aa5281ff4a02 419 uint8_t tAddrSetup_Ns; /*!< The address setup time. */
AnnaBridge 161:aa5281ff4a02 420 uint8_t tAddrHold_Ns; /*!< The address hold time. */
AnnaBridge 161:aa5281ff4a02 421 uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
AnnaBridge 161:aa5281ff4a02 422 uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
AnnaBridge 161:aa5281ff4a02 423 uint8_t tReLow_Ns; /*!< RE low time for async mode. */
AnnaBridge 161:aa5281ff4a02 424 uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
AnnaBridge 161:aa5281ff4a02 425 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
AnnaBridge 161:aa5281ff4a02 426 uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
AnnaBridge 161:aa5281ff4a02 427 uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
AnnaBridge 161:aa5281ff4a02 428 uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
AnnaBridge 161:aa5281ff4a02 429 uint8_t latencyCount; /*!< Latency count for sync mode. */
AnnaBridge 161:aa5281ff4a02 430 uint8_t readCycle; /*!< Read cycle time for sync mode. */
AnnaBridge 161:aa5281ff4a02 431 } semc_nor_config_t;
AnnaBridge 161:aa5281ff4a02 432
AnnaBridge 161:aa5281ff4a02 433 /*! @brief SEMC SRAM configuration structure. */
AnnaBridge 161:aa5281ff4a02 434 typedef struct _semc_sram_config
AnnaBridge 161:aa5281ff4a02 435 {
AnnaBridge 161:aa5281ff4a02 436 semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */
AnnaBridge 161:aa5281ff4a02 437 semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */
AnnaBridge 161:aa5281ff4a02 438 uint32_t address; /*!< The base address. */
AnnaBridge 161:aa5281ff4a02 439 uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */
AnnaBridge 161:aa5281ff4a02 440 uint8_t addrPortWidth; /*!< The address port width. */
AnnaBridge 161:aa5281ff4a02 441 semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */
AnnaBridge 161:aa5281ff4a02 442 semc_addr_mode_t addrMode; /*!< Address mode. */
AnnaBridge 161:aa5281ff4a02 443 sem_norsram_burst_len_t burstLen; /*!< Burst length. */
AnnaBridge 161:aa5281ff4a02 444 smec_port_size_t portSize; /*!< Port size. */
AnnaBridge 161:aa5281ff4a02 445 uint8_t tCeSetup_Ns; /*!< The CE setup time. */
AnnaBridge 161:aa5281ff4a02 446 uint8_t tCeHold_Ns; /*!< The CE hold time. */
AnnaBridge 161:aa5281ff4a02 447 uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */
AnnaBridge 161:aa5281ff4a02 448 uint8_t tAddrSetup_Ns; /*!< The address setup time. */
AnnaBridge 161:aa5281ff4a02 449 uint8_t tAddrHold_Ns; /*!< The address hold time. */
AnnaBridge 161:aa5281ff4a02 450 uint8_t tWeLow_Ns; /*!< WE low time for async mode. */
AnnaBridge 161:aa5281ff4a02 451 uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */
AnnaBridge 161:aa5281ff4a02 452 uint8_t tReLow_Ns; /*!< RE low time for async mode. */
AnnaBridge 161:aa5281ff4a02 453 uint8_t tReHigh_Ns; /*!< RE high time for async mode. */
AnnaBridge 161:aa5281ff4a02 454 uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */
AnnaBridge 161:aa5281ff4a02 455 uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */
AnnaBridge 161:aa5281ff4a02 456 uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/
AnnaBridge 161:aa5281ff4a02 457 uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */
AnnaBridge 161:aa5281ff4a02 458 uint8_t latencyCount; /*!< Latency count for sync mode. */
AnnaBridge 161:aa5281ff4a02 459 uint8_t readCycle; /*!< Read cycle time for sync mode. */
AnnaBridge 161:aa5281ff4a02 460 } semc_sram_config_t;
AnnaBridge 161:aa5281ff4a02 461
AnnaBridge 161:aa5281ff4a02 462 /*! @brief SEMC DBI configuration structure. */
AnnaBridge 161:aa5281ff4a02 463 typedef struct _semc_dbi_config
AnnaBridge 161:aa5281ff4a02 464 {
AnnaBridge 161:aa5281ff4a02 465 semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */
AnnaBridge 161:aa5281ff4a02 466 uint32_t address; /*!< The base address. */
AnnaBridge 161:aa5281ff4a02 467 uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */
AnnaBridge 161:aa5281ff4a02 468 semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */
AnnaBridge 161:aa5281ff4a02 469 sem_dbi_burst_len_t burstLen; /*!< Burst length. */
AnnaBridge 161:aa5281ff4a02 470 smec_port_size_t portSize; /*!< Port size. */
AnnaBridge 161:aa5281ff4a02 471 uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */
AnnaBridge 161:aa5281ff4a02 472 uint8_t tCsxHold_Ns; /*!< The CSX hold time. */
AnnaBridge 161:aa5281ff4a02 473 uint8_t tWexLow_Ns; /*!< WEX low time. */
AnnaBridge 161:aa5281ff4a02 474 uint8_t tWexHigh_Ns; /*!< WEX high time. */
AnnaBridge 161:aa5281ff4a02 475 uint8_t tRdxLow_Ns; /*!< RDX low time. */
AnnaBridge 161:aa5281ff4a02 476 uint8_t tRdxHigh_Ns; /*!< RDX high time. */
AnnaBridge 161:aa5281ff4a02 477 uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/
AnnaBridge 161:aa5281ff4a02 478 } semc_dbi_config_t;
AnnaBridge 161:aa5281ff4a02 479
AnnaBridge 161:aa5281ff4a02 480 /*! @brief SEMC AXI queue a weight setting. */
AnnaBridge 161:aa5281ff4a02 481 typedef struct _semc_queuea_weight
AnnaBridge 161:aa5281ff4a02 482 {
AnnaBridge 161:aa5281ff4a02 483 uint32_t qos : 4; /*!< weight of qos for queue 0 . */
AnnaBridge 161:aa5281ff4a02 484 uint32_t aging : 4; /*!< weight of aging for queue 0.*/
AnnaBridge 161:aa5281ff4a02 485 uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/
AnnaBridge 161:aa5281ff4a02 486 uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/
AnnaBridge 161:aa5281ff4a02 487 } semc_queuea_weight_t;
AnnaBridge 161:aa5281ff4a02 488
AnnaBridge 161:aa5281ff4a02 489 /*! @brief SEMC AXI queue b weight setting. */
AnnaBridge 161:aa5281ff4a02 490 typedef struct _semc_queueb_weight
AnnaBridge 161:aa5281ff4a02 491 {
AnnaBridge 161:aa5281ff4a02 492 uint32_t qos : 4; /*!< weight of qos for queue 1. */
AnnaBridge 161:aa5281ff4a02 493 uint32_t aging : 4; /*!< weight of aging for queue 1.*/
AnnaBridge 161:aa5281ff4a02 494 uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/
AnnaBridge 161:aa5281ff4a02 495 uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/
AnnaBridge 161:aa5281ff4a02 496 uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/
AnnaBridge 161:aa5281ff4a02 497 } semc_queueb_weight_t;
AnnaBridge 161:aa5281ff4a02 498
AnnaBridge 161:aa5281ff4a02 499 /*! @brief SEMC AXI queue weight setting. */
AnnaBridge 161:aa5281ff4a02 500 typedef struct _semc_axi_queueweight
AnnaBridge 161:aa5281ff4a02 501 {
AnnaBridge 161:aa5281ff4a02 502 semc_queuea_weight_t *queueaWeight; /*!< Weight settings for queue a. */
AnnaBridge 161:aa5281ff4a02 503 semc_queueb_weight_t *queuebWeight; /*!< Weight settings for queue b. */
AnnaBridge 161:aa5281ff4a02 504 } semc_axi_queueweight_t;
AnnaBridge 161:aa5281ff4a02 505
AnnaBridge 161:aa5281ff4a02 506 /*!
AnnaBridge 161:aa5281ff4a02 507 * @brief SEMC configuration structure.
AnnaBridge 161:aa5281ff4a02 508 *
AnnaBridge 161:aa5281ff4a02 509 * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is
AnnaBridge 161:aa5281ff4a02 510 * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024.
AnnaBridge 161:aa5281ff4a02 511 * cmdTimeoutCycles: is used for command execution timeout cycles. it's
AnnaBridge 161:aa5281ff4a02 512 * similar to the busTimeoutCycles.
AnnaBridge 161:aa5281ff4a02 513 */
AnnaBridge 161:aa5281ff4a02 514 typedef struct _semc_config_t
AnnaBridge 161:aa5281ff4a02 515 {
AnnaBridge 161:aa5281ff4a02 516 semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */
AnnaBridge 161:aa5281ff4a02 517 uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */
AnnaBridge 161:aa5281ff4a02 518 uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */
AnnaBridge 161:aa5281ff4a02 519 semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */
AnnaBridge 161:aa5281ff4a02 520 } semc_config_t;
AnnaBridge 161:aa5281ff4a02 521
AnnaBridge 161:aa5281ff4a02 522 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 523 * API
AnnaBridge 161:aa5281ff4a02 524 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 525
AnnaBridge 161:aa5281ff4a02 526 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 527 extern "C" {
AnnaBridge 161:aa5281ff4a02 528 #endif
AnnaBridge 161:aa5281ff4a02 529
AnnaBridge 161:aa5281ff4a02 530 /*!
AnnaBridge 161:aa5281ff4a02 531 * @name SEMC Initialization and De-initialization
AnnaBridge 161:aa5281ff4a02 532 * @{
AnnaBridge 161:aa5281ff4a02 533 */
AnnaBridge 161:aa5281ff4a02 534
AnnaBridge 161:aa5281ff4a02 535 /*!
AnnaBridge 161:aa5281ff4a02 536 * @brief Gets the SEMC default basic configuration structure.
AnnaBridge 161:aa5281ff4a02 537 *
AnnaBridge 161:aa5281ff4a02 538 * The purpose of this API is to get the default SEMC
AnnaBridge 161:aa5281ff4a02 539 * configure structure for SEMC_Init(). User may use the initialized
AnnaBridge 161:aa5281ff4a02 540 * structure unchanged in SEMC_Init(), or modify some fields of the
AnnaBridge 161:aa5281ff4a02 541 * structure before calling SEMC_Init().
AnnaBridge 161:aa5281ff4a02 542 * Example:
AnnaBridge 161:aa5281ff4a02 543 @code
AnnaBridge 161:aa5281ff4a02 544 semc_config_t config;
AnnaBridge 161:aa5281ff4a02 545 SEMC_GetDefaultConfig(&config);
AnnaBridge 161:aa5281ff4a02 546 @endcode
AnnaBridge 161:aa5281ff4a02 547 * @param config The SEMC configuration structure pointer.
AnnaBridge 161:aa5281ff4a02 548 */
AnnaBridge 161:aa5281ff4a02 549 void SEMC_GetDefaultConfig(semc_config_t *config);
AnnaBridge 161:aa5281ff4a02 550
AnnaBridge 161:aa5281ff4a02 551 /*!
AnnaBridge 161:aa5281ff4a02 552 * @brief Initializes SEMC.
AnnaBridge 161:aa5281ff4a02 553 * This function ungates the SEMC clock and initializes SEMC.
AnnaBridge 161:aa5281ff4a02 554 * This function must be called before calling any other SEMC driver functions.
AnnaBridge 161:aa5281ff4a02 555 *
AnnaBridge 161:aa5281ff4a02 556 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 557 * @param configure The SEMC configuration structure pointer.
AnnaBridge 161:aa5281ff4a02 558 */
AnnaBridge 161:aa5281ff4a02 559 void SEMC_Init(SEMC_Type *base, semc_config_t *configure);
AnnaBridge 161:aa5281ff4a02 560
AnnaBridge 161:aa5281ff4a02 561 /*!
AnnaBridge 161:aa5281ff4a02 562 * @brief Deinitializes the SEMC module and gates the clock.
AnnaBridge 161:aa5281ff4a02 563 * This function gates the SEMC clock. As a result, the SEMC
AnnaBridge 161:aa5281ff4a02 564 * module doesn't work after calling this function.
AnnaBridge 161:aa5281ff4a02 565 *
AnnaBridge 161:aa5281ff4a02 566 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 567 */
AnnaBridge 161:aa5281ff4a02 568 void SEMC_Deinit(SEMC_Type *base);
AnnaBridge 161:aa5281ff4a02 569
AnnaBridge 161:aa5281ff4a02 570 /* @} */
AnnaBridge 161:aa5281ff4a02 571
AnnaBridge 161:aa5281ff4a02 572 /*!
AnnaBridge 161:aa5281ff4a02 573 * @name SEMC Configuration Operation For Each Memory Type
AnnaBridge 161:aa5281ff4a02 574 * @{
AnnaBridge 161:aa5281ff4a02 575 */
AnnaBridge 161:aa5281ff4a02 576
AnnaBridge 161:aa5281ff4a02 577 /*!
AnnaBridge 161:aa5281ff4a02 578 * @brief Configures SDRAM controller in SEMC.
AnnaBridge 161:aa5281ff4a02 579 *
AnnaBridge 161:aa5281ff4a02 580 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 581 * @param cs The chip selection.
AnnaBridge 161:aa5281ff4a02 582 * @param config The sdram configuration.
AnnaBridge 161:aa5281ff4a02 583 * @param clkSrc_Hz The SEMC clock frequency.
AnnaBridge 161:aa5281ff4a02 584 */
AnnaBridge 161:aa5281ff4a02 585 status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz);
AnnaBridge 161:aa5281ff4a02 586
AnnaBridge 161:aa5281ff4a02 587 /*!
AnnaBridge 161:aa5281ff4a02 588 * @brief Configures NAND controller in SEMC.
AnnaBridge 161:aa5281ff4a02 589 *
AnnaBridge 161:aa5281ff4a02 590 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 591 * @param config The nand configuration.
AnnaBridge 161:aa5281ff4a02 592 * @param clkSrc_Hz The SEMC clock frequency.
AnnaBridge 161:aa5281ff4a02 593 */
AnnaBridge 161:aa5281ff4a02 594 status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz);
AnnaBridge 161:aa5281ff4a02 595
AnnaBridge 161:aa5281ff4a02 596 /*!
AnnaBridge 161:aa5281ff4a02 597 * @brief Configures NOR controller in SEMC.
AnnaBridge 161:aa5281ff4a02 598 *
AnnaBridge 161:aa5281ff4a02 599 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 600 * @param config The nor configuration.
AnnaBridge 161:aa5281ff4a02 601 * @param clkSrc_Hz The SEMC clock frequency.
AnnaBridge 161:aa5281ff4a02 602 */
AnnaBridge 161:aa5281ff4a02 603 status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz);
AnnaBridge 161:aa5281ff4a02 604
AnnaBridge 161:aa5281ff4a02 605 /*!
AnnaBridge 161:aa5281ff4a02 606 * @brief Configures SRAM controller in SEMC.
AnnaBridge 161:aa5281ff4a02 607 *
AnnaBridge 161:aa5281ff4a02 608 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 609 * @param config The sram configuration.
AnnaBridge 161:aa5281ff4a02 610 * @param clkSrc_Hz The SEMC clock frequency.
AnnaBridge 161:aa5281ff4a02 611 */
AnnaBridge 161:aa5281ff4a02 612 status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz);
AnnaBridge 161:aa5281ff4a02 613
AnnaBridge 161:aa5281ff4a02 614 /*!
AnnaBridge 161:aa5281ff4a02 615 * @brief Configures DBI controller in SEMC.
AnnaBridge 161:aa5281ff4a02 616 *
AnnaBridge 161:aa5281ff4a02 617 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 618 * @param config The dbi configuration.
AnnaBridge 161:aa5281ff4a02 619 * @param clkSrc_Hz The SEMC clock frequency.
AnnaBridge 161:aa5281ff4a02 620 */
AnnaBridge 161:aa5281ff4a02 621 status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz);
AnnaBridge 161:aa5281ff4a02 622
AnnaBridge 161:aa5281ff4a02 623 /* @} */
AnnaBridge 161:aa5281ff4a02 624
AnnaBridge 161:aa5281ff4a02 625 /*!
AnnaBridge 161:aa5281ff4a02 626 * @name SEMC Interrupt Operation
AnnaBridge 161:aa5281ff4a02 627 * @{
AnnaBridge 161:aa5281ff4a02 628 */
AnnaBridge 161:aa5281ff4a02 629
AnnaBridge 161:aa5281ff4a02 630 /*!
AnnaBridge 161:aa5281ff4a02 631 * @brief Enables the SEMC interrupt.
AnnaBridge 161:aa5281ff4a02 632 *
AnnaBridge 161:aa5281ff4a02 633 * This function enables the SEMC interrupts according to the provided mask. The mask
AnnaBridge 161:aa5281ff4a02 634 * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
AnnaBridge 161:aa5281ff4a02 635 * For example, to enable the IP command done and error interrupt, do the following.
AnnaBridge 161:aa5281ff4a02 636 * @code
AnnaBridge 161:aa5281ff4a02 637 * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
AnnaBridge 161:aa5281ff4a02 638 * @endcode
AnnaBridge 161:aa5281ff4a02 639 *
AnnaBridge 161:aa5281ff4a02 640 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 641 * @param mask SEMC interrupts to enable. This is a logical OR of the
AnnaBridge 161:aa5281ff4a02 642 * enumeration :: semc_interrupt_enable_t.
AnnaBridge 161:aa5281ff4a02 643 */
AnnaBridge 161:aa5281ff4a02 644 static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 645 {
AnnaBridge 161:aa5281ff4a02 646 base->INTEN |= mask;
AnnaBridge 161:aa5281ff4a02 647 }
AnnaBridge 161:aa5281ff4a02 648
AnnaBridge 161:aa5281ff4a02 649 /*!
AnnaBridge 161:aa5281ff4a02 650 * @brief Disables the SEMC interrupt.
AnnaBridge 161:aa5281ff4a02 651 *
AnnaBridge 161:aa5281ff4a02 652 * This function disables the SEMC interrupts according to the provided mask. The mask
AnnaBridge 161:aa5281ff4a02 653 * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t.
AnnaBridge 161:aa5281ff4a02 654 * For example, to disable the IP command done and error interrupt, do the following.
AnnaBridge 161:aa5281ff4a02 655 * @code
AnnaBridge 161:aa5281ff4a02 656 * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt);
AnnaBridge 161:aa5281ff4a02 657 * @endcode
AnnaBridge 161:aa5281ff4a02 658 *
AnnaBridge 161:aa5281ff4a02 659 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 660 * @param mask SEMC interrupts to disable. This is a logical OR of the
AnnaBridge 161:aa5281ff4a02 661 * enumeration :: semc_interrupt_enable_t.
AnnaBridge 161:aa5281ff4a02 662 */
AnnaBridge 161:aa5281ff4a02 663 static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 664 {
AnnaBridge 161:aa5281ff4a02 665 base->INTEN &= ~mask;
AnnaBridge 161:aa5281ff4a02 666 }
AnnaBridge 161:aa5281ff4a02 667
AnnaBridge 161:aa5281ff4a02 668 /*!
AnnaBridge 161:aa5281ff4a02 669 * @brief Gets the SEMC status.
AnnaBridge 161:aa5281ff4a02 670 *
AnnaBridge 161:aa5281ff4a02 671 * This function gets the SEMC interrupts event status.
AnnaBridge 161:aa5281ff4a02 672 * User can use the a logical OR of enumeration member as a mask.
AnnaBridge 161:aa5281ff4a02 673 * See @ref semc_interrupt_enable_t.
AnnaBridge 161:aa5281ff4a02 674 *
AnnaBridge 161:aa5281ff4a02 675 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 676 * @return status flag, use status flag in semc_interrupt_enable_t to get the related status.
AnnaBridge 161:aa5281ff4a02 677 */
AnnaBridge 161:aa5281ff4a02 678 static inline bool SEMC_GetStatusFlag(SEMC_Type *base)
AnnaBridge 161:aa5281ff4a02 679 {
AnnaBridge 161:aa5281ff4a02 680 return base->INTR;
AnnaBridge 161:aa5281ff4a02 681 }
AnnaBridge 161:aa5281ff4a02 682
AnnaBridge 161:aa5281ff4a02 683 /*!
AnnaBridge 161:aa5281ff4a02 684 * @brief Clears the SEMC status flag state.
AnnaBridge 161:aa5281ff4a02 685 *
AnnaBridge 161:aa5281ff4a02 686 * The following status register flags can be cleared SEMC interrupt status.
AnnaBridge 161:aa5281ff4a02 687 *
AnnaBridge 161:aa5281ff4a02 688 * @param base SEMC base pointer
AnnaBridge 161:aa5281ff4a02 689 * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t.
AnnaBridge 161:aa5281ff4a02 690 */
AnnaBridge 161:aa5281ff4a02 691 static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 692 {
AnnaBridge 161:aa5281ff4a02 693 base->INTR |= mask;
AnnaBridge 161:aa5281ff4a02 694 }
AnnaBridge 161:aa5281ff4a02 695
AnnaBridge 161:aa5281ff4a02 696 /* @} */
AnnaBridge 161:aa5281ff4a02 697
AnnaBridge 161:aa5281ff4a02 698 /*!
AnnaBridge 161:aa5281ff4a02 699 * @name SEMC Memory Access Operation
AnnaBridge 161:aa5281ff4a02 700 * @{
AnnaBridge 161:aa5281ff4a02 701 */
AnnaBridge 161:aa5281ff4a02 702
AnnaBridge 161:aa5281ff4a02 703 /*!
AnnaBridge 161:aa5281ff4a02 704 * @brief Check if SEMC is in idle.
AnnaBridge 161:aa5281ff4a02 705 *
AnnaBridge 161:aa5281ff4a02 706 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 707 * @return True SEMC is in idle, false is not in idle.
AnnaBridge 161:aa5281ff4a02 708 */
AnnaBridge 161:aa5281ff4a02 709 static inline bool SEMC_IsInIdle(SEMC_Type *base)
AnnaBridge 161:aa5281ff4a02 710 {
AnnaBridge 161:aa5281ff4a02 711 return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false;
AnnaBridge 161:aa5281ff4a02 712 }
AnnaBridge 161:aa5281ff4a02 713
AnnaBridge 161:aa5281ff4a02 714 /*!
AnnaBridge 161:aa5281ff4a02 715 * @brief SEMC IP command access.
AnnaBridge 161:aa5281ff4a02 716 *
AnnaBridge 161:aa5281ff4a02 717 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 718 * @param type SEMC memory type. refer to "semc_mem_type_t"
AnnaBridge 161:aa5281ff4a02 719 * @param address SEMC device address.
AnnaBridge 161:aa5281ff4a02 720 * @param command SEMC IP command.
AnnaBridge 161:aa5281ff4a02 721 * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command.
AnnaBridge 161:aa5281ff4a02 722 * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t".
AnnaBridge 161:aa5281ff4a02 723 * For SRAM device, take refer to "semc_ipcmd_sram_t".
AnnaBridge 161:aa5281ff4a02 724 * For SDRAM device, take refer to "semc_ipcmd_sdram_t".
AnnaBridge 161:aa5281ff4a02 725 * @param write Data for write access.
AnnaBridge 161:aa5281ff4a02 726 * @param read Data pointer for read data out.
AnnaBridge 161:aa5281ff4a02 727 */
AnnaBridge 161:aa5281ff4a02 728 status_t SEMC_SendIPCommand(
AnnaBridge 161:aa5281ff4a02 729 SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read);
AnnaBridge 161:aa5281ff4a02 730
AnnaBridge 161:aa5281ff4a02 731 /*!
AnnaBridge 161:aa5281ff4a02 732 * @brief Build SEMC IP command for NAND.
AnnaBridge 161:aa5281ff4a02 733 *
AnnaBridge 161:aa5281ff4a02 734 * This function build SEMC NAND IP command. The command is build of user command code,
AnnaBridge 161:aa5281ff4a02 735 * SEMC address mode and SEMC command mode.
AnnaBridge 161:aa5281ff4a02 736 *
AnnaBridge 161:aa5281ff4a02 737 * @param userCommand NAND device normal command.
AnnaBridge 161:aa5281ff4a02 738 * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t".
AnnaBridge 161:aa5281ff4a02 739 * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t".
AnnaBridge 161:aa5281ff4a02 740 */
AnnaBridge 161:aa5281ff4a02 741 static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand,
AnnaBridge 161:aa5281ff4a02 742 semc_ipcmd_nand_addrmode_t addrMode,
AnnaBridge 161:aa5281ff4a02 743 semc_ipcmd_nand_cmdmode_t cmdMode)
AnnaBridge 161:aa5281ff4a02 744 {
AnnaBridge 161:aa5281ff4a02 745 return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu);
AnnaBridge 161:aa5281ff4a02 746 }
AnnaBridge 161:aa5281ff4a02 747
AnnaBridge 161:aa5281ff4a02 748 /*!
AnnaBridge 161:aa5281ff4a02 749 * @brief Check if the NAND device is ready.
AnnaBridge 161:aa5281ff4a02 750 *
AnnaBridge 161:aa5281ff4a02 751 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 752 * @return True NAND is ready, false NAND is not ready.
AnnaBridge 161:aa5281ff4a02 753 */
AnnaBridge 161:aa5281ff4a02 754 static inline bool SEMC_IsNandReady(SEMC_Type *base)
AnnaBridge 161:aa5281ff4a02 755 {
AnnaBridge 161:aa5281ff4a02 756 return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false;
AnnaBridge 161:aa5281ff4a02 757 }
AnnaBridge 161:aa5281ff4a02 758
AnnaBridge 161:aa5281ff4a02 759 /*!
AnnaBridge 161:aa5281ff4a02 760 * @brief SEMC NAND device memory write through IP command.
AnnaBridge 161:aa5281ff4a02 761 *
AnnaBridge 161:aa5281ff4a02 762 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 763 * @param address SEMC NAND device address.
AnnaBridge 161:aa5281ff4a02 764 * @param data Data for write access.
AnnaBridge 161:aa5281ff4a02 765 * @param size_bytes Data length.
AnnaBridge 161:aa5281ff4a02 766 */
AnnaBridge 161:aa5281ff4a02 767 status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
AnnaBridge 161:aa5281ff4a02 768
AnnaBridge 161:aa5281ff4a02 769 /*!
AnnaBridge 161:aa5281ff4a02 770 * @brief SEMC NAND device memory read through IP command.
AnnaBridge 161:aa5281ff4a02 771 *
AnnaBridge 161:aa5281ff4a02 772 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 773 * @param address SEMC NAND device address.
AnnaBridge 161:aa5281ff4a02 774 * @param data Data pointer for data read out.
AnnaBridge 161:aa5281ff4a02 775 * @param size_bytes Data length.
AnnaBridge 161:aa5281ff4a02 776 */
AnnaBridge 161:aa5281ff4a02 777 status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
AnnaBridge 161:aa5281ff4a02 778
AnnaBridge 161:aa5281ff4a02 779 /*!
AnnaBridge 161:aa5281ff4a02 780 * @brief SEMC NOR device memory write through IP command.
AnnaBridge 161:aa5281ff4a02 781 *
AnnaBridge 161:aa5281ff4a02 782 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 783 * @param address SEMC NOR device address.
AnnaBridge 161:aa5281ff4a02 784 * @param data Data for write access.
AnnaBridge 161:aa5281ff4a02 785 * @param size_bytes Data length.
AnnaBridge 161:aa5281ff4a02 786 */
AnnaBridge 161:aa5281ff4a02 787 status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
AnnaBridge 161:aa5281ff4a02 788
AnnaBridge 161:aa5281ff4a02 789 /*!
AnnaBridge 161:aa5281ff4a02 790 * @brief SEMC NOR device memory read through IP command.
AnnaBridge 161:aa5281ff4a02 791 *
AnnaBridge 161:aa5281ff4a02 792 * @param base SEMC peripheral base address.
AnnaBridge 161:aa5281ff4a02 793 * @param address SEMC NOR device address.
AnnaBridge 161:aa5281ff4a02 794 * @param data Data pointer for data read out.
AnnaBridge 161:aa5281ff4a02 795 * @param size_bytes Data length.
AnnaBridge 161:aa5281ff4a02 796 */
AnnaBridge 161:aa5281ff4a02 797 status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes);
AnnaBridge 161:aa5281ff4a02 798
AnnaBridge 161:aa5281ff4a02 799 /* @} */
AnnaBridge 161:aa5281ff4a02 800
AnnaBridge 161:aa5281ff4a02 801 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 802 }
AnnaBridge 161:aa5281ff4a02 803 #endif
AnnaBridge 161:aa5281ff4a02 804
AnnaBridge 161:aa5281ff4a02 805 /*! @}*/
AnnaBridge 161:aa5281ff4a02 806
AnnaBridge 161:aa5281ff4a02 807 #endif /* _FSL_SEMC_H_*/