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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_flexspi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 /*
AnnaBridge 170:e95d10626187 2 * The Clear BSD License
AnnaBridge 161:aa5281ff4a02 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 161:aa5281ff4a02 4 * Copyright 2016-2017 NXP
AnnaBridge 170:e95d10626187 5 * All rights reserved.
AnnaBridge 170:e95d10626187 6 *
AnnaBridge 161:aa5281ff4a02 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 170:e95d10626187 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 170:e95d10626187 9 * that the following conditions are met:
AnnaBridge 161:aa5281ff4a02 10 *
AnnaBridge 161:aa5281ff4a02 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 161:aa5281ff4a02 12 * of conditions and the following disclaimer.
AnnaBridge 161:aa5281ff4a02 13 *
AnnaBridge 161:aa5281ff4a02 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 161:aa5281ff4a02 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 161:aa5281ff4a02 16 * other materials provided with the distribution.
AnnaBridge 161:aa5281ff4a02 17 *
AnnaBridge 161:aa5281ff4a02 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 161:aa5281ff4a02 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 161:aa5281ff4a02 20 * software without specific prior written permission.
AnnaBridge 161:aa5281ff4a02 21 *
AnnaBridge 170:e95d10626187 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 161:aa5281ff4a02 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 161:aa5281ff4a02 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 161:aa5281ff4a02 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 161:aa5281ff4a02 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 161:aa5281ff4a02 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 161:aa5281ff4a02 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 161:aa5281ff4a02 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 161:aa5281ff4a02 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 161:aa5281ff4a02 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 161:aa5281ff4a02 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 161:aa5281ff4a02 33 */
AnnaBridge 161:aa5281ff4a02 34
AnnaBridge 161:aa5281ff4a02 35 #ifndef __FSL_FLEXSPI_H_
AnnaBridge 161:aa5281ff4a02 36 #define __FSL_FLEXSPI_H_
AnnaBridge 161:aa5281ff4a02 37
AnnaBridge 161:aa5281ff4a02 38 #include <stddef.h>
AnnaBridge 161:aa5281ff4a02 39 #include "fsl_device_registers.h"
AnnaBridge 161:aa5281ff4a02 40 #include "fsl_common.h"
AnnaBridge 161:aa5281ff4a02 41
AnnaBridge 161:aa5281ff4a02 42 /*!
AnnaBridge 161:aa5281ff4a02 43 * @addtogroup flexspi
AnnaBridge 161:aa5281ff4a02 44 * @{
AnnaBridge 161:aa5281ff4a02 45 */
AnnaBridge 161:aa5281ff4a02 46
AnnaBridge 161:aa5281ff4a02 47 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 48 * Definitions
AnnaBridge 161:aa5281ff4a02 49 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 50
AnnaBridge 161:aa5281ff4a02 51 /*! @name Driver version */
AnnaBridge 161:aa5281ff4a02 52 /*@{*/
AnnaBridge 170:e95d10626187 53 /*! @brief FLEXSPI driver version 2.0.2. */
AnnaBridge 170:e95d10626187 54 #define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
AnnaBridge 161:aa5281ff4a02 55 /*@}*/
AnnaBridge 161:aa5281ff4a02 56
AnnaBridge 161:aa5281ff4a02 57 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
AnnaBridge 161:aa5281ff4a02 58
AnnaBridge 161:aa5281ff4a02 59 /*! @breif Formula to form FLEXSPI instructions in LUT table. */
AnnaBridge 161:aa5281ff4a02 60 #define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
AnnaBridge 161:aa5281ff4a02 61 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
AnnaBridge 161:aa5281ff4a02 62 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
AnnaBridge 161:aa5281ff4a02 63
AnnaBridge 161:aa5281ff4a02 64 /*! @brief Status structure of FLEXSPI.*/
AnnaBridge 161:aa5281ff4a02 65 enum _flexspi_status
AnnaBridge 161:aa5281ff4a02 66 {
AnnaBridge 161:aa5281ff4a02 67 kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */
AnnaBridge 161:aa5281ff4a02 68 kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout
AnnaBridge 161:aa5281ff4a02 69 error occurred during FLEXSPI transfer. */
AnnaBridge 161:aa5281ff4a02 70 kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution
AnnaBridge 161:aa5281ff4a02 71 timeout error occurred during FLEXSPI transfer. */
AnnaBridge 161:aa5281ff4a02 72 kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error
AnnaBridge 161:aa5281ff4a02 73 occurred during FLEXSPI transfer. */
AnnaBridge 161:aa5281ff4a02 74 };
AnnaBridge 161:aa5281ff4a02 75
AnnaBridge 161:aa5281ff4a02 76 /*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */
AnnaBridge 161:aa5281ff4a02 77 enum _flexspi_command
AnnaBridge 161:aa5281ff4a02 78 {
AnnaBridge 161:aa5281ff4a02 79 kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */
AnnaBridge 161:aa5281ff4a02 80 kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 81 kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 82 kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 83 kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 84 kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 85 kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 86 kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 87 kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 88 kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */
AnnaBridge 161:aa5281ff4a02 89 kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */
AnnaBridge 161:aa5281ff4a02 90 kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */
AnnaBridge 161:aa5281ff4a02 91 kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/
AnnaBridge 161:aa5281ff4a02 92 kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller,
AnnaBridge 161:aa5281ff4a02 93 dummy cycles decided by RWDS. */
AnnaBridge 161:aa5281ff4a02 94 kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 95 kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 96 kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 97 kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 98 kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 99 kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 100 kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 101 kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 102 kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */
AnnaBridge 161:aa5281ff4a02 103 kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */
AnnaBridge 161:aa5281ff4a02 104 kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */
AnnaBridge 161:aa5281ff4a02 105 kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/
AnnaBridge 161:aa5281ff4a02 106 kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller,
AnnaBridge 161:aa5281ff4a02 107 dummy cycles decided by RWDS. */
AnnaBridge 161:aa5281ff4a02 108 kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the
AnnaBridge 161:aa5281ff4a02 109 instruction start pointer for next sequence */
AnnaBridge 161:aa5281ff4a02 110 };
AnnaBridge 161:aa5281ff4a02 111
AnnaBridge 161:aa5281ff4a02 112 /*! @brief pad definition of FLEXSPI, use to form LUT instruction. */
AnnaBridge 161:aa5281ff4a02 113 enum _flexspi_pad
AnnaBridge 161:aa5281ff4a02 114 {
AnnaBridge 161:aa5281ff4a02 115 kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */
AnnaBridge 161:aa5281ff4a02 116 kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */
AnnaBridge 161:aa5281ff4a02 117 kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */
AnnaBridge 161:aa5281ff4a02 118 kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */
AnnaBridge 161:aa5281ff4a02 119 };
AnnaBridge 161:aa5281ff4a02 120
AnnaBridge 161:aa5281ff4a02 121 /*! @brief FLEXSPI interrupt status flags.*/
AnnaBridge 161:aa5281ff4a02 122 typedef enum _flexspi_flags
AnnaBridge 161:aa5281ff4a02 123 {
AnnaBridge 161:aa5281ff4a02 124 kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */
AnnaBridge 161:aa5281ff4a02 125 kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */
AnnaBridge 161:aa5281ff4a02 126 kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
AnnaBridge 161:aa5281ff4a02 127 FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command
AnnaBridge 161:aa5281ff4a02 128 sequence because Async TX FIFO empty. */
AnnaBridge 161:aa5281ff4a02 129 kFLEXSPI_SckStoppedBecauseRxFullFlag =
AnnaBridge 161:aa5281ff4a02 130 FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command
AnnaBridge 161:aa5281ff4a02 131 sequence because Async RX FIFO full. */
AnnaBridge 161:aa5281ff4a02 132 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
AnnaBridge 161:aa5281ff4a02 133 kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */
AnnaBridge 161:aa5281ff4a02 134 #endif
AnnaBridge 161:aa5281ff4a02 135 kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */
AnnaBridge 161:aa5281ff4a02 136 kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */
AnnaBridge 161:aa5281ff4a02 137 kFLEXSPI_AhbCommandSequenceErrorFlag =
AnnaBridge 161:aa5281ff4a02 138 FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */
AnnaBridge 161:aa5281ff4a02 139 kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */
AnnaBridge 161:aa5281ff4a02 140 kFLEXSPI_AhbCommandGrantTimeoutFlag =
AnnaBridge 161:aa5281ff4a02 141 FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */
AnnaBridge 161:aa5281ff4a02 142 kFLEXSPI_IpCommandGrantTimeoutFlag =
AnnaBridge 161:aa5281ff4a02 143 FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */
AnnaBridge 161:aa5281ff4a02 144 kFLEXSPI_IpCommandExcutionDoneFlag =
AnnaBridge 161:aa5281ff4a02 145 FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */
AnnaBridge 161:aa5281ff4a02 146 kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */
AnnaBridge 161:aa5281ff4a02 147 } flexspi_flags_t;
AnnaBridge 161:aa5281ff4a02 148
AnnaBridge 161:aa5281ff4a02 149 /*! @brief FLEXSPI sample clock source selection for Flash Reading.*/
AnnaBridge 161:aa5281ff4a02 150 typedef enum _flexspi_read_sample_clock
AnnaBridge 161:aa5281ff4a02 151 {
AnnaBridge 161:aa5281ff4a02 152 kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller
AnnaBridge 161:aa5281ff4a02 153 and loopback internally. */
AnnaBridge 161:aa5281ff4a02 154 kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller
AnnaBridge 161:aa5281ff4a02 155 and loopback from DQS pad. */
AnnaBridge 161:aa5281ff4a02 156 kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */
AnnaBridge 161:aa5281ff4a02 157 kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */
AnnaBridge 161:aa5281ff4a02 158 } flexspi_read_sample_clock_t;
AnnaBridge 161:aa5281ff4a02 159
AnnaBridge 161:aa5281ff4a02 160 /*! @brief FLEXSPI interval unit for flash device select.*/
AnnaBridge 161:aa5281ff4a02 161 typedef enum _flexspi_cs_interval_cycle_unit
AnnaBridge 161:aa5281ff4a02 162 {
AnnaBridge 161:aa5281ff4a02 163 kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */
AnnaBridge 161:aa5281ff4a02 164 kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */
AnnaBridge 161:aa5281ff4a02 165 } flexspi_cs_interval_cycle_unit_t;
AnnaBridge 161:aa5281ff4a02 166
AnnaBridge 161:aa5281ff4a02 167 /*! @brief FLEXSPI AHB wait interval unit for writting.*/
AnnaBridge 161:aa5281ff4a02 168 typedef enum _flexspi_ahb_write_wait_unit
AnnaBridge 161:aa5281ff4a02 169 {
AnnaBridge 161:aa5281ff4a02 170 kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 171 kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 172 kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 173 kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 174 kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 175 kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 176 kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 177 kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */
AnnaBridge 161:aa5281ff4a02 178 } flexspi_ahb_write_wait_unit_t;
AnnaBridge 161:aa5281ff4a02 179
AnnaBridge 161:aa5281ff4a02 180 /*! @brief Error Code when IP command Error detected.*/
AnnaBridge 161:aa5281ff4a02 181 typedef enum _flexspi_ip_error_code
AnnaBridge 161:aa5281ff4a02 182 {
AnnaBridge 161:aa5281ff4a02 183 kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */
AnnaBridge 161:aa5281ff4a02 184 kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */
AnnaBridge 161:aa5281ff4a02 185 kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
AnnaBridge 161:aa5281ff4a02 186 kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR
AnnaBridge 161:aa5281ff4a02 187 used in DDR sequence. */
AnnaBridge 161:aa5281ff4a02 188 kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
AnnaBridge 161:aa5281ff4a02 189 used in SDR sequence. */
AnnaBridge 161:aa5281ff4a02 190 kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole
AnnaBridge 161:aa5281ff4a02 191 flash address range (A1/A2/B1/B2). */
AnnaBridge 161:aa5281ff4a02 192 kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */
AnnaBridge 161:aa5281ff4a02 193 kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */
AnnaBridge 161:aa5281ff4a02 194 } flexspi_ip_error_code_t;
AnnaBridge 161:aa5281ff4a02 195
AnnaBridge 161:aa5281ff4a02 196 /*! @brief Error Code when AHB command Error detected.*/
AnnaBridge 161:aa5281ff4a02 197 typedef enum _flexspi_ahb_error_code
AnnaBridge 161:aa5281ff4a02 198 {
AnnaBridge 161:aa5281ff4a02 199 kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */
AnnaBridge 161:aa5281ff4a02 200 kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction
AnnaBridge 161:aa5281ff4a02 201 used in the sequence. */
AnnaBridge 161:aa5281ff4a02 202 kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */
AnnaBridge 161:aa5281ff4a02 203 kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used
AnnaBridge 161:aa5281ff4a02 204 in DDR sequence. */
AnnaBridge 161:aa5281ff4a02 205 kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR
AnnaBridge 161:aa5281ff4a02 206 used in SDR sequence. */
AnnaBridge 161:aa5281ff4a02 207 kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */
AnnaBridge 161:aa5281ff4a02 208 } flexspi_ahb_error_code_t;
AnnaBridge 161:aa5281ff4a02 209
AnnaBridge 161:aa5281ff4a02 210 /*! @brief FLEXSPI operation port select.*/
AnnaBridge 161:aa5281ff4a02 211 typedef enum _flexspi_port
AnnaBridge 161:aa5281ff4a02 212 {
AnnaBridge 161:aa5281ff4a02 213 kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */
AnnaBridge 161:aa5281ff4a02 214 kFLEXSPI_PortA2 = 0x1U, /*!< Access flash on A2 port. */
AnnaBridge 161:aa5281ff4a02 215 kFLEXSPI_PortB1 = 0x2U, /*!< Access flash on B1 port. */
AnnaBridge 161:aa5281ff4a02 216 kFLEXSPI_PortB2 = 0x3U, /*!< Access flash on B2 port. */
AnnaBridge 161:aa5281ff4a02 217 } flexspi_port_t;
AnnaBridge 161:aa5281ff4a02 218
AnnaBridge 161:aa5281ff4a02 219 /*! @brief Trigger source of current command sequence granted by arbitrator.*/
AnnaBridge 161:aa5281ff4a02 220 typedef enum _flexspi_arb_command_source
AnnaBridge 161:aa5281ff4a02 221 {
AnnaBridge 161:aa5281ff4a02 222 kFLEXSPI_AhbReadCommand = 0x0U,
AnnaBridge 161:aa5281ff4a02 223 kFLEXSPI_AhbWriteCommand = 0x1U,
AnnaBridge 161:aa5281ff4a02 224 kFLEXSPI_IpCommand = 0x2U,
AnnaBridge 161:aa5281ff4a02 225 kFLEXSPI_SuspendedCommand = 0x3U,
AnnaBridge 161:aa5281ff4a02 226 } flexspi_arb_command_source_t;
AnnaBridge 161:aa5281ff4a02 227
AnnaBridge 161:aa5281ff4a02 228 typedef enum _flexspi_command_type
AnnaBridge 161:aa5281ff4a02 229 {
AnnaBridge 161:aa5281ff4a02 230 kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */
AnnaBridge 161:aa5281ff4a02 231 kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */
AnnaBridge 161:aa5281ff4a02 232 kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
AnnaBridge 161:aa5281ff4a02 233 kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
AnnaBridge 161:aa5281ff4a02 234 } flexspi_command_type_t;
AnnaBridge 161:aa5281ff4a02 235
AnnaBridge 161:aa5281ff4a02 236 typedef struct _flexspi_ahbBuffer_config
AnnaBridge 161:aa5281ff4a02 237 {
AnnaBridge 170:e95d10626187 238 uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */
AnnaBridge 170:e95d10626187 239 uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
AnnaBridge 170:e95d10626187 240 uint16_t bufferSize; /*!< AHB buffer size in byte. */
AnnaBridge 170:e95d10626187 241 bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
AnnaBridge 170:e95d10626187 242 prefetch disable/enable seperately for each master. */
AnnaBridge 161:aa5281ff4a02 243 } flexspi_ahbBuffer_config_t;
AnnaBridge 161:aa5281ff4a02 244
AnnaBridge 161:aa5281ff4a02 245 /*! @brief FLEXSPI configuration structure. */
AnnaBridge 161:aa5281ff4a02 246 typedef struct _flexspi_config
AnnaBridge 161:aa5281ff4a02 247 {
AnnaBridge 161:aa5281ff4a02 248 flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */
AnnaBridge 161:aa5281ff4a02 249 bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */
AnnaBridge 161:aa5281ff4a02 250 bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins
AnnaBridge 161:aa5281ff4a02 251 (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */
AnnaBridge 161:aa5281ff4a02 252 bool enableDoze; /*!< Enable/disable doze mode support. */
AnnaBridge 161:aa5281ff4a02 253 bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half
AnnaBridge 161:aa5281ff4a02 254 speed commands. */
AnnaBridge 161:aa5281ff4a02 255 bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
AnnaBridge 161:aa5281ff4a02 256 output, when enable, Port B flash access is not available. */
AnnaBridge 161:aa5281ff4a02 257 bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
AnnaBridge 161:aa5281ff4a02 258 when enabled, same configuration in FLASHA1CRx is applied to all. */
AnnaBridge 161:aa5281ff4a02 259 uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution,
AnnaBridge 161:aa5281ff4a02 260 timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */
AnnaBridge 161:aa5281ff4a02 261 uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after
AnnaBridge 161:aa5281ff4a02 262 ipGrantTimeoutCycle*1024 AHB clock cycles. */
AnnaBridge 161:aa5281ff4a02 263 uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */
AnnaBridge 161:aa5281ff4a02 264 uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */
AnnaBridge 161:aa5281ff4a02 265 struct
AnnaBridge 161:aa5281ff4a02 266 {
AnnaBridge 161:aa5281ff4a02 267 bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */
AnnaBridge 161:aa5281ff4a02 268 bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */
AnnaBridge 161:aa5281ff4a02 269 uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant,
AnnaBridge 161:aa5281ff4a02 270 timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */
AnnaBridge 161:aa5281ff4a02 271 uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access,
AnnaBridge 161:aa5281ff4a02 272 timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */
AnnaBridge 161:aa5281ff4a02 273 uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence
AnnaBridge 161:aa5281ff4a02 274 resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */
AnnaBridge 161:aa5281ff4a02 275 flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
AnnaBridge 161:aa5281ff4a02 276 bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
AnnaBridge 161:aa5281ff4a02 277 when FLEXSPI returns STOP mode ACK. */
AnnaBridge 170:e95d10626187 278 bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation.
AnnaBridge 170:e95d10626187 279 when eanble, there is no AHB read burst start address alignment limitation. */
AnnaBridge 161:aa5281ff4a02 280 bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
AnnaBridge 161:aa5281ff4a02 281 will fetch more data than current AHB burst. */
AnnaBridge 161:aa5281ff4a02 282 bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled,
AnnaBridge 161:aa5281ff4a02 283 FLEXSPI return before waiting for command excution finished. */
AnnaBridge 161:aa5281ff4a02 284 bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */
AnnaBridge 161:aa5281ff4a02 285 } ahbConfig;
AnnaBridge 161:aa5281ff4a02 286 } flexspi_config_t;
AnnaBridge 161:aa5281ff4a02 287
AnnaBridge 161:aa5281ff4a02 288 /*! @brief External device configuration items. */
AnnaBridge 161:aa5281ff4a02 289 typedef struct _flexspi_device_config
AnnaBridge 161:aa5281ff4a02 290 {
AnnaBridge 161:aa5281ff4a02 291 uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */
AnnaBridge 161:aa5281ff4a02 292 bool isSck2Enabled; /*!< FLEXSPI use SCK2. */
AnnaBridge 161:aa5281ff4a02 293 uint32_t flashSize; /*!< Flash size in KByte. */
AnnaBridge 161:aa5281ff4a02 294 flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */
AnnaBridge 161:aa5281ff4a02 295 uint16_t CSInterval; /*!< CS line assert interval, mutiply CS interval unit to
AnnaBridge 161:aa5281ff4a02 296 get the CS line assert interval cycles. */
AnnaBridge 161:aa5281ff4a02 297 uint8_t CSHoldTime; /*!< CS line hold time. */
AnnaBridge 161:aa5281ff4a02 298 uint8_t CSSetupTime; /*!< CS line setup time. */
AnnaBridge 161:aa5281ff4a02 299 uint8_t dataValidTime; /*!< Data valid time for external device. */
AnnaBridge 161:aa5281ff4a02 300 uint8_t columnspace; /*!< Column space size. */
AnnaBridge 161:aa5281ff4a02 301 bool enableWordAddress; /*!< If enable word address.*/
AnnaBridge 161:aa5281ff4a02 302 uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */
AnnaBridge 161:aa5281ff4a02 303 uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */
AnnaBridge 161:aa5281ff4a02 304 uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */
AnnaBridge 161:aa5281ff4a02 305 uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */
AnnaBridge 161:aa5281ff4a02 306 flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */
AnnaBridge 161:aa5281ff4a02 307 uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, mutiply AHB write interval
AnnaBridge 161:aa5281ff4a02 308 unit to get the AHB write wait cycles. */
AnnaBridge 161:aa5281ff4a02 309 bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
AnnaBridge 161:aa5281ff4a02 310 when writing to external device. */
AnnaBridge 161:aa5281ff4a02 311 } flexspi_device_config_t;
AnnaBridge 161:aa5281ff4a02 312
AnnaBridge 161:aa5281ff4a02 313 /*! @brief Transfer structure for FLEXSPI. */
AnnaBridge 161:aa5281ff4a02 314 typedef struct _flexspi_transfer
AnnaBridge 161:aa5281ff4a02 315 {
AnnaBridge 161:aa5281ff4a02 316 uint32_t deviceAddress; /*!< Operation device address. */
AnnaBridge 161:aa5281ff4a02 317 flexspi_port_t port; /*!< Operation port. */
AnnaBridge 161:aa5281ff4a02 318 flexspi_command_type_t cmdType; /*!< Execution command type. */
AnnaBridge 161:aa5281ff4a02 319 uint8_t seqIndex; /*!< Sequence ID for command. */
AnnaBridge 161:aa5281ff4a02 320 uint8_t SeqNumber; /*!< Sequence number for command. */
AnnaBridge 161:aa5281ff4a02 321 uint32_t *data; /*!< Data buffer. */
AnnaBridge 161:aa5281ff4a02 322 size_t dataSize; /*!< Data size in bytes. */
AnnaBridge 161:aa5281ff4a02 323 } flexspi_transfer_t;
AnnaBridge 161:aa5281ff4a02 324
AnnaBridge 161:aa5281ff4a02 325 /* Forward declaration of the handle typedef. */
AnnaBridge 161:aa5281ff4a02 326 typedef struct _flexspi_handle flexspi_handle_t;
AnnaBridge 161:aa5281ff4a02 327
AnnaBridge 161:aa5281ff4a02 328 /*! @brief FLEXSPI transfer callback function. */
AnnaBridge 161:aa5281ff4a02 329 typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base,
AnnaBridge 161:aa5281ff4a02 330 flexspi_handle_t *handle,
AnnaBridge 161:aa5281ff4a02 331 status_t status,
AnnaBridge 161:aa5281ff4a02 332 void *userData);
AnnaBridge 161:aa5281ff4a02 333
AnnaBridge 161:aa5281ff4a02 334 /*! @brief Transfer handle structure for FLEXSPI. */
AnnaBridge 161:aa5281ff4a02 335 struct _flexspi_handle
AnnaBridge 161:aa5281ff4a02 336 {
AnnaBridge 161:aa5281ff4a02 337 uint32_t state; /*!< Internal state for FLEXSPI transfer */
AnnaBridge 161:aa5281ff4a02 338 uint32_t *data; /*!< Data buffer. */
AnnaBridge 161:aa5281ff4a02 339 size_t dataSize; /*!< Remaining Data size in bytes. */
AnnaBridge 161:aa5281ff4a02 340 size_t transferTotalSize; /*!< Total Data size in bytes. */
AnnaBridge 161:aa5281ff4a02 341 flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */
AnnaBridge 161:aa5281ff4a02 342 void *userData; /*!< FLEXSPI callback function parameter.*/
AnnaBridge 161:aa5281ff4a02 343 };
AnnaBridge 161:aa5281ff4a02 344
AnnaBridge 161:aa5281ff4a02 345 /*******************************************************************************
AnnaBridge 161:aa5281ff4a02 346 * API
AnnaBridge 161:aa5281ff4a02 347 ******************************************************************************/
AnnaBridge 161:aa5281ff4a02 348
AnnaBridge 161:aa5281ff4a02 349 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 350 extern "C" {
AnnaBridge 161:aa5281ff4a02 351 #endif /*_cplusplus. */
AnnaBridge 161:aa5281ff4a02 352
AnnaBridge 161:aa5281ff4a02 353 /*!
AnnaBridge 161:aa5281ff4a02 354 * @name Initialization and deinitialization
AnnaBridge 161:aa5281ff4a02 355 * @{
AnnaBridge 161:aa5281ff4a02 356 */
AnnaBridge 161:aa5281ff4a02 357 /*!
AnnaBridge 161:aa5281ff4a02 358 * @brief Initializes the FLEXSPI module and internal state.
AnnaBridge 161:aa5281ff4a02 359 *
AnnaBridge 161:aa5281ff4a02 360 * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the
AnnaBridge 161:aa5281ff4a02 361 * input configure parameters. Users should call this function before any FLEXSPI operations.
AnnaBridge 161:aa5281ff4a02 362 *
AnnaBridge 161:aa5281ff4a02 363 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 364 * @param config FLEXSPI configure structure.
AnnaBridge 161:aa5281ff4a02 365 */
AnnaBridge 161:aa5281ff4a02 366 void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
AnnaBridge 161:aa5281ff4a02 367
AnnaBridge 161:aa5281ff4a02 368 /*!
AnnaBridge 161:aa5281ff4a02 369 * @brief Gets default settings for FLEXSPI.
AnnaBridge 161:aa5281ff4a02 370 *
AnnaBridge 161:aa5281ff4a02 371 * @param config FLEXSPI configuration structure.
AnnaBridge 161:aa5281ff4a02 372 */
AnnaBridge 161:aa5281ff4a02 373 void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
AnnaBridge 161:aa5281ff4a02 374
AnnaBridge 161:aa5281ff4a02 375 /*!
AnnaBridge 161:aa5281ff4a02 376 * @brief Deinitializes the FLEXSPI module.
AnnaBridge 161:aa5281ff4a02 377 *
AnnaBridge 161:aa5281ff4a02 378 * Clears the FLEXSPI state and FLEXSPI module registers.
AnnaBridge 161:aa5281ff4a02 379 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 380 */
AnnaBridge 161:aa5281ff4a02 381 void FLEXSPI_Deinit(FLEXSPI_Type *base);
AnnaBridge 161:aa5281ff4a02 382
AnnaBridge 161:aa5281ff4a02 383 /*!
AnnaBridge 161:aa5281ff4a02 384 * @brief Configures the connected device parameter.
AnnaBridge 161:aa5281ff4a02 385 *
AnnaBridge 161:aa5281ff4a02 386 * This function configures the connected device relevant parameters, such as the size, command, and so on.
AnnaBridge 161:aa5281ff4a02 387 * The flash configuration value cannot have a default value. The user needs to configure it according to the
AnnaBridge 161:aa5281ff4a02 388 * connected device.
AnnaBridge 161:aa5281ff4a02 389 *
AnnaBridge 161:aa5281ff4a02 390 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 391 * @param config Flash configuration parameters.
AnnaBridge 161:aa5281ff4a02 392 * @param port FLEXSPI Operation port.
AnnaBridge 161:aa5281ff4a02 393 */
AnnaBridge 161:aa5281ff4a02 394 void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
AnnaBridge 161:aa5281ff4a02 395
AnnaBridge 161:aa5281ff4a02 396 /*!
AnnaBridge 161:aa5281ff4a02 397 * @brief Software reset for the FLEXSPI logic.
AnnaBridge 161:aa5281ff4a02 398 *
AnnaBridge 161:aa5281ff4a02 399 * This function sets the software reset flags for both AHB and buffer domain and
AnnaBridge 161:aa5281ff4a02 400 * resets both AHB buffer and also IP FIFOs.
AnnaBridge 161:aa5281ff4a02 401 *
AnnaBridge 161:aa5281ff4a02 402 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 403 */
AnnaBridge 161:aa5281ff4a02 404 static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
AnnaBridge 161:aa5281ff4a02 405 {
AnnaBridge 161:aa5281ff4a02 406 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
AnnaBridge 161:aa5281ff4a02 407 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
AnnaBridge 161:aa5281ff4a02 408 {
AnnaBridge 161:aa5281ff4a02 409 }
AnnaBridge 161:aa5281ff4a02 410 }
AnnaBridge 161:aa5281ff4a02 411
AnnaBridge 161:aa5281ff4a02 412 /*!
AnnaBridge 161:aa5281ff4a02 413 * @brief Enables or disables the FLEXSPI module.
AnnaBridge 161:aa5281ff4a02 414 *
AnnaBridge 161:aa5281ff4a02 415 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 416 * @param enable True means enable FLEXSPI, false means disable.
AnnaBridge 161:aa5281ff4a02 417 */
AnnaBridge 161:aa5281ff4a02 418 static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 419 {
AnnaBridge 161:aa5281ff4a02 420 if (enable)
AnnaBridge 161:aa5281ff4a02 421 {
AnnaBridge 161:aa5281ff4a02 422 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
AnnaBridge 161:aa5281ff4a02 423 }
AnnaBridge 161:aa5281ff4a02 424 else
AnnaBridge 161:aa5281ff4a02 425 {
AnnaBridge 161:aa5281ff4a02 426 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
AnnaBridge 161:aa5281ff4a02 427 }
AnnaBridge 161:aa5281ff4a02 428 }
AnnaBridge 161:aa5281ff4a02 429
AnnaBridge 161:aa5281ff4a02 430 /* @} */
AnnaBridge 161:aa5281ff4a02 431
AnnaBridge 161:aa5281ff4a02 432 /*!
AnnaBridge 161:aa5281ff4a02 433 * @name Interrupts
AnnaBridge 161:aa5281ff4a02 434 * @{
AnnaBridge 161:aa5281ff4a02 435 */
AnnaBridge 161:aa5281ff4a02 436 /*!
AnnaBridge 161:aa5281ff4a02 437 * @brief Enables the FLEXSPI interrupts.
AnnaBridge 161:aa5281ff4a02 438 *
AnnaBridge 161:aa5281ff4a02 439 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 440 * @param mask FLEXSPI interrupt source.
AnnaBridge 161:aa5281ff4a02 441 */
AnnaBridge 161:aa5281ff4a02 442 static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 443 {
AnnaBridge 161:aa5281ff4a02 444 base->INTEN |= mask;
AnnaBridge 161:aa5281ff4a02 445 }
AnnaBridge 161:aa5281ff4a02 446
AnnaBridge 161:aa5281ff4a02 447 /*!
AnnaBridge 161:aa5281ff4a02 448 * @brief Disable the FLEXSPI interrupts.
AnnaBridge 161:aa5281ff4a02 449 *
AnnaBridge 161:aa5281ff4a02 450 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 451 * @param mask FLEXSPI interrupt source.
AnnaBridge 161:aa5281ff4a02 452 */
AnnaBridge 161:aa5281ff4a02 453 static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 454 {
AnnaBridge 161:aa5281ff4a02 455 base->INTEN &= ~mask;
AnnaBridge 161:aa5281ff4a02 456 }
AnnaBridge 161:aa5281ff4a02 457
AnnaBridge 161:aa5281ff4a02 458 /* @} */
AnnaBridge 161:aa5281ff4a02 459
AnnaBridge 161:aa5281ff4a02 460 /*! @name DMA control */
AnnaBridge 161:aa5281ff4a02 461 /*@{*/
AnnaBridge 161:aa5281ff4a02 462
AnnaBridge 161:aa5281ff4a02 463 /*!
AnnaBridge 161:aa5281ff4a02 464 * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests.
AnnaBridge 161:aa5281ff4a02 465 *
AnnaBridge 161:aa5281ff4a02 466 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 467 * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable.
AnnaBridge 161:aa5281ff4a02 468 */
AnnaBridge 161:aa5281ff4a02 469 static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 470 {
AnnaBridge 161:aa5281ff4a02 471 if (enable)
AnnaBridge 161:aa5281ff4a02 472 {
AnnaBridge 161:aa5281ff4a02 473 base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK;
AnnaBridge 161:aa5281ff4a02 474 }
AnnaBridge 161:aa5281ff4a02 475 else
AnnaBridge 161:aa5281ff4a02 476 {
AnnaBridge 161:aa5281ff4a02 477 base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK;
AnnaBridge 161:aa5281ff4a02 478 }
AnnaBridge 161:aa5281ff4a02 479 }
AnnaBridge 161:aa5281ff4a02 480
AnnaBridge 161:aa5281ff4a02 481 /*!
AnnaBridge 161:aa5281ff4a02 482 * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests.
AnnaBridge 161:aa5281ff4a02 483 *
AnnaBridge 161:aa5281ff4a02 484 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 485 * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable.
AnnaBridge 161:aa5281ff4a02 486 */
AnnaBridge 161:aa5281ff4a02 487 static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 488 {
AnnaBridge 161:aa5281ff4a02 489 if (enable)
AnnaBridge 161:aa5281ff4a02 490 {
AnnaBridge 161:aa5281ff4a02 491 base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK;
AnnaBridge 161:aa5281ff4a02 492 }
AnnaBridge 161:aa5281ff4a02 493 else
AnnaBridge 161:aa5281ff4a02 494 {
AnnaBridge 161:aa5281ff4a02 495 base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK;
AnnaBridge 161:aa5281ff4a02 496 }
AnnaBridge 161:aa5281ff4a02 497 }
AnnaBridge 161:aa5281ff4a02 498
AnnaBridge 161:aa5281ff4a02 499 /*!
AnnaBridge 161:aa5281ff4a02 500 * @brief Gets FLEXSPI IP tx fifo address for DMA transfer.
AnnaBridge 161:aa5281ff4a02 501 *
AnnaBridge 161:aa5281ff4a02 502 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 503 * @retval The tx fifo address.
AnnaBridge 161:aa5281ff4a02 504 */
AnnaBridge 161:aa5281ff4a02 505 static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
AnnaBridge 161:aa5281ff4a02 506 {
AnnaBridge 161:aa5281ff4a02 507 return (uint32_t)&base->TFDR[0];
AnnaBridge 161:aa5281ff4a02 508 }
AnnaBridge 161:aa5281ff4a02 509
AnnaBridge 161:aa5281ff4a02 510 /*!
AnnaBridge 161:aa5281ff4a02 511 * @brief Gets FLEXSPI IP rx fifo address for DMA transfer.
AnnaBridge 161:aa5281ff4a02 512 *
AnnaBridge 161:aa5281ff4a02 513 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 514 * @retval The rx fifo address.
AnnaBridge 161:aa5281ff4a02 515 */
AnnaBridge 161:aa5281ff4a02 516 static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
AnnaBridge 161:aa5281ff4a02 517 {
AnnaBridge 161:aa5281ff4a02 518 return (uint32_t)&base->RFDR[0];
AnnaBridge 161:aa5281ff4a02 519 }
AnnaBridge 161:aa5281ff4a02 520
AnnaBridge 161:aa5281ff4a02 521 /*@}*/
AnnaBridge 161:aa5281ff4a02 522
AnnaBridge 161:aa5281ff4a02 523 /*! @name FIFO control */
AnnaBridge 161:aa5281ff4a02 524 /*@{*/
AnnaBridge 161:aa5281ff4a02 525
AnnaBridge 161:aa5281ff4a02 526 /*! @brief Clears the FLEXSPI IP FIFO logic.
AnnaBridge 161:aa5281ff4a02 527 *
AnnaBridge 161:aa5281ff4a02 528 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 529 * @param txFifo Pass true to reset TX FIFO.
AnnaBridge 161:aa5281ff4a02 530 * @param rxFifo Pass true to reset RX FIFO.
AnnaBridge 161:aa5281ff4a02 531 */
AnnaBridge 161:aa5281ff4a02 532 static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
AnnaBridge 161:aa5281ff4a02 533 {
AnnaBridge 161:aa5281ff4a02 534 if (txFifo)
AnnaBridge 161:aa5281ff4a02 535 {
AnnaBridge 161:aa5281ff4a02 536 base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
AnnaBridge 161:aa5281ff4a02 537 }
AnnaBridge 161:aa5281ff4a02 538 if (rxFifo)
AnnaBridge 161:aa5281ff4a02 539 {
AnnaBridge 161:aa5281ff4a02 540 base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
AnnaBridge 161:aa5281ff4a02 541 }
AnnaBridge 161:aa5281ff4a02 542 }
AnnaBridge 161:aa5281ff4a02 543
AnnaBridge 161:aa5281ff4a02 544 /*!
AnnaBridge 161:aa5281ff4a02 545 * @brief Gets the valid data entries in the FLEXSPI FIFOs.
AnnaBridge 161:aa5281ff4a02 546 *
AnnaBridge 161:aa5281ff4a02 547 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 548 * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
AnnaBridge 161:aa5281ff4a02 549 * Pass NULL if this value is not required.
AnnaBridge 161:aa5281ff4a02 550 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
AnnaBridge 161:aa5281ff4a02 551 * Pass NULL if this value is not required.
AnnaBridge 161:aa5281ff4a02 552 */
AnnaBridge 161:aa5281ff4a02 553 static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
AnnaBridge 161:aa5281ff4a02 554 {
AnnaBridge 161:aa5281ff4a02 555 if (txCount)
AnnaBridge 161:aa5281ff4a02 556 {
AnnaBridge 161:aa5281ff4a02 557 *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
AnnaBridge 161:aa5281ff4a02 558 }
AnnaBridge 161:aa5281ff4a02 559 if (rxCount)
AnnaBridge 161:aa5281ff4a02 560 {
AnnaBridge 161:aa5281ff4a02 561 *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
AnnaBridge 161:aa5281ff4a02 562 }
AnnaBridge 161:aa5281ff4a02 563 }
AnnaBridge 161:aa5281ff4a02 564
AnnaBridge 161:aa5281ff4a02 565 /*@}*/
AnnaBridge 161:aa5281ff4a02 566
AnnaBridge 161:aa5281ff4a02 567 /*!
AnnaBridge 161:aa5281ff4a02 568 * @name Status
AnnaBridge 161:aa5281ff4a02 569 * @{
AnnaBridge 161:aa5281ff4a02 570 */
AnnaBridge 161:aa5281ff4a02 571 /*!
AnnaBridge 161:aa5281ff4a02 572 * @brief Get the FLEXSPI interrupt status flags.
AnnaBridge 161:aa5281ff4a02 573 *
AnnaBridge 161:aa5281ff4a02 574 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 575 * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status.
AnnaBridge 161:aa5281ff4a02 576 */
AnnaBridge 161:aa5281ff4a02 577 static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
AnnaBridge 161:aa5281ff4a02 578 {
AnnaBridge 161:aa5281ff4a02 579 return base->INTR;
AnnaBridge 161:aa5281ff4a02 580 }
AnnaBridge 161:aa5281ff4a02 581
AnnaBridge 161:aa5281ff4a02 582 /*!
AnnaBridge 161:aa5281ff4a02 583 * @brief Get the FLEXSPI interrupt status flags.
AnnaBridge 161:aa5281ff4a02 584 *
AnnaBridge 161:aa5281ff4a02 585 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 586 * @param interrupt status flag.
AnnaBridge 161:aa5281ff4a02 587 */
AnnaBridge 161:aa5281ff4a02 588 static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
AnnaBridge 161:aa5281ff4a02 589 {
AnnaBridge 161:aa5281ff4a02 590 base->INTR |= mask;
AnnaBridge 161:aa5281ff4a02 591 }
AnnaBridge 161:aa5281ff4a02 592
AnnaBridge 161:aa5281ff4a02 593 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
AnnaBridge 161:aa5281ff4a02 594 /*! @brief Gets the sampling clock phase selection after Data Learning.
AnnaBridge 161:aa5281ff4a02 595 *
AnnaBridge 161:aa5281ff4a02 596 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 597 * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA.
AnnaBridge 161:aa5281ff4a02 598 * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB.
AnnaBridge 161:aa5281ff4a02 599 */
AnnaBridge 161:aa5281ff4a02 600 static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase)
AnnaBridge 161:aa5281ff4a02 601 {
AnnaBridge 161:aa5281ff4a02 602 if (portAPhase)
AnnaBridge 161:aa5281ff4a02 603 {
AnnaBridge 161:aa5281ff4a02 604 *portAPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT;
AnnaBridge 161:aa5281ff4a02 605 }
AnnaBridge 161:aa5281ff4a02 606
AnnaBridge 161:aa5281ff4a02 607 if (portBPhase)
AnnaBridge 161:aa5281ff4a02 608 {
AnnaBridge 161:aa5281ff4a02 609 *portBPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT;
AnnaBridge 161:aa5281ff4a02 610 }
AnnaBridge 161:aa5281ff4a02 611 }
AnnaBridge 161:aa5281ff4a02 612 #endif
AnnaBridge 161:aa5281ff4a02 613
AnnaBridge 161:aa5281ff4a02 614 /*! @brief Gets the trigger source of current command sequence granted by arbitrator.
AnnaBridge 161:aa5281ff4a02 615 *
AnnaBridge 161:aa5281ff4a02 616 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 617 * @retval trigger source of current command sequence.
AnnaBridge 161:aa5281ff4a02 618 */
AnnaBridge 161:aa5281ff4a02 619 static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
AnnaBridge 161:aa5281ff4a02 620 {
AnnaBridge 161:aa5281ff4a02 621 return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT);
AnnaBridge 161:aa5281ff4a02 622 }
AnnaBridge 161:aa5281ff4a02 623
AnnaBridge 161:aa5281ff4a02 624 /*! @brief Gets the error code when IP command error detected.
AnnaBridge 161:aa5281ff4a02 625 *
AnnaBridge 161:aa5281ff4a02 626 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 627 * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
AnnaBridge 161:aa5281ff4a02 628 * @retval error code when IP command error detected.
AnnaBridge 161:aa5281ff4a02 629 */
AnnaBridge 161:aa5281ff4a02 630 static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
AnnaBridge 161:aa5281ff4a02 631 {
AnnaBridge 161:aa5281ff4a02 632 *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT;
AnnaBridge 161:aa5281ff4a02 633 return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT);
AnnaBridge 161:aa5281ff4a02 634 }
AnnaBridge 161:aa5281ff4a02 635
AnnaBridge 161:aa5281ff4a02 636 /*! @brief Gets the error code when AHB command error detected.
AnnaBridge 161:aa5281ff4a02 637 *
AnnaBridge 161:aa5281ff4a02 638 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 639 * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected.
AnnaBridge 161:aa5281ff4a02 640 * @retval error code when AHB command error detected.
AnnaBridge 161:aa5281ff4a02 641 */
AnnaBridge 161:aa5281ff4a02 642 static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
AnnaBridge 161:aa5281ff4a02 643 {
AnnaBridge 161:aa5281ff4a02 644 *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
AnnaBridge 161:aa5281ff4a02 645 return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >>
AnnaBridge 161:aa5281ff4a02 646 FLEXSPI_STS1_AHBCMDERRCODE_SHIFT);
AnnaBridge 161:aa5281ff4a02 647 }
AnnaBridge 161:aa5281ff4a02 648
AnnaBridge 161:aa5281ff4a02 649 /*! @brief Returns whether the bus is idle.
AnnaBridge 161:aa5281ff4a02 650 *
AnnaBridge 161:aa5281ff4a02 651 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 652 * @retval true Bus is idle.
AnnaBridge 161:aa5281ff4a02 653 * @retval false Bus is busy.
AnnaBridge 161:aa5281ff4a02 654 */
AnnaBridge 161:aa5281ff4a02 655 static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
AnnaBridge 161:aa5281ff4a02 656 {
AnnaBridge 161:aa5281ff4a02 657 return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK);
AnnaBridge 161:aa5281ff4a02 658 }
AnnaBridge 161:aa5281ff4a02 659 /*@}*/
AnnaBridge 161:aa5281ff4a02 660
AnnaBridge 161:aa5281ff4a02 661 /*!
AnnaBridge 161:aa5281ff4a02 662 * @name Bus Operations
AnnaBridge 161:aa5281ff4a02 663 * @{
AnnaBridge 161:aa5281ff4a02 664 */
AnnaBridge 161:aa5281ff4a02 665
AnnaBridge 161:aa5281ff4a02 666 /*! @brief Enables/disables the FLEXSPI IP command parallel mode.
AnnaBridge 161:aa5281ff4a02 667 *
AnnaBridge 161:aa5281ff4a02 668 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 669 * @param enable True means enable parallel mode, false means disable parallel mode.
AnnaBridge 161:aa5281ff4a02 670 */
AnnaBridge 161:aa5281ff4a02 671 static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 672 {
AnnaBridge 161:aa5281ff4a02 673 if (enable)
AnnaBridge 161:aa5281ff4a02 674 {
AnnaBridge 161:aa5281ff4a02 675 base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK;
AnnaBridge 161:aa5281ff4a02 676 }
AnnaBridge 161:aa5281ff4a02 677 else
AnnaBridge 161:aa5281ff4a02 678 {
AnnaBridge 161:aa5281ff4a02 679 base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
AnnaBridge 161:aa5281ff4a02 680 }
AnnaBridge 161:aa5281ff4a02 681 }
AnnaBridge 161:aa5281ff4a02 682
AnnaBridge 161:aa5281ff4a02 683 /*! @brief Enables/disables the FLEXSPI AHB command parallel mode.
AnnaBridge 161:aa5281ff4a02 684 *
AnnaBridge 161:aa5281ff4a02 685 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 686 * @param enable True means enable parallel mode, false means disable parallel mode.
AnnaBridge 161:aa5281ff4a02 687 */
AnnaBridge 161:aa5281ff4a02 688 static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
AnnaBridge 161:aa5281ff4a02 689 {
AnnaBridge 161:aa5281ff4a02 690 if (enable)
AnnaBridge 161:aa5281ff4a02 691 {
AnnaBridge 161:aa5281ff4a02 692 base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK;
AnnaBridge 161:aa5281ff4a02 693 }
AnnaBridge 161:aa5281ff4a02 694 else
AnnaBridge 161:aa5281ff4a02 695 {
AnnaBridge 161:aa5281ff4a02 696 base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
AnnaBridge 161:aa5281ff4a02 697 }
AnnaBridge 161:aa5281ff4a02 698 }
AnnaBridge 161:aa5281ff4a02 699
AnnaBridge 161:aa5281ff4a02 700 /*! @brief Updates the LUT table.
AnnaBridge 161:aa5281ff4a02 701 *
AnnaBridge 161:aa5281ff4a02 702 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 703 * @param index From which index start to update. It could be any index of the LUT table, which
AnnaBridge 161:aa5281ff4a02 704 * also allows user to update command content inside a command. Each command consists of up to
AnnaBridge 161:aa5281ff4a02 705 * 8 instructions and occupy 4*32-bit memory.
AnnaBridge 161:aa5281ff4a02 706 * @param cmd Command sequence array.
AnnaBridge 161:aa5281ff4a02 707 * @param count Number of sequences.
AnnaBridge 161:aa5281ff4a02 708 */
AnnaBridge 161:aa5281ff4a02 709 void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
AnnaBridge 161:aa5281ff4a02 710
AnnaBridge 161:aa5281ff4a02 711 /*!
AnnaBridge 161:aa5281ff4a02 712 * @brief Writes data into FIFO.
AnnaBridge 161:aa5281ff4a02 713 *
AnnaBridge 161:aa5281ff4a02 714 * @param base FLEXSPI peripheral base address
AnnaBridge 161:aa5281ff4a02 715 * @param data The data bytes to send
AnnaBridge 161:aa5281ff4a02 716 * @param fifoIndex Destination fifo index.
AnnaBridge 161:aa5281ff4a02 717 */
AnnaBridge 161:aa5281ff4a02 718 static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
AnnaBridge 161:aa5281ff4a02 719 {
AnnaBridge 161:aa5281ff4a02 720 base->TFDR[fifoIndex] = data;
AnnaBridge 161:aa5281ff4a02 721 }
AnnaBridge 161:aa5281ff4a02 722
AnnaBridge 161:aa5281ff4a02 723 /*!
AnnaBridge 161:aa5281ff4a02 724 * @brief Receives data from data FIFO.
AnnaBridge 161:aa5281ff4a02 725 *
AnnaBridge 161:aa5281ff4a02 726 * @param base FLEXSPI peripheral base address
AnnaBridge 161:aa5281ff4a02 727 * @param fifoIndex Source fifo index.
AnnaBridge 161:aa5281ff4a02 728 * @return The data in the FIFO.
AnnaBridge 161:aa5281ff4a02 729 */
AnnaBridge 161:aa5281ff4a02 730 static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
AnnaBridge 161:aa5281ff4a02 731 {
AnnaBridge 161:aa5281ff4a02 732 return base->RFDR[fifoIndex];
AnnaBridge 161:aa5281ff4a02 733 }
AnnaBridge 161:aa5281ff4a02 734
AnnaBridge 161:aa5281ff4a02 735 /*!
AnnaBridge 161:aa5281ff4a02 736 * @brief Sends a buffer of data bytes using blocking method.
AnnaBridge 161:aa5281ff4a02 737 * @note This function blocks via polling until all bytes have been sent.
AnnaBridge 161:aa5281ff4a02 738 * @param base FLEXSPI peripheral base address
AnnaBridge 161:aa5281ff4a02 739 * @param buffer The data bytes to send
AnnaBridge 161:aa5281ff4a02 740 * @param size The number of data bytes to send
AnnaBridge 161:aa5281ff4a02 741 * @retval kStatus_Success write success without error
AnnaBridge 161:aa5281ff4a02 742 * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
AnnaBridge 161:aa5281ff4a02 743 * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
AnnaBridge 161:aa5281ff4a02 744 * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
AnnaBridge 161:aa5281ff4a02 745 */
AnnaBridge 161:aa5281ff4a02 746 status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
AnnaBridge 161:aa5281ff4a02 747
AnnaBridge 161:aa5281ff4a02 748 /*!
AnnaBridge 161:aa5281ff4a02 749 * @brief Receives a buffer of data bytes using a blocking method.
AnnaBridge 161:aa5281ff4a02 750 * @note This function blocks via polling until all bytes have been sent.
AnnaBridge 161:aa5281ff4a02 751 * @param base FLEXSPI peripheral base address
AnnaBridge 161:aa5281ff4a02 752 * @param buffer The data bytes to send
AnnaBridge 161:aa5281ff4a02 753 * @param size The number of data bytes to receive
AnnaBridge 161:aa5281ff4a02 754 * @retval kStatus_Success read success without error
AnnaBridge 161:aa5281ff4a02 755 * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
AnnaBridge 161:aa5281ff4a02 756 * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
AnnaBridge 161:aa5281ff4a02 757 * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
AnnaBridge 161:aa5281ff4a02 758 */
AnnaBridge 161:aa5281ff4a02 759 status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
AnnaBridge 161:aa5281ff4a02 760
AnnaBridge 161:aa5281ff4a02 761 /*!
AnnaBridge 161:aa5281ff4a02 762 * @brief Execute command to transfer a buffer data bytes using a blocking method.
AnnaBridge 161:aa5281ff4a02 763 * @param base FLEXSPI peripheral base address
AnnaBridge 161:aa5281ff4a02 764 * @param xfer pointer to the transfer structure.
AnnaBridge 161:aa5281ff4a02 765 * @retval kStatus_Success command transfer success without error
AnnaBridge 161:aa5281ff4a02 766 * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout
AnnaBridge 161:aa5281ff4a02 767 * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
AnnaBridge 161:aa5281ff4a02 768 * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
AnnaBridge 161:aa5281ff4a02 769 */
AnnaBridge 161:aa5281ff4a02 770 status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
AnnaBridge 161:aa5281ff4a02 771 /*! @} */
AnnaBridge 161:aa5281ff4a02 772
AnnaBridge 161:aa5281ff4a02 773 /*!
AnnaBridge 161:aa5281ff4a02 774 * @name Transactional
AnnaBridge 161:aa5281ff4a02 775 * @{
AnnaBridge 161:aa5281ff4a02 776 */
AnnaBridge 161:aa5281ff4a02 777
AnnaBridge 161:aa5281ff4a02 778 /*!
AnnaBridge 161:aa5281ff4a02 779 * @brief Initializes the FLEXSPI handle which is used in transactional functions.
AnnaBridge 161:aa5281ff4a02 780 *
AnnaBridge 161:aa5281ff4a02 781 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 782 * @param handle pointer to flexspi_handle_t structure to store the transfer state.
AnnaBridge 161:aa5281ff4a02 783 * @param callback pointer to user callback function.
AnnaBridge 161:aa5281ff4a02 784 * @param userData user parameter passed to the callback function.
AnnaBridge 161:aa5281ff4a02 785 */
AnnaBridge 161:aa5281ff4a02 786 void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
AnnaBridge 161:aa5281ff4a02 787 flexspi_handle_t *handle,
AnnaBridge 161:aa5281ff4a02 788 flexspi_transfer_callback_t callback,
AnnaBridge 161:aa5281ff4a02 789 void *userData);
AnnaBridge 161:aa5281ff4a02 790
AnnaBridge 161:aa5281ff4a02 791 /*!
AnnaBridge 161:aa5281ff4a02 792 * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus.
AnnaBridge 161:aa5281ff4a02 793 *
AnnaBridge 161:aa5281ff4a02 794 * @note Calling the API returns immediately after transfer initiates. The user needs
AnnaBridge 161:aa5281ff4a02 795 * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether
AnnaBridge 161:aa5281ff4a02 796 * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer
AnnaBridge 161:aa5281ff4a02 797 * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or
AnnaBridge 161:aa5281ff4a02 798 * FLEXSPI could not read data properly.
AnnaBridge 161:aa5281ff4a02 799 *
AnnaBridge 161:aa5281ff4a02 800 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 801 * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
AnnaBridge 161:aa5281ff4a02 802 * @param xfer pointer to flexspi_transfer_t structure.
AnnaBridge 161:aa5281ff4a02 803 * @retval kStatus_Success Successfully start the data transmission.
AnnaBridge 161:aa5281ff4a02 804 * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished.
AnnaBridge 161:aa5281ff4a02 805 */
AnnaBridge 161:aa5281ff4a02 806 status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer);
AnnaBridge 161:aa5281ff4a02 807
AnnaBridge 161:aa5281ff4a02 808 /*!
AnnaBridge 161:aa5281ff4a02 809 * @brief Gets the master transfer status during a interrupt non-blocking transfer.
AnnaBridge 161:aa5281ff4a02 810 *
AnnaBridge 161:aa5281ff4a02 811 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 812 * @param handle pointer to flexspi_handle_t structure which stores the transfer state.
AnnaBridge 161:aa5281ff4a02 813 * @param count Number of bytes transferred so far by the non-blocking transaction.
AnnaBridge 161:aa5281ff4a02 814 * @retval kStatus_InvalidArgument count is Invalid.
AnnaBridge 161:aa5281ff4a02 815 * @retval kStatus_Success Successfully return the count.
AnnaBridge 161:aa5281ff4a02 816 */
AnnaBridge 161:aa5281ff4a02 817 status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count);
AnnaBridge 161:aa5281ff4a02 818
AnnaBridge 161:aa5281ff4a02 819 /*!
AnnaBridge 161:aa5281ff4a02 820 * @brief Aborts an interrupt non-blocking transfer early.
AnnaBridge 161:aa5281ff4a02 821 *
AnnaBridge 161:aa5281ff4a02 822 * @note This API can be called at any time when an interrupt non-blocking transfer initiates
AnnaBridge 161:aa5281ff4a02 823 * to abort the transfer early.
AnnaBridge 161:aa5281ff4a02 824 *
AnnaBridge 161:aa5281ff4a02 825 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 826 * @param handle pointer to flexspi_handle_t structure which stores the transfer state
AnnaBridge 161:aa5281ff4a02 827 */
AnnaBridge 161:aa5281ff4a02 828 void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle);
AnnaBridge 161:aa5281ff4a02 829
AnnaBridge 161:aa5281ff4a02 830 /*!
AnnaBridge 161:aa5281ff4a02 831 * @brief Master interrupt handler.
AnnaBridge 161:aa5281ff4a02 832 *
AnnaBridge 161:aa5281ff4a02 833 * @param base FLEXSPI peripheral base address.
AnnaBridge 161:aa5281ff4a02 834 * @param handle pointer to flexspi_handle_t structure.
AnnaBridge 161:aa5281ff4a02 835 */
AnnaBridge 161:aa5281ff4a02 836 void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
AnnaBridge 161:aa5281ff4a02 837 /*! @} */
AnnaBridge 161:aa5281ff4a02 838
AnnaBridge 161:aa5281ff4a02 839 #if defined(__cplusplus)
AnnaBridge 161:aa5281ff4a02 840 }
AnnaBridge 161:aa5281ff4a02 841 #endif /*_cplusplus. */
AnnaBridge 161:aa5281ff4a02 842 /*@}*/
AnnaBridge 161:aa5281ff4a02 843
AnnaBridge 161:aa5281ff4a02 844 #endif /* __FSL_FLEXSPI_H_ */