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TARGET_MIMXRT1050_EVK/TOOLCHAIN_IAR/fsl_cache.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 161:aa5281ff4a02 | 1 | /* |
| AnnaBridge | 170:e95d10626187 | 2 | * The Clear BSD License |
| AnnaBridge | 161:aa5281ff4a02 | 3 | * Copyright (c) 2016, Freescale Semiconductor, Inc. |
| AnnaBridge | 161:aa5281ff4a02 | 4 | * Copyright 2016-2017 NXP |
| AnnaBridge | 170:e95d10626187 | 5 | * All rights reserved. |
| AnnaBridge | 170:e95d10626187 | 6 | * |
| AnnaBridge | 161:aa5281ff4a02 | 7 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 170:e95d10626187 | 8 | * are permitted (subject to the limitations in the disclaimer below) provided |
| AnnaBridge | 170:e95d10626187 | 9 | * that the following conditions are met: |
| AnnaBridge | 161:aa5281ff4a02 | 10 | * |
| AnnaBridge | 161:aa5281ff4a02 | 11 | * o Redistributions of source code must retain the above copyright notice, this list |
| AnnaBridge | 161:aa5281ff4a02 | 12 | * of conditions and the following disclaimer. |
| AnnaBridge | 161:aa5281ff4a02 | 13 | * |
| AnnaBridge | 161:aa5281ff4a02 | 14 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| AnnaBridge | 161:aa5281ff4a02 | 15 | * list of conditions and the following disclaimer in the documentation and/or |
| AnnaBridge | 161:aa5281ff4a02 | 16 | * other materials provided with the distribution. |
| AnnaBridge | 161:aa5281ff4a02 | 17 | * |
| AnnaBridge | 161:aa5281ff4a02 | 18 | * o Neither the name of the copyright holder nor the names of its |
| AnnaBridge | 161:aa5281ff4a02 | 19 | * contributors may be used to endorse or promote products derived from this |
| AnnaBridge | 161:aa5281ff4a02 | 20 | * software without specific prior written permission. |
| AnnaBridge | 161:aa5281ff4a02 | 21 | * |
| AnnaBridge | 170:e95d10626187 | 22 | * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. |
| AnnaBridge | 161:aa5281ff4a02 | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| AnnaBridge | 161:aa5281ff4a02 | 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| AnnaBridge | 161:aa5281ff4a02 | 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 161:aa5281ff4a02 | 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| AnnaBridge | 161:aa5281ff4a02 | 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 161:aa5281ff4a02 | 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| AnnaBridge | 161:aa5281ff4a02 | 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| AnnaBridge | 161:aa5281ff4a02 | 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| AnnaBridge | 161:aa5281ff4a02 | 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| AnnaBridge | 161:aa5281ff4a02 | 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 161:aa5281ff4a02 | 33 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 34 | #ifndef _FSL_CACHE_H_ |
| AnnaBridge | 161:aa5281ff4a02 | 35 | #define _FSL_CACHE_H_ |
| AnnaBridge | 161:aa5281ff4a02 | 36 | |
| AnnaBridge | 161:aa5281ff4a02 | 37 | #include "fsl_common.h" |
| AnnaBridge | 161:aa5281ff4a02 | 38 | |
| AnnaBridge | 161:aa5281ff4a02 | 39 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 40 | * @addtogroup cache |
| AnnaBridge | 161:aa5281ff4a02 | 41 | * @{ |
| AnnaBridge | 161:aa5281ff4a02 | 42 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 43 | |
| AnnaBridge | 161:aa5281ff4a02 | 44 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 45 | * Definitions |
| AnnaBridge | 161:aa5281ff4a02 | 46 | ******************************************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 47 | |
| AnnaBridge | 161:aa5281ff4a02 | 48 | /*! @name Driver version */ |
| AnnaBridge | 161:aa5281ff4a02 | 49 | /*@{*/ |
| AnnaBridge | 161:aa5281ff4a02 | 50 | /*! @brief cache driver version 2.0.1. */ |
| AnnaBridge | 161:aa5281ff4a02 | 51 | #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) |
| AnnaBridge | 161:aa5281ff4a02 | 52 | /*@}*/ |
| AnnaBridge | 161:aa5281ff4a02 | 53 | |
| AnnaBridge | 170:e95d10626187 | 54 | #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT |
| AnnaBridge | 161:aa5281ff4a02 | 55 | #ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT |
| AnnaBridge | 161:aa5281ff4a02 | 56 | #define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 |
| AnnaBridge | 161:aa5281ff4a02 | 57 | #endif |
| AnnaBridge | 170:e95d10626187 | 58 | #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ |
| AnnaBridge | 161:aa5281ff4a02 | 59 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 60 | * Definitions |
| AnnaBridge | 161:aa5281ff4a02 | 61 | ******************************************************************************/ |
| AnnaBridge | 170:e95d10626187 | 62 | #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT |
| AnnaBridge | 161:aa5281ff4a02 | 63 | |
| AnnaBridge | 161:aa5281ff4a02 | 64 | /*! @brief Number of level 2 cache controller ways. */ |
| AnnaBridge | 161:aa5281ff4a02 | 65 | typedef enum _l2cache_way_num |
| AnnaBridge | 161:aa5281ff4a02 | 66 | { |
| AnnaBridge | 161:aa5281ff4a02 | 67 | kL2CACHE_8ways = 0, /*!< 8 ways. */ |
| AnnaBridge | 161:aa5281ff4a02 | 68 | #if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY |
| AnnaBridge | 161:aa5281ff4a02 | 69 | kL2CACHE_16ways /*!< 16 ways. */ |
| AnnaBridge | 161:aa5281ff4a02 | 70 | #endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ |
| AnnaBridge | 161:aa5281ff4a02 | 71 | } l2cache_way_num_t; |
| AnnaBridge | 161:aa5281ff4a02 | 72 | |
| AnnaBridge | 161:aa5281ff4a02 | 73 | /*! @brief Level 2 cache controller way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 74 | typedef enum _l2cache_way_size |
| AnnaBridge | 161:aa5281ff4a02 | 75 | { |
| AnnaBridge | 161:aa5281ff4a02 | 76 | kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 77 | kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 78 | kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 79 | kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 80 | kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 81 | kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ |
| AnnaBridge | 161:aa5281ff4a02 | 82 | } l2cache_way_size; |
| AnnaBridge | 161:aa5281ff4a02 | 83 | |
| AnnaBridge | 161:aa5281ff4a02 | 84 | /*! @brief Level 2 cache controller replacement policy. */ |
| AnnaBridge | 161:aa5281ff4a02 | 85 | typedef enum _l2cache_replacement |
| AnnaBridge | 161:aa5281ff4a02 | 86 | { |
| AnnaBridge | 161:aa5281ff4a02 | 87 | kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ |
| AnnaBridge | 161:aa5281ff4a02 | 88 | kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ |
| AnnaBridge | 161:aa5281ff4a02 | 89 | } l2cache_replacement_t; |
| AnnaBridge | 161:aa5281ff4a02 | 90 | |
| AnnaBridge | 161:aa5281ff4a02 | 91 | /*! @brief Level 2 cache controller force write allocate options. */ |
| AnnaBridge | 161:aa5281ff4a02 | 92 | typedef enum _l2cache_writealloc |
| AnnaBridge | 161:aa5281ff4a02 | 93 | { |
| AnnaBridge | 161:aa5281ff4a02 | 94 | kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ |
| AnnaBridge | 161:aa5281ff4a02 | 95 | kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ |
| AnnaBridge | 161:aa5281ff4a02 | 96 | kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ |
| AnnaBridge | 161:aa5281ff4a02 | 97 | } l2cache_writealloc_t; |
| AnnaBridge | 161:aa5281ff4a02 | 98 | |
| AnnaBridge | 161:aa5281ff4a02 | 99 | /*! @brief Level 2 cache controller tag/data ram latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 100 | typedef enum _l2cache_latency |
| AnnaBridge | 161:aa5281ff4a02 | 101 | { |
| AnnaBridge | 161:aa5281ff4a02 | 102 | kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 103 | kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 104 | kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 105 | kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 106 | kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 107 | kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 108 | kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 109 | kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 110 | } l2cache_latency_t; |
| AnnaBridge | 161:aa5281ff4a02 | 111 | |
| AnnaBridge | 161:aa5281ff4a02 | 112 | /*! @brief Level 2 cache controller tag/data ram latency configure structure. */ |
| AnnaBridge | 161:aa5281ff4a02 | 113 | typedef struct _l2cache_latency_config |
| AnnaBridge | 161:aa5281ff4a02 | 114 | { |
| AnnaBridge | 161:aa5281ff4a02 | 115 | l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 116 | l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 117 | l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 118 | l2cache_latency_t dataWriteLate; /*!< Data write latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 119 | l2cache_latency_t dataReadLate; /*!< Data Read latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 120 | l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ |
| AnnaBridge | 161:aa5281ff4a02 | 121 | } L2cache_latency_config_t; |
| AnnaBridge | 161:aa5281ff4a02 | 122 | |
| AnnaBridge | 161:aa5281ff4a02 | 123 | /*! @brief Level 2 cache controller configure structure. */ |
| AnnaBridge | 161:aa5281ff4a02 | 124 | typedef struct _l2cache_config |
| AnnaBridge | 161:aa5281ff4a02 | 125 | { |
| AnnaBridge | 161:aa5281ff4a02 | 126 | /* ------------------------ l2 cachec basic settings ---------------------------- */ |
| AnnaBridge | 161:aa5281ff4a02 | 127 | l2cache_way_num_t wayNum; /*!< The number of ways. */ |
| AnnaBridge | 161:aa5281ff4a02 | 128 | l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ |
| AnnaBridge | 161:aa5281ff4a02 | 129 | l2cache_replacement_t repacePolicy;/*!< Replacemnet policy. */ |
| AnnaBridge | 161:aa5281ff4a02 | 130 | /* ------------------------ tag/data ram latency settings ----------------------- */ |
| AnnaBridge | 161:aa5281ff4a02 | 131 | L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ |
| AnnaBridge | 161:aa5281ff4a02 | 132 | /* ------------------------ Prefetch enable settings ---------------------------- */ |
| AnnaBridge | 161:aa5281ff4a02 | 133 | bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ |
| AnnaBridge | 161:aa5281ff4a02 | 134 | bool dataPrefetchEnable; /*!< Data prefetch enable. */ |
| AnnaBridge | 161:aa5281ff4a02 | 135 | /* ------------------------ Non-secure access settings -------------------------- */ |
| AnnaBridge | 161:aa5281ff4a02 | 136 | bool nsLockdownEnable; /*!< None-secure lockdown enable. */ |
| AnnaBridge | 161:aa5281ff4a02 | 137 | /* ------------------------ other settings -------------------------------------- */ |
| AnnaBridge | 161:aa5281ff4a02 | 138 | l2cache_writealloc_t writeAlloc;/*!< Write allcoate force option. */ |
| AnnaBridge | 161:aa5281ff4a02 | 139 | } l2cache_config_t; |
| AnnaBridge | 170:e95d10626187 | 140 | #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ |
| AnnaBridge | 161:aa5281ff4a02 | 141 | /******************************************************************************* |
| AnnaBridge | 161:aa5281ff4a02 | 142 | * API |
| AnnaBridge | 161:aa5281ff4a02 | 143 | ******************************************************************************/ |
| AnnaBridge | 161:aa5281ff4a02 | 144 | |
| AnnaBridge | 161:aa5281ff4a02 | 145 | #if defined(__cplusplus) |
| AnnaBridge | 161:aa5281ff4a02 | 146 | extern "C" { |
| AnnaBridge | 161:aa5281ff4a02 | 147 | #endif |
| AnnaBridge | 161:aa5281ff4a02 | 148 | |
| AnnaBridge | 161:aa5281ff4a02 | 149 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 150 | * @name Control for cortex-m7 L1 cache |
| AnnaBridge | 161:aa5281ff4a02 | 151 | *@{ |
| AnnaBridge | 161:aa5281ff4a02 | 152 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 153 | |
| AnnaBridge | 161:aa5281ff4a02 | 154 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 155 | * @brief Enables cortex-m7 L1 instruction cache. |
| AnnaBridge | 161:aa5281ff4a02 | 156 | * |
| AnnaBridge | 161:aa5281ff4a02 | 157 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 158 | static inline void L1CACHE_EnableICache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 159 | { |
| AnnaBridge | 161:aa5281ff4a02 | 160 | SCB_EnableICache(); |
| AnnaBridge | 161:aa5281ff4a02 | 161 | } |
| AnnaBridge | 161:aa5281ff4a02 | 162 | |
| AnnaBridge | 161:aa5281ff4a02 | 163 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 164 | * @brief Disables cortex-m7 L1 instruction cache. |
| AnnaBridge | 161:aa5281ff4a02 | 165 | * |
| AnnaBridge | 161:aa5281ff4a02 | 166 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 167 | static inline void L1CACHE_DisableICache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 168 | { |
| AnnaBridge | 161:aa5281ff4a02 | 169 | SCB_DisableICache(); |
| AnnaBridge | 161:aa5281ff4a02 | 170 | } |
| AnnaBridge | 161:aa5281ff4a02 | 171 | |
| AnnaBridge | 161:aa5281ff4a02 | 172 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 173 | * @brief Invalidate cortex-m7 L1 instruction cache. |
| AnnaBridge | 161:aa5281ff4a02 | 174 | * |
| AnnaBridge | 161:aa5281ff4a02 | 175 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 176 | static inline void L1CACHE_InvalidateICache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 177 | { |
| AnnaBridge | 161:aa5281ff4a02 | 178 | SCB_InvalidateICache(); |
| AnnaBridge | 161:aa5281ff4a02 | 179 | } |
| AnnaBridge | 161:aa5281ff4a02 | 180 | |
| AnnaBridge | 161:aa5281ff4a02 | 181 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 182 | * @brief Invalidate cortex-m7 L1 instruction cache by range. |
| AnnaBridge | 161:aa5281ff4a02 | 183 | * |
| AnnaBridge | 161:aa5281ff4a02 | 184 | * @param address The start address of the memory to be invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 185 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 186 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 187 | * The startAddr here will be forced to align to L1 I-cache line size if |
| AnnaBridge | 161:aa5281ff4a02 | 188 | * startAddr is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 189 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 190 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 191 | void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 192 | |
| AnnaBridge | 161:aa5281ff4a02 | 193 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 194 | * @brief Enables cortex-m7 L1 data cache. |
| AnnaBridge | 161:aa5281ff4a02 | 195 | * |
| AnnaBridge | 161:aa5281ff4a02 | 196 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 197 | static inline void L1CACHE_EnableDCache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 198 | { |
| AnnaBridge | 161:aa5281ff4a02 | 199 | SCB_EnableDCache(); |
| AnnaBridge | 161:aa5281ff4a02 | 200 | } |
| AnnaBridge | 161:aa5281ff4a02 | 201 | |
| AnnaBridge | 161:aa5281ff4a02 | 202 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 203 | * @brief Disables cortex-m7 L1 data cache. |
| AnnaBridge | 161:aa5281ff4a02 | 204 | * |
| AnnaBridge | 161:aa5281ff4a02 | 205 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 206 | static inline void L1CACHE_DisableDCache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 207 | { |
| AnnaBridge | 161:aa5281ff4a02 | 208 | SCB_DisableDCache(); |
| AnnaBridge | 161:aa5281ff4a02 | 209 | } |
| AnnaBridge | 161:aa5281ff4a02 | 210 | |
| AnnaBridge | 161:aa5281ff4a02 | 211 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 212 | * @brief Invalidates cortex-m7 L1 data cache. |
| AnnaBridge | 161:aa5281ff4a02 | 213 | * |
| AnnaBridge | 161:aa5281ff4a02 | 214 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 215 | static inline void L1CACHE_InvalidateDCache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 216 | { |
| AnnaBridge | 161:aa5281ff4a02 | 217 | SCB_InvalidateDCache(); |
| AnnaBridge | 161:aa5281ff4a02 | 218 | } |
| AnnaBridge | 161:aa5281ff4a02 | 219 | |
| AnnaBridge | 161:aa5281ff4a02 | 220 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 221 | * @brief Cleans cortex-m7 L1 data cache. |
| AnnaBridge | 161:aa5281ff4a02 | 222 | * |
| AnnaBridge | 161:aa5281ff4a02 | 223 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 224 | static inline void L1CACHE_CleanDCache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 225 | { |
| AnnaBridge | 161:aa5281ff4a02 | 226 | SCB_CleanDCache(); |
| AnnaBridge | 161:aa5281ff4a02 | 227 | } |
| AnnaBridge | 161:aa5281ff4a02 | 228 | |
| AnnaBridge | 161:aa5281ff4a02 | 229 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 230 | * @brief Cleans and Invalidates cortex-m7 L1 data cache. |
| AnnaBridge | 161:aa5281ff4a02 | 231 | * |
| AnnaBridge | 161:aa5281ff4a02 | 232 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 233 | static inline void L1CACHE_CleanInvalidateDCache(void) |
| AnnaBridge | 161:aa5281ff4a02 | 234 | { |
| AnnaBridge | 161:aa5281ff4a02 | 235 | SCB_CleanInvalidateDCache(); |
| AnnaBridge | 161:aa5281ff4a02 | 236 | } |
| AnnaBridge | 161:aa5281ff4a02 | 237 | |
| AnnaBridge | 161:aa5281ff4a02 | 238 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 239 | * @brief Invalidates cortex-m7 L1 data cache by range. |
| AnnaBridge | 161:aa5281ff4a02 | 240 | * |
| AnnaBridge | 161:aa5281ff4a02 | 241 | * @param address The start address of the memory to be invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 242 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 243 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 244 | * The startAddr here will be forced to align to L1 D-cache line size if |
| AnnaBridge | 161:aa5281ff4a02 | 245 | * startAddr is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 246 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 247 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 248 | static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) |
| AnnaBridge | 161:aa5281ff4a02 | 249 | { |
| AnnaBridge | 161:aa5281ff4a02 | 250 | uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); |
| AnnaBridge | 161:aa5281ff4a02 | 251 | uint32_t size = size_byte + address - startAddr; |
| AnnaBridge | 161:aa5281ff4a02 | 252 | |
| AnnaBridge | 161:aa5281ff4a02 | 253 | SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size); |
| AnnaBridge | 161:aa5281ff4a02 | 254 | } |
| AnnaBridge | 161:aa5281ff4a02 | 255 | |
| AnnaBridge | 161:aa5281ff4a02 | 256 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 257 | * @brief Cleans cortex-m7 L1 data cache by range. |
| AnnaBridge | 161:aa5281ff4a02 | 258 | * |
| AnnaBridge | 161:aa5281ff4a02 | 259 | * @param address The start address of the memory to be cleaned. |
| AnnaBridge | 161:aa5281ff4a02 | 260 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 261 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 262 | * The startAddr here will be forced to align to L1 D-cache line size if |
| AnnaBridge | 161:aa5281ff4a02 | 263 | * startAddr is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 264 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 265 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 266 | static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) |
| AnnaBridge | 161:aa5281ff4a02 | 267 | { |
| AnnaBridge | 161:aa5281ff4a02 | 268 | uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); |
| AnnaBridge | 161:aa5281ff4a02 | 269 | uint32_t size = size_byte + address - startAddr; |
| AnnaBridge | 161:aa5281ff4a02 | 270 | |
| AnnaBridge | 161:aa5281ff4a02 | 271 | SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size); |
| AnnaBridge | 161:aa5281ff4a02 | 272 | } |
| AnnaBridge | 161:aa5281ff4a02 | 273 | |
| AnnaBridge | 161:aa5281ff4a02 | 274 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 275 | * @brief Cleans and Invalidates cortex-m7 L1 data cache by range. |
| AnnaBridge | 161:aa5281ff4a02 | 276 | * |
| AnnaBridge | 161:aa5281ff4a02 | 277 | * @param address The start address of the memory to be clean and invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 278 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 279 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 280 | * The startAddr here will be forced to align to L1 D-cache line size if |
| AnnaBridge | 161:aa5281ff4a02 | 281 | * startAddr is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 282 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 283 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 284 | static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) |
| AnnaBridge | 161:aa5281ff4a02 | 285 | { |
| AnnaBridge | 161:aa5281ff4a02 | 286 | uint32_t startAddr = address & (uint32_t)~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); |
| AnnaBridge | 161:aa5281ff4a02 | 287 | uint32_t size = size_byte + address - startAddr; |
| AnnaBridge | 161:aa5281ff4a02 | 288 | |
| AnnaBridge | 161:aa5281ff4a02 | 289 | SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size); |
| AnnaBridge | 161:aa5281ff4a02 | 290 | } |
| AnnaBridge | 161:aa5281ff4a02 | 291 | /*@}*/ |
| AnnaBridge | 161:aa5281ff4a02 | 292 | |
| AnnaBridge | 170:e95d10626187 | 293 | #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT |
| AnnaBridge | 161:aa5281ff4a02 | 294 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 295 | * @name Control for L2 pl310 cache |
| AnnaBridge | 161:aa5281ff4a02 | 296 | *@{ |
| AnnaBridge | 161:aa5281ff4a02 | 297 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 298 | |
| AnnaBridge | 161:aa5281ff4a02 | 299 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 300 | * @brief Initializes the level 2 cache controller module. |
| AnnaBridge | 161:aa5281ff4a02 | 301 | * |
| AnnaBridge | 161:aa5281ff4a02 | 302 | * @param config Pointer to configuration structure. See "l2cache_config_t". |
| AnnaBridge | 161:aa5281ff4a02 | 303 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 304 | void L2CACHE_Init(l2cache_config_t *config); |
| AnnaBridge | 161:aa5281ff4a02 | 305 | |
| AnnaBridge | 161:aa5281ff4a02 | 306 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 307 | * @brief Gets an available default settings for the cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 308 | * |
| AnnaBridge | 161:aa5281ff4a02 | 309 | * This function initializes the cache controller configuration structure with default settings. |
| AnnaBridge | 161:aa5281ff4a02 | 310 | * The default values are: |
| AnnaBridge | 161:aa5281ff4a02 | 311 | * @code |
| AnnaBridge | 161:aa5281ff4a02 | 312 | * config->waysNum = kL2CACHE_8ways; |
| AnnaBridge | 161:aa5281ff4a02 | 313 | * config->waySize = kL2CACHE_32KbSize; |
| AnnaBridge | 161:aa5281ff4a02 | 314 | * config->repacePolicy = kL2CACHE_Roundrobin; |
| AnnaBridge | 161:aa5281ff4a02 | 315 | * config->lateConfig = NULL; |
| AnnaBridge | 161:aa5281ff4a02 | 316 | * config->istrPrefetchEnable = false; |
| AnnaBridge | 161:aa5281ff4a02 | 317 | * config->dataPrefetchEnable = false; |
| AnnaBridge | 161:aa5281ff4a02 | 318 | * config->nsLockdownEnable = false; |
| AnnaBridge | 161:aa5281ff4a02 | 319 | * config->writeAlloc = kL2CACHE_UseAwcache; |
| AnnaBridge | 161:aa5281ff4a02 | 320 | * @endcode |
| AnnaBridge | 161:aa5281ff4a02 | 321 | * @param config Pointer to the configuration structure. |
| AnnaBridge | 161:aa5281ff4a02 | 322 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 323 | void L2CACHE_GetDefaultConfig(l2cache_config_t *config); |
| AnnaBridge | 161:aa5281ff4a02 | 324 | |
| AnnaBridge | 161:aa5281ff4a02 | 325 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 326 | * @brief Enables the level 2 cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 327 | * This function enables the cache controller. Must be written using a secure access. |
| AnnaBridge | 161:aa5281ff4a02 | 328 | * If write with a Non-secure access will cause a DECERR response. |
| AnnaBridge | 161:aa5281ff4a02 | 329 | * |
| AnnaBridge | 161:aa5281ff4a02 | 330 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 331 | void L2CACHE_Enable(void); |
| AnnaBridge | 161:aa5281ff4a02 | 332 | |
| AnnaBridge | 161:aa5281ff4a02 | 333 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 334 | * @brief Disables the level 2 cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 335 | * This function disables the cache controller. Must be written using a secure access. |
| AnnaBridge | 161:aa5281ff4a02 | 336 | * If write with a Non-secure access will cause a DECERR response. |
| AnnaBridge | 161:aa5281ff4a02 | 337 | * |
| AnnaBridge | 161:aa5281ff4a02 | 338 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 339 | void L2CACHE_Disable(void); |
| AnnaBridge | 161:aa5281ff4a02 | 340 | |
| AnnaBridge | 161:aa5281ff4a02 | 341 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 342 | * @brief Invalidates the Level 2 cache. |
| AnnaBridge | 161:aa5281ff4a02 | 343 | * This function invalidates all entries in cache. |
| AnnaBridge | 161:aa5281ff4a02 | 344 | * |
| AnnaBridge | 161:aa5281ff4a02 | 345 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 346 | void L2CACHE_Invalidate(void); |
| AnnaBridge | 161:aa5281ff4a02 | 347 | |
| AnnaBridge | 161:aa5281ff4a02 | 348 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 349 | * @brief Invalidates the Level 2 cache lines in the range of two physical addresses. |
| AnnaBridge | 161:aa5281ff4a02 | 350 | * This function invalidates all cache lines between two physical addresses. |
| AnnaBridge | 161:aa5281ff4a02 | 351 | * |
| AnnaBridge | 161:aa5281ff4a02 | 352 | * @param address The start address of the memory to be invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 353 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 354 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 355 | * The startAddr here will be forced to align to L2 line size if startAddr |
| AnnaBridge | 161:aa5281ff4a02 | 356 | * is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 357 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 358 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 359 | void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 360 | |
| AnnaBridge | 161:aa5281ff4a02 | 361 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 362 | * @brief Cleans the level 2 cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 363 | * This function cleans all entries in the level 2 cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 364 | * |
| AnnaBridge | 161:aa5281ff4a02 | 365 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 366 | void L2CACHE_Clean(void); |
| AnnaBridge | 161:aa5281ff4a02 | 367 | |
| AnnaBridge | 161:aa5281ff4a02 | 368 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 369 | * @brief Cleans the Level 2 cache lines in the range of two physical addresses. |
| AnnaBridge | 161:aa5281ff4a02 | 370 | * This function cleans all cache lines between two physical addresses. |
| AnnaBridge | 161:aa5281ff4a02 | 371 | * |
| AnnaBridge | 161:aa5281ff4a02 | 372 | * @param address The start address of the memory to be cleaned. |
| AnnaBridge | 161:aa5281ff4a02 | 373 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 374 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 375 | * The startAddr here will be forced to align to L2 line size if startAddr |
| AnnaBridge | 161:aa5281ff4a02 | 376 | * is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 377 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 378 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 379 | void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 380 | |
| AnnaBridge | 161:aa5281ff4a02 | 381 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 382 | * @brief Cleans and invalidates the level 2 cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 383 | * This function cleans and invalidates all entries in the level 2 cache controller. |
| AnnaBridge | 161:aa5281ff4a02 | 384 | * |
| AnnaBridge | 161:aa5281ff4a02 | 385 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 386 | void L2CACHE_CleanInvalidate(void); |
| AnnaBridge | 161:aa5281ff4a02 | 387 | |
| AnnaBridge | 161:aa5281ff4a02 | 388 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 389 | * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. |
| AnnaBridge | 161:aa5281ff4a02 | 390 | * This function cleans and invalidates all cache lines between two physical addresses. |
| AnnaBridge | 161:aa5281ff4a02 | 391 | * |
| AnnaBridge | 161:aa5281ff4a02 | 392 | * @param address The start address of the memory to be cleaned and invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 393 | * @param size_byte The memory size. |
| AnnaBridge | 161:aa5281ff4a02 | 394 | * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 395 | * The startAddr here will be forced to align to L2 line size if startAddr |
| AnnaBridge | 161:aa5281ff4a02 | 396 | * is not aligned. For the size_byte, application should make sure the |
| AnnaBridge | 161:aa5281ff4a02 | 397 | * alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 398 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 399 | void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 400 | |
| AnnaBridge | 161:aa5281ff4a02 | 401 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 402 | * @brief Enables or disables to lock down the data and instruction by way. |
| AnnaBridge | 161:aa5281ff4a02 | 403 | * This function locks down the cached instruction/data by way and prevent the adresses from |
| AnnaBridge | 161:aa5281ff4a02 | 404 | * being allocated and prevent dara from being evicted out of the level 2 cache. |
| AnnaBridge | 161:aa5281ff4a02 | 405 | * But the normal cache maintenance operations that invalidate, clean or clean |
| AnnaBridge | 161:aa5281ff4a02 | 406 | * and validate cache contents affect the locked-down cache lines as normal. |
| AnnaBridge | 161:aa5281ff4a02 | 407 | * |
| AnnaBridge | 161:aa5281ff4a02 | 408 | * @param masterId The master id, range from 0 ~ 7. |
| AnnaBridge | 161:aa5281ff4a02 | 409 | * @param mask The ways to be enabled or disabled to lockdown. |
| AnnaBridge | 161:aa5281ff4a02 | 410 | * each bit in value is related to each way of the cache. for example: |
| AnnaBridge | 161:aa5281ff4a02 | 411 | * value: bit 0 ------ way 0. |
| AnnaBridge | 161:aa5281ff4a02 | 412 | * value: bit 1 ------ way 1. |
| AnnaBridge | 161:aa5281ff4a02 | 413 | * -------------------------- |
| AnnaBridge | 161:aa5281ff4a02 | 414 | * value: bit 15 ------ way 15. |
| AnnaBridge | 161:aa5281ff4a02 | 415 | * Note: please make sure the value setting is align with your supported ways. |
| AnnaBridge | 161:aa5281ff4a02 | 416 | * @param enable True enable the lockdown, false to disable the lockdown. |
| AnnaBridge | 161:aa5281ff4a02 | 417 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 418 | void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); |
| AnnaBridge | 161:aa5281ff4a02 | 419 | |
| AnnaBridge | 161:aa5281ff4a02 | 420 | /*@}*/ |
| AnnaBridge | 170:e95d10626187 | 421 | #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ |
| AnnaBridge | 161:aa5281ff4a02 | 422 | |
| AnnaBridge | 161:aa5281ff4a02 | 423 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 424 | * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) |
| AnnaBridge | 161:aa5281ff4a02 | 425 | * Mainly used for many drivers for easy cache operation. |
| AnnaBridge | 161:aa5281ff4a02 | 426 | *@{ |
| AnnaBridge | 161:aa5281ff4a02 | 427 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 428 | |
| AnnaBridge | 161:aa5281ff4a02 | 429 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 430 | * @brief Invalidates all instruction caches by range. |
| AnnaBridge | 161:aa5281ff4a02 | 431 | * |
| AnnaBridge | 161:aa5281ff4a02 | 432 | * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. |
| AnnaBridge | 161:aa5281ff4a02 | 433 | * |
| AnnaBridge | 161:aa5281ff4a02 | 434 | * @param address The physical address. |
| AnnaBridge | 161:aa5281ff4a02 | 435 | * @param size_byte size of the memory to be invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 436 | * @note address and size should be aligned to cache line size |
| AnnaBridge | 161:aa5281ff4a02 | 437 | * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced |
| AnnaBridge | 161:aa5281ff4a02 | 438 | * to align to the cache line size if startAddr is not aligned. For the size_byte, application should |
| AnnaBridge | 161:aa5281ff4a02 | 439 | * make sure the alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 440 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 441 | void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 442 | |
| AnnaBridge | 161:aa5281ff4a02 | 443 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 444 | * @brief Invalidates all data caches by range. |
| AnnaBridge | 161:aa5281ff4a02 | 445 | * |
| AnnaBridge | 161:aa5281ff4a02 | 446 | * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. |
| AnnaBridge | 161:aa5281ff4a02 | 447 | * |
| AnnaBridge | 161:aa5281ff4a02 | 448 | * @param address The physical address. |
| AnnaBridge | 161:aa5281ff4a02 | 449 | * @param size_byte size of the memory to be invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 450 | * @note address and size should be aligned to cache line size |
| AnnaBridge | 161:aa5281ff4a02 | 451 | * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced |
| AnnaBridge | 161:aa5281ff4a02 | 452 | * to align to the cache line size if startAddr is not aligned. For the size_byte, application should |
| AnnaBridge | 161:aa5281ff4a02 | 453 | * make sure the alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 454 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 455 | void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 456 | |
| AnnaBridge | 161:aa5281ff4a02 | 457 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 458 | * @brief Cleans all data caches by range. |
| AnnaBridge | 161:aa5281ff4a02 | 459 | * |
| AnnaBridge | 161:aa5281ff4a02 | 460 | * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. |
| AnnaBridge | 161:aa5281ff4a02 | 461 | * |
| AnnaBridge | 161:aa5281ff4a02 | 462 | * @param address The physical address. |
| AnnaBridge | 161:aa5281ff4a02 | 463 | * @param size_byte size of the memory to be cleaned. |
| AnnaBridge | 161:aa5281ff4a02 | 464 | * @note address and size should be aligned to cache line size |
| AnnaBridge | 161:aa5281ff4a02 | 465 | * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced |
| AnnaBridge | 161:aa5281ff4a02 | 466 | * to align to the cache line size if startAddr is not aligned. For the size_byte, application should |
| AnnaBridge | 161:aa5281ff4a02 | 467 | * make sure the alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 468 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 469 | void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 470 | |
| AnnaBridge | 161:aa5281ff4a02 | 471 | /*! |
| AnnaBridge | 161:aa5281ff4a02 | 472 | * @brief Cleans and Invalidates all data caches by range. |
| AnnaBridge | 161:aa5281ff4a02 | 473 | * |
| AnnaBridge | 161:aa5281ff4a02 | 474 | * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. |
| AnnaBridge | 161:aa5281ff4a02 | 475 | * |
| AnnaBridge | 161:aa5281ff4a02 | 476 | * @param address The physical address. |
| AnnaBridge | 161:aa5281ff4a02 | 477 | * @param size_byte size of the memory to be cleaned and invalidated. |
| AnnaBridge | 161:aa5281ff4a02 | 478 | * @note address and size should be aligned to cache line size |
| AnnaBridge | 161:aa5281ff4a02 | 479 | * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced |
| AnnaBridge | 161:aa5281ff4a02 | 480 | * to align to the cache line size if startAddr is not aligned. For the size_byte, application should |
| AnnaBridge | 161:aa5281ff4a02 | 481 | * make sure the alignment or make sure the right operation order if the size_byte is not aligned. |
| AnnaBridge | 161:aa5281ff4a02 | 482 | */ |
| AnnaBridge | 161:aa5281ff4a02 | 483 | void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); |
| AnnaBridge | 161:aa5281ff4a02 | 484 | |
| AnnaBridge | 161:aa5281ff4a02 | 485 | /*@}*/ |
| AnnaBridge | 161:aa5281ff4a02 | 486 | |
| AnnaBridge | 161:aa5281ff4a02 | 487 | |
| AnnaBridge | 161:aa5281ff4a02 | 488 | #if defined(__cplusplus) |
| AnnaBridge | 161:aa5281ff4a02 | 489 | } |
| AnnaBridge | 161:aa5281ff4a02 | 490 | #endif |
| AnnaBridge | 161:aa5281ff4a02 | 491 | |
| AnnaBridge | 161:aa5281ff4a02 | 492 | /*! @}*/ |
| AnnaBridge | 161:aa5281ff4a02 | 493 | |
| AnnaBridge | 161:aa5281ff4a02 | 494 | #endif /* _FSL_CACHE_H_*/ |
