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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/spix_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Fields, Field Positions, Masks and Values for the SPIX Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 19:45:43 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24673 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_SPIX_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_SPIX_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /// @cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 /// @endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* **** Definitions **** */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @ingroup spix
AnnaBridge 171:3a7713b1edbc 75 * @defgroup spix_registers Registers
AnnaBridge 171:3a7713b1edbc 76 * @brief Registers, Bit Masks and Bit Positions for the SPIX Peripheral Module.
AnnaBridge 171:3a7713b1edbc 77 */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 81 * Structure type to access the SPIX Registers.
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t master_cfg; /**< SPIX_MASTER_CFG Register. */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t fetch_ctrl; /**< SPIX_FETCH_CTRL Register. */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t mode_ctrl; /**< SPIX_MODE_CTRL Register. */
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t mode_data; /**< SPIX_MODE_DATA Register. */
AnnaBridge 171:3a7713b1edbc 88 __IO uint32_t sck_fb_ctrl; /**< SPIX_SCK_FB_CTRL Register. */
AnnaBridge 171:3a7713b1edbc 89 } mxc_spix_regs_t;
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 93 * @defgroup SPIX_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 94 * @brief SPIX Peripheral Register Offsets from the SPIX Base Peripheral Address, #MXC_BASE_SPIX.
AnnaBridge 171:3a7713b1edbc 95 * @{
AnnaBridge 171:3a7713b1edbc 96 */
AnnaBridge 171:3a7713b1edbc 97 #define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x000</tt> */
AnnaBridge 171:3a7713b1edbc 98 #define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x004</tt> */
AnnaBridge 171:3a7713b1edbc 99 #define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x008</tt> */
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x00C</tt> */
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from #MXC_BASE_SPIX: <tt>\b 0x010</tt> */
AnnaBridge 171:3a7713b1edbc 102 /**@} end of SPIX_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /**
AnnaBridge 171:3a7713b1edbc 105 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 106 * @defgroup SPIX_Master_Cfg_Register SPIX_MASTER_CFG Register Fields
AnnaBridge 171:3a7713b1edbc 107 * @brief Register Fields and Shifted Field Masks for the SPIX_MASTER_CFG Register.
AnnaBridge 171:3a7713b1edbc 108 * @{
AnnaBridge 171:3a7713b1edbc 109 */
AnnaBridge 171:3a7713b1edbc 110 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0 /**< SPI_MODE Field Position */
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SPI_MODE Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2 /**< SS_ACT_LO Field Position */
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< SS_ACT_LO Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3 /**< ALT_TIMING_EN Field Position */
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< ALT_TIMING_EN Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4 /**< SLAVE_SEL Field Position */
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8 /**< SCK_LO_CLK Field Position */
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12 /**< SCK_HI_CLK Field Position */
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Field Position */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Field Position */
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20 /**< ALT_SCK_LO_CLK Field Position */
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS)) /**< ALT_SCK_LO_CLK Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24 /**< ALT_SCK_HI_CLK Field Position */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS)) /**< ALT_SCK_HI_CLK Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28 /**< SDIO_SAMPLE_POINT Field Position */
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 132 /**@}*/
AnnaBridge 171:3a7713b1edbc 133 /**
AnnaBridge 171:3a7713b1edbc 134 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 135 * @defgroup SPIX_Fetch_Ctrl_Register SPIX_FETCH_CTRL Register Fields
AnnaBridge 171:3a7713b1edbc 136 * @brief Register Fields and Shifted Masks for the SPIX_FETCH_CTRL Register.
AnnaBridge 171:3a7713b1edbc 137 * @{
AnnaBridge 171:3a7713b1edbc 138 */
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0 /**< CMD_VALUE Field Position */
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS)) /**< CMD_VALUE Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8 /**< CMD_WIDTH Field Position */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< CMD_WIDTH Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< ADDR_WIDTH Field Position */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< ADDR_WIDTH Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12 /**< DATA_WIDTH Field Position */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FOUR_BYTE_ADDR Field Position */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FOUR_BYTE_ADDRField Mask */
AnnaBridge 171:3a7713b1edbc 149 /**@}*/
AnnaBridge 171:3a7713b1edbc 150 /**
AnnaBridge 171:3a7713b1edbc 151 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 152 * @defgroup SPIX_Mode_Ctrl_Register SPIX_MODE_CTRL Register Fields
AnnaBridge 171:3a7713b1edbc 153 * @brief Register Fields and Shifted Masks for the SPIX_MODE_CTRL Register.
AnnaBridge 171:3a7713b1edbc 154 * @{
AnnaBridge 171:3a7713b1edbc 155 */
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0 /**< MODE_CLOCKS Field Position */
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS)) /**< MODE_CLOCKS Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8 /**< NO_CMD_MODE Field Position */
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)) /**< NO_CMD_MODE Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 160 /**@}*/
AnnaBridge 171:3a7713b1edbc 161 /**
AnnaBridge 171:3a7713b1edbc 162 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 163 * @defgroup SPIX_Mode_Data_Register SPIX_MODE_DATA Register Fields
AnnaBridge 171:3a7713b1edbc 164 * @brief Register Fields and Shifted Masks for the SPIX_MODE_DATA Register.
AnnaBridge 171:3a7713b1edbc 165 * @{
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0 /**< MODE_DATA_BITS Field Position */
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS)) /**< MODE_DATA_BITS Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16 /**< MODE_DATA_OE Field Position */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS)) /**< MODE_DATA_OE Shifted Field Mask */
AnnaBridge 171:3a7713b1edbc 171 /**@}*/
AnnaBridge 171:3a7713b1edbc 172 /**
AnnaBridge 171:3a7713b1edbc 173 * @ingroup spix_registers
AnnaBridge 171:3a7713b1edbc 174 * @defgroup SPIX_SCK_Fb_Ctrl_Register SPIX_SCK_FB_CTRL Register Fields
AnnaBridge 171:3a7713b1edbc 175 * @brief Register Fields and Shifted Masks for the SPIX_SCK_FB_CTRL Register.
AnnaBridge 171:3a7713b1edbc 176 * @{
AnnaBridge 171:3a7713b1edbc 177 */
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0 /**< Field Position */
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< Field Mask */
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1 /**< Field Position */
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS)) /**< Field Mask */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 #if(MXC_SPIX_REV == 0)
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4 /**< Field Position */
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS)) /**< Field Mask */
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 /**< Field Position */
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) /**< Field Mask */
AnnaBridge 171:3a7713b1edbc 188 #endif
AnnaBridge 171:3a7713b1edbc 189 /**@}*/
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 /**
AnnaBridge 171:3a7713b1edbc 193 * @ingroup SPIX_Master_Cfg_Register
AnnaBridge 171:3a7713b1edbc 194 * @defgroup SPIX_Master_Cfg_SCK SCK Sampling Mode Field
AnnaBridge 171:3a7713b1edbc 195 * @brief Field values and shifted field values for setting the SPIX SCK Sampling Mode.
AnnaBridge 171:3a7713b1edbc 196 * @{
AnnaBridge 171:3a7713b1edbc 197 */
AnnaBridge 171:3a7713b1edbc 198 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) /**< Field value for setting the sampling of the SCK on the rising edge. */
AnnaBridge 171:3a7713b1edbc 199 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) /**< Field value for setting the sampling of the SCK on the falling edge. */
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on rising edge Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 202 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) /**< SCK sampling on falling edge Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 203 /**@}*/
AnnaBridge 171:3a7713b1edbc 204 /**
AnnaBridge 171:3a7713b1edbc 205 * @ingroup SPIX_Master_Cfg_Register
AnnaBridge 171:3a7713b1edbc 206 * @defgroup SPIX_Master_Cfg_SS Slave Select Polarity Field
AnnaBridge 171:3a7713b1edbc 207 * @brief Field values and shifted field values for setting the SPIX Slave Select Active High/Low Field.
AnnaBridge 171:3a7713b1edbc 208 * @{
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) /**< Slave Select Active High Field selection value. */
AnnaBridge 171:3a7713b1edbc 211 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL)) /**< Slave Select Active Low Field selection value. */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active High Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) /**< Slave Select Active Low Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 215 /**@}*/
AnnaBridge 171:3a7713b1edbc 216 /**
AnnaBridge 171:3a7713b1edbc 217 * @ingroup SPIX_Master_Cfg_Register
AnnaBridge 171:3a7713b1edbc 218 * @defgroup SPIX_Master_Cfg_Alt Alternate Timing
AnnaBridge 171:3a7713b1edbc 219 * @brief Field values and shifted field values for setting the SPIX Alternate Timing Field.
AnnaBridge 171:3a7713b1edbc 220 * @{
AnnaBridge 171:3a7713b1edbc 221 */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL)) /**< Alternate Timing Disabled (Default) Field selection value. */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL)) /**< Alternate Timing Enabled As Needed Field selection value. */
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Disabled Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 226 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) /**< Alternate Timing Enabled As Needed Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 227 /**@}*/
AnnaBridge 171:3a7713b1edbc 228 /**
AnnaBridge 171:3a7713b1edbc 229 * @ingroup SPIX_Master_Cfg_Register
AnnaBridge 171:3a7713b1edbc 230 * @defgroup SPIX_Master_Cfg_Act Active Delay Settings
AnnaBridge 171:3a7713b1edbc 231 * @brief Field values and shifted field values for setting the SPIX Activity Delay, the number of SPIX clocks between slave selection assert and active SPI clocking.
AnnaBridge 171:3a7713b1edbc 232 * @{
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Activity Delay Off Field selection value. */
AnnaBridge 171:3a7713b1edbc 235 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */
AnnaBridge 171:3a7713b1edbc 236 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */
AnnaBridge 171:3a7713b1edbc 237 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< Activity Delay Off Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 243 /**@}*/
AnnaBridge 171:3a7713b1edbc 244 /**
AnnaBridge 171:3a7713b1edbc 245 * @ingroup SPIX_Master_Cfg_Register
AnnaBridge 171:3a7713b1edbc 246 * @defgroup SPIX_Master_Cfg_Inact Inactive Delay Settings
AnnaBridge 171:3a7713b1edbc 247 * @brief Field values and shifted field values for setting the SPIX Inactivity Delay, the number of SPIX clocks between the active SPI Clock and the Slave Select Deassertion.
AnnaBridge 171:3a7713b1edbc 248 * @{
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) /**< Inactivity Delay Off Field selection value. */
AnnaBridge 171:3a7713b1edbc 251 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) /**< 2 Mode Clocks Field selection value. */
AnnaBridge 171:3a7713b1edbc 252 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) /**< 4 Mode Clocks Field selection value. */
AnnaBridge 171:3a7713b1edbc 253 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) /**< 8 Mode Clocks Field selection value. */
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< Inactivity Delay Off Shifted Value. */
AnnaBridge 171:3a7713b1edbc 256 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 2 Mode Clocks Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 257 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 4 Mode Clocks Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 258 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) /**< 8 Mode Clocks Field Shifted Value. */
AnnaBridge 171:3a7713b1edbc 259 /**@}*/
AnnaBridge 171:3a7713b1edbc 260 /**
AnnaBridge 171:3a7713b1edbc 261 * @ingroup SPIX_Fetch_Ctrl_Register
AnnaBridge 171:3a7713b1edbc 262 * @defgroup SPIX_Fetch_ctrl_cmd_width Address Width Values and Shifted Values
AnnaBridge 171:3a7713b1edbc 263 * @brief Field values and shifted field values for selecting the SPIX Command Fetch Width
AnnaBridge 171:3a7713b1edbc 264 * @{
AnnaBridge 171:3a7713b1edbc 265 */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 command width field value. */
AnnaBridge 171:3a7713b1edbc 267 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual command field value. */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad command field value. */
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x1 command width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 271 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x2 Dual command width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 272 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) /**< x4 Quad command width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 273 /**@}*/
AnnaBridge 171:3a7713b1edbc 274 /**
AnnaBridge 171:3a7713b1edbc 275 * @ingroup SPIX_Fetch_Ctrl_Register
AnnaBridge 171:3a7713b1edbc 276 * @defgroup SPIX_Fetch_ctrl_addr_width Address Width Values and Shifted Values
AnnaBridge 171:3a7713b1edbc 277 * @brief Field values and shifted field values for selecting the SPIX Address Fetch Width
AnnaBridge 171:3a7713b1edbc 278 * @{
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< x1 addr width field value. */
AnnaBridge 171:3a7713b1edbc 281 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< x2 Dual addr field value. */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< x4 Quad addr field value. */
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x1 addr width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 285 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x2 Dual addr width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) /**< x4 Quad addr width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 287 /**@}*/
AnnaBridge 171:3a7713b1edbc 288 /**
AnnaBridge 171:3a7713b1edbc 289 * @ingroup SPIX_Fetch_Ctrl_Register
AnnaBridge 171:3a7713b1edbc 290 * @defgroup SPIX_Fetch_ctrl_data_width Data Width Values and Shifted Values
AnnaBridge 171:3a7713b1edbc 291 * @brief Field values and shifted field values for selecting the SPIX Data Fetch Width
AnnaBridge 171:3a7713b1edbc 292 * @{
AnnaBridge 171:3a7713b1edbc 293 */
AnnaBridge 171:3a7713b1edbc 294 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) /**< Value to select x1 data width fetch for SPIX Field selection value. */
AnnaBridge 171:3a7713b1edbc 295 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) /**< Value to select x2 Dual Mode data width fetch for SPIX Field selection value. */
AnnaBridge 171:3a7713b1edbc 296 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) /**< Value to select x4 Quad Mode data width fetch for SPIX Field selection value. */
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x1 data width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 299 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x2 Dual data width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 300 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) /**< x4 Quad data width fetch shifted value. */
AnnaBridge 171:3a7713b1edbc 301 /**@}*/
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 305 }
AnnaBridge 171:3a7713b1edbc 306 #endif
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 #endif /* _MXC_SPIX_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 309