mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/spim_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 19:42:44 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24672 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_SPIM_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_SPIM_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 ///@cond
AnnaBridge 171:3a7713b1edbc 55 /*
AnnaBridge 171:3a7713b1edbc 56 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 57 */
AnnaBridge 171:3a7713b1edbc 58 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 59 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 60 #endif
AnnaBridge 171:3a7713b1edbc 61 #ifndef __I
AnnaBridge 171:3a7713b1edbc 62 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 63 #endif
AnnaBridge 171:3a7713b1edbc 64 #ifndef __O
AnnaBridge 171:3a7713b1edbc 65 #define __O volatile
AnnaBridge 171:3a7713b1edbc 66 #endif
AnnaBridge 171:3a7713b1edbc 67 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 68 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 69 #endif
AnnaBridge 171:3a7713b1edbc 70 ///@endcond
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @ingroup spim
AnnaBridge 171:3a7713b1edbc 75 * @defgroup spim_registers Registers
AnnaBridge 171:3a7713b1edbc 76 * @brief Registers, Bit Masks and Bit Positions for the SPIM Peripheral Module.
AnnaBridge 171:3a7713b1edbc 77 * @{
AnnaBridge 171:3a7713b1edbc 78 */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /**
AnnaBridge 171:3a7713b1edbc 81 * Structure type to access the SPIM Peripheral Module Registers
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t mstr_cfg; /**< <tt>\b 0x0000:</tt> SPIM_MSTR_CFG Register - SPI Master Configuration Register */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t ss_sr_polarity; /**< <tt>\b 0x0004:</tt> SPIM_SS_SR_POLARITY Register - SPI Master Polarity Control for SS and SR Signals */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t gen_ctrl; /**< <tt>\b 0x0008:</tt> SPIM_GEN_CTRL Register - SPI Master General Control Register */
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t fifo_ctrl; /**< <tt>\b 0x000C:</tt> SPIM_FIFO_CTRL Register - SPI Master FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 88 __IO uint32_t spcl_ctrl; /**< <tt>\b 0x0010:</tt> SPIM_SPCL_CTRL Register - SPI Master Special Mode Controls */
AnnaBridge 171:3a7713b1edbc 89 __IO uint32_t intfl; /**< <tt>\b 0x0014:</tt> SPIM_INTFL Register - SPI Master Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 90 __IO uint32_t inten; /**< <tt>\b 0x0018:</tt> SPIM_INTEN Register - SPI Master Interrupt Enable/Disable Settings */
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t simple_headers; /**< <tt>\b 0x001C:</tt> SPIM_SIMPLE_HEADERS Register - SPI Master Simple Mode Transaction Headers */
AnnaBridge 171:3a7713b1edbc 92 } mxc_spim_regs_t;
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /**
AnnaBridge 171:3a7713b1edbc 96 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 97 * @defgroup spim_fifos SPIM TX and RX FIFOs
AnnaBridge 171:3a7713b1edbc 98 * @brief TX and RX FIFO access for reads and writes using 8-bit, 16-bit and 32-bit data types.
AnnaBridge 171:3a7713b1edbc 99 * @{
AnnaBridge 171:3a7713b1edbc 100 */
AnnaBridge 171:3a7713b1edbc 101 /**
AnnaBridge 171:3a7713b1edbc 102 * Structure type for the SPIM Transmit and Receive FIFOs.
AnnaBridge 171:3a7713b1edbc 103 */
AnnaBridge 171:3a7713b1edbc 104 typedef struct {
AnnaBridge 171:3a7713b1edbc 105 union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */
AnnaBridge 171:3a7713b1edbc 106 __IO uint8_t trans_8[2048]; /**< 8-bit access to Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 107 __IO uint16_t trans_16[1024]; /**< 16-bit access to Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 108 __IO uint32_t trans_32[512]; /**< 32-bit access to Transmit FIFO */
AnnaBridge 171:3a7713b1edbc 109 };
AnnaBridge 171:3a7713b1edbc 110 union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */
AnnaBridge 171:3a7713b1edbc 111 __IO uint8_t rslts_8[2048]; /**< 8-bit access to Receive FIFO */
AnnaBridge 171:3a7713b1edbc 112 __IO uint16_t rslts_16[1024]; /**< 16-bit access to Receive FIFO */
AnnaBridge 171:3a7713b1edbc 113 __IO uint32_t rslts_32[512]; /**< 32-bit access to Receive FIFO */
AnnaBridge 171:3a7713b1edbc 114 };
AnnaBridge 171:3a7713b1edbc 115 } mxc_spim_fifo_regs_t;
AnnaBridge 171:3a7713b1edbc 116 /**@} end of group spim_fifos */
AnnaBridge 171:3a7713b1edbc 117 /**@} end of group spim_registers */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 /*
AnnaBridge 171:3a7713b1edbc 121 Register offsets for module SPIM.
AnnaBridge 171:3a7713b1edbc 122 */
AnnaBridge 171:3a7713b1edbc 123 /**
AnnaBridge 171:3a7713b1edbc 124 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 125 * @defgroup SPIM_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 126 * @brief SPI Master Register Offsets from the SPIM[n] Base Peripheral Address, where \c n \c = SPIM Instance Number.
AnnaBridge 171:3a7713b1edbc 127 * @{
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0000</tt>*/
AnnaBridge 171:3a7713b1edbc 130 #define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0004</tt>*/
AnnaBridge 171:3a7713b1edbc 131 #define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0008</tt>*/
AnnaBridge 171:3a7713b1edbc 132 #define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x000C</tt>*/
AnnaBridge 171:3a7713b1edbc 133 #define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0010</tt>*/
AnnaBridge 171:3a7713b1edbc 134 #define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0014</tt>*/
AnnaBridge 171:3a7713b1edbc 135 #define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x0018</tt>*/
AnnaBridge 171:3a7713b1edbc 136 #define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL) /**< Offset from SPIM[n] Base Address: <tt>\b 0x001C</tt>*/
AnnaBridge 171:3a7713b1edbc 137 /**@} end of group SPIM_Register_Offsets*/
AnnaBridge 171:3a7713b1edbc 138 /**
AnnaBridge 171:3a7713b1edbc 139 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 140 * @defgroup SPIM_FIFO_Offsets FIFO Offsets
AnnaBridge 171:3a7713b1edbc 141 * @brief SPI Master FIFO Offsets from the SPIM[n] Base FIFO Address, where \c n \c = SPIM Instance Number.
AnnaBridge 171:3a7713b1edbc 142 * @{
AnnaBridge 171:3a7713b1edbc 143 */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from SPIM[n] Base FIFO Address: <tt>\b 0x0000</tt>*/
AnnaBridge 171:3a7713b1edbc 145 #define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from SPIM[n] Base FIFO Address: <tt>\b 0x0800</tt>*/
AnnaBridge 171:3a7713b1edbc 146 /**@} end of group SPIM_FIFO_Offsets*/
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /*
AnnaBridge 171:3a7713b1edbc 149 Field positions and masks for module SPIM.
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151 /**
AnnaBridge 171:3a7713b1edbc 152 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 153 * @defgroup SPIM_MSTR_CFG_Register SPIM_MSTR_CFG
AnnaBridge 171:3a7713b1edbc 154 * @brief Field Positions and Bit Masks for the SPIM_MSTR_CFG register
AnnaBridge 171:3a7713b1edbc 155 * @{
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0 /**< SLAVE_SEL Position */
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS)) /**< SLAVE_SEL Mask */
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3 /**< THREE_WIRE_MODE Position */
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS)) /**< THREE_WIRE_MODE Mask */
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4 /**< SPI_MODE Position */
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS)) /**< SPI_MODE Mask */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6 /**< PAGE_SIZE Position */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)) /**< PAGE_SIZE Mask */
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8 /**< SCK_HI_CLK Position */
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS)) /**< SCK_HI_CLK Mask */
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12 /**< SCK_LO_CLK Position */
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS)) /**< SCK_LO_CLK Mask */
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16 /**< ACT_DELAY Position */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS)) /**< ACT_DELAY Mask */
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18 /**< INACT_DELAY Position */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS)) /**< INACT_DELAY Mask */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20 /**< SDIO_SAMPLE_POINT Position */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS)) /**< SDIO_SAMPLE_POINT Mask */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL) /**< PAGE_SIZE_4B Field Value */
AnnaBridge 171:3a7713b1edbc 177 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL) /**< PAGE_SIZE_8B Field Value */
AnnaBridge 171:3a7713b1edbc 178 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL) /**< PAGE_SIZE_16B Field Value */
AnnaBridge 171:3a7713b1edbc 179 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL) /**< PAGE_SIZE_32B Field Value */
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 #define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_4B Shifted Field Value */
AnnaBridge 171:3a7713b1edbc 182 #define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_8B Shifted Field Value */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_16B Shifted Field Value */
AnnaBridge 171:3a7713b1edbc 184 #define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS) /**< PAGE_SIZE_32B Shifted Field Value */
AnnaBridge 171:3a7713b1edbc 185 /**@} end of group SPIM_MSTR_CFG*/
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 188 * @defgroup SPIM_SS_SR_POLARITY_Register SPIM_SS_SR_POLARITY
AnnaBridge 171:3a7713b1edbc 189 * @brief Field Positions and Bit Masks for the SPIM_SS_SR_POLARITY register
AnnaBridge 171:3a7713b1edbc 190 * @{
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0 /**< SS_POLARITY Position */
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS)) /**< SS_POLARITY Mask */
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8 /**< FC_POLARITY Position */
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS)) /**< FC_POLARITY Mask */
AnnaBridge 171:3a7713b1edbc 196 /**@} end of group SPIM_SS_SR_POLARITY*/
AnnaBridge 171:3a7713b1edbc 197 /**
AnnaBridge 171:3a7713b1edbc 198 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 199 * @defgroup SPIM_GEN_CTRL_Register SPIM_GEN_CTRL
AnnaBridge 171:3a7713b1edbc 200 * @brief Field Positions and Bit Masks for the SPIM_GEN_CTRL register
AnnaBridge 171:3a7713b1edbc 201 * @{
AnnaBridge 171:3a7713b1edbc 202 */
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0 /**< SPI_MSTR_EN Position */
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS)) /**< SPI_MSTR_EN Mask */
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3 /**< BIT_BANG_MODE Position */
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS)) /**< BIT_BANG_MODE Mask */
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4 /**< BB_SS_IN_OUT Position */
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS)) /**< BB_SS_IN_OUT Mask */
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5 /**< BB_SR_IN Position */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS)) /**< BB_SR_IN Mask */
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6 /**< BB_SCK_IN_OUT Position */
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS)) /**< BB_SCK_IN_OUT Mask */
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8 /**< BB_SDIO_IN osition */
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS)) /**< BB_SDIO_IN Mask */
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12 /**< BB_SDIO_OUT Position */
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS)) /**< BB_SDIO_OUT Mask */
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16 /**< BB_SDIO_DR_EN Position */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS)) /**< BB_SDIO_DR_EN Mask */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20 /**< SIMPLE_MODE Position */
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS)) /**< SIMPLE_MODE Mask */
AnnaBridge 171:3a7713b1edbc 225 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21 /**< START_RX_ONLY Position */
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS)) /**< START_RX_ONLY Mask */
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22 /**< DEASSERT_ACT_SS Position */
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS)) /**< DEASSERT_ACT_SS Mask */
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24 /**< ENABLE_SCK_FB_MOD Position */
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS)) /**< ENABLE_SCK_FB_MOD Mask */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25 /**< INVERT_SCK_FB_CLK Position */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS)) /**< INVERT_SCK_FB_CLK Mask */
AnnaBridge 171:3a7713b1edbc 233 /**@} end of group SPIM_GEN_CTRL*/
AnnaBridge 171:3a7713b1edbc 234 /**
AnnaBridge 171:3a7713b1edbc 235 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 236 * @defgroup SPIM_FIFO_CTRL_Register SPIM_FIFO_CTRL
AnnaBridge 171:3a7713b1edbc 237 * @brief Field Positions and Bit Masks for the SPIM_FIFO_CTRL register
AnnaBridge 171:3a7713b1edbc 238 * @{
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8 /**< TX_FIFO_USED Position */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< RX_FIFO_AF_LVL Position */
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24 /**< RX_FIFO_USED Position */
AnnaBridge 171:3a7713b1edbc 247 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
AnnaBridge 171:3a7713b1edbc 248 /**@} end of group SPIM_FIFO_CTRL*/
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 251 * @defgroup SPIM_SPCL_CTRL_Register SPIM_SPCL_CTRL
AnnaBridge 171:3a7713b1edbc 252 * @brief Field Positions and Bit Masks for the SPIM_SPCL_CTRL register
AnnaBridge 171:3a7713b1edbc 253 * @{
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0 /**< SS_SAMPLE_MODE Position */
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS)) /**< SS_SAMPLE_MODE Mask */
AnnaBridge 171:3a7713b1edbc 257 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1 /**< MISO_FC_EN Position */
AnnaBridge 171:3a7713b1edbc 258 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS)) /**< MISO_FC_EN Mask */
AnnaBridge 171:3a7713b1edbc 259 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4 /**< SS_SA_SDIO_OUT Position */
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS)) /**< SS_SA_SDIO_OUT Mask */
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8 /**< SS_SA_SDIO_DR_EN Position */
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS)) /**< SS_SA_SDIO_DR_EN Mask */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 #if (MXC_SPIM_REV == 0)
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16 /**< SPECIAL_MODE_3_EN Position */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS)) /**< SPECIAL_MODE_3_EN Mask */
AnnaBridge 171:3a7713b1edbc 267 #else
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12 /**< RX_FIFO_MARGIN Position */
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS)) /**< RX_FIFO_MARGIN Mask */
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16 /**< SCK_FB_DELAY Position */
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS)) /**< SCK_FB_DELAY Mask */
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20 /**< SPARE_RESERVED Position */
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS)) /**< SPARE_RESERVED Mask */
AnnaBridge 171:3a7713b1edbc 274 #endif
AnnaBridge 171:3a7713b1edbc 275 /**@} end of group SPIM_SPCL_CTRL*/
AnnaBridge 171:3a7713b1edbc 276 /**
AnnaBridge 171:3a7713b1edbc 277 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 278 * @defgroup SPIM_INTFL_Register SPIM_INTFL
AnnaBridge 171:3a7713b1edbc 279 * @brief Field Positions and Bit Masks for the SPIM_INTFL register
AnnaBridge 171:3a7713b1edbc 280 * @{
AnnaBridge 171:3a7713b1edbc 281 */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_SPIM_INTFL_TX_STALLED_POS 0 /**< TX_STALLED Position */
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS)) /**< TX_STALLED Mask */
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_SPIM_INTFL_RX_STALLED_POS 1 /**< RX_STALLED Position */
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS)) /**< RX_STALLED Mask */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_SPIM_INTFL_TX_READY_POS 2 /**< TX_READY Position */
AnnaBridge 171:3a7713b1edbc 287 #define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS)) /**< TX_READY Mask */
AnnaBridge 171:3a7713b1edbc 288 #define MXC_F_SPIM_INTFL_RX_DONE_POS 3 /**< RX_DONE Position */
AnnaBridge 171:3a7713b1edbc 289 #define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS)) /**< RX_DONE Mask */
AnnaBridge 171:3a7713b1edbc 290 #define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */
AnnaBridge 171:3a7713b1edbc 291 #define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
AnnaBridge 171:3a7713b1edbc 292 #define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */
AnnaBridge 171:3a7713b1edbc 293 #define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
AnnaBridge 171:3a7713b1edbc 294 /**@} end of group SPIM_INTFL*/
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 297 * @defgroup SPIM_INTEN_Register SPIM_INTEN
AnnaBridge 171:3a7713b1edbc 298 * @brief Field Positions and Bit Masks for the SPIM_INTEN register
AnnaBridge 171:3a7713b1edbc 299 * @{
AnnaBridge 171:3a7713b1edbc 300 */
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_SPIM_INTEN_TX_STALLED_POS 0 /**< TX_STALLED Position */
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS)) /**< TX_STALLED Mask */
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_SPIM_INTEN_RX_STALLED_POS 1 /**< RX_STALLED Position */
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS)) /**< RX_STALLED Mask */
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_SPIM_INTEN_TX_READY_POS 2 /**< TX_READY Position */
AnnaBridge 171:3a7713b1edbc 306 #define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS)) /**< TX_READY Mask */
AnnaBridge 171:3a7713b1edbc 307 #define MXC_F_SPIM_INTEN_RX_DONE_POS 3 /**< RX_DONE Position */
AnnaBridge 171:3a7713b1edbc 308 #define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS)) /**< RX_DONE Mask */
AnnaBridge 171:3a7713b1edbc 309 #define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4 /**< TX_FIFO_AE Position */
AnnaBridge 171:3a7713b1edbc 310 #define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
AnnaBridge 171:3a7713b1edbc 311 #define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5 /**< RX_FIFO_AF Position */
AnnaBridge 171:3a7713b1edbc 312 #define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
AnnaBridge 171:3a7713b1edbc 313 /**@} end of group SPIM_INTEN*/
AnnaBridge 171:3a7713b1edbc 314 /**
AnnaBridge 171:3a7713b1edbc 315 * @ingroup spim_registers
AnnaBridge 171:3a7713b1edbc 316 * @defgroup SPIM_SIMPLE_HEADERS_Register SPIM_SIMPLE_HEADERS
AnnaBridge 171:3a7713b1edbc 317 * @brief Field Positions and Bit Masks for the SPIM_SIMPLE_HEADERS register
AnnaBridge 171:3a7713b1edbc 318 * @{
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0 /**< TX_BIDIR_HEADER Position */
AnnaBridge 171:3a7713b1edbc 321 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS)) /**< TX_BIDIR_HEADER Mask */
AnnaBridge 171:3a7713b1edbc 322 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16 /**< RX_ONLY_HEADER Position */
AnnaBridge 171:3a7713b1edbc 323 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS)) /**< RX_ONLY_HEADER Mask */
AnnaBridge 171:3a7713b1edbc 324 /**@} end of group SPIM_SIMPLE_HEADERS*/
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 328 }
AnnaBridge 171:3a7713b1edbc 329 #endif
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 #endif /* _MXC_SPIM_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 332