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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/rtc_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the Real-Time Clock.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 */
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 19:28:26 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24670 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 **************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_RTC_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_RTC_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 47 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 50 extern "C" {
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /*
AnnaBridge 171:3a7713b1edbc 54 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56 /// @cond
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 /// @endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @ingroup rtc
AnnaBridge 171:3a7713b1edbc 73 * @defgroup rtc_registers RTC Registers
AnnaBridge 171:3a7713b1edbc 74 * @brief Registers, Bit Masks and Bit Positions
AnnaBridge 171:3a7713b1edbc 75 * @{
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /**
AnnaBridge 171:3a7713b1edbc 79 * Structure type for the Real-Time Clock module registers allowing direct 32-bit access to each register.
AnnaBridge 171:3a7713b1edbc 80 */
AnnaBridge 171:3a7713b1edbc 81 typedef struct {
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t ctrl; /**< <tt>\b 0x0000: </tt> RTC_CTRL Register - RTC Timer Control */
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t timer; /**< <tt>\b 0x0004: </tt> RTC_TIMER Register - RTC Timer Count Value */
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t comp[2]; /**< <tt>\b 0x0008-0x000C: </tt> RTC_COMP0/RTC_COMP1 Registers - RTC Time of Day Alarm [0..1] Compare Register */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t flags; /**< <tt>\b 0x0010: </tt> RTC_FLAGS Register - CPU Interrupt and RTC Domain Flags */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t snz_val; /**< <tt>\b 0x0014: </tt> RTC_SNZ_VAL Register - RTC Timer Alarm Snooze Value */
AnnaBridge 171:3a7713b1edbc 87 __IO uint32_t inten; /**< <tt>\b 0x0018: </tt> RTC_INTEN Register - Interrupt Enable Controls */
AnnaBridge 171:3a7713b1edbc 88 __IO uint32_t prescale; /**< <tt>\b 0x001C: </tt> RTC_PRESCALE Register - RTC Timer Prescale Setting */
AnnaBridge 171:3a7713b1edbc 89 __RO uint32_t rsv020; /**< <tt>\b 0x0020: </tt> RESERVED */
AnnaBridge 171:3a7713b1edbc 90 __IO uint32_t prescale_mask; /**< <tt>\b 0x0024: </tt> RTC_PRESCALE_MASK Register - RTC Timer Prescale Compare Mask */
AnnaBridge 171:3a7713b1edbc 91 __IO uint32_t trim_ctrl; /**< <tt>\b 0x0028: </tt> RTC_TRIM_CTRL Register - RTC Timer Trim Controls */
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t trim_value; /**< <tt>\b 0x002C: </tt> RTC_TRIM_VALUE Register - RTC Timer Trim Adjustment Interval */
AnnaBridge 171:3a7713b1edbc 93 } mxc_rtctmr_regs_t;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 /**
AnnaBridge 171:3a7713b1edbc 97 * Structure type for access to the RTC CFG hardware.
AnnaBridge 171:3a7713b1edbc 98 */
AnnaBridge 171:3a7713b1edbc 99 typedef struct {
AnnaBridge 171:3a7713b1edbc 100 __IO uint32_t nano_cntr; /**< <tt>\b 0x0000: </tt> - RTCCFG_NANO_CNTR - Nano Oscillator Counter Read Register */
AnnaBridge 171:3a7713b1edbc 101 __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> - RTCCFG_CLK_CTRL - RTC Clock Control Settings */
AnnaBridge 171:3a7713b1edbc 102 __RO uint32_t rsv008; /**< <tt>\b 0x0008: </tt> - RESERVED */
AnnaBridge 171:3a7713b1edbc 103 __IO uint32_t osc_ctrl; /**< <tt>\b 0x000C: </tt> - RTCCFG_OSC_CTRL - RTC Oscillator Control */
AnnaBridge 171:3a7713b1edbc 104 } mxc_rtccfg_regs_t;
AnnaBridge 171:3a7713b1edbc 105 /**@} end of group rtc_registers.*/
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /*
AnnaBridge 171:3a7713b1edbc 108 Register offsets for module RTC.
AnnaBridge 171:3a7713b1edbc 109 */
AnnaBridge 171:3a7713b1edbc 110 /**
AnnaBridge 171:3a7713b1edbc 111 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 112 * @defgroup RTC_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 113 * @brief Real-Time Clock Register Offsets from the RTC Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 114 * @{
AnnaBridge 171:3a7713b1edbc 115 */
AnnaBridge 171:3a7713b1edbc 116 #define MXC_R_RTCTMR_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 117 #define MXC_R_RTCTMR_OFFS_TIMER ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 118 #define MXC_R_RTCTMR_OFFS_COMP0 ((uint32_t)0x00000008UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 119 #define MXC_R_RTCTMR_OFFS_COMP1 ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_RTCTMR_OFFS_FLAGS ((uint32_t)0x00000010UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0010</tt> */
AnnaBridge 171:3a7713b1edbc 121 #define MXC_R_RTCTMR_OFFS_SNZ_VAL ((uint32_t)0x00000014UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0014</tt> */
AnnaBridge 171:3a7713b1edbc 122 #define MXC_R_RTCTMR_OFFS_INTEN ((uint32_t)0x00000018UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0018</tt> */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_R_RTCTMR_OFFS_PRESCALE ((uint32_t)0x0000001CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x001C</tt> */
AnnaBridge 171:3a7713b1edbc 124 #define MXC_R_RTCTMR_OFFS_PRESCALE_MASK ((uint32_t)0x00000024UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0024</tt> */
AnnaBridge 171:3a7713b1edbc 125 #define MXC_R_RTCTMR_OFFS_TRIM_CTRL ((uint32_t)0x00000028UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0028</tt> */
AnnaBridge 171:3a7713b1edbc 126 #define MXC_R_RTCTMR_OFFS_TRIM_VALUE ((uint32_t)0x0000002CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x002C</tt> */
AnnaBridge 171:3a7713b1edbc 127 /**@} end of group RTC_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 128 /**
AnnaBridge 171:3a7713b1edbc 129 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 130 * @defgroup RTCCFG_Register_Offsets RTCCFG Register Offsets
AnnaBridge 171:3a7713b1edbc 131 * @brief Real-Time Clock CFG Register Offsets from the RTCCFG Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 132 * @{
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134 #define MXC_R_RTCCFG_OFFS_NANO_CNTR ((uint32_t)0x00000000UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 135 #define MXC_R_RTCCFG_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 136 #define MXC_R_RTCCFG_OFFS_OSC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from the RTC Base Peripheral Address:<tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 137 /**@} end of group RTCCFG_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /*
AnnaBridge 171:3a7713b1edbc 140 Field positions and masks for module RTC.
AnnaBridge 171:3a7713b1edbc 141 */
AnnaBridge 171:3a7713b1edbc 142 /**
AnnaBridge 171:3a7713b1edbc 143 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 144 * @defgroup RTC_CTRL_Register RTC_CTRL
AnnaBridge 171:3a7713b1edbc 145 * @{
AnnaBridge 171:3a7713b1edbc 146 */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_RTC_CTRL_ENABLE_POS 0 /**< ENABLE Position */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_RTC_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS)) /**< ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_RTC_CTRL_CLEAR_POS 1 /**< CLEAR Position */
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_RTC_CTRL_CLEAR ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS)) /**< CLEAR Mask */
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_RTC_CTRL_PENDING_POS 2 /**< PENDING Position */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_RTC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS)) /**< PENDING Mask */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS 3 /**< USE_ASYNC_FLAGS Position */
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS)) /**< USE_ASYNC_FLAGS Mask */
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS 4 /**< AGGRESSIVE_RST Position */
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_RTC_CTRL_AGGRESSIVE_RST ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS)) /**< AGGRESSIVE_RST Mask */
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS 5 /**< AUTO_UPDATE_DISABLE Position */
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AUTO_UPDATE_DISABLE_POS)) /**< AUTO_UPDATE_DISABLE Mask */
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS 6 /**< SNOOZE_ENABLE Position */
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_RTC_CTRL_SNOOZE_ENABLE ((uint32_t)(0x00000003UL << MXC_F_RTC_CTRL_SNOOZE_ENABLE_POS)) /**< SNOOZE_ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS 16 /**< RTC_ENABLE_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_ENABLE_ACTIVE_POS)) /**< RTC_ENABLE_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS 17 /**< OSC_GOTO_LOW_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS)) /**< OSC_GOTO_LOW_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS 18 /**< OSC_FRCE_SM_EN_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS)) /**< OSC_FRCE_SM_EN_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS 19 /**< OSC_FRCE_ST_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS)) /**< OSC_FRCE_ST_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS 20 /**< RTC_SET_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_RTC_CTRL_RTC_SET_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_SET_ACTIVE_POS)) /**< RTC_SET_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS 21 /**< RTC_CLR_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_RTC_CTRL_RTC_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_RTC_CLR_ACTIVE_POS)) /**< RTC_CLR_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS 22 /**< ROLLOVER_CLR_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS)) /**< ROLLOVER_CLR_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS 23 /**< PRESCALE_CMPR0_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS)) /**< PRESCALE_CMPR0_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS 24 /**< PRESCALE_UPDATE_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS)) /**< PRESCALE_UPDATE_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS 25 /**< CMPR1_CLR_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS)) /**< CMPR1_CLR_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS 26 /**< CMPR0_CLR_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS)) /**< CMPR0_CLR_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS 27 /**< TRIM_ENABLE_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_ENABLE_ACTIVE_POS)) /**< TRIM_ENABLE_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS 28 /**< TRIM_SLOWER_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_SLOWER_ACTIVE_POS)) /**< TRIM_SLOWER_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS 29 /**< TRIM_CLR_ACTIVE Position */
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_TRIM_CLR_ACTIVE_POS)) /**< TRIM_CLR_ACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS 30 /**< ACTIVE_TRANS_0 Position */
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_RTC_CTRL_ACTIVE_TRANS_0 ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ACTIVE_TRANS_0_POS)) /**< ACTIVE_TRANS_0 Mask */
AnnaBridge 171:3a7713b1edbc 191 /**@} end of group RTC_CTRL*/
AnnaBridge 171:3a7713b1edbc 192 /**
AnnaBridge 171:3a7713b1edbc 193 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 194 * @defgroup RTC_FLAGS_Register RTC_FLAGS
AnnaBridge 171:3a7713b1edbc 195 * @{
AnnaBridge 171:3a7713b1edbc 196 */
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_RTC_FLAGS_COMP0_POS 0 /**< COMP0 Position */
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_RTC_FLAGS_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS)) /**< COMP0 Mask */
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_RTC_FLAGS_COMP1_POS 1 /**< COMP1 Position */
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_RTC_FLAGS_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS)) /**< COMP1 Mask */
AnnaBridge 171:3a7713b1edbc 201 #define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
AnnaBridge 171:3a7713b1edbc 202 #define MXC_F_RTC_FLAGS_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_RTC_FLAGS_OVERFLOW_POS 3 /**< OVERFLOW Position */
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_RTC_FLAGS_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS)) /**< OVERFLOW Mask */
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_RTC_FLAGS_TRIM_POS 4 /**< TRIM Position */
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_RTC_FLAGS_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS)) /**< TRIM Mask */
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_RTC_FLAGS_SNOOZE_POS 5 /**< SNOOZE Position */
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_RTC_FLAGS_SNOOZE ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_POS)) /**< SNOOZE Mask */
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS 8 /**< COMP0_FLAG_A Position */
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_RTC_FLAGS_COMP0_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS)) /**< COMP0_FLAG_A Mask */
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS 9 /**< COMP1_FLAG_A Position */
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_RTC_FLAGS_COMP1_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS)) /**< COMP1_FLAG_A Mask */
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS 10 /**< PRESCL_FLAG_A Position */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_RTC_FLAGS_PRESCL_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS)) /**< PRESCL_FLAG_A Mask */
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS 11 /**< OVERFLOW_FLAG_A Position */
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS)) /**< OVERFLOW_FLAG_A Mask */
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS 12 /**< TRIM_FLAG_A Position */
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_RTC_FLAGS_TRIM_FLAG_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS)) /**< TRIM_FLAG_A Mask */
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_RTC_FLAGS_SNOOZE_A_POS 28 /**< SNOOZE_A Position */
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_RTC_FLAGS_SNOOZE_A ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_A_POS)) /**< SNOOZE_A Mask */
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_RTC_FLAGS_SNOOZE_B_POS 29 /**< SNOOZE_B Position */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_RTC_FLAGS_SNOOZE_B ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_SNOOZE_B_POS)) /**< SNOOZE_B Mask */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS 31 /**< ASYNC_CLR_FLAGS Position */
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS)) /**< ASYNC_CLR_FLAGS Mask */
AnnaBridge 171:3a7713b1edbc 225 /**@} end of group RTC_FLAGS_Register */
AnnaBridge 171:3a7713b1edbc 226 /**
AnnaBridge 171:3a7713b1edbc 227 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 228 * @defgroup RTC_SNZ_VAL_Register RTC_SNZ_VAL.
AnnaBridge 171:3a7713b1edbc 229 * @{
AnnaBridge 171:3a7713b1edbc 230 */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_RTC_SNZ_VAL_VALUE_POS 0 /**< VALUE Position */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_RTC_SNZ_VAL_VALUE ((uint32_t)(0x000003FFUL << MXC_F_RTC_SNZ_VAL_VALUE_POS)) /**< VALUE Mask */
AnnaBridge 171:3a7713b1edbc 233 /**@} end of group RTC_SNZ_VAL_Register */
AnnaBridge 171:3a7713b1edbc 234 /**
AnnaBridge 171:3a7713b1edbc 235 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 236 * @defgroup RTC_INTEN_Register RTC_INTEN.
AnnaBridge 171:3a7713b1edbc 237 * @{
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239 #define MXC_F_RTC_INTEN_COMP0_POS 0 /**< COMP0 Position */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_RTC_INTEN_COMP0 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS)) /**< COMP0 Mask */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_RTC_INTEN_COMP1_POS 1 /**< COMP1 Position */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_RTC_INTEN_COMP1 ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS)) /**< COMP1 Mask */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_RTC_INTEN_PRESCALE_COMP_POS 2 /**< PRESCALE_COMP Position */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_RTC_INTEN_PRESCALE_COMP ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS)) /**< PRESCALE_COMP Mask */
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_RTC_INTEN_OVERFLOW_POS 3 /**< OVERFLOW Position */
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_RTC_INTEN_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS)) /**< OVERFLOW Mask */
AnnaBridge 171:3a7713b1edbc 247 #define MXC_F_RTC_INTEN_TRIM_POS 4 /**< TRIM Position */
AnnaBridge 171:3a7713b1edbc 248 #define MXC_F_RTC_INTEN_TRIM ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS)) /**< TRIM Mask */
AnnaBridge 171:3a7713b1edbc 249 /**@} end of group RTC_INTEN_Register */
AnnaBridge 171:3a7713b1edbc 250 /**
AnnaBridge 171:3a7713b1edbc 251 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 252 * @defgroup RTC_PRESCALE_Register RTC_PRESCALE.
AnnaBridge 171:3a7713b1edbc 253 * @{
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_RTC_PRESCALE_PRESCALE_POS 0 /**< PRESCALE Position */
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_RTC_PRESCALE_PRESCALE ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_PRESCALE_POS)) /**< PRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 257 /**@} end of group RTC_INTEN_Register */
AnnaBridge 171:3a7713b1edbc 258 /**
AnnaBridge 171:3a7713b1edbc 259 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 260 * @defgroup RTC_PRESCALE_MASK_Register RTC_PRESCALE_MASK.
AnnaBridge 171:3a7713b1edbc 261 * @{
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS 0 /**< PRESCALE_MASK Position */
AnnaBridge 171:3a7713b1edbc 264 #define MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_PRESCALE_MASK_POS)) /**< PRESCALE_MASK Mask */
AnnaBridge 171:3a7713b1edbc 265 /**@} end of group RTC_PRESCALE_MASK_Register */
AnnaBridge 171:3a7713b1edbc 266 /**
AnnaBridge 171:3a7713b1edbc 267 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 268 * @defgroup RTC_TRIM_CTRL_Register RTC_TRIM_CTRL.
AnnaBridge 171:3a7713b1edbc 269 * @{
AnnaBridge 171:3a7713b1edbc 270 */
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS 0 /**< TRIM_ENABLE_R Position */
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS)) /**< TRIM_ENABLE_R Mask */
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS 1 /**< TRIM_FASTER_OVR_R Position */
AnnaBridge 171:3a7713b1edbc 274 #define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS)) /**< TRIM_FASTER_OVR_R Mask */
AnnaBridge 171:3a7713b1edbc 275 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS 2 /**< TRIM_SLOWER_R Position */
AnnaBridge 171:3a7713b1edbc 276 #define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS)) /**< TRIM_SLOWER_R Mask */
AnnaBridge 171:3a7713b1edbc 277 /**@} end of group RTC_TRIM_CTRL_Register */
AnnaBridge 171:3a7713b1edbc 278 /**
AnnaBridge 171:3a7713b1edbc 279 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 280 * @defgroup RTC_TRIM_VALUE_Register RTC_TRIM_VALUE.
AnnaBridge 171:3a7713b1edbc 281 * @{
AnnaBridge 171:3a7713b1edbc 282 */
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS 0 /**< TRIM_VALUE Position */
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS)) /**< TRIM_VALUE Mask */
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS 18 /**< TRIM_SLOWER_CONTROL Position */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_SLOWER_CONTROL_POS)) /**< TRIM_SLOWER_CONTROL Mask */
AnnaBridge 171:3a7713b1edbc 287 /**@} end of group RTC_TRIM_VALUE_Register */
AnnaBridge 171:3a7713b1edbc 288 /**
AnnaBridge 171:3a7713b1edbc 289 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 290 * @defgroup RTC_NANO_CNTR_Register RTC_NANO_CNTR.
AnnaBridge 171:3a7713b1edbc 291 * @{
AnnaBridge 171:3a7713b1edbc 292 */
AnnaBridge 171:3a7713b1edbc 293 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS 0 /**< NANORING_COUNTER Position */
AnnaBridge 171:3a7713b1edbc 294 #define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS)) /**< NANORING_COUNTER Mask */
AnnaBridge 171:3a7713b1edbc 295 /**@} end of group RTC_NANO_CNTR_Register */
AnnaBridge 171:3a7713b1edbc 296 /**
AnnaBridge 171:3a7713b1edbc 297 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 298 * @defgroup RTC_CLK_CTRL_Register RTC_CLK_CTRL.
AnnaBridge 171:3a7713b1edbc 299 * @{
AnnaBridge 171:3a7713b1edbc 300 */
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS 0 /**< OSC1_EN Position */
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_RTC_CLK_CTRL_OSC1_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS)) /**< OSC1_EN Mask */
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS 1 /**< OSC2_EN Position */
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_RTC_CLK_CTRL_OSC2_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS)) /**< OSC2_EN Mask */
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_RTC_CLK_CTRL_NANO_EN_POS 2 /**< NANO_EN Position */
AnnaBridge 171:3a7713b1edbc 306 #define MXC_F_RTC_CLK_CTRL_NANO_EN ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS)) /**< NANO_EN Mask */
AnnaBridge 171:3a7713b1edbc 307 /**@} end of group RTC_CLK_CTRL_Register */
AnnaBridge 171:3a7713b1edbc 308 /**
AnnaBridge 171:3a7713b1edbc 309 * @ingroup rtc_registers
AnnaBridge 171:3a7713b1edbc 310 * @defgroup RTC_OSC_CTRL_Register RTC_OSC_CTRL.
AnnaBridge 171:3a7713b1edbc 311 * @{
AnnaBridge 171:3a7713b1edbc 312 */
AnnaBridge 171:3a7713b1edbc 313 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS 0 /**< OSC_BYPASS Position */
AnnaBridge 171:3a7713b1edbc 314 #define MXC_F_RTC_OSC_CTRL_OSC_BYPASS ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS)) /**< OSC_BYPASS Mask */
AnnaBridge 171:3a7713b1edbc 315 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS 1 /**< OSC_DISABLE_R Position */
AnnaBridge 171:3a7713b1edbc 316 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS)) /**< OSC_DISABLE_R Mask */
AnnaBridge 171:3a7713b1edbc 317 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS 2 /**< OSC_DISABLE_SEL Position */
AnnaBridge 171:3a7713b1edbc 318 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS)) /**< OSC_DISABLE_SEL Mask */
AnnaBridge 171:3a7713b1edbc 319 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS 3 /**< OSC_DISABLE_O Position */
AnnaBridge 171:3a7713b1edbc 320 #define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS)) /**< OSC_DISABLE_O Mask */
AnnaBridge 171:3a7713b1edbc 321 #define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS 14 /**< OSC_WARMUP_ENABLE Position */
AnnaBridge 171:3a7713b1edbc 322 #define MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE_POS)) /**< OSC_WARMUP_ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 323 /**@} end of group RTC_OSC_CTRL_Register */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /*
AnnaBridge 171:3a7713b1edbc 326 Field values
AnnaBridge 171:3a7713b1edbc 327 */
AnnaBridge 171:3a7713b1edbc 328 /**
AnnaBridge 171:3a7713b1edbc 329 * @ingroup RTC_CTRL_Register
AnnaBridge 171:3a7713b1edbc 330 * @defgroup rtc_snz_mode_values RTC SNOOZE MODE Values
AnnaBridge 171:3a7713b1edbc 331 * @{
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333 #define MXC_V_RTC_CTRL_SNOOZE_DISABLE ((uint32_t)(0x00000000UL)) /**< SNOOZE Mode Disable */
AnnaBridge 171:3a7713b1edbc 334 #define MXC_V_RTC_CTRL_SNOOZE_MODE_A ((uint32_t)(0x00000001UL)) /**< SNOOZE Mode A */
AnnaBridge 171:3a7713b1edbc 335 #define MXC_V_RTC_CTRL_SNOOZE_MODE_B ((uint32_t)(0x00000002UL)) /**< SNOOZE Mode B */
AnnaBridge 171:3a7713b1edbc 336 /**@} end of group rtc_snz_mode_values */
AnnaBridge 171:3a7713b1edbc 337 /**
AnnaBridge 171:3a7713b1edbc 338 * @ingroup RTC_PRESCALE_Register
AnnaBridge 171:3a7713b1edbc 339 * @defgroup rtc_prescale_values RTC Prescale Values
AnnaBridge 171:3a7713b1edbc 340 * @{
AnnaBridge 171:3a7713b1edbc 341 */
AnnaBridge 171:3a7713b1edbc 342 #define MXC_V_RTC_PRESCALE_DIV_2_0 ((uint32_t)(0x00000000UL)) /**< RTC Prescale Divide by \f$ 2^{0} \f$.*/
AnnaBridge 171:3a7713b1edbc 343 #define MXC_V_RTC_PRESCALE_DIV_2_1 ((uint32_t)(0x00000001UL)) /**< RTC Prescale Divide by \f$ 2^{1} \f$.*/
AnnaBridge 171:3a7713b1edbc 344 #define MXC_V_RTC_PRESCALE_DIV_2_2 ((uint32_t)(0x00000002UL)) /**< RTC Prescale Divide by \f$ 2^{2} \f$.*/
AnnaBridge 171:3a7713b1edbc 345 #define MXC_V_RTC_PRESCALE_DIV_2_3 ((uint32_t)(0x00000003UL)) /**< RTC Prescale Divide by \f$ 2^{3} \f$.*/
AnnaBridge 171:3a7713b1edbc 346 #define MXC_V_RTC_PRESCALE_DIV_2_4 ((uint32_t)(0x00000004UL)) /**< RTC Prescale Divide by \f$ 2^{4} \f$.*/
AnnaBridge 171:3a7713b1edbc 347 #define MXC_V_RTC_PRESCALE_DIV_2_5 ((uint32_t)(0x00000005UL)) /**< RTC Prescale Divide by \f$ 2^{5} \f$.*/
AnnaBridge 171:3a7713b1edbc 348 #define MXC_V_RTC_PRESCALE_DIV_2_6 ((uint32_t)(0x00000006UL)) /**< RTC Prescale Divide by \f$ 2^{6} \f$.*/
AnnaBridge 171:3a7713b1edbc 349 #define MXC_V_RTC_PRESCALE_DIV_2_7 ((uint32_t)(0x00000007UL)) /**< RTC Prescale Divide by \f$ 2^{7} \f$.*/
AnnaBridge 171:3a7713b1edbc 350 #define MXC_V_RTC_PRESCALE_DIV_2_8 ((uint32_t)(0x00000008UL)) /**< RTC Prescale Divide by \f$ 2^{8} \f$.*/
AnnaBridge 171:3a7713b1edbc 351 #define MXC_V_RTC_PRESCALE_DIV_2_9 ((uint32_t)(0x00000009UL)) /**< RTC Prescale Divide by \f$ 2^{9} \f$.*/
AnnaBridge 171:3a7713b1edbc 352 #define MXC_V_RTC_PRESCALE_DIV_2_10 ((uint32_t)(0x0000000AUL)) /**< RTC Prescale Divide by \f$ 2^{10} \f$.*/
AnnaBridge 171:3a7713b1edbc 353 #define MXC_V_RTC_PRESCALE_DIV_2_11 ((uint32_t)(0x0000000BUL)) /**< RTC Prescale Divide by \f$ 2^{11} \f$.*/
AnnaBridge 171:3a7713b1edbc 354 #define MXC_V_RTC_PRESCALE_DIV_2_12 ((uint32_t)(0x0000000CUL)) /**< RTC Prescale Divide by \f$ 2^{12} \f$.*/
AnnaBridge 171:3a7713b1edbc 355 /**@} end of group rtc_prescale_values*/
AnnaBridge 171:3a7713b1edbc 356
AnnaBridge 171:3a7713b1edbc 357 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 358 }
AnnaBridge 171:3a7713b1edbc 359 #endif
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 #endif /* _MXC_RTC_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 362