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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/pwrseq_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *
AnnaBridge 171:3a7713b1edbc 32 * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 171:3a7713b1edbc 33 * $Revision: 21838 $
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifndef _MXC_PWRSEQ_REGS_H_
AnnaBridge 171:3a7713b1edbc 38 #define _MXC_PWRSEQ_REGS_H_
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /*
AnnaBridge 171:3a7713b1edbc 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 48 */
AnnaBridge 171:3a7713b1edbc 49 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 50 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52 #ifndef __I
AnnaBridge 171:3a7713b1edbc 53 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 54 #endif
AnnaBridge 171:3a7713b1edbc 55 #ifndef __O
AnnaBridge 171:3a7713b1edbc 56 #define __O volatile
AnnaBridge 171:3a7713b1edbc 57 #endif
AnnaBridge 171:3a7713b1edbc 58 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 59 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 60 #endif
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /*
AnnaBridge 171:3a7713b1edbc 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 171:3a7713b1edbc 65 access to each register in module.
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 69 ============= ============================================================================ */
AnnaBridge 171:3a7713b1edbc 70 typedef struct {
AnnaBridge 171:3a7713b1edbc 71 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
AnnaBridge 171:3a7713b1edbc 72 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
AnnaBridge 171:3a7713b1edbc 73 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
AnnaBridge 171:3a7713b1edbc 74 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
AnnaBridge 171:3a7713b1edbc 76 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
AnnaBridge 171:3a7713b1edbc 77 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
AnnaBridge 171:3a7713b1edbc 78 __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
AnnaBridge 171:3a7713b1edbc 80 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
AnnaBridge 171:3a7713b1edbc 81 __RO uint32_t rsv028; /* 0x0028 */
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
AnnaBridge 171:3a7713b1edbc 87 } mxc_pwrseq_regs_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /*
AnnaBridge 171:3a7713b1edbc 91 Register offsets for module PWRSEQ.
AnnaBridge 171:3a7713b1edbc 92 */
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 95 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 96 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 97 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 98 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 99 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
AnnaBridge 171:3a7713b1edbc 102 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
AnnaBridge 171:3a7713b1edbc 103 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
AnnaBridge 171:3a7713b1edbc 104 #define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
AnnaBridge 171:3a7713b1edbc 105 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
AnnaBridge 171:3a7713b1edbc 106 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
AnnaBridge 171:3a7713b1edbc 107 #define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
AnnaBridge 171:3a7713b1edbc 108 #define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /*
AnnaBridge 171:3a7713b1edbc 112 Field positions and masks for module PWRSEQ.
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
AnnaBridge 171:3a7713b1edbc 201 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
AnnaBridge 171:3a7713b1edbc 225 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
AnnaBridge 171:3a7713b1edbc 234 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
AnnaBridge 171:3a7713b1edbc 235 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
AnnaBridge 171:3a7713b1edbc 236 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
AnnaBridge 171:3a7713b1edbc 237 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
AnnaBridge 171:3a7713b1edbc 238 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
AnnaBridge 171:3a7713b1edbc 239 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
AnnaBridge 171:3a7713b1edbc 247 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
AnnaBridge 171:3a7713b1edbc 248 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
AnnaBridge 171:3a7713b1edbc 249 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
AnnaBridge 171:3a7713b1edbc 250 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
AnnaBridge 171:3a7713b1edbc 251 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
AnnaBridge 171:3a7713b1edbc 252 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
AnnaBridge 171:3a7713b1edbc 257 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
AnnaBridge 171:3a7713b1edbc 258 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
AnnaBridge 171:3a7713b1edbc 259 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
AnnaBridge 171:3a7713b1edbc 272 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
AnnaBridge 171:3a7713b1edbc 273 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
AnnaBridge 171:3a7713b1edbc 274 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
AnnaBridge 171:3a7713b1edbc 277 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
AnnaBridge 171:3a7713b1edbc 278 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
AnnaBridge 171:3a7713b1edbc 285 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 287 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
AnnaBridge 171:3a7713b1edbc 288 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 289 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
AnnaBridge 171:3a7713b1edbc 290 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
AnnaBridge 171:3a7713b1edbc 291 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
AnnaBridge 171:3a7713b1edbc 292 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 293 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
AnnaBridge 171:3a7713b1edbc 294 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 295 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
AnnaBridge 171:3a7713b1edbc 296 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 297 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
AnnaBridge 171:3a7713b1edbc 298 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 299 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
AnnaBridge 171:3a7713b1edbc 300 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
AnnaBridge 171:3a7713b1edbc 306 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
AnnaBridge 171:3a7713b1edbc 307 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
AnnaBridge 171:3a7713b1edbc 308 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
AnnaBridge 171:3a7713b1edbc 309 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
AnnaBridge 171:3a7713b1edbc 310 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
AnnaBridge 171:3a7713b1edbc 311 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
AnnaBridge 171:3a7713b1edbc 312 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
AnnaBridge 171:3a7713b1edbc 313 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
AnnaBridge 171:3a7713b1edbc 314 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 315 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
AnnaBridge 171:3a7713b1edbc 316 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 317 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
AnnaBridge 171:3a7713b1edbc 318 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
AnnaBridge 171:3a7713b1edbc 319 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
AnnaBridge 171:3a7713b1edbc 320 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 321 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
AnnaBridge 171:3a7713b1edbc 322 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 323 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
AnnaBridge 171:3a7713b1edbc 324 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 325 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
AnnaBridge 171:3a7713b1edbc 326 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 327 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
AnnaBridge 171:3a7713b1edbc 328 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
AnnaBridge 171:3a7713b1edbc 329 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
AnnaBridge 171:3a7713b1edbc 330 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
AnnaBridge 171:3a7713b1edbc 333 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
AnnaBridge 171:3a7713b1edbc 334 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
AnnaBridge 171:3a7713b1edbc 335 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 336 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
AnnaBridge 171:3a7713b1edbc 337 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 338 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
AnnaBridge 171:3a7713b1edbc 339 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
AnnaBridge 171:3a7713b1edbc 340 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
AnnaBridge 171:3a7713b1edbc 341 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 342 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
AnnaBridge 171:3a7713b1edbc 343 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 344 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
AnnaBridge 171:3a7713b1edbc 345 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 346 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
AnnaBridge 171:3a7713b1edbc 347 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 348 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
AnnaBridge 171:3a7713b1edbc 349 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 350 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
AnnaBridge 171:3a7713b1edbc 351 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 352 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
AnnaBridge 171:3a7713b1edbc 353 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
AnnaBridge 171:3a7713b1edbc 354 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
AnnaBridge 171:3a7713b1edbc 355 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
AnnaBridge 171:3a7713b1edbc 356 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
AnnaBridge 171:3a7713b1edbc 357 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
AnnaBridge 171:3a7713b1edbc 358 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
AnnaBridge 171:3a7713b1edbc 359 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
AnnaBridge 171:3a7713b1edbc 360 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
AnnaBridge 171:3a7713b1edbc 361 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
AnnaBridge 171:3a7713b1edbc 362 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
AnnaBridge 171:3a7713b1edbc 363 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 364 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
AnnaBridge 171:3a7713b1edbc 365 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
AnnaBridge 171:3a7713b1edbc 366 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
AnnaBridge 171:3a7713b1edbc 367 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
AnnaBridge 171:3a7713b1edbc 368 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
AnnaBridge 171:3a7713b1edbc 369 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 370 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
AnnaBridge 171:3a7713b1edbc 371 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
AnnaBridge 171:3a7713b1edbc 372 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
AnnaBridge 171:3a7713b1edbc 373 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 374 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
AnnaBridge 171:3a7713b1edbc 375 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 376 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
AnnaBridge 171:3a7713b1edbc 377 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
AnnaBridge 171:3a7713b1edbc 378 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
AnnaBridge 171:3a7713b1edbc 379 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
AnnaBridge 171:3a7713b1edbc 382 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
AnnaBridge 171:3a7713b1edbc 383 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
AnnaBridge 171:3a7713b1edbc 384 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
AnnaBridge 171:3a7713b1edbc 385 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
AnnaBridge 171:3a7713b1edbc 386 #define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
AnnaBridge 171:3a7713b1edbc 387 #define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
AnnaBridge 171:3a7713b1edbc 388 #define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
AnnaBridge 171:3a7713b1edbc 389 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
AnnaBridge 171:3a7713b1edbc 390 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
AnnaBridge 171:3a7713b1edbc 391 #define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
AnnaBridge 171:3a7713b1edbc 392 #define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
AnnaBridge 171:3a7713b1edbc 395 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
AnnaBridge 171:3a7713b1edbc 396 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
AnnaBridge 171:3a7713b1edbc 397 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
AnnaBridge 171:3a7713b1edbc 398 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
AnnaBridge 171:3a7713b1edbc 399 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
AnnaBridge 171:3a7713b1edbc 400 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
AnnaBridge 171:3a7713b1edbc 401 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
AnnaBridge 171:3a7713b1edbc 402 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
AnnaBridge 171:3a7713b1edbc 403 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
AnnaBridge 171:3a7713b1edbc 406 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
AnnaBridge 171:3a7713b1edbc 407 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
AnnaBridge 171:3a7713b1edbc 408 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
AnnaBridge 171:3a7713b1edbc 409
AnnaBridge 171:3a7713b1edbc 410 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
AnnaBridge 171:3a7713b1edbc 411 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
AnnaBridge 171:3a7713b1edbc 414 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
AnnaBridge 171:3a7713b1edbc 415 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
AnnaBridge 171:3a7713b1edbc 416 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
AnnaBridge 171:3a7713b1edbc 417 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
AnnaBridge 171:3a7713b1edbc 418 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
AnnaBridge 171:3a7713b1edbc 419 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
AnnaBridge 171:3a7713b1edbc 420 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
AnnaBridge 171:3a7713b1edbc 421 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
AnnaBridge 171:3a7713b1edbc 422 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 427 }
AnnaBridge 171:3a7713b1edbc 428 #endif
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 #endif /* _MXC_PWRSEQ_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 431