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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/ioman_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief IOMAN hardware register definitions. |
| AnnaBridge | 171:3a7713b1edbc | 4 | */ |
| AnnaBridge | 171:3a7713b1edbc | 5 | /* ***************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| AnnaBridge | 171:3a7713b1edbc | 7 | * |
| AnnaBridge | 171:3a7713b1edbc | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
| AnnaBridge | 171:3a7713b1edbc | 9 | * copy of this software and associated documentation files (the "Software"), |
| AnnaBridge | 171:3a7713b1edbc | 10 | * to deal in the Software without restriction, including without limitation |
| AnnaBridge | 171:3a7713b1edbc | 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * and/or sell copies of the Software, and to permit persons to whom the |
| AnnaBridge | 171:3a7713b1edbc | 13 | * Software is furnished to do so, subject to the following conditions: |
| AnnaBridge | 171:3a7713b1edbc | 14 | * |
| AnnaBridge | 171:3a7713b1edbc | 15 | * The above copyright notice and this permission notice shall be included |
| AnnaBridge | 171:3a7713b1edbc | 16 | * in all copies or substantial portions of the Software. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * |
| AnnaBridge | 171:3a7713b1edbc | 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| AnnaBridge | 171:3a7713b1edbc | 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| AnnaBridge | 171:3a7713b1edbc | 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| AnnaBridge | 171:3a7713b1edbc | 22 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| AnnaBridge | 171:3a7713b1edbc | 23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| AnnaBridge | 171:3a7713b1edbc | 24 | * OTHER DEALINGS IN THE SOFTWARE. |
| AnnaBridge | 171:3a7713b1edbc | 25 | * |
| AnnaBridge | 171:3a7713b1edbc | 26 | * Except as contained in this notice, the name of Maxim Integrated |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| AnnaBridge | 171:3a7713b1edbc | 28 | * Products, Inc. Branding Policy. |
| AnnaBridge | 171:3a7713b1edbc | 29 | * |
| AnnaBridge | 171:3a7713b1edbc | 30 | * The mere transfer of this software does not imply any licenses |
| AnnaBridge | 171:3a7713b1edbc | 31 | * of trade secrets, proprietary technology, copyrights, patents, |
| AnnaBridge | 171:3a7713b1edbc | 32 | * trademarks, maskwork rights, or any other form of intellectual |
| AnnaBridge | 171:3a7713b1edbc | 33 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| AnnaBridge | 171:3a7713b1edbc | 34 | * ownership rights. |
| AnnaBridge | 171:3a7713b1edbc | 35 | * |
| AnnaBridge | 171:3a7713b1edbc | 36 | * $Date: 2016-10-31 17:07:02 -0500 (Mon, 31 Oct 2016) $ |
| AnnaBridge | 171:3a7713b1edbc | 37 | * $Revision: 24857 $ |
| AnnaBridge | 171:3a7713b1edbc | 38 | * |
| AnnaBridge | 171:3a7713b1edbc | 39 | **************************************************************************** */ |
| AnnaBridge | 171:3a7713b1edbc | 40 | |
| AnnaBridge | 171:3a7713b1edbc | 41 | /* Define to prevent redundant inclusion. */ |
| AnnaBridge | 171:3a7713b1edbc | 42 | #ifndef _MXC_IOMAN_REGS_H_ |
| AnnaBridge | 171:3a7713b1edbc | 43 | #define _MXC_IOMAN_REGS_H_ |
| AnnaBridge | 171:3a7713b1edbc | 44 | |
| AnnaBridge | 171:3a7713b1edbc | 45 | /* **** Includes **** */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | #include <stdint.h> |
| AnnaBridge | 171:3a7713b1edbc | 47 | |
| AnnaBridge | 171:3a7713b1edbc | 48 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 49 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 50 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 51 | |
| AnnaBridge | 171:3a7713b1edbc | 52 | /* |
| AnnaBridge | 171:3a7713b1edbc | 53 | If types are not defined elsewhere (CMSIS) define them here |
| AnnaBridge | 171:3a7713b1edbc | 54 | */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | ///@cond |
| AnnaBridge | 171:3a7713b1edbc | 56 | #ifndef __IO |
| AnnaBridge | 171:3a7713b1edbc | 57 | #define __IO volatile |
| AnnaBridge | 171:3a7713b1edbc | 58 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 59 | #ifndef __I |
| AnnaBridge | 171:3a7713b1edbc | 60 | #define __I volatile const |
| AnnaBridge | 171:3a7713b1edbc | 61 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 62 | #ifndef __O |
| AnnaBridge | 171:3a7713b1edbc | 63 | #define __O volatile |
| AnnaBridge | 171:3a7713b1edbc | 64 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 65 | #ifndef __RO |
| AnnaBridge | 171:3a7713b1edbc | 66 | #define __RO volatile const |
| AnnaBridge | 171:3a7713b1edbc | 67 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 68 | ///@endcond |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | /* **** Definitions **** */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | /** |
| AnnaBridge | 171:3a7713b1edbc | 72 | * Structure type for wakeup detection @b request for port 4, port 5, port 6 and port 7. |
| AnnaBridge | 171:3a7713b1edbc | 73 | */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 75 | uint32_t wud_req_p4 : 8; /**< Port 4 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | uint32_t wud_req_p5 : 8; /**< Port 5 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t wud_req_p6 : 8; /**< Port 6 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | uint32_t wud_req_p7 : 8; /**< Port 7 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | } mxc_ioman_wud_req1_t; |
| AnnaBridge | 171:3a7713b1edbc | 80 | /** |
| AnnaBridge | 171:3a7713b1edbc | 81 | * Structure type for wakeup detection @b acknowledgement for port 0, port 1, port 2 and port 3. |
| AnnaBridge | 171:3a7713b1edbc | 82 | */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 84 | uint32_t wud_ack_p0 : 8; /**< Port 0 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t wud_ack_p1 : 8; /**< Port 1 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | uint32_t wud_ack_p2 : 8; /**< Port 2 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t wud_ack_p3 : 8; /**< Port 3 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | } mxc_ioman_wud_ack0_t; |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | /** |
| AnnaBridge | 171:3a7713b1edbc | 91 | * @ingroup ioman |
| AnnaBridge | 171:3a7713b1edbc | 92 | * @defgroup ioman_req_ack_bit_fields IOMAN Bit Field Structures |
| AnnaBridge | 171:3a7713b1edbc | 93 | * @brief Bit Field Structes used to request and configure all I/O for all |
| AnnaBridge | 171:3a7713b1edbc | 94 | * port pins and peripherals with external I/O. |
| AnnaBridge | 171:3a7713b1edbc | 95 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 96 | */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t wud_req_p0 : 8; /**< Port 0 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | uint32_t wud_req_p1 : 8; /**< Port 1 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | uint32_t wud_req_p2 : 8; /**< Port 2 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | uint32_t wud_req_p3 : 8; /**< Port 3 wake-up detection @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | } mxc_ioman_wud_req0_t; |
| AnnaBridge | 171:3a7713b1edbc | 103 | /** |
| AnnaBridge | 171:3a7713b1edbc | 104 | * Structure type for wakeup detection @b acknowledgement for port 4, port 5, port 6 and port 7. |
| AnnaBridge | 171:3a7713b1edbc | 105 | */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 107 | uint32_t wud_ack_p4 : 8; /**< Port 4 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t wud_ack_p5 : 8; /**< Port 5 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | uint32_t wud_ack_p6 : 8; /**< Port 6 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | uint32_t wud_ack_p7 : 8; /**< Port 7 wake-up detection @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | } mxc_ioman_wud_ack1_t; |
| AnnaBridge | 171:3a7713b1edbc | 112 | /** |
| AnnaBridge | 171:3a7713b1edbc | 113 | * Structure type for analog input @b request for port 0, port 1, port 2 and port 3. |
| AnnaBridge | 171:3a7713b1edbc | 114 | */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 116 | uint32_t ali_req_p0 : 8; /**< Port 0 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | uint32_t ali_req_p1 : 8; /**< Port 1 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | uint32_t ali_req_p2 : 8; /**< Port 2 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | uint32_t ali_req_p3 : 8; /**< Port 3 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | } mxc_ioman_ali_req0_t; |
| AnnaBridge | 171:3a7713b1edbc | 121 | /** |
| AnnaBridge | 171:3a7713b1edbc | 122 | * Structure type for analog input @b request for port 4, port 5, port 6 and port 7. |
| AnnaBridge | 171:3a7713b1edbc | 123 | */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 125 | uint32_t ali_req_p4 : 8; /**< Port 4 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | uint32_t ali_req_p5 : 8; /**< Port 5 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | uint32_t ali_req_p6 : 8; /**< Port 6 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | uint32_t ali_req_p7 : 8; /**< Port 7 analog input @b request bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | } mxc_ioman_ali_req1_t; |
| AnnaBridge | 171:3a7713b1edbc | 130 | /** |
| AnnaBridge | 171:3a7713b1edbc | 131 | * Structure type for analog input @b acknowledgement for port 0, port 1, port 2 and port 3. |
| AnnaBridge | 171:3a7713b1edbc | 132 | */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 134 | uint32_t ali_ack_p0 : 8; /**< Port 0 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | uint32_t ali_ack_p1 : 8; /**< Port 1 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | uint32_t ali_ack_p2 : 8; /**< Port 2 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | uint32_t ali_ack_p3 : 8; /**< Port 3 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | } mxc_ioman_ali_ack0_t; |
| AnnaBridge | 171:3a7713b1edbc | 139 | /** |
| AnnaBridge | 171:3a7713b1edbc | 140 | * Structure type for analog input @b acknowledgement for port 4, port 5, port 6 and port 7. |
| AnnaBridge | 171:3a7713b1edbc | 141 | */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 143 | uint32_t ali_ack_p4 : 8; /**< Port 4 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | uint32_t ali_ack_p5 : 8; /**< Port 5 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | uint32_t ali_ack_p6 : 8; /**< Port 6 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | uint32_t ali_ack_p7 : 8; /**< Port 7 analog input @b acknowledgement bit field. */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | } mxc_ioman_ali_ack1_t; |
| AnnaBridge | 171:3a7713b1edbc | 148 | /** |
| AnnaBridge | 171:3a7713b1edbc | 149 | * Structure type for SPI XIP configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 150 | */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 152 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | uint32_t core_io_req : 1; /**< Set to request the SPIX core external pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | uint32_t : 1; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | uint32_t : 15; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | } mxc_ioman_spix_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 164 | /** |
| AnnaBridge | 171:3a7713b1edbc | 165 | * Structure type for SPI XIP configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 168 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | uint32_t core_io_ack : 1; /**< Is set if the request for the SPIX core external pins succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | uint32_t : 1; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | uint32_t : 15; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | } mxc_ioman_spix_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 180 | /** |
| AnnaBridge | 171:3a7713b1edbc | 181 | * Structure type for UART0 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 182 | */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 184 | uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | } mxc_ioman_uart0_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 193 | /** |
| AnnaBridge | 171:3a7713b1edbc | 194 | * Structure type for UART0 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 197 | uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | } mxc_ioman_uart0_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 206 | /** |
| AnnaBridge | 171:3a7713b1edbc | 207 | * Structure type for UART1 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 208 | */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 210 | uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | } mxc_ioman_uart1_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 219 | /** |
| AnnaBridge | 171:3a7713b1edbc | 220 | * Structure type for UART1 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 221 | */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 223 | uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | } mxc_ioman_uart1_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 232 | /** |
| AnnaBridge | 171:3a7713b1edbc | 233 | * Structure type for UART2 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 234 | */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 236 | uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | } mxc_ioman_uart2_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 245 | /** |
| AnnaBridge | 171:3a7713b1edbc | 246 | * Structure type for UART2 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 247 | */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 249 | uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | } mxc_ioman_uart2_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 258 | /** |
| AnnaBridge | 171:3a7713b1edbc | 259 | * Structure type for UART3 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 260 | */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 262 | uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | } mxc_ioman_uart3_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 271 | /** |
| AnnaBridge | 171:3a7713b1edbc | 272 | * Structure type for UART3 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 273 | */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 275 | uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | uint32_t : 25; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | } mxc_ioman_uart3_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 284 | /** |
| AnnaBridge | 171:3a7713b1edbc | 285 | * Structure type for I2C Master 0 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 286 | */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 288 | uint32_t : 4; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM0 pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | } mxc_ioman_i2cm0_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 292 | /** |
| AnnaBridge | 171:3a7713b1edbc | 293 | * Structure type for I2C Master 0 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 294 | */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 296 | uint32_t : 4; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | } mxc_ioman_i2cm0_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 300 | /** |
| AnnaBridge | 171:3a7713b1edbc | 301 | * Structure type for I2C Master 1 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 302 | */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 304 | uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM1 CLK and Data pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | uint32_t : 2; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM1 pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | } mxc_ioman_i2cm1_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 309 | /** |
| AnnaBridge | 171:3a7713b1edbc | 310 | * Structure type for I2C Master 1 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 311 | */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 313 | uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | uint32_t : 2; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | } mxc_ioman_i2cm1_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 318 | /** |
| AnnaBridge | 171:3a7713b1edbc | 319 | * Structure type for I2C Master 2 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 320 | */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 322 | uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM2 CLK and Data pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | uint32_t : 2; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM2 pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | } mxc_ioman_i2cm2_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 327 | /** |
| AnnaBridge | 171:3a7713b1edbc | 328 | * Structure type for I2C Master 2 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 329 | */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 331 | uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | uint32_t : 2; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | } mxc_ioman_i2cm2_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 336 | /** |
| AnnaBridge | 171:3a7713b1edbc | 337 | * Structure type for I2C Slave 0 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 338 | */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 340 | uint32_t io_sel : 3; /**< Value for the desired pin mapping for the I2CS0 CLK and Data pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CS0 pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | } mxc_ioman_i2cs_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 345 | /** |
| AnnaBridge | 171:3a7713b1edbc | 346 | * Structure type for I2C Slave 0 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 347 | */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 349 | uint32_t io_sel : 3; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | uint32_t : 1; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | uint32_t : 27; /**< Reserved: Do No Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | } mxc_ioman_i2cs_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 354 | /** |
| AnnaBridge | 171:3a7713b1edbc | 355 | * Structure type for SPI Master 0 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 356 | */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 358 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | uint32_t core_io_req : 1; /**< Set to request the SPIM0 core external pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | uint32_t ss3_io_req : 1; /**< Set to request slave select 3 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | uint32_t ss4_io_req : 1; /**< Set to request slave select 4 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | uint32_t quad_io_req : 1; /**< Set to 1 to request Quad I/O for SPIM0. */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | uint32_t fast_mode : 1; /**< Set to request fast mode operation for SPIM0. */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | } mxc_ioman_spim0_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 372 | /** |
| AnnaBridge | 171:3a7713b1edbc | 373 | * Structure type for SPI Master 0 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 374 | */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 376 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM0 core external pins succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | uint32_t ss3_io_ack : 1; /**< Is set if the request for the slave select 3 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | uint32_t ss4_io_ack : 1; /**< Is set if the request for the slave select 4 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | } mxc_ioman_spim0_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 390 | /** |
| AnnaBridge | 171:3a7713b1edbc | 391 | * Structure type for SPI Master 1 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 392 | */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 394 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | uint32_t core_io_req : 1; /**< Set to request the SPIM1 core external pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | uint32_t : 9; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | } mxc_ioman_spim1_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 406 | /** |
| AnnaBridge | 171:3a7713b1edbc | 407 | * Structure type for SPI Master 1 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 408 | */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 410 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM1 core external pins succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | uint32_t : 9; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | } mxc_ioman_spim1_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 422 | /** |
| AnnaBridge | 171:3a7713b1edbc | 423 | * Structure type for SPI Master 2 configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 424 | */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 426 | uint32_t mapping_req : 2; /**< Set to the desired port pin mapping for the SPIM2. */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | uint32_t : 2; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | uint32_t core_io_req : 1; /**< Set to request the SPIM2 core external pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | uint32_t : 5; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | uint32_t sr0_io_req : 1; /**< Set to 1 to request slave ready 0 input. */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | uint32_t sr1_io_req : 1; /**< Set to 1 to request slave ready 1 input. */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | uint32_t : 2; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | } mxc_ioman_spim2_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 442 | /** |
| AnnaBridge | 171:3a7713b1edbc | 443 | * Structure type for SPI Master 2 configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 444 | */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 446 | uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | uint32_t : 2; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM2 core external pins succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | uint32_t : 5; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | uint32_t sr0_io_req : 1; /**< Is set if the request for the slave ready 0 active input succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | uint32_t sr1_io_req : 1; /**< Is set if the request for the slave ready 1 active input succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | uint32_t : 2; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | uint32_t : 7; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | } mxc_ioman_spim2_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 462 | /** |
| AnnaBridge | 171:3a7713b1edbc | 463 | * Structure type for SPI Bridge configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 464 | */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 466 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | uint32_t core_io_req : 1; /**< Set to request the SPIB core external pins. */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | uint32_t : 19; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | } mxc_ioman_spib_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 474 | /** |
| AnnaBridge | 171:3a7713b1edbc | 475 | * Structure type for SPI Bridge configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 476 | */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 478 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | uint32_t core_io_ack : 1; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | uint32_t : 19; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | } mxc_ioman_spib_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 486 | /** |
| AnnaBridge | 171:3a7713b1edbc | 487 | * Structure type for 1-Wire Master (OWM) configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 488 | */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 490 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | uint32_t mapping_req : 1; /**< Set to the desired port pin mapping for the 1-Wire Master. */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | uint32_t epu_io_req : 1; /**< Set to 1 to request External Pull-up for the 1-Wire Master. */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | uint32_t : 26; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | } mxc_ioman_owm_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 495 | /** |
| AnnaBridge | 171:3a7713b1edbc | 496 | * Structure type for 1-Wire Master configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 497 | */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 499 | uint32_t : 4; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | uint32_t mapping_ack : 1; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | uint32_t epu_io_ack : 1; /**< Non-zero if external pull-up request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | uint32_t : 26; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | } mxc_ioman_owm_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 504 | /** |
| AnnaBridge | 171:3a7713b1edbc | 505 | * Structure type for SPI Slave configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 506 | */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 508 | uint32_t mapping_req : 2; /**< Set to desired port pin mapping for the SPIS peripheral. */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | uint32_t : 2; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | uint32_t core_io_req : 1; /**< Set to 1 to request the I/O be assigned to the SPIS. */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | uint32_t fast_mode : 1; /**< Set to request fast mode operation. */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | uint32_t : 19; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | } mxc_ioman_spis_req_t; |
| AnnaBridge | 171:3a7713b1edbc | 517 | /** |
| AnnaBridge | 171:3a7713b1edbc | 518 | * Structure type for SPI Slave configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 519 | */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 521 | uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | uint32_t : 2; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | uint32_t core_io_ack : 1; /**< Non-zero if core io request successful. */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | uint32_t : 3; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | uint32_t : 19; /**< Reserved: Do Not Modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | } mxc_ioman_spis_ack_t; |
| AnnaBridge | 171:3a7713b1edbc | 530 | /** |
| AnnaBridge | 171:3a7713b1edbc | 531 | * Structure type to configure the I/O pad mode options. |
| AnnaBridge | 171:3a7713b1edbc | 532 | */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 534 | uint32_t slow_mode : 1; /**< Slow mode I/O operation */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | uint32_t alt_rcvr_mode : 1; /**< Alternative receive mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | uint32_t : 30; /**< Reserved: Do not modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | } mxc_ioman_pad_mode_t; |
| AnnaBridge | 171:3a7713b1edbc | 538 | /** |
| AnnaBridge | 171:3a7713b1edbc | 539 | * Structure type for Wake-Up Detect (WUD) configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 540 | */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 542 | uint32_t wud_req_p8 : 2; /**< Request bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | uint32_t : 30; /**< Reserved: Do not modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | } mxc_ioman_wud_req2_t; |
| AnnaBridge | 171:3a7713b1edbc | 545 | /** |
| AnnaBridge | 171:3a7713b1edbc | 546 | * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 547 | */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 549 | uint32_t wud_ack_p8 : 2; /**< Acknowledgement bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | uint32_t : 30; /**< Reserved: Do not modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | } mxc_ioman_wud_ack2_t; |
| AnnaBridge | 171:3a7713b1edbc | 552 | /** |
| AnnaBridge | 171:3a7713b1edbc | 553 | * Structure type for Analog Wake-Up Detect (WUD) configuration @b requests. |
| AnnaBridge | 171:3a7713b1edbc | 554 | */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 556 | uint32_t ali_req_p8 : 2; /**< Request bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | uint32_t : 30; /**< Reserved: Do not modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | } mxc_ioman_ali_req2_t; |
| AnnaBridge | 171:3a7713b1edbc | 559 | /** |
| AnnaBridge | 171:3a7713b1edbc | 560 | * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements. |
| AnnaBridge | 171:3a7713b1edbc | 561 | */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 563 | uint32_t ali_ack_p8 : 2; /**< Acknowledgement bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | uint32_t : 30; /**< Reserved: Do not modify. */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | } mxc_ioman_ali_ack2_t; |
| AnnaBridge | 171:3a7713b1edbc | 566 | /**@} end of group ioman_req_ack_bit_fields */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | /** |
| AnnaBridge | 171:3a7713b1edbc | 568 | * @ingroup ioman |
| AnnaBridge | 171:3a7713b1edbc | 569 | * @defgroup ioman_registers IOMAN Registers |
| AnnaBridge | 171:3a7713b1edbc | 570 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 571 | * Structure type for the IOMAN Register Interface. |
| AnnaBridge | 171:3a7713b1edbc | 572 | * The table below shows the IOMAN Regsiter Offsets from the Base IOMAN Peripheral Address #MXC_BASE_IOMAN. |
| AnnaBridge | 171:3a7713b1edbc | 573 | */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 575 | __IO uint32_t wud_req0; /**< Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | __IO uint32_t wud_req1; /**< Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | __IO uint32_t wud_ack0; /**< Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | __IO uint32_t wud_ack1; /**< Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | __IO uint32_t ali_req0; /**< Analog Input Request Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | __IO uint32_t ali_req1; /**< Analog Input Request Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | __IO uint32_t ali_ack0; /**< Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | __IO uint32_t ali_ack1; /**< Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | __IO uint32_t ali_connect0; /**< Analog I/O Connection Control Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | __IO uint32_t ali_connect1; /**< Analog I/O Connection Control Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | __IO uint32_t spix_req; /**< SPIX I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | __IO uint32_t spix_ack; /**< SPIX I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | __IO uint32_t uart0_req; /**< UART0 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | __IO uint32_t uart0_ack; /**< UART0 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | __IO uint32_t uart1_req; /**< UART1 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | __IO uint32_t uart1_ack; /**< UART1 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | __IO uint32_t uart2_req; /**< UART2 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | __IO uint32_t uart2_ack; /**< UART2 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | __IO uint32_t uart3_req; /**< UART3 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | __IO uint32_t uart3_ack; /**< UART3 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | __IO uint32_t i2cm0_req; /**< I2C Master 0 I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | __IO uint32_t i2cm0_ack; /**< I2C Master 0 I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | __IO uint32_t i2cm1_req; /**< I2C Master 1 I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | __IO uint32_t i2cm1_ack; /**< I2C Master 1 I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | __IO uint32_t i2cm2_req; /**< I2C Master 2 I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | __IO uint32_t i2cm2_ack; /**< I2C Master 2 I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | __IO uint32_t i2cs_req; /**< I2C Slave I/O Request */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | __IO uint32_t i2cs_ack; /**< I2C Slave I/O Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | __IO uint32_t spim0_req; /**< SPI Master 0 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | __IO uint32_t spim0_ack; /**< SPI Master 0 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | __IO uint32_t spim1_req; /**< SPI Master 1 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | __IO uint32_t spim1_ack; /**< SPI Master 1 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | __IO uint32_t spim2_req; /**< SPI Master 2 I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | __IO uint32_t spim2_ack; /**< SPI Master 2 I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | __IO uint32_t spib_req; /**< SPI Bridge I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | __IO uint32_t spib_ack; /**< SPI Bridge I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | __IO uint32_t owm_req; /**< 1-Wire Master I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | __IO uint32_t owm_ack; /**< 1-Wire Master I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | __IO uint32_t spis_req; /**< SPI Slave I/O Mode Request */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | __IO uint32_t spis_ack; /**< SPI Slave I/O Mode Acknowledge */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | __RO uint32_t rsv0A0[24]; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | __IO uint32_t use_vddioh_0; /**< Enable VDDIOH Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | __IO uint32_t use_vddioh_1; /**< Enable VDDIOH Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | __IO uint32_t use_vddioh_2; /**< Enable VDDIOH Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | __RO uint32_t rsv10C; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | __IO uint32_t pad_mode; /**< Pad Mode Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | __RO uint32_t rsv114[27]; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | __IO uint32_t wud_req2; /**< Wakeup Detect Mode Request Register 2 (Port 8) */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | __RO uint32_t rsv184; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | __IO uint32_t wud_ack2; /**< Wakeup Detect Mode Acknowledge Register 2 (Port 8) */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | __RO uint32_t rsv18C; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | __IO uint32_t ali_req2; /**< Analog Input Request Register 2 (Port 8) */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | __RO uint32_t rsv194; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | __IO uint32_t ali_ack2; /**< Analog Input Acknowledge Register 2 (Port 8) */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | __RO uint32_t rsv19C; /**< RESERVED: DO NOT MODIFY */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | __IO uint32_t ali_connect2; /**< Analog I/O Connection Control Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | } mxc_ioman_regs_t; |
| AnnaBridge | 171:3a7713b1edbc | 632 | /**@}*/ |
| AnnaBridge | 171:3a7713b1edbc | 633 | |
| AnnaBridge | 171:3a7713b1edbc | 634 | /* |
| AnnaBridge | 171:3a7713b1edbc | 635 | Register offsets for module IOMAN. |
| AnnaBridge | 171:3a7713b1edbc | 636 | */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | /** |
| AnnaBridge | 171:3a7713b1edbc | 638 | * @ingroup ioman_registers |
| AnnaBridge | 171:3a7713b1edbc | 639 | * @defgroup ioman_reg_offs IOMAN Register Offsets |
| AnnaBridge | 171:3a7713b1edbc | 640 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 641 | * @details The @ref IOMAN_REGS_OFFS_TABLE "IOMAN Register Offset Table" |
| AnnaBridge | 171:3a7713b1edbc | 642 | * shows the register offsets for the IOMAN registers from the base |
| AnnaBridge | 171:3a7713b1edbc | 643 | * IOMAN peripheral address, #MXC_BASE_IOMAN. |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @anchor IOMAN_REGS_OFFS_TABLE |
| AnnaBridge | 171:3a7713b1edbc | 645 | * | Register | Offset | |
| AnnaBridge | 171:3a7713b1edbc | 646 | * | :----------- | ------:| |
| AnnaBridge | 171:3a7713b1edbc | 647 | * | WUD_REQ0 | 0x0000 | |
| AnnaBridge | 171:3a7713b1edbc | 648 | * | WUD_REQ1 | 0x0004 | |
| AnnaBridge | 171:3a7713b1edbc | 649 | * | WUD_ACK0 | 0x0008 | |
| AnnaBridge | 171:3a7713b1edbc | 650 | * | WUD_ACK1 | 0x000C | |
| AnnaBridge | 171:3a7713b1edbc | 651 | * | ALI_REQ0 | 0x0010 | |
| AnnaBridge | 171:3a7713b1edbc | 652 | * | ALI_REQ1 | 0x0014 | |
| AnnaBridge | 171:3a7713b1edbc | 653 | * | ALI_ACK0 | 0x0018 | |
| AnnaBridge | 171:3a7713b1edbc | 654 | * | ALI_ACK1 | 0x001C | |
| AnnaBridge | 171:3a7713b1edbc | 655 | * | ALI_CONNECT0 | 0x0020 | |
| AnnaBridge | 171:3a7713b1edbc | 656 | * | ALI_CONNECT1 | 0x0024 | |
| AnnaBridge | 171:3a7713b1edbc | 657 | * | SPIX_REQ | 0x0028 | |
| AnnaBridge | 171:3a7713b1edbc | 658 | * | SPIX_ACK | 0x002C | |
| AnnaBridge | 171:3a7713b1edbc | 659 | * | UART0_REQ | 0x0030 | |
| AnnaBridge | 171:3a7713b1edbc | 660 | * | UART0_ACK | 0x0034 | |
| AnnaBridge | 171:3a7713b1edbc | 661 | * | UART1_REQ | 0x0038 | |
| AnnaBridge | 171:3a7713b1edbc | 662 | * | UART1_ACK | 0x003C | |
| AnnaBridge | 171:3a7713b1edbc | 663 | * | UART2_REQ | 0x0040 | |
| AnnaBridge | 171:3a7713b1edbc | 664 | * | UART2_ACK | 0x0044 | |
| AnnaBridge | 171:3a7713b1edbc | 665 | * | UART3_REQ | 0x0048 | |
| AnnaBridge | 171:3a7713b1edbc | 666 | * | UART3_ACK | 0x004C | |
| AnnaBridge | 171:3a7713b1edbc | 667 | * | I2CM0_REQ | 0x0050 | |
| AnnaBridge | 171:3a7713b1edbc | 668 | * | I2CM0_ACK | 0x0054 | |
| AnnaBridge | 171:3a7713b1edbc | 669 | * | I2CM1_REQ | 0x0058 | |
| AnnaBridge | 171:3a7713b1edbc | 670 | * | I2CM1_ACK | 0x005C | |
| AnnaBridge | 171:3a7713b1edbc | 671 | * | I2CM2_REQ | 0x0060 | |
| AnnaBridge | 171:3a7713b1edbc | 672 | * | I2CM2_ACK | 0x0064 | |
| AnnaBridge | 171:3a7713b1edbc | 673 | * | I2CS_REQ | 0x0068 | |
| AnnaBridge | 171:3a7713b1edbc | 674 | * | I2CS_ACK | 0x006C | |
| AnnaBridge | 171:3a7713b1edbc | 675 | * | SPIM0_REQ | 0x0070 | |
| AnnaBridge | 171:3a7713b1edbc | 676 | * | SPIM0_ACK | 0x0074 | |
| AnnaBridge | 171:3a7713b1edbc | 677 | * | SPIM1_REQ | 0x0078 | |
| AnnaBridge | 171:3a7713b1edbc | 678 | * | SPIM1_ACK | 0x007C | |
| AnnaBridge | 171:3a7713b1edbc | 679 | * | SPIM2_REQ | 0x0080 | |
| AnnaBridge | 171:3a7713b1edbc | 680 | * | SPIM2_ACK | 0x0084 | |
| AnnaBridge | 171:3a7713b1edbc | 681 | * | SPIB_REQ | 0x0088 | |
| AnnaBridge | 171:3a7713b1edbc | 682 | * | SPIB_ACK | 0x008C | |
| AnnaBridge | 171:3a7713b1edbc | 683 | * | OWM_REQ | 0x0090 | |
| AnnaBridge | 171:3a7713b1edbc | 684 | * | OWM_ACK | 0x0094 | |
| AnnaBridge | 171:3a7713b1edbc | 685 | * | SPIS_REQ | 0x0098 | |
| AnnaBridge | 171:3a7713b1edbc | 686 | * | SPIS_ACK | 0x009C | |
| AnnaBridge | 171:3a7713b1edbc | 687 | * | USE_VDDIOH_0 | 0x0100 | |
| AnnaBridge | 171:3a7713b1edbc | 688 | * | USE_VDDIOH_1 | 0x0104 | |
| AnnaBridge | 171:3a7713b1edbc | 689 | * | USE_VDDIOH_2 | 0x0108 | |
| AnnaBridge | 171:3a7713b1edbc | 690 | * | PAD_MODE | 0x0110 | |
| AnnaBridge | 171:3a7713b1edbc | 691 | * | WUD_REQ2 | 0x0180 | |
| AnnaBridge | 171:3a7713b1edbc | 692 | * | WUD_ACK2 | 0x0188 | |
| AnnaBridge | 171:3a7713b1edbc | 693 | * | ALI_REQ2 | 0x0190 | |
| AnnaBridge | 171:3a7713b1edbc | 694 | * | ALI_ACK2 | 0x0198 | |
| AnnaBridge | 171:3a7713b1edbc | 695 | * | ALI_CONNECT2 | 0x01A0 | |
| AnnaBridge | 171:3a7713b1edbc | 696 | */ |
| AnnaBridge | 171:3a7713b1edbc | 697 | #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) /**< WUD_REQ0 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) /**< WUD_REQ1 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) /**< WUD_ACK0 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) /**< WUD_ACK1 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) /**< ALI_REQ0 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) /**< ALI_REQ1 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) /**< ALI_ACK0 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) /**< ALI_ACK1 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) /**< ALI_CONNECT0 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 706 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) /**< ALI_CONNECT1 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | #define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) /**< SPIX_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | #define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) /**< SPIX_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) /**< UART0_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) /**< UART0_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) /**< UART1_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) /**< UART1_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) /**< UART2_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) /**< UART2_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) /**< UART3_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) /**< UART3_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) /**< I2CM0_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) /**< I2CM0_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) /**< I2CM1_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) /**< I2CM1_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) /**< I2CM2_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) /**< I2CM2_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 723 | #define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) /**< I2CS_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) /**< I2CS_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) /**< SPIM0_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) /**< SPIM0_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) /**< SPIM1_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) /**< SPIM1_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) /**< SPIM2_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 730 | #define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) /**< SPIM2_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | #define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) /**< SPIB_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 732 | #define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) /**< SPIB_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) /**< OWM_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | #define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) /**< OWM_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) /**< SPIS_REQ Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) /**< SPIS_ACK Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) /**< USE_VDDIOH_0 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) /**< USE_VDDIOH_1 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL) /**< USE_VDDIOH_2 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | #define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) /**< PAD_MODE Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | #define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL) /**< WUD_REQ2 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL) /**< WUD_ACK2 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL) /**< ALI_REQ2 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL) /**< ALI_ACK2 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL) /**< ALI_CONNECT2 Register Offset from base IOMAN Peripheral Address. */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | /**@}*/ |
| AnnaBridge | 171:3a7713b1edbc | 747 | |
| AnnaBridge | 171:3a7713b1edbc | 748 | /* |
| AnnaBridge | 171:3a7713b1edbc | 749 | Field positions and masks for module IOMAN. |
| AnnaBridge | 171:3a7713b1edbc | 750 | */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | /** |
| AnnaBridge | 171:3a7713b1edbc | 752 | * @ingroup ioman_registers |
| AnnaBridge | 171:3a7713b1edbc | 753 | * @defgroup Bit and Field Positions Masks for the IOMAN Registers. |
| AnnaBridge | 171:3a7713b1edbc | 754 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 755 | */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 761 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 762 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 763 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 764 | |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 771 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 773 | |
| AnnaBridge | 171:3a7713b1edbc | 774 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 780 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 782 | |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 789 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 791 | |
| AnnaBridge | 171:3a7713b1edbc | 792 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 793 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 795 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 796 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 797 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 798 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 799 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 800 | |
| AnnaBridge | 171:3a7713b1edbc | 801 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 802 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 803 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 804 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 805 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 806 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 807 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 808 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 809 | |
| AnnaBridge | 171:3a7713b1edbc | 810 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 814 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 816 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 817 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 818 | |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 820 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 821 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 822 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 823 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 825 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 827 | |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 829 | #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 831 | #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 832 | #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 833 | #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 834 | #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 835 | #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 836 | #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 837 | #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 838 | #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 839 | #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 840 | |
| AnnaBridge | 171:3a7713b1edbc | 841 | #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 842 | #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 843 | #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 844 | #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 845 | #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 846 | #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 847 | #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 848 | #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 849 | #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 850 | #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 851 | #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 852 | #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 853 | |
| AnnaBridge | 171:3a7713b1edbc | 854 | #define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 855 | #define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 856 | #define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 858 | #define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 859 | #define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 860 | #define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 861 | #define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 862 | #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 863 | #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 864 | #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 865 | #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 866 | |
| AnnaBridge | 171:3a7713b1edbc | 867 | #define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 868 | #define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 869 | #define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 870 | #define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 871 | #define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 872 | #define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 873 | #define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 874 | #define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 875 | #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 876 | #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 877 | #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 878 | #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 879 | |
| AnnaBridge | 171:3a7713b1edbc | 880 | #define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 881 | #define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 882 | #define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 883 | #define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 884 | #define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 885 | #define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 886 | #define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 887 | #define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 888 | #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 889 | #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 890 | #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 891 | #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 892 | |
| AnnaBridge | 171:3a7713b1edbc | 893 | #define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 894 | #define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 895 | #define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 896 | #define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 897 | #define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 898 | #define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 899 | #define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 900 | #define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 901 | #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 902 | #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 903 | #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 904 | #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 905 | |
| AnnaBridge | 171:3a7713b1edbc | 906 | #define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 907 | #define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 908 | #define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 909 | #define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 910 | #define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 911 | #define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 912 | #define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 913 | #define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 914 | #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 915 | #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 916 | #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 917 | #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 918 | |
| AnnaBridge | 171:3a7713b1edbc | 919 | #define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 920 | #define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 921 | #define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 922 | #define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 923 | #define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 924 | #define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 925 | #define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 926 | #define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 927 | #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 928 | #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 929 | #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 930 | #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 931 | |
| AnnaBridge | 171:3a7713b1edbc | 932 | #define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 933 | #define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 934 | #define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 935 | #define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 936 | #define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 937 | #define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 938 | #define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 939 | #define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 940 | #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 941 | #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 942 | #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 943 | #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 944 | |
| AnnaBridge | 171:3a7713b1edbc | 945 | #define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 946 | #define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 947 | #define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 948 | #define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 949 | #define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2 |
| AnnaBridge | 171:3a7713b1edbc | 950 | #define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 951 | #define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 952 | #define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 953 | #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 954 | #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 955 | #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6 |
| AnnaBridge | 171:3a7713b1edbc | 956 | #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 957 | |
| AnnaBridge | 171:3a7713b1edbc | 958 | #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 959 | #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 960 | |
| AnnaBridge | 171:3a7713b1edbc | 961 | #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 962 | #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 963 | |
| AnnaBridge | 171:3a7713b1edbc | 964 | #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 965 | #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 966 | #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 967 | #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 968 | |
| AnnaBridge | 171:3a7713b1edbc | 969 | #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 970 | #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 971 | #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 972 | #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 973 | |
| AnnaBridge | 171:3a7713b1edbc | 974 | #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 975 | #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 976 | #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 977 | #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 978 | |
| AnnaBridge | 171:3a7713b1edbc | 979 | #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 980 | #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 981 | #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 982 | #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 983 | |
| AnnaBridge | 171:3a7713b1edbc | 984 | #define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 985 | #define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 986 | #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 987 | #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 988 | |
| AnnaBridge | 171:3a7713b1edbc | 989 | #define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 990 | #define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 991 | #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 992 | #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 993 | |
| AnnaBridge | 171:3a7713b1edbc | 994 | #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 995 | #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 996 | #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 997 | #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 998 | #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 999 | #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1000 | #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 1001 | #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1002 | #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 1003 | #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1004 | #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 1005 | #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1006 | #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 1007 | #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1008 | #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 1009 | #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1010 | |
| AnnaBridge | 171:3a7713b1edbc | 1011 | #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1012 | #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1013 | #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1014 | #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1015 | #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 1016 | #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1017 | #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 1018 | #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1019 | #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 |
| AnnaBridge | 171:3a7713b1edbc | 1020 | #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1021 | #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 1022 | #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1023 | #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 1024 | #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1025 | #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 1026 | #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1027 | |
| AnnaBridge | 171:3a7713b1edbc | 1028 | #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1029 | #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1030 | #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1031 | #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1032 | #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 1033 | #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1034 | #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 1035 | #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1036 | #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 1037 | #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1038 | #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 1039 | #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1040 | |
| AnnaBridge | 171:3a7713b1edbc | 1041 | #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1042 | #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1043 | #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1044 | #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1045 | #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 1046 | #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1047 | #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 1048 | #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1049 | #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 1050 | #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1051 | #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 1052 | #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1053 | |
| AnnaBridge | 171:3a7713b1edbc | 1054 | #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1055 | #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1056 | #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1057 | #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1058 | #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1059 | #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1060 | #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 1061 | #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1062 | #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 1063 | #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1064 | #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 1065 | #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1066 | #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 1067 | #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1068 | #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 1069 | #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1070 | #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 1071 | #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1072 | |
| AnnaBridge | 171:3a7713b1edbc | 1073 | #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1074 | #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1075 | #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1076 | #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1077 | #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1078 | #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1079 | #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 |
| AnnaBridge | 171:3a7713b1edbc | 1080 | #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1081 | #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 |
| AnnaBridge | 171:3a7713b1edbc | 1082 | #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1083 | #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16 |
| AnnaBridge | 171:3a7713b1edbc | 1084 | #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1085 | #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17 |
| AnnaBridge | 171:3a7713b1edbc | 1086 | #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1087 | #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20 |
| AnnaBridge | 171:3a7713b1edbc | 1088 | #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1089 | #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 |
| AnnaBridge | 171:3a7713b1edbc | 1090 | #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1091 | |
| AnnaBridge | 171:3a7713b1edbc | 1092 | #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1093 | #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1094 | #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1095 | #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1096 | #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 1097 | #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1098 | |
| AnnaBridge | 171:3a7713b1edbc | 1099 | #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1100 | #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1101 | #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1102 | #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1103 | #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 1104 | #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1105 | |
| AnnaBridge | 171:3a7713b1edbc | 1106 | #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1107 | #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1108 | #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 1109 | #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1110 | |
| AnnaBridge | 171:3a7713b1edbc | 1111 | #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1112 | #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1113 | #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 |
| AnnaBridge | 171:3a7713b1edbc | 1114 | #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1115 | |
| AnnaBridge | 171:3a7713b1edbc | 1116 | #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1117 | #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1118 | #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1119 | #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1120 | #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1121 | #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1122 | #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 1123 | #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1124 | |
| AnnaBridge | 171:3a7713b1edbc | 1125 | #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1126 | #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1127 | #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4 |
| AnnaBridge | 171:3a7713b1edbc | 1128 | #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1129 | #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8 |
| AnnaBridge | 171:3a7713b1edbc | 1130 | #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1131 | #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12 |
| AnnaBridge | 171:3a7713b1edbc | 1132 | #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1133 | |
| AnnaBridge | 171:3a7713b1edbc | 1134 | #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1135 | #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1136 | #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1 |
| AnnaBridge | 171:3a7713b1edbc | 1137 | #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1138 | |
| AnnaBridge | 171:3a7713b1edbc | 1139 | #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1140 | #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1141 | |
| AnnaBridge | 171:3a7713b1edbc | 1142 | #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1143 | #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1144 | |
| AnnaBridge | 171:3a7713b1edbc | 1145 | #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1146 | #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1147 | |
| AnnaBridge | 171:3a7713b1edbc | 1148 | #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0 |
| AnnaBridge | 171:3a7713b1edbc | 1149 | #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS)) |
| AnnaBridge | 171:3a7713b1edbc | 1150 | |
| AnnaBridge | 171:3a7713b1edbc | 1151 | /* |
| AnnaBridge | 171:3a7713b1edbc | 1152 | Generic field positions and masks |
| AnnaBridge | 171:3a7713b1edbc | 1153 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1154 | #define MXC_F_IOMAN_UART_REQ_IO_REQ MXC_F_IOMAN_UART0_REQ_IO_REQ |
| AnnaBridge | 171:3a7713b1edbc | 1155 | #define MXC_F_IOMAN_UART_ACK_IO_ACK MXC_F_IOMAN_UART0_ACK_IO_ACK |
| AnnaBridge | 171:3a7713b1edbc | 1156 | /**@}*/ |
| AnnaBridge | 171:3a7713b1edbc | 1157 | |
| AnnaBridge | 171:3a7713b1edbc | 1158 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 1159 | } |
| AnnaBridge | 171:3a7713b1edbc | 1160 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 1161 | |
| AnnaBridge | 171:3a7713b1edbc | 1162 | #endif /* _MXC_IOMAN_REGS_H_ */ |
| AnnaBridge | 171:3a7713b1edbc | 1163 |
