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TARGET_MAX32630FTHR/TOOLCHAIN_GCC_ARM/aes_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5
AnnaBridge 171:3a7713b1edbc 6 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 10 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 11 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 13 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 14 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 17 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 25 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 29 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 32 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 33 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 35 * ownership rights.
AnnaBridge 171:3a7713b1edbc 36 *
AnnaBridge 171:3a7713b1edbc 37 * $Date: 2016-10-10 16:51:05 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 38 * $Revision: 24655 $
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 43 #ifndef _MXC_AES_REGS_H_
AnnaBridge 171:3a7713b1edbc 44 #define _MXC_AES_REGS_H_
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 47 extern "C" {
AnnaBridge 171:3a7713b1edbc 48 #endif
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 51 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /// @cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 /// @endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* **** Definitions **** */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @ingroup aes
AnnaBridge 171:3a7713b1edbc 75 * @defgroup aes_registers Registers
AnnaBridge 171:3a7713b1edbc 76 * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module.
AnnaBridge 171:3a7713b1edbc 77 * @{
AnnaBridge 171:3a7713b1edbc 78 */
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /**
AnnaBridge 171:3a7713b1edbc 81 * Structure type to access the AES Registers.
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> AES_CTRL Register */
AnnaBridge 171:3a7713b1edbc 85 __RO uint32_t rsv004; /**< <tt>\b 0x0004:</tt> RESERVED */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t erase_all; /**< <tt>\b 0x0008:</tt> AES_ERASE_ALL Register - A write to this register will trigger AES Memory Erase */
AnnaBridge 171:3a7713b1edbc 87 } mxc_aes_regs_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 /**
AnnaBridge 171:3a7713b1edbc 90 * Structure type to access the AES Memory Registers.
AnnaBridge 171:3a7713b1edbc 91 */
AnnaBridge 171:3a7713b1edbc 92 typedef struct {
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t inp[4]; /**< <tt>\b 0x0000-0x000C:</tt> AES Input (128 bits) */
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t key[8]; /**< <tt>\b 0x0010-0x002C:</tt> AES Symmetric Key (up to 256 bits) */
AnnaBridge 171:3a7713b1edbc 95 __IO uint32_t out[4]; /**< <tt>\b 0x0030-0x003C:</tt> AES Output Data (128 bits) */
AnnaBridge 171:3a7713b1edbc 96 __IO uint32_t expkey[8]; /**< <tt>\b 0x0040-0x005C:</tt> AES Expanded Key Data (256 bits) */
AnnaBridge 171:3a7713b1edbc 97 } mxc_aes_mem_regs_t;
AnnaBridge 171:3a7713b1edbc 98 /**@} end of group aes_registers */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /**
AnnaBridge 171:3a7713b1edbc 101 * @ingroup aes_registers
AnnaBridge 171:3a7713b1edbc 102 * @defgroup AES_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 103 * @brief AES Register Offsets from the AES Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 104 * @{
AnnaBridge 171:3a7713b1edbc 105 */
AnnaBridge 171:3a7713b1edbc 106 /**
AnnaBridge 171:3a7713b1edbc 107 * AES Register offsets from the AES base peripheral address.
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109 #define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 110 #define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 111 #define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 112 #define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 113 #define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 114 #define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 115 #define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0010</tt> */
AnnaBridge 171:3a7713b1edbc 116 #define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0014</tt> */
AnnaBridge 171:3a7713b1edbc 117 #define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0018</tt> */
AnnaBridge 171:3a7713b1edbc 118 #define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x001C</tt> */
AnnaBridge 171:3a7713b1edbc 119 #define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0020</tt> */
AnnaBridge 171:3a7713b1edbc 120 #define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0024</tt> */
AnnaBridge 171:3a7713b1edbc 121 #define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0028</tt> */
AnnaBridge 171:3a7713b1edbc 122 #define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x002C</tt> */
AnnaBridge 171:3a7713b1edbc 123 #define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0030</tt> */
AnnaBridge 171:3a7713b1edbc 124 #define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0034</tt> */
AnnaBridge 171:3a7713b1edbc 125 #define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0038</tt> */
AnnaBridge 171:3a7713b1edbc 126 #define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x003C</tt> */
AnnaBridge 171:3a7713b1edbc 127 #define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0040</tt> */
AnnaBridge 171:3a7713b1edbc 128 #define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0044</tt> */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0048</tt> */
AnnaBridge 171:3a7713b1edbc 130 #define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x004C</tt> */
AnnaBridge 171:3a7713b1edbc 131 #define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0050</tt> */
AnnaBridge 171:3a7713b1edbc 132 #define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0054</tt> */
AnnaBridge 171:3a7713b1edbc 133 #define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x0058</tt> */
AnnaBridge 171:3a7713b1edbc 134 #define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL) /**< Offset from the AES Base Peripheral Address: <tt>\b 0x005C</tt> */
AnnaBridge 171:3a7713b1edbc 135 /**@} end of group AES_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /**
AnnaBridge 171:3a7713b1edbc 138 * @ingroup aes_registers
AnnaBridge 171:3a7713b1edbc 139 * @defgroup AES_CTRL_Register AES_CTRL
AnnaBridge 171:3a7713b1edbc 140 * @brief Field Positions and Bit Masks for the AES_CTRL register
AnnaBridge 171:3a7713b1edbc 141 * @{
AnnaBridge 171:3a7713b1edbc 142 */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_AES_CTRL_START_POS 0 /**< AES_CTRL START Position */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS)) /**< AES_CTRL START Mask */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_AES_CTRL_CRYPT_MODE_POS 1 /**< AES_CTRL CRYPT_MODE Position */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL CRYPT_MODE Mask */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2 /**< AES_CTRL EXP_KEY_MODE Position */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL EXP_KEY_MODE Mask */
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_AES_CTRL_KEY_SIZE_POS 3 /**< AES_CTRL KEY_SIZE Position */
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL KEY_SIZE Mask */
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_AES_CTRL_INTEN_POS 5 /**< AES_CTRL INTEN Position */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS)) /**< AES_CTRL INTEN Mask */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_AES_CTRL_INTFL_POS 6 /**< AES_CTRL INTFL Position */
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS)) /**< AES_CTRL INTFL Mask */
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7 /**< AES_CTRL LOAD_HW_KEY Position */
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS)) /**< AES_CTRL LOAD_HW_KEY Mask */
AnnaBridge 171:3a7713b1edbc 157 /**@} end of aes_registers group */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /*
AnnaBridge 171:3a7713b1edbc 160 Field values and shifted values for module AES.
AnnaBridge 171:3a7713b1edbc 161 */
AnnaBridge 171:3a7713b1edbc 162 ///@cond
AnnaBridge 171:3a7713b1edbc 163 #define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode value */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode value */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 #define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Encryption Mode Shifted Value*/
AnnaBridge 171:3a7713b1edbc 167 #define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS)) /**< AES_CTRL: CRYPT_MODE Field: Decryption Mode Shifted Value*/
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 #define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key value */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key value */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 #define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Calculate New Exp Key Shifted Value*/
AnnaBridge 171:3a7713b1edbc 173 #define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS)) /**< AES_CTRL: EXP_KEY_MODE Field: Use previous Exp Key Shifted Value*/
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 #define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL)) /**< AES_CTRL: KEY_SIZE 128-bit setting value */
AnnaBridge 171:3a7713b1edbc 176 #define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL)) /**< AES_CTRL: KEY_SIZE 192-bit setting value */
AnnaBridge 171:3a7713b1edbc 177 #define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL)) /**< AES_CTRL: KEY_SIZE 256-bit setting value */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 #define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 128-bit Shifted Value */
AnnaBridge 171:3a7713b1edbc 180 #define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 192-bit Shifted Value */
AnnaBridge 171:3a7713b1edbc 181 #define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< AES_CTRL: KEY_SIZE 256-bit Shifted Value */
AnnaBridge 171:3a7713b1edbc 182 ///@endcond
AnnaBridge 171:3a7713b1edbc 183 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 184 }
AnnaBridge 171:3a7713b1edbc 185 #endif
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 #endif /* _MXC_AES_REGS_H_ */
AnnaBridge 171:3a7713b1edbc 188