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TARGET_MAX32620FTHR/TOOLCHAIN_GCC_ARM/i2cm_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_I2CM_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_I2CM_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 #define MXC_S_I2CM_TRANS_TAG_START 0x000
AnnaBridge 167:84c0a372a020 64 #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
AnnaBridge 167:84c0a372a020 65 #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
AnnaBridge 167:84c0a372a020 66 #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
AnnaBridge 167:84c0a372a020 67 #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
AnnaBridge 167:84c0a372a020 68 #define MXC_S_I2CM_TRANS_TAG_STOP 0x700
AnnaBridge 167:84c0a372a020 69 #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
AnnaBridge 167:84c0a372a020 70 #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
AnnaBridge 167:84c0a372a020 71
AnnaBridge 167:84c0a372a020 72 /*
AnnaBridge 167:84c0a372a020 73 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 74 access to each register in module.
AnnaBridge 167:84c0a372a020 75 */
AnnaBridge 167:84c0a372a020 76
AnnaBridge 167:84c0a372a020 77 /* Offset Register Description
AnnaBridge 167:84c0a372a020 78 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 79 typedef struct {
AnnaBridge 167:84c0a372a020 80 __IO uint32_t fs_clk_div; /* 0x0000 I2C Master Full Speed SCL Clock Settings */
AnnaBridge 167:84c0a372a020 81 __RO uint32_t rsv004[2]; /* 0x0004-0x0008 */
AnnaBridge 167:84c0a372a020 82 __IO uint32_t timeout; /* 0x000C I2C Master Timeout and Auto-Stop Settings */
AnnaBridge 167:84c0a372a020 83 __IO uint32_t ctrl; /* 0x0010 I2C Master Control Register */
AnnaBridge 167:84c0a372a020 84 __IO uint32_t trans; /* 0x0014 I2C Master Transaction Start and Status Flags */
AnnaBridge 167:84c0a372a020 85 __IO uint32_t intfl; /* 0x0018 I2C Master Interrupt Flags */
AnnaBridge 167:84c0a372a020 86 __IO uint32_t inten; /* 0x001C I2C Master Interrupt Enable/Disable Controls */
AnnaBridge 167:84c0a372a020 87 __RO uint32_t rsv020[2]; /* 0x0020-0x0024 */
AnnaBridge 167:84c0a372a020 88 __IO uint32_t bb; /* 0x0028 I2C Master Bit-Bang Control Register */
AnnaBridge 167:84c0a372a020 89 } mxc_i2cm_regs_t;
AnnaBridge 167:84c0a372a020 90
AnnaBridge 167:84c0a372a020 91
AnnaBridge 167:84c0a372a020 92 /* Offset Register Description
AnnaBridge 167:84c0a372a020 93 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 94 typedef struct {
AnnaBridge 167:84c0a372a020 95 union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */
AnnaBridge 167:84c0a372a020 96 __IO uint16_t tx;
AnnaBridge 167:84c0a372a020 97 __IO uint8_t tx_8[2048];
AnnaBridge 167:84c0a372a020 98 __IO uint16_t tx_16[1024];
AnnaBridge 167:84c0a372a020 99 __IO uint32_t tx_32[512];
AnnaBridge 167:84c0a372a020 100 };
AnnaBridge 167:84c0a372a020 101 union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */
AnnaBridge 167:84c0a372a020 102 __IO uint16_t rx;
AnnaBridge 167:84c0a372a020 103 __IO uint8_t rx_8[2048];
AnnaBridge 167:84c0a372a020 104 __IO uint16_t rx_16[1024];
AnnaBridge 167:84c0a372a020 105 __IO uint32_t rx_32[512];
AnnaBridge 167:84c0a372a020 106 };
AnnaBridge 167:84c0a372a020 107 } mxc_i2cm_fifo_regs_t;
AnnaBridge 167:84c0a372a020 108
AnnaBridge 167:84c0a372a020 109
AnnaBridge 167:84c0a372a020 110 /*
AnnaBridge 167:84c0a372a020 111 Register offsets for module I2CM.
AnnaBridge 167:84c0a372a020 112 */
AnnaBridge 167:84c0a372a020 113
AnnaBridge 167:84c0a372a020 114 #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 115 #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 116 #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 117 #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
AnnaBridge 167:84c0a372a020 118 #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
AnnaBridge 167:84c0a372a020 119 #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
AnnaBridge 167:84c0a372a020 120 #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
AnnaBridge 167:84c0a372a020 121 #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 122 #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
AnnaBridge 167:84c0a372a020 123
AnnaBridge 167:84c0a372a020 124
AnnaBridge 167:84c0a372a020 125 /*
AnnaBridge 167:84c0a372a020 126 Field positions and masks for module I2CM.
AnnaBridge 167:84c0a372a020 127 */
AnnaBridge 167:84c0a372a020 128
AnnaBridge 167:84c0a372a020 129 #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0
AnnaBridge 167:84c0a372a020 130 #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS))
AnnaBridge 167:84c0a372a020 131 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8
AnnaBridge 167:84c0a372a020 132 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS))
AnnaBridge 167:84c0a372a020 133 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20
AnnaBridge 167:84c0a372a020 134 #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS))
AnnaBridge 167:84c0a372a020 135
AnnaBridge 167:84c0a372a020 136 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
AnnaBridge 167:84c0a372a020 137 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
AnnaBridge 167:84c0a372a020 138 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
AnnaBridge 167:84c0a372a020 139 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
AnnaBridge 167:84c0a372a020 140
AnnaBridge 167:84c0a372a020 141 #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
AnnaBridge 167:84c0a372a020 142 #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 143 #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
AnnaBridge 167:84c0a372a020 144 #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 145 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
AnnaBridge 167:84c0a372a020 146 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
AnnaBridge 167:84c0a372a020 147
AnnaBridge 167:84c0a372a020 148 #define MXC_F_I2CM_TRANS_TX_START_POS 0
AnnaBridge 167:84c0a372a020 149 #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
AnnaBridge 167:84c0a372a020 150 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
AnnaBridge 167:84c0a372a020 151 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
AnnaBridge 167:84c0a372a020 152 #define MXC_F_I2CM_TRANS_TX_DONE_POS 2
AnnaBridge 167:84c0a372a020 153 #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
AnnaBridge 167:84c0a372a020 154 #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
AnnaBridge 167:84c0a372a020 155 #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
AnnaBridge 167:84c0a372a020 157 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
AnnaBridge 167:84c0a372a020 158 #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
AnnaBridge 167:84c0a372a020 159 #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
AnnaBridge 167:84c0a372a020 160
AnnaBridge 167:84c0a372a020 161 #define MXC_F_I2CM_INTFL_TX_DONE_POS 0
AnnaBridge 167:84c0a372a020 162 #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
AnnaBridge 167:84c0a372a020 163 #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
AnnaBridge 167:84c0a372a020 164 #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
AnnaBridge 167:84c0a372a020 165 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
AnnaBridge 167:84c0a372a020 166 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
AnnaBridge 167:84c0a372a020 167 #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
AnnaBridge 167:84c0a372a020 168 #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
AnnaBridge 167:84c0a372a020 169 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
AnnaBridge 167:84c0a372a020 170 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
AnnaBridge 167:84c0a372a020 171 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
AnnaBridge 167:84c0a372a020 172 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
AnnaBridge 167:84c0a372a020 173 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
AnnaBridge 167:84c0a372a020 174 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
AnnaBridge 167:84c0a372a020 175 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
AnnaBridge 167:84c0a372a020 176 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
AnnaBridge 167:84c0a372a020 177 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
AnnaBridge 167:84c0a372a020 178 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
AnnaBridge 167:84c0a372a020 179 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
AnnaBridge 167:84c0a372a020 180 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
AnnaBridge 167:84c0a372a020 181
AnnaBridge 167:84c0a372a020 182 #define MXC_F_I2CM_INTEN_TX_DONE_POS 0
AnnaBridge 167:84c0a372a020 183 #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
AnnaBridge 167:84c0a372a020 184 #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
AnnaBridge 167:84c0a372a020 185 #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
AnnaBridge 167:84c0a372a020 186 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
AnnaBridge 167:84c0a372a020 187 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
AnnaBridge 167:84c0a372a020 188 #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
AnnaBridge 167:84c0a372a020 189 #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
AnnaBridge 167:84c0a372a020 190 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
AnnaBridge 167:84c0a372a020 191 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
AnnaBridge 167:84c0a372a020 192 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
AnnaBridge 167:84c0a372a020 193 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
AnnaBridge 167:84c0a372a020 194 #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6
AnnaBridge 167:84c0a372a020 195 #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS))
AnnaBridge 167:84c0a372a020 196 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
AnnaBridge 167:84c0a372a020 197 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
AnnaBridge 167:84c0a372a020 198 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
AnnaBridge 167:84c0a372a020 199 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
AnnaBridge 167:84c0a372a020 200 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
AnnaBridge 167:84c0a372a020 201 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
AnnaBridge 167:84c0a372a020 202
AnnaBridge 167:84c0a372a020 203 #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
AnnaBridge 167:84c0a372a020 204 #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
AnnaBridge 167:84c0a372a020 205 #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
AnnaBridge 167:84c0a372a020 206 #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
AnnaBridge 167:84c0a372a020 207 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
AnnaBridge 167:84c0a372a020 208 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
AnnaBridge 167:84c0a372a020 209 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
AnnaBridge 167:84c0a372a020 210 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
AnnaBridge 167:84c0a372a020 211 #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
AnnaBridge 167:84c0a372a020 212 #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
AnnaBridge 167:84c0a372a020 213
AnnaBridge 167:84c0a372a020 214
AnnaBridge 167:84c0a372a020 215
AnnaBridge 167:84c0a372a020 216 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 217 }
AnnaBridge 167:84c0a372a020 218 #endif
AnnaBridge 167:84c0a372a020 219
AnnaBridge 167:84c0a372a020 220 #endif /* _MXC_I2CM_REGS_H_ */
AnnaBridge 167:84c0a372a020 221