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TARGET_LPC4337/TOOLCHAIN_ARM_STD/LPC43xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/*
AnnaBridge	171:3a7713b1edbc	2	* LPC43xx/LPC18xx MCU header
AnnaBridge	171:3a7713b1edbc	3	*
AnnaBridge	171:3a7713b1edbc	4	* Copyright(C) NXP Semiconductors, 2012
AnnaBridge	171:3a7713b1edbc	5	* All rights reserved.
AnnaBridge	171:3a7713b1edbc	6	*
AnnaBridge	171:3a7713b1edbc	7	* Software that is described herein is for illustrative purposes only
AnnaBridge	171:3a7713b1edbc	8	* which provides customers with programming information regarding the
AnnaBridge	171:3a7713b1edbc	9	* LPC products. This software is supplied "AS IS" without any warranties of
AnnaBridge	171:3a7713b1edbc	10	* any kind, and NXP Semiconductors and its licensor disclaim any and
AnnaBridge	171:3a7713b1edbc	11	* all warranties, express or implied, including all implied warranties of
AnnaBridge	171:3a7713b1edbc	12	* merchantability, fitness for a particular purpose and non-infringement of
AnnaBridge	171:3a7713b1edbc	13	* intellectual property rights. NXP Semiconductors assumes no responsibility
AnnaBridge	171:3a7713b1edbc	14	* or liability for the use of the software, conveys no license or rights under any
AnnaBridge	171:3a7713b1edbc	15	* patent, copyright, mask work right, or any other intellectual property rights in
AnnaBridge	171:3a7713b1edbc	16	* or to any products. NXP Semiconductors reserves the right to make changes
AnnaBridge	171:3a7713b1edbc	17	* in the software without notification. NXP Semiconductors also makes no
AnnaBridge	171:3a7713b1edbc	18	* representation or warranty that such application will be suitable for the
AnnaBridge	171:3a7713b1edbc	19	* specified use without further testing or modification.
AnnaBridge	171:3a7713b1edbc	20	*
AnnaBridge	171:3a7713b1edbc	21	* Permission to use, copy, modify, and distribute this software and its
AnnaBridge	171:3a7713b1edbc	22	* documentation is hereby granted, under NXP Semiconductors' and its
AnnaBridge	171:3a7713b1edbc	23	* licensor's relevant copyrights in the software, without fee, provided that it
AnnaBridge	171:3a7713b1edbc	24	* is used in conjunction with NXP Semiconductors microcontrollers. This
AnnaBridge	171:3a7713b1edbc	25	* copyright, permission, and disclaimer notice must appear in all copies of
AnnaBridge	171:3a7713b1edbc	26	* this code.
AnnaBridge	171:3a7713b1edbc	27	*
AnnaBridge	171:3a7713b1edbc	28	* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
AnnaBridge	171:3a7713b1edbc	29	* 05/15/13 Micromint USA <support@micromint.com>
AnnaBridge	171:3a7713b1edbc	30	*/
AnnaBridge	171:3a7713b1edbc	31
AnnaBridge	171:3a7713b1edbc	32	#ifndef __LPC43XX_H
AnnaBridge	171:3a7713b1edbc	33	#define __LPC43XX_H
AnnaBridge	171:3a7713b1edbc	34
AnnaBridge	171:3a7713b1edbc	35	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	36	extern "C" {
AnnaBridge	171:3a7713b1edbc	37	#endif
AnnaBridge	171:3a7713b1edbc	38
AnnaBridge	171:3a7713b1edbc	39	/* Treat __CORE_Mx as CORE_Mx */
AnnaBridge	171:3a7713b1edbc	40	#if defined(__CORTEX_M0) && !defined(CORE_M0)
AnnaBridge	171:3a7713b1edbc	41	#define CORE_M0
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43	#if defined(__CORTEX_M3) && !defined(CORE_M3)
AnnaBridge	171:3a7713b1edbc	44	#define CORE_M3
AnnaBridge	171:3a7713b1edbc	45	#endif
AnnaBridge	171:3a7713b1edbc	46	/* Default to M4 core if no core explicitly declared */
AnnaBridge	171:3a7713b1edbc	47	#if !defined(CORE_M0) && !defined(CORE_M3)
AnnaBridge	171:3a7713b1edbc	48	#define CORE_M4
AnnaBridge	171:3a7713b1edbc	49	#endif
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/* Define LPC18XX or LPC43XX according to core type */
AnnaBridge	171:3a7713b1edbc	52	#if (defined(CORE_M4) \|\| defined(CORE_M0)) && !defined(__LPC43XX__)
AnnaBridge	171:3a7713b1edbc	53	#define __LPC43XX__
AnnaBridge	171:3a7713b1edbc	54	#endif
AnnaBridge	171:3a7713b1edbc	55	#if defined(CORE_M3) && !defined(__LPC18XX__)
AnnaBridge	171:3a7713b1edbc	56	#define __LPC18XX__
AnnaBridge	171:3a7713b1edbc	57	#endif
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	/* Start of section using anonymous unions */
AnnaBridge	171:3a7713b1edbc	60	#if defined(__ARMCC_VERSION)
AnnaBridge	171:3a7713b1edbc	61	// Kill warning "#pragma push with no matching #pragma pop"
AnnaBridge	171:3a7713b1edbc	62	#pragma diag_suppress 2525
AnnaBridge	171:3a7713b1edbc	63	#pragma push
AnnaBridge	171:3a7713b1edbc	64	#pragma anon_unions
AnnaBridge	171:3a7713b1edbc	65	#elif defined(__CWCC__)
AnnaBridge	171:3a7713b1edbc	66	#pragma push
AnnaBridge	171:3a7713b1edbc	67	#pragma cpp_extensions on
AnnaBridge	171:3a7713b1edbc	68	#elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge	171:3a7713b1edbc	69	//#pragma push // FIXME not usable for IAR
AnnaBridge	171:3a7713b1edbc	70	#pragma language=extended
AnnaBridge	171:3a7713b1edbc	71	#else /* defined(__GNUC__) and others */
AnnaBridge	171:3a7713b1edbc	72	/* Assume anonymous unions are enabled by default */
AnnaBridge	171:3a7713b1edbc	73	#endif
AnnaBridge	171:3a7713b1edbc	74
AnnaBridge	171:3a7713b1edbc	75	#if defined(CORE_M4)
AnnaBridge	171:3a7713b1edbc	76	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	77	* LPC43xx (M4 Core) Cortex CMSIS definitions
AnnaBridge	171:3a7713b1edbc	78	*/
AnnaBridge	171:3a7713b1edbc	79
AnnaBridge	171:3a7713b1edbc	80	#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
AnnaBridge	171:3a7713b1edbc	81	#define __MPU_PRESENT 1 /* MPU present or not */
AnnaBridge	171:3a7713b1edbc	82	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
AnnaBridge	171:3a7713b1edbc	83	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
AnnaBridge	171:3a7713b1edbc	84	#define __FPU_PRESENT 1 /* FPU present or not */
AnnaBridge	171:3a7713b1edbc	85	#define CHIP_LPC43XX /* LPCOPEN compatibility */
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	88	* LPC43xx peripheral interrupt numbers
AnnaBridge	171:3a7713b1edbc	89	*/
AnnaBridge	171:3a7713b1edbc	90
AnnaBridge	171:3a7713b1edbc	91	typedef enum {
AnnaBridge	171:3a7713b1edbc	92	/* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
AnnaBridge	171:3a7713b1edbc	93	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
AnnaBridge	171:3a7713b1edbc	94	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
AnnaBridge	171:3a7713b1edbc	95	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
AnnaBridge	171:3a7713b1edbc	96	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
AnnaBridge	171:3a7713b1edbc	97	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
AnnaBridge	171:3a7713b1edbc	98	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
AnnaBridge	171:3a7713b1edbc	99	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
AnnaBridge	171:3a7713b1edbc	100	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
AnnaBridge	171:3a7713b1edbc	101	PendSV_IRQn = -2,/* 14 Pendable request for system service */
AnnaBridge	171:3a7713b1edbc	102	SysTick_IRQn = -1,/* 15 System Tick Timer */
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
AnnaBridge	171:3a7713b1edbc	105	DAC_IRQn = 0,/* 0 DAC */
AnnaBridge	171:3a7713b1edbc	106	M0CORE_IRQn = 1,/* 1 M0a */
AnnaBridge	171:3a7713b1edbc	107	DMA_IRQn = 2,/* 2 DMA */
AnnaBridge	171:3a7713b1edbc	108	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
AnnaBridge	171:3a7713b1edbc	109	RESERVED2_IRQn = 4,
AnnaBridge	171:3a7713b1edbc	110	ETHERNET_IRQn = 5,/* 5 ETHERNET */
AnnaBridge	171:3a7713b1edbc	111	SDIO_IRQn = 6,/* 6 SDIO */
AnnaBridge	171:3a7713b1edbc	112	LCD_IRQn = 7,/* 7 LCD */
AnnaBridge	171:3a7713b1edbc	113	USB0_IRQn = 8,/* 8 USB0 */
AnnaBridge	171:3a7713b1edbc	114	USB1_IRQn = 9,/* 9 USB1 */
AnnaBridge	171:3a7713b1edbc	115	SCT_IRQn = 10,/* 10 SCT */
AnnaBridge	171:3a7713b1edbc	116	RITIMER_IRQn = 11,/* 11 RITIMER */
AnnaBridge	171:3a7713b1edbc	117	TIMER0_IRQn = 12,/* 12 TIMER0 */
AnnaBridge	171:3a7713b1edbc	118	TIMER1_IRQn = 13,/* 13 TIMER1 */
AnnaBridge	171:3a7713b1edbc	119	TIMER2_IRQn = 14,/* 14 TIMER2 */
AnnaBridge	171:3a7713b1edbc	120	TIMER3_IRQn = 15,/* 15 TIMER3 */
AnnaBridge	171:3a7713b1edbc	121	MCPWM_IRQn = 16,/* 16 MCPWM */
AnnaBridge	171:3a7713b1edbc	122	ADC0_IRQn = 17,/* 17 ADC0 */
AnnaBridge	171:3a7713b1edbc	123	I2C0_IRQn = 18,/* 18 I2C0 */
AnnaBridge	171:3a7713b1edbc	124	I2C1_IRQn = 19,/* 19 I2C1 */
AnnaBridge	171:3a7713b1edbc	125	SPI_INT_IRQn = 20,/* 20 SPI_INT */
AnnaBridge	171:3a7713b1edbc	126	ADC1_IRQn = 21,/* 21 ADC1 */
AnnaBridge	171:3a7713b1edbc	127	SSP0_IRQn = 22,/* 22 SSP0 */
AnnaBridge	171:3a7713b1edbc	128	SSP1_IRQn = 23,/* 23 SSP1 */
AnnaBridge	171:3a7713b1edbc	129	USART0_IRQn = 24,/* 24 USART0 */
AnnaBridge	171:3a7713b1edbc	130	UART1_IRQn = 25,/* 25 UART1 */
AnnaBridge	171:3a7713b1edbc	131	USART2_IRQn = 26,/* 26 USART2 */
AnnaBridge	171:3a7713b1edbc	132	USART3_IRQn = 27,/* 27 USART3 */
AnnaBridge	171:3a7713b1edbc	133	I2S0_IRQn = 28,/* 28 I2S0 */
AnnaBridge	171:3a7713b1edbc	134	I2S1_IRQn = 29,/* 29 I2S1 */
AnnaBridge	171:3a7713b1edbc	135	RESERVED4_IRQn = 30,
AnnaBridge	171:3a7713b1edbc	136	SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
AnnaBridge	171:3a7713b1edbc	137	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
AnnaBridge	171:3a7713b1edbc	138	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
AnnaBridge	171:3a7713b1edbc	139	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
AnnaBridge	171:3a7713b1edbc	140	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
AnnaBridge	171:3a7713b1edbc	141	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
AnnaBridge	171:3a7713b1edbc	142	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
AnnaBridge	171:3a7713b1edbc	143	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
AnnaBridge	171:3a7713b1edbc	144	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
AnnaBridge	171:3a7713b1edbc	145	GINT0_IRQn = 40,/* 40 GINT0 */
AnnaBridge	171:3a7713b1edbc	146	GINT1_IRQn = 41,/* 41 GINT1 */
AnnaBridge	171:3a7713b1edbc	147	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
AnnaBridge	171:3a7713b1edbc	148	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
AnnaBridge	171:3a7713b1edbc	149	RESERVED6_IRQn = 44,
AnnaBridge	171:3a7713b1edbc	150	RESERVED7_IRQn = 45,/* 45 VADC */
AnnaBridge	171:3a7713b1edbc	151	ATIMER_IRQn = 46,/* 46 ATIMER */
AnnaBridge	171:3a7713b1edbc	152	RTC_IRQn = 47,/* 47 RTC */
AnnaBridge	171:3a7713b1edbc	153	RESERVED8_IRQn = 48,
AnnaBridge	171:3a7713b1edbc	154	WWDT_IRQn = 49,/* 49 WWDT */
AnnaBridge	171:3a7713b1edbc	155	RESERVED9_IRQn = 50,
AnnaBridge	171:3a7713b1edbc	156	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
AnnaBridge	171:3a7713b1edbc	157	QEI_IRQn = 52,/* 52 QEI */
AnnaBridge	171:3a7713b1edbc	158	} IRQn_Type;
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge	171:3a7713b1edbc	161
AnnaBridge	171:3a7713b1edbc	162	#elif defined(CORE_M3)
AnnaBridge	171:3a7713b1edbc	163	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	164	* LPC18xx (M3 Core) Cortex CMSIS definitions
AnnaBridge	171:3a7713b1edbc	165	*/
AnnaBridge	171:3a7713b1edbc	166	#define __MPU_PRESENT 1 /* MPU present or not */
AnnaBridge	171:3a7713b1edbc	167	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
AnnaBridge	171:3a7713b1edbc	168	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
AnnaBridge	171:3a7713b1edbc	169	#define __FPU_PRESENT 0 /* FPU present or not */
AnnaBridge	171:3a7713b1edbc	170	#define CHIP_LPC18XX /* LPCOPEN compatibility */
AnnaBridge	171:3a7713b1edbc	171
AnnaBridge	171:3a7713b1edbc	172	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	173	* LPC18xx peripheral interrupt numbers
AnnaBridge	171:3a7713b1edbc	174	*/
AnnaBridge	171:3a7713b1edbc	175
AnnaBridge	171:3a7713b1edbc	176	typedef enum {
AnnaBridge	171:3a7713b1edbc	177	/* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
AnnaBridge	171:3a7713b1edbc	178	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
AnnaBridge	171:3a7713b1edbc	179	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
AnnaBridge	171:3a7713b1edbc	180	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
AnnaBridge	171:3a7713b1edbc	181	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
AnnaBridge	171:3a7713b1edbc	182	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
AnnaBridge	171:3a7713b1edbc	183	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
AnnaBridge	171:3a7713b1edbc	184	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
AnnaBridge	171:3a7713b1edbc	185	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
AnnaBridge	171:3a7713b1edbc	186	PendSV_IRQn = -2,/* 14 Pendable request for system service */
AnnaBridge	171:3a7713b1edbc	187	SysTick_IRQn = -1,/* 15 System Tick Timer */
AnnaBridge	171:3a7713b1edbc	188
AnnaBridge	171:3a7713b1edbc	189	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
AnnaBridge	171:3a7713b1edbc	190	DAC_IRQn = 0,/* 0 DAC */
AnnaBridge	171:3a7713b1edbc	191	RESERVED0_IRQn = 1,
AnnaBridge	171:3a7713b1edbc	192	DMA_IRQn = 2,/* 2 DMA */
AnnaBridge	171:3a7713b1edbc	193	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
AnnaBridge	171:3a7713b1edbc	194	RESERVED2_IRQn = 4,
AnnaBridge	171:3a7713b1edbc	195	ETHERNET_IRQn = 5,/* 5 ETHERNET */
AnnaBridge	171:3a7713b1edbc	196	SDIO_IRQn = 6,/* 6 SDIO */
AnnaBridge	171:3a7713b1edbc	197	LCD_IRQn = 7,/* 7 LCD */
AnnaBridge	171:3a7713b1edbc	198	USB0_IRQn = 8,/* 8 USB0 */
AnnaBridge	171:3a7713b1edbc	199	USB1_IRQn = 9,/* 9 USB1 */
AnnaBridge	171:3a7713b1edbc	200	SCT_IRQn = 10,/* 10 SCT */
AnnaBridge	171:3a7713b1edbc	201	RITIMER_IRQn = 11,/* 11 RITIMER */
AnnaBridge	171:3a7713b1edbc	202	TIMER0_IRQn = 12,/* 12 TIMER0 */
AnnaBridge	171:3a7713b1edbc	203	TIMER1_IRQn = 13,/* 13 TIMER1 */
AnnaBridge	171:3a7713b1edbc	204	TIMER2_IRQn = 14,/* 14 TIMER2 */
AnnaBridge	171:3a7713b1edbc	205	TIMER3_IRQn = 15,/* 15 TIMER3 */
AnnaBridge	171:3a7713b1edbc	206	MCPWM_IRQn = 16,/* 16 MCPWM */
AnnaBridge	171:3a7713b1edbc	207	ADC0_IRQn = 17,/* 17 ADC0 */
AnnaBridge	171:3a7713b1edbc	208	I2C0_IRQn = 18,/* 18 I2C0 */
AnnaBridge	171:3a7713b1edbc	209	I2C1_IRQn = 19,/* 19 I2C1 */
AnnaBridge	171:3a7713b1edbc	210	RESERVED3_IRQn = 20,
AnnaBridge	171:3a7713b1edbc	211	ADC1_IRQn = 21,/* 21 ADC1 */
AnnaBridge	171:3a7713b1edbc	212	SSP0_IRQn = 22,/* 22 SSP0 */
AnnaBridge	171:3a7713b1edbc	213	SSP1_IRQn = 23,/* 23 SSP1 */
AnnaBridge	171:3a7713b1edbc	214	USART0_IRQn = 24,/* 24 USART0 */
AnnaBridge	171:3a7713b1edbc	215	UART1_IRQn = 25,/* 25 UART1 */
AnnaBridge	171:3a7713b1edbc	216	USART2_IRQn = 26,/* 26 USART2 */
AnnaBridge	171:3a7713b1edbc	217	USART3_IRQn = 27,/* 27 USART3 */
AnnaBridge	171:3a7713b1edbc	218	I2S0_IRQn = 28,/* 28 I2S0 */
AnnaBridge	171:3a7713b1edbc	219	I2S1_IRQn = 29,/* 29 I2S1 */
AnnaBridge	171:3a7713b1edbc	220	RESERVED4_IRQn = 30,
AnnaBridge	171:3a7713b1edbc	221	RESERVED5_IRQn = 31,
AnnaBridge	171:3a7713b1edbc	222	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
AnnaBridge	171:3a7713b1edbc	223	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
AnnaBridge	171:3a7713b1edbc	224	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
AnnaBridge	171:3a7713b1edbc	225	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
AnnaBridge	171:3a7713b1edbc	226	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
AnnaBridge	171:3a7713b1edbc	227	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
AnnaBridge	171:3a7713b1edbc	228	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
AnnaBridge	171:3a7713b1edbc	229	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
AnnaBridge	171:3a7713b1edbc	230	GINT0_IRQn = 40,/* 40 GINT0 */
AnnaBridge	171:3a7713b1edbc	231	GINT1_IRQn = 41,/* 41 GINT1 */
AnnaBridge	171:3a7713b1edbc	232	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
AnnaBridge	171:3a7713b1edbc	233	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
AnnaBridge	171:3a7713b1edbc	234	RESERVED6_IRQn = 44,
AnnaBridge	171:3a7713b1edbc	235	RESERVED7_IRQn = 45,/* 45 VADC */
AnnaBridge	171:3a7713b1edbc	236	ATIMER_IRQn = 46,/* 46 ATIMER */
AnnaBridge	171:3a7713b1edbc	237	RTC_IRQn = 47,/* 47 RTC */
AnnaBridge	171:3a7713b1edbc	238	RESERVED8_IRQn = 48,
AnnaBridge	171:3a7713b1edbc	239	WWDT_IRQn = 49,/* 49 WWDT */
AnnaBridge	171:3a7713b1edbc	240	RESERVED9_IRQn = 50,
AnnaBridge	171:3a7713b1edbc	241	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
AnnaBridge	171:3a7713b1edbc	242	QEI_IRQn = 52,/* 52 QEI */
AnnaBridge	171:3a7713b1edbc	243	} IRQn_Type;
AnnaBridge	171:3a7713b1edbc	244
AnnaBridge	171:3a7713b1edbc	245	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	#elif defined(CORE_M0)
AnnaBridge	171:3a7713b1edbc	248	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	249	* LPC43xx (M0 Core) Cortex CMSIS definitions
AnnaBridge	171:3a7713b1edbc	250	*/
AnnaBridge	171:3a7713b1edbc	251
AnnaBridge	171:3a7713b1edbc	252	#define __MPU_PRESENT 0 /* MPU present or not */
AnnaBridge	171:3a7713b1edbc	253	#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
AnnaBridge	171:3a7713b1edbc	254	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
AnnaBridge	171:3a7713b1edbc	255	#define __FPU_PRESENT 0 /* FPU present or not */
AnnaBridge	171:3a7713b1edbc	256	#define CHIP_LPC43XX /* LPCOPEN compatibility */
AnnaBridge	171:3a7713b1edbc	257
AnnaBridge	171:3a7713b1edbc	258	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	259	* LPC43xx (M0 Core) peripheral interrupt numbers
AnnaBridge	171:3a7713b1edbc	260	*/
AnnaBridge	171:3a7713b1edbc	261
AnnaBridge	171:3a7713b1edbc	262	typedef enum {
AnnaBridge	171:3a7713b1edbc	263	/* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
AnnaBridge	171:3a7713b1edbc	264	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
AnnaBridge	171:3a7713b1edbc	265	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
AnnaBridge	171:3a7713b1edbc	266	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
AnnaBridge	171:3a7713b1edbc	267	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
AnnaBridge	171:3a7713b1edbc	268	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
AnnaBridge	171:3a7713b1edbc	269	PendSV_IRQn = -2,/* 14 Pendable request for system service */
AnnaBridge	171:3a7713b1edbc	270	SysTick_IRQn = -1,/* 15 System Tick Timer */
AnnaBridge	171:3a7713b1edbc	271
AnnaBridge	171:3a7713b1edbc	272	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
AnnaBridge	171:3a7713b1edbc	273	DAC_IRQn = 0,/* 0 DAC */
AnnaBridge	171:3a7713b1edbc	274	M0_M4CORE_IRQn = 1,/* 1 M0a */
AnnaBridge	171:3a7713b1edbc	275	DMA_IRQn = 2,/* 2 DMA r */
AnnaBridge	171:3a7713b1edbc	276	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
AnnaBridge	171:3a7713b1edbc	277	FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
AnnaBridge	171:3a7713b1edbc	278	ETHERNET_IRQn = 5,/* 5 ETHERNET */
AnnaBridge	171:3a7713b1edbc	279	SDIO_IRQn = 6,/* 6 SDIO */
AnnaBridge	171:3a7713b1edbc	280	LCD_IRQn = 7,/* 7 LCD */
AnnaBridge	171:3a7713b1edbc	281	USB0_IRQn = 8,/* 8 USB0 */
AnnaBridge	171:3a7713b1edbc	282	USB1_IRQn = 9,/* 9 USB1 */
AnnaBridge	171:3a7713b1edbc	283	SCT_IRQn = 10,/* 10 SCT */
AnnaBridge	171:3a7713b1edbc	284	RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
AnnaBridge	171:3a7713b1edbc	285	TIMER0_IRQn = 12,/* 12 TIMER0 */
AnnaBridge	171:3a7713b1edbc	286	GINT1_IRQn = 13,/* 13 GINT1 */
AnnaBridge	171:3a7713b1edbc	287	PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
AnnaBridge	171:3a7713b1edbc	288	TIMER3_IRQn = 15,/* 15 TIMER3 */
AnnaBridge	171:3a7713b1edbc	289	MCPWM_IRQn = 16,/* 16 MCPWM */
AnnaBridge	171:3a7713b1edbc	290	ADC0_IRQn = 17,/* 17 ADC0 */
AnnaBridge	171:3a7713b1edbc	291	I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
AnnaBridge	171:3a7713b1edbc	292	SGPIO_INT_IRQn = 19,/* 19 SGPIO */
AnnaBridge	171:3a7713b1edbc	293	SPI_INT_IRQn = 20,/* 20 SPI_INT */
AnnaBridge	171:3a7713b1edbc	294	ADC1_IRQn = 21,/* 21 ADC1 */
AnnaBridge	171:3a7713b1edbc	295	SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
AnnaBridge	171:3a7713b1edbc	296	EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
AnnaBridge	171:3a7713b1edbc	297	USART0_IRQn = 24,/* 24 USART0 */
AnnaBridge	171:3a7713b1edbc	298	UART1_IRQn = 25,/* 25 UART1 */
AnnaBridge	171:3a7713b1edbc	299	USART2_IRQn = 26,/* 26 USART2 */
AnnaBridge	171:3a7713b1edbc	300	USART3_IRQn = 27,/* 27 USART3 */
AnnaBridge	171:3a7713b1edbc	301	I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
AnnaBridge	171:3a7713b1edbc	302	C_CAN0_IRQn = 29,/* 29 C_CAN0 */
AnnaBridge	171:3a7713b1edbc	303	I2S1_IRQn = 29,/* 29 I2S1 */
AnnaBridge	171:3a7713b1edbc	304	RESERVED2_IRQn = 30,
AnnaBridge	171:3a7713b1edbc	305	RESERVED3_IRQn = 31,
AnnaBridge	171:3a7713b1edbc	306	} IRQn_Type;
AnnaBridge	171:3a7713b1edbc	307
AnnaBridge	171:3a7713b1edbc	308	#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge	171:3a7713b1edbc	309	#else
AnnaBridge	171:3a7713b1edbc	310	#error Please #define CORE_M0, CORE_M3 or CORE_M4
AnnaBridge	171:3a7713b1edbc	311	#endif
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	#include "system_LPC43xx.h"
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	316	* State Configurable Timer register block structure
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318	#define LPC_SCT_BASE 0x40000000
AnnaBridge	171:3a7713b1edbc	319	#define CONFIG_SCT_nEV (16) /* Number of events */
AnnaBridge	171:3a7713b1edbc	320	#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
AnnaBridge	171:3a7713b1edbc	321	#define CONFIG_SCT_nOU (16) /* Number of outputs */
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	typedef struct {
AnnaBridge	171:3a7713b1edbc	324	__IO uint32_t CONFIG; /* Configuration Register */
AnnaBridge	171:3a7713b1edbc	325	union {
AnnaBridge	171:3a7713b1edbc	326	__IO uint32_t CTRL_U; /* Control Register */
AnnaBridge	171:3a7713b1edbc	327	struct {
AnnaBridge	171:3a7713b1edbc	328	__IO uint16_t CTRL_L; /* Low control register */
AnnaBridge	171:3a7713b1edbc	329	__IO uint16_t CTRL_H; /* High control register */
AnnaBridge	171:3a7713b1edbc	330	};
AnnaBridge	171:3a7713b1edbc	331
AnnaBridge	171:3a7713b1edbc	332	};
AnnaBridge	171:3a7713b1edbc	333
AnnaBridge	171:3a7713b1edbc	334	__IO uint16_t LIMIT_L; /* limit register for counter L */
AnnaBridge	171:3a7713b1edbc	335	__IO uint16_t LIMIT_H; /* limit register for counter H */
AnnaBridge	171:3a7713b1edbc	336	__IO uint16_t HALT_L; /* halt register for counter L */
AnnaBridge	171:3a7713b1edbc	337	__IO uint16_t HALT_H; /* halt register for counter H */
AnnaBridge	171:3a7713b1edbc	338	__IO uint16_t STOP_L; /* stop register for counter L */
AnnaBridge	171:3a7713b1edbc	339	__IO uint16_t STOP_H; /* stop register for counter H */
AnnaBridge	171:3a7713b1edbc	340	__IO uint16_t START_L; /* start register for counter L */
AnnaBridge	171:3a7713b1edbc	341	__IO uint16_t START_H; /* start register for counter H */
AnnaBridge	171:3a7713b1edbc	342	uint32_t RESERVED1[10]; /* 0x03C reserved */
AnnaBridge	171:3a7713b1edbc	343	union {
AnnaBridge	171:3a7713b1edbc	344	__IO uint32_t COUNT_U; /* counter register */
AnnaBridge	171:3a7713b1edbc	345	struct {
AnnaBridge	171:3a7713b1edbc	346	__IO uint16_t COUNT_L; /* counter register for counter L */
AnnaBridge	171:3a7713b1edbc	347	__IO uint16_t COUNT_H; /* counter register for counter H */
AnnaBridge	171:3a7713b1edbc	348	};
AnnaBridge	171:3a7713b1edbc	349
AnnaBridge	171:3a7713b1edbc	350	};
AnnaBridge	171:3a7713b1edbc	351
AnnaBridge	171:3a7713b1edbc	352	__IO uint16_t STATE_L; /* state register for counter L */
AnnaBridge	171:3a7713b1edbc	353	__IO uint16_t STATE_H; /* state register for counter H */
AnnaBridge	171:3a7713b1edbc	354	__I uint32_t INPUT; /* input register */
AnnaBridge	171:3a7713b1edbc	355	__IO uint16_t REGMODE_L; /* match - capture registers mode register L */
AnnaBridge	171:3a7713b1edbc	356	__IO uint16_t REGMODE_H; /* match - capture registers mode register H */
AnnaBridge	171:3a7713b1edbc	357	__IO uint32_t OUTPUT; /* output register */
AnnaBridge	171:3a7713b1edbc	358	__IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
AnnaBridge	171:3a7713b1edbc	359	__IO uint32_t RES; /* conflict resolution register */
AnnaBridge	171:3a7713b1edbc	360	__IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
AnnaBridge	171:3a7713b1edbc	361	__IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
AnnaBridge	171:3a7713b1edbc	362	uint32_t RESERVED2[35];
AnnaBridge	171:3a7713b1edbc	363	__IO uint32_t EVEN; /* event enable register */
AnnaBridge	171:3a7713b1edbc	364	__IO uint32_t EVFLAG; /* event flag register */
AnnaBridge	171:3a7713b1edbc	365	__IO uint32_t CONEN; /* conflict enable register */
AnnaBridge	171:3a7713b1edbc	366	__IO uint32_t CONFLAG; /* conflict flag register */
AnnaBridge	171:3a7713b1edbc	367	union {
AnnaBridge	171:3a7713b1edbc	368	__IO union { /* ... Match / Capture value */
AnnaBridge	171:3a7713b1edbc	369	uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
AnnaBridge	171:3a7713b1edbc	370	struct {
AnnaBridge	171:3a7713b1edbc	371	uint16_t L; /* SCTMATCH[i].L Access to L value */
AnnaBridge	171:3a7713b1edbc	372	uint16_t H; /* SCTMATCH[i].H Access to H value */
AnnaBridge	171:3a7713b1edbc	373	};
AnnaBridge	171:3a7713b1edbc	374
AnnaBridge	171:3a7713b1edbc	375	} MATCH[CONFIG_SCT_nRG];
AnnaBridge	171:3a7713b1edbc	376
AnnaBridge	171:3a7713b1edbc	377	__I union {
AnnaBridge	171:3a7713b1edbc	378	uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
AnnaBridge	171:3a7713b1edbc	379	struct {
AnnaBridge	171:3a7713b1edbc	380	uint16_t L; /* SCTCAP[i].L Access to L value */
AnnaBridge	171:3a7713b1edbc	381	uint16_t H; /* SCTCAP[i].H Access to H value */
AnnaBridge	171:3a7713b1edbc	382	};
AnnaBridge	171:3a7713b1edbc	383
AnnaBridge	171:3a7713b1edbc	384	} CAP[CONFIG_SCT_nRG];
AnnaBridge	171:3a7713b1edbc	385
AnnaBridge	171:3a7713b1edbc	386	};
AnnaBridge	171:3a7713b1edbc	387
AnnaBridge	171:3a7713b1edbc	388	uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
AnnaBridge	171:3a7713b1edbc	389	union {
AnnaBridge	171:3a7713b1edbc	390	__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
AnnaBridge	171:3a7713b1edbc	391	__I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
AnnaBridge	171:3a7713b1edbc	392	};
AnnaBridge	171:3a7713b1edbc	393
AnnaBridge	171:3a7713b1edbc	394	uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
AnnaBridge	171:3a7713b1edbc	395	union {
AnnaBridge	171:3a7713b1edbc	396	__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
AnnaBridge	171:3a7713b1edbc	397	__I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
AnnaBridge	171:3a7713b1edbc	398	};
AnnaBridge	171:3a7713b1edbc	399
AnnaBridge	171:3a7713b1edbc	400	uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
AnnaBridge	171:3a7713b1edbc	401	union {
AnnaBridge	171:3a7713b1edbc	402	__IO union { /* 0x200-... Match Reload / Capture Control value */
AnnaBridge	171:3a7713b1edbc	403	uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
AnnaBridge	171:3a7713b1edbc	404	struct {
AnnaBridge	171:3a7713b1edbc	405	uint16_t L; /* SCTMATCHREL[i].L Access to L value */
AnnaBridge	171:3a7713b1edbc	406	uint16_t H; /* SCTMATCHREL[i].H Access to H value */
AnnaBridge	171:3a7713b1edbc	407	};
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	} MATCHREL[CONFIG_SCT_nRG];
AnnaBridge	171:3a7713b1edbc	410
AnnaBridge	171:3a7713b1edbc	411	__IO union {
AnnaBridge	171:3a7713b1edbc	412	uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
AnnaBridge	171:3a7713b1edbc	413	struct {
AnnaBridge	171:3a7713b1edbc	414	uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
AnnaBridge	171:3a7713b1edbc	415	uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
AnnaBridge	171:3a7713b1edbc	416	};
AnnaBridge	171:3a7713b1edbc	417
AnnaBridge	171:3a7713b1edbc	418	} CAPCTRL[CONFIG_SCT_nRG];
AnnaBridge	171:3a7713b1edbc	419
AnnaBridge	171:3a7713b1edbc	420	};
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
AnnaBridge	171:3a7713b1edbc	423	union {
AnnaBridge	171:3a7713b1edbc	424	__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
AnnaBridge	171:3a7713b1edbc	425	__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
AnnaBridge	171:3a7713b1edbc	426	};
AnnaBridge	171:3a7713b1edbc	427
AnnaBridge	171:3a7713b1edbc	428	uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
AnnaBridge	171:3a7713b1edbc	429	union {
AnnaBridge	171:3a7713b1edbc	430	__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
AnnaBridge	171:3a7713b1edbc	431	__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
AnnaBridge	171:3a7713b1edbc	432	};
AnnaBridge	171:3a7713b1edbc	433
AnnaBridge	171:3a7713b1edbc	434	uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
AnnaBridge	171:3a7713b1edbc	435	__IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
AnnaBridge	171:3a7713b1edbc	436	uint32_t STATE; /* Event State Register */
AnnaBridge	171:3a7713b1edbc	437	uint32_t CTRL; /* Event Control Register */
AnnaBridge	171:3a7713b1edbc	438	} EVENT[CONFIG_SCT_nEV];
AnnaBridge	171:3a7713b1edbc	439
AnnaBridge	171:3a7713b1edbc	440	uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
AnnaBridge	171:3a7713b1edbc	441	__IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
AnnaBridge	171:3a7713b1edbc	442	uint32_t SET; /* Output n Set Register */
AnnaBridge	171:3a7713b1edbc	443	uint32_t CLR; /* Output n Clear Register */
AnnaBridge	171:3a7713b1edbc	444	} OUT[CONFIG_SCT_nOU];
AnnaBridge	171:3a7713b1edbc	445
AnnaBridge	171:3a7713b1edbc	446	uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
AnnaBridge	171:3a7713b1edbc	447	__I uint32_t MODULECONTENT; /* 0x7FC Module Content */
AnnaBridge	171:3a7713b1edbc	448	} LPC_SCT_T;
AnnaBridge	171:3a7713b1edbc	449
AnnaBridge	171:3a7713b1edbc	450	/* Macro defines for SCT configuration register */
AnnaBridge	171:3a7713b1edbc	451	#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
AnnaBridge	171:3a7713b1edbc	452	#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
AnnaBridge	171:3a7713b1edbc	453
AnnaBridge	171:3a7713b1edbc	454	#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
AnnaBridge	171:3a7713b1edbc	455	#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
AnnaBridge	171:3a7713b1edbc	456	#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
AnnaBridge	171:3a7713b1edbc	457	#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
AnnaBridge	171:3a7713b1edbc	458
AnnaBridge	171:3a7713b1edbc	459	#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
AnnaBridge	171:3a7713b1edbc	460	#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
AnnaBridge	171:3a7713b1edbc	461
AnnaBridge	171:3a7713b1edbc	462	/* Macro defines for SCT control register */
AnnaBridge	171:3a7713b1edbc	463	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
AnnaBridge	171:3a7713b1edbc	464	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
AnnaBridge	171:3a7713b1edbc	465
AnnaBridge	171:3a7713b1edbc	466	#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
AnnaBridge	171:3a7713b1edbc	467	#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
AnnaBridge	171:3a7713b1edbc	468	#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
AnnaBridge	171:3a7713b1edbc	469	#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
AnnaBridge	171:3a7713b1edbc	470	#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
AnnaBridge	171:3a7713b1edbc	471
AnnaBridge	171:3a7713b1edbc	472	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
AnnaBridge	171:3a7713b1edbc	473	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
AnnaBridge	171:3a7713b1edbc	474	#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
AnnaBridge	171:3a7713b1edbc	475	#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
AnnaBridge	171:3a7713b1edbc	476	#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
AnnaBridge	171:3a7713b1edbc	477	#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
AnnaBridge	171:3a7713b1edbc	478	#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	/* Macro defines for SCT Conflict resolution register */
AnnaBridge	171:3a7713b1edbc	481	#define SCT_RES_NOCHANGE (0)
AnnaBridge	171:3a7713b1edbc	482	#define SCT_RES_SET_OUTPUT (1)
AnnaBridge	171:3a7713b1edbc	483	#define SCT_RES_CLEAR_OUTPUT (2)
AnnaBridge	171:3a7713b1edbc	484	#define SCT_RES_TOGGLE_OUTPUT (3)
AnnaBridge	171:3a7713b1edbc	485
AnnaBridge	171:3a7713b1edbc	486	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	487	* GPDMA Channel register block structure
AnnaBridge	171:3a7713b1edbc	488	*/
AnnaBridge	171:3a7713b1edbc	489	#define LPC_GPDMA_BASE 0x40002000
AnnaBridge	171:3a7713b1edbc	490
AnnaBridge	171:3a7713b1edbc	491	typedef struct {
AnnaBridge	171:3a7713b1edbc	492	__IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
AnnaBridge	171:3a7713b1edbc	493	__IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
AnnaBridge	171:3a7713b1edbc	494	__IO uint32_t LLI; /* DMA Channel Linked List Item Register */
AnnaBridge	171:3a7713b1edbc	495	__IO uint32_t CONTROL; /* DMA Channel Control Register */
AnnaBridge	171:3a7713b1edbc	496	__IO uint32_t CONFIG; /* DMA Channel Configuration Register */
AnnaBridge	171:3a7713b1edbc	497	__I uint32_t RESERVED1[3];
AnnaBridge	171:3a7713b1edbc	498	} LPC_GPDMA_CH_T;
AnnaBridge	171:3a7713b1edbc	499
AnnaBridge	171:3a7713b1edbc	500	#define GPDMA_CHANNELS 8
AnnaBridge	171:3a7713b1edbc	501
AnnaBridge	171:3a7713b1edbc	502	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	503	* GPDMA register block
AnnaBridge	171:3a7713b1edbc	504	*/
AnnaBridge	171:3a7713b1edbc	505	typedef struct { /* GPDMA Structure */
AnnaBridge	171:3a7713b1edbc	506	__I uint32_t INTSTAT; /* DMA Interrupt Status Register */
AnnaBridge	171:3a7713b1edbc	507	__I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
AnnaBridge	171:3a7713b1edbc	508	__O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
AnnaBridge	171:3a7713b1edbc	509	__I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
AnnaBridge	171:3a7713b1edbc	510	__O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
AnnaBridge	171:3a7713b1edbc	511	__I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
AnnaBridge	171:3a7713b1edbc	512	__I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
AnnaBridge	171:3a7713b1edbc	513	__I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
AnnaBridge	171:3a7713b1edbc	514	__IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
AnnaBridge	171:3a7713b1edbc	515	__IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
AnnaBridge	171:3a7713b1edbc	516	__IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
AnnaBridge	171:3a7713b1edbc	517	__IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
AnnaBridge	171:3a7713b1edbc	518	__IO uint32_t CONFIG; /* DMA Configuration Register */
AnnaBridge	171:3a7713b1edbc	519	__IO uint32_t SYNC; /* DMA Synchronization Register */
AnnaBridge	171:3a7713b1edbc	520	__I uint32_t RESERVED0[50];
AnnaBridge	171:3a7713b1edbc	521	LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
AnnaBridge	171:3a7713b1edbc	522	} LPC_GPDMA_T;
AnnaBridge	171:3a7713b1edbc	523
AnnaBridge	171:3a7713b1edbc	524	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	525	* SPIFI register block structure
AnnaBridge	171:3a7713b1edbc	526	*/
AnnaBridge	171:3a7713b1edbc	527	#define LPC_SPIFI_BASE 0x40003000
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	typedef struct { /* SPIFI Structure */
AnnaBridge	171:3a7713b1edbc	530	__IO uint32_t CTRL; /* Control register */
AnnaBridge	171:3a7713b1edbc	531	__IO uint32_t CMD; /* Command register */
AnnaBridge	171:3a7713b1edbc	532	__IO uint32_t ADDR; /* Address register */
AnnaBridge	171:3a7713b1edbc	533	__IO uint32_t IDATA; /* Intermediate data register */
AnnaBridge	171:3a7713b1edbc	534	__IO uint32_t CLIMIT; /* Cache limit register */
AnnaBridge	171:3a7713b1edbc	535	union {
AnnaBridge	171:3a7713b1edbc	536	__IO uint32_t DATA;
AnnaBridge	171:3a7713b1edbc	537	__IO uint16_t DATA_HWORD;
AnnaBridge	171:3a7713b1edbc	538	__IO uint8_t DATA_BYTE;
AnnaBridge	171:3a7713b1edbc	539	}; /* Data register */
AnnaBridge	171:3a7713b1edbc	540	__IO uint32_t MCMD; /* Memory command register */
AnnaBridge	171:3a7713b1edbc	541	__IO uint32_t STAT; /* Status register */
AnnaBridge	171:3a7713b1edbc	542	} LPC_SPIFI_T;
AnnaBridge	171:3a7713b1edbc	543
AnnaBridge	171:3a7713b1edbc	544	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	545	* SD/MMC & SDIO register block structure
AnnaBridge	171:3a7713b1edbc	546	*/
AnnaBridge	171:3a7713b1edbc	547	#define LPC_SDMMC_BASE 0x40004000
AnnaBridge	171:3a7713b1edbc	548
AnnaBridge	171:3a7713b1edbc	549	typedef struct { /* SDMMC Structure */
AnnaBridge	171:3a7713b1edbc	550	__IO uint32_t CTRL; /* Control Register */
AnnaBridge	171:3a7713b1edbc	551	__IO uint32_t PWREN; /* Power Enable Register */
AnnaBridge	171:3a7713b1edbc	552	__IO uint32_t CLKDIV; /* Clock Divider Register */
AnnaBridge	171:3a7713b1edbc	553	__IO uint32_t CLKSRC; /* SD Clock Source Register */
AnnaBridge	171:3a7713b1edbc	554	__IO uint32_t CLKENA; /* Clock Enable Register */
AnnaBridge	171:3a7713b1edbc	555	__IO uint32_t TMOUT; /* Timeout Register */
AnnaBridge	171:3a7713b1edbc	556	__IO uint32_t CTYPE; /* Card Type Register */
AnnaBridge	171:3a7713b1edbc	557	__IO uint32_t BLKSIZ; /* Block Size Register */
AnnaBridge	171:3a7713b1edbc	558	__IO uint32_t BYTCNT; /* Byte Count Register */
AnnaBridge	171:3a7713b1edbc	559	__IO uint32_t INTMASK; /* Interrupt Mask Register */
AnnaBridge	171:3a7713b1edbc	560	__IO uint32_t CMDARG; /* Command Argument Register */
AnnaBridge	171:3a7713b1edbc	561	__IO uint32_t CMD; /* Command Register */
AnnaBridge	171:3a7713b1edbc	562	__I uint32_t RESP0; /* Response Register 0 */
AnnaBridge	171:3a7713b1edbc	563	__I uint32_t RESP1; /* Response Register 1 */
AnnaBridge	171:3a7713b1edbc	564	__I uint32_t RESP2; /* Response Register 2 */
AnnaBridge	171:3a7713b1edbc	565	__I uint32_t RESP3; /* Response Register 3 */
AnnaBridge	171:3a7713b1edbc	566	__I uint32_t MINTSTS; /* Masked Interrupt Status Register */
AnnaBridge	171:3a7713b1edbc	567	__IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
AnnaBridge	171:3a7713b1edbc	568	__I uint32_t STATUS; /* Status Register */
AnnaBridge	171:3a7713b1edbc	569	__IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
AnnaBridge	171:3a7713b1edbc	570	__I uint32_t CDETECT; /* Card Detect Register */
AnnaBridge	171:3a7713b1edbc	571	__I uint32_t WRTPRT; /* Write Protect Register */
AnnaBridge	171:3a7713b1edbc	572	__IO uint32_t GPIO; /* General Purpose Input/Output Register */
AnnaBridge	171:3a7713b1edbc	573	__I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
AnnaBridge	171:3a7713b1edbc	574	__I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
AnnaBridge	171:3a7713b1edbc	575	__IO uint32_t DEBNCE; /* Debounce Count Register */
AnnaBridge	171:3a7713b1edbc	576	__IO uint32_t USRID; /* User ID Register */
AnnaBridge	171:3a7713b1edbc	577	__I uint32_t VERID; /* Version ID Register */
AnnaBridge	171:3a7713b1edbc	578	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	579	__IO uint32_t UHS_REG; /* UHS-1 Register */
AnnaBridge	171:3a7713b1edbc	580	__IO uint32_t RST_N; /* Hardware Reset */
AnnaBridge	171:3a7713b1edbc	581	__I uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	582	__IO uint32_t BMOD; /* Bus Mode Register */
AnnaBridge	171:3a7713b1edbc	583	__O uint32_t PLDMND; /* Poll Demand Register */
AnnaBridge	171:3a7713b1edbc	584	__IO uint32_t DBADDR; /* Descriptor List Base Address Register */
AnnaBridge	171:3a7713b1edbc	585	__IO uint32_t IDSTS; /* Internal DMAC Status Register */
AnnaBridge	171:3a7713b1edbc	586	__IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
AnnaBridge	171:3a7713b1edbc	587	__I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
AnnaBridge	171:3a7713b1edbc	588	__I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
AnnaBridge	171:3a7713b1edbc	589	} LPC_SDMMC_T;
AnnaBridge	171:3a7713b1edbc	590
AnnaBridge	171:3a7713b1edbc	591	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	592	* External Memory Controller (EMC) register block structure
AnnaBridge	171:3a7713b1edbc	593	*/
AnnaBridge	171:3a7713b1edbc	594	#define LPC_EMC_BASE 0x40005000
AnnaBridge	171:3a7713b1edbc	595
AnnaBridge	171:3a7713b1edbc	596	typedef struct { /* EMC Structure */
AnnaBridge	171:3a7713b1edbc	597	__IO uint32_t CONTROL; /* Controls operation of the memory controller. */
AnnaBridge	171:3a7713b1edbc	598	__I uint32_t STATUS; /* Provides EMC status information. */
AnnaBridge	171:3a7713b1edbc	599	__IO uint32_t CONFIG; /* Configures operation of the memory controller. */
AnnaBridge	171:3a7713b1edbc	600	__I uint32_t RESERVED0[5];
AnnaBridge	171:3a7713b1edbc	601	__IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
AnnaBridge	171:3a7713b1edbc	602	__IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
AnnaBridge	171:3a7713b1edbc	603	__IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
AnnaBridge	171:3a7713b1edbc	604	__I uint32_t RESERVED1;
AnnaBridge	171:3a7713b1edbc	605	__IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
AnnaBridge	171:3a7713b1edbc	606	__IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
AnnaBridge	171:3a7713b1edbc	607	__IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
AnnaBridge	171:3a7713b1edbc	608	__IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
AnnaBridge	171:3a7713b1edbc	609	__IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
AnnaBridge	171:3a7713b1edbc	610	__IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
AnnaBridge	171:3a7713b1edbc	611	__IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
AnnaBridge	171:3a7713b1edbc	612	__IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
AnnaBridge	171:3a7713b1edbc	613	__IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
AnnaBridge	171:3a7713b1edbc	614	__IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
AnnaBridge	171:3a7713b1edbc	615	__IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
AnnaBridge	171:3a7713b1edbc	616	__I uint32_t RESERVED2[9];
AnnaBridge	171:3a7713b1edbc	617	__IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
AnnaBridge	171:3a7713b1edbc	618	__I uint32_t RESERVED3[31];
AnnaBridge	171:3a7713b1edbc	619	__IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	620	__IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	621	__I uint32_t RESERVED4[6];
AnnaBridge	171:3a7713b1edbc	622	__IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	623	__IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	624	__I uint32_t RESERVED5[6];
AnnaBridge	171:3a7713b1edbc	625	__IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	626	__IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	627	__I uint32_t RESERVED6[6];
AnnaBridge	171:3a7713b1edbc	628	__IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	629	__IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
AnnaBridge	171:3a7713b1edbc	630	__I uint32_t RESERVED7[38];
AnnaBridge	171:3a7713b1edbc	631	__IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
AnnaBridge	171:3a7713b1edbc	632	__IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
AnnaBridge	171:3a7713b1edbc	633	__IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
AnnaBridge	171:3a7713b1edbc	634	__IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
AnnaBridge	171:3a7713b1edbc	635	__IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
AnnaBridge	171:3a7713b1edbc	636	__IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
AnnaBridge	171:3a7713b1edbc	637	__IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
AnnaBridge	171:3a7713b1edbc	638	__I uint32_t RESERVED8;
AnnaBridge	171:3a7713b1edbc	639	__IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
AnnaBridge	171:3a7713b1edbc	640	__IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
AnnaBridge	171:3a7713b1edbc	641	__IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
AnnaBridge	171:3a7713b1edbc	642	__IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
AnnaBridge	171:3a7713b1edbc	643	__IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
AnnaBridge	171:3a7713b1edbc	644	__IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
AnnaBridge	171:3a7713b1edbc	645	__IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
AnnaBridge	171:3a7713b1edbc	646	__I uint32_t RESERVED9;
AnnaBridge	171:3a7713b1edbc	647	__IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
AnnaBridge	171:3a7713b1edbc	648	__IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
AnnaBridge	171:3a7713b1edbc	649	__IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
AnnaBridge	171:3a7713b1edbc	650	__IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
AnnaBridge	171:3a7713b1edbc	651	__IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
AnnaBridge	171:3a7713b1edbc	652	__IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
AnnaBridge	171:3a7713b1edbc	653	__IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
AnnaBridge	171:3a7713b1edbc	654	__I uint32_t RESERVED10;
AnnaBridge	171:3a7713b1edbc	655	__IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
AnnaBridge	171:3a7713b1edbc	656	__IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
AnnaBridge	171:3a7713b1edbc	657	__IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
AnnaBridge	171:3a7713b1edbc	658	__IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
AnnaBridge	171:3a7713b1edbc	659	__IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
AnnaBridge	171:3a7713b1edbc	660	__IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
AnnaBridge	171:3a7713b1edbc	661	__IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
AnnaBridge	171:3a7713b1edbc	662	} LPC_EMC_T;
AnnaBridge	171:3a7713b1edbc	663
AnnaBridge	171:3a7713b1edbc	664	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	665	* USB High-Speed register block structure
AnnaBridge	171:3a7713b1edbc	666	*/
AnnaBridge	171:3a7713b1edbc	667	#define LPC_USB0_BASE 0x40006000
AnnaBridge	171:3a7713b1edbc	668	#define LPC_USB1_BASE 0x40007000
AnnaBridge	171:3a7713b1edbc	669
AnnaBridge	171:3a7713b1edbc	670	typedef struct { /* USB Structure */
AnnaBridge	171:3a7713b1edbc	671	__I uint32_t RESERVED0[64];
AnnaBridge	171:3a7713b1edbc	672	__I uint32_t CAPLENGTH; /* Capability register length */
AnnaBridge	171:3a7713b1edbc	673	__I uint32_t HCSPARAMS; /* Host controller structural parameters */
AnnaBridge	171:3a7713b1edbc	674	__I uint32_t HCCPARAMS; /* Host controller capability parameters */
AnnaBridge	171:3a7713b1edbc	675	__I uint32_t RESERVED1[5];
AnnaBridge	171:3a7713b1edbc	676	__I uint32_t DCIVERSION; /* Device interface version number */
AnnaBridge	171:3a7713b1edbc	677	__I uint32_t RESERVED2[7];
AnnaBridge	171:3a7713b1edbc	678	union {
AnnaBridge	171:3a7713b1edbc	679	__IO uint32_t USBCMD_H; /* USB command (host mode) */
AnnaBridge	171:3a7713b1edbc	680	__IO uint32_t USBCMD_D; /* USB command (device mode) */
AnnaBridge	171:3a7713b1edbc	681	};
AnnaBridge	171:3a7713b1edbc	682
AnnaBridge	171:3a7713b1edbc	683	union {
AnnaBridge	171:3a7713b1edbc	684	__IO uint32_t USBSTS_H; /* USB status (host mode) */
AnnaBridge	171:3a7713b1edbc	685	__IO uint32_t USBSTS_D; /* USB status (device mode) */
AnnaBridge	171:3a7713b1edbc	686	};
AnnaBridge	171:3a7713b1edbc	687
AnnaBridge	171:3a7713b1edbc	688	union {
AnnaBridge	171:3a7713b1edbc	689	__IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
AnnaBridge	171:3a7713b1edbc	690	__IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
AnnaBridge	171:3a7713b1edbc	691	};
AnnaBridge	171:3a7713b1edbc	692
AnnaBridge	171:3a7713b1edbc	693	union {
AnnaBridge	171:3a7713b1edbc	694	__IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
AnnaBridge	171:3a7713b1edbc	695	__I uint32_t FRINDEX_D; /* USB frame index (device mode) */
AnnaBridge	171:3a7713b1edbc	696	};
AnnaBridge	171:3a7713b1edbc	697
AnnaBridge	171:3a7713b1edbc	698	__I uint32_t RESERVED3;
AnnaBridge	171:3a7713b1edbc	699	union {
AnnaBridge	171:3a7713b1edbc	700	__IO uint32_t PERIODICLISTBASE; /* Frame list base address */
AnnaBridge	171:3a7713b1edbc	701	__IO uint32_t DEVICEADDR; /* USB device address */
AnnaBridge	171:3a7713b1edbc	702	};
AnnaBridge	171:3a7713b1edbc	703
AnnaBridge	171:3a7713b1edbc	704	union {
AnnaBridge	171:3a7713b1edbc	705	__IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
AnnaBridge	171:3a7713b1edbc	706	__IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
AnnaBridge	171:3a7713b1edbc	707	};
AnnaBridge	171:3a7713b1edbc	708
AnnaBridge	171:3a7713b1edbc	709	__IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
AnnaBridge	171:3a7713b1edbc	710	__IO uint32_t BURSTSIZE; /* Programmable burst size */
AnnaBridge	171:3a7713b1edbc	711	__IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
AnnaBridge	171:3a7713b1edbc	712	__I uint32_t RESERVED4[2];
AnnaBridge	171:3a7713b1edbc	713	__IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
AnnaBridge	171:3a7713b1edbc	714	__IO uint32_t BINTERVAL; /* Length of virtual frame */
AnnaBridge	171:3a7713b1edbc	715	__IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
AnnaBridge	171:3a7713b1edbc	716	__IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
AnnaBridge	171:3a7713b1edbc	717	__I uint32_t RESERVED5;
AnnaBridge	171:3a7713b1edbc	718	union {
AnnaBridge	171:3a7713b1edbc	719	__IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
AnnaBridge	171:3a7713b1edbc	720	__IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
AnnaBridge	171:3a7713b1edbc	721	};
AnnaBridge	171:3a7713b1edbc	722
AnnaBridge	171:3a7713b1edbc	723	__I uint32_t RESERVED6[7];
AnnaBridge	171:3a7713b1edbc	724	__IO uint32_t OTGSC; /* OTG status and control */
AnnaBridge	171:3a7713b1edbc	725	union {
AnnaBridge	171:3a7713b1edbc	726	__IO uint32_t USBMODE_H; /* USB mode (host mode) */
AnnaBridge	171:3a7713b1edbc	727	__IO uint32_t USBMODE_D; /* USB mode (device mode) */
AnnaBridge	171:3a7713b1edbc	728	};
AnnaBridge	171:3a7713b1edbc	729
AnnaBridge	171:3a7713b1edbc	730	__IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
AnnaBridge	171:3a7713b1edbc	731	__IO uint32_t ENDPTPRIME; /* Endpoint initialization */
AnnaBridge	171:3a7713b1edbc	732	__IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
AnnaBridge	171:3a7713b1edbc	733	__I uint32_t ENDPTSTAT; /* Endpoint status */
AnnaBridge	171:3a7713b1edbc	734	__IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
AnnaBridge	171:3a7713b1edbc	735	__IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
AnnaBridge	171:3a7713b1edbc	736	} LPC_USBHS_T;
AnnaBridge	171:3a7713b1edbc	737
AnnaBridge	171:3a7713b1edbc	738	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	739	* LCD Controller register block structure
AnnaBridge	171:3a7713b1edbc	740	*/
AnnaBridge	171:3a7713b1edbc	741	#define LPC_LCD_BASE 0x40008000
AnnaBridge	171:3a7713b1edbc	742
AnnaBridge	171:3a7713b1edbc	743	typedef struct { /* LCD Structure */
AnnaBridge	171:3a7713b1edbc	744	__IO uint32_t TIMH; /* Horizontal Timing Control register */
AnnaBridge	171:3a7713b1edbc	745	__IO uint32_t TIMV; /* Vertical Timing Control register */
AnnaBridge	171:3a7713b1edbc	746	__IO uint32_t POL; /* Clock and Signal Polarity Control register */
AnnaBridge	171:3a7713b1edbc	747	__IO uint32_t LE; /* Line End Control register */
AnnaBridge	171:3a7713b1edbc	748	__IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
AnnaBridge	171:3a7713b1edbc	749	__IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
AnnaBridge	171:3a7713b1edbc	750	__IO uint32_t CTRL; /* LCD Control register */
AnnaBridge	171:3a7713b1edbc	751	__IO uint32_t INTMSK; /* Interrupt Mask register */
AnnaBridge	171:3a7713b1edbc	752	__I uint32_t INTRAW; /* Raw Interrupt Status register */
AnnaBridge	171:3a7713b1edbc	753	__I uint32_t INTSTAT; /* Masked Interrupt Status register */
AnnaBridge	171:3a7713b1edbc	754	__O uint32_t INTCLR; /* Interrupt Clear register */
AnnaBridge	171:3a7713b1edbc	755	__I uint32_t UPCURR; /* Upper Panel Current Address Value register */
AnnaBridge	171:3a7713b1edbc	756	__I uint32_t LPCURR; /* Lower Panel Current Address Value register */
AnnaBridge	171:3a7713b1edbc	757	__I uint32_t RESERVED0[115];
AnnaBridge	171:3a7713b1edbc	758	__IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
AnnaBridge	171:3a7713b1edbc	759	__I uint32_t RESERVED1[256];
AnnaBridge	171:3a7713b1edbc	760	__IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
AnnaBridge	171:3a7713b1edbc	761	__IO uint32_t CRSR_CTRL; /* Cursor Control register */
AnnaBridge	171:3a7713b1edbc	762	__IO uint32_t CRSR_CFG; /* Cursor Configuration register */
AnnaBridge	171:3a7713b1edbc	763	__IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
AnnaBridge	171:3a7713b1edbc	764	__IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
AnnaBridge	171:3a7713b1edbc	765	__IO uint32_t CRSR_XY; /* Cursor XY Position register */
AnnaBridge	171:3a7713b1edbc	766	__IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
AnnaBridge	171:3a7713b1edbc	767	__I uint32_t RESERVED2[2];
AnnaBridge	171:3a7713b1edbc	768	__IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
AnnaBridge	171:3a7713b1edbc	769	__O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
AnnaBridge	171:3a7713b1edbc	770	__I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
AnnaBridge	171:3a7713b1edbc	771	__I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
AnnaBridge	171:3a7713b1edbc	772	} LPC_LCD_T;
AnnaBridge	171:3a7713b1edbc	773
AnnaBridge	171:3a7713b1edbc	774	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	775	* EEPROM register block structure
AnnaBridge	171:3a7713b1edbc	776	*/
AnnaBridge	171:3a7713b1edbc	777	#define LPC_EEPROM_BASE 0x4000E000
AnnaBridge	171:3a7713b1edbc	778
AnnaBridge	171:3a7713b1edbc	779	typedef struct { /* EEPROM Structure */
AnnaBridge	171:3a7713b1edbc	780	__IO uint32_t CMD; /* EEPROM command register */
AnnaBridge	171:3a7713b1edbc	781	uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	782	__IO uint32_t RWSTATE; /* EEPROM read wait state register */
AnnaBridge	171:3a7713b1edbc	783	__IO uint32_t AUTOPROG; /* EEPROM auto programming register */
AnnaBridge	171:3a7713b1edbc	784	__IO uint32_t WSTATE; /* EEPROM wait state register */
AnnaBridge	171:3a7713b1edbc	785	__IO uint32_t CLKDIV; /* EEPROM clock divider register */
AnnaBridge	171:3a7713b1edbc	786	__IO uint32_t PWRDWN; /* EEPROM power-down register */
AnnaBridge	171:3a7713b1edbc	787	uint32_t RESERVED2[1007];
AnnaBridge	171:3a7713b1edbc	788	__O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
AnnaBridge	171:3a7713b1edbc	789	__O uint32_t INTENSET; /* EEPROM interrupt enable set */
AnnaBridge	171:3a7713b1edbc	790	__I uint32_t INTSTAT; /* EEPROM interrupt status */
AnnaBridge	171:3a7713b1edbc	791	__I uint32_t INTEN; /* EEPROM interrupt enable */
AnnaBridge	171:3a7713b1edbc	792	__O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
AnnaBridge	171:3a7713b1edbc	793	__O uint32_t INTSTATSET; /* EEPROM interrupt status set */
AnnaBridge	171:3a7713b1edbc	794	} LPC_EEPROM_T;
AnnaBridge	171:3a7713b1edbc	795
AnnaBridge	171:3a7713b1edbc	796	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	797	* 10/100 MII & RMII Ethernet with timestamping register block structure
AnnaBridge	171:3a7713b1edbc	798	*/
AnnaBridge	171:3a7713b1edbc	799	#define LPC_ETHERNET_BASE 0x40010000
AnnaBridge	171:3a7713b1edbc	800
AnnaBridge	171:3a7713b1edbc	801	typedef struct { /* ETHERNET Structure */
AnnaBridge	171:3a7713b1edbc	802	__IO uint32_t MAC_CONFIG; /* MAC configuration register */
AnnaBridge	171:3a7713b1edbc	803	__IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
AnnaBridge	171:3a7713b1edbc	804	__IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
AnnaBridge	171:3a7713b1edbc	805	__IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
AnnaBridge	171:3a7713b1edbc	806	__IO uint32_t MAC_MII_ADDR; /* MII address register */
AnnaBridge	171:3a7713b1edbc	807	__IO uint32_t MAC_MII_DATA; /* MII data register */
AnnaBridge	171:3a7713b1edbc	808	__IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
AnnaBridge	171:3a7713b1edbc	809	__IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
AnnaBridge	171:3a7713b1edbc	810	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	811	__I uint32_t MAC_DEBUG; /* Debug register */
AnnaBridge	171:3a7713b1edbc	812	__IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
AnnaBridge	171:3a7713b1edbc	813	__IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
AnnaBridge	171:3a7713b1edbc	814	__I uint32_t RESERVED1[2];
AnnaBridge	171:3a7713b1edbc	815	__I uint32_t MAC_INTR; /* Interrupt status register */
AnnaBridge	171:3a7713b1edbc	816	__IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
AnnaBridge	171:3a7713b1edbc	817	__IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
AnnaBridge	171:3a7713b1edbc	818	__IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
AnnaBridge	171:3a7713b1edbc	819	__I uint32_t RESERVED2[430];
AnnaBridge	171:3a7713b1edbc	820	__IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
AnnaBridge	171:3a7713b1edbc	821	__IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
AnnaBridge	171:3a7713b1edbc	822	__I uint32_t SECONDS; /* System time seconds register */
AnnaBridge	171:3a7713b1edbc	823	__I uint32_t NANOSECONDS; /* System time nanoseconds register */
AnnaBridge	171:3a7713b1edbc	824	__IO uint32_t SECONDSUPDATE; /* System time seconds update register */
AnnaBridge	171:3a7713b1edbc	825	__IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
AnnaBridge	171:3a7713b1edbc	826	__IO uint32_t ADDEND; /* Time stamp addend register */
AnnaBridge	171:3a7713b1edbc	827	__IO uint32_t TARGETSECONDS; /* Target time seconds register */
AnnaBridge	171:3a7713b1edbc	828	__IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
AnnaBridge	171:3a7713b1edbc	829	__IO uint32_t HIGHWORD; /* System time higher word seconds register */
AnnaBridge	171:3a7713b1edbc	830	__I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
AnnaBridge	171:3a7713b1edbc	831	__IO uint32_t PPSCTRL; /* PPS control register */
AnnaBridge	171:3a7713b1edbc	832	__I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
AnnaBridge	171:3a7713b1edbc	833	__I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
AnnaBridge	171:3a7713b1edbc	834	__I uint32_t RESERVED3[562];
AnnaBridge	171:3a7713b1edbc	835	__IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
AnnaBridge	171:3a7713b1edbc	836	__IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
AnnaBridge	171:3a7713b1edbc	837	__IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
AnnaBridge	171:3a7713b1edbc	838	__IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
AnnaBridge	171:3a7713b1edbc	839	__IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
AnnaBridge	171:3a7713b1edbc	840	__IO uint32_t DMA_STAT; /* Status register */
AnnaBridge	171:3a7713b1edbc	841	__IO uint32_t DMA_OP_MODE; /* Operation mode register */
AnnaBridge	171:3a7713b1edbc	842	__IO uint32_t DMA_INT_EN; /* Interrupt enable register */
AnnaBridge	171:3a7713b1edbc	843	__I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
AnnaBridge	171:3a7713b1edbc	844	__IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
AnnaBridge	171:3a7713b1edbc	845	__I uint32_t RESERVED4[8];
AnnaBridge	171:3a7713b1edbc	846	__I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
AnnaBridge	171:3a7713b1edbc	847	__I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
AnnaBridge	171:3a7713b1edbc	848	__I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
AnnaBridge	171:3a7713b1edbc	849	__I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
AnnaBridge	171:3a7713b1edbc	850	} LPC_ENET_T;
AnnaBridge	171:3a7713b1edbc	851
AnnaBridge	171:3a7713b1edbc	852	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	853	* Alarm Timer register block structure
AnnaBridge	171:3a7713b1edbc	854	*/
AnnaBridge	171:3a7713b1edbc	855	#define LPC_ATIMER_BASE 0x40040000
AnnaBridge	171:3a7713b1edbc	856
AnnaBridge	171:3a7713b1edbc	857	typedef struct { /* ATIMER Structure */
AnnaBridge	171:3a7713b1edbc	858	__IO uint32_t DOWNCOUNTER; /* Downcounter register */
AnnaBridge	171:3a7713b1edbc	859	__IO uint32_t PRESET; /* Preset value register */
AnnaBridge	171:3a7713b1edbc	860	__I uint32_t RESERVED0[1012];
AnnaBridge	171:3a7713b1edbc	861	__O uint32_t CLR_EN; /* Interrupt clear enable register */
AnnaBridge	171:3a7713b1edbc	862	__O uint32_t SET_EN; /* Interrupt set enable register */
AnnaBridge	171:3a7713b1edbc	863	__I uint32_t STATUS; /* Status register */
AnnaBridge	171:3a7713b1edbc	864	__I uint32_t ENABLE; /* Enable register */
AnnaBridge	171:3a7713b1edbc	865	__O uint32_t CLR_STAT; /* Clear register */
AnnaBridge	171:3a7713b1edbc	866	__O uint32_t SET_STAT; /* Set register */
AnnaBridge	171:3a7713b1edbc	867	} LPC_ATIMER_T;
AnnaBridge	171:3a7713b1edbc	868
AnnaBridge	171:3a7713b1edbc	869	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	870	* Register File register block structure
AnnaBridge	171:3a7713b1edbc	871	*/
AnnaBridge	171:3a7713b1edbc	872	#define LPC_REGFILE_BASE 0x40041000
AnnaBridge	171:3a7713b1edbc	873
AnnaBridge	171:3a7713b1edbc	874	typedef struct {
AnnaBridge	171:3a7713b1edbc	875	__IO uint32_t REGFILE[64]; /* General purpose storage register */
AnnaBridge	171:3a7713b1edbc	876	} LPC_REGFILE_T;
AnnaBridge	171:3a7713b1edbc	877
AnnaBridge	171:3a7713b1edbc	878	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	879	* Power Management Controller register block structure
AnnaBridge	171:3a7713b1edbc	880	*/
AnnaBridge	171:3a7713b1edbc	881	#define LPC_PMC_BASE 0x40042000
AnnaBridge	171:3a7713b1edbc	882
AnnaBridge	171:3a7713b1edbc	883	typedef struct { /* PMC Structure */
AnnaBridge	171:3a7713b1edbc	884	__IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
AnnaBridge	171:3a7713b1edbc	885	__I uint32_t RESERVED0[6];
AnnaBridge	171:3a7713b1edbc	886	__IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
AnnaBridge	171:3a7713b1edbc	887	} LPC_PMC_T;
AnnaBridge	171:3a7713b1edbc	888
AnnaBridge	171:3a7713b1edbc	889	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	890	* CREG Register Block
AnnaBridge	171:3a7713b1edbc	891	*/
AnnaBridge	171:3a7713b1edbc	892	#define LPC_CREG_BASE 0x40043000
AnnaBridge	171:3a7713b1edbc	893
AnnaBridge	171:3a7713b1edbc	894	typedef struct { /* CREG Structure */
AnnaBridge	171:3a7713b1edbc	895	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	896	__IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
AnnaBridge	171:3a7713b1edbc	897	__I uint32_t RESERVED1[62];
AnnaBridge	171:3a7713b1edbc	898	__IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
AnnaBridge	171:3a7713b1edbc	899	#if defined(CHIP_LPC18XX)
AnnaBridge	171:3a7713b1edbc	900	__I uint32_t RESERVED2[5];
AnnaBridge	171:3a7713b1edbc	901	#else
AnnaBridge	171:3a7713b1edbc	902	__I uint32_t RESERVED2;
AnnaBridge	171:3a7713b1edbc	903	__I uint32_t CREG1; /* Configuration Register 1 */
AnnaBridge	171:3a7713b1edbc	904	__I uint32_t CREG2; /* Configuration Register 2 */
AnnaBridge	171:3a7713b1edbc	905	__I uint32_t CREG3; /* Configuration Register 3 */
AnnaBridge	171:3a7713b1edbc	906	__I uint32_t CREG4; /* Configuration Register 4 */
AnnaBridge	171:3a7713b1edbc	907	#endif
AnnaBridge	171:3a7713b1edbc	908	__IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
AnnaBridge	171:3a7713b1edbc	909	__IO uint32_t DMAMUX; /* DMA muxing control */
AnnaBridge	171:3a7713b1edbc	910	__IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
AnnaBridge	171:3a7713b1edbc	911	__IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
AnnaBridge	171:3a7713b1edbc	912	__IO uint32_t ETBCFG; /* ETB RAM configuration */
AnnaBridge	171:3a7713b1edbc	913	__IO uint32_t CREG6; /* Chip configuration register 6. */
AnnaBridge	171:3a7713b1edbc	914	#if defined(CHIP_LPC18XX)
AnnaBridge	171:3a7713b1edbc	915	__I uint32_t RESERVED4[52];
AnnaBridge	171:3a7713b1edbc	916	#else
AnnaBridge	171:3a7713b1edbc	917	__IO uint32_t M4TXEVENT; /* M4 IPC event register */
AnnaBridge	171:3a7713b1edbc	918	__I uint32_t RESERVED4[51];
AnnaBridge	171:3a7713b1edbc	919	#endif
AnnaBridge	171:3a7713b1edbc	920	__I uint32_t CHIPID; /* Part ID */
AnnaBridge	171:3a7713b1edbc	921	#if defined(CHIP_LPC18XX)
AnnaBridge	171:3a7713b1edbc	922	__I uint32_t RESERVED5[191];
AnnaBridge	171:3a7713b1edbc	923	#else
AnnaBridge	171:3a7713b1edbc	924	__I uint32_t RESERVED5[127];
AnnaBridge	171:3a7713b1edbc	925	__IO uint32_t M0TXEVENT; /* M0 IPC Event register */
AnnaBridge	171:3a7713b1edbc	926	__IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
AnnaBridge	171:3a7713b1edbc	927	__I uint32_t RESERVED6[62];
AnnaBridge	171:3a7713b1edbc	928	#endif
AnnaBridge	171:3a7713b1edbc	929	__IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
AnnaBridge	171:3a7713b1edbc	930	__I uint32_t RESERVED7[63];
AnnaBridge	171:3a7713b1edbc	931	__IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
AnnaBridge	171:3a7713b1edbc	932	} LPC_CREG_T;
AnnaBridge	171:3a7713b1edbc	933
AnnaBridge	171:3a7713b1edbc	934	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	935	* Event Router register structure
AnnaBridge	171:3a7713b1edbc	936	*/
AnnaBridge	171:3a7713b1edbc	937	#define LPC_EVRT_BASE 0x40044000
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	typedef struct { /* EVENTROUTER Structure */
AnnaBridge	171:3a7713b1edbc	940	__IO uint32_t HILO; /* Level configuration register */
AnnaBridge	171:3a7713b1edbc	941	__IO uint32_t EDGE; /* Edge configuration */
AnnaBridge	171:3a7713b1edbc	942	__I uint32_t RESERVED0[1012];
AnnaBridge	171:3a7713b1edbc	943	__O uint32_t CLR_EN; /* Event clear enable register */
AnnaBridge	171:3a7713b1edbc	944	__O uint32_t SET_EN; /* Event set enable register */
AnnaBridge	171:3a7713b1edbc	945	__I uint32_t STATUS; /* Status register */
AnnaBridge	171:3a7713b1edbc	946	__I uint32_t ENABLE; /* Enable register */
AnnaBridge	171:3a7713b1edbc	947	__O uint32_t CLR_STAT; /* Clear register */
AnnaBridge	171:3a7713b1edbc	948	__O uint32_t SET_STAT; /* Set register */
AnnaBridge	171:3a7713b1edbc	949	} LPC_EVRT_T;
AnnaBridge	171:3a7713b1edbc	950
AnnaBridge	171:3a7713b1edbc	951	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	952	* Real Time Clock register block structure
AnnaBridge	171:3a7713b1edbc	953	*/
AnnaBridge	171:3a7713b1edbc	954	#define LPC_RTC_BASE 0x40046000
AnnaBridge	171:3a7713b1edbc	955	#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
AnnaBridge	171:3a7713b1edbc	956
AnnaBridge	171:3a7713b1edbc	957	typedef enum RTC_TIMEINDEX {
AnnaBridge	171:3a7713b1edbc	958	RTC_TIMETYPE_SECOND, /* Second */
AnnaBridge	171:3a7713b1edbc	959	RTC_TIMETYPE_MINUTE, /* Month */
AnnaBridge	171:3a7713b1edbc	960	RTC_TIMETYPE_HOUR, /* Hour */
AnnaBridge	171:3a7713b1edbc	961	RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
AnnaBridge	171:3a7713b1edbc	962	RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
AnnaBridge	171:3a7713b1edbc	963	RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
AnnaBridge	171:3a7713b1edbc	964	RTC_TIMETYPE_MONTH, /* Month */
AnnaBridge	171:3a7713b1edbc	965	RTC_TIMETYPE_YEAR, /* Year */
AnnaBridge	171:3a7713b1edbc	966	RTC_TIMETYPE_LAST
AnnaBridge	171:3a7713b1edbc	967	} RTC_TIMEINDEX_T;
AnnaBridge	171:3a7713b1edbc	968
AnnaBridge	171:3a7713b1edbc	969	#if RTC_EV_SUPPORT
AnnaBridge	171:3a7713b1edbc	970	typedef enum LPC_RTC_EV_CHANNEL {
AnnaBridge	171:3a7713b1edbc	971	RTC_EV_CHANNEL_1 = 0,
AnnaBridge	171:3a7713b1edbc	972	RTC_EV_CHANNEL_2,
AnnaBridge	171:3a7713b1edbc	973	RTC_EV_CHANNEL_3,
AnnaBridge	171:3a7713b1edbc	974	RTC_EV_CHANNEL_NUM,
AnnaBridge	171:3a7713b1edbc	975	} LPC_RTC_EV_CHANNEL_T;
AnnaBridge	171:3a7713b1edbc	976	#endif /RTC_EV_SUPPORT/
AnnaBridge	171:3a7713b1edbc	977
AnnaBridge	171:3a7713b1edbc	978	typedef struct { /* RTC Structure */
AnnaBridge	171:3a7713b1edbc	979	__IO uint32_t ILR; /* Interrupt Location Register */
AnnaBridge	171:3a7713b1edbc	980	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	981	__IO uint32_t CCR; /* Clock Control Register */
AnnaBridge	171:3a7713b1edbc	982	__IO uint32_t CIIR; /* Counter Increment Interrupt Register */
AnnaBridge	171:3a7713b1edbc	983	__IO uint32_t AMR; /* Alarm Mask Register */
AnnaBridge	171:3a7713b1edbc	984	__I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
AnnaBridge	171:3a7713b1edbc	985	__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
AnnaBridge	171:3a7713b1edbc	986	__IO uint32_t CALIBRATION; /* Calibration Value Register */
AnnaBridge	171:3a7713b1edbc	987	__I uint32_t RESERVED1[7];
AnnaBridge	171:3a7713b1edbc	988	__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
AnnaBridge	171:3a7713b1edbc	989	#if RTC_EV_SUPPORT
AnnaBridge	171:3a7713b1edbc	990	__IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
AnnaBridge	171:3a7713b1edbc	991	__IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
AnnaBridge	171:3a7713b1edbc	992	__I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
AnnaBridge	171:3a7713b1edbc	993	__I uint32_t RESERVED2;
AnnaBridge	171:3a7713b1edbc	994	__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
AnnaBridge	171:3a7713b1edbc	995	__I uint32_t RESERVED3;
AnnaBridge	171:3a7713b1edbc	996	__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
AnnaBridge	171:3a7713b1edbc	997	#endif /RTC_EV_SUPPORT/
AnnaBridge	171:3a7713b1edbc	998	} LPC_RTC_T;
AnnaBridge	171:3a7713b1edbc	999
AnnaBridge	171:3a7713b1edbc	1000	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1001	* LPC18XX/43XX CGU register block structure
AnnaBridge	171:3a7713b1edbc	1002	*/
AnnaBridge	171:3a7713b1edbc	1003	#define LPC_CGU_BASE 0x40050000
AnnaBridge	171:3a7713b1edbc	1004	#define LPC_CCU1_BASE 0x40051000
AnnaBridge	171:3a7713b1edbc	1005	#define LPC_CCU2_BASE 0x40052000
AnnaBridge	171:3a7713b1edbc	1006	/*
AnnaBridge	171:3a7713b1edbc	1007	* Input clocks for the CGU and can come from both external (crystal) and
AnnaBridge	171:3a7713b1edbc	1008	* internal (PLL) sources. Can be routed to the base clocks.
AnnaBridge	171:3a7713b1edbc	1009	*/
AnnaBridge	171:3a7713b1edbc	1010	typedef enum CGU_CLKIN {
AnnaBridge	171:3a7713b1edbc	1011	CLKIN_32K, /* External 32KHz input */
AnnaBridge	171:3a7713b1edbc	1012	CLKIN_IRC, /* Internal IRC (12MHz) input */
AnnaBridge	171:3a7713b1edbc	1013	CLKIN_ENET_RX, /* External ENET_RX pin input */
AnnaBridge	171:3a7713b1edbc	1014	CLKIN_ENET_TX, /* External ENET_TX pin input */
AnnaBridge	171:3a7713b1edbc	1015	CLKIN_CLKIN, /* External GPCLKIN pin input */
AnnaBridge	171:3a7713b1edbc	1016	CLKIN_RESERVED1,
AnnaBridge	171:3a7713b1edbc	1017	CLKIN_CRYSTAL, /* External (main) crystal pin input */
AnnaBridge	171:3a7713b1edbc	1018	CLKIN_USBPLL, /* Internal USB PLL input */
AnnaBridge	171:3a7713b1edbc	1019	CLKIN_AUDIOPLL, /* Internal Audio PLL input */
AnnaBridge	171:3a7713b1edbc	1020	CLKIN_MAINPLL, /* Internal Main PLL input */
AnnaBridge	171:3a7713b1edbc	1021	CLKIN_RESERVED2,
AnnaBridge	171:3a7713b1edbc	1022	CLKIN_RESERVED3,
AnnaBridge	171:3a7713b1edbc	1023	CLKIN_IDIVA, /* Internal divider A input */
AnnaBridge	171:3a7713b1edbc	1024	CLKIN_IDIVB, /* Internal divider B input */
AnnaBridge	171:3a7713b1edbc	1025	CLKIN_IDIVC, /* Internal divider C input */
AnnaBridge	171:3a7713b1edbc	1026	CLKIN_IDIVD, /* Internal divider D input */
AnnaBridge	171:3a7713b1edbc	1027	CLKIN_IDIVE, /* Internal divider E input */
AnnaBridge	171:3a7713b1edbc	1028	CLKINPUT_PD /* External 32KHz input */
AnnaBridge	171:3a7713b1edbc	1029	} CGU_CLKIN_T;
AnnaBridge	171:3a7713b1edbc	1030
AnnaBridge	171:3a7713b1edbc	1031	#define CLKIN_PLL0USB CLKIN_USBPLL
AnnaBridge	171:3a7713b1edbc	1032	#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
AnnaBridge	171:3a7713b1edbc	1033	#define CLKIN_PLL1 CLKIN_MAINPLL
AnnaBridge	171:3a7713b1edbc	1034
AnnaBridge	171:3a7713b1edbc	1035	/*
AnnaBridge	171:3a7713b1edbc	1036	* CGU base clocks are clocks that are associated with a single input clock
AnnaBridge	171:3a7713b1edbc	1037	* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
AnnaBridge	171:3a7713b1edbc	1038	* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
AnnaBridge	171:3a7713b1edbc	1039	* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
AnnaBridge	171:3a7713b1edbc	1040	* CLK_PERIPH_SGPIO periphral clocks.
AnnaBridge	171:3a7713b1edbc	1041	*/
AnnaBridge	171:3a7713b1edbc	1042	typedef enum CGU_BASE_CLK {
AnnaBridge	171:3a7713b1edbc	1043	CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
AnnaBridge	171:3a7713b1edbc	1044	CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
AnnaBridge	171:3a7713b1edbc	1045	#if defined(CHIP_LPC43XX)
AnnaBridge	171:3a7713b1edbc	1046	CLK_BASE_PERIPH, /* Base clock for SGPIO */
AnnaBridge	171:3a7713b1edbc	1047	#else
AnnaBridge	171:3a7713b1edbc	1048	CLK_BASE_RESERVED1,
AnnaBridge	171:3a7713b1edbc	1049	#endif
AnnaBridge	171:3a7713b1edbc	1050	CLK_BASE_USB1, /* Base USB clock for USB1 */
AnnaBridge	171:3a7713b1edbc	1051	CLK_BASE_MX, /* Base clock for CPU core */
AnnaBridge	171:3a7713b1edbc	1052	CLK_BASE_SPIFI, /* Base clock for SPIFI */
AnnaBridge	171:3a7713b1edbc	1053	#if defined(CHIP_LPC43XX)
AnnaBridge	171:3a7713b1edbc	1054	CLK_BASE_SPI, /* Base clock for SPI */
AnnaBridge	171:3a7713b1edbc	1055	#else
AnnaBridge	171:3a7713b1edbc	1056	CLK_BASE_RESERVED2,
AnnaBridge	171:3a7713b1edbc	1057	#endif
AnnaBridge	171:3a7713b1edbc	1058	CLK_BASE_PHY_RX, /* Base clock for PHY RX */
AnnaBridge	171:3a7713b1edbc	1059	CLK_BASE_PHY_TX, /* Base clock for PHY TX */
AnnaBridge	171:3a7713b1edbc	1060	CLK_BASE_APB1, /* Base clock for APB1 group */
AnnaBridge	171:3a7713b1edbc	1061	CLK_BASE_APB3, /* Base clock for APB3 group */
AnnaBridge	171:3a7713b1edbc	1062	CLK_BASE_LCD, /* Base clock for LCD pixel clock */
AnnaBridge	171:3a7713b1edbc	1063	#if defined(CHIP_LPC43XX)
AnnaBridge	171:3a7713b1edbc	1064	CLK_BASE_VADC, /* Base clock for VADC */
AnnaBridge	171:3a7713b1edbc	1065	#else
AnnaBridge	171:3a7713b1edbc	1066	CLK_BASE_RESERVED3,
AnnaBridge	171:3a7713b1edbc	1067	#endif
AnnaBridge	171:3a7713b1edbc	1068	CLK_BASE_SDIO, /* Base clock for SDIO */
AnnaBridge	171:3a7713b1edbc	1069	CLK_BASE_SSP0, /* Base clock for SSP0 */
AnnaBridge	171:3a7713b1edbc	1070	CLK_BASE_SSP1, /* Base clock for SSP1 */
AnnaBridge	171:3a7713b1edbc	1071	CLK_BASE_UART0, /* Base clock for UART0 */
AnnaBridge	171:3a7713b1edbc	1072	CLK_BASE_UART1, /* Base clock for UART1 */
AnnaBridge	171:3a7713b1edbc	1073	CLK_BASE_UART2, /* Base clock for UART2 */
AnnaBridge	171:3a7713b1edbc	1074	CLK_BASE_UART3, /* Base clock for UART3 */
AnnaBridge	171:3a7713b1edbc	1075	CLK_BASE_OUT, /* Base clock for CLKOUT pin */
AnnaBridge	171:3a7713b1edbc	1076	CLK_BASE_RESERVED4,
AnnaBridge	171:3a7713b1edbc	1077	CLK_BASE_RESERVED5,
AnnaBridge	171:3a7713b1edbc	1078	CLK_BASE_RESERVED6,
AnnaBridge	171:3a7713b1edbc	1079	CLK_BASE_RESERVED7,
AnnaBridge	171:3a7713b1edbc	1080	CLK_BASE_APLL, /* Base clock for audio PLL */
AnnaBridge	171:3a7713b1edbc	1081	CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
AnnaBridge	171:3a7713b1edbc	1082	CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
AnnaBridge	171:3a7713b1edbc	1083	CLK_BASE_LAST,
AnnaBridge	171:3a7713b1edbc	1084	CLK_BASE_NONE = CLK_BASE_LAST
AnnaBridge	171:3a7713b1edbc	1085	} CGU_BASE_CLK_T;
AnnaBridge	171:3a7713b1edbc	1086
AnnaBridge	171:3a7713b1edbc	1087	/*
AnnaBridge	171:3a7713b1edbc	1088	* CGU dividers provide an extra clock state where a specific clock can be
AnnaBridge	171:3a7713b1edbc	1089	* divided before being routed to a peripheral group. A divider accepts an
AnnaBridge	171:3a7713b1edbc	1090	* input clock and then divides it. To use the divided clock for a base clock
AnnaBridge	171:3a7713b1edbc	1091	* group, use the divider as the input clock for the base clock (for example,
AnnaBridge	171:3a7713b1edbc	1092	* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
AnnaBridge	171:3a7713b1edbc	1093	*/
AnnaBridge	171:3a7713b1edbc	1094	typedef enum CGU_IDIV {
AnnaBridge	171:3a7713b1edbc	1095	CLK_IDIV_A, /* CGU clock divider A */
AnnaBridge	171:3a7713b1edbc	1096	CLK_IDIV_B, /* CGU clock divider B */
AnnaBridge	171:3a7713b1edbc	1097	CLK_IDIV_C, /* CGU clock divider A */
AnnaBridge	171:3a7713b1edbc	1098	CLK_IDIV_D, /* CGU clock divider D */
AnnaBridge	171:3a7713b1edbc	1099	CLK_IDIV_E, /* CGU clock divider E */
AnnaBridge	171:3a7713b1edbc	1100	CLK_IDIV_LAST
AnnaBridge	171:3a7713b1edbc	1101	} CGU_IDIV_T;
AnnaBridge	171:3a7713b1edbc	1102
AnnaBridge	171:3a7713b1edbc	1103	/*
AnnaBridge	171:3a7713b1edbc	1104	* Peripheral clocks are individual clocks routed to peripherals. Although
AnnaBridge	171:3a7713b1edbc	1105	* multiple peripherals may share a same base clock, each peripheral's clock
AnnaBridge	171:3a7713b1edbc	1106	* can be enabled or disabled individually. Some peripheral clocks also have
AnnaBridge	171:3a7713b1edbc	1107	* additional dividers associated with them.
AnnaBridge	171:3a7713b1edbc	1108	*/
AnnaBridge	171:3a7713b1edbc	1109	typedef enum CCU_CLK {
AnnaBridge	171:3a7713b1edbc	1110	/* CCU1 clocks */
AnnaBridge	171:3a7713b1edbc	1111	CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
AnnaBridge	171:3a7713b1edbc	1112	CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
AnnaBridge	171:3a7713b1edbc	1113	CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
AnnaBridge	171:3a7713b1edbc	1114	CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
AnnaBridge	171:3a7713b1edbc	1115	CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
AnnaBridge	171:3a7713b1edbc	1116	CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
AnnaBridge	171:3a7713b1edbc	1117	CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
AnnaBridge	171:3a7713b1edbc	1118	CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
AnnaBridge	171:3a7713b1edbc	1119	CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
AnnaBridge	171:3a7713b1edbc	1120	CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
AnnaBridge	171:3a7713b1edbc	1121	CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
AnnaBridge	171:3a7713b1edbc	1122	CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
AnnaBridge	171:3a7713b1edbc	1123	CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1124	CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1125	CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1126	CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1127	CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1128	CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1129	CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1130	CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1131	CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1132	CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1133	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
AnnaBridge	171:3a7713b1edbc	1134	CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1135	CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1136	CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1137	CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1138	CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1139	#if defined(CHIP_LPC43XX)
AnnaBridge	171:3a7713b1edbc	1140	CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1141	CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1142	#else
AnnaBridge	171:3a7713b1edbc	1143	CLK_RESERVED1,
AnnaBridge	171:3a7713b1edbc	1144	CLK_RESERVED2,
AnnaBridge	171:3a7713b1edbc	1145	#endif
AnnaBridge	171:3a7713b1edbc	1146	CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1147	CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1148	CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1149	CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1150	CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1151	CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1152	CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1153	CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1154	CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1155	CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1156	CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1157	CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1158	CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1159	CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1160	CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1161	CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
AnnaBridge	171:3a7713b1edbc	1162	#if defined(CHIP_LPC43XX)
AnnaBridge	171:3a7713b1edbc	1163	CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
AnnaBridge	171:3a7713b1edbc	1164	CLK_RESERVED3,
AnnaBridge	171:3a7713b1edbc	1165	CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
AnnaBridge	171:3a7713b1edbc	1166	CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
AnnaBridge	171:3a7713b1edbc	1167	#else
AnnaBridge	171:3a7713b1edbc	1168	CLK_RESERVED3 = 192,
AnnaBridge	171:3a7713b1edbc	1169	CLK_RESERVED3A,
AnnaBridge	171:3a7713b1edbc	1170	CLK_RESERVED4,
AnnaBridge	171:3a7713b1edbc	1171	CLK_RESERVED5,
AnnaBridge	171:3a7713b1edbc	1172	#endif
AnnaBridge	171:3a7713b1edbc	1173	CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
AnnaBridge	171:3a7713b1edbc	1174	CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
AnnaBridge	171:3a7713b1edbc	1175	#if defined(CHIP_LPC43XX)
AnnaBridge	171:3a7713b1edbc	1176	CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
AnnaBridge	171:3a7713b1edbc	1177	CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
AnnaBridge	171:3a7713b1edbc	1178	#else
AnnaBridge	171:3a7713b1edbc	1179	CLK_RESERVED7 = 320,
AnnaBridge	171:3a7713b1edbc	1180	CLK_RESERVED8,
AnnaBridge	171:3a7713b1edbc	1181	#endif
AnnaBridge	171:3a7713b1edbc	1182	CLK_CCU1_LAST,
AnnaBridge	171:3a7713b1edbc	1183
AnnaBridge	171:3a7713b1edbc	1184	/* CCU2 clocks */
AnnaBridge	171:3a7713b1edbc	1185	CLK_CCU2_START,
AnnaBridge	171:3a7713b1edbc	1186	CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
AnnaBridge	171:3a7713b1edbc	1187	RESERVED_ALIGNB = CLK_CCU2_START + 31,
AnnaBridge	171:3a7713b1edbc	1188	CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
AnnaBridge	171:3a7713b1edbc	1189	RESERVED_ALIGNC = CLK_CCU2_START + 63,
AnnaBridge	171:3a7713b1edbc	1190	CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
AnnaBridge	171:3a7713b1edbc	1191	RESERVED_ALIGND = CLK_CCU2_START + 95,
AnnaBridge	171:3a7713b1edbc	1192	CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
AnnaBridge	171:3a7713b1edbc	1193	RESERVED_ALIGNE = CLK_CCU2_START + 127,
AnnaBridge	171:3a7713b1edbc	1194	CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
AnnaBridge	171:3a7713b1edbc	1195	RESERVED_ALIGNF = CLK_CCU2_START + 159,
AnnaBridge	171:3a7713b1edbc	1196	CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
AnnaBridge	171:3a7713b1edbc	1197	RESERVED_ALIGNG = CLK_CCU2_START + 191,
AnnaBridge	171:3a7713b1edbc	1198	CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
AnnaBridge	171:3a7713b1edbc	1199	RESERVED_ALIGNH = CLK_CCU2_START + 223,
AnnaBridge	171:3a7713b1edbc	1200	CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
AnnaBridge	171:3a7713b1edbc	1201	CLK_CCU2_LAST
AnnaBridge	171:3a7713b1edbc	1202	} CCU_CLK_T;
AnnaBridge	171:3a7713b1edbc	1203
AnnaBridge	171:3a7713b1edbc	1204	/*
AnnaBridge	171:3a7713b1edbc	1205	* Audio or USB PLL selection
AnnaBridge	171:3a7713b1edbc	1206	*/
AnnaBridge	171:3a7713b1edbc	1207	typedef enum CGU_USB_AUDIO_PLL {
AnnaBridge	171:3a7713b1edbc	1208	CGU_USB_PLL,
AnnaBridge	171:3a7713b1edbc	1209	CGU_AUDIO_PLL
AnnaBridge	171:3a7713b1edbc	1210	} CGU_USB_AUDIO_PLL_T;
AnnaBridge	171:3a7713b1edbc	1211
AnnaBridge	171:3a7713b1edbc	1212	/*
AnnaBridge	171:3a7713b1edbc	1213	* PLL register block
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215	typedef struct {
AnnaBridge	171:3a7713b1edbc	1216	__I uint32_t PLL_STAT; /* PLL status register */
AnnaBridge	171:3a7713b1edbc	1217	__IO uint32_t PLL_CTRL; /* PLL control register */
AnnaBridge	171:3a7713b1edbc	1218	__IO uint32_t PLL_MDIV; /* PLL M-divider register */
AnnaBridge	171:3a7713b1edbc	1219	__IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
AnnaBridge	171:3a7713b1edbc	1220	} CGU_PLL_REG_T;
AnnaBridge	171:3a7713b1edbc	1221
AnnaBridge	171:3a7713b1edbc	1222	typedef struct { /* (@ 0x40050000) CGU Structure */
AnnaBridge	171:3a7713b1edbc	1223	__I uint32_t RESERVED0[5];
AnnaBridge	171:3a7713b1edbc	1224	__IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
AnnaBridge	171:3a7713b1edbc	1225	__IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
AnnaBridge	171:3a7713b1edbc	1226	CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
AnnaBridge	171:3a7713b1edbc	1227	__IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
AnnaBridge	171:3a7713b1edbc	1228	__I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
AnnaBridge	171:3a7713b1edbc	1229	__IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
AnnaBridge	171:3a7713b1edbc	1230	__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
AnnaBridge	171:3a7713b1edbc	1231	__IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
AnnaBridge	171:3a7713b1edbc	1232	} LPC_CGU_T;
AnnaBridge	171:3a7713b1edbc	1233
AnnaBridge	171:3a7713b1edbc	1234	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1235	* CCU clock config/status register pair
AnnaBridge	171:3a7713b1edbc	1236	*/
AnnaBridge	171:3a7713b1edbc	1237	typedef struct {
AnnaBridge	171:3a7713b1edbc	1238	__IO uint32_t CFG; /* CCU clock configuration register */
AnnaBridge	171:3a7713b1edbc	1239	__I uint32_t STAT; /* CCU clock status register */
AnnaBridge	171:3a7713b1edbc	1240	} CCU_CFGSTAT_T;
AnnaBridge	171:3a7713b1edbc	1241
AnnaBridge	171:3a7713b1edbc	1242	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1243	* CCU1 register block structure
AnnaBridge	171:3a7713b1edbc	1244	*/
AnnaBridge	171:3a7713b1edbc	1245	typedef struct { /* (@ 0x40051000) CCU1 Structure */
AnnaBridge	171:3a7713b1edbc	1246	__IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
AnnaBridge	171:3a7713b1edbc	1247	__I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
AnnaBridge	171:3a7713b1edbc	1248	__I uint32_t RESERVED0[62];
AnnaBridge	171:3a7713b1edbc	1249	CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
AnnaBridge	171:3a7713b1edbc	1250	} LPC_CCU1_T;
AnnaBridge	171:3a7713b1edbc	1251
AnnaBridge	171:3a7713b1edbc	1252	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1253	* CCU2 register block structure
AnnaBridge	171:3a7713b1edbc	1254	*/
AnnaBridge	171:3a7713b1edbc	1255	typedef struct { /* (@ 0x40052000) CCU2 Structure */
AnnaBridge	171:3a7713b1edbc	1256	__IO uint32_t PM; /* (@ 0x40052000) Power mode register */
AnnaBridge	171:3a7713b1edbc	1257	__I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
AnnaBridge	171:3a7713b1edbc	1258	__I uint32_t RESERVED0[62];
AnnaBridge	171:3a7713b1edbc	1259	CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
AnnaBridge	171:3a7713b1edbc	1260	} LPC_CCU2_T;
AnnaBridge	171:3a7713b1edbc	1261
AnnaBridge	171:3a7713b1edbc	1262	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1263	* RGU register structure
AnnaBridge	171:3a7713b1edbc	1264	*/
AnnaBridge	171:3a7713b1edbc	1265	#define LPC_RGU_BASE 0x40053000
AnnaBridge	171:3a7713b1edbc	1266
AnnaBridge	171:3a7713b1edbc	1267	typedef enum RGU_RST {
AnnaBridge	171:3a7713b1edbc	1268	RGU_CORE_RST,
AnnaBridge	171:3a7713b1edbc	1269	RGU_PERIPH_RST,
AnnaBridge	171:3a7713b1edbc	1270	RGU_MASTER_RST,
AnnaBridge	171:3a7713b1edbc	1271	RGU_WWDT_RST = 4,
AnnaBridge	171:3a7713b1edbc	1272	RGU_CREG_RST,
AnnaBridge	171:3a7713b1edbc	1273	RGU_BUS_RST = 8,
AnnaBridge	171:3a7713b1edbc	1274	RGU_SCU_RST,
AnnaBridge	171:3a7713b1edbc	1275	RGU_M3_RST = 13,
AnnaBridge	171:3a7713b1edbc	1276	RGU_LCD_RST = 16,
AnnaBridge	171:3a7713b1edbc	1277	RGU_USB0_RST,
AnnaBridge	171:3a7713b1edbc	1278	RGU_USB1_RST,
AnnaBridge	171:3a7713b1edbc	1279	RGU_DMA_RST,
AnnaBridge	171:3a7713b1edbc	1280	RGU_SDIO_RST,
AnnaBridge	171:3a7713b1edbc	1281	RGU_EMC_RST,
AnnaBridge	171:3a7713b1edbc	1282	RGU_ETHERNET_RST,
AnnaBridge	171:3a7713b1edbc	1283	RGU_FLASHA_RST = 25,
AnnaBridge	171:3a7713b1edbc	1284	RGU_EEPROM_RST = 27,
AnnaBridge	171:3a7713b1edbc	1285	RGU_GPIO_RST,
AnnaBridge	171:3a7713b1edbc	1286	RGU_FLASHB_RST,
AnnaBridge	171:3a7713b1edbc	1287	RGU_TIMER0_RST = 32,
AnnaBridge	171:3a7713b1edbc	1288	RGU_TIMER1_RST,
AnnaBridge	171:3a7713b1edbc	1289	RGU_TIMER2_RST,
AnnaBridge	171:3a7713b1edbc	1290	RGU_TIMER3_RST,
AnnaBridge	171:3a7713b1edbc	1291	RGU_RITIMER_RST,
AnnaBridge	171:3a7713b1edbc	1292	RGU_SCT_RST,
AnnaBridge	171:3a7713b1edbc	1293	RGU_MOTOCONPWM_RST,
AnnaBridge	171:3a7713b1edbc	1294	RGU_QEI_RST,
AnnaBridge	171:3a7713b1edbc	1295	RGU_ADC0_RST,
AnnaBridge	171:3a7713b1edbc	1296	RGU_ADC1_RST,
AnnaBridge	171:3a7713b1edbc	1297	RGU_DAC_RST,
AnnaBridge	171:3a7713b1edbc	1298	RGU_UART0_RST = 44,
AnnaBridge	171:3a7713b1edbc	1299	RGU_UART1_RST,
AnnaBridge	171:3a7713b1edbc	1300	RGU_UART2_RST,
AnnaBridge	171:3a7713b1edbc	1301	RGU_UART3_RST,
AnnaBridge	171:3a7713b1edbc	1302	RGU_I2C0_RST,
AnnaBridge	171:3a7713b1edbc	1303	RGU_I2C1_RST,
AnnaBridge	171:3a7713b1edbc	1304	RGU_SSP0_RST,
AnnaBridge	171:3a7713b1edbc	1305	RGU_SSP1_RST,
AnnaBridge	171:3a7713b1edbc	1306	RGU_I2S_RST,
AnnaBridge	171:3a7713b1edbc	1307	RGU_SPIFI_RST,
AnnaBridge	171:3a7713b1edbc	1308	RGU_CAN1_RST,
AnnaBridge	171:3a7713b1edbc	1309	RGU_CAN0_RST,
AnnaBridge	171:3a7713b1edbc	1310	#ifdef CHIP_LPC43XX
AnnaBridge	171:3a7713b1edbc	1311	RGU_M0APP_RST,
AnnaBridge	171:3a7713b1edbc	1312	RGU_SGPIO_RST,
AnnaBridge	171:3a7713b1edbc	1313	RGU_SPI_RST,
AnnaBridge	171:3a7713b1edbc	1314	#endif
AnnaBridge	171:3a7713b1edbc	1315	RGU_LAST_RST = 63,
AnnaBridge	171:3a7713b1edbc	1316	} RGU_RST_T;
AnnaBridge	171:3a7713b1edbc	1317
AnnaBridge	171:3a7713b1edbc	1318	typedef struct { /* RGU Structure */
AnnaBridge	171:3a7713b1edbc	1319	__I uint32_t RESERVED0[64];
AnnaBridge	171:3a7713b1edbc	1320	__O uint32_t RESET_CTRL0; /* Reset control register 0 */
AnnaBridge	171:3a7713b1edbc	1321	__O uint32_t RESET_CTRL1; /* Reset control register 1 */
AnnaBridge	171:3a7713b1edbc	1322	__I uint32_t RESERVED1[2];
AnnaBridge	171:3a7713b1edbc	1323	__IO uint32_t RESET_STATUS0; /* Reset status register 0 */
AnnaBridge	171:3a7713b1edbc	1324	__IO uint32_t RESET_STATUS1; /* Reset status register 1 */
AnnaBridge	171:3a7713b1edbc	1325	__IO uint32_t RESET_STATUS2; /* Reset status register 2 */
AnnaBridge	171:3a7713b1edbc	1326	__IO uint32_t RESET_STATUS3; /* Reset status register 3 */
AnnaBridge	171:3a7713b1edbc	1327	__I uint32_t RESERVED2[12];
AnnaBridge	171:3a7713b1edbc	1328	__I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
AnnaBridge	171:3a7713b1edbc	1329	__I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
AnnaBridge	171:3a7713b1edbc	1330	__I uint32_t RESERVED3[170];
AnnaBridge	171:3a7713b1edbc	1331	__IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
AnnaBridge	171:3a7713b1edbc	1332	} LPC_RGU_T;
AnnaBridge	171:3a7713b1edbc	1333
AnnaBridge	171:3a7713b1edbc	1334	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1335	* Windowed Watchdog register block structure
AnnaBridge	171:3a7713b1edbc	1336	*/
AnnaBridge	171:3a7713b1edbc	1337	#define LPC_WWDT_BASE 0x40080000
AnnaBridge	171:3a7713b1edbc	1338
AnnaBridge	171:3a7713b1edbc	1339	typedef struct { /* WWDT Structure */
AnnaBridge	171:3a7713b1edbc	1340	__IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
AnnaBridge	171:3a7713b1edbc	1341	__IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
AnnaBridge	171:3a7713b1edbc	1342	__O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
AnnaBridge	171:3a7713b1edbc	1343	__I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
AnnaBridge	171:3a7713b1edbc	1344	#ifdef WATCHDOG_CLKSEL_SUPPORT
AnnaBridge	171:3a7713b1edbc	1345	__IO uint32_t CLKSEL; /* Watchdog clock select register. */
AnnaBridge	171:3a7713b1edbc	1346	#else
AnnaBridge	171:3a7713b1edbc	1347	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1348	#endif
AnnaBridge	171:3a7713b1edbc	1349	#ifdef WATCHDOG_WINDOW_SUPPORT
AnnaBridge	171:3a7713b1edbc	1350	__IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
AnnaBridge	171:3a7713b1edbc	1351	__IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
AnnaBridge	171:3a7713b1edbc	1352	#endif
AnnaBridge	171:3a7713b1edbc	1353	} LPC_WWDT_T;
AnnaBridge	171:3a7713b1edbc	1354
AnnaBridge	171:3a7713b1edbc	1355	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1356	* USART register block structure
AnnaBridge	171:3a7713b1edbc	1357	*/
AnnaBridge	171:3a7713b1edbc	1358	#define LPC_USART0_BASE 0x40081000
AnnaBridge	171:3a7713b1edbc	1359	#define LPC_UART1_BASE 0x40082000
AnnaBridge	171:3a7713b1edbc	1360	#define LPC_USART2_BASE 0x400C1000
AnnaBridge	171:3a7713b1edbc	1361	#define LPC_USART3_BASE 0x400C2000
AnnaBridge	171:3a7713b1edbc	1362
AnnaBridge	171:3a7713b1edbc	1363	typedef struct { /* USARTn Structure */
AnnaBridge	171:3a7713b1edbc	1364
AnnaBridge	171:3a7713b1edbc	1365	union {
AnnaBridge	171:3a7713b1edbc	1366	__IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
AnnaBridge	171:3a7713b1edbc	1367	__O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
AnnaBridge	171:3a7713b1edbc	1368	__I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
AnnaBridge	171:3a7713b1edbc	1369	};
AnnaBridge	171:3a7713b1edbc	1370
AnnaBridge	171:3a7713b1edbc	1371	union {
AnnaBridge	171:3a7713b1edbc	1372	__IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
AnnaBridge	171:3a7713b1edbc	1373	__IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
AnnaBridge	171:3a7713b1edbc	1374	};
AnnaBridge	171:3a7713b1edbc	1375
AnnaBridge	171:3a7713b1edbc	1376	union {
AnnaBridge	171:3a7713b1edbc	1377	__O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
AnnaBridge	171:3a7713b1edbc	1378	__I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
AnnaBridge	171:3a7713b1edbc	1379	};
AnnaBridge	171:3a7713b1edbc	1380
AnnaBridge	171:3a7713b1edbc	1381	__IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
AnnaBridge	171:3a7713b1edbc	1382	__IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
AnnaBridge	171:3a7713b1edbc	1383	__I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
AnnaBridge	171:3a7713b1edbc	1384	__I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
AnnaBridge	171:3a7713b1edbc	1385	__IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
AnnaBridge	171:3a7713b1edbc	1386	__IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
AnnaBridge	171:3a7713b1edbc	1387	__IO uint32_t ICR; /* IrDA control register (not all UARTS) */
AnnaBridge	171:3a7713b1edbc	1388	__IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
AnnaBridge	171:3a7713b1edbc	1389	__IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
AnnaBridge	171:3a7713b1edbc	1390	__IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
AnnaBridge	171:3a7713b1edbc	1391	uint32_t RESERVED0[3];
AnnaBridge	171:3a7713b1edbc	1392	__IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
AnnaBridge	171:3a7713b1edbc	1393	__I uint32_t RESERVED1[1];
AnnaBridge	171:3a7713b1edbc	1394	__IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
AnnaBridge	171:3a7713b1edbc	1395	__IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
AnnaBridge	171:3a7713b1edbc	1396	__IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
AnnaBridge	171:3a7713b1edbc	1397	__IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
AnnaBridge	171:3a7713b1edbc	1398	union {
AnnaBridge	171:3a7713b1edbc	1399	__IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
AnnaBridge	171:3a7713b1edbc	1400	__I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
AnnaBridge	171:3a7713b1edbc	1401	};
AnnaBridge	171:3a7713b1edbc	1402
AnnaBridge	171:3a7713b1edbc	1403	__IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
AnnaBridge	171:3a7713b1edbc	1404	} LPC_USART_T;
AnnaBridge	171:3a7713b1edbc	1405
AnnaBridge	171:3a7713b1edbc	1406	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1407	* SSP register block structure
AnnaBridge	171:3a7713b1edbc	1408	*/
AnnaBridge	171:3a7713b1edbc	1409	#define LPC_SSP0_BASE 0x40083000
AnnaBridge	171:3a7713b1edbc	1410	#define LPC_SSP1_BASE 0x400C5000
AnnaBridge	171:3a7713b1edbc	1411
AnnaBridge	171:3a7713b1edbc	1412	typedef struct { /* SSPn Structure */
AnnaBridge	171:3a7713b1edbc	1413	__IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
AnnaBridge	171:3a7713b1edbc	1414	__IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
AnnaBridge	171:3a7713b1edbc	1415	__IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
AnnaBridge	171:3a7713b1edbc	1416	__I uint32_t SR; /* Status Register */
AnnaBridge	171:3a7713b1edbc	1417	__IO uint32_t CPSR; /* Clock Prescale Register */
AnnaBridge	171:3a7713b1edbc	1418	__IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
AnnaBridge	171:3a7713b1edbc	1419	__I uint32_t RIS; /* Raw Interrupt Status Register */
AnnaBridge	171:3a7713b1edbc	1420	__I uint32_t MIS; /* Masked Interrupt Status Register */
AnnaBridge	171:3a7713b1edbc	1421	__O uint32_t ICR; /* SSPICR Interrupt Clear Register */
AnnaBridge	171:3a7713b1edbc	1422	__IO uint32_t DMACR; /* SSPn DMA control register */
AnnaBridge	171:3a7713b1edbc	1423	} LPC_SSP_T;
AnnaBridge	171:3a7713b1edbc	1424
AnnaBridge	171:3a7713b1edbc	1425	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1426	* 32-bit Standard timer register block structure
AnnaBridge	171:3a7713b1edbc	1427	*/
AnnaBridge	171:3a7713b1edbc	1428	#define LPC_TIMER0_BASE 0x40084000
AnnaBridge	171:3a7713b1edbc	1429	#define LPC_TIMER1_BASE 0x40085000
AnnaBridge	171:3a7713b1edbc	1430	#define LPC_TIMER2_BASE 0x400C3000
AnnaBridge	171:3a7713b1edbc	1431	#define LPC_TIMER3_BASE 0x400C4000
AnnaBridge	171:3a7713b1edbc	1432
AnnaBridge	171:3a7713b1edbc	1433	typedef struct { /* TIMERn Structure */
AnnaBridge	171:3a7713b1edbc	1434	__IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
AnnaBridge	171:3a7713b1edbc	1435	__IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
AnnaBridge	171:3a7713b1edbc	1436	__IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
AnnaBridge	171:3a7713b1edbc	1437	__IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
AnnaBridge	171:3a7713b1edbc	1438	__IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
AnnaBridge	171:3a7713b1edbc	1439	__IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
AnnaBridge	171:3a7713b1edbc	1440	__IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
AnnaBridge	171:3a7713b1edbc	1441	__IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
AnnaBridge	171:3a7713b1edbc	1442	__IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
AnnaBridge	171:3a7713b1edbc	1443	__IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
AnnaBridge	171:3a7713b1edbc	1444	__I uint32_t RESERVED0[12];
AnnaBridge	171:3a7713b1edbc	1445	__IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
AnnaBridge	171:3a7713b1edbc	1446	} LPC_TIMER_T;
AnnaBridge	171:3a7713b1edbc	1447
AnnaBridge	171:3a7713b1edbc	1448	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1449	* System Control Unit register block
AnnaBridge	171:3a7713b1edbc	1450	*/
AnnaBridge	171:3a7713b1edbc	1451	#define LPC_SCU_BASE 0x40086000
AnnaBridge	171:3a7713b1edbc	1452
AnnaBridge	171:3a7713b1edbc	1453	typedef struct {
AnnaBridge	171:3a7713b1edbc	1454	__IO uint32_t SFSP[16][32];
AnnaBridge	171:3a7713b1edbc	1455	__I uint32_t RESERVED0[256];
AnnaBridge	171:3a7713b1edbc	1456	__IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
AnnaBridge	171:3a7713b1edbc	1457	__I uint32_t RESERVED16[28];
AnnaBridge	171:3a7713b1edbc	1458	__IO uint32_t SFSUSB; /* Pin configuration register for USB */
AnnaBridge	171:3a7713b1edbc	1459	__IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
AnnaBridge	171:3a7713b1edbc	1460	__IO uint32_t ENAIO[3]; /* Analog function select registers */
AnnaBridge	171:3a7713b1edbc	1461	__I uint32_t RESERVED17[27];
AnnaBridge	171:3a7713b1edbc	1462	__IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
AnnaBridge	171:3a7713b1edbc	1463	__I uint32_t RESERVED18[63];
AnnaBridge	171:3a7713b1edbc	1464	__IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
AnnaBridge	171:3a7713b1edbc	1465	__IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
AnnaBridge	171:3a7713b1edbc	1466	} LPC_SCU_T;
AnnaBridge	171:3a7713b1edbc	1467
AnnaBridge	171:3a7713b1edbc	1468	/*
AnnaBridge	171:3a7713b1edbc	1469	* SCU function and mode selection definitions
AnnaBridge	171:3a7713b1edbc	1470	* See the User Manual for specific modes and functions supoprted by the
AnnaBridge	171:3a7713b1edbc	1471	* various LPC18xx/43xx devices. Functionality can vary per device.
AnnaBridge	171:3a7713b1edbc	1472	*/
AnnaBridge	171:3a7713b1edbc	1473	#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
AnnaBridge	171:3a7713b1edbc	1474	#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
AnnaBridge	171:3a7713b1edbc	1475	#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
AnnaBridge	171:3a7713b1edbc	1476	#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
AnnaBridge	171:3a7713b1edbc	1477	#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
AnnaBridge	171:3a7713b1edbc	1478	#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
AnnaBridge	171:3a7713b1edbc	1479	#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
AnnaBridge	171:3a7713b1edbc	1480	#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
AnnaBridge	171:3a7713b1edbc	1481	#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
AnnaBridge	171:3a7713b1edbc	1482	#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
AnnaBridge	171:3a7713b1edbc	1483	#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
AnnaBridge	171:3a7713b1edbc	1484
AnnaBridge	171:3a7713b1edbc	1485	#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
AnnaBridge	171:3a7713b1edbc	1486	#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
AnnaBridge	171:3a7713b1edbc	1487	#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
AnnaBridge	171:3a7713b1edbc	1488	#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
AnnaBridge	171:3a7713b1edbc	1489	#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
AnnaBridge	171:3a7713b1edbc	1490	#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
AnnaBridge	171:3a7713b1edbc	1491	#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
AnnaBridge	171:3a7713b1edbc	1492	#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
AnnaBridge	171:3a7713b1edbc	1493
AnnaBridge	171:3a7713b1edbc	1494	/* Common SCU configurations */
AnnaBridge	171:3a7713b1edbc	1495	#define SCU_PINIO_FAST (SCU_MODE_INACT \| SCU_MODE_HIGHSPEEDSLEW_EN \| SCU_MODE_INBUFF_EN \| SCU_MODE_ZIF_DIS)
AnnaBridge	171:3a7713b1edbc	1496	#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
AnnaBridge	171:3a7713b1edbc	1497	#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN \| SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
AnnaBridge	171:3a7713b1edbc	1498	#define SCU_PINIO_PULLNONE (SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
AnnaBridge	171:3a7713b1edbc	1499
AnnaBridge	171:3a7713b1edbc	1500	/* Calculate SCU offset and register address from group and pin number */
AnnaBridge	171:3a7713b1edbc	1501	#define SCU_OFF(group, num) ((group << 7) + (num << 2))
AnnaBridge	171:3a7713b1edbc	1502	#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
AnnaBridge	171:3a7713b1edbc	1503
AnnaBridge	171:3a7713b1edbc	1504	/**
AnnaBridge	171:3a7713b1edbc	1505	* SCU function and mode selection definitions (old)
AnnaBridge	171:3a7713b1edbc	1506	* For backwards compatibility.
AnnaBridge	171:3a7713b1edbc	1507	*/
AnnaBridge	171:3a7713b1edbc	1508	#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
AnnaBridge	171:3a7713b1edbc	1509	#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
AnnaBridge	171:3a7713b1edbc	1510	#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
AnnaBridge	171:3a7713b1edbc	1511	#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
AnnaBridge	171:3a7713b1edbc	1512	#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
AnnaBridge	171:3a7713b1edbc	1513	#define MD_EZI (0x1 << 6) /* Input buffer enable */
AnnaBridge	171:3a7713b1edbc	1514	#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
AnnaBridge	171:3a7713b1edbc	1515	#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
AnnaBridge	171:3a7713b1edbc	1516	#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
AnnaBridge	171:3a7713b1edbc	1517	#define MD_PLN_FAST (MD_PLN \| MD_EZI \| MD_ZI \| MD_EHS)
AnnaBridge	171:3a7713b1edbc	1518	#define I2C0_STANDARD_FAST_MODE (1 << 3 \| 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
AnnaBridge	171:3a7713b1edbc	1519	#define I2C0_FAST_MODE_PLUS (2 << 1 \| 1 << 3 \| 1 << 7 \| 1 << 10 \| 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
AnnaBridge	171:3a7713b1edbc	1520
AnnaBridge	171:3a7713b1edbc	1521	#define FUNC0 0x0 /* Pin function 0 */
AnnaBridge	171:3a7713b1edbc	1522	#define FUNC1 0x1 /* Pin function 1 */
AnnaBridge	171:3a7713b1edbc	1523	#define FUNC2 0x2 /* Pin function 2 */
AnnaBridge	171:3a7713b1edbc	1524	#define FUNC3 0x3 /* Pin function 3 */
AnnaBridge	171:3a7713b1edbc	1525	#define FUNC4 0x4 /* Pin function 4 */
AnnaBridge	171:3a7713b1edbc	1526	#define FUNC5 0x5 /* Pin function 5 */
AnnaBridge	171:3a7713b1edbc	1527	#define FUNC6 0x6 /* Pin function 6 */
AnnaBridge	171:3a7713b1edbc	1528	#define FUNC7 0x7 /* Pin function 7 */
AnnaBridge	171:3a7713b1edbc	1529
AnnaBridge	171:3a7713b1edbc	1530	#define PORT_OFFSET 0x80 /* Port offset definition */
AnnaBridge	171:3a7713b1edbc	1531	#define PIN_OFFSET 0x04 /* Pin offset definition */
AnnaBridge	171:3a7713b1edbc	1532
AnnaBridge	171:3a7713b1edbc	1533	/* Returns the SFSP register address in the SCU for a pin and port,
AnnaBridge	171:3a7713b1edbc	1534	recommend using ((volatile int ) &LPC_SCU->SFSP[po][pi];) */
AnnaBridge	171:3a7713b1edbc	1535	#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
AnnaBridge	171:3a7713b1edbc	1536	((volatile int ) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
AnnaBridge	171:3a7713b1edbc	1537
AnnaBridge	171:3a7713b1edbc	1538	/* Returns the address in the SCU for a SFSCLK clock register,
AnnaBridge	171:3a7713b1edbc	1539	recommend using ((volatile int ) &LPC_SCU->SFSCLK[c];) */
AnnaBridge	171:3a7713b1edbc	1540	#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
AnnaBridge	171:3a7713b1edbc	1541	((volatile int ) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
AnnaBridge	171:3a7713b1edbc	1542
AnnaBridge	171:3a7713b1edbc	1543	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1544	* GPIO pin interrupt register block structure
AnnaBridge	171:3a7713b1edbc	1545	*/
AnnaBridge	171:3a7713b1edbc	1546	#define LPC_GPIO_PIN_INT_BASE 0x40087000
AnnaBridge	171:3a7713b1edbc	1547
AnnaBridge	171:3a7713b1edbc	1548	typedef struct { /* GPIO_PIN_INT Structure */
AnnaBridge	171:3a7713b1edbc	1549	__IO uint32_t ISEL; /* Pin Interrupt Mode register */
AnnaBridge	171:3a7713b1edbc	1550	__IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
AnnaBridge	171:3a7713b1edbc	1551	__O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
AnnaBridge	171:3a7713b1edbc	1552	__O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
AnnaBridge	171:3a7713b1edbc	1553	__IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
AnnaBridge	171:3a7713b1edbc	1554	__O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
AnnaBridge	171:3a7713b1edbc	1555	__O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
AnnaBridge	171:3a7713b1edbc	1556	__IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
AnnaBridge	171:3a7713b1edbc	1557	__IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
AnnaBridge	171:3a7713b1edbc	1558	__IO uint32_t IST; /* Pin Interrupt Status register */
AnnaBridge	171:3a7713b1edbc	1559	} LPC_GPIOPININT_T;
AnnaBridge	171:3a7713b1edbc	1560
AnnaBridge	171:3a7713b1edbc	1561	typedef enum LPC_GPIOPININT_MODE {
AnnaBridge	171:3a7713b1edbc	1562	GPIOPININT_RISING_EDGE = 0x01,
AnnaBridge	171:3a7713b1edbc	1563	GPIOPININT_FALLING_EDGE = 0x02,
AnnaBridge	171:3a7713b1edbc	1564	GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
AnnaBridge	171:3a7713b1edbc	1565	GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
AnnaBridge	171:3a7713b1edbc	1566	} LPC_GPIOPININT_MODE_T;
AnnaBridge	171:3a7713b1edbc	1567
AnnaBridge	171:3a7713b1edbc	1568	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1569	* GPIO grouped interrupt register block structure
AnnaBridge	171:3a7713b1edbc	1570	*/
AnnaBridge	171:3a7713b1edbc	1571	#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
AnnaBridge	171:3a7713b1edbc	1572	#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
AnnaBridge	171:3a7713b1edbc	1573
AnnaBridge	171:3a7713b1edbc	1574	typedef struct { /* GPIO_GROUP_INTn Structure */
AnnaBridge	171:3a7713b1edbc	1575	__IO uint32_t CTRL; /* GPIO grouped interrupt control register */
AnnaBridge	171:3a7713b1edbc	1576	__I uint32_t RESERVED0[7];
AnnaBridge	171:3a7713b1edbc	1577	__IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
AnnaBridge	171:3a7713b1edbc	1578	__IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
AnnaBridge	171:3a7713b1edbc	1579	} LPC_GPIOGROUPINT_T;
AnnaBridge	171:3a7713b1edbc	1580
AnnaBridge	171:3a7713b1edbc	1581	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1582	* Motor Control PWM register block structure
AnnaBridge	171:3a7713b1edbc	1583	*/
AnnaBridge	171:3a7713b1edbc	1584	#define LPC_MCPWM_BASE 0x400A0000
AnnaBridge	171:3a7713b1edbc	1585
AnnaBridge	171:3a7713b1edbc	1586	typedef struct { /* MCPWM Structure */
AnnaBridge	171:3a7713b1edbc	1587	__I uint32_t CON; /* PWM Control read address */
AnnaBridge	171:3a7713b1edbc	1588	__O uint32_t CON_SET; /* PWM Control set address */
AnnaBridge	171:3a7713b1edbc	1589	__O uint32_t CON_CLR; /* PWM Control clear address */
AnnaBridge	171:3a7713b1edbc	1590	__I uint32_t CAPCON; /* Capture Control read address */
AnnaBridge	171:3a7713b1edbc	1591	__O uint32_t CAPCON_SET; /* Capture Control set address */
AnnaBridge	171:3a7713b1edbc	1592	__O uint32_t CAPCON_CLR; /* Event Control clear address */
AnnaBridge	171:3a7713b1edbc	1593	__IO uint32_t TC[3]; /* Timer Counter register */
AnnaBridge	171:3a7713b1edbc	1594	__IO uint32_t LIM[3]; /* Limit register */
AnnaBridge	171:3a7713b1edbc	1595	__IO uint32_t MAT[3]; /* Match register */
AnnaBridge	171:3a7713b1edbc	1596	__IO uint32_t DT; /* Dead time register */
AnnaBridge	171:3a7713b1edbc	1597	__IO uint32_t CCP; /* Communication Pattern register */
AnnaBridge	171:3a7713b1edbc	1598	__I uint32_t CAP[3]; /* Capture register */
AnnaBridge	171:3a7713b1edbc	1599	__I uint32_t INTEN; /* Interrupt Enable read address */
AnnaBridge	171:3a7713b1edbc	1600	__O uint32_t INTEN_SET; /* Interrupt Enable set address */
AnnaBridge	171:3a7713b1edbc	1601	__O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
AnnaBridge	171:3a7713b1edbc	1602	__I uint32_t CNTCON; /* Count Control read address */
AnnaBridge	171:3a7713b1edbc	1603	__O uint32_t CNTCON_SET; /* Count Control set address */
AnnaBridge	171:3a7713b1edbc	1604	__O uint32_t CNTCON_CLR; /* Count Control clear address */
AnnaBridge	171:3a7713b1edbc	1605	__I uint32_t INTF; /* Interrupt flags read address */
AnnaBridge	171:3a7713b1edbc	1606	__O uint32_t INTF_SET; /* Interrupt flags set address */
AnnaBridge	171:3a7713b1edbc	1607	__O uint32_t INTF_CLR; /* Interrupt flags clear address */
AnnaBridge	171:3a7713b1edbc	1608	__O uint32_t CAP_CLR; /* Capture clear address */
AnnaBridge	171:3a7713b1edbc	1609	} LPC_MCPWM_T;
AnnaBridge	171:3a7713b1edbc	1610
AnnaBridge	171:3a7713b1edbc	1611	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1612	* I2C register block structure
AnnaBridge	171:3a7713b1edbc	1613	*/
AnnaBridge	171:3a7713b1edbc	1614	#define LPC_I2C0_BASE 0x400A1000
AnnaBridge	171:3a7713b1edbc	1615	#define LPC_I2C1_BASE 0x400E0000
AnnaBridge	171:3a7713b1edbc	1616
AnnaBridge	171:3a7713b1edbc	1617	typedef struct { /* I2C0 Structure */
AnnaBridge	171:3a7713b1edbc	1618	__IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
AnnaBridge	171:3a7713b1edbc	1619	__I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
AnnaBridge	171:3a7713b1edbc	1620	__IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
AnnaBridge	171:3a7713b1edbc	1621	__IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
AnnaBridge	171:3a7713b1edbc	1622	__IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
AnnaBridge	171:3a7713b1edbc	1623	__IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
AnnaBridge	171:3a7713b1edbc	1624	__O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
AnnaBridge	171:3a7713b1edbc	1625	__IO uint32_t MMCTRL; /* Monitor mode control register. */
AnnaBridge	171:3a7713b1edbc	1626	__IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
AnnaBridge	171:3a7713b1edbc	1627	__IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
AnnaBridge	171:3a7713b1edbc	1628	__IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
AnnaBridge	171:3a7713b1edbc	1629	__I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
AnnaBridge	171:3a7713b1edbc	1630	__IO uint32_t MASK[4]; /* I2C Slave address mask register */
AnnaBridge	171:3a7713b1edbc	1631	} LPC_I2C_T;
AnnaBridge	171:3a7713b1edbc	1632
AnnaBridge	171:3a7713b1edbc	1633	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1634	* I2S register block structure
AnnaBridge	171:3a7713b1edbc	1635	*/
AnnaBridge	171:3a7713b1edbc	1636	#define LPC_I2S0_BASE 0x400A2000
AnnaBridge	171:3a7713b1edbc	1637	#define LPC_I2S1_BASE 0x400A3000
AnnaBridge	171:3a7713b1edbc	1638
AnnaBridge	171:3a7713b1edbc	1639	typedef struct { /* I2S Structure */
AnnaBridge	171:3a7713b1edbc	1640	__IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
AnnaBridge	171:3a7713b1edbc	1641	__IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
AnnaBridge	171:3a7713b1edbc	1642	__O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
AnnaBridge	171:3a7713b1edbc	1643	__I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
AnnaBridge	171:3a7713b1edbc	1644	__I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
AnnaBridge	171:3a7713b1edbc	1645	__IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
AnnaBridge	171:3a7713b1edbc	1646	__IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
AnnaBridge	171:3a7713b1edbc	1647	__IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
AnnaBridge	171:3a7713b1edbc	1648	__IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
AnnaBridge	171:3a7713b1edbc	1649	__IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
AnnaBridge	171:3a7713b1edbc	1650	__IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
AnnaBridge	171:3a7713b1edbc	1651	__IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
AnnaBridge	171:3a7713b1edbc	1652	__IO uint32_t TXMODE; /* I2S Transmit mode control */
AnnaBridge	171:3a7713b1edbc	1653	__IO uint32_t RXMODE; /* I2S Receive mode control */
AnnaBridge	171:3a7713b1edbc	1654	} LPC_I2S_T;
AnnaBridge	171:3a7713b1edbc	1655
AnnaBridge	171:3a7713b1edbc	1656	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1657	* CCAN Controller Area Network register block structure
AnnaBridge	171:3a7713b1edbc	1658	*/
AnnaBridge	171:3a7713b1edbc	1659	#define LPC_C_CAN1_BASE 0x400A4000
AnnaBridge	171:3a7713b1edbc	1660	#define LPC_C_CAN0_BASE 0x400E2000
AnnaBridge	171:3a7713b1edbc	1661
AnnaBridge	171:3a7713b1edbc	1662	typedef struct { /* C_CAN message interface Structure */
AnnaBridge	171:3a7713b1edbc	1663	__IO uint32_t IF_CMDREQ; /* Message interface command request */
AnnaBridge	171:3a7713b1edbc	1664	union {
AnnaBridge	171:3a7713b1edbc	1665	__IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
AnnaBridge	171:3a7713b1edbc	1666	__IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
AnnaBridge	171:3a7713b1edbc	1667	};
AnnaBridge	171:3a7713b1edbc	1668
AnnaBridge	171:3a7713b1edbc	1669	__IO uint32_t IF_MSK1; /* Message interface mask 1 */
AnnaBridge	171:3a7713b1edbc	1670	__IO uint32_t IF_MSK2; /* Message interface mask 2 */
AnnaBridge	171:3a7713b1edbc	1671	__IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
AnnaBridge	171:3a7713b1edbc	1672	__IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
AnnaBridge	171:3a7713b1edbc	1673	__IO uint32_t IF_MCTRL; /* Message interface message control */
AnnaBridge	171:3a7713b1edbc	1674	__IO uint32_t IF_DA1; /* Message interface data A1 */
AnnaBridge	171:3a7713b1edbc	1675	__IO uint32_t IF_DA2; /* Message interface data A2 */
AnnaBridge	171:3a7713b1edbc	1676	__IO uint32_t IF_DB1; /* Message interface data B1 */
AnnaBridge	171:3a7713b1edbc	1677	__IO uint32_t IF_DB2; /* Message interface data B2 */
AnnaBridge	171:3a7713b1edbc	1678	__I uint32_t RESERVED[13];
AnnaBridge	171:3a7713b1edbc	1679	} LPC_CCAN_IF_T;
AnnaBridge	171:3a7713b1edbc	1680
AnnaBridge	171:3a7713b1edbc	1681	typedef struct { /* C_CAN Structure */
AnnaBridge	171:3a7713b1edbc	1682	__IO uint32_t CNTL; /* CAN control */
AnnaBridge	171:3a7713b1edbc	1683	__IO uint32_t STAT; /* Status register */
AnnaBridge	171:3a7713b1edbc	1684	__I uint32_t EC; /* Error counter */
AnnaBridge	171:3a7713b1edbc	1685	__IO uint32_t BT; /* Bit timing register */
AnnaBridge	171:3a7713b1edbc	1686	__I uint32_t INT; /* Interrupt register */
AnnaBridge	171:3a7713b1edbc	1687	__IO uint32_t TEST; /* Test register */
AnnaBridge	171:3a7713b1edbc	1688	__IO uint32_t BRPE; /* Baud rate prescaler extension register */
AnnaBridge	171:3a7713b1edbc	1689	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1690	LPC_CCAN_IF_T IF[2];
AnnaBridge	171:3a7713b1edbc	1691	__I uint32_t RESERVED2[8];
AnnaBridge	171:3a7713b1edbc	1692	__I uint32_t TXREQ1; /* Transmission request 1 */
AnnaBridge	171:3a7713b1edbc	1693	__I uint32_t TXREQ2; /* Transmission request 2 */
AnnaBridge	171:3a7713b1edbc	1694	__I uint32_t RESERVED3[6];
AnnaBridge	171:3a7713b1edbc	1695	__I uint32_t ND1; /* New data 1 */
AnnaBridge	171:3a7713b1edbc	1696	__I uint32_t ND2; /* New data 2 */
AnnaBridge	171:3a7713b1edbc	1697	__I uint32_t RESERVED4[6];
AnnaBridge	171:3a7713b1edbc	1698	__I uint32_t IR1; /* Interrupt pending 1 */
AnnaBridge	171:3a7713b1edbc	1699	__I uint32_t IR2; /* Interrupt pending 2 */
AnnaBridge	171:3a7713b1edbc	1700	__I uint32_t RESERVED5[6];
AnnaBridge	171:3a7713b1edbc	1701	__I uint32_t MSGV1; /* Message valid 1 */
AnnaBridge	171:3a7713b1edbc	1702	__I uint32_t MSGV2; /* Message valid 2 */
AnnaBridge	171:3a7713b1edbc	1703	__I uint32_t RESERVED6[6];
AnnaBridge	171:3a7713b1edbc	1704	__IO uint32_t CLKDIV; /* CAN clock divider register */
AnnaBridge	171:3a7713b1edbc	1705	} LPC_CCAN_T;
AnnaBridge	171:3a7713b1edbc	1706
AnnaBridge	171:3a7713b1edbc	1707	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1708	* Repetitive Interrupt Timer register block structure
AnnaBridge	171:3a7713b1edbc	1709	*/
AnnaBridge	171:3a7713b1edbc	1710	#define LPC_RITIMER_BASE 0x400C0000
AnnaBridge	171:3a7713b1edbc	1711
AnnaBridge	171:3a7713b1edbc	1712	typedef struct { /* RITIMER Structure */
AnnaBridge	171:3a7713b1edbc	1713	__IO uint32_t COMPVAL; /* Compare register */
AnnaBridge	171:3a7713b1edbc	1714	__IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
AnnaBridge	171:3a7713b1edbc	1715	__IO uint32_t CTRL; /* Control register. */
AnnaBridge	171:3a7713b1edbc	1716	__IO uint32_t COUNTER; /* 32-bit counter */
AnnaBridge	171:3a7713b1edbc	1717	} LPC_RITIMER_T;
AnnaBridge	171:3a7713b1edbc	1718
AnnaBridge	171:3a7713b1edbc	1719	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1720	* Quadrature Encoder Interface register block structure
AnnaBridge	171:3a7713b1edbc	1721	*/
AnnaBridge	171:3a7713b1edbc	1722	#define LPC_QEI_BASE 0x400C6000
AnnaBridge	171:3a7713b1edbc	1723
AnnaBridge	171:3a7713b1edbc	1724	typedef struct { /* QEI Structure */
AnnaBridge	171:3a7713b1edbc	1725	__O uint32_t CON; /* Control register */
AnnaBridge	171:3a7713b1edbc	1726	__I uint32_t STAT; /* Encoder status register */
AnnaBridge	171:3a7713b1edbc	1727	__IO uint32_t CONF; /* Configuration register */
AnnaBridge	171:3a7713b1edbc	1728	__I uint32_t POS; /* Position register */
AnnaBridge	171:3a7713b1edbc	1729	__IO uint32_t MAXPOS; /* Maximum position register */
AnnaBridge	171:3a7713b1edbc	1730	__IO uint32_t CMPOS0; /* position compare register 0 */
AnnaBridge	171:3a7713b1edbc	1731	__IO uint32_t CMPOS1; /* position compare register 1 */
AnnaBridge	171:3a7713b1edbc	1732	__IO uint32_t CMPOS2; /* position compare register 2 */
AnnaBridge	171:3a7713b1edbc	1733	__I uint32_t INXCNT; /* Index count register */
AnnaBridge	171:3a7713b1edbc	1734	__IO uint32_t INXCMP0; /* Index compare register 0 */
AnnaBridge	171:3a7713b1edbc	1735	__IO uint32_t LOAD; /* Velocity timer reload register */
AnnaBridge	171:3a7713b1edbc	1736	__I uint32_t TIME; /* Velocity timer register */
AnnaBridge	171:3a7713b1edbc	1737	__I uint32_t VEL; /* Velocity counter register */
AnnaBridge	171:3a7713b1edbc	1738	__I uint32_t CAP; /* Velocity capture register */
AnnaBridge	171:3a7713b1edbc	1739	__IO uint32_t VELCOMP; /* Velocity compare register */
AnnaBridge	171:3a7713b1edbc	1740	__IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
AnnaBridge	171:3a7713b1edbc	1741	__IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
AnnaBridge	171:3a7713b1edbc	1742	__IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
AnnaBridge	171:3a7713b1edbc	1743	__IO uint32_t WINDOW; /* Index acceptance window register */
AnnaBridge	171:3a7713b1edbc	1744	__IO uint32_t INXCMP1; /* Index compare register 1 */
AnnaBridge	171:3a7713b1edbc	1745	__IO uint32_t INXCMP2; /* Index compare register 2 */
AnnaBridge	171:3a7713b1edbc	1746	__I uint32_t RESERVED0[993];
AnnaBridge	171:3a7713b1edbc	1747	__O uint32_t IEC; /* Interrupt enable clear register */
AnnaBridge	171:3a7713b1edbc	1748	__O uint32_t IES; /* Interrupt enable set register */
AnnaBridge	171:3a7713b1edbc	1749	__I uint32_t INTSTAT; /* Interrupt status register */
AnnaBridge	171:3a7713b1edbc	1750	__I uint32_t IE; /* Interrupt enable register */
AnnaBridge	171:3a7713b1edbc	1751	__O uint32_t CLR; /* Interrupt status clear register */
AnnaBridge	171:3a7713b1edbc	1752	__O uint32_t SET; /* Interrupt status set register */
AnnaBridge	171:3a7713b1edbc	1753	} LPC_QEI_T;
AnnaBridge	171:3a7713b1edbc	1754
AnnaBridge	171:3a7713b1edbc	1755	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1756	* Global Input Multiplexer Array (GIMA) register block structure
AnnaBridge	171:3a7713b1edbc	1757	*/
AnnaBridge	171:3a7713b1edbc	1758	#define LPC_GIMA_BASE 0x400C7000
AnnaBridge	171:3a7713b1edbc	1759
AnnaBridge	171:3a7713b1edbc	1760	typedef struct { /* GIMA Structure */
AnnaBridge	171:3a7713b1edbc	1761	__IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x4)+y)) /
AnnaBridge	171:3a7713b1edbc	1762	__IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
AnnaBridge	171:3a7713b1edbc	1763	__IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
AnnaBridge	171:3a7713b1edbc	1764	__IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
AnnaBridge	171:3a7713b1edbc	1765	__IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
AnnaBridge	171:3a7713b1edbc	1766	__IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
AnnaBridge	171:3a7713b1edbc	1767	__IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
AnnaBridge	171:3a7713b1edbc	1768	__IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
AnnaBridge	171:3a7713b1edbc	1769	} LPC_GIMA_T;
AnnaBridge	171:3a7713b1edbc	1770
AnnaBridge	171:3a7713b1edbc	1771	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1772	* DAC register block structure
AnnaBridge	171:3a7713b1edbc	1773	*/
AnnaBridge	171:3a7713b1edbc	1774	#define LPC_DAC_BASE 0x400E1000
AnnaBridge	171:3a7713b1edbc	1775
AnnaBridge	171:3a7713b1edbc	1776	typedef struct { /* DAC Structure */
AnnaBridge	171:3a7713b1edbc	1777	__IO uint32_t CR; /* DAC register. Holds the conversion data. */
AnnaBridge	171:3a7713b1edbc	1778	__IO uint32_t CTRL; /* DAC control register. */
AnnaBridge	171:3a7713b1edbc	1779	__IO uint32_t CNTVAL; /* DAC counter value register. */
AnnaBridge	171:3a7713b1edbc	1780	} LPC_DAC_T;
AnnaBridge	171:3a7713b1edbc	1781
AnnaBridge	171:3a7713b1edbc	1782	/* After the selected settling time after this field is written with a
AnnaBridge	171:3a7713b1edbc	1783	* new VALUE, the voltage on the AOUT pin (with respect to VSSA)
AnnaBridge	171:3a7713b1edbc	1784	* is VALUE/1024 ? VREF
AnnaBridge	171:3a7713b1edbc	1785	*/
AnnaBridge	171:3a7713b1edbc	1786	#define DAC_RANGE 0x3FF
AnnaBridge	171:3a7713b1edbc	1787	#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
AnnaBridge	171:3a7713b1edbc	1788	#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
AnnaBridge	171:3a7713b1edbc	1789	#define DAC_VALUE(n) DAC_SET(n)
AnnaBridge	171:3a7713b1edbc	1790	/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
AnnaBridge	171:3a7713b1edbc	1791	* and the maximum current is 700 microAmpere
AnnaBridge	171:3a7713b1edbc	1792	* If this bit = 1: The settling time of the DAC is 2.5 microsecond
AnnaBridge	171:3a7713b1edbc	1793	* and the maximum current is 350 microAmpere
AnnaBridge	171:3a7713b1edbc	1794	*/
AnnaBridge	171:3a7713b1edbc	1795	#define DAC_BIAS_EN ((uint32_t) (1 << 16))
AnnaBridge	171:3a7713b1edbc	1796	/* Value to reload interrupt DMA counter */
AnnaBridge	171:3a7713b1edbc	1797	#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
AnnaBridge	171:3a7713b1edbc	1798
AnnaBridge	171:3a7713b1edbc	1799	#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
AnnaBridge	171:3a7713b1edbc	1800	#define DAC_CNT_ENA ((uint32_t) (1 << 2))
AnnaBridge	171:3a7713b1edbc	1801	#define DAC_DMA_ENA ((uint32_t) (1 << 3))
AnnaBridge	171:3a7713b1edbc	1802	#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
AnnaBridge	171:3a7713b1edbc	1803
AnnaBridge	171:3a7713b1edbc	1804	/* Current option in DAC configuration option */
AnnaBridge	171:3a7713b1edbc	1805	typedef enum DAC_CURRENT_OPT {
AnnaBridge	171:3a7713b1edbc	1806	DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
AnnaBridge	171:3a7713b1edbc	1807	allows for a maximum update rate of 1 MHz */
AnnaBridge	171:3a7713b1edbc	1808	DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
AnnaBridge	171:3a7713b1edbc	1809	allows for a maximum update rate of 400 kHz */
AnnaBridge	171:3a7713b1edbc	1810	} DAC_CURRENT_OPT_T;
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1813	* ADC register block structure
AnnaBridge	171:3a7713b1edbc	1814	*/
AnnaBridge	171:3a7713b1edbc	1815	#define LPC_ADC0_BASE 0x400E3000
AnnaBridge	171:3a7713b1edbc	1816	#define LPC_ADC1_BASE 0x400E4000
AnnaBridge	171:3a7713b1edbc	1817	#define ADC_ACC_10BITS
AnnaBridge	171:3a7713b1edbc	1818
AnnaBridge	171:3a7713b1edbc	1819	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1820	* 10 or 12-bit ADC register block structure
AnnaBridge	171:3a7713b1edbc	1821	*/
AnnaBridge	171:3a7713b1edbc	1822	typedef struct { /* ADCn Structure */
AnnaBridge	171:3a7713b1edbc	1823	__IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
AnnaBridge	171:3a7713b1edbc	1824	__I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
AnnaBridge	171:3a7713b1edbc	1825	__I uint32_t RESERVED0;
AnnaBridge	171:3a7713b1edbc	1826	__IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
AnnaBridge	171:3a7713b1edbc	1827	__I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
AnnaBridge	171:3a7713b1edbc	1828	__I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
AnnaBridge	171:3a7713b1edbc	1829	} LPC_ADC_T;
AnnaBridge	171:3a7713b1edbc	1830
AnnaBridge	171:3a7713b1edbc	1831	/* ADC register support bitfields and mask */
AnnaBridge	171:3a7713b1edbc	1832	#define ADC_RANGE 0x3FF
AnnaBridge	171:3a7713b1edbc	1833	#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
AnnaBridge	171:3a7713b1edbc	1834	#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
AnnaBridge	171:3a7713b1edbc	1835	#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
AnnaBridge	171:3a7713b1edbc	1836	#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
AnnaBridge	171:3a7713b1edbc	1837	#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
AnnaBridge	171:3a7713b1edbc	1838	#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
AnnaBridge	171:3a7713b1edbc	1839	#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
AnnaBridge	171:3a7713b1edbc	1840	#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
AnnaBridge	171:3a7713b1edbc	1841	#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
AnnaBridge	171:3a7713b1edbc	1842	#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
AnnaBridge	171:3a7713b1edbc	1843	#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
AnnaBridge	171:3a7713b1edbc	1844	#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
AnnaBridge	171:3a7713b1edbc	1845	#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
AnnaBridge	171:3a7713b1edbc	1846	#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
AnnaBridge	171:3a7713b1edbc	1847	#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
AnnaBridge	171:3a7713b1edbc	1848	#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
AnnaBridge	171:3a7713b1edbc	1849	#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
AnnaBridge	171:3a7713b1edbc	1850	#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) \| ADC_CR_BITACC(0x07) \| ADC_CR_PDN)
AnnaBridge	171:3a7713b1edbc	1851
AnnaBridge	171:3a7713b1edbc	1852	/* ADC status register used for IP drivers */
AnnaBridge	171:3a7713b1edbc	1853	typedef enum ADC_STATUS {
AnnaBridge	171:3a7713b1edbc	1854	ADC_DR_DONE_STAT, /* ADC data register staus */
AnnaBridge	171:3a7713b1edbc	1855	ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
AnnaBridge	171:3a7713b1edbc	1856	ADC_DR_ADINT_STAT /* ADC interrupt status */
AnnaBridge	171:3a7713b1edbc	1857	} ADC_STATUS_T;
AnnaBridge	171:3a7713b1edbc	1858
AnnaBridge	171:3a7713b1edbc	1859	/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
AnnaBridge	171:3a7713b1edbc	1860	typedef enum ADC_START_MODE {
AnnaBridge	171:3a7713b1edbc	1861	ADC_NO_START = 0,
AnnaBridge	171:3a7713b1edbc	1862	ADC_START_NOW, /* Start conversion now */
AnnaBridge	171:3a7713b1edbc	1863	ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
AnnaBridge	171:3a7713b1edbc	1864	ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
AnnaBridge	171:3a7713b1edbc	1865	ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
AnnaBridge	171:3a7713b1edbc	1866	ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
AnnaBridge	171:3a7713b1edbc	1867	ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
AnnaBridge	171:3a7713b1edbc	1868	} ADC_START_MODE_T;
AnnaBridge	171:3a7713b1edbc	1869
AnnaBridge	171:3a7713b1edbc	1870	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1871	* GPIO port register block structure
AnnaBridge	171:3a7713b1edbc	1872	*/
AnnaBridge	171:3a7713b1edbc	1873	#define LPC_GPIO_PORT_BASE 0x400F4000
AnnaBridge	171:3a7713b1edbc	1874	#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
AnnaBridge	171:3a7713b1edbc	1875	#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
AnnaBridge	171:3a7713b1edbc	1876	#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
AnnaBridge	171:3a7713b1edbc	1877	#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
AnnaBridge	171:3a7713b1edbc	1878	#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
AnnaBridge	171:3a7713b1edbc	1879	#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
AnnaBridge	171:3a7713b1edbc	1880	#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
AnnaBridge	171:3a7713b1edbc	1881	#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
AnnaBridge	171:3a7713b1edbc	1882
AnnaBridge	171:3a7713b1edbc	1883	typedef struct { /* GPIO_PORT Structure */
AnnaBridge	171:3a7713b1edbc	1884	__IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
AnnaBridge	171:3a7713b1edbc	1885	__IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
AnnaBridge	171:3a7713b1edbc	1886	__IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
AnnaBridge	171:3a7713b1edbc	1887	__IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
AnnaBridge	171:3a7713b1edbc	1888	__IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
AnnaBridge	171:3a7713b1edbc	1889	__IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
AnnaBridge	171:3a7713b1edbc	1890	__IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
AnnaBridge	171:3a7713b1edbc	1891	__O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
AnnaBridge	171:3a7713b1edbc	1892	__O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
AnnaBridge	171:3a7713b1edbc	1893	} LPC_GPIO_T;
AnnaBridge	171:3a7713b1edbc	1894
AnnaBridge	171:3a7713b1edbc	1895	/* Calculate GPIO offset and port register address from group and pin number */
AnnaBridge	171:3a7713b1edbc	1896	#define GPIO_OFF(port, pin) ((port << 5) + pin)
AnnaBridge	171:3a7713b1edbc	1897	#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
AnnaBridge	171:3a7713b1edbc	1898
AnnaBridge	171:3a7713b1edbc	1899	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1900	* SPI register block structure
AnnaBridge	171:3a7713b1edbc	1901	*/
AnnaBridge	171:3a7713b1edbc	1902	#define LPC_SPI_BASE 0x40100000
AnnaBridge	171:3a7713b1edbc	1903
AnnaBridge	171:3a7713b1edbc	1904	typedef struct { /* SPI Structure */
AnnaBridge	171:3a7713b1edbc	1905	__IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
AnnaBridge	171:3a7713b1edbc	1906	__I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
AnnaBridge	171:3a7713b1edbc	1907	__IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
AnnaBridge	171:3a7713b1edbc	1908	__IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
AnnaBridge	171:3a7713b1edbc	1909	__I uint32_t RESERVED0[3];
AnnaBridge	171:3a7713b1edbc	1910	__IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
AnnaBridge	171:3a7713b1edbc	1911	} LPC_SPI_T;
AnnaBridge	171:3a7713b1edbc	1912
AnnaBridge	171:3a7713b1edbc	1913	/* SPI CFG Register BitMask */
AnnaBridge	171:3a7713b1edbc	1914	#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
AnnaBridge	171:3a7713b1edbc	1915	/* Enable of controlling the number of bits per transfer */
AnnaBridge	171:3a7713b1edbc	1916	#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
AnnaBridge	171:3a7713b1edbc	1917	/* Mask of field of bit controlling */
AnnaBridge	171:3a7713b1edbc	1918	#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
AnnaBridge	171:3a7713b1edbc	1919	/* Set the number of bits per a transfer */
AnnaBridge	171:3a7713b1edbc	1920	#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
AnnaBridge	171:3a7713b1edbc	1921	/* SPI Clock Phase Select*/
AnnaBridge	171:3a7713b1edbc	1922	#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /Capture data on the first edge, Change data on the following edge/
AnnaBridge	171:3a7713b1edbc	1923	#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
AnnaBridge	171:3a7713b1edbc	1924	/* SPI Clock Polarity Select*/
AnnaBridge	171:3a7713b1edbc	1925	#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
AnnaBridge	171:3a7713b1edbc	1926	#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
AnnaBridge	171:3a7713b1edbc	1927	/* SPI Slave Mode Select */
AnnaBridge	171:3a7713b1edbc	1928	#define SPI_CR_SLAVE_EN ((uint32_t) 0)
AnnaBridge	171:3a7713b1edbc	1929	/* SPI Master Mode Select */
AnnaBridge	171:3a7713b1edbc	1930	#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
AnnaBridge	171:3a7713b1edbc	1931	/* SPI MSB First mode enable */
AnnaBridge	171:3a7713b1edbc	1932	#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
AnnaBridge	171:3a7713b1edbc	1933	/* SPI LSB First mode enable */
AnnaBridge	171:3a7713b1edbc	1934	#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
AnnaBridge	171:3a7713b1edbc	1935	/* SPI interrupt enable */
AnnaBridge	171:3a7713b1edbc	1936	#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
AnnaBridge	171:3a7713b1edbc	1937	/* SPI STAT Register BitMask */
AnnaBridge	171:3a7713b1edbc	1938	#define SPI_SR_BITMASK ((uint32_t) 0xF8)
AnnaBridge	171:3a7713b1edbc	1939	/* Slave abort Flag */
AnnaBridge	171:3a7713b1edbc	1940	#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
AnnaBridge	171:3a7713b1edbc	1941	/* Mode fault Flag */
AnnaBridge	171:3a7713b1edbc	1942	#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
AnnaBridge	171:3a7713b1edbc	1943	/* Read overrun flag*/
AnnaBridge	171:3a7713b1edbc	1944	#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
AnnaBridge	171:3a7713b1edbc	1945	/* Write collision flag. */
AnnaBridge	171:3a7713b1edbc	1946	#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
AnnaBridge	171:3a7713b1edbc	1947	/* SPI transfer complete flag. */
AnnaBridge	171:3a7713b1edbc	1948	#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
AnnaBridge	171:3a7713b1edbc	1949	/* SPI error flag */
AnnaBridge	171:3a7713b1edbc	1950	#define SPI_SR_ERROR (SPI_SR_ABRT \| SPI_SR_MODF \| SPI_SR_ROVR \| SPI_SR_WCOL)
AnnaBridge	171:3a7713b1edbc	1951	/* Enable SPI Test Mode */
AnnaBridge	171:3a7713b1edbc	1952	#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
AnnaBridge	171:3a7713b1edbc	1953	/* SPI interrupt flag */
AnnaBridge	171:3a7713b1edbc	1954	#define SPI_INT_SPIF ((uint32_t) (1 << 0))
AnnaBridge	171:3a7713b1edbc	1955	/* Receiver Data */
AnnaBridge	171:3a7713b1edbc	1956	#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
AnnaBridge	171:3a7713b1edbc	1957
AnnaBridge	171:3a7713b1edbc	1958	/* SPI Mode*/
AnnaBridge	171:3a7713b1edbc	1959	typedef enum LPC_SPI_MODE {
AnnaBridge	171:3a7713b1edbc	1960	SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
AnnaBridge	171:3a7713b1edbc	1961	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
AnnaBridge	171:3a7713b1edbc	1962	} LPC_SPI_MODE_T;
AnnaBridge	171:3a7713b1edbc	1963
AnnaBridge	171:3a7713b1edbc	1964	/* SPI Clock Mode*/
AnnaBridge	171:3a7713b1edbc	1965	typedef enum LPC_SPI_CLOCK_MODE {
AnnaBridge	171:3a7713b1edbc	1966	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
AnnaBridge	171:3a7713b1edbc	1967	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
AnnaBridge	171:3a7713b1edbc	1968	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
AnnaBridge	171:3a7713b1edbc	1969	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
AnnaBridge	171:3a7713b1edbc	1970	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
AnnaBridge	171:3a7713b1edbc	1971	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
AnnaBridge	171:3a7713b1edbc	1972	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
AnnaBridge	171:3a7713b1edbc	1973	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
AnnaBridge	171:3a7713b1edbc	1974	} LPC_SPI_CLOCK_MODE_T;
AnnaBridge	171:3a7713b1edbc	1975
AnnaBridge	171:3a7713b1edbc	1976	/* SPI Data Order Mode*/
AnnaBridge	171:3a7713b1edbc	1977	typedef enum LPC_SPI_DATA_ORDER {
AnnaBridge	171:3a7713b1edbc	1978	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
AnnaBridge	171:3a7713b1edbc	1979	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
AnnaBridge	171:3a7713b1edbc	1980	} LPC_SPI_DATA_ORDER_T;
AnnaBridge	171:3a7713b1edbc	1981
AnnaBridge	171:3a7713b1edbc	1982	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1983	* Serial GPIO register block structure
AnnaBridge	171:3a7713b1edbc	1984	*/
AnnaBridge	171:3a7713b1edbc	1985	#define LPC_SGPIO_BASE 0x40101000
AnnaBridge	171:3a7713b1edbc	1986
AnnaBridge	171:3a7713b1edbc	1987	typedef struct { /* SGPIO Structure */
AnnaBridge	171:3a7713b1edbc	1988	__IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
AnnaBridge	171:3a7713b1edbc	1989	__IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
AnnaBridge	171:3a7713b1edbc	1990	__IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
AnnaBridge	171:3a7713b1edbc	1991	__IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
AnnaBridge	171:3a7713b1edbc	1992	__IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
AnnaBridge	171:3a7713b1edbc	1993	__IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
AnnaBridge	171:3a7713b1edbc	1994	__IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
AnnaBridge	171:3a7713b1edbc	1995	__IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
AnnaBridge	171:3a7713b1edbc	1996	__IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
AnnaBridge	171:3a7713b1edbc	1997	__IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
AnnaBridge	171:3a7713b1edbc	1998	__IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
AnnaBridge	171:3a7713b1edbc	1999	__IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
AnnaBridge	171:3a7713b1edbc	2000	__I uint32_t GPIO_INREG; /* GPIO input status register */
AnnaBridge	171:3a7713b1edbc	2001	__IO uint32_t GPIO_OUTREG; /* GPIO output control register */
AnnaBridge	171:3a7713b1edbc	2002	__IO uint32_t GPIO_OENREG; /* GPIO OE control register */
AnnaBridge	171:3a7713b1edbc	2003	__IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
AnnaBridge	171:3a7713b1edbc	2004	__IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
AnnaBridge	171:3a7713b1edbc	2005	__I uint32_t RESERVED0[823];
AnnaBridge	171:3a7713b1edbc	2006	__O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
AnnaBridge	171:3a7713b1edbc	2007	__O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
AnnaBridge	171:3a7713b1edbc	2008	__I uint32_t ENABLE_0; /* Shift clock interrupt enable */
AnnaBridge	171:3a7713b1edbc	2009	__I uint32_t STATUS_0; /* Shift clock interrupt status */
AnnaBridge	171:3a7713b1edbc	2010	__O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
AnnaBridge	171:3a7713b1edbc	2011	__O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
AnnaBridge	171:3a7713b1edbc	2012	__I uint32_t RESERVED1[2];
AnnaBridge	171:3a7713b1edbc	2013	__O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
AnnaBridge	171:3a7713b1edbc	2014	__O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
AnnaBridge	171:3a7713b1edbc	2015	__I uint32_t ENABLE_1; /* Capture clock interrupt enable */
AnnaBridge	171:3a7713b1edbc	2016	__I uint32_t STATUS_1; /* Capture clock interrupt status */
AnnaBridge	171:3a7713b1edbc	2017	__O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
AnnaBridge	171:3a7713b1edbc	2018	__O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
AnnaBridge	171:3a7713b1edbc	2019	__I uint32_t RESERVED2[2];
AnnaBridge	171:3a7713b1edbc	2020	__O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
AnnaBridge	171:3a7713b1edbc	2021	__O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
AnnaBridge	171:3a7713b1edbc	2022	__I uint32_t ENABLE_2; /* Pattern match interrupt enable */
AnnaBridge	171:3a7713b1edbc	2023	__I uint32_t STATUS_2; /* Pattern match interrupt status */
AnnaBridge	171:3a7713b1edbc	2024	__O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
AnnaBridge	171:3a7713b1edbc	2025	__O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
AnnaBridge	171:3a7713b1edbc	2026	__I uint32_t RESERVED3[2];
AnnaBridge	171:3a7713b1edbc	2027	__O uint32_t CLR_EN_3; /* Input interrupt clear mask */
AnnaBridge	171:3a7713b1edbc	2028	__O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
AnnaBridge	171:3a7713b1edbc	2029	__I uint32_t ENABLE_3; /* Input bit match interrupt enable */
AnnaBridge	171:3a7713b1edbc	2030	__I uint32_t STATUS_3; /* Input bit match interrupt status */
AnnaBridge	171:3a7713b1edbc	2031	__O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
AnnaBridge	171:3a7713b1edbc	2032	__O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
AnnaBridge	171:3a7713b1edbc	2033	} LPC_SGPIO_T;
AnnaBridge	171:3a7713b1edbc	2034
AnnaBridge	171:3a7713b1edbc	2035	/* End of section using anonymous unions */
AnnaBridge	171:3a7713b1edbc	2036	#if defined(__ARMCC_VERSION)
AnnaBridge	171:3a7713b1edbc	2037	#pragma pop
AnnaBridge	171:3a7713b1edbc	2038	#elif defined(__CWCC__)
AnnaBridge	171:3a7713b1edbc	2039	#pragma pop
AnnaBridge	171:3a7713b1edbc	2040	#elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge	171:3a7713b1edbc	2041	//#pragma pop // FIXME not usable for IAR
AnnaBridge	171:3a7713b1edbc	2042	#else /* defined(__GNUC__) and others */
AnnaBridge	171:3a7713b1edbc	2043	/* Leave anonymous unions enabled */
AnnaBridge	171:3a7713b1edbc	2044	#endif
AnnaBridge	171:3a7713b1edbc	2045
AnnaBridge	171:3a7713b1edbc	2046	/* ---------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2047	* LPC43xx Peripheral register set declarations
AnnaBridge	171:3a7713b1edbc	2048	*/
AnnaBridge	171:3a7713b1edbc	2049	#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
AnnaBridge	171:3a7713b1edbc	2050	#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
AnnaBridge	171:3a7713b1edbc	2051	#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
AnnaBridge	171:3a7713b1edbc	2052	#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
AnnaBridge	171:3a7713b1edbc	2053	#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
AnnaBridge	171:3a7713b1edbc	2054	#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
AnnaBridge	171:3a7713b1edbc	2055	#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
AnnaBridge	171:3a7713b1edbc	2056	#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
AnnaBridge	171:3a7713b1edbc	2057	#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
AnnaBridge	171:3a7713b1edbc	2058	#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
AnnaBridge	171:3a7713b1edbc	2059	#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
AnnaBridge	171:3a7713b1edbc	2060	#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
AnnaBridge	171:3a7713b1edbc	2061	#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
AnnaBridge	171:3a7713b1edbc	2062	#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
AnnaBridge	171:3a7713b1edbc	2063	#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
AnnaBridge	171:3a7713b1edbc	2064	#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
AnnaBridge	171:3a7713b1edbc	2065	#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
AnnaBridge	171:3a7713b1edbc	2066	#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
AnnaBridge	171:3a7713b1edbc	2067	#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
AnnaBridge	171:3a7713b1edbc	2068	#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
AnnaBridge	171:3a7713b1edbc	2069	#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
AnnaBridge	171:3a7713b1edbc	2070	#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
AnnaBridge	171:3a7713b1edbc	2071	#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
AnnaBridge	171:3a7713b1edbc	2072	#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
AnnaBridge	171:3a7713b1edbc	2073	#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
AnnaBridge	171:3a7713b1edbc	2074	#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
AnnaBridge	171:3a7713b1edbc	2075	#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
AnnaBridge	171:3a7713b1edbc	2076	#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
AnnaBridge	171:3a7713b1edbc	2077	#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
AnnaBridge	171:3a7713b1edbc	2078	#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
AnnaBridge	171:3a7713b1edbc	2079	#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
AnnaBridge	171:3a7713b1edbc	2080	#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
AnnaBridge	171:3a7713b1edbc	2081	#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
AnnaBridge	171:3a7713b1edbc	2082	#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
AnnaBridge	171:3a7713b1edbc	2083	#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
AnnaBridge	171:3a7713b1edbc	2084	#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
AnnaBridge	171:3a7713b1edbc	2085	#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
AnnaBridge	171:3a7713b1edbc	2086	#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
AnnaBridge	171:3a7713b1edbc	2087	#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
AnnaBridge	171:3a7713b1edbc	2088	#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
AnnaBridge	171:3a7713b1edbc	2089	#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
AnnaBridge	171:3a7713b1edbc	2090	#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
AnnaBridge	171:3a7713b1edbc	2091	#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
AnnaBridge	171:3a7713b1edbc	2092	#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
AnnaBridge	171:3a7713b1edbc	2093	#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
AnnaBridge	171:3a7713b1edbc	2094	#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
AnnaBridge	171:3a7713b1edbc	2095	#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
AnnaBridge	171:3a7713b1edbc	2096	#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
AnnaBridge	171:3a7713b1edbc	2097	#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
AnnaBridge	171:3a7713b1edbc	2098	#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
AnnaBridge	171:3a7713b1edbc	2099	#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
AnnaBridge	171:3a7713b1edbc	2100	#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
AnnaBridge	171:3a7713b1edbc	2101	#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
AnnaBridge	171:3a7713b1edbc	2102	#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
AnnaBridge	171:3a7713b1edbc	2103	#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
AnnaBridge	171:3a7713b1edbc	2104	#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
AnnaBridge	171:3a7713b1edbc	2105	#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
AnnaBridge	171:3a7713b1edbc	2106	#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
AnnaBridge	171:3a7713b1edbc	2107	#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
AnnaBridge	171:3a7713b1edbc	2108
AnnaBridge	171:3a7713b1edbc	2109	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2110	}
AnnaBridge	171:3a7713b1edbc	2111	#endif
AnnaBridge	171:3a7713b1edbc	2112
AnnaBridge	171:3a7713b1edbc	2113	#endif /* __LPC43XX_H */