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TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z644.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processors: MKL27Z32VDA4
AnnaBridge 171:3a7713b1edbc 4 ** MKL27Z32VFM4
AnnaBridge 171:3a7713b1edbc 5 ** MKL27Z32VFT4
AnnaBridge 171:3a7713b1edbc 6 ** MKL27Z32VLH4
AnnaBridge 171:3a7713b1edbc 7 ** MKL27Z32VMP4
AnnaBridge 171:3a7713b1edbc 8 ** MKL27Z64VDA4
AnnaBridge 171:3a7713b1edbc 9 ** MKL27Z64VFM4
AnnaBridge 171:3a7713b1edbc 10 ** MKL27Z64VFT4
AnnaBridge 171:3a7713b1edbc 11 ** MKL27Z64VLH4
AnnaBridge 171:3a7713b1edbc 12 ** MKL27Z64VMP4
AnnaBridge 171:3a7713b1edbc 13 **
AnnaBridge 171:3a7713b1edbc 14 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 171:3a7713b1edbc 15 ** Freescale C/C++ for Embedded ARM
AnnaBridge 171:3a7713b1edbc 16 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 17 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 18 **
AnnaBridge 171:3a7713b1edbc 19 ** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014
AnnaBridge 171:3a7713b1edbc 20 ** Version: rev. 1.4, 2014-09-22
AnnaBridge 171:3a7713b1edbc 21 ** Build: b151221
AnnaBridge 171:3a7713b1edbc 22 **
AnnaBridge 171:3a7713b1edbc 23 ** Abstract:
AnnaBridge 171:3a7713b1edbc 24 ** CMSIS Peripheral Access Layer for MKL27Z644
AnnaBridge 171:3a7713b1edbc 25 **
AnnaBridge 171:3a7713b1edbc 26 ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 27 ** All rights reserved.
AnnaBridge 171:3a7713b1edbc 28 **
AnnaBridge 171:3a7713b1edbc 29 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 30 ** are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 31 **
AnnaBridge 171:3a7713b1edbc 32 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 33 ** of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 34 **
AnnaBridge 171:3a7713b1edbc 35 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 36 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 37 ** other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 38 **
AnnaBridge 171:3a7713b1edbc 39 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 40 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 41 ** software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 42 **
AnnaBridge 171:3a7713b1edbc 43 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 44 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 45 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 46 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 47 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 48 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 49 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 50 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 51 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 52 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 53 **
AnnaBridge 171:3a7713b1edbc 54 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 55 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 56 **
AnnaBridge 171:3a7713b1edbc 57 ** Revisions:
AnnaBridge 171:3a7713b1edbc 58 ** - rev. 1.0 (2014-05-12)
AnnaBridge 171:3a7713b1edbc 59 ** Initial version.
AnnaBridge 171:3a7713b1edbc 60 ** - rev. 1.1 (2014-07-10)
AnnaBridge 171:3a7713b1edbc 61 ** UART0 - UART0 module renamed to UART2.
AnnaBridge 171:3a7713b1edbc 62 ** - rev. 1.2 (2014-08-12)
AnnaBridge 171:3a7713b1edbc 63 ** CRC - CRC register renamed to DATA.
AnnaBridge 171:3a7713b1edbc 64 ** - rev. 1.3 (2014-09-02)
AnnaBridge 171:3a7713b1edbc 65 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
AnnaBridge 171:3a7713b1edbc 66 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
AnnaBridge 171:3a7713b1edbc 67 ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
AnnaBridge 171:3a7713b1edbc 68 ** - rev. 1.4 (2014-09-22)
AnnaBridge 171:3a7713b1edbc 69 ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
AnnaBridge 171:3a7713b1edbc 70 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
AnnaBridge 171:3a7713b1edbc 71 ** SIM - Removed bitfield DIEID in SDID register.
AnnaBridge 171:3a7713b1edbc 72 ** UART2 - Removed ED register.
AnnaBridge 171:3a7713b1edbc 73 ** UART2 - Removed MODEM register.
AnnaBridge 171:3a7713b1edbc 74 ** UART2 - Removed IR register.
AnnaBridge 171:3a7713b1edbc 75 ** UART2 - Removed PFIFO register.
AnnaBridge 171:3a7713b1edbc 76 ** UART2 - Removed CFIFO register.
AnnaBridge 171:3a7713b1edbc 77 ** UART2 - Removed SFIFO register.
AnnaBridge 171:3a7713b1edbc 78 ** UART2 - Removed TWFIFO register.
AnnaBridge 171:3a7713b1edbc 79 ** UART2 - Removed TCFIFO register.
AnnaBridge 171:3a7713b1edbc 80 ** UART2 - Removed RWFIFO register.
AnnaBridge 171:3a7713b1edbc 81 ** UART2 - Removed RCFIFO register.
AnnaBridge 171:3a7713b1edbc 82 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
AnnaBridge 171:3a7713b1edbc 83 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
AnnaBridge 171:3a7713b1edbc 84 **
AnnaBridge 171:3a7713b1edbc 85 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 86 */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 /*!
AnnaBridge 171:3a7713b1edbc 89 * @file MKL27Z644.h
AnnaBridge 171:3a7713b1edbc 90 * @version 1.4
AnnaBridge 171:3a7713b1edbc 91 * @date 2014-09-22
AnnaBridge 171:3a7713b1edbc 92 * @brief CMSIS Peripheral Access Layer for MKL27Z644
AnnaBridge 171:3a7713b1edbc 93 *
AnnaBridge 171:3a7713b1edbc 94 * CMSIS Peripheral Access Layer for MKL27Z644
AnnaBridge 171:3a7713b1edbc 95 */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 #ifndef _MKL27Z644_H_
AnnaBridge 171:3a7713b1edbc 98 #define _MKL27Z644_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 101 * compatible) */
AnnaBridge 171:3a7713b1edbc 102 #define MCU_MEM_MAP_VERSION 0x0100U
AnnaBridge 171:3a7713b1edbc 103 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 104 #define MCU_MEM_MAP_VERSION_MINOR 0x0004U
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 108 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 109 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /*!
AnnaBridge 171:3a7713b1edbc 112 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 113 * @{
AnnaBridge 171:3a7713b1edbc 114 */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 117 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 120 /* Auxiliary constants */
AnnaBridge 171:3a7713b1edbc 121 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 124 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 125 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 126 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 127 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 128 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 131 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
AnnaBridge 171:3a7713b1edbc 132 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
AnnaBridge 171:3a7713b1edbc 133 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
AnnaBridge 171:3a7713b1edbc 134 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
AnnaBridge 171:3a7713b1edbc 135 Reserved20_IRQn = 4, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 136 FTFA_IRQn = 5, /**< Command complete and read collision */
AnnaBridge 171:3a7713b1edbc 137 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
AnnaBridge 171:3a7713b1edbc 138 LLWU_IRQn = 7, /**< Low leakage wakeup */
AnnaBridge 171:3a7713b1edbc 139 I2C0_IRQn = 8, /**< I2C0 interrupt */
AnnaBridge 171:3a7713b1edbc 140 I2C1_IRQn = 9, /**< I2C1 interrupt */
AnnaBridge 171:3a7713b1edbc 141 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 142 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 143 LPUART0_IRQn = 12, /**< LPUART0 status and error */
AnnaBridge 171:3a7713b1edbc 144 LPUART1_IRQn = 13, /**< LPUART1 status and error */
AnnaBridge 171:3a7713b1edbc 145 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
AnnaBridge 171:3a7713b1edbc 146 ADC0_IRQn = 15, /**< ADC0 interrupt */
AnnaBridge 171:3a7713b1edbc 147 CMP0_IRQn = 16, /**< CMP0 interrupt */
AnnaBridge 171:3a7713b1edbc 148 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 149 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 150 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 151 RTC_IRQn = 20, /**< RTC alarm */
AnnaBridge 171:3a7713b1edbc 152 RTC_Seconds_IRQn = 21, /**< RTC seconds */
AnnaBridge 171:3a7713b1edbc 153 PIT_IRQn = 22, /**< PIT interrupt */
AnnaBridge 171:3a7713b1edbc 154 Reserved39_IRQn = 23, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 155 USB0_IRQn = 24, /**< USB0 interrupt */
AnnaBridge 171:3a7713b1edbc 156 Reserved41_IRQn = 25, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 157 Reserved42_IRQn = 26, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 158 Reserved43_IRQn = 27, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 159 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
AnnaBridge 171:3a7713b1edbc 160 Reserved45_IRQn = 29, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 161 PORTA_IRQn = 30, /**< PORTA Pin detect */
AnnaBridge 171:3a7713b1edbc 162 PORTB_PORTC_PORTD_PORTE_IRQn = 31 /**< Single interrupt vector for PORTB,PORTC,PORTD,PORTE */
AnnaBridge 171:3a7713b1edbc 163 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /*!
AnnaBridge 171:3a7713b1edbc 166 * @}
AnnaBridge 171:3a7713b1edbc 167 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 171 -- Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 172 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 /*!
AnnaBridge 171:3a7713b1edbc 175 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 176 * @{
AnnaBridge 171:3a7713b1edbc 177 */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
AnnaBridge 171:3a7713b1edbc 180 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 181 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 182 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 183 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 186 #include "system_MKL27Z644.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 /*!
AnnaBridge 171:3a7713b1edbc 189 * @}
AnnaBridge 171:3a7713b1edbc 190 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 194 -- Mapping Information
AnnaBridge 171:3a7713b1edbc 195 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /*!
AnnaBridge 171:3a7713b1edbc 198 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 171:3a7713b1edbc 199 * @{
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 /** Mapping Information */
AnnaBridge 171:3a7713b1edbc 203 /*!
AnnaBridge 171:3a7713b1edbc 204 * @addtogroup edma_request
AnnaBridge 171:3a7713b1edbc 205 * @{
AnnaBridge 171:3a7713b1edbc 206 */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 209 * Definitions
AnnaBridge 171:3a7713b1edbc 210 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /*!
AnnaBridge 171:3a7713b1edbc 213 * @brief Structure for the DMA hardware request
AnnaBridge 171:3a7713b1edbc 214 *
AnnaBridge 171:3a7713b1edbc 215 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 171:3a7713b1edbc 216 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 171:3a7713b1edbc 217 * of the hardware request varies according to the to SoC.
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 typedef enum _dma_request_source
AnnaBridge 171:3a7713b1edbc 220 {
AnnaBridge 171:3a7713b1edbc 221 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 171:3a7713b1edbc 222 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
AnnaBridge 171:3a7713b1edbc 223 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
AnnaBridge 171:3a7713b1edbc 224 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
AnnaBridge 171:3a7713b1edbc 225 kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */
AnnaBridge 171:3a7713b1edbc 226 kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */
AnnaBridge 171:3a7713b1edbc 227 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
AnnaBridge 171:3a7713b1edbc 228 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
AnnaBridge 171:3a7713b1edbc 229 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
AnnaBridge 171:3a7713b1edbc 230 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
AnnaBridge 171:3a7713b1edbc 231 kDmaRequestMux0FlexIOChannel0 = 10|0x100U, /**< FLEXIO. */
AnnaBridge 171:3a7713b1edbc 232 kDmaRequestMux0FlexIOChannel1 = 11|0x100U, /**< FLEXIO. */
AnnaBridge 171:3a7713b1edbc 233 kDmaRequestMux0FlexIOChannel2 = 12|0x100U, /**< FLEXIO. */
AnnaBridge 171:3a7713b1edbc 234 kDmaRequestMux0FlexIOChannel3 = 13|0x100U, /**< FLEXIO. */
AnnaBridge 171:3a7713b1edbc 235 kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */
AnnaBridge 171:3a7713b1edbc 236 kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */
AnnaBridge 171:3a7713b1edbc 237 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */
AnnaBridge 171:3a7713b1edbc 238 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */
AnnaBridge 171:3a7713b1edbc 239 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */
AnnaBridge 171:3a7713b1edbc 240 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */
AnnaBridge 171:3a7713b1edbc 241 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */
AnnaBridge 171:3a7713b1edbc 242 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */
AnnaBridge 171:3a7713b1edbc 243 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */
AnnaBridge 171:3a7713b1edbc 244 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */
AnnaBridge 171:3a7713b1edbc 245 kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */
AnnaBridge 171:3a7713b1edbc 246 kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */
AnnaBridge 171:3a7713b1edbc 247 kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */
AnnaBridge 171:3a7713b1edbc 248 kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */
AnnaBridge 171:3a7713b1edbc 249 kDmaRequestMux0TPM0Channel4 = 28|0x100U, /**< TPM0 C4V. */
AnnaBridge 171:3a7713b1edbc 250 kDmaRequestMux0TPM0Channel5 = 29|0x100U, /**< TPM0 C5V. */
AnnaBridge 171:3a7713b1edbc 251 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */
AnnaBridge 171:3a7713b1edbc 252 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */
AnnaBridge 171:3a7713b1edbc 253 kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */
AnnaBridge 171:3a7713b1edbc 254 kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */
AnnaBridge 171:3a7713b1edbc 255 kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */
AnnaBridge 171:3a7713b1edbc 256 kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */
AnnaBridge 171:3a7713b1edbc 257 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
AnnaBridge 171:3a7713b1edbc 258 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
AnnaBridge 171:3a7713b1edbc 259 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
AnnaBridge 171:3a7713b1edbc 260 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
AnnaBridge 171:3a7713b1edbc 261 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 171:3a7713b1edbc 262 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
AnnaBridge 171:3a7713b1edbc 263 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 171:3a7713b1edbc 264 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */
AnnaBridge 171:3a7713b1edbc 265 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
AnnaBridge 171:3a7713b1edbc 266 kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */
AnnaBridge 171:3a7713b1edbc 267 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
AnnaBridge 171:3a7713b1edbc 268 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
AnnaBridge 171:3a7713b1edbc 269 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */
AnnaBridge 171:3a7713b1edbc 270 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 171:3a7713b1edbc 271 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 171:3a7713b1edbc 272 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 171:3a7713b1edbc 273 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
AnnaBridge 171:3a7713b1edbc 274 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
AnnaBridge 171:3a7713b1edbc 275 kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */
AnnaBridge 171:3a7713b1edbc 276 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */
AnnaBridge 171:3a7713b1edbc 277 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */
AnnaBridge 171:3a7713b1edbc 278 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
AnnaBridge 171:3a7713b1edbc 279 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
AnnaBridge 171:3a7713b1edbc 280 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
AnnaBridge 171:3a7713b1edbc 281 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 282 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 283 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 284 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 285 } dma_request_source_t;
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /* @} */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289
AnnaBridge 171:3a7713b1edbc 290 /*!
AnnaBridge 171:3a7713b1edbc 291 * @}
AnnaBridge 171:3a7713b1edbc 292 */ /* end of group Mapping_Information */
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 296 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 297 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /*!
AnnaBridge 171:3a7713b1edbc 300 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 301 * @{
AnnaBridge 171:3a7713b1edbc 302 */
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 /*
AnnaBridge 171:3a7713b1edbc 306 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 310 #pragma push
AnnaBridge 171:3a7713b1edbc 311 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 312 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 313 #pragma push
AnnaBridge 171:3a7713b1edbc 314 #pragma cpp_extensions on
AnnaBridge 171:3a7713b1edbc 315 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 316 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 317 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 318 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 319 #else
AnnaBridge 171:3a7713b1edbc 320 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 321 #endif
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 324 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 325 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /*!
AnnaBridge 171:3a7713b1edbc 328 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 329 * @{
AnnaBridge 171:3a7713b1edbc 330 */
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 333 typedef struct {
AnnaBridge 171:3a7713b1edbc 334 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 336 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 337 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 342 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 348 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 349 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 351 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 352 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 356 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 357 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 358 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 359 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 360 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 363 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 364 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /*!
AnnaBridge 171:3a7713b1edbc 367 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 368 * @{
AnnaBridge 171:3a7713b1edbc 369 */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 171:3a7713b1edbc 372 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 373 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 374 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 375 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 376 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 377 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 378 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 379 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 380 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 171:3a7713b1edbc 381 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 382 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 383 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /* The count of ADC_SC1 */
AnnaBridge 171:3a7713b1edbc 386 #define ADC_SC1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 387
AnnaBridge 171:3a7713b1edbc 388 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 389 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 390 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 391 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 392 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 393 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 394 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 395 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 396 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 397 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 171:3a7713b1edbc 398 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 399 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 400 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 401 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 402 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 403 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 406 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 407 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 408 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 409 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 410 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 411 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 171:3a7713b1edbc 412 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 413 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 414 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 171:3a7713b1edbc 415 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 416 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 417 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /*! @name R - ADC Data Result Register */
AnnaBridge 171:3a7713b1edbc 420 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 421 #define ADC_R_D_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 422 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /* The count of ADC_R */
AnnaBridge 171:3a7713b1edbc 425 #define ADC_R_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /*! @name CV1 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 428 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 429 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 430 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 /*! @name CV2 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 433 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 434 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 435 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 171:3a7713b1edbc 438 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 439 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 440 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 441 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 442 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 443 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 444 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 445 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 446 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 171:3a7713b1edbc 447 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 448 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 449 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 171:3a7713b1edbc 450 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 451 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 452 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 171:3a7713b1edbc 453 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 454 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 455 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 171:3a7713b1edbc 456 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 457 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 458 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 171:3a7713b1edbc 461 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 462 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 463 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 464 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 465 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 466 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 171:3a7713b1edbc 467 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 468 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 469 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 171:3a7713b1edbc 470 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 471 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 472 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 171:3a7713b1edbc 473 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 474 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 475 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 171:3a7713b1edbc 478 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 479 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 480 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 483 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 484 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 485 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 488 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 489 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 490 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 493 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 494 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 495 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 498 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 499 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 500 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 503 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 504 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 505 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 508 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 509 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 510 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 513 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 514 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 518 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 519 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 520 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 523 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 524 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 525 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 528 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 529 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 530 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 533 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 534 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 535 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 538 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 539 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 540 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 541
AnnaBridge 171:3a7713b1edbc 542 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 543 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 544 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 545 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 548 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 549 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 550 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 553 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 554 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 555 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 558 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 559 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 560 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /*!
AnnaBridge 171:3a7713b1edbc 564 * @}
AnnaBridge 171:3a7713b1edbc 565 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 569 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 570 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 571 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 572 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 573 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 574 #define ADC_BASE_ADDRS { ADC0_BASE }
AnnaBridge 171:3a7713b1edbc 575 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 576 #define ADC_BASE_PTRS { ADC0 }
AnnaBridge 171:3a7713b1edbc 577 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 171:3a7713b1edbc 578 #define ADC_IRQS { ADC0_IRQn }
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 /*!
AnnaBridge 171:3a7713b1edbc 581 * @}
AnnaBridge 171:3a7713b1edbc 582 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 586 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 587 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 /*!
AnnaBridge 171:3a7713b1edbc 590 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 591 * @{
AnnaBridge 171:3a7713b1edbc 592 */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 595 typedef struct {
AnnaBridge 171:3a7713b1edbc 596 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 597 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 598 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 599 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 600 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 601 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 602 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 605 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 606 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /*!
AnnaBridge 171:3a7713b1edbc 609 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 610 * @{
AnnaBridge 171:3a7713b1edbc 611 */
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 171:3a7713b1edbc 614 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 615 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 616 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 617 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 618 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 619 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 171:3a7713b1edbc 622 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 623 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 624 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 625 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 626 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 627 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 171:3a7713b1edbc 628 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 629 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 630 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 171:3a7713b1edbc 631 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 632 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 633 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 171:3a7713b1edbc 634 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 635 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 636 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 171:3a7713b1edbc 637 #define CMP_CR1_TRIGM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 638 #define CMP_CR1_TRIGM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 639 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
AnnaBridge 171:3a7713b1edbc 640 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 641 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 642 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 171:3a7713b1edbc 643 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 644 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 645 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 171:3a7713b1edbc 648 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 649 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 650 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 171:3a7713b1edbc 653 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 654 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 655 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 171:3a7713b1edbc 656 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 657 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 658 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 171:3a7713b1edbc 659 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 660 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 661 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 662 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 663 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 664 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 171:3a7713b1edbc 665 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 666 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 667 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 171:3a7713b1edbc 668 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 669 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 670 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 /*! @name DACCR - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 673 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 674 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 675 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 676 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 677 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 678 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 171:3a7713b1edbc 679 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 680 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 681 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 /*! @name MUXCR - MUX Control Register */
AnnaBridge 171:3a7713b1edbc 684 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 685 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 686 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 687 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 688 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 689 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 690 #define CMP_MUXCR_PSTM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 691 #define CMP_MUXCR_PSTM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 692 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694
AnnaBridge 171:3a7713b1edbc 695 /*!
AnnaBridge 171:3a7713b1edbc 696 * @}
AnnaBridge 171:3a7713b1edbc 697 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 698
AnnaBridge 171:3a7713b1edbc 699
AnnaBridge 171:3a7713b1edbc 700 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 701 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 702 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 703 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 704 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 705 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 706 #define CMP_BASE_ADDRS { CMP0_BASE }
AnnaBridge 171:3a7713b1edbc 707 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 708 #define CMP_BASE_PTRS { CMP0 }
AnnaBridge 171:3a7713b1edbc 709 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 171:3a7713b1edbc 710 #define CMP_IRQS { CMP0_IRQn }
AnnaBridge 171:3a7713b1edbc 711
AnnaBridge 171:3a7713b1edbc 712 /*!
AnnaBridge 171:3a7713b1edbc 713 * @}
AnnaBridge 171:3a7713b1edbc 714 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 715
AnnaBridge 171:3a7713b1edbc 716
AnnaBridge 171:3a7713b1edbc 717 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 718 -- CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 719 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 /*!
AnnaBridge 171:3a7713b1edbc 722 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 723 * @{
AnnaBridge 171:3a7713b1edbc 724 */
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726 /** CRC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 727 typedef struct {
AnnaBridge 171:3a7713b1edbc 728 union { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 729 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 730 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 731 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 732 } ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 733 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 734 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 735 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 736 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 737 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 738 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 739 } ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 740 };
AnnaBridge 171:3a7713b1edbc 741 union { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 742 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 743 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 744 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 745 } GPOLY_ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 746 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 747 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 748 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 749 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 750 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 751 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 752 } GPOLY_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 753 };
AnnaBridge 171:3a7713b1edbc 754 union { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 755 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 756 struct { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 757 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 758 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
AnnaBridge 171:3a7713b1edbc 759 } CTRL_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 760 };
AnnaBridge 171:3a7713b1edbc 761 } CRC_Type;
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 764 -- CRC Register Masks
AnnaBridge 171:3a7713b1edbc 765 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767 /*!
AnnaBridge 171:3a7713b1edbc 768 * @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge 171:3a7713b1edbc 769 * @{
AnnaBridge 171:3a7713b1edbc 770 */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 /*! @name DATAL - CRC_DATAL register. */
AnnaBridge 171:3a7713b1edbc 773 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 774 #define CRC_DATAL_DATAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 775 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 /*! @name DATAH - CRC_DATAH register. */
AnnaBridge 171:3a7713b1edbc 778 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 779 #define CRC_DATAH_DATAH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 780 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
AnnaBridge 171:3a7713b1edbc 781
AnnaBridge 171:3a7713b1edbc 782 /*! @name DATA - CRC Data register */
AnnaBridge 171:3a7713b1edbc 783 #define CRC_DATA_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 784 #define CRC_DATA_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 785 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
AnnaBridge 171:3a7713b1edbc 786 #define CRC_DATA_LU_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 787 #define CRC_DATA_LU_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 788 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
AnnaBridge 171:3a7713b1edbc 789 #define CRC_DATA_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 790 #define CRC_DATA_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 791 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
AnnaBridge 171:3a7713b1edbc 792 #define CRC_DATA_HU_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 793 #define CRC_DATA_HU_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 794 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /*! @name DATALL - CRC_DATALL register. */
AnnaBridge 171:3a7713b1edbc 797 #define CRC_DATALL_DATALL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 798 #define CRC_DATALL_DATALL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 799 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
AnnaBridge 171:3a7713b1edbc 800
AnnaBridge 171:3a7713b1edbc 801 /*! @name DATALU - CRC_DATALU register. */
AnnaBridge 171:3a7713b1edbc 802 #define CRC_DATALU_DATALU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 803 #define CRC_DATALU_DATALU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 804 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
AnnaBridge 171:3a7713b1edbc 805
AnnaBridge 171:3a7713b1edbc 806 /*! @name DATAHL - CRC_DATAHL register. */
AnnaBridge 171:3a7713b1edbc 807 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 808 #define CRC_DATAHL_DATAHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 809 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
AnnaBridge 171:3a7713b1edbc 810
AnnaBridge 171:3a7713b1edbc 811 /*! @name DATAHU - CRC_DATAHU register. */
AnnaBridge 171:3a7713b1edbc 812 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 813 #define CRC_DATAHU_DATAHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 814 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
AnnaBridge 171:3a7713b1edbc 815
AnnaBridge 171:3a7713b1edbc 816 /*! @name GPOLYL - CRC_GPOLYL register. */
AnnaBridge 171:3a7713b1edbc 817 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 818 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 819 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge 171:3a7713b1edbc 820
AnnaBridge 171:3a7713b1edbc 821 /*! @name GPOLYH - CRC_GPOLYH register. */
AnnaBridge 171:3a7713b1edbc 822 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 823 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 824 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge 171:3a7713b1edbc 825
AnnaBridge 171:3a7713b1edbc 826 /*! @name GPOLY - CRC Polynomial register */
AnnaBridge 171:3a7713b1edbc 827 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 828 #define CRC_GPOLY_LOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 829 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
AnnaBridge 171:3a7713b1edbc 830 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 831 #define CRC_GPOLY_HIGH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 832 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 /*! @name GPOLYLL - CRC_GPOLYLL register. */
AnnaBridge 171:3a7713b1edbc 835 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 836 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 837 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge 171:3a7713b1edbc 838
AnnaBridge 171:3a7713b1edbc 839 /*! @name GPOLYLU - CRC_GPOLYLU register. */
AnnaBridge 171:3a7713b1edbc 840 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 841 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 842 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge 171:3a7713b1edbc 843
AnnaBridge 171:3a7713b1edbc 844 /*! @name GPOLYHL - CRC_GPOLYHL register. */
AnnaBridge 171:3a7713b1edbc 845 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 846 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 847 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge 171:3a7713b1edbc 848
AnnaBridge 171:3a7713b1edbc 849 /*! @name GPOLYHU - CRC_GPOLYHU register. */
AnnaBridge 171:3a7713b1edbc 850 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 851 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 852 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /*! @name CTRL - CRC Control register */
AnnaBridge 171:3a7713b1edbc 855 #define CRC_CTRL_TCRC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 856 #define CRC_CTRL_TCRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 857 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 858 #define CRC_CTRL_WAS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 859 #define CRC_CTRL_WAS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 860 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 861 #define CRC_CTRL_FXOR_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 862 #define CRC_CTRL_FXOR_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 863 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 864 #define CRC_CTRL_TOTR_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 865 #define CRC_CTRL_TOTR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 866 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 867 #define CRC_CTRL_TOT_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 868 #define CRC_CTRL_TOT_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 869 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 /*! @name CTRLHU - CRC_CTRLHU register. */
AnnaBridge 171:3a7713b1edbc 872 #define CRC_CTRLHU_TCRC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 873 #define CRC_CTRLHU_TCRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 874 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 875 #define CRC_CTRLHU_WAS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 876 #define CRC_CTRLHU_WAS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 877 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 878 #define CRC_CTRLHU_FXOR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 879 #define CRC_CTRLHU_FXOR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 880 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 881 #define CRC_CTRLHU_TOTR_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 882 #define CRC_CTRLHU_TOTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 883 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 884 #define CRC_CTRLHU_TOT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 885 #define CRC_CTRLHU_TOT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 886 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 887
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 /*!
AnnaBridge 171:3a7713b1edbc 890 * @}
AnnaBridge 171:3a7713b1edbc 891 */ /* end of group CRC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 892
AnnaBridge 171:3a7713b1edbc 893
AnnaBridge 171:3a7713b1edbc 894 /* CRC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 895 /** Peripheral CRC base address */
AnnaBridge 171:3a7713b1edbc 896 #define CRC_BASE (0x40032000u)
AnnaBridge 171:3a7713b1edbc 897 /** Peripheral CRC base pointer */
AnnaBridge 171:3a7713b1edbc 898 #define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge 171:3a7713b1edbc 899 /** Array initializer of CRC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 900 #define CRC_BASE_ADDRS { CRC_BASE }
AnnaBridge 171:3a7713b1edbc 901 /** Array initializer of CRC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 902 #define CRC_BASE_PTRS { CRC0 }
AnnaBridge 171:3a7713b1edbc 903
AnnaBridge 171:3a7713b1edbc 904 /*!
AnnaBridge 171:3a7713b1edbc 905 * @}
AnnaBridge 171:3a7713b1edbc 906 */ /* end of group CRC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 907
AnnaBridge 171:3a7713b1edbc 908
AnnaBridge 171:3a7713b1edbc 909 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 910 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 911 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 912
AnnaBridge 171:3a7713b1edbc 913 /*!
AnnaBridge 171:3a7713b1edbc 914 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 915 * @{
AnnaBridge 171:3a7713b1edbc 916 */
AnnaBridge 171:3a7713b1edbc 917
AnnaBridge 171:3a7713b1edbc 918 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 919 typedef struct {
AnnaBridge 171:3a7713b1edbc 920 uint8_t RESERVED_0[256];
AnnaBridge 171:3a7713b1edbc 921 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 922 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 923 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 924 union { /* offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 925 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 926 struct { /* offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 927 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 928 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 929 } DMA_DSR_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 930 };
AnnaBridge 171:3a7713b1edbc 931 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 932 } DMA[4];
AnnaBridge 171:3a7713b1edbc 933 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 934
AnnaBridge 171:3a7713b1edbc 935 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 936 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 937 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 938
AnnaBridge 171:3a7713b1edbc 939 /*!
AnnaBridge 171:3a7713b1edbc 940 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 941 * @{
AnnaBridge 171:3a7713b1edbc 942 */
AnnaBridge 171:3a7713b1edbc 943
AnnaBridge 171:3a7713b1edbc 944 /*! @name SAR - Source Address Register */
AnnaBridge 171:3a7713b1edbc 945 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 946 #define DMA_SAR_SAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 947 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK)
AnnaBridge 171:3a7713b1edbc 948
AnnaBridge 171:3a7713b1edbc 949 /* The count of DMA_SAR */
AnnaBridge 171:3a7713b1edbc 950 #define DMA_SAR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 951
AnnaBridge 171:3a7713b1edbc 952 /*! @name DAR - Destination Address Register */
AnnaBridge 171:3a7713b1edbc 953 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 954 #define DMA_DAR_DAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 955 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK)
AnnaBridge 171:3a7713b1edbc 956
AnnaBridge 171:3a7713b1edbc 957 /* The count of DMA_DAR */
AnnaBridge 171:3a7713b1edbc 958 #define DMA_DAR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 959
AnnaBridge 171:3a7713b1edbc 960 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */
AnnaBridge 171:3a7713b1edbc 961 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 962 #define DMA_DSR_BCR_BCR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 963 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK)
AnnaBridge 171:3a7713b1edbc 964 #define DMA_DSR_BCR_DONE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 965 #define DMA_DSR_BCR_DONE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 966 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK)
AnnaBridge 171:3a7713b1edbc 967 #define DMA_DSR_BCR_BSY_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 968 #define DMA_DSR_BCR_BSY_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 969 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK)
AnnaBridge 171:3a7713b1edbc 970 #define DMA_DSR_BCR_REQ_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 971 #define DMA_DSR_BCR_REQ_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 972 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 973 #define DMA_DSR_BCR_BED_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 974 #define DMA_DSR_BCR_BED_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 975 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK)
AnnaBridge 171:3a7713b1edbc 976 #define DMA_DSR_BCR_BES_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 977 #define DMA_DSR_BCR_BES_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 978 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK)
AnnaBridge 171:3a7713b1edbc 979 #define DMA_DSR_BCR_CE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 980 #define DMA_DSR_BCR_CE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 981 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK)
AnnaBridge 171:3a7713b1edbc 982
AnnaBridge 171:3a7713b1edbc 983 /* The count of DMA_DSR_BCR */
AnnaBridge 171:3a7713b1edbc 984 #define DMA_DSR_BCR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 985
AnnaBridge 171:3a7713b1edbc 986 /* The count of DMA_DSR */
AnnaBridge 171:3a7713b1edbc 987 #define DMA_DSR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 988
AnnaBridge 171:3a7713b1edbc 989 /*! @name DCR - DMA Control Register */
AnnaBridge 171:3a7713b1edbc 990 #define DMA_DCR_LCH2_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 991 #define DMA_DCR_LCH2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 992 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK)
AnnaBridge 171:3a7713b1edbc 993 #define DMA_DCR_LCH1_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 994 #define DMA_DCR_LCH1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 995 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK)
AnnaBridge 171:3a7713b1edbc 996 #define DMA_DCR_LINKCC_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 997 #define DMA_DCR_LINKCC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 998 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK)
AnnaBridge 171:3a7713b1edbc 999 #define DMA_DCR_D_REQ_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1000 #define DMA_DCR_D_REQ_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1001 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 1002 #define DMA_DCR_DMOD_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 1003 #define DMA_DCR_DMOD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1004 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 1005 #define DMA_DCR_SMOD_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 1006 #define DMA_DCR_SMOD_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1007 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 1008 #define DMA_DCR_START_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1009 #define DMA_DCR_START_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1010 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK)
AnnaBridge 171:3a7713b1edbc 1011 #define DMA_DCR_DSIZE_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 1012 #define DMA_DCR_DSIZE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1013 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 1014 #define DMA_DCR_DINC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 1015 #define DMA_DCR_DINC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 1016 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK)
AnnaBridge 171:3a7713b1edbc 1017 #define DMA_DCR_SSIZE_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 1018 #define DMA_DCR_SSIZE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1019 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 1020 #define DMA_DCR_SINC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1021 #define DMA_DCR_SINC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1022 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK)
AnnaBridge 171:3a7713b1edbc 1023 #define DMA_DCR_EADREQ_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 1024 #define DMA_DCR_EADREQ_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 1025 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK)
AnnaBridge 171:3a7713b1edbc 1026 #define DMA_DCR_AA_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1027 #define DMA_DCR_AA_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1028 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK)
AnnaBridge 171:3a7713b1edbc 1029 #define DMA_DCR_CS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1030 #define DMA_DCR_CS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1031 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK)
AnnaBridge 171:3a7713b1edbc 1032 #define DMA_DCR_ERQ_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1033 #define DMA_DCR_ERQ_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1034 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK)
AnnaBridge 171:3a7713b1edbc 1035 #define DMA_DCR_EINT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1036 #define DMA_DCR_EINT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1037 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK)
AnnaBridge 171:3a7713b1edbc 1038
AnnaBridge 171:3a7713b1edbc 1039 /* The count of DMA_DCR */
AnnaBridge 171:3a7713b1edbc 1040 #define DMA_DCR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042
AnnaBridge 171:3a7713b1edbc 1043 /*!
AnnaBridge 171:3a7713b1edbc 1044 * @}
AnnaBridge 171:3a7713b1edbc 1045 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1046
AnnaBridge 171:3a7713b1edbc 1047
AnnaBridge 171:3a7713b1edbc 1048 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1049 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 1050 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 1051 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 1052 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 1053 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1054 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 171:3a7713b1edbc 1055 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1056 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 171:3a7713b1edbc 1057 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 171:3a7713b1edbc 1058 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 /*!
AnnaBridge 171:3a7713b1edbc 1061 * @}
AnnaBridge 171:3a7713b1edbc 1062 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1063
AnnaBridge 171:3a7713b1edbc 1064
AnnaBridge 171:3a7713b1edbc 1065 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1066 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1067 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1068
AnnaBridge 171:3a7713b1edbc 1069 /*!
AnnaBridge 171:3a7713b1edbc 1070 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1071 * @{
AnnaBridge 171:3a7713b1edbc 1072 */
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1075 typedef struct {
AnnaBridge 171:3a7713b1edbc 1076 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 1077 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 1078
AnnaBridge 171:3a7713b1edbc 1079 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1080 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 1081 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 /*!
AnnaBridge 171:3a7713b1edbc 1084 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 1085 * @{
AnnaBridge 171:3a7713b1edbc 1086 */
AnnaBridge 171:3a7713b1edbc 1087
AnnaBridge 171:3a7713b1edbc 1088 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 171:3a7713b1edbc 1089 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 1090 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1091 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 1092 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1093 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1094 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 1095 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1096 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1097 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 171:3a7713b1edbc 1098
AnnaBridge 171:3a7713b1edbc 1099 /* The count of DMAMUX_CHCFG */
AnnaBridge 171:3a7713b1edbc 1100 #define DMAMUX_CHCFG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1101
AnnaBridge 171:3a7713b1edbc 1102
AnnaBridge 171:3a7713b1edbc 1103 /*!
AnnaBridge 171:3a7713b1edbc 1104 * @}
AnnaBridge 171:3a7713b1edbc 1105 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1109 /** Peripheral DMAMUX0 base address */
AnnaBridge 171:3a7713b1edbc 1110 #define DMAMUX0_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 1111 /** Peripheral DMAMUX0 base pointer */
AnnaBridge 171:3a7713b1edbc 1112 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
AnnaBridge 171:3a7713b1edbc 1113 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1114 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
AnnaBridge 171:3a7713b1edbc 1115 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1116 #define DMAMUX_BASE_PTRS { DMAMUX0 }
AnnaBridge 171:3a7713b1edbc 1117
AnnaBridge 171:3a7713b1edbc 1118 /*!
AnnaBridge 171:3a7713b1edbc 1119 * @}
AnnaBridge 171:3a7713b1edbc 1120 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1121
AnnaBridge 171:3a7713b1edbc 1122
AnnaBridge 171:3a7713b1edbc 1123 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1124 -- FLEXIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1125 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1126
AnnaBridge 171:3a7713b1edbc 1127 /*!
AnnaBridge 171:3a7713b1edbc 1128 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1129 * @{
AnnaBridge 171:3a7713b1edbc 1130 */
AnnaBridge 171:3a7713b1edbc 1131
AnnaBridge 171:3a7713b1edbc 1132 /** FLEXIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1133 typedef struct {
AnnaBridge 171:3a7713b1edbc 1134 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1135 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1136 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1137 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 1138 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1139 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1140 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 1141 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 1142 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 1143 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 1144 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 1145 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 1146 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 1147 uint8_t RESERVED_3[76];
AnnaBridge 171:3a7713b1edbc 1148 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1149 uint8_t RESERVED_4[112];
AnnaBridge 171:3a7713b1edbc 1150 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1151 uint8_t RESERVED_5[240];
AnnaBridge 171:3a7713b1edbc 1152 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1153 uint8_t RESERVED_6[112];
AnnaBridge 171:3a7713b1edbc 1154 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1155 uint8_t RESERVED_7[112];
AnnaBridge 171:3a7713b1edbc 1156 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1157 uint8_t RESERVED_8[112];
AnnaBridge 171:3a7713b1edbc 1158 __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1159 uint8_t RESERVED_9[112];
AnnaBridge 171:3a7713b1edbc 1160 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1161 uint8_t RESERVED_10[112];
AnnaBridge 171:3a7713b1edbc 1162 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1163 uint8_t RESERVED_11[112];
AnnaBridge 171:3a7713b1edbc 1164 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 1165 } FLEXIO_Type;
AnnaBridge 171:3a7713b1edbc 1166
AnnaBridge 171:3a7713b1edbc 1167 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1168 -- FLEXIO Register Masks
AnnaBridge 171:3a7713b1edbc 1169 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1170
AnnaBridge 171:3a7713b1edbc 1171 /*!
AnnaBridge 171:3a7713b1edbc 1172 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
AnnaBridge 171:3a7713b1edbc 1173 * @{
AnnaBridge 171:3a7713b1edbc 1174 */
AnnaBridge 171:3a7713b1edbc 1175
AnnaBridge 171:3a7713b1edbc 1176 /*! @name VERID - Version ID Register */
AnnaBridge 171:3a7713b1edbc 1177 #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1178 #define FLEXIO_VERID_FEATURE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1179 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
AnnaBridge 171:3a7713b1edbc 1180 #define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 1181 #define FLEXIO_VERID_MINOR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1182 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
AnnaBridge 171:3a7713b1edbc 1183 #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 1184 #define FLEXIO_VERID_MAJOR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1185 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
AnnaBridge 171:3a7713b1edbc 1186
AnnaBridge 171:3a7713b1edbc 1187 /*! @name PARAM - Parameter Register */
AnnaBridge 171:3a7713b1edbc 1188 #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1189 #define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1190 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
AnnaBridge 171:3a7713b1edbc 1191 #define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 1192 #define FLEXIO_PARAM_TIMER_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1193 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 1194 #define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 1195 #define FLEXIO_PARAM_PIN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1196 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 1197 #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 1198 #define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1199 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
AnnaBridge 171:3a7713b1edbc 1200
AnnaBridge 171:3a7713b1edbc 1201 /*! @name CTRL - FlexIO Control Register */
AnnaBridge 171:3a7713b1edbc 1202 #define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1203 #define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1204 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
AnnaBridge 171:3a7713b1edbc 1205 #define FLEXIO_CTRL_SWRST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1206 #define FLEXIO_CTRL_SWRST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1207 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
AnnaBridge 171:3a7713b1edbc 1208 #define FLEXIO_CTRL_FASTACC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1209 #define FLEXIO_CTRL_FASTACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1210 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
AnnaBridge 171:3a7713b1edbc 1211 #define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1212 #define FLEXIO_CTRL_DBGE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1213 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 1214 #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1215 #define FLEXIO_CTRL_DOZEN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1216 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
AnnaBridge 171:3a7713b1edbc 1217
AnnaBridge 171:3a7713b1edbc 1218 /*! @name SHIFTSTAT - Shifter Status Register */
AnnaBridge 171:3a7713b1edbc 1219 #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1220 #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1221 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
AnnaBridge 171:3a7713b1edbc 1222
AnnaBridge 171:3a7713b1edbc 1223 /*! @name SHIFTERR - Shifter Error Register */
AnnaBridge 171:3a7713b1edbc 1224 #define FLEXIO_SHIFTERR_SEF_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1225 #define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1226 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 1227
AnnaBridge 171:3a7713b1edbc 1228 /*! @name TIMSTAT - Timer Status Register */
AnnaBridge 171:3a7713b1edbc 1229 #define FLEXIO_TIMSTAT_TSF_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1230 #define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1231 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
AnnaBridge 171:3a7713b1edbc 1232
AnnaBridge 171:3a7713b1edbc 1233 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1234 #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1235 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1236 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
AnnaBridge 171:3a7713b1edbc 1237
AnnaBridge 171:3a7713b1edbc 1238 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1239 #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1240 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1241 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 1242
AnnaBridge 171:3a7713b1edbc 1243 /*! @name TIMIEN - Timer Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 1244 #define FLEXIO_TIMIEN_TEIE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1245 #define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1246 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
AnnaBridge 171:3a7713b1edbc 1247
AnnaBridge 171:3a7713b1edbc 1248 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
AnnaBridge 171:3a7713b1edbc 1249 #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1250 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1251 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /*! @name SHIFTCTL - Shifter Control N Register */
AnnaBridge 171:3a7713b1edbc 1254 #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 1255 #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1256 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 1257 #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1258 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1259 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
AnnaBridge 171:3a7713b1edbc 1260 #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 1261 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1262 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1263 #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 1264 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1265 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
AnnaBridge 171:3a7713b1edbc 1266 #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 1267 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 1268 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
AnnaBridge 171:3a7713b1edbc 1269 #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 1270 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1271 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1272
AnnaBridge 171:3a7713b1edbc 1273 /* The count of FLEXIO_SHIFTCTL */
AnnaBridge 171:3a7713b1edbc 1274 #define FLEXIO_SHIFTCTL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 /*! @name SHIFTCFG - Shifter Configuration N Register */
AnnaBridge 171:3a7713b1edbc 1277 #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1278 #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1279 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
AnnaBridge 171:3a7713b1edbc 1280 #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1281 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1282 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
AnnaBridge 171:3a7713b1edbc 1283 #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1284 #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1285 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
AnnaBridge 171:3a7713b1edbc 1286
AnnaBridge 171:3a7713b1edbc 1287 /* The count of FLEXIO_SHIFTCFG */
AnnaBridge 171:3a7713b1edbc 1288 #define FLEXIO_SHIFTCFG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1289
AnnaBridge 171:3a7713b1edbc 1290 /*! @name SHIFTBUF - Shifter Buffer N Register */
AnnaBridge 171:3a7713b1edbc 1291 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1292 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1293 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
AnnaBridge 171:3a7713b1edbc 1294
AnnaBridge 171:3a7713b1edbc 1295 /* The count of FLEXIO_SHIFTBUF */
AnnaBridge 171:3a7713b1edbc 1296 #define FLEXIO_SHIFTBUF_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1297
AnnaBridge 171:3a7713b1edbc 1298 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
AnnaBridge 171:3a7713b1edbc 1299 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1300 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1301 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
AnnaBridge 171:3a7713b1edbc 1302
AnnaBridge 171:3a7713b1edbc 1303 /* The count of FLEXIO_SHIFTBUFBIS */
AnnaBridge 171:3a7713b1edbc 1304 #define FLEXIO_SHIFTBUFBIS_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1305
AnnaBridge 171:3a7713b1edbc 1306 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
AnnaBridge 171:3a7713b1edbc 1307 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1308 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1309 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
AnnaBridge 171:3a7713b1edbc 1310
AnnaBridge 171:3a7713b1edbc 1311 /* The count of FLEXIO_SHIFTBUFBYS */
AnnaBridge 171:3a7713b1edbc 1312 #define FLEXIO_SHIFTBUFBYS_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1313
AnnaBridge 171:3a7713b1edbc 1314 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
AnnaBridge 171:3a7713b1edbc 1315 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1316 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1317 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
AnnaBridge 171:3a7713b1edbc 1318
AnnaBridge 171:3a7713b1edbc 1319 /* The count of FLEXIO_SHIFTBUFBBS */
AnnaBridge 171:3a7713b1edbc 1320 #define FLEXIO_SHIFTBUFBBS_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1321
AnnaBridge 171:3a7713b1edbc 1322 /*! @name TIMCTL - Timer Control N Register */
AnnaBridge 171:3a7713b1edbc 1323 #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1324 #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1325 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
AnnaBridge 171:3a7713b1edbc 1326 #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1327 #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1328 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
AnnaBridge 171:3a7713b1edbc 1329 #define FLEXIO_TIMCTL_PINSEL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 1330 #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1331 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1332 #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 1333 #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1334 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
AnnaBridge 171:3a7713b1edbc 1335 #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1336 #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1337 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
AnnaBridge 171:3a7713b1edbc 1338 #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 1339 #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 1340 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
AnnaBridge 171:3a7713b1edbc 1341 #define FLEXIO_TIMCTL_TRGSEL_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 1342 #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1343 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1344
AnnaBridge 171:3a7713b1edbc 1345 /* The count of FLEXIO_TIMCTL */
AnnaBridge 171:3a7713b1edbc 1346 #define FLEXIO_TIMCTL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1347
AnnaBridge 171:3a7713b1edbc 1348 /*! @name TIMCFG - Timer Configuration N Register */
AnnaBridge 171:3a7713b1edbc 1349 #define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1350 #define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1351 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
AnnaBridge 171:3a7713b1edbc 1352 #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1353 #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1354 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
AnnaBridge 171:3a7713b1edbc 1355 #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 1356 #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1357 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
AnnaBridge 171:3a7713b1edbc 1358 #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 1359 #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1360 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
AnnaBridge 171:3a7713b1edbc 1361 #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 1362 #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1363 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
AnnaBridge 171:3a7713b1edbc 1364 #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 1365 #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1366 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
AnnaBridge 171:3a7713b1edbc 1367 #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 1368 #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1369 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
AnnaBridge 171:3a7713b1edbc 1370
AnnaBridge 171:3a7713b1edbc 1371 /* The count of FLEXIO_TIMCFG */
AnnaBridge 171:3a7713b1edbc 1372 #define FLEXIO_TIMCFG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1373
AnnaBridge 171:3a7713b1edbc 1374 /*! @name TIMCMP - Timer Compare N Register */
AnnaBridge 171:3a7713b1edbc 1375 #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1376 #define FLEXIO_TIMCMP_CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1377 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 1378
AnnaBridge 171:3a7713b1edbc 1379 /* The count of FLEXIO_TIMCMP */
AnnaBridge 171:3a7713b1edbc 1380 #define FLEXIO_TIMCMP_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1381
AnnaBridge 171:3a7713b1edbc 1382
AnnaBridge 171:3a7713b1edbc 1383 /*!
AnnaBridge 171:3a7713b1edbc 1384 * @}
AnnaBridge 171:3a7713b1edbc 1385 */ /* end of group FLEXIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1386
AnnaBridge 171:3a7713b1edbc 1387
AnnaBridge 171:3a7713b1edbc 1388 /* FLEXIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1389 /** Peripheral FLEXIO base address */
AnnaBridge 171:3a7713b1edbc 1390 #define FLEXIO_BASE (0x4005F000u)
AnnaBridge 171:3a7713b1edbc 1391 /** Peripheral FLEXIO base pointer */
AnnaBridge 171:3a7713b1edbc 1392 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
AnnaBridge 171:3a7713b1edbc 1393 /** Array initializer of FLEXIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1394 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
AnnaBridge 171:3a7713b1edbc 1395 /** Array initializer of FLEXIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1396 #define FLEXIO_BASE_PTRS { FLEXIO }
AnnaBridge 171:3a7713b1edbc 1397 /** Interrupt vectors for the FLEXIO peripheral type */
AnnaBridge 171:3a7713b1edbc 1398 #define FLEXIO_IRQS { UART2_FLEXIO_IRQn }
AnnaBridge 171:3a7713b1edbc 1399
AnnaBridge 171:3a7713b1edbc 1400 /*!
AnnaBridge 171:3a7713b1edbc 1401 * @}
AnnaBridge 171:3a7713b1edbc 1402 */ /* end of group FLEXIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1403
AnnaBridge 171:3a7713b1edbc 1404
AnnaBridge 171:3a7713b1edbc 1405 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1406 -- FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1407 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1408
AnnaBridge 171:3a7713b1edbc 1409 /*!
AnnaBridge 171:3a7713b1edbc 1410 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1411 * @{
AnnaBridge 171:3a7713b1edbc 1412 */
AnnaBridge 171:3a7713b1edbc 1413
AnnaBridge 171:3a7713b1edbc 1414 /** FTFA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1415 typedef struct {
AnnaBridge 171:3a7713b1edbc 1416 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1417 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1418 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1419 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1420 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1421 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1422 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1423 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1424 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1425 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1426 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1427 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1428 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1429 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 1430 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 1431 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 1432 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1433 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 1434 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 1435 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 1436 } FTFA_Type;
AnnaBridge 171:3a7713b1edbc 1437
AnnaBridge 171:3a7713b1edbc 1438 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1439 -- FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 1440 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1441
AnnaBridge 171:3a7713b1edbc 1442 /*!
AnnaBridge 171:3a7713b1edbc 1443 * @addtogroup FTFA_Register_Masks FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 1444 * @{
AnnaBridge 171:3a7713b1edbc 1445 */
AnnaBridge 171:3a7713b1edbc 1446
AnnaBridge 171:3a7713b1edbc 1447 /*! @name FSTAT - Flash Status Register */
AnnaBridge 171:3a7713b1edbc 1448 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1449 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1450 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
AnnaBridge 171:3a7713b1edbc 1451 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1452 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1453 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
AnnaBridge 171:3a7713b1edbc 1454 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1455 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1456 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
AnnaBridge 171:3a7713b1edbc 1457 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1458 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1459 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
AnnaBridge 171:3a7713b1edbc 1460 #define FTFA_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1461 #define FTFA_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1462 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
AnnaBridge 171:3a7713b1edbc 1463
AnnaBridge 171:3a7713b1edbc 1464 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 171:3a7713b1edbc 1465 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1466 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1467 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
AnnaBridge 171:3a7713b1edbc 1468 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1469 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1470 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
AnnaBridge 171:3a7713b1edbc 1471 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1472 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1473 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
AnnaBridge 171:3a7713b1edbc 1474 #define FTFA_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1475 #define FTFA_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1476 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
AnnaBridge 171:3a7713b1edbc 1477
AnnaBridge 171:3a7713b1edbc 1478 /*! @name FSEC - Flash Security Register */
AnnaBridge 171:3a7713b1edbc 1479 #define FTFA_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1480 #define FTFA_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1481 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 1482 #define FTFA_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 1483 #define FTFA_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1484 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 1485 #define FTFA_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1486 #define FTFA_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1487 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 1488 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 1489 #define FTFA_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1490 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 1491
AnnaBridge 171:3a7713b1edbc 1492 /*! @name FOPT - Flash Option Register */
AnnaBridge 171:3a7713b1edbc 1493 #define FTFA_FOPT_OPT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1494 #define FTFA_FOPT_OPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1495 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 1496
AnnaBridge 171:3a7713b1edbc 1497 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1498 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1499 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1500 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1501
AnnaBridge 171:3a7713b1edbc 1502 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1503 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1504 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1505 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1506
AnnaBridge 171:3a7713b1edbc 1507 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1508 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1509 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1510 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1511
AnnaBridge 171:3a7713b1edbc 1512 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1513 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1514 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1515 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1516
AnnaBridge 171:3a7713b1edbc 1517 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1518 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1519 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1520 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1521
AnnaBridge 171:3a7713b1edbc 1522 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1523 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1524 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1525 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1526
AnnaBridge 171:3a7713b1edbc 1527 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1528 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1529 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1530 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1531
AnnaBridge 171:3a7713b1edbc 1532 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1533 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1534 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1535 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1536
AnnaBridge 171:3a7713b1edbc 1537 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1538 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1539 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1540 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1541
AnnaBridge 171:3a7713b1edbc 1542 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1543 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1544 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1545 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1546
AnnaBridge 171:3a7713b1edbc 1547 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1548 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1549 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1550 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1551
AnnaBridge 171:3a7713b1edbc 1552 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 1553 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1554 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1555 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 1556
AnnaBridge 171:3a7713b1edbc 1557 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 1558 #define FTFA_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1559 #define FTFA_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1560 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 1561
AnnaBridge 171:3a7713b1edbc 1562 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 1563 #define FTFA_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1564 #define FTFA_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1565 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 1566
AnnaBridge 171:3a7713b1edbc 1567 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 1568 #define FTFA_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1569 #define FTFA_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1570 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 1571
AnnaBridge 171:3a7713b1edbc 1572 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 1573 #define FTFA_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1574 #define FTFA_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1575 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 1576
AnnaBridge 171:3a7713b1edbc 1577
AnnaBridge 171:3a7713b1edbc 1578 /*!
AnnaBridge 171:3a7713b1edbc 1579 * @}
AnnaBridge 171:3a7713b1edbc 1580 */ /* end of group FTFA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1581
AnnaBridge 171:3a7713b1edbc 1582
AnnaBridge 171:3a7713b1edbc 1583 /* FTFA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1584 /** Peripheral FTFA base address */
AnnaBridge 171:3a7713b1edbc 1585 #define FTFA_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 1586 /** Peripheral FTFA base pointer */
AnnaBridge 171:3a7713b1edbc 1587 #define FTFA ((FTFA_Type *)FTFA_BASE)
AnnaBridge 171:3a7713b1edbc 1588 /** Array initializer of FTFA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1589 #define FTFA_BASE_ADDRS { FTFA_BASE }
AnnaBridge 171:3a7713b1edbc 1590 /** Array initializer of FTFA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1591 #define FTFA_BASE_PTRS { FTFA }
AnnaBridge 171:3a7713b1edbc 1592 /** Interrupt vectors for the FTFA peripheral type */
AnnaBridge 171:3a7713b1edbc 1593 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
AnnaBridge 171:3a7713b1edbc 1594
AnnaBridge 171:3a7713b1edbc 1595 /*!
AnnaBridge 171:3a7713b1edbc 1596 * @}
AnnaBridge 171:3a7713b1edbc 1597 */ /* end of group FTFA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1598
AnnaBridge 171:3a7713b1edbc 1599
AnnaBridge 171:3a7713b1edbc 1600 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1601 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1602 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1603
AnnaBridge 171:3a7713b1edbc 1604 /*!
AnnaBridge 171:3a7713b1edbc 1605 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1606 * @{
AnnaBridge 171:3a7713b1edbc 1607 */
AnnaBridge 171:3a7713b1edbc 1608
AnnaBridge 171:3a7713b1edbc 1609 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1610 typedef struct {
AnnaBridge 171:3a7713b1edbc 1611 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1612 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1613 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1614 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1615 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1616 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1617 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 1618
AnnaBridge 171:3a7713b1edbc 1619 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1620 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 1621 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1622
AnnaBridge 171:3a7713b1edbc 1623 /*!
AnnaBridge 171:3a7713b1edbc 1624 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 1625 * @{
AnnaBridge 171:3a7713b1edbc 1626 */
AnnaBridge 171:3a7713b1edbc 1627
AnnaBridge 171:3a7713b1edbc 1628 /*! @name PDOR - Port Data Output Register */
AnnaBridge 171:3a7713b1edbc 1629 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1630 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1631 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 1632
AnnaBridge 171:3a7713b1edbc 1633 /*! @name PSOR - Port Set Output Register */
AnnaBridge 171:3a7713b1edbc 1634 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1635 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1636 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 1637
AnnaBridge 171:3a7713b1edbc 1638 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 171:3a7713b1edbc 1639 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1640 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1641 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 1642
AnnaBridge 171:3a7713b1edbc 1643 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 171:3a7713b1edbc 1644 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1645 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1646 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 1647
AnnaBridge 171:3a7713b1edbc 1648 /*! @name PDIR - Port Data Input Register */
AnnaBridge 171:3a7713b1edbc 1649 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1650 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1651 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 1652
AnnaBridge 171:3a7713b1edbc 1653 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 171:3a7713b1edbc 1654 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1655 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1656 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 1657
AnnaBridge 171:3a7713b1edbc 1658
AnnaBridge 171:3a7713b1edbc 1659 /*!
AnnaBridge 171:3a7713b1edbc 1660 * @}
AnnaBridge 171:3a7713b1edbc 1661 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1662
AnnaBridge 171:3a7713b1edbc 1663
AnnaBridge 171:3a7713b1edbc 1664 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1665 /** Peripheral GPIOA base address */
AnnaBridge 171:3a7713b1edbc 1666 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 1667 /** Peripheral GPIOA base pointer */
AnnaBridge 171:3a7713b1edbc 1668 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 1669 /** Peripheral GPIOB base address */
AnnaBridge 171:3a7713b1edbc 1670 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 1671 /** Peripheral GPIOB base pointer */
AnnaBridge 171:3a7713b1edbc 1672 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 1673 /** Peripheral GPIOC base address */
AnnaBridge 171:3a7713b1edbc 1674 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 1675 /** Peripheral GPIOC base pointer */
AnnaBridge 171:3a7713b1edbc 1676 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 1677 /** Peripheral GPIOD base address */
AnnaBridge 171:3a7713b1edbc 1678 #define GPIOD_BASE (0x400FF0C0u)
AnnaBridge 171:3a7713b1edbc 1679 /** Peripheral GPIOD base pointer */
AnnaBridge 171:3a7713b1edbc 1680 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 1681 /** Peripheral GPIOE base address */
AnnaBridge 171:3a7713b1edbc 1682 #define GPIOE_BASE (0x400FF100u)
AnnaBridge 171:3a7713b1edbc 1683 /** Peripheral GPIOE base pointer */
AnnaBridge 171:3a7713b1edbc 1684 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 1685 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1686 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
AnnaBridge 171:3a7713b1edbc 1687 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1688 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
AnnaBridge 171:3a7713b1edbc 1689
AnnaBridge 171:3a7713b1edbc 1690 /*!
AnnaBridge 171:3a7713b1edbc 1691 * @}
AnnaBridge 171:3a7713b1edbc 1692 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1693
AnnaBridge 171:3a7713b1edbc 1694
AnnaBridge 171:3a7713b1edbc 1695 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1696 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1697 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1698
AnnaBridge 171:3a7713b1edbc 1699 /*!
AnnaBridge 171:3a7713b1edbc 1700 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1701 * @{
AnnaBridge 171:3a7713b1edbc 1702 */
AnnaBridge 171:3a7713b1edbc 1703
AnnaBridge 171:3a7713b1edbc 1704 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1705 typedef struct {
AnnaBridge 171:3a7713b1edbc 1706 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1707 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1708 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1709 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1710 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1711 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1712 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1713 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1714 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1715 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1716 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1717 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1718 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1719 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 1720
AnnaBridge 171:3a7713b1edbc 1721 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1722 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 1723 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1724
AnnaBridge 171:3a7713b1edbc 1725 /*!
AnnaBridge 171:3a7713b1edbc 1726 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 1727 * @{
AnnaBridge 171:3a7713b1edbc 1728 */
AnnaBridge 171:3a7713b1edbc 1729
AnnaBridge 171:3a7713b1edbc 1730 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 171:3a7713b1edbc 1731 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 1732 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1733 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 1734
AnnaBridge 171:3a7713b1edbc 1735 /*! @name F - I2C Frequency Divider register */
AnnaBridge 171:3a7713b1edbc 1736 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 1737 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1738 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 1739 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 1740 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1741 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 1742
AnnaBridge 171:3a7713b1edbc 1743 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 171:3a7713b1edbc 1744 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1745 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1746 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 1747 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1748 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1749 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 171:3a7713b1edbc 1750 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1751 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1752 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 1753 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1754 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1755 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 171:3a7713b1edbc 1756 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1757 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1758 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 1759 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1760 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1761 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 171:3a7713b1edbc 1762 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1763 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1764 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 171:3a7713b1edbc 1765 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1766 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1767 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 171:3a7713b1edbc 1768
AnnaBridge 171:3a7713b1edbc 1769 /*! @name S - I2C Status register */
AnnaBridge 171:3a7713b1edbc 1770 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1771 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1772 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 171:3a7713b1edbc 1773 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1774 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1775 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 171:3a7713b1edbc 1776 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1777 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1778 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 1779 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1780 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1781 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 171:3a7713b1edbc 1782 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1783 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1784 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 171:3a7713b1edbc 1785 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1786 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1787 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 1788 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1789 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1790 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 171:3a7713b1edbc 1791 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1792 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1793 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 1794
AnnaBridge 171:3a7713b1edbc 1795 /*! @name D - I2C Data I/O register */
AnnaBridge 171:3a7713b1edbc 1796 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1797 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1798 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 1799
AnnaBridge 171:3a7713b1edbc 1800 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 171:3a7713b1edbc 1801 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 1802 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1803 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 1804 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1805 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1806 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 171:3a7713b1edbc 1807 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1808 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1809 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 171:3a7713b1edbc 1810 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1811 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1812 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 171:3a7713b1edbc 1813 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1814 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1815 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 171:3a7713b1edbc 1816 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1817 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1818 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 171:3a7713b1edbc 1819
AnnaBridge 171:3a7713b1edbc 1820 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
AnnaBridge 171:3a7713b1edbc 1821 #define I2C_FLT_FLT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1822 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1823 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 1824 #define I2C_FLT_STARTF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1825 #define I2C_FLT_STARTF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1826 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
AnnaBridge 171:3a7713b1edbc 1827 #define I2C_FLT_SSIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1828 #define I2C_FLT_SSIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1829 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
AnnaBridge 171:3a7713b1edbc 1830 #define I2C_FLT_STOPF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1831 #define I2C_FLT_STOPF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1832 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
AnnaBridge 171:3a7713b1edbc 1833 #define I2C_FLT_SHEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1834 #define I2C_FLT_SHEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1835 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
AnnaBridge 171:3a7713b1edbc 1836
AnnaBridge 171:3a7713b1edbc 1837 /*! @name RA - I2C Range Address register */
AnnaBridge 171:3a7713b1edbc 1838 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 1839 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1840 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 1841
AnnaBridge 171:3a7713b1edbc 1842 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 171:3a7713b1edbc 1843 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1844 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1845 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 171:3a7713b1edbc 1846 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1847 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1848 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 171:3a7713b1edbc 1849 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1850 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1851 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 171:3a7713b1edbc 1852 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1853 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1854 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 171:3a7713b1edbc 1855 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1856 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1857 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1858 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1859 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1860 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 171:3a7713b1edbc 1861 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1862 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1863 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 171:3a7713b1edbc 1864 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1865 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1866 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 171:3a7713b1edbc 1867
AnnaBridge 171:3a7713b1edbc 1868 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 171:3a7713b1edbc 1869 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 1870 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1871 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 1872
AnnaBridge 171:3a7713b1edbc 1873 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 171:3a7713b1edbc 1874 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1875 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1876 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 1877
AnnaBridge 171:3a7713b1edbc 1878 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 171:3a7713b1edbc 1879 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1880 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1881 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 1882
AnnaBridge 171:3a7713b1edbc 1883 /*! @name S2 - I2C Status register 2 */
AnnaBridge 171:3a7713b1edbc 1884 #define I2C_S2_EMPTY_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1885 #define I2C_S2_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1886 #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 1887 #define I2C_S2_ERROR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1888 #define I2C_S2_ERROR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1889 #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 1890
AnnaBridge 171:3a7713b1edbc 1891
AnnaBridge 171:3a7713b1edbc 1892 /*!
AnnaBridge 171:3a7713b1edbc 1893 * @}
AnnaBridge 171:3a7713b1edbc 1894 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1895
AnnaBridge 171:3a7713b1edbc 1896
AnnaBridge 171:3a7713b1edbc 1897 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1898 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 1899 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 1900 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 1901 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 1902 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 1903 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 1904 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 1905 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 1906 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1907 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
AnnaBridge 171:3a7713b1edbc 1908 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1909 #define I2C_BASE_PTRS { I2C0, I2C1 }
AnnaBridge 171:3a7713b1edbc 1910 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 171:3a7713b1edbc 1911 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
AnnaBridge 171:3a7713b1edbc 1912
AnnaBridge 171:3a7713b1edbc 1913 /*!
AnnaBridge 171:3a7713b1edbc 1914 * @}
AnnaBridge 171:3a7713b1edbc 1915 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1916
AnnaBridge 171:3a7713b1edbc 1917
AnnaBridge 171:3a7713b1edbc 1918 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1919 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1920 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1921
AnnaBridge 171:3a7713b1edbc 1922 /*!
AnnaBridge 171:3a7713b1edbc 1923 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1924 * @{
AnnaBridge 171:3a7713b1edbc 1925 */
AnnaBridge 171:3a7713b1edbc 1926
AnnaBridge 171:3a7713b1edbc 1927 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1928 typedef struct {
AnnaBridge 171:3a7713b1edbc 1929 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1930 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1931 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1932 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1933 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1934 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1935 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1936 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1937 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1938 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1939 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 1940
AnnaBridge 171:3a7713b1edbc 1941 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1942 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 1943 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1944
AnnaBridge 171:3a7713b1edbc 1945 /*!
AnnaBridge 171:3a7713b1edbc 1946 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 1947 * @{
AnnaBridge 171:3a7713b1edbc 1948 */
AnnaBridge 171:3a7713b1edbc 1949
AnnaBridge 171:3a7713b1edbc 1950 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 171:3a7713b1edbc 1951 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1952 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1953 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 1954 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 1955 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1956 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 1957 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1958 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1959 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 1960 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 1961 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1962 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 1963
AnnaBridge 171:3a7713b1edbc 1964 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 171:3a7713b1edbc 1965 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1966 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1967 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 1968 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 1969 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1970 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 1971 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1972 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1973 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 1974 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 1975 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1976 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 1977
AnnaBridge 171:3a7713b1edbc 1978 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 171:3a7713b1edbc 1979 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1980 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1981 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 1982 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 1983 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1984 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 1985 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 1986 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1987 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 1988 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 1989 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1990 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 1991
AnnaBridge 171:3a7713b1edbc 1992 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 171:3a7713b1edbc 1993 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1994 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1995 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 1996 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 1997 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1998 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 1999 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2000 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2001 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 2002 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 2003 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2004 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 2005
AnnaBridge 171:3a7713b1edbc 2006 /*! @name ME - LLWU Module Enable register */
AnnaBridge 171:3a7713b1edbc 2007 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2008 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2009 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 171:3a7713b1edbc 2010 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2011 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2012 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 171:3a7713b1edbc 2013 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2014 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2015 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 171:3a7713b1edbc 2016 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2017 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2018 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 171:3a7713b1edbc 2019 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2020 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2021 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 171:3a7713b1edbc 2022 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2023 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2024 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 171:3a7713b1edbc 2025 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2026 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2027 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 171:3a7713b1edbc 2028 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2029 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2030 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 171:3a7713b1edbc 2031
AnnaBridge 171:3a7713b1edbc 2032 /*! @name F1 - LLWU Flag 1 register */
AnnaBridge 171:3a7713b1edbc 2033 #define LLWU_F1_WUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2034 #define LLWU_F1_WUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2035 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
AnnaBridge 171:3a7713b1edbc 2036 #define LLWU_F1_WUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2037 #define LLWU_F1_WUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2038 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
AnnaBridge 171:3a7713b1edbc 2039 #define LLWU_F1_WUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2040 #define LLWU_F1_WUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2041 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
AnnaBridge 171:3a7713b1edbc 2042 #define LLWU_F1_WUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2043 #define LLWU_F1_WUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2044 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
AnnaBridge 171:3a7713b1edbc 2045 #define LLWU_F1_WUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2046 #define LLWU_F1_WUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2047 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
AnnaBridge 171:3a7713b1edbc 2048 #define LLWU_F1_WUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2049 #define LLWU_F1_WUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2050 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
AnnaBridge 171:3a7713b1edbc 2051 #define LLWU_F1_WUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2052 #define LLWU_F1_WUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2053 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
AnnaBridge 171:3a7713b1edbc 2054 #define LLWU_F1_WUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2055 #define LLWU_F1_WUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2056 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
AnnaBridge 171:3a7713b1edbc 2057
AnnaBridge 171:3a7713b1edbc 2058 /*! @name F2 - LLWU Flag 2 register */
AnnaBridge 171:3a7713b1edbc 2059 #define LLWU_F2_WUF8_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2060 #define LLWU_F2_WUF8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2061 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
AnnaBridge 171:3a7713b1edbc 2062 #define LLWU_F2_WUF9_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2063 #define LLWU_F2_WUF9_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2064 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
AnnaBridge 171:3a7713b1edbc 2065 #define LLWU_F2_WUF10_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2066 #define LLWU_F2_WUF10_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2067 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
AnnaBridge 171:3a7713b1edbc 2068 #define LLWU_F2_WUF11_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2069 #define LLWU_F2_WUF11_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2070 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
AnnaBridge 171:3a7713b1edbc 2071 #define LLWU_F2_WUF12_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2072 #define LLWU_F2_WUF12_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2073 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
AnnaBridge 171:3a7713b1edbc 2074 #define LLWU_F2_WUF13_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2075 #define LLWU_F2_WUF13_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2076 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
AnnaBridge 171:3a7713b1edbc 2077 #define LLWU_F2_WUF14_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2078 #define LLWU_F2_WUF14_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2079 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
AnnaBridge 171:3a7713b1edbc 2080 #define LLWU_F2_WUF15_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2081 #define LLWU_F2_WUF15_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2082 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
AnnaBridge 171:3a7713b1edbc 2083
AnnaBridge 171:3a7713b1edbc 2084 /*! @name F3 - LLWU Flag 3 register */
AnnaBridge 171:3a7713b1edbc 2085 #define LLWU_F3_MWUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2086 #define LLWU_F3_MWUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2087 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
AnnaBridge 171:3a7713b1edbc 2088 #define LLWU_F3_MWUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2089 #define LLWU_F3_MWUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2090 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
AnnaBridge 171:3a7713b1edbc 2091 #define LLWU_F3_MWUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2092 #define LLWU_F3_MWUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2093 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
AnnaBridge 171:3a7713b1edbc 2094 #define LLWU_F3_MWUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2095 #define LLWU_F3_MWUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2096 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
AnnaBridge 171:3a7713b1edbc 2097 #define LLWU_F3_MWUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2098 #define LLWU_F3_MWUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2099 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
AnnaBridge 171:3a7713b1edbc 2100 #define LLWU_F3_MWUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2101 #define LLWU_F3_MWUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2102 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
AnnaBridge 171:3a7713b1edbc 2103 #define LLWU_F3_MWUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2104 #define LLWU_F3_MWUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2105 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
AnnaBridge 171:3a7713b1edbc 2106 #define LLWU_F3_MWUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2107 #define LLWU_F3_MWUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2108 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
AnnaBridge 171:3a7713b1edbc 2109
AnnaBridge 171:3a7713b1edbc 2110 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 171:3a7713b1edbc 2111 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2112 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2113 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2114 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 2115 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2116 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 2117 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2118 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2119 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 2120
AnnaBridge 171:3a7713b1edbc 2121 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 171:3a7713b1edbc 2122 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2123 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2124 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 2125 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 2126 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2127 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 2128 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2129 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2130 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 2131
AnnaBridge 171:3a7713b1edbc 2132
AnnaBridge 171:3a7713b1edbc 2133 /*!
AnnaBridge 171:3a7713b1edbc 2134 * @}
AnnaBridge 171:3a7713b1edbc 2135 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2136
AnnaBridge 171:3a7713b1edbc 2137
AnnaBridge 171:3a7713b1edbc 2138 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2139 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 2140 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 2141 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 2142 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 2143 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2144 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 171:3a7713b1edbc 2145 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2146 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 171:3a7713b1edbc 2147 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 171:3a7713b1edbc 2148 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 171:3a7713b1edbc 2149
AnnaBridge 171:3a7713b1edbc 2150 /*!
AnnaBridge 171:3a7713b1edbc 2151 * @}
AnnaBridge 171:3a7713b1edbc 2152 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2153
AnnaBridge 171:3a7713b1edbc 2154
AnnaBridge 171:3a7713b1edbc 2155 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2156 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2157 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2158
AnnaBridge 171:3a7713b1edbc 2159 /*!
AnnaBridge 171:3a7713b1edbc 2160 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2161 * @{
AnnaBridge 171:3a7713b1edbc 2162 */
AnnaBridge 171:3a7713b1edbc 2163
AnnaBridge 171:3a7713b1edbc 2164 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2165 typedef struct {
AnnaBridge 171:3a7713b1edbc 2166 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2167 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2168 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2169 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2170 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 2171
AnnaBridge 171:3a7713b1edbc 2172 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2173 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 2174 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2175
AnnaBridge 171:3a7713b1edbc 2176 /*!
AnnaBridge 171:3a7713b1edbc 2177 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 2178 * @{
AnnaBridge 171:3a7713b1edbc 2179 */
AnnaBridge 171:3a7713b1edbc 2180
AnnaBridge 171:3a7713b1edbc 2181 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 2182 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2183 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2184 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 2185 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2186 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2187 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 171:3a7713b1edbc 2188 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2189 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2190 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 171:3a7713b1edbc 2191 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2192 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2193 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 171:3a7713b1edbc 2194 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2195 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2196 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 2197 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2198 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2199 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 2200 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2201 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2202 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 2203
AnnaBridge 171:3a7713b1edbc 2204 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 171:3a7713b1edbc 2205 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 2206 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2207 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 2208 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2209 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2210 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 171:3a7713b1edbc 2211 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 171:3a7713b1edbc 2212 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2213 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 2214
AnnaBridge 171:3a7713b1edbc 2215 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 171:3a7713b1edbc 2216 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2217 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2218 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 2219
AnnaBridge 171:3a7713b1edbc 2220 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 171:3a7713b1edbc 2221 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2222 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2223 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 2224
AnnaBridge 171:3a7713b1edbc 2225
AnnaBridge 171:3a7713b1edbc 2226 /*!
AnnaBridge 171:3a7713b1edbc 2227 * @}
AnnaBridge 171:3a7713b1edbc 2228 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2229
AnnaBridge 171:3a7713b1edbc 2230
AnnaBridge 171:3a7713b1edbc 2231 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2232 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 2233 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 2234 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 2235 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 2236 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2237 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
AnnaBridge 171:3a7713b1edbc 2238 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2239 #define LPTMR_BASE_PTRS { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 2240 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 171:3a7713b1edbc 2241 #define LPTMR_IRQS { LPTMR0_IRQn }
AnnaBridge 171:3a7713b1edbc 2242
AnnaBridge 171:3a7713b1edbc 2243 /*!
AnnaBridge 171:3a7713b1edbc 2244 * @}
AnnaBridge 171:3a7713b1edbc 2245 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2246
AnnaBridge 171:3a7713b1edbc 2247
AnnaBridge 171:3a7713b1edbc 2248 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2249 -- LPUART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2250 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2251
AnnaBridge 171:3a7713b1edbc 2252 /*!
AnnaBridge 171:3a7713b1edbc 2253 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2254 * @{
AnnaBridge 171:3a7713b1edbc 2255 */
AnnaBridge 171:3a7713b1edbc 2256
AnnaBridge 171:3a7713b1edbc 2257 /** LPUART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2258 typedef struct {
AnnaBridge 171:3a7713b1edbc 2259 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2260 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2261 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2262 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2263 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2264 } LPUART_Type;
AnnaBridge 171:3a7713b1edbc 2265
AnnaBridge 171:3a7713b1edbc 2266 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2267 -- LPUART Register Masks
AnnaBridge 171:3a7713b1edbc 2268 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2269
AnnaBridge 171:3a7713b1edbc 2270 /*!
AnnaBridge 171:3a7713b1edbc 2271 * @addtogroup LPUART_Register_Masks LPUART Register Masks
AnnaBridge 171:3a7713b1edbc 2272 * @{
AnnaBridge 171:3a7713b1edbc 2273 */
AnnaBridge 171:3a7713b1edbc 2274
AnnaBridge 171:3a7713b1edbc 2275 /*! @name BAUD - LPUART Baud Rate Register */
AnnaBridge 171:3a7713b1edbc 2276 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 2277 #define LPUART_BAUD_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2278 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 2279 #define LPUART_BAUD_SBNS_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2280 #define LPUART_BAUD_SBNS_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2281 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
AnnaBridge 171:3a7713b1edbc 2282 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2283 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2284 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 2285 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2286 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2287 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
AnnaBridge 171:3a7713b1edbc 2288 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2289 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2290 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
AnnaBridge 171:3a7713b1edbc 2291 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2292 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2293 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
AnnaBridge 171:3a7713b1edbc 2294 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 2295 #define LPUART_BAUD_MATCFG_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2296 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
AnnaBridge 171:3a7713b1edbc 2297 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2298 #define LPUART_BAUD_RDMAE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2299 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 2300 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2301 #define LPUART_BAUD_TDMAE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2302 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 2303 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 2304 #define LPUART_BAUD_OSR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2305 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
AnnaBridge 171:3a7713b1edbc 2306 #define LPUART_BAUD_M10_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 2307 #define LPUART_BAUD_M10_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2308 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
AnnaBridge 171:3a7713b1edbc 2309 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2310 #define LPUART_BAUD_MAEN2_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2311 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 2312 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2313 #define LPUART_BAUD_MAEN1_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2314 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 2315
AnnaBridge 171:3a7713b1edbc 2316 /*! @name STAT - LPUART Status Register */
AnnaBridge 171:3a7713b1edbc 2317 #define LPUART_STAT_MA2F_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2318 #define LPUART_STAT_MA2F_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2319 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
AnnaBridge 171:3a7713b1edbc 2320 #define LPUART_STAT_MA1F_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2321 #define LPUART_STAT_MA1F_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2322 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
AnnaBridge 171:3a7713b1edbc 2323 #define LPUART_STAT_PF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2324 #define LPUART_STAT_PF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2325 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
AnnaBridge 171:3a7713b1edbc 2326 #define LPUART_STAT_FE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2327 #define LPUART_STAT_FE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2328 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
AnnaBridge 171:3a7713b1edbc 2329 #define LPUART_STAT_NF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2330 #define LPUART_STAT_NF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2331 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
AnnaBridge 171:3a7713b1edbc 2332 #define LPUART_STAT_OR_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2333 #define LPUART_STAT_OR_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2334 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
AnnaBridge 171:3a7713b1edbc 2335 #define LPUART_STAT_IDLE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2336 #define LPUART_STAT_IDLE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2337 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 2338 #define LPUART_STAT_RDRF_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2339 #define LPUART_STAT_RDRF_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2340 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 2341 #define LPUART_STAT_TC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2342 #define LPUART_STAT_TC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2343 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
AnnaBridge 171:3a7713b1edbc 2344 #define LPUART_STAT_TDRE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2345 #define LPUART_STAT_TDRE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2346 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 2347 #define LPUART_STAT_RAF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2348 #define LPUART_STAT_RAF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2349 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 2350 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 2351 #define LPUART_STAT_LBKDE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 2352 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
AnnaBridge 171:3a7713b1edbc 2353 #define LPUART_STAT_BRK13_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 2354 #define LPUART_STAT_BRK13_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 2355 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 2356 #define LPUART_STAT_RWUID_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 2357 #define LPUART_STAT_RWUID_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 2358 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 2359 #define LPUART_STAT_RXINV_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2360 #define LPUART_STAT_RXINV_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2361 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 2362 #define LPUART_STAT_MSBF_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 2363 #define LPUART_STAT_MSBF_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2364 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 2365 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2366 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2367 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 2368 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2369 #define LPUART_STAT_LBKDIF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2370 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
AnnaBridge 171:3a7713b1edbc 2371
AnnaBridge 171:3a7713b1edbc 2372 /*! @name CTRL - LPUART Control Register */
AnnaBridge 171:3a7713b1edbc 2373 #define LPUART_CTRL_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2374 #define LPUART_CTRL_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2375 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 2376 #define LPUART_CTRL_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2377 #define LPUART_CTRL_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2378 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
AnnaBridge 171:3a7713b1edbc 2379 #define LPUART_CTRL_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2380 #define LPUART_CTRL_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2381 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 2382 #define LPUART_CTRL_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2383 #define LPUART_CTRL_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2384 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 2385 #define LPUART_CTRL_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2386 #define LPUART_CTRL_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2387 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
AnnaBridge 171:3a7713b1edbc 2388 #define LPUART_CTRL_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2389 #define LPUART_CTRL_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2390 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2391 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2392 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2393 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
AnnaBridge 171:3a7713b1edbc 2394 #define LPUART_CTRL_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2395 #define LPUART_CTRL_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2396 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 2397 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 2398 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2399 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
AnnaBridge 171:3a7713b1edbc 2400 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2401 #define LPUART_CTRL_MA2IE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2402 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
AnnaBridge 171:3a7713b1edbc 2403 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2404 #define LPUART_CTRL_MA1IE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2405 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
AnnaBridge 171:3a7713b1edbc 2406 #define LPUART_CTRL_SBK_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2407 #define LPUART_CTRL_SBK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2408 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 2409 #define LPUART_CTRL_RWU_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2410 #define LPUART_CTRL_RWU_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2411 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 2412 #define LPUART_CTRL_RE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2413 #define LPUART_CTRL_RE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2414 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
AnnaBridge 171:3a7713b1edbc 2415 #define LPUART_CTRL_TE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2416 #define LPUART_CTRL_TE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2417 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
AnnaBridge 171:3a7713b1edbc 2418 #define LPUART_CTRL_ILIE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2419 #define LPUART_CTRL_ILIE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2420 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 2421 #define LPUART_CTRL_RIE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2422 #define LPUART_CTRL_RIE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2423 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 2424 #define LPUART_CTRL_TCIE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2425 #define LPUART_CTRL_TCIE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2426 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 2427 #define LPUART_CTRL_TIE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2428 #define LPUART_CTRL_TIE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2429 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 2430 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2431 #define LPUART_CTRL_PEIE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2432 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 2433 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 2434 #define LPUART_CTRL_FEIE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 2435 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 2436 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 2437 #define LPUART_CTRL_NEIE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 2438 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 2439 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 2440 #define LPUART_CTRL_ORIE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 2441 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 2442 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2443 #define LPUART_CTRL_TXINV_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2444 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 2445 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 2446 #define LPUART_CTRL_TXDIR_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2447 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 2448 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2449 #define LPUART_CTRL_R9T8_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2450 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
AnnaBridge 171:3a7713b1edbc 2451 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2452 #define LPUART_CTRL_R8T9_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2453 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
AnnaBridge 171:3a7713b1edbc 2454
AnnaBridge 171:3a7713b1edbc 2455 /*! @name DATA - LPUART Data Register */
AnnaBridge 171:3a7713b1edbc 2456 #define LPUART_DATA_R0T0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2457 #define LPUART_DATA_R0T0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2458 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
AnnaBridge 171:3a7713b1edbc 2459 #define LPUART_DATA_R1T1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2460 #define LPUART_DATA_R1T1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2461 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
AnnaBridge 171:3a7713b1edbc 2462 #define LPUART_DATA_R2T2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2463 #define LPUART_DATA_R2T2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2464 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
AnnaBridge 171:3a7713b1edbc 2465 #define LPUART_DATA_R3T3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2466 #define LPUART_DATA_R3T3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2467 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
AnnaBridge 171:3a7713b1edbc 2468 #define LPUART_DATA_R4T4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2469 #define LPUART_DATA_R4T4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2470 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
AnnaBridge 171:3a7713b1edbc 2471 #define LPUART_DATA_R5T5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2472 #define LPUART_DATA_R5T5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2473 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
AnnaBridge 171:3a7713b1edbc 2474 #define LPUART_DATA_R6T6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2475 #define LPUART_DATA_R6T6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2476 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
AnnaBridge 171:3a7713b1edbc 2477 #define LPUART_DATA_R7T7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2478 #define LPUART_DATA_R7T7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2479 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
AnnaBridge 171:3a7713b1edbc 2480 #define LPUART_DATA_R8T8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2481 #define LPUART_DATA_R8T8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2482 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
AnnaBridge 171:3a7713b1edbc 2483 #define LPUART_DATA_R9T9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2484 #define LPUART_DATA_R9T9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2485 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
AnnaBridge 171:3a7713b1edbc 2486 #define LPUART_DATA_IDLINE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2487 #define LPUART_DATA_IDLINE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2488 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
AnnaBridge 171:3a7713b1edbc 2489 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2490 #define LPUART_DATA_RXEMPT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2491 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 2492 #define LPUART_DATA_FRETSC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2493 #define LPUART_DATA_FRETSC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2494 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
AnnaBridge 171:3a7713b1edbc 2495 #define LPUART_DATA_PARITYE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2496 #define LPUART_DATA_PARITYE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2497 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
AnnaBridge 171:3a7713b1edbc 2498 #define LPUART_DATA_NOISY_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2499 #define LPUART_DATA_NOISY_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2500 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
AnnaBridge 171:3a7713b1edbc 2501
AnnaBridge 171:3a7713b1edbc 2502 /*! @name MATCH - LPUART Match Address Register */
AnnaBridge 171:3a7713b1edbc 2503 #define LPUART_MATCH_MA1_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 2504 #define LPUART_MATCH_MA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2505 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
AnnaBridge 171:3a7713b1edbc 2506 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 2507 #define LPUART_MATCH_MA2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2508 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
AnnaBridge 171:3a7713b1edbc 2509
AnnaBridge 171:3a7713b1edbc 2510
AnnaBridge 171:3a7713b1edbc 2511 /*!
AnnaBridge 171:3a7713b1edbc 2512 * @}
AnnaBridge 171:3a7713b1edbc 2513 */ /* end of group LPUART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2514
AnnaBridge 171:3a7713b1edbc 2515
AnnaBridge 171:3a7713b1edbc 2516 /* LPUART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2517 /** Peripheral LPUART0 base address */
AnnaBridge 171:3a7713b1edbc 2518 #define LPUART0_BASE (0x40054000u)
AnnaBridge 171:3a7713b1edbc 2519 /** Peripheral LPUART0 base pointer */
AnnaBridge 171:3a7713b1edbc 2520 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
AnnaBridge 171:3a7713b1edbc 2521 /** Peripheral LPUART1 base address */
AnnaBridge 171:3a7713b1edbc 2522 #define LPUART1_BASE (0x40055000u)
AnnaBridge 171:3a7713b1edbc 2523 /** Peripheral LPUART1 base pointer */
AnnaBridge 171:3a7713b1edbc 2524 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
AnnaBridge 171:3a7713b1edbc 2525 /** Array initializer of LPUART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2526 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
AnnaBridge 171:3a7713b1edbc 2527 /** Array initializer of LPUART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2528 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
AnnaBridge 171:3a7713b1edbc 2529 /** Interrupt vectors for the LPUART peripheral type */
AnnaBridge 171:3a7713b1edbc 2530 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
AnnaBridge 171:3a7713b1edbc 2531 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
AnnaBridge 171:3a7713b1edbc 2532
AnnaBridge 171:3a7713b1edbc 2533 /*!
AnnaBridge 171:3a7713b1edbc 2534 * @}
AnnaBridge 171:3a7713b1edbc 2535 */ /* end of group LPUART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2536
AnnaBridge 171:3a7713b1edbc 2537
AnnaBridge 171:3a7713b1edbc 2538 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2539 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2540 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2541
AnnaBridge 171:3a7713b1edbc 2542 /*!
AnnaBridge 171:3a7713b1edbc 2543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2544 * @{
AnnaBridge 171:3a7713b1edbc 2545 */
AnnaBridge 171:3a7713b1edbc 2546
AnnaBridge 171:3a7713b1edbc 2547 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2548 typedef struct {
AnnaBridge 171:3a7713b1edbc 2549 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2550 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2551 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 2552 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 2553 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 2554 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2555 uint8_t RESERVED_2[15];
AnnaBridge 171:3a7713b1edbc 2556 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 2557 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 2558
AnnaBridge 171:3a7713b1edbc 2559 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2560 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 2561 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2562
AnnaBridge 171:3a7713b1edbc 2563 /*!
AnnaBridge 171:3a7713b1edbc 2564 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 2565 * @{
AnnaBridge 171:3a7713b1edbc 2566 */
AnnaBridge 171:3a7713b1edbc 2567
AnnaBridge 171:3a7713b1edbc 2568 /*! @name C1 - MCG Control Register 1 */
AnnaBridge 171:3a7713b1edbc 2569 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2570 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2571 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 2572 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2573 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2574 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 2575 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 2576 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2577 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 2578
AnnaBridge 171:3a7713b1edbc 2579 /*! @name C2 - MCG Control Register 2 */
AnnaBridge 171:3a7713b1edbc 2580 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2581 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2582 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 171:3a7713b1edbc 2583 #define MCG_C2_EREFS0_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2584 #define MCG_C2_EREFS0_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2585 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK)
AnnaBridge 171:3a7713b1edbc 2586 #define MCG_C2_HGO0_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2587 #define MCG_C2_HGO0_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2588 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK)
AnnaBridge 171:3a7713b1edbc 2589 #define MCG_C2_RANGE0_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2590 #define MCG_C2_RANGE0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2591 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
AnnaBridge 171:3a7713b1edbc 2592
AnnaBridge 171:3a7713b1edbc 2593 /*! @name S - MCG Status Register */
AnnaBridge 171:3a7713b1edbc 2594 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2595 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2596 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 171:3a7713b1edbc 2597 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 2598 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2599 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 2600
AnnaBridge 171:3a7713b1edbc 2601 /*! @name SC - MCG Status and Control Register */
AnnaBridge 171:3a7713b1edbc 2602 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 2603 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2604 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 2605
AnnaBridge 171:3a7713b1edbc 2606 /*! @name MC - MCG Miscellaneous Control Register */
AnnaBridge 171:3a7713b1edbc 2607 #define MCG_MC_LIRC_DIV2_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2608 #define MCG_MC_LIRC_DIV2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2609 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_LIRC_DIV2_SHIFT)) & MCG_MC_LIRC_DIV2_MASK)
AnnaBridge 171:3a7713b1edbc 2610 #define MCG_MC_HIRCLPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2611 #define MCG_MC_HIRCLPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2612 #define MCG_MC_HIRCLPEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCLPEN_SHIFT)) & MCG_MC_HIRCLPEN_MASK)
AnnaBridge 171:3a7713b1edbc 2613 #define MCG_MC_HIRCEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2614 #define MCG_MC_HIRCEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2615 #define MCG_MC_HIRCEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_MC_HIRCEN_SHIFT)) & MCG_MC_HIRCEN_MASK)
AnnaBridge 171:3a7713b1edbc 2616
AnnaBridge 171:3a7713b1edbc 2617
AnnaBridge 171:3a7713b1edbc 2618 /*!
AnnaBridge 171:3a7713b1edbc 2619 * @}
AnnaBridge 171:3a7713b1edbc 2620 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2621
AnnaBridge 171:3a7713b1edbc 2622
AnnaBridge 171:3a7713b1edbc 2623 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2624 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 2625 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 2626 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 2627 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 2628 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2629 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 171:3a7713b1edbc 2630 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2631 #define MCG_BASE_PTRS { MCG }
AnnaBridge 171:3a7713b1edbc 2632
AnnaBridge 171:3a7713b1edbc 2633 /*!
AnnaBridge 171:3a7713b1edbc 2634 * @}
AnnaBridge 171:3a7713b1edbc 2635 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2636
AnnaBridge 171:3a7713b1edbc 2637
AnnaBridge 171:3a7713b1edbc 2638 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2639 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2640 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2641
AnnaBridge 171:3a7713b1edbc 2642 /*!
AnnaBridge 171:3a7713b1edbc 2643 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2644 * @{
AnnaBridge 171:3a7713b1edbc 2645 */
AnnaBridge 171:3a7713b1edbc 2646
AnnaBridge 171:3a7713b1edbc 2647 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2648 typedef struct {
AnnaBridge 171:3a7713b1edbc 2649 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 2650 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2651 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 2652 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2653 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 2654 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 2655 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 2656
AnnaBridge 171:3a7713b1edbc 2657 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2658 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 2659 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2660
AnnaBridge 171:3a7713b1edbc 2661 /*!
AnnaBridge 171:3a7713b1edbc 2662 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 2663 * @{
AnnaBridge 171:3a7713b1edbc 2664 */
AnnaBridge 171:3a7713b1edbc 2665
AnnaBridge 171:3a7713b1edbc 2666 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 171:3a7713b1edbc 2667 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2668 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2669 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 2670
AnnaBridge 171:3a7713b1edbc 2671 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 171:3a7713b1edbc 2672 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2673 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2674 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 2675
AnnaBridge 171:3a7713b1edbc 2676 /*! @name PLACR - Platform Control Register */
AnnaBridge 171:3a7713b1edbc 2677 #define MCM_PLACR_ARB_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2678 #define MCM_PLACR_ARB_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2679 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
AnnaBridge 171:3a7713b1edbc 2680 #define MCM_PLACR_CFCC_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2681 #define MCM_PLACR_CFCC_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2682 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
AnnaBridge 171:3a7713b1edbc 2683 #define MCM_PLACR_DFCDA_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2684 #define MCM_PLACR_DFCDA_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2685 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
AnnaBridge 171:3a7713b1edbc 2686 #define MCM_PLACR_DFCIC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2687 #define MCM_PLACR_DFCIC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2688 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
AnnaBridge 171:3a7713b1edbc 2689 #define MCM_PLACR_DFCC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2690 #define MCM_PLACR_DFCC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2691 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
AnnaBridge 171:3a7713b1edbc 2692 #define MCM_PLACR_EFDS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2693 #define MCM_PLACR_EFDS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2694 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
AnnaBridge 171:3a7713b1edbc 2695 #define MCM_PLACR_DFCS_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2696 #define MCM_PLACR_DFCS_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2697 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
AnnaBridge 171:3a7713b1edbc 2698 #define MCM_PLACR_ESFC_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2699 #define MCM_PLACR_ESFC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2700 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
AnnaBridge 171:3a7713b1edbc 2701
AnnaBridge 171:3a7713b1edbc 2702 /*! @name CPO - Compute Operation Control Register */
AnnaBridge 171:3a7713b1edbc 2703 #define MCM_CPO_CPOREQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2704 #define MCM_CPO_CPOREQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2705 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
AnnaBridge 171:3a7713b1edbc 2706 #define MCM_CPO_CPOACK_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2707 #define MCM_CPO_CPOACK_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2708 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
AnnaBridge 171:3a7713b1edbc 2709 #define MCM_CPO_CPOWOI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2710 #define MCM_CPO_CPOWOI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2711 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
AnnaBridge 171:3a7713b1edbc 2712
AnnaBridge 171:3a7713b1edbc 2713
AnnaBridge 171:3a7713b1edbc 2714 /*!
AnnaBridge 171:3a7713b1edbc 2715 * @}
AnnaBridge 171:3a7713b1edbc 2716 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2717
AnnaBridge 171:3a7713b1edbc 2718
AnnaBridge 171:3a7713b1edbc 2719 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2720 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 2721 #define MCM_BASE (0xF0003000u)
AnnaBridge 171:3a7713b1edbc 2722 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 2723 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 2724 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2725 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 171:3a7713b1edbc 2726 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2727 #define MCM_BASE_PTRS { MCM }
AnnaBridge 171:3a7713b1edbc 2728
AnnaBridge 171:3a7713b1edbc 2729 /*!
AnnaBridge 171:3a7713b1edbc 2730 * @}
AnnaBridge 171:3a7713b1edbc 2731 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2732
AnnaBridge 171:3a7713b1edbc 2733
AnnaBridge 171:3a7713b1edbc 2734 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2735 -- MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2736 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2737
AnnaBridge 171:3a7713b1edbc 2738 /*!
AnnaBridge 171:3a7713b1edbc 2739 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2740 * @{
AnnaBridge 171:3a7713b1edbc 2741 */
AnnaBridge 171:3a7713b1edbc 2742
AnnaBridge 171:3a7713b1edbc 2743 /** MTB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2744 typedef struct {
AnnaBridge 171:3a7713b1edbc 2745 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2746 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2747 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2748 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2749 uint8_t RESERVED_0[3824];
AnnaBridge 171:3a7713b1edbc 2750 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
AnnaBridge 171:3a7713b1edbc 2751 uint8_t RESERVED_1[156];
AnnaBridge 171:3a7713b1edbc 2752 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
AnnaBridge 171:3a7713b1edbc 2753 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
AnnaBridge 171:3a7713b1edbc 2754 uint8_t RESERVED_2[8];
AnnaBridge 171:3a7713b1edbc 2755 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
AnnaBridge 171:3a7713b1edbc 2756 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
AnnaBridge 171:3a7713b1edbc 2757 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
AnnaBridge 171:3a7713b1edbc 2758 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
AnnaBridge 171:3a7713b1edbc 2759 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 2760 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 2761 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 2762 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2763 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2764 } MTB_Type;
AnnaBridge 171:3a7713b1edbc 2765
AnnaBridge 171:3a7713b1edbc 2766 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2767 -- MTB Register Masks
AnnaBridge 171:3a7713b1edbc 2768 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2769
AnnaBridge 171:3a7713b1edbc 2770 /*!
AnnaBridge 171:3a7713b1edbc 2771 * @addtogroup MTB_Register_Masks MTB Register Masks
AnnaBridge 171:3a7713b1edbc 2772 * @{
AnnaBridge 171:3a7713b1edbc 2773 */
AnnaBridge 171:3a7713b1edbc 2774
AnnaBridge 171:3a7713b1edbc 2775 /*! @name POSITION - MTB Position Register */
AnnaBridge 171:3a7713b1edbc 2776 #define MTB_POSITION_WRAP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2777 #define MTB_POSITION_WRAP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2778 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
AnnaBridge 171:3a7713b1edbc 2779 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 2780 #define MTB_POSITION_POINTER_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2781 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
AnnaBridge 171:3a7713b1edbc 2782
AnnaBridge 171:3a7713b1edbc 2783 /*! @name MASTER - MTB Master Register */
AnnaBridge 171:3a7713b1edbc 2784 #define MTB_MASTER_MASK_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 2785 #define MTB_MASTER_MASK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2786 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 2787 #define MTB_MASTER_TSTARTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2788 #define MTB_MASTER_TSTARTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2789 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
AnnaBridge 171:3a7713b1edbc 2790 #define MTB_MASTER_TSTOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2791 #define MTB_MASTER_TSTOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2792 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 2793 #define MTB_MASTER_SFRWPRIV_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2794 #define MTB_MASTER_SFRWPRIV_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2795 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
AnnaBridge 171:3a7713b1edbc 2796 #define MTB_MASTER_RAMPRIV_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2797 #define MTB_MASTER_RAMPRIV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2798 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
AnnaBridge 171:3a7713b1edbc 2799 #define MTB_MASTER_HALTREQ_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2800 #define MTB_MASTER_HALTREQ_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2801 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
AnnaBridge 171:3a7713b1edbc 2802 #define MTB_MASTER_EN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2803 #define MTB_MASTER_EN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2804 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2805
AnnaBridge 171:3a7713b1edbc 2806 /*! @name FLOW - MTB Flow Register */
AnnaBridge 171:3a7713b1edbc 2807 #define MTB_FLOW_AUTOSTOP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2808 #define MTB_FLOW_AUTOSTOP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2809 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
AnnaBridge 171:3a7713b1edbc 2810 #define MTB_FLOW_AUTOHALT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2811 #define MTB_FLOW_AUTOHALT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2812 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
AnnaBridge 171:3a7713b1edbc 2813 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 2814 #define MTB_FLOW_WATERMARK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2815 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
AnnaBridge 171:3a7713b1edbc 2816
AnnaBridge 171:3a7713b1edbc 2817 /*! @name BASE - MTB Base Register */
AnnaBridge 171:3a7713b1edbc 2818 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2819 #define MTB_BASE_BASEADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2820 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
AnnaBridge 171:3a7713b1edbc 2821
AnnaBridge 171:3a7713b1edbc 2822 /*! @name MODECTRL - Integration Mode Control Register */
AnnaBridge 171:3a7713b1edbc 2823 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2824 #define MTB_MODECTRL_MODECTRL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2825 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 2826
AnnaBridge 171:3a7713b1edbc 2827 /*! @name TAGSET - Claim TAG Set Register */
AnnaBridge 171:3a7713b1edbc 2828 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2829 #define MTB_TAGSET_TAGSET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2830 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
AnnaBridge 171:3a7713b1edbc 2831
AnnaBridge 171:3a7713b1edbc 2832 /*! @name TAGCLEAR - Claim TAG Clear Register */
AnnaBridge 171:3a7713b1edbc 2833 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2834 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2835 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 2836
AnnaBridge 171:3a7713b1edbc 2837 /*! @name LOCKACCESS - Lock Access Register */
AnnaBridge 171:3a7713b1edbc 2838 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2839 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2840 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 2841
AnnaBridge 171:3a7713b1edbc 2842 /*! @name LOCKSTAT - Lock Status Register */
AnnaBridge 171:3a7713b1edbc 2843 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2844 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2845 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 2846
AnnaBridge 171:3a7713b1edbc 2847 /*! @name AUTHSTAT - Authentication Status Register */
AnnaBridge 171:3a7713b1edbc 2848 #define MTB_AUTHSTAT_BIT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2849 #define MTB_AUTHSTAT_BIT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2850 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
AnnaBridge 171:3a7713b1edbc 2851 #define MTB_AUTHSTAT_BIT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2852 #define MTB_AUTHSTAT_BIT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2853 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
AnnaBridge 171:3a7713b1edbc 2854 #define MTB_AUTHSTAT_BIT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2855 #define MTB_AUTHSTAT_BIT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2856 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
AnnaBridge 171:3a7713b1edbc 2857 #define MTB_AUTHSTAT_BIT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2858 #define MTB_AUTHSTAT_BIT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2859 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
AnnaBridge 171:3a7713b1edbc 2860
AnnaBridge 171:3a7713b1edbc 2861 /*! @name DEVICEARCH - Device Architecture Register */
AnnaBridge 171:3a7713b1edbc 2862 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2863 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2864 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
AnnaBridge 171:3a7713b1edbc 2865
AnnaBridge 171:3a7713b1edbc 2866 /*! @name DEVICECFG - Device Configuration Register */
AnnaBridge 171:3a7713b1edbc 2867 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2868 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2869 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 2870
AnnaBridge 171:3a7713b1edbc 2871 /*! @name DEVICETYPID - Device Type Identifier Register */
AnnaBridge 171:3a7713b1edbc 2872 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2873 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2874 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 2875
AnnaBridge 171:3a7713b1edbc 2876 /*! @name PERIPHID - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 2877 #define MTB_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2878 #define MTB_PERIPHID_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2879 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID_PERIPHID_SHIFT)) & MTB_PERIPHID_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 2880
AnnaBridge 171:3a7713b1edbc 2881 /* The count of MTB_PERIPHID */
AnnaBridge 171:3a7713b1edbc 2882 #define MTB_PERIPHID_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 2883
AnnaBridge 171:3a7713b1edbc 2884 /*! @name COMPID - Component ID Register */
AnnaBridge 171:3a7713b1edbc 2885 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2886 #define MTB_COMPID_COMPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2887 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 2888
AnnaBridge 171:3a7713b1edbc 2889 /* The count of MTB_COMPID */
AnnaBridge 171:3a7713b1edbc 2890 #define MTB_COMPID_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2891
AnnaBridge 171:3a7713b1edbc 2892
AnnaBridge 171:3a7713b1edbc 2893 /*!
AnnaBridge 171:3a7713b1edbc 2894 * @}
AnnaBridge 171:3a7713b1edbc 2895 */ /* end of group MTB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2896
AnnaBridge 171:3a7713b1edbc 2897
AnnaBridge 171:3a7713b1edbc 2898 /* MTB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2899 /** Peripheral MTB base address */
AnnaBridge 171:3a7713b1edbc 2900 #define MTB_BASE (0xF0000000u)
AnnaBridge 171:3a7713b1edbc 2901 /** Peripheral MTB base pointer */
AnnaBridge 171:3a7713b1edbc 2902 #define MTB ((MTB_Type *)MTB_BASE)
AnnaBridge 171:3a7713b1edbc 2903 /** Array initializer of MTB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2904 #define MTB_BASE_ADDRS { MTB_BASE }
AnnaBridge 171:3a7713b1edbc 2905 /** Array initializer of MTB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2906 #define MTB_BASE_PTRS { MTB }
AnnaBridge 171:3a7713b1edbc 2907
AnnaBridge 171:3a7713b1edbc 2908 /*!
AnnaBridge 171:3a7713b1edbc 2909 * @}
AnnaBridge 171:3a7713b1edbc 2910 */ /* end of group MTB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2911
AnnaBridge 171:3a7713b1edbc 2912
AnnaBridge 171:3a7713b1edbc 2913 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2914 -- MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2915 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2916
AnnaBridge 171:3a7713b1edbc 2917 /*!
AnnaBridge 171:3a7713b1edbc 2918 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2919 * @{
AnnaBridge 171:3a7713b1edbc 2920 */
AnnaBridge 171:3a7713b1edbc 2921
AnnaBridge 171:3a7713b1edbc 2922 /** MTBDWT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2923 typedef struct {
AnnaBridge 171:3a7713b1edbc 2924 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2925 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 2926 struct { /* offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2927 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2928 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2929 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2930 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 2931 } COMPARATOR[2];
AnnaBridge 171:3a7713b1edbc 2932 uint8_t RESERVED_1[448];
AnnaBridge 171:3a7713b1edbc 2933 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 2934 uint8_t RESERVED_2[3524];
AnnaBridge 171:3a7713b1edbc 2935 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 2936 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 2937 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2938 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2939 } MTBDWT_Type;
AnnaBridge 171:3a7713b1edbc 2940
AnnaBridge 171:3a7713b1edbc 2941 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2942 -- MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 2943 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2944
AnnaBridge 171:3a7713b1edbc 2945 /*!
AnnaBridge 171:3a7713b1edbc 2946 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 2947 * @{
AnnaBridge 171:3a7713b1edbc 2948 */
AnnaBridge 171:3a7713b1edbc 2949
AnnaBridge 171:3a7713b1edbc 2950 /*! @name CTRL - MTB DWT Control Register */
AnnaBridge 171:3a7713b1edbc 2951 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2952 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2953 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
AnnaBridge 171:3a7713b1edbc 2954 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2955 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2956 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
AnnaBridge 171:3a7713b1edbc 2957
AnnaBridge 171:3a7713b1edbc 2958 /*! @name COMP - MTB_DWT Comparator Register */
AnnaBridge 171:3a7713b1edbc 2959 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2960 #define MTBDWT_COMP_COMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2961 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
AnnaBridge 171:3a7713b1edbc 2962
AnnaBridge 171:3a7713b1edbc 2963 /* The count of MTBDWT_COMP */
AnnaBridge 171:3a7713b1edbc 2964 #define MTBDWT_COMP_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 2965
AnnaBridge 171:3a7713b1edbc 2966 /*! @name MASK - MTB_DWT Comparator Mask Register */
AnnaBridge 171:3a7713b1edbc 2967 #define MTBDWT_MASK_MASK_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 2968 #define MTBDWT_MASK_MASK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2969 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 2970
AnnaBridge 171:3a7713b1edbc 2971 /* The count of MTBDWT_MASK */
AnnaBridge 171:3a7713b1edbc 2972 #define MTBDWT_MASK_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 2973
AnnaBridge 171:3a7713b1edbc 2974 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
AnnaBridge 171:3a7713b1edbc 2975 #define MTBDWT_FCT_FUNCTION_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2976 #define MTBDWT_FCT_FUNCTION_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2977 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
AnnaBridge 171:3a7713b1edbc 2978 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2979 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2980 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
AnnaBridge 171:3a7713b1edbc 2981 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 2982 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2983 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 2984 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 2985 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2986 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 2987 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2988 #define MTBDWT_FCT_MATCHED_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2989 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
AnnaBridge 171:3a7713b1edbc 2990
AnnaBridge 171:3a7713b1edbc 2991 /* The count of MTBDWT_FCT */
AnnaBridge 171:3a7713b1edbc 2992 #define MTBDWT_FCT_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 2993
AnnaBridge 171:3a7713b1edbc 2994 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
AnnaBridge 171:3a7713b1edbc 2995 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2996 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2997 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
AnnaBridge 171:3a7713b1edbc 2998 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2999 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3000 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
AnnaBridge 171:3a7713b1edbc 3001 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 3002 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3003 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
AnnaBridge 171:3a7713b1edbc 3004
AnnaBridge 171:3a7713b1edbc 3005 /*! @name DEVICECFG - Device Configuration Register */
AnnaBridge 171:3a7713b1edbc 3006 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3007 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3008 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 3009
AnnaBridge 171:3a7713b1edbc 3010 /*! @name DEVICETYPID - Device Type Identifier Register */
AnnaBridge 171:3a7713b1edbc 3011 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3012 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3013 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 3014
AnnaBridge 171:3a7713b1edbc 3015 /*! @name PERIPHID - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3016 #define MTBDWT_PERIPHID_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3017 #define MTBDWT_PERIPHID_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3018 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID_PERIPHID_SHIFT)) & MTBDWT_PERIPHID_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3019
AnnaBridge 171:3a7713b1edbc 3020 /* The count of MTBDWT_PERIPHID */
AnnaBridge 171:3a7713b1edbc 3021 #define MTBDWT_PERIPHID_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 3022
AnnaBridge 171:3a7713b1edbc 3023 /*! @name COMPID - Component ID Register */
AnnaBridge 171:3a7713b1edbc 3024 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3025 #define MTBDWT_COMPID_COMPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3026 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 3027
AnnaBridge 171:3a7713b1edbc 3028 /* The count of MTBDWT_COMPID */
AnnaBridge 171:3a7713b1edbc 3029 #define MTBDWT_COMPID_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 3030
AnnaBridge 171:3a7713b1edbc 3031
AnnaBridge 171:3a7713b1edbc 3032 /*!
AnnaBridge 171:3a7713b1edbc 3033 * @}
AnnaBridge 171:3a7713b1edbc 3034 */ /* end of group MTBDWT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3035
AnnaBridge 171:3a7713b1edbc 3036
AnnaBridge 171:3a7713b1edbc 3037 /* MTBDWT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3038 /** Peripheral MTBDWT base address */
AnnaBridge 171:3a7713b1edbc 3039 #define MTBDWT_BASE (0xF0001000u)
AnnaBridge 171:3a7713b1edbc 3040 /** Peripheral MTBDWT base pointer */
AnnaBridge 171:3a7713b1edbc 3041 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
AnnaBridge 171:3a7713b1edbc 3042 /** Array initializer of MTBDWT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3043 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
AnnaBridge 171:3a7713b1edbc 3044 /** Array initializer of MTBDWT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3045 #define MTBDWT_BASE_PTRS { MTBDWT }
AnnaBridge 171:3a7713b1edbc 3046
AnnaBridge 171:3a7713b1edbc 3047 /*!
AnnaBridge 171:3a7713b1edbc 3048 * @}
AnnaBridge 171:3a7713b1edbc 3049 */ /* end of group MTBDWT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3050
AnnaBridge 171:3a7713b1edbc 3051
AnnaBridge 171:3a7713b1edbc 3052 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3053 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3054 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3055
AnnaBridge 171:3a7713b1edbc 3056 /*!
AnnaBridge 171:3a7713b1edbc 3057 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3058 * @{
AnnaBridge 171:3a7713b1edbc 3059 */
AnnaBridge 171:3a7713b1edbc 3060
AnnaBridge 171:3a7713b1edbc 3061 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3062 typedef struct {
AnnaBridge 171:3a7713b1edbc 3063 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3064 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3065 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3066 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3067 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3068 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3069 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3070 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3071 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3072 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3073 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3074 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3075 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3076 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 3077 } NV_Type;
AnnaBridge 171:3a7713b1edbc 3078
AnnaBridge 171:3a7713b1edbc 3079 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3080 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 3081 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3082
AnnaBridge 171:3a7713b1edbc 3083 /*!
AnnaBridge 171:3a7713b1edbc 3084 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 3085 * @{
AnnaBridge 171:3a7713b1edbc 3086 */
AnnaBridge 171:3a7713b1edbc 3087
AnnaBridge 171:3a7713b1edbc 3088 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 171:3a7713b1edbc 3089 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3090 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3091 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3092
AnnaBridge 171:3a7713b1edbc 3093 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 171:3a7713b1edbc 3094 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3095 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3096 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3097
AnnaBridge 171:3a7713b1edbc 3098 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 171:3a7713b1edbc 3099 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3100 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3101 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3102
AnnaBridge 171:3a7713b1edbc 3103 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 171:3a7713b1edbc 3104 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3105 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3106 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3107
AnnaBridge 171:3a7713b1edbc 3108 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 171:3a7713b1edbc 3109 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3110 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3111 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3112
AnnaBridge 171:3a7713b1edbc 3113 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 171:3a7713b1edbc 3114 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3115 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3116 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3117
AnnaBridge 171:3a7713b1edbc 3118 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 171:3a7713b1edbc 3119 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3120 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3121 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3122
AnnaBridge 171:3a7713b1edbc 3123 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 171:3a7713b1edbc 3124 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3125 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3126 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 3127
AnnaBridge 171:3a7713b1edbc 3128 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 171:3a7713b1edbc 3129 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3130 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3131 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3132
AnnaBridge 171:3a7713b1edbc 3133 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 171:3a7713b1edbc 3134 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3135 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3136 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3137
AnnaBridge 171:3a7713b1edbc 3138 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 171:3a7713b1edbc 3139 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3140 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3141 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3142
AnnaBridge 171:3a7713b1edbc 3143 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 171:3a7713b1edbc 3144 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3145 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3146 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 3147
AnnaBridge 171:3a7713b1edbc 3148 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 171:3a7713b1edbc 3149 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3150 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3151 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 3152 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 3153 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3154 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 3155 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3156 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3157 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 3158 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3159 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3160 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 3161
AnnaBridge 171:3a7713b1edbc 3162 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 171:3a7713b1edbc 3163 #define NV_FOPT_LPBOOT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3164 #define NV_FOPT_LPBOOT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3165 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
AnnaBridge 171:3a7713b1edbc 3166 #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3167 #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3168 #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 3169 #define NV_FOPT_NMI_DIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3170 #define NV_FOPT_NMI_DIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3171 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 3172 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3173 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3174 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
AnnaBridge 171:3a7713b1edbc 3175 #define NV_FOPT_LPBOOT1_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3176 #define NV_FOPT_LPBOOT1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3177 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
AnnaBridge 171:3a7713b1edbc 3178 #define NV_FOPT_FAST_INIT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3179 #define NV_FOPT_FAST_INIT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3180 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 3181 #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3182 #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3183 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 3184
AnnaBridge 171:3a7713b1edbc 3185
AnnaBridge 171:3a7713b1edbc 3186 /*!
AnnaBridge 171:3a7713b1edbc 3187 * @}
AnnaBridge 171:3a7713b1edbc 3188 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3189
AnnaBridge 171:3a7713b1edbc 3190
AnnaBridge 171:3a7713b1edbc 3191 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3192 /** Peripheral FTFA_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 3193 #define FTFA_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 3194 /** Peripheral FTFA_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 3195 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 3196 /** Array initializer of NV peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3197 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
AnnaBridge 171:3a7713b1edbc 3198 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3199 #define NV_BASE_PTRS { FTFA_FlashConfig }
AnnaBridge 171:3a7713b1edbc 3200
AnnaBridge 171:3a7713b1edbc 3201 /*!
AnnaBridge 171:3a7713b1edbc 3202 * @}
AnnaBridge 171:3a7713b1edbc 3203 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3204
AnnaBridge 171:3a7713b1edbc 3205
AnnaBridge 171:3a7713b1edbc 3206 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3207 -- OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3208 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3209
AnnaBridge 171:3a7713b1edbc 3210 /*!
AnnaBridge 171:3a7713b1edbc 3211 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3212 * @{
AnnaBridge 171:3a7713b1edbc 3213 */
AnnaBridge 171:3a7713b1edbc 3214
AnnaBridge 171:3a7713b1edbc 3215 /** OSC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3216 typedef struct {
AnnaBridge 171:3a7713b1edbc 3217 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3218 } OSC_Type;
AnnaBridge 171:3a7713b1edbc 3219
AnnaBridge 171:3a7713b1edbc 3220 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3221 -- OSC Register Masks
AnnaBridge 171:3a7713b1edbc 3222 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3223
AnnaBridge 171:3a7713b1edbc 3224 /*!
AnnaBridge 171:3a7713b1edbc 3225 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 171:3a7713b1edbc 3226 * @{
AnnaBridge 171:3a7713b1edbc 3227 */
AnnaBridge 171:3a7713b1edbc 3228
AnnaBridge 171:3a7713b1edbc 3229 /*! @name CR - OSC Control Register */
AnnaBridge 171:3a7713b1edbc 3230 #define OSC_CR_SC16P_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3231 #define OSC_CR_SC16P_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3232 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 3233 #define OSC_CR_SC8P_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3234 #define OSC_CR_SC8P_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3235 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 3236 #define OSC_CR_SC4P_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3237 #define OSC_CR_SC4P_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3238 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 3239 #define OSC_CR_SC2P_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3240 #define OSC_CR_SC2P_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3241 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 3242 #define OSC_CR_EREFSTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3243 #define OSC_CR_EREFSTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3244 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 3245 #define OSC_CR_ERCLKEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3246 #define OSC_CR_ERCLKEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3247 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 3248
AnnaBridge 171:3a7713b1edbc 3249
AnnaBridge 171:3a7713b1edbc 3250 /*!
AnnaBridge 171:3a7713b1edbc 3251 * @}
AnnaBridge 171:3a7713b1edbc 3252 */ /* end of group OSC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3253
AnnaBridge 171:3a7713b1edbc 3254
AnnaBridge 171:3a7713b1edbc 3255 /* OSC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3256 /** Peripheral OSC0 base address */
AnnaBridge 171:3a7713b1edbc 3257 #define OSC0_BASE (0x40065000u)
AnnaBridge 171:3a7713b1edbc 3258 /** Peripheral OSC0 base pointer */
AnnaBridge 171:3a7713b1edbc 3259 #define OSC0 ((OSC_Type *)OSC0_BASE)
AnnaBridge 171:3a7713b1edbc 3260 /** Array initializer of OSC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3261 #define OSC_BASE_ADDRS { OSC0_BASE }
AnnaBridge 171:3a7713b1edbc 3262 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3263 #define OSC_BASE_PTRS { OSC0 }
AnnaBridge 171:3a7713b1edbc 3264
AnnaBridge 171:3a7713b1edbc 3265 /*!
AnnaBridge 171:3a7713b1edbc 3266 * @}
AnnaBridge 171:3a7713b1edbc 3267 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3268
AnnaBridge 171:3a7713b1edbc 3269
AnnaBridge 171:3a7713b1edbc 3270 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3271 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3272 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3273
AnnaBridge 171:3a7713b1edbc 3274 /*!
AnnaBridge 171:3a7713b1edbc 3275 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3276 * @{
AnnaBridge 171:3a7713b1edbc 3277 */
AnnaBridge 171:3a7713b1edbc 3278
AnnaBridge 171:3a7713b1edbc 3279 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3280 typedef struct {
AnnaBridge 171:3a7713b1edbc 3281 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3282 uint8_t RESERVED_0[220];
AnnaBridge 171:3a7713b1edbc 3283 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 3284 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 3285 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 3286 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3287 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3288 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3289 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3290 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 3291 } CHANNEL[2];
AnnaBridge 171:3a7713b1edbc 3292 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 3293
AnnaBridge 171:3a7713b1edbc 3294 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3295 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 3296 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3297
AnnaBridge 171:3a7713b1edbc 3298 /*!
AnnaBridge 171:3a7713b1edbc 3299 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 3300 * @{
AnnaBridge 171:3a7713b1edbc 3301 */
AnnaBridge 171:3a7713b1edbc 3302
AnnaBridge 171:3a7713b1edbc 3303 /*! @name MCR - PIT Module Control Register */
AnnaBridge 171:3a7713b1edbc 3304 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3305 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3306 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 3307 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3308 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3309 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 3310
AnnaBridge 171:3a7713b1edbc 3311 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
AnnaBridge 171:3a7713b1edbc 3312 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3313 #define PIT_LTMR64H_LTH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3314 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
AnnaBridge 171:3a7713b1edbc 3315
AnnaBridge 171:3a7713b1edbc 3316 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
AnnaBridge 171:3a7713b1edbc 3317 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3318 #define PIT_LTMR64L_LTL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3319 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
AnnaBridge 171:3a7713b1edbc 3320
AnnaBridge 171:3a7713b1edbc 3321 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 171:3a7713b1edbc 3322 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3323 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3324 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 3325
AnnaBridge 171:3a7713b1edbc 3326 /* The count of PIT_LDVAL */
AnnaBridge 171:3a7713b1edbc 3327 #define PIT_LDVAL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 3328
AnnaBridge 171:3a7713b1edbc 3329 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 171:3a7713b1edbc 3330 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3331 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3332 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 3333
AnnaBridge 171:3a7713b1edbc 3334 /* The count of PIT_CVAL */
AnnaBridge 171:3a7713b1edbc 3335 #define PIT_CVAL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 3336
AnnaBridge 171:3a7713b1edbc 3337 /*! @name TCTRL - Timer Control Register */
AnnaBridge 171:3a7713b1edbc 3338 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3339 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3340 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 3341 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3342 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3343 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 3344 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3345 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3346 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 171:3a7713b1edbc 3347
AnnaBridge 171:3a7713b1edbc 3348 /* The count of PIT_TCTRL */
AnnaBridge 171:3a7713b1edbc 3349 #define PIT_TCTRL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 3350
AnnaBridge 171:3a7713b1edbc 3351 /*! @name TFLG - Timer Flag Register */
AnnaBridge 171:3a7713b1edbc 3352 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3353 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3354 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 3355
AnnaBridge 171:3a7713b1edbc 3356 /* The count of PIT_TFLG */
AnnaBridge 171:3a7713b1edbc 3357 #define PIT_TFLG_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 3358
AnnaBridge 171:3a7713b1edbc 3359
AnnaBridge 171:3a7713b1edbc 3360 /*!
AnnaBridge 171:3a7713b1edbc 3361 * @}
AnnaBridge 171:3a7713b1edbc 3362 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3363
AnnaBridge 171:3a7713b1edbc 3364
AnnaBridge 171:3a7713b1edbc 3365 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3366 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 3367 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 3368 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 3369 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 3370 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3371 #define PIT_BASE_ADDRS { PIT_BASE }
AnnaBridge 171:3a7713b1edbc 3372 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3373 #define PIT_BASE_PTRS { PIT }
AnnaBridge 171:3a7713b1edbc 3374 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 171:3a7713b1edbc 3375 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
AnnaBridge 171:3a7713b1edbc 3376
AnnaBridge 171:3a7713b1edbc 3377 /*!
AnnaBridge 171:3a7713b1edbc 3378 * @}
AnnaBridge 171:3a7713b1edbc 3379 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3380
AnnaBridge 171:3a7713b1edbc 3381
AnnaBridge 171:3a7713b1edbc 3382 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3383 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3384 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3385
AnnaBridge 171:3a7713b1edbc 3386 /*!
AnnaBridge 171:3a7713b1edbc 3387 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3388 * @{
AnnaBridge 171:3a7713b1edbc 3389 */
AnnaBridge 171:3a7713b1edbc 3390
AnnaBridge 171:3a7713b1edbc 3391 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3392 typedef struct {
AnnaBridge 171:3a7713b1edbc 3393 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3394 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3395 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3396 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 3397
AnnaBridge 171:3a7713b1edbc 3398 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3399 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 3400 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3401
AnnaBridge 171:3a7713b1edbc 3402 /*!
AnnaBridge 171:3a7713b1edbc 3403 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 3404 * @{
AnnaBridge 171:3a7713b1edbc 3405 */
AnnaBridge 171:3a7713b1edbc 3406
AnnaBridge 171:3a7713b1edbc 3407 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 171:3a7713b1edbc 3408 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3409 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3410 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 3411 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3412 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3413 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 171:3a7713b1edbc 3414 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3415 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3416 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 171:3a7713b1edbc 3417 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3418 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3419 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 171:3a7713b1edbc 3420 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3421 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3422 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 171:3a7713b1edbc 3423
AnnaBridge 171:3a7713b1edbc 3424 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 171:3a7713b1edbc 3425 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3426 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3427 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 3428 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3429 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3430 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 171:3a7713b1edbc 3431 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3432 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3433 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 171:3a7713b1edbc 3434 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3435 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3436 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 171:3a7713b1edbc 3437
AnnaBridge 171:3a7713b1edbc 3438 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 171:3a7713b1edbc 3439 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3440 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3441 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 171:3a7713b1edbc 3442 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3443 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3444 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 171:3a7713b1edbc 3445 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3446 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3447 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 171:3a7713b1edbc 3448 #define PMC_REGSC_BGEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3449 #define PMC_REGSC_BGEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3450 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
AnnaBridge 171:3a7713b1edbc 3451 #define PMC_REGSC_VLPO_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3452 #define PMC_REGSC_VLPO_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3453 #define PMC_REGSC_VLPO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK)
AnnaBridge 171:3a7713b1edbc 3454
AnnaBridge 171:3a7713b1edbc 3455
AnnaBridge 171:3a7713b1edbc 3456 /*!
AnnaBridge 171:3a7713b1edbc 3457 * @}
AnnaBridge 171:3a7713b1edbc 3458 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3459
AnnaBridge 171:3a7713b1edbc 3460
AnnaBridge 171:3a7713b1edbc 3461 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3462 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 3463 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 3464 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 3465 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 3466 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3467 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 171:3a7713b1edbc 3468 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3469 #define PMC_BASE_PTRS { PMC }
AnnaBridge 171:3a7713b1edbc 3470 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 171:3a7713b1edbc 3471 #define PMC_IRQS { PMC_IRQn }
AnnaBridge 171:3a7713b1edbc 3472
AnnaBridge 171:3a7713b1edbc 3473 /*!
AnnaBridge 171:3a7713b1edbc 3474 * @}
AnnaBridge 171:3a7713b1edbc 3475 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3476
AnnaBridge 171:3a7713b1edbc 3477
AnnaBridge 171:3a7713b1edbc 3478 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3479 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3480 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3481
AnnaBridge 171:3a7713b1edbc 3482 /*!
AnnaBridge 171:3a7713b1edbc 3483 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3484 * @{
AnnaBridge 171:3a7713b1edbc 3485 */
AnnaBridge 171:3a7713b1edbc 3486
AnnaBridge 171:3a7713b1edbc 3487 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3488 typedef struct {
AnnaBridge 171:3a7713b1edbc 3489 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3490 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 3491 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 3492 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 3493 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 3494 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 3495
AnnaBridge 171:3a7713b1edbc 3496 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3497 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 3498 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3499
AnnaBridge 171:3a7713b1edbc 3500 /*!
AnnaBridge 171:3a7713b1edbc 3501 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 3502 * @{
AnnaBridge 171:3a7713b1edbc 3503 */
AnnaBridge 171:3a7713b1edbc 3504
AnnaBridge 171:3a7713b1edbc 3505 /*! @name PCR - Pin Control Register n */
AnnaBridge 171:3a7713b1edbc 3506 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3507 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3508 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 3509 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3510 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3511 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 171:3a7713b1edbc 3512 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3513 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3514 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 171:3a7713b1edbc 3515 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3516 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3517 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 171:3a7713b1edbc 3518 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3519 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3520 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 171:3a7713b1edbc 3521 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 3522 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3523 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 3524 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 3525 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3526 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 3527 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3528 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3529 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 3530
AnnaBridge 171:3a7713b1edbc 3531 /* The count of PORT_PCR */
AnnaBridge 171:3a7713b1edbc 3532 #define PORT_PCR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 3533
AnnaBridge 171:3a7713b1edbc 3534 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 171:3a7713b1edbc 3535 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3536 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3537 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 3538 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 3539 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3540 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 3541
AnnaBridge 171:3a7713b1edbc 3542 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 171:3a7713b1edbc 3543 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3544 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3545 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 3546 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 3547 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3548 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 3549
AnnaBridge 171:3a7713b1edbc 3550 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 171:3a7713b1edbc 3551 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3552 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3553 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 3554
AnnaBridge 171:3a7713b1edbc 3555
AnnaBridge 171:3a7713b1edbc 3556 /*!
AnnaBridge 171:3a7713b1edbc 3557 * @}
AnnaBridge 171:3a7713b1edbc 3558 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3559
AnnaBridge 171:3a7713b1edbc 3560
AnnaBridge 171:3a7713b1edbc 3561 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3562 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 3563 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 3564 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 3565 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 3566 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 3567 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 3568 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 3569 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 3570 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 3571 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 3572 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 3573 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 3574 /** Peripheral PORTD base address */
AnnaBridge 171:3a7713b1edbc 3575 #define PORTD_BASE (0x4004C000u)
AnnaBridge 171:3a7713b1edbc 3576 /** Peripheral PORTD base pointer */
AnnaBridge 171:3a7713b1edbc 3577 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 171:3a7713b1edbc 3578 /** Peripheral PORTE base address */
AnnaBridge 171:3a7713b1edbc 3579 #define PORTE_BASE (0x4004D000u)
AnnaBridge 171:3a7713b1edbc 3580 /** Peripheral PORTE base pointer */
AnnaBridge 171:3a7713b1edbc 3581 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 171:3a7713b1edbc 3582 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3583 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
AnnaBridge 171:3a7713b1edbc 3584 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3585 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 171:3a7713b1edbc 3586 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 171:3a7713b1edbc 3587 #define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn, PORTB_PORTC_PORTD_PORTE_IRQn }
AnnaBridge 171:3a7713b1edbc 3588
AnnaBridge 171:3a7713b1edbc 3589 /*!
AnnaBridge 171:3a7713b1edbc 3590 * @}
AnnaBridge 171:3a7713b1edbc 3591 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3592
AnnaBridge 171:3a7713b1edbc 3593
AnnaBridge 171:3a7713b1edbc 3594 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3595 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3596 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3597
AnnaBridge 171:3a7713b1edbc 3598 /*!
AnnaBridge 171:3a7713b1edbc 3599 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3600 * @{
AnnaBridge 171:3a7713b1edbc 3601 */
AnnaBridge 171:3a7713b1edbc 3602
AnnaBridge 171:3a7713b1edbc 3603 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3604 typedef struct {
AnnaBridge 171:3a7713b1edbc 3605 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3606 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3607 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 3608 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3609 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3610 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3611 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3612 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3613 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3614 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 3615
AnnaBridge 171:3a7713b1edbc 3616 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3617 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 3618 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3619
AnnaBridge 171:3a7713b1edbc 3620 /*!
AnnaBridge 171:3a7713b1edbc 3621 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 3622 * @{
AnnaBridge 171:3a7713b1edbc 3623 */
AnnaBridge 171:3a7713b1edbc 3624
AnnaBridge 171:3a7713b1edbc 3625 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 3626 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3627 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3628 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 3629 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3630 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3631 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 171:3a7713b1edbc 3632 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3633 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3634 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 171:3a7713b1edbc 3635 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3636 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3637 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 3638 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3639 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3640 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 171:3a7713b1edbc 3641
AnnaBridge 171:3a7713b1edbc 3642 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 3643 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3644 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3645 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 3646 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3647 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3648 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 171:3a7713b1edbc 3649 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3650 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3651 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 3652 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3653 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3654 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 3655
AnnaBridge 171:3a7713b1edbc 3656 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 171:3a7713b1edbc 3657 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3658 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3659 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 3660 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3661 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3662 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 171:3a7713b1edbc 3663
AnnaBridge 171:3a7713b1edbc 3664 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 171:3a7713b1edbc 3665 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 3666 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3667 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3668
AnnaBridge 171:3a7713b1edbc 3669 /*! @name FM - Force Mode Register */
AnnaBridge 171:3a7713b1edbc 3670 #define RCM_FM_FORCEROM_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 3671 #define RCM_FM_FORCEROM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3672 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK)
AnnaBridge 171:3a7713b1edbc 3673
AnnaBridge 171:3a7713b1edbc 3674 /*! @name MR - Mode Register */
AnnaBridge 171:3a7713b1edbc 3675 #define RCM_MR_BOOTROM_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 3676 #define RCM_MR_BOOTROM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3677 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK)
AnnaBridge 171:3a7713b1edbc 3678
AnnaBridge 171:3a7713b1edbc 3679 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 3680 #define RCM_SSRS0_SWAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3681 #define RCM_SSRS0_SWAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3682 #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 3683 #define RCM_SSRS0_SLVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3684 #define RCM_SSRS0_SLVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3685 #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
AnnaBridge 171:3a7713b1edbc 3686 #define RCM_SSRS0_SWDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3687 #define RCM_SSRS0_SWDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3688 #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 3689 #define RCM_SSRS0_SPIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3690 #define RCM_SSRS0_SPIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3691 #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
AnnaBridge 171:3a7713b1edbc 3692 #define RCM_SSRS0_SPOR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3693 #define RCM_SSRS0_SPOR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3694 #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
AnnaBridge 171:3a7713b1edbc 3695
AnnaBridge 171:3a7713b1edbc 3696 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 3697 #define RCM_SSRS1_SLOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3698 #define RCM_SSRS1_SLOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3699 #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 3700 #define RCM_SSRS1_SSW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3701 #define RCM_SSRS1_SSW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3702 #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
AnnaBridge 171:3a7713b1edbc 3703 #define RCM_SSRS1_SMDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3704 #define RCM_SSRS1_SMDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3705 #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 3706 #define RCM_SSRS1_SSACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3707 #define RCM_SSRS1_SSACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3708 #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 3709
AnnaBridge 171:3a7713b1edbc 3710
AnnaBridge 171:3a7713b1edbc 3711 /*!
AnnaBridge 171:3a7713b1edbc 3712 * @}
AnnaBridge 171:3a7713b1edbc 3713 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3714
AnnaBridge 171:3a7713b1edbc 3715
AnnaBridge 171:3a7713b1edbc 3716 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3717 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 3718 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 3719 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 3720 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 3721 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3722 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 171:3a7713b1edbc 3723 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3724 #define RCM_BASE_PTRS { RCM }
AnnaBridge 171:3a7713b1edbc 3725
AnnaBridge 171:3a7713b1edbc 3726 /*!
AnnaBridge 171:3a7713b1edbc 3727 * @}
AnnaBridge 171:3a7713b1edbc 3728 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3729
AnnaBridge 171:3a7713b1edbc 3730
AnnaBridge 171:3a7713b1edbc 3731 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3732 -- RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3733 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3734
AnnaBridge 171:3a7713b1edbc 3735 /*!
AnnaBridge 171:3a7713b1edbc 3736 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3737 * @{
AnnaBridge 171:3a7713b1edbc 3738 */
AnnaBridge 171:3a7713b1edbc 3739
AnnaBridge 171:3a7713b1edbc 3740 /** RFSYS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3741 typedef struct {
AnnaBridge 171:3a7713b1edbc 3742 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3743 } RFSYS_Type;
AnnaBridge 171:3a7713b1edbc 3744
AnnaBridge 171:3a7713b1edbc 3745 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3746 -- RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 3747 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3748
AnnaBridge 171:3a7713b1edbc 3749 /*!
AnnaBridge 171:3a7713b1edbc 3750 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 3751 * @{
AnnaBridge 171:3a7713b1edbc 3752 */
AnnaBridge 171:3a7713b1edbc 3753
AnnaBridge 171:3a7713b1edbc 3754 /*! @name REG - Register file register */
AnnaBridge 171:3a7713b1edbc 3755 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3756 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3757 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 3758 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 3759 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3760 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 3761 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 3762 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3763 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 3764 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 3765 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3766 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 3767
AnnaBridge 171:3a7713b1edbc 3768 /* The count of RFSYS_REG */
AnnaBridge 171:3a7713b1edbc 3769 #define RFSYS_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 3770
AnnaBridge 171:3a7713b1edbc 3771
AnnaBridge 171:3a7713b1edbc 3772 /*!
AnnaBridge 171:3a7713b1edbc 3773 * @}
AnnaBridge 171:3a7713b1edbc 3774 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3775
AnnaBridge 171:3a7713b1edbc 3776
AnnaBridge 171:3a7713b1edbc 3777 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3778 /** Peripheral RFSYS base address */
AnnaBridge 171:3a7713b1edbc 3779 #define RFSYS_BASE (0x40041000u)
AnnaBridge 171:3a7713b1edbc 3780 /** Peripheral RFSYS base pointer */
AnnaBridge 171:3a7713b1edbc 3781 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 171:3a7713b1edbc 3782 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3783 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 171:3a7713b1edbc 3784 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3785 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 171:3a7713b1edbc 3786
AnnaBridge 171:3a7713b1edbc 3787 /*!
AnnaBridge 171:3a7713b1edbc 3788 * @}
AnnaBridge 171:3a7713b1edbc 3789 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3790
AnnaBridge 171:3a7713b1edbc 3791
AnnaBridge 171:3a7713b1edbc 3792 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3793 -- ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3794 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3795
AnnaBridge 171:3a7713b1edbc 3796 /*!
AnnaBridge 171:3a7713b1edbc 3797 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3798 * @{
AnnaBridge 171:3a7713b1edbc 3799 */
AnnaBridge 171:3a7713b1edbc 3800
AnnaBridge 171:3a7713b1edbc 3801 /** ROM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3802 typedef struct {
AnnaBridge 171:3a7713b1edbc 3803 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3804 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3805 uint8_t RESERVED_0[4028];
AnnaBridge 171:3a7713b1edbc 3806 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 3807 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
AnnaBridge 171:3a7713b1edbc 3808 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
AnnaBridge 171:3a7713b1edbc 3809 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
AnnaBridge 171:3a7713b1edbc 3810 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
AnnaBridge 171:3a7713b1edbc 3811 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
AnnaBridge 171:3a7713b1edbc 3812 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
AnnaBridge 171:3a7713b1edbc 3813 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
AnnaBridge 171:3a7713b1edbc 3814 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
AnnaBridge 171:3a7713b1edbc 3815 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 3816 } ROM_Type;
AnnaBridge 171:3a7713b1edbc 3817
AnnaBridge 171:3a7713b1edbc 3818 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3819 -- ROM Register Masks
AnnaBridge 171:3a7713b1edbc 3820 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3821
AnnaBridge 171:3a7713b1edbc 3822 /*!
AnnaBridge 171:3a7713b1edbc 3823 * @addtogroup ROM_Register_Masks ROM Register Masks
AnnaBridge 171:3a7713b1edbc 3824 * @{
AnnaBridge 171:3a7713b1edbc 3825 */
AnnaBridge 171:3a7713b1edbc 3826
AnnaBridge 171:3a7713b1edbc 3827 /*! @name ENTRY - Entry */
AnnaBridge 171:3a7713b1edbc 3828 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3829 #define ROM_ENTRY_ENTRY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3830 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
AnnaBridge 171:3a7713b1edbc 3831
AnnaBridge 171:3a7713b1edbc 3832 /* The count of ROM_ENTRY */
AnnaBridge 171:3a7713b1edbc 3833 #define ROM_ENTRY_COUNT (3U)
AnnaBridge 171:3a7713b1edbc 3834
AnnaBridge 171:3a7713b1edbc 3835 /*! @name TABLEMARK - End of Table Marker Register */
AnnaBridge 171:3a7713b1edbc 3836 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3837 #define ROM_TABLEMARK_MARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3838 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 3839
AnnaBridge 171:3a7713b1edbc 3840 /*! @name SYSACCESS - System Access Register */
AnnaBridge 171:3a7713b1edbc 3841 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3842 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3843 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 3844
AnnaBridge 171:3a7713b1edbc 3845 /*! @name PERIPHID4 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3846 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3847 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3848 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3849
AnnaBridge 171:3a7713b1edbc 3850 /*! @name PERIPHID5 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3851 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3852 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3853 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3854
AnnaBridge 171:3a7713b1edbc 3855 /*! @name PERIPHID6 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3856 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3857 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3858 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3859
AnnaBridge 171:3a7713b1edbc 3860 /*! @name PERIPHID7 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3861 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3862 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3863 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3864
AnnaBridge 171:3a7713b1edbc 3865 /*! @name PERIPHID0 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3866 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3867 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3868 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3869
AnnaBridge 171:3a7713b1edbc 3870 /*! @name PERIPHID1 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3871 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3872 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3873 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3874
AnnaBridge 171:3a7713b1edbc 3875 /*! @name PERIPHID2 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3876 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3877 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3878 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3879
AnnaBridge 171:3a7713b1edbc 3880 /*! @name PERIPHID3 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 3881 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3882 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3883 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 3884
AnnaBridge 171:3a7713b1edbc 3885 /*! @name COMPID - Component ID Register */
AnnaBridge 171:3a7713b1edbc 3886 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3887 #define ROM_COMPID_COMPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3888 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 3889
AnnaBridge 171:3a7713b1edbc 3890 /* The count of ROM_COMPID */
AnnaBridge 171:3a7713b1edbc 3891 #define ROM_COMPID_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 3892
AnnaBridge 171:3a7713b1edbc 3893
AnnaBridge 171:3a7713b1edbc 3894 /*!
AnnaBridge 171:3a7713b1edbc 3895 * @}
AnnaBridge 171:3a7713b1edbc 3896 */ /* end of group ROM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3897
AnnaBridge 171:3a7713b1edbc 3898
AnnaBridge 171:3a7713b1edbc 3899 /* ROM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3900 /** Peripheral ROM base address */
AnnaBridge 171:3a7713b1edbc 3901 #define ROM_BASE (0xF0002000u)
AnnaBridge 171:3a7713b1edbc 3902 /** Peripheral ROM base pointer */
AnnaBridge 171:3a7713b1edbc 3903 #define ROM ((ROM_Type *)ROM_BASE)
AnnaBridge 171:3a7713b1edbc 3904 /** Array initializer of ROM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3905 #define ROM_BASE_ADDRS { ROM_BASE }
AnnaBridge 171:3a7713b1edbc 3906 /** Array initializer of ROM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3907 #define ROM_BASE_PTRS { ROM }
AnnaBridge 171:3a7713b1edbc 3908
AnnaBridge 171:3a7713b1edbc 3909 /*!
AnnaBridge 171:3a7713b1edbc 3910 * @}
AnnaBridge 171:3a7713b1edbc 3911 */ /* end of group ROM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3912
AnnaBridge 171:3a7713b1edbc 3913
AnnaBridge 171:3a7713b1edbc 3914 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3915 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3916 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3917
AnnaBridge 171:3a7713b1edbc 3918 /*!
AnnaBridge 171:3a7713b1edbc 3919 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3920 * @{
AnnaBridge 171:3a7713b1edbc 3921 */
AnnaBridge 171:3a7713b1edbc 3922
AnnaBridge 171:3a7713b1edbc 3923 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3924 typedef struct {
AnnaBridge 171:3a7713b1edbc 3925 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3926 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3927 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3928 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3929 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 3930 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3931 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 3932 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 3933 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 3934
AnnaBridge 171:3a7713b1edbc 3935 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3936 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 3937 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3938
AnnaBridge 171:3a7713b1edbc 3939 /*!
AnnaBridge 171:3a7713b1edbc 3940 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 3941 * @{
AnnaBridge 171:3a7713b1edbc 3942 */
AnnaBridge 171:3a7713b1edbc 3943
AnnaBridge 171:3a7713b1edbc 3944 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 3945 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3946 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3947 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 3948
AnnaBridge 171:3a7713b1edbc 3949 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 171:3a7713b1edbc 3950 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3951 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3952 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 3953
AnnaBridge 171:3a7713b1edbc 3954 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 171:3a7713b1edbc 3955 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3956 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3957 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 3958
AnnaBridge 171:3a7713b1edbc 3959 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 171:3a7713b1edbc 3960 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3961 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3962 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 3963 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 3964 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3965 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 3966 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 3967 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3968 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 3969 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 3970 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3971 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 3972
AnnaBridge 171:3a7713b1edbc 3973 /*! @name CR - RTC Control Register */
AnnaBridge 171:3a7713b1edbc 3974 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3975 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3976 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 171:3a7713b1edbc 3977 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3978 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3979 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 171:3a7713b1edbc 3980 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3981 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3982 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 171:3a7713b1edbc 3983 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3984 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3985 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 171:3a7713b1edbc 3986 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3987 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3988 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 171:3a7713b1edbc 3989 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3990 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3991 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 171:3a7713b1edbc 3992 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3993 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3994 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 171:3a7713b1edbc 3995 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3996 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3997 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 3998 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3999 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4000 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 4001 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4002 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4003 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 4004 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4005 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4006 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 4007
AnnaBridge 171:3a7713b1edbc 4008 /*! @name SR - RTC Status Register */
AnnaBridge 171:3a7713b1edbc 4009 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4010 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4011 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 4012 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4013 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4014 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 4015 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4016 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4017 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 171:3a7713b1edbc 4018 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4019 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4020 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 4021
AnnaBridge 171:3a7713b1edbc 4022 /*! @name LR - RTC Lock Register */
AnnaBridge 171:3a7713b1edbc 4023 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4024 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4025 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 171:3a7713b1edbc 4026 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4027 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4028 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 171:3a7713b1edbc 4029 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4030 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4031 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 171:3a7713b1edbc 4032 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4033 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4034 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 171:3a7713b1edbc 4035
AnnaBridge 171:3a7713b1edbc 4036 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 4037 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4038 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4039 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 171:3a7713b1edbc 4040 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4041 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4042 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 4043 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4044 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4045 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 171:3a7713b1edbc 4046 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4047 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4048 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 171:3a7713b1edbc 4049 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4050 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4051 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 171:3a7713b1edbc 4052
AnnaBridge 171:3a7713b1edbc 4053
AnnaBridge 171:3a7713b1edbc 4054 /*!
AnnaBridge 171:3a7713b1edbc 4055 * @}
AnnaBridge 171:3a7713b1edbc 4056 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4057
AnnaBridge 171:3a7713b1edbc 4058
AnnaBridge 171:3a7713b1edbc 4059 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4060 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 4061 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 4062 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 4063 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 4064 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4065 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 171:3a7713b1edbc 4066 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4067 #define RTC_BASE_PTRS { RTC }
AnnaBridge 171:3a7713b1edbc 4068 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 171:3a7713b1edbc 4069 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 171:3a7713b1edbc 4070 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 171:3a7713b1edbc 4071
AnnaBridge 171:3a7713b1edbc 4072 /*!
AnnaBridge 171:3a7713b1edbc 4073 * @}
AnnaBridge 171:3a7713b1edbc 4074 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4075
AnnaBridge 171:3a7713b1edbc 4076
AnnaBridge 171:3a7713b1edbc 4077 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4078 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4079 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4080
AnnaBridge 171:3a7713b1edbc 4081 /*!
AnnaBridge 171:3a7713b1edbc 4082 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4083 * @{
AnnaBridge 171:3a7713b1edbc 4084 */
AnnaBridge 171:3a7713b1edbc 4085
AnnaBridge 171:3a7713b1edbc 4086 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4087 typedef struct {
AnnaBridge 171:3a7713b1edbc 4088 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4089 uint8_t RESERVED_0[4096];
AnnaBridge 171:3a7713b1edbc 4090 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 4091 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 4092 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 4093 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 4094 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 4095 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 4096 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 4097 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 4098 uint8_t RESERVED_4[12];
AnnaBridge 171:3a7713b1edbc 4099 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 4100 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 4101 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 4102 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 4103 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 4104 uint8_t RESERVED_5[4];
AnnaBridge 171:3a7713b1edbc 4105 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 4106 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 4107 uint8_t RESERVED_6[4];
AnnaBridge 171:3a7713b1edbc 4108 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 4109 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 4110 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 4111 uint8_t RESERVED_7[156];
AnnaBridge 171:3a7713b1edbc 4112 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
AnnaBridge 171:3a7713b1edbc 4113 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
AnnaBridge 171:3a7713b1edbc 4114 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 4115
AnnaBridge 171:3a7713b1edbc 4116 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4117 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 4118 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4119
AnnaBridge 171:3a7713b1edbc 4120 /*!
AnnaBridge 171:3a7713b1edbc 4121 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 4122 * @{
AnnaBridge 171:3a7713b1edbc 4123 */
AnnaBridge 171:3a7713b1edbc 4124
AnnaBridge 171:3a7713b1edbc 4125 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 171:3a7713b1edbc 4126 #define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 4127 #define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4128 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
AnnaBridge 171:3a7713b1edbc 4129 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 4130 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4131 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4132
AnnaBridge 171:3a7713b1edbc 4133 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 171:3a7713b1edbc 4134 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4135 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4136 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4137 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 4138 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4139 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4140 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4141 #define SIM_SOPT2_USBSRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4142 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4143 #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 4144 #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4145 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4146 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 4147 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4148 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4149 #define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 4150 #define SIM_SOPT2_LPUART0SRC_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4151 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 4152 #define SIM_SOPT2_LPUART1SRC_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 4153 #define SIM_SOPT2_LPUART1SRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4154 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART1SRC_SHIFT)) & SIM_SOPT2_LPUART1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 4155
AnnaBridge 171:3a7713b1edbc 4156 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 171:3a7713b1edbc 4157 #define SIM_SOPT4_TPM1CH0SRC_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 4158 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4159 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 4160 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4161 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4162 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 4163 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4164 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4165 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4166 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4167 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4168 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4169 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4170 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4171 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4172
AnnaBridge 171:3a7713b1edbc 4173 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 171:3a7713b1edbc 4174 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 4175 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4176 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4177 #define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4178 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4179 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4180 #define SIM_SOPT5_LPUART1TXSRC_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4181 #define SIM_SOPT5_LPUART1TXSRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4182 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4183 #define SIM_SOPT5_LPUART1RXSRC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4184 #define SIM_SOPT5_LPUART1RXSRC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4185 #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4186 #define SIM_SOPT5_LPUART0ODE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4187 #define SIM_SOPT5_LPUART0ODE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4188 #define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK)
AnnaBridge 171:3a7713b1edbc 4189 #define SIM_SOPT5_LPUART1ODE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4190 #define SIM_SOPT5_LPUART1ODE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4191 #define SIM_SOPT5_LPUART1ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1ODE_SHIFT)) & SIM_SOPT5_LPUART1ODE_MASK)
AnnaBridge 171:3a7713b1edbc 4192 #define SIM_SOPT5_UART2ODE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4193 #define SIM_SOPT5_UART2ODE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4194 #define SIM_SOPT5_UART2ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART2ODE_SHIFT)) & SIM_SOPT5_UART2ODE_MASK)
AnnaBridge 171:3a7713b1edbc 4195
AnnaBridge 171:3a7713b1edbc 4196 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 171:3a7713b1edbc 4197 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4198 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4199 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4200 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4201 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4202 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4203 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4204 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4205 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 4206
AnnaBridge 171:3a7713b1edbc 4207 /*! @name SDID - System Device Identification Register */
AnnaBridge 171:3a7713b1edbc 4208 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4209 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4210 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 4211 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 4212 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4213 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 4214 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 4215 #define SIM_SDID_SRAMSIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4216 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4217 #define SIM_SDID_SERIESID_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 4218 #define SIM_SDID_SERIESID_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4219 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
AnnaBridge 171:3a7713b1edbc 4220 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 4221 #define SIM_SDID_SUBFAMID_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4222 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
AnnaBridge 171:3a7713b1edbc 4223 #define SIM_SDID_FAMID_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 4224 #define SIM_SDID_FAMID_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4225 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 4226
AnnaBridge 171:3a7713b1edbc 4227 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 171:3a7713b1edbc 4228 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4229 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4230 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 171:3a7713b1edbc 4231 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4232 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4233 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 171:3a7713b1edbc 4234 #define SIM_SCGC4_UART2_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4235 #define SIM_SCGC4_UART2_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4236 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
AnnaBridge 171:3a7713b1edbc 4237 #define SIM_SCGC4_USBFS_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4238 #define SIM_SCGC4_USBFS_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4239 #define SIM_SCGC4_USBFS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBFS_SHIFT)) & SIM_SCGC4_USBFS_MASK)
AnnaBridge 171:3a7713b1edbc 4240 #define SIM_SCGC4_CMP0_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4241 #define SIM_SCGC4_CMP0_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4242 #define SIM_SCGC4_CMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK)
AnnaBridge 171:3a7713b1edbc 4243 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4244 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4245 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 171:3a7713b1edbc 4246 #define SIM_SCGC4_SPI0_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4247 #define SIM_SCGC4_SPI0_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4248 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK)
AnnaBridge 171:3a7713b1edbc 4249 #define SIM_SCGC4_SPI1_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4250 #define SIM_SCGC4_SPI1_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4251 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK)
AnnaBridge 171:3a7713b1edbc 4252
AnnaBridge 171:3a7713b1edbc 4253 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 171:3a7713b1edbc 4254 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4255 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4256 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 171:3a7713b1edbc 4257 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4258 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4259 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 171:3a7713b1edbc 4260 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4261 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4262 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 171:3a7713b1edbc 4263 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4264 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4265 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 171:3a7713b1edbc 4266 #define SIM_SCGC5_PORTD_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4267 #define SIM_SCGC5_PORTD_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4268 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
AnnaBridge 171:3a7713b1edbc 4269 #define SIM_SCGC5_PORTE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4270 #define SIM_SCGC5_PORTE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4271 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
AnnaBridge 171:3a7713b1edbc 4272 #define SIM_SCGC5_LPUART0_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4273 #define SIM_SCGC5_LPUART0_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4274 #define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
AnnaBridge 171:3a7713b1edbc 4275 #define SIM_SCGC5_LPUART1_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4276 #define SIM_SCGC5_LPUART1_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4277 #define SIM_SCGC5_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK)
AnnaBridge 171:3a7713b1edbc 4278 #define SIM_SCGC5_FLEXIO_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4279 #define SIM_SCGC5_FLEXIO_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4280 #define SIM_SCGC5_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO_SHIFT)) & SIM_SCGC5_FLEXIO_MASK)
AnnaBridge 171:3a7713b1edbc 4281
AnnaBridge 171:3a7713b1edbc 4282 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 171:3a7713b1edbc 4283 #define SIM_SCGC6_FTF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4284 #define SIM_SCGC6_FTF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4285 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
AnnaBridge 171:3a7713b1edbc 4286 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4287 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4288 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 171:3a7713b1edbc 4289 #define SIM_SCGC6_CRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4290 #define SIM_SCGC6_CRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4291 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 4292 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4293 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4294 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 171:3a7713b1edbc 4295 #define SIM_SCGC6_TPM0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4296 #define SIM_SCGC6_TPM0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4297 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
AnnaBridge 171:3a7713b1edbc 4298 #define SIM_SCGC6_TPM1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4299 #define SIM_SCGC6_TPM1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4300 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
AnnaBridge 171:3a7713b1edbc 4301 #define SIM_SCGC6_TPM2_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4302 #define SIM_SCGC6_TPM2_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4303 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
AnnaBridge 171:3a7713b1edbc 4304 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4305 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4306 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 171:3a7713b1edbc 4307 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4308 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4309 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 171:3a7713b1edbc 4310
AnnaBridge 171:3a7713b1edbc 4311 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 171:3a7713b1edbc 4312 #define SIM_SCGC7_DMA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4313 #define SIM_SCGC7_DMA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4314 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 4315
AnnaBridge 171:3a7713b1edbc 4316 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 171:3a7713b1edbc 4317 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 4318 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4319 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 4320 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 4321 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4322 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 4323
AnnaBridge 171:3a7713b1edbc 4324 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 4325 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4326 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4327 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 171:3a7713b1edbc 4328 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4329 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4330 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 171:3a7713b1edbc 4331 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 4332 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4333 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4334
AnnaBridge 171:3a7713b1edbc 4335 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 4336 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 4337 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4338 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 4339
AnnaBridge 171:3a7713b1edbc 4340 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 171:3a7713b1edbc 4341 #define SIM_UIDMH_UID_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4342 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4343 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 4344
AnnaBridge 171:3a7713b1edbc 4345 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 171:3a7713b1edbc 4346 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4347 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4348 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 4349
AnnaBridge 171:3a7713b1edbc 4350 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 171:3a7713b1edbc 4351 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4352 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4353 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 4354
AnnaBridge 171:3a7713b1edbc 4355 /*! @name COPC - COP Control Register */
AnnaBridge 171:3a7713b1edbc 4356 #define SIM_COPC_COPW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4357 #define SIM_COPC_COPW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4358 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
AnnaBridge 171:3a7713b1edbc 4359 #define SIM_COPC_COPCLKS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4360 #define SIM_COPC_COPCLKS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4361 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
AnnaBridge 171:3a7713b1edbc 4362 #define SIM_COPC_COPT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4363 #define SIM_COPC_COPT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4364 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
AnnaBridge 171:3a7713b1edbc 4365 #define SIM_COPC_COPSTPEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4366 #define SIM_COPC_COPSTPEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4367 #define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK)
AnnaBridge 171:3a7713b1edbc 4368 #define SIM_COPC_COPDBGEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4369 #define SIM_COPC_COPDBGEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4370 #define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 4371 #define SIM_COPC_COPCLKSEL_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4372 #define SIM_COPC_COPCLKSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4373 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4374
AnnaBridge 171:3a7713b1edbc 4375 /*! @name SRVCOP - Service COP */
AnnaBridge 171:3a7713b1edbc 4376 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4377 #define SIM_SRVCOP_SRVCOP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4378 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
AnnaBridge 171:3a7713b1edbc 4379
AnnaBridge 171:3a7713b1edbc 4380
AnnaBridge 171:3a7713b1edbc 4381 /*!
AnnaBridge 171:3a7713b1edbc 4382 * @}
AnnaBridge 171:3a7713b1edbc 4383 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4384
AnnaBridge 171:3a7713b1edbc 4385
AnnaBridge 171:3a7713b1edbc 4386 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4387 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 4388 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 4389 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 4390 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 4391 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4392 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 171:3a7713b1edbc 4393 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4394 #define SIM_BASE_PTRS { SIM }
AnnaBridge 171:3a7713b1edbc 4395
AnnaBridge 171:3a7713b1edbc 4396 /*!
AnnaBridge 171:3a7713b1edbc 4397 * @}
AnnaBridge 171:3a7713b1edbc 4398 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4399
AnnaBridge 171:3a7713b1edbc 4400
AnnaBridge 171:3a7713b1edbc 4401 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4402 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4403 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4404
AnnaBridge 171:3a7713b1edbc 4405 /*!
AnnaBridge 171:3a7713b1edbc 4406 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4407 * @{
AnnaBridge 171:3a7713b1edbc 4408 */
AnnaBridge 171:3a7713b1edbc 4409
AnnaBridge 171:3a7713b1edbc 4410 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4411 typedef struct {
AnnaBridge 171:3a7713b1edbc 4412 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4413 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4414 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4415 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4416 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 4417
AnnaBridge 171:3a7713b1edbc 4418 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4419 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 4420 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4421
AnnaBridge 171:3a7713b1edbc 4422 /*!
AnnaBridge 171:3a7713b1edbc 4423 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 4424 * @{
AnnaBridge 171:3a7713b1edbc 4425 */
AnnaBridge 171:3a7713b1edbc 4426
AnnaBridge 171:3a7713b1edbc 4427 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 171:3a7713b1edbc 4428 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4429 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4430 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 171:3a7713b1edbc 4431 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4432 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4433 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 171:3a7713b1edbc 4434 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4435 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4436 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 171:3a7713b1edbc 4437
AnnaBridge 171:3a7713b1edbc 4438 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 171:3a7713b1edbc 4439 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 4440 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4441 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 4442 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4443 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4444 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 171:3a7713b1edbc 4445 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 4446 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4447 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 4448
AnnaBridge 171:3a7713b1edbc 4449 /*! @name STOPCTRL - Stop Control Register */
AnnaBridge 171:3a7713b1edbc 4450 #define SMC_STOPCTRL_VLLSM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 4451 #define SMC_STOPCTRL_VLLSM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4452 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK)
AnnaBridge 171:3a7713b1edbc 4453 #define SMC_STOPCTRL_LPOPO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4454 #define SMC_STOPCTRL_LPOPO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4455 #define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK)
AnnaBridge 171:3a7713b1edbc 4456 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4457 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4458 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
AnnaBridge 171:3a7713b1edbc 4459 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4460 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4461 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
AnnaBridge 171:3a7713b1edbc 4462
AnnaBridge 171:3a7713b1edbc 4463 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 171:3a7713b1edbc 4464 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4465 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4466 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 4467
AnnaBridge 171:3a7713b1edbc 4468
AnnaBridge 171:3a7713b1edbc 4469 /*!
AnnaBridge 171:3a7713b1edbc 4470 * @}
AnnaBridge 171:3a7713b1edbc 4471 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4472
AnnaBridge 171:3a7713b1edbc 4473
AnnaBridge 171:3a7713b1edbc 4474 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4475 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 4476 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 4477 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 4478 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 4479 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4480 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 171:3a7713b1edbc 4481 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4482 #define SMC_BASE_PTRS { SMC }
AnnaBridge 171:3a7713b1edbc 4483
AnnaBridge 171:3a7713b1edbc 4484 /*!
AnnaBridge 171:3a7713b1edbc 4485 * @}
AnnaBridge 171:3a7713b1edbc 4486 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4487
AnnaBridge 171:3a7713b1edbc 4488
AnnaBridge 171:3a7713b1edbc 4489 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4490 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4491 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4492
AnnaBridge 171:3a7713b1edbc 4493 /*!
AnnaBridge 171:3a7713b1edbc 4494 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4495 * @{
AnnaBridge 171:3a7713b1edbc 4496 */
AnnaBridge 171:3a7713b1edbc 4497
AnnaBridge 171:3a7713b1edbc 4498 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4499 typedef struct {
AnnaBridge 171:3a7713b1edbc 4500 __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4501 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4502 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4503 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4504 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4505 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4506 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4507 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 4508 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 4509 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4510 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 4511 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 4512
AnnaBridge 171:3a7713b1edbc 4513 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4514 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 4515 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4516
AnnaBridge 171:3a7713b1edbc 4517 /*!
AnnaBridge 171:3a7713b1edbc 4518 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 4519 * @{
AnnaBridge 171:3a7713b1edbc 4520 */
AnnaBridge 171:3a7713b1edbc 4521
AnnaBridge 171:3a7713b1edbc 4522 /*! @name S - SPI Status Register */
AnnaBridge 171:3a7713b1edbc 4523 #define SPI_S_RFIFOEF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4524 #define SPI_S_RFIFOEF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4525 #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK)
AnnaBridge 171:3a7713b1edbc 4526 #define SPI_S_TXFULLF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4527 #define SPI_S_TXFULLF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4528 #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK)
AnnaBridge 171:3a7713b1edbc 4529 #define SPI_S_TNEAREF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4530 #define SPI_S_TNEAREF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4531 #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK)
AnnaBridge 171:3a7713b1edbc 4532 #define SPI_S_RNFULLF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4533 #define SPI_S_RNFULLF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4534 #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK)
AnnaBridge 171:3a7713b1edbc 4535 #define SPI_S_MODF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4536 #define SPI_S_MODF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4537 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK)
AnnaBridge 171:3a7713b1edbc 4538 #define SPI_S_SPTEF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4539 #define SPI_S_SPTEF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4540 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK)
AnnaBridge 171:3a7713b1edbc 4541 #define SPI_S_SPMF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4542 #define SPI_S_SPMF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4543 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK)
AnnaBridge 171:3a7713b1edbc 4544 #define SPI_S_SPRF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4545 #define SPI_S_SPRF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4546 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK)
AnnaBridge 171:3a7713b1edbc 4547
AnnaBridge 171:3a7713b1edbc 4548 /*! @name BR - SPI Baud Rate Register */
AnnaBridge 171:3a7713b1edbc 4549 #define SPI_BR_SPR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4550 #define SPI_BR_SPR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4551 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK)
AnnaBridge 171:3a7713b1edbc 4552 #define SPI_BR_SPPR_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 4553 #define SPI_BR_SPPR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4554 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK)
AnnaBridge 171:3a7713b1edbc 4555
AnnaBridge 171:3a7713b1edbc 4556 /*! @name C2 - SPI Control Register 2 */
AnnaBridge 171:3a7713b1edbc 4557 #define SPI_C2_SPC0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4558 #define SPI_C2_SPC0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4559 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK)
AnnaBridge 171:3a7713b1edbc 4560 #define SPI_C2_SPISWAI_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4561 #define SPI_C2_SPISWAI_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4562 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK)
AnnaBridge 171:3a7713b1edbc 4563 #define SPI_C2_RXDMAE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4564 #define SPI_C2_RXDMAE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4565 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 4566 #define SPI_C2_BIDIROE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4567 #define SPI_C2_BIDIROE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4568 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK)
AnnaBridge 171:3a7713b1edbc 4569 #define SPI_C2_MODFEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4570 #define SPI_C2_MODFEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4571 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK)
AnnaBridge 171:3a7713b1edbc 4572 #define SPI_C2_TXDMAE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4573 #define SPI_C2_TXDMAE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4574 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 4575 #define SPI_C2_SPIMODE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4576 #define SPI_C2_SPIMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4577 #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK)
AnnaBridge 171:3a7713b1edbc 4578 #define SPI_C2_SPMIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4579 #define SPI_C2_SPMIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4580 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK)
AnnaBridge 171:3a7713b1edbc 4581
AnnaBridge 171:3a7713b1edbc 4582 /*! @name C1 - SPI Control Register 1 */
AnnaBridge 171:3a7713b1edbc 4583 #define SPI_C1_LSBFE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4584 #define SPI_C1_LSBFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4585 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK)
AnnaBridge 171:3a7713b1edbc 4586 #define SPI_C1_SSOE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4587 #define SPI_C1_SSOE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4588 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK)
AnnaBridge 171:3a7713b1edbc 4589 #define SPI_C1_CPHA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4590 #define SPI_C1_CPHA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4591 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 4592 #define SPI_C1_CPOL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4593 #define SPI_C1_CPOL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4594 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 4595 #define SPI_C1_MSTR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4596 #define SPI_C1_MSTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4597 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK)
AnnaBridge 171:3a7713b1edbc 4598 #define SPI_C1_SPTIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4599 #define SPI_C1_SPTIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4600 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK)
AnnaBridge 171:3a7713b1edbc 4601 #define SPI_C1_SPE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4602 #define SPI_C1_SPE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4603 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK)
AnnaBridge 171:3a7713b1edbc 4604 #define SPI_C1_SPIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4605 #define SPI_C1_SPIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4606 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK)
AnnaBridge 171:3a7713b1edbc 4607
AnnaBridge 171:3a7713b1edbc 4608 /*! @name ML - SPI Match Register low */
AnnaBridge 171:3a7713b1edbc 4609 #define SPI_ML_Bits_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4610 #define SPI_ML_Bits_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4611 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4612
AnnaBridge 171:3a7713b1edbc 4613 /*! @name MH - SPI match register high */
AnnaBridge 171:3a7713b1edbc 4614 #define SPI_MH_Bits_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4615 #define SPI_MH_Bits_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4616 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4617
AnnaBridge 171:3a7713b1edbc 4618 /*! @name DL - SPI Data Register low */
AnnaBridge 171:3a7713b1edbc 4619 #define SPI_DL_Bits_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4620 #define SPI_DL_Bits_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4621 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4622
AnnaBridge 171:3a7713b1edbc 4623 /*! @name DH - SPI data register high */
AnnaBridge 171:3a7713b1edbc 4624 #define SPI_DH_Bits_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4625 #define SPI_DH_Bits_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4626 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK)
AnnaBridge 171:3a7713b1edbc 4627
AnnaBridge 171:3a7713b1edbc 4628 /*! @name CI - SPI clear interrupt register */
AnnaBridge 171:3a7713b1edbc 4629 #define SPI_CI_SPRFCI_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4630 #define SPI_CI_SPRFCI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4631 #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK)
AnnaBridge 171:3a7713b1edbc 4632 #define SPI_CI_SPTEFCI_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4633 #define SPI_CI_SPTEFCI_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4634 #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK)
AnnaBridge 171:3a7713b1edbc 4635 #define SPI_CI_RNFULLFCI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4636 #define SPI_CI_RNFULLFCI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4637 #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK)
AnnaBridge 171:3a7713b1edbc 4638 #define SPI_CI_TNEAREFCI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4639 #define SPI_CI_TNEAREFCI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4640 #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK)
AnnaBridge 171:3a7713b1edbc 4641 #define SPI_CI_RXFOF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4642 #define SPI_CI_RXFOF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4643 #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK)
AnnaBridge 171:3a7713b1edbc 4644 #define SPI_CI_TXFOF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4645 #define SPI_CI_TXFOF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4646 #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK)
AnnaBridge 171:3a7713b1edbc 4647 #define SPI_CI_RXFERR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4648 #define SPI_CI_RXFERR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4649 #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK)
AnnaBridge 171:3a7713b1edbc 4650 #define SPI_CI_TXFERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4651 #define SPI_CI_TXFERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4652 #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK)
AnnaBridge 171:3a7713b1edbc 4653
AnnaBridge 171:3a7713b1edbc 4654 /*! @name C3 - SPI control register 3 */
AnnaBridge 171:3a7713b1edbc 4655 #define SPI_C3_FIFOMODE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4656 #define SPI_C3_FIFOMODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4657 #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK)
AnnaBridge 171:3a7713b1edbc 4658 #define SPI_C3_RNFULLIEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4659 #define SPI_C3_RNFULLIEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4660 #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK)
AnnaBridge 171:3a7713b1edbc 4661 #define SPI_C3_TNEARIEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4662 #define SPI_C3_TNEARIEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4663 #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK)
AnnaBridge 171:3a7713b1edbc 4664 #define SPI_C3_INTCLR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4665 #define SPI_C3_INTCLR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4666 #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK)
AnnaBridge 171:3a7713b1edbc 4667 #define SPI_C3_RNFULLF_MARK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4668 #define SPI_C3_RNFULLF_MARK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4669 #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 4670 #define SPI_C3_TNEAREF_MARK_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4671 #define SPI_C3_TNEAREF_MARK_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4672 #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 4673
AnnaBridge 171:3a7713b1edbc 4674
AnnaBridge 171:3a7713b1edbc 4675 /*!
AnnaBridge 171:3a7713b1edbc 4676 * @}
AnnaBridge 171:3a7713b1edbc 4677 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4678
AnnaBridge 171:3a7713b1edbc 4679
AnnaBridge 171:3a7713b1edbc 4680 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4681 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 4682 #define SPI0_BASE (0x40076000u)
AnnaBridge 171:3a7713b1edbc 4683 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 4684 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 4685 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 4686 #define SPI1_BASE (0x40077000u)
AnnaBridge 171:3a7713b1edbc 4687 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 4688 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 4689 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4690 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
AnnaBridge 171:3a7713b1edbc 4691 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4692 #define SPI_BASE_PTRS { SPI0, SPI1 }
AnnaBridge 171:3a7713b1edbc 4693 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 171:3a7713b1edbc 4694 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
AnnaBridge 171:3a7713b1edbc 4695
AnnaBridge 171:3a7713b1edbc 4696 /*!
AnnaBridge 171:3a7713b1edbc 4697 * @}
AnnaBridge 171:3a7713b1edbc 4698 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4699
AnnaBridge 171:3a7713b1edbc 4700
AnnaBridge 171:3a7713b1edbc 4701 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4702 -- TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4703 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4704
AnnaBridge 171:3a7713b1edbc 4705 /*!
AnnaBridge 171:3a7713b1edbc 4706 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4707 * @{
AnnaBridge 171:3a7713b1edbc 4708 */
AnnaBridge 171:3a7713b1edbc 4709
AnnaBridge 171:3a7713b1edbc 4710 /** TPM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4711 typedef struct {
AnnaBridge 171:3a7713b1edbc 4712 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4713 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4714 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4715 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4716 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4717 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4718 } CONTROLS[6];
AnnaBridge 171:3a7713b1edbc 4719 uint8_t RESERVED_0[20];
AnnaBridge 171:3a7713b1edbc 4720 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 4721 uint8_t RESERVED_1[28];
AnnaBridge 171:3a7713b1edbc 4722 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 4723 uint8_t RESERVED_2[16];
AnnaBridge 171:3a7713b1edbc 4724 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 4725 } TPM_Type;
AnnaBridge 171:3a7713b1edbc 4726
AnnaBridge 171:3a7713b1edbc 4727 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4728 -- TPM Register Masks
AnnaBridge 171:3a7713b1edbc 4729 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4730
AnnaBridge 171:3a7713b1edbc 4731 /*!
AnnaBridge 171:3a7713b1edbc 4732 * @addtogroup TPM_Register_Masks TPM Register Masks
AnnaBridge 171:3a7713b1edbc 4733 * @{
AnnaBridge 171:3a7713b1edbc 4734 */
AnnaBridge 171:3a7713b1edbc 4735
AnnaBridge 171:3a7713b1edbc 4736 /*! @name SC - Status and Control */
AnnaBridge 171:3a7713b1edbc 4737 #define TPM_SC_PS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 4738 #define TPM_SC_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4739 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 4740 #define TPM_SC_CMOD_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 4741 #define TPM_SC_CMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4742 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
AnnaBridge 171:3a7713b1edbc 4743 #define TPM_SC_CPWMS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4744 #define TPM_SC_CPWMS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4745 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
AnnaBridge 171:3a7713b1edbc 4746 #define TPM_SC_TOIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4747 #define TPM_SC_TOIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4748 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 4749 #define TPM_SC_TOF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4750 #define TPM_SC_TOF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4751 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 4752 #define TPM_SC_DMA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4753 #define TPM_SC_DMA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4754 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 4755
AnnaBridge 171:3a7713b1edbc 4756 /*! @name CNT - Counter */
AnnaBridge 171:3a7713b1edbc 4757 #define TPM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4758 #define TPM_CNT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4759 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 4760
AnnaBridge 171:3a7713b1edbc 4761 /*! @name MOD - Modulo */
AnnaBridge 171:3a7713b1edbc 4762 #define TPM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4763 #define TPM_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4764 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 4765
AnnaBridge 171:3a7713b1edbc 4766 /*! @name CnSC - Channel (n) Status and Control */
AnnaBridge 171:3a7713b1edbc 4767 #define TPM_CnSC_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4768 #define TPM_CnSC_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4769 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 4770 #define TPM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4771 #define TPM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4772 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
AnnaBridge 171:3a7713b1edbc 4773 #define TPM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4774 #define TPM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4775 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
AnnaBridge 171:3a7713b1edbc 4776 #define TPM_CnSC_MSA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4777 #define TPM_CnSC_MSA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4778 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
AnnaBridge 171:3a7713b1edbc 4779 #define TPM_CnSC_MSB_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4780 #define TPM_CnSC_MSB_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4781 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 4782 #define TPM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4783 #define TPM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4784 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
AnnaBridge 171:3a7713b1edbc 4785 #define TPM_CnSC_CHF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4786 #define TPM_CnSC_CHF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4787 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
AnnaBridge 171:3a7713b1edbc 4788
AnnaBridge 171:3a7713b1edbc 4789 /* The count of TPM_CnSC */
AnnaBridge 171:3a7713b1edbc 4790 #define TPM_CnSC_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 4791
AnnaBridge 171:3a7713b1edbc 4792 /*! @name CnV - Channel (n) Value */
AnnaBridge 171:3a7713b1edbc 4793 #define TPM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4794 #define TPM_CnV_VAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4795 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 4796
AnnaBridge 171:3a7713b1edbc 4797 /* The count of TPM_CnV */
AnnaBridge 171:3a7713b1edbc 4798 #define TPM_CnV_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 4799
AnnaBridge 171:3a7713b1edbc 4800 /*! @name STATUS - Capture and Compare Status */
AnnaBridge 171:3a7713b1edbc 4801 #define TPM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4802 #define TPM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4803 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
AnnaBridge 171:3a7713b1edbc 4804 #define TPM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4805 #define TPM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4806 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
AnnaBridge 171:3a7713b1edbc 4807 #define TPM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4808 #define TPM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4809 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
AnnaBridge 171:3a7713b1edbc 4810 #define TPM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4811 #define TPM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4812 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
AnnaBridge 171:3a7713b1edbc 4813 #define TPM_STATUS_CH4F_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4814 #define TPM_STATUS_CH4F_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4815 #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK)
AnnaBridge 171:3a7713b1edbc 4816 #define TPM_STATUS_CH5F_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4817 #define TPM_STATUS_CH5F_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4818 #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK)
AnnaBridge 171:3a7713b1edbc 4819 #define TPM_STATUS_TOF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4820 #define TPM_STATUS_TOF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4821 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 4822
AnnaBridge 171:3a7713b1edbc 4823 /*! @name POL - Channel Polarity */
AnnaBridge 171:3a7713b1edbc 4824 #define TPM_POL_POL0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4825 #define TPM_POL_POL0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4826 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
AnnaBridge 171:3a7713b1edbc 4827 #define TPM_POL_POL1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4828 #define TPM_POL_POL1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4829 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
AnnaBridge 171:3a7713b1edbc 4830 #define TPM_POL_POL2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4831 #define TPM_POL_POL2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4832 #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
AnnaBridge 171:3a7713b1edbc 4833 #define TPM_POL_POL3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4834 #define TPM_POL_POL3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4835 #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
AnnaBridge 171:3a7713b1edbc 4836 #define TPM_POL_POL4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4837 #define TPM_POL_POL4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4838 #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK)
AnnaBridge 171:3a7713b1edbc 4839 #define TPM_POL_POL5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4840 #define TPM_POL_POL5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4841 #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK)
AnnaBridge 171:3a7713b1edbc 4842
AnnaBridge 171:3a7713b1edbc 4843 /*! @name CONF - Configuration */
AnnaBridge 171:3a7713b1edbc 4844 #define TPM_CONF_DOZEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4845 #define TPM_CONF_DOZEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4846 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
AnnaBridge 171:3a7713b1edbc 4847 #define TPM_CONF_DBGMODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4848 #define TPM_CONF_DBGMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4849 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 4850 #define TPM_CONF_GTBSYNC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4851 #define TPM_CONF_GTBSYNC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4852 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 4853 #define TPM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4854 #define TPM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4855 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
AnnaBridge 171:3a7713b1edbc 4856 #define TPM_CONF_CSOT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4857 #define TPM_CONF_CSOT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4858 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
AnnaBridge 171:3a7713b1edbc 4859 #define TPM_CONF_CSOO_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4860 #define TPM_CONF_CSOO_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4861 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
AnnaBridge 171:3a7713b1edbc 4862 #define TPM_CONF_CROT_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4863 #define TPM_CONF_CROT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4864 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
AnnaBridge 171:3a7713b1edbc 4865 #define TPM_CONF_CPOT_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4866 #define TPM_CONF_CPOT_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4867 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
AnnaBridge 171:3a7713b1edbc 4868 #define TPM_CONF_TRGPOL_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4869 #define TPM_CONF_TRGPOL_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4870 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
AnnaBridge 171:3a7713b1edbc 4871 #define TPM_CONF_TRGSRC_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4872 #define TPM_CONF_TRGSRC_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4873 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4874 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 4875 #define TPM_CONF_TRGSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4876 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4877
AnnaBridge 171:3a7713b1edbc 4878
AnnaBridge 171:3a7713b1edbc 4879 /*!
AnnaBridge 171:3a7713b1edbc 4880 * @}
AnnaBridge 171:3a7713b1edbc 4881 */ /* end of group TPM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4882
AnnaBridge 171:3a7713b1edbc 4883
AnnaBridge 171:3a7713b1edbc 4884 /* TPM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4885 /** Peripheral TPM0 base address */
AnnaBridge 171:3a7713b1edbc 4886 #define TPM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 4887 /** Peripheral TPM0 base pointer */
AnnaBridge 171:3a7713b1edbc 4888 #define TPM0 ((TPM_Type *)TPM0_BASE)
AnnaBridge 171:3a7713b1edbc 4889 /** Peripheral TPM1 base address */
AnnaBridge 171:3a7713b1edbc 4890 #define TPM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 4891 /** Peripheral TPM1 base pointer */
AnnaBridge 171:3a7713b1edbc 4892 #define TPM1 ((TPM_Type *)TPM1_BASE)
AnnaBridge 171:3a7713b1edbc 4893 /** Peripheral TPM2 base address */
AnnaBridge 171:3a7713b1edbc 4894 #define TPM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 4895 /** Peripheral TPM2 base pointer */
AnnaBridge 171:3a7713b1edbc 4896 #define TPM2 ((TPM_Type *)TPM2_BASE)
AnnaBridge 171:3a7713b1edbc 4897 /** Array initializer of TPM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4898 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
AnnaBridge 171:3a7713b1edbc 4899 /** Array initializer of TPM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4900 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
AnnaBridge 171:3a7713b1edbc 4901 /** Interrupt vectors for the TPM peripheral type */
AnnaBridge 171:3a7713b1edbc 4902 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
AnnaBridge 171:3a7713b1edbc 4903
AnnaBridge 171:3a7713b1edbc 4904 /*!
AnnaBridge 171:3a7713b1edbc 4905 * @}
AnnaBridge 171:3a7713b1edbc 4906 */ /* end of group TPM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4907
AnnaBridge 171:3a7713b1edbc 4908
AnnaBridge 171:3a7713b1edbc 4909 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4910 -- UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4911 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4912
AnnaBridge 171:3a7713b1edbc 4913 /*!
AnnaBridge 171:3a7713b1edbc 4914 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4915 * @{
AnnaBridge 171:3a7713b1edbc 4916 */
AnnaBridge 171:3a7713b1edbc 4917
AnnaBridge 171:3a7713b1edbc 4918 /** UART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4919 typedef struct {
AnnaBridge 171:3a7713b1edbc 4920 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4921 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4922 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4923 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4924 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4925 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4926 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4927 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 4928 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4929 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 4930 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4931 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 4932 uint8_t RESERVED_0[12];
AnnaBridge 171:3a7713b1edbc 4933 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 4934 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 4935 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 4936 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 4937 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 4938 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 4939 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 4940 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 4941 uint8_t RESERVED_1[26];
AnnaBridge 171:3a7713b1edbc 4942 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
AnnaBridge 171:3a7713b1edbc 4943 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
AnnaBridge 171:3a7713b1edbc 4944 union { /* offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 4945 struct { /* offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 4946 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 4947 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
AnnaBridge 171:3a7713b1edbc 4948 } TYPE0;
AnnaBridge 171:3a7713b1edbc 4949 struct { /* offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 4950 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 4951 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
AnnaBridge 171:3a7713b1edbc 4952 } TYPE1;
AnnaBridge 171:3a7713b1edbc 4953 };
AnnaBridge 171:3a7713b1edbc 4954 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
AnnaBridge 171:3a7713b1edbc 4955 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
AnnaBridge 171:3a7713b1edbc 4956 } UART_Type;
AnnaBridge 171:3a7713b1edbc 4957
AnnaBridge 171:3a7713b1edbc 4958 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4959 -- UART Register Masks
AnnaBridge 171:3a7713b1edbc 4960 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4961
AnnaBridge 171:3a7713b1edbc 4962 /*!
AnnaBridge 171:3a7713b1edbc 4963 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 171:3a7713b1edbc 4964 * @{
AnnaBridge 171:3a7713b1edbc 4965 */
AnnaBridge 171:3a7713b1edbc 4966
AnnaBridge 171:3a7713b1edbc 4967 /*! @name BDH - UART Baud Rate Registers: High */
AnnaBridge 171:3a7713b1edbc 4968 #define UART_BDH_SBR_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4969 #define UART_BDH_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4970 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 4971 #define UART_BDH_RXEDGIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4972 #define UART_BDH_RXEDGIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4973 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 4974
AnnaBridge 171:3a7713b1edbc 4975 /*! @name BDL - UART Baud Rate Registers: Low */
AnnaBridge 171:3a7713b1edbc 4976 #define UART_BDL_SBR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4977 #define UART_BDL_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4978 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 4979
AnnaBridge 171:3a7713b1edbc 4980 /*! @name C1 - UART Control Register 1 */
AnnaBridge 171:3a7713b1edbc 4981 #define UART_C1_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4982 #define UART_C1_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4983 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
AnnaBridge 171:3a7713b1edbc 4984 #define UART_C1_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4985 #define UART_C1_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4986 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
AnnaBridge 171:3a7713b1edbc 4987 #define UART_C1_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4988 #define UART_C1_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4989 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 4990 #define UART_C1_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4991 #define UART_C1_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4992 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 4993 #define UART_C1_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4994 #define UART_C1_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4995 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
AnnaBridge 171:3a7713b1edbc 4996 #define UART_C1_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4997 #define UART_C1_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4998 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 4999 #define UART_C1_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5000 #define UART_C1_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5001 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 5002
AnnaBridge 171:3a7713b1edbc 5003 /*! @name C2 - UART Control Register 2 */
AnnaBridge 171:3a7713b1edbc 5004 #define UART_C2_SBK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5005 #define UART_C2_SBK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5006 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 5007 #define UART_C2_RWU_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5008 #define UART_C2_RWU_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5009 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 5010 #define UART_C2_RE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5011 #define UART_C2_RE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5012 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
AnnaBridge 171:3a7713b1edbc 5013 #define UART_C2_TE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5014 #define UART_C2_TE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5015 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
AnnaBridge 171:3a7713b1edbc 5016 #define UART_C2_ILIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5017 #define UART_C2_ILIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5018 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 5019 #define UART_C2_RIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5020 #define UART_C2_RIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5021 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 5022 #define UART_C2_TCIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5023 #define UART_C2_TCIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5024 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 5025 #define UART_C2_TIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5026 #define UART_C2_TIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5027 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 5028
AnnaBridge 171:3a7713b1edbc 5029 /*! @name S1 - UART Status Register 1 */
AnnaBridge 171:3a7713b1edbc 5030 #define UART_S1_PF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5031 #define UART_S1_PF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5032 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
AnnaBridge 171:3a7713b1edbc 5033 #define UART_S1_FE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5034 #define UART_S1_FE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5035 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
AnnaBridge 171:3a7713b1edbc 5036 #define UART_S1_NF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5037 #define UART_S1_NF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5038 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
AnnaBridge 171:3a7713b1edbc 5039 #define UART_S1_OR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5040 #define UART_S1_OR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5041 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
AnnaBridge 171:3a7713b1edbc 5042 #define UART_S1_IDLE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5043 #define UART_S1_IDLE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5044 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 5045 #define UART_S1_RDRF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5046 #define UART_S1_RDRF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5047 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 5048 #define UART_S1_TC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5049 #define UART_S1_TC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5050 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
AnnaBridge 171:3a7713b1edbc 5051 #define UART_S1_TDRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5052 #define UART_S1_TDRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5053 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 5054
AnnaBridge 171:3a7713b1edbc 5055 /*! @name S2 - UART Status Register 2 */
AnnaBridge 171:3a7713b1edbc 5056 #define UART_S2_RAF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5057 #define UART_S2_RAF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5058 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 5059 #define UART_S2_BRK13_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5060 #define UART_S2_BRK13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5061 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 5062 #define UART_S2_RWUID_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5063 #define UART_S2_RWUID_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5064 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 5065 #define UART_S2_RXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5066 #define UART_S2_RXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5067 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 5068 #define UART_S2_MSBF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5069 #define UART_S2_MSBF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5070 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 5071 #define UART_S2_RXEDGIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5072 #define UART_S2_RXEDGIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5073 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 5074
AnnaBridge 171:3a7713b1edbc 5075 /*! @name C3 - UART Control Register 3 */
AnnaBridge 171:3a7713b1edbc 5076 #define UART_C3_PEIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5077 #define UART_C3_PEIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5078 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 5079 #define UART_C3_FEIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5080 #define UART_C3_FEIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5081 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 5082 #define UART_C3_NEIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5083 #define UART_C3_NEIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5084 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 5085 #define UART_C3_ORIE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5086 #define UART_C3_ORIE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5087 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 5088 #define UART_C3_TXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5089 #define UART_C3_TXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5090 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 5091 #define UART_C3_TXDIR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5092 #define UART_C3_TXDIR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5093 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 5094 #define UART_C3_T8_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5095 #define UART_C3_T8_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5096 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
AnnaBridge 171:3a7713b1edbc 5097 #define UART_C3_R8_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5098 #define UART_C3_R8_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5099 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
AnnaBridge 171:3a7713b1edbc 5100
AnnaBridge 171:3a7713b1edbc 5101 /*! @name D - UART Data Register */
AnnaBridge 171:3a7713b1edbc 5102 #define UART_D_RT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5103 #define UART_D_RT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5104 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
AnnaBridge 171:3a7713b1edbc 5105
AnnaBridge 171:3a7713b1edbc 5106 /*! @name MA1 - UART Match Address Registers 1 */
AnnaBridge 171:3a7713b1edbc 5107 #define UART_MA1_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5108 #define UART_MA1_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5109 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
AnnaBridge 171:3a7713b1edbc 5110
AnnaBridge 171:3a7713b1edbc 5111 /*! @name MA2 - UART Match Address Registers 2 */
AnnaBridge 171:3a7713b1edbc 5112 #define UART_MA2_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5113 #define UART_MA2_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5114 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
AnnaBridge 171:3a7713b1edbc 5115
AnnaBridge 171:3a7713b1edbc 5116 /*! @name C4 - UART Control Register 4 */
AnnaBridge 171:3a7713b1edbc 5117 #define UART_C4_BRFA_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5118 #define UART_C4_BRFA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5119 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
AnnaBridge 171:3a7713b1edbc 5120 #define UART_C4_M10_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5121 #define UART_C4_M10_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5122 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
AnnaBridge 171:3a7713b1edbc 5123 #define UART_C4_MAEN2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5124 #define UART_C4_MAEN2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5125 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 5126 #define UART_C4_MAEN1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5127 #define UART_C4_MAEN1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5128 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 5129
AnnaBridge 171:3a7713b1edbc 5130 /*! @name C5 - UART Control Register 5 */
AnnaBridge 171:3a7713b1edbc 5131 #define UART_C5_RDMAS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5132 #define UART_C5_RDMAS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5133 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 5134 #define UART_C5_TDMAS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5135 #define UART_C5_TDMAS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5136 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 5137
AnnaBridge 171:3a7713b1edbc 5138 /*! @name C7816 - UART 7816 Control Register */
AnnaBridge 171:3a7713b1edbc 5139 #define UART_C7816_ISO_7816E_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5140 #define UART_C7816_ISO_7816E_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5141 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
AnnaBridge 171:3a7713b1edbc 5142 #define UART_C7816_TTYPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5143 #define UART_C7816_TTYPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5144 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
AnnaBridge 171:3a7713b1edbc 5145 #define UART_C7816_INIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5146 #define UART_C7816_INIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5147 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 5148 #define UART_C7816_ANACK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5149 #define UART_C7816_ANACK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5150 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
AnnaBridge 171:3a7713b1edbc 5151 #define UART_C7816_ONACK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5152 #define UART_C7816_ONACK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5153 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
AnnaBridge 171:3a7713b1edbc 5154
AnnaBridge 171:3a7713b1edbc 5155 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 5156 #define UART_IE7816_RXTE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5157 #define UART_IE7816_RXTE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5158 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
AnnaBridge 171:3a7713b1edbc 5159 #define UART_IE7816_TXTE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5160 #define UART_IE7816_TXTE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5161 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
AnnaBridge 171:3a7713b1edbc 5162 #define UART_IE7816_GTVE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5163 #define UART_IE7816_GTVE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5164 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
AnnaBridge 171:3a7713b1edbc 5165 #define UART_IE7816_ADTE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5166 #define UART_IE7816_ADTE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5167 #define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
AnnaBridge 171:3a7713b1edbc 5168 #define UART_IE7816_INITDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5169 #define UART_IE7816_INITDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5170 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
AnnaBridge 171:3a7713b1edbc 5171 #define UART_IE7816_BWTE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5172 #define UART_IE7816_BWTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5173 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
AnnaBridge 171:3a7713b1edbc 5174 #define UART_IE7816_CWTE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5175 #define UART_IE7816_CWTE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5176 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
AnnaBridge 171:3a7713b1edbc 5177 #define UART_IE7816_WTE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5178 #define UART_IE7816_WTE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5179 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
AnnaBridge 171:3a7713b1edbc 5180
AnnaBridge 171:3a7713b1edbc 5181 /*! @name IS7816 - UART 7816 Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 5182 #define UART_IS7816_RXT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5183 #define UART_IS7816_RXT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5184 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
AnnaBridge 171:3a7713b1edbc 5185 #define UART_IS7816_TXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5186 #define UART_IS7816_TXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5187 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
AnnaBridge 171:3a7713b1edbc 5188 #define UART_IS7816_GTV_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5189 #define UART_IS7816_GTV_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5190 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
AnnaBridge 171:3a7713b1edbc 5191 #define UART_IS7816_ADT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5192 #define UART_IS7816_ADT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5193 #define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
AnnaBridge 171:3a7713b1edbc 5194 #define UART_IS7816_INITD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5195 #define UART_IS7816_INITD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5196 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
AnnaBridge 171:3a7713b1edbc 5197 #define UART_IS7816_BWT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5198 #define UART_IS7816_BWT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5199 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
AnnaBridge 171:3a7713b1edbc 5200 #define UART_IS7816_CWT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5201 #define UART_IS7816_CWT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5202 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
AnnaBridge 171:3a7713b1edbc 5203 #define UART_IS7816_WT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5204 #define UART_IS7816_WT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5205 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
AnnaBridge 171:3a7713b1edbc 5206
AnnaBridge 171:3a7713b1edbc 5207 /*! @name WP7816 - UART 7816 Wait Parameter Register */
AnnaBridge 171:3a7713b1edbc 5208 #define UART_WP7816_WTX_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5209 #define UART_WP7816_WTX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5210 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
AnnaBridge 171:3a7713b1edbc 5211
AnnaBridge 171:3a7713b1edbc 5212 /*! @name WN7816 - UART 7816 Wait N Register */
AnnaBridge 171:3a7713b1edbc 5213 #define UART_WN7816_GTN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5214 #define UART_WN7816_GTN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5215 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
AnnaBridge 171:3a7713b1edbc 5216
AnnaBridge 171:3a7713b1edbc 5217 /*! @name WF7816 - UART 7816 Wait FD Register */
AnnaBridge 171:3a7713b1edbc 5218 #define UART_WF7816_GTFD_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5219 #define UART_WF7816_GTFD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5220 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
AnnaBridge 171:3a7713b1edbc 5221
AnnaBridge 171:3a7713b1edbc 5222 /*! @name ET7816 - UART 7816 Error Threshold Register */
AnnaBridge 171:3a7713b1edbc 5223 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 5224 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5225 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 5226 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 5227 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5228 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 5229
AnnaBridge 171:3a7713b1edbc 5230 /*! @name TL7816 - UART 7816 Transmit Length Register */
AnnaBridge 171:3a7713b1edbc 5231 #define UART_TL7816_TLEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5232 #define UART_TL7816_TLEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5233 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
AnnaBridge 171:3a7713b1edbc 5234
AnnaBridge 171:3a7713b1edbc 5235 /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
AnnaBridge 171:3a7713b1edbc 5236 #define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5237 #define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5238 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
AnnaBridge 171:3a7713b1edbc 5239
AnnaBridge 171:3a7713b1edbc 5240 /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
AnnaBridge 171:3a7713b1edbc 5241 #define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5242 #define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5243 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
AnnaBridge 171:3a7713b1edbc 5244
AnnaBridge 171:3a7713b1edbc 5245 /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
AnnaBridge 171:3a7713b1edbc 5246 #define UART_WP7816A_T0_WI_H_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5247 #define UART_WP7816A_T0_WI_H_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5248 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
AnnaBridge 171:3a7713b1edbc 5249
AnnaBridge 171:3a7713b1edbc 5250 /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
AnnaBridge 171:3a7713b1edbc 5251 #define UART_WP7816B_T0_WI_L_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5252 #define UART_WP7816B_T0_WI_L_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5253 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
AnnaBridge 171:3a7713b1edbc 5254
AnnaBridge 171:3a7713b1edbc 5255 /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
AnnaBridge 171:3a7713b1edbc 5256 #define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5257 #define UART_WP7816A_T1_BWI_H_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5258 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
AnnaBridge 171:3a7713b1edbc 5259
AnnaBridge 171:3a7713b1edbc 5260 /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
AnnaBridge 171:3a7713b1edbc 5261 #define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5262 #define UART_WP7816B_T1_BWI_L_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5263 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
AnnaBridge 171:3a7713b1edbc 5264
AnnaBridge 171:3a7713b1edbc 5265 /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
AnnaBridge 171:3a7713b1edbc 5266 #define UART_WGP7816_T1_BGI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 5267 #define UART_WGP7816_T1_BGI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5268 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
AnnaBridge 171:3a7713b1edbc 5269 #define UART_WGP7816_T1_CWI1_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 5270 #define UART_WGP7816_T1_CWI1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5271 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
AnnaBridge 171:3a7713b1edbc 5272
AnnaBridge 171:3a7713b1edbc 5273 /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
AnnaBridge 171:3a7713b1edbc 5274 #define UART_WP7816C_T1_CWI2_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5275 #define UART_WP7816C_T1_CWI2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5276 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
AnnaBridge 171:3a7713b1edbc 5277
AnnaBridge 171:3a7713b1edbc 5278
AnnaBridge 171:3a7713b1edbc 5279 /*!
AnnaBridge 171:3a7713b1edbc 5280 * @}
AnnaBridge 171:3a7713b1edbc 5281 */ /* end of group UART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5282
AnnaBridge 171:3a7713b1edbc 5283
AnnaBridge 171:3a7713b1edbc 5284 /* UART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5285 /** Peripheral UART2 base address */
AnnaBridge 171:3a7713b1edbc 5286 #define UART2_BASE (0x4006C000u)
AnnaBridge 171:3a7713b1edbc 5287 /** Peripheral UART2 base pointer */
AnnaBridge 171:3a7713b1edbc 5288 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 171:3a7713b1edbc 5289 /** Array initializer of UART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5290 #define UART_BASE_ADDRS { 0u, 0u, UART2_BASE }
AnnaBridge 171:3a7713b1edbc 5291 /** Array initializer of UART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5292 #define UART_BASE_PTRS { (UART_Type *)0u, (UART_Type *)0u, UART2 }
AnnaBridge 171:3a7713b1edbc 5293 /** Interrupt vectors for the UART peripheral type */
AnnaBridge 171:3a7713b1edbc 5294 #define UART_RX_TX_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
AnnaBridge 171:3a7713b1edbc 5295 #define UART_ERR_IRQS { NotAvail_IRQn, NotAvail_IRQn, UART2_FLEXIO_IRQn }
AnnaBridge 171:3a7713b1edbc 5296
AnnaBridge 171:3a7713b1edbc 5297 /*!
AnnaBridge 171:3a7713b1edbc 5298 * @}
AnnaBridge 171:3a7713b1edbc 5299 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5300
AnnaBridge 171:3a7713b1edbc 5301
AnnaBridge 171:3a7713b1edbc 5302 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5303 -- USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5304 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5305
AnnaBridge 171:3a7713b1edbc 5306 /*!
AnnaBridge 171:3a7713b1edbc 5307 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5308 * @{
AnnaBridge 171:3a7713b1edbc 5309 */
AnnaBridge 171:3a7713b1edbc 5310
AnnaBridge 171:3a7713b1edbc 5311 /** USB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5312 typedef struct {
AnnaBridge 171:3a7713b1edbc 5313 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5314 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 5315 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5316 uint8_t RESERVED_1[3];
AnnaBridge 171:3a7713b1edbc 5317 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5318 uint8_t RESERVED_2[3];
AnnaBridge 171:3a7713b1edbc 5319 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5320 uint8_t RESERVED_3[15];
AnnaBridge 171:3a7713b1edbc 5321 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 5322 uint8_t RESERVED_4[99];
AnnaBridge 171:3a7713b1edbc 5323 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 5324 uint8_t RESERVED_5[3];
AnnaBridge 171:3a7713b1edbc 5325 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 5326 uint8_t RESERVED_6[3];
AnnaBridge 171:3a7713b1edbc 5327 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 5328 uint8_t RESERVED_7[3];
AnnaBridge 171:3a7713b1edbc 5329 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 5330 uint8_t RESERVED_8[3];
AnnaBridge 171:3a7713b1edbc 5331 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 5332 uint8_t RESERVED_9[3];
AnnaBridge 171:3a7713b1edbc 5333 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 5334 uint8_t RESERVED_10[3];
AnnaBridge 171:3a7713b1edbc 5335 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 5336 uint8_t RESERVED_11[3];
AnnaBridge 171:3a7713b1edbc 5337 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 5338 uint8_t RESERVED_12[3];
AnnaBridge 171:3a7713b1edbc 5339 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 5340 uint8_t RESERVED_13[3];
AnnaBridge 171:3a7713b1edbc 5341 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 5342 uint8_t RESERVED_14[11];
AnnaBridge 171:3a7713b1edbc 5343 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 5344 uint8_t RESERVED_15[3];
AnnaBridge 171:3a7713b1edbc 5345 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 5346 uint8_t RESERVED_16[11];
AnnaBridge 171:3a7713b1edbc 5347 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5348 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5349 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 5350 } ENDPOINT[16];
AnnaBridge 171:3a7713b1edbc 5351 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 5352 uint8_t RESERVED_17[3];
AnnaBridge 171:3a7713b1edbc 5353 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 5354 uint8_t RESERVED_18[3];
AnnaBridge 171:3a7713b1edbc 5355 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 5356 uint8_t RESERVED_19[3];
AnnaBridge 171:3a7713b1edbc 5357 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 5358 uint8_t RESERVED_20[7];
AnnaBridge 171:3a7713b1edbc 5359 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 5360 uint8_t RESERVED_21[15];
AnnaBridge 171:3a7713b1edbc 5361 __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 5362 uint8_t RESERVED_22[3];
AnnaBridge 171:3a7713b1edbc 5363 __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */
AnnaBridge 171:3a7713b1edbc 5364 uint8_t RESERVED_23[23];
AnnaBridge 171:3a7713b1edbc 5365 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
AnnaBridge 171:3a7713b1edbc 5366 uint8_t RESERVED_24[3];
AnnaBridge 171:3a7713b1edbc 5367 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 5368 uint8_t RESERVED_25[15];
AnnaBridge 171:3a7713b1edbc 5369 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
AnnaBridge 171:3a7713b1edbc 5370 uint8_t RESERVED_26[7];
AnnaBridge 171:3a7713b1edbc 5371 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
AnnaBridge 171:3a7713b1edbc 5372 } USB_Type;
AnnaBridge 171:3a7713b1edbc 5373
AnnaBridge 171:3a7713b1edbc 5374 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5375 -- USB Register Masks
AnnaBridge 171:3a7713b1edbc 5376 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5377
AnnaBridge 171:3a7713b1edbc 5378 /*!
AnnaBridge 171:3a7713b1edbc 5379 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 171:3a7713b1edbc 5380 * @{
AnnaBridge 171:3a7713b1edbc 5381 */
AnnaBridge 171:3a7713b1edbc 5382
AnnaBridge 171:3a7713b1edbc 5383 /*! @name PERID - Peripheral ID register */
AnnaBridge 171:3a7713b1edbc 5384 #define USB_PERID_ID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5385 #define USB_PERID_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5386 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 5387
AnnaBridge 171:3a7713b1edbc 5388 /*! @name IDCOMP - Peripheral ID Complement register */
AnnaBridge 171:3a7713b1edbc 5389 #define USB_IDCOMP_NID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5390 #define USB_IDCOMP_NID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5391 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
AnnaBridge 171:3a7713b1edbc 5392
AnnaBridge 171:3a7713b1edbc 5393 /*! @name REV - Peripheral Revision register */
AnnaBridge 171:3a7713b1edbc 5394 #define USB_REV_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5395 #define USB_REV_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5396 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
AnnaBridge 171:3a7713b1edbc 5397
AnnaBridge 171:3a7713b1edbc 5398 /*! @name ADDINFO - Peripheral Additional Info register */
AnnaBridge 171:3a7713b1edbc 5399 #define USB_ADDINFO_IEHOST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5400 #define USB_ADDINFO_IEHOST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5401 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
AnnaBridge 171:3a7713b1edbc 5402
AnnaBridge 171:3a7713b1edbc 5403 /*! @name OTGCTL - OTG Control register */
AnnaBridge 171:3a7713b1edbc 5404 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5405 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5406 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 5407
AnnaBridge 171:3a7713b1edbc 5408 /*! @name ISTAT - Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 5409 #define USB_ISTAT_USBRST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5410 #define USB_ISTAT_USBRST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5411 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
AnnaBridge 171:3a7713b1edbc 5412 #define USB_ISTAT_ERROR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5413 #define USB_ISTAT_ERROR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5414 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 5415 #define USB_ISTAT_SOFTOK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5416 #define USB_ISTAT_SOFTOK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5417 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
AnnaBridge 171:3a7713b1edbc 5418 #define USB_ISTAT_TOKDNE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5419 #define USB_ISTAT_TOKDNE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5420 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
AnnaBridge 171:3a7713b1edbc 5421 #define USB_ISTAT_SLEEP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5422 #define USB_ISTAT_SLEEP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5423 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
AnnaBridge 171:3a7713b1edbc 5424 #define USB_ISTAT_RESUME_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5425 #define USB_ISTAT_RESUME_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5426 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 5427 #define USB_ISTAT_STALL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5428 #define USB_ISTAT_STALL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5429 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
AnnaBridge 171:3a7713b1edbc 5430
AnnaBridge 171:3a7713b1edbc 5431 /*! @name INTEN - Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 5432 #define USB_INTEN_USBRSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5433 #define USB_INTEN_USBRSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5434 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 5435 #define USB_INTEN_ERROREN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5436 #define USB_INTEN_ERROREN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5437 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
AnnaBridge 171:3a7713b1edbc 5438 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5439 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5440 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
AnnaBridge 171:3a7713b1edbc 5441 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5442 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5443 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
AnnaBridge 171:3a7713b1edbc 5444 #define USB_INTEN_SLEEPEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5445 #define USB_INTEN_SLEEPEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5446 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
AnnaBridge 171:3a7713b1edbc 5447 #define USB_INTEN_RESUMEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5448 #define USB_INTEN_RESUMEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5449 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
AnnaBridge 171:3a7713b1edbc 5450 #define USB_INTEN_STALLEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5451 #define USB_INTEN_STALLEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5452 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
AnnaBridge 171:3a7713b1edbc 5453
AnnaBridge 171:3a7713b1edbc 5454 /*! @name ERRSTAT - Error Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 5455 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5456 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5457 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
AnnaBridge 171:3a7713b1edbc 5458 #define USB_ERRSTAT_CRC5_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5459 #define USB_ERRSTAT_CRC5_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5460 #define USB_ERRSTAT_CRC5(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5_SHIFT)) & USB_ERRSTAT_CRC5_MASK)
AnnaBridge 171:3a7713b1edbc 5461 #define USB_ERRSTAT_CRC16_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5462 #define USB_ERRSTAT_CRC16_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5463 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
AnnaBridge 171:3a7713b1edbc 5464 #define USB_ERRSTAT_DFN8_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5465 #define USB_ERRSTAT_DFN8_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5466 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
AnnaBridge 171:3a7713b1edbc 5467 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5468 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5469 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
AnnaBridge 171:3a7713b1edbc 5470 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5471 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5472 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
AnnaBridge 171:3a7713b1edbc 5473 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5474 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5475 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
AnnaBridge 171:3a7713b1edbc 5476
AnnaBridge 171:3a7713b1edbc 5477 /*! @name ERREN - Error Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 5478 #define USB_ERREN_PIDERREN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5479 #define USB_ERREN_PIDERREN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5480 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
AnnaBridge 171:3a7713b1edbc 5481 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5482 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5483 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 5484 #define USB_ERREN_CRC16EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5485 #define USB_ERREN_CRC16EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5486 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
AnnaBridge 171:3a7713b1edbc 5487 #define USB_ERREN_DFN8EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5488 #define USB_ERREN_DFN8EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5489 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
AnnaBridge 171:3a7713b1edbc 5490 #define USB_ERREN_BTOERREN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5491 #define USB_ERREN_BTOERREN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5492 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
AnnaBridge 171:3a7713b1edbc 5493 #define USB_ERREN_DMAERREN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5494 #define USB_ERREN_DMAERREN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5495 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
AnnaBridge 171:3a7713b1edbc 5496 #define USB_ERREN_BTSERREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5497 #define USB_ERREN_BTSERREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5498 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
AnnaBridge 171:3a7713b1edbc 5499
AnnaBridge 171:3a7713b1edbc 5500 /*! @name STAT - Status register */
AnnaBridge 171:3a7713b1edbc 5501 #define USB_STAT_ODD_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5502 #define USB_STAT_ODD_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5503 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
AnnaBridge 171:3a7713b1edbc 5504 #define USB_STAT_TX_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5505 #define USB_STAT_TX_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5506 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
AnnaBridge 171:3a7713b1edbc 5507 #define USB_STAT_ENDP_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 5508 #define USB_STAT_ENDP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5509 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
AnnaBridge 171:3a7713b1edbc 5510
AnnaBridge 171:3a7713b1edbc 5511 /*! @name CTL - Control register */
AnnaBridge 171:3a7713b1edbc 5512 #define USB_CTL_USBENSOFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5513 #define USB_CTL_USBENSOFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5514 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 5515 #define USB_CTL_ODDRST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5516 #define USB_CTL_ODDRST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5517 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
AnnaBridge 171:3a7713b1edbc 5518 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5519 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5520 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
AnnaBridge 171:3a7713b1edbc 5521 #define USB_CTL_SE0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5522 #define USB_CTL_SE0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5523 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 5524 #define USB_CTL_JSTATE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5525 #define USB_CTL_JSTATE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5526 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
AnnaBridge 171:3a7713b1edbc 5527
AnnaBridge 171:3a7713b1edbc 5528 /*! @name ADDR - Address register */
AnnaBridge 171:3a7713b1edbc 5529 #define USB_ADDR_ADDR_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 5530 #define USB_ADDR_ADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5531 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
AnnaBridge 171:3a7713b1edbc 5532
AnnaBridge 171:3a7713b1edbc 5533 /*! @name BDTPAGE1 - BDT Page register 1 */
AnnaBridge 171:3a7713b1edbc 5534 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 5535 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5536 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 5537
AnnaBridge 171:3a7713b1edbc 5538 /*! @name FRMNUML - Frame Number register Low */
AnnaBridge 171:3a7713b1edbc 5539 #define USB_FRMNUML_FRM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5540 #define USB_FRMNUML_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5541 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 5542
AnnaBridge 171:3a7713b1edbc 5543 /*! @name FRMNUMH - Frame Number register High */
AnnaBridge 171:3a7713b1edbc 5544 #define USB_FRMNUMH_FRM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 5545 #define USB_FRMNUMH_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5546 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 5547
AnnaBridge 171:3a7713b1edbc 5548 /*! @name BDTPAGE2 - BDT Page Register 2 */
AnnaBridge 171:3a7713b1edbc 5549 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5550 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5551 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 5552
AnnaBridge 171:3a7713b1edbc 5553 /*! @name BDTPAGE3 - BDT Page Register 3 */
AnnaBridge 171:3a7713b1edbc 5554 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5555 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5556 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 5557
AnnaBridge 171:3a7713b1edbc 5558 /*! @name ENDPT - Endpoint Control register */
AnnaBridge 171:3a7713b1edbc 5559 #define USB_ENDPT_EPHSHK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5560 #define USB_ENDPT_EPHSHK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5561 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
AnnaBridge 171:3a7713b1edbc 5562 #define USB_ENDPT_EPSTALL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5563 #define USB_ENDPT_EPSTALL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5564 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
AnnaBridge 171:3a7713b1edbc 5565 #define USB_ENDPT_EPTXEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5566 #define USB_ENDPT_EPTXEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5567 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
AnnaBridge 171:3a7713b1edbc 5568 #define USB_ENDPT_EPRXEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5569 #define USB_ENDPT_EPRXEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5570 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
AnnaBridge 171:3a7713b1edbc 5571 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5572 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5573 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5574
AnnaBridge 171:3a7713b1edbc 5575 /* The count of USB_ENDPT */
AnnaBridge 171:3a7713b1edbc 5576 #define USB_ENDPT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 5577
AnnaBridge 171:3a7713b1edbc 5578 /*! @name USBCTRL - USB Control register */
AnnaBridge 171:3a7713b1edbc 5579 #define USB_USBCTRL_PDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5580 #define USB_USBCTRL_PDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5581 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
AnnaBridge 171:3a7713b1edbc 5582 #define USB_USBCTRL_SUSP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5583 #define USB_USBCTRL_SUSP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5584 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
AnnaBridge 171:3a7713b1edbc 5585
AnnaBridge 171:3a7713b1edbc 5586 /*! @name OBSERVE - USB OTG Observe register */
AnnaBridge 171:3a7713b1edbc 5587 #define USB_OBSERVE_DMPD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5588 #define USB_OBSERVE_DMPD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5589 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
AnnaBridge 171:3a7713b1edbc 5590 #define USB_OBSERVE_DPPD_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5591 #define USB_OBSERVE_DPPD_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5592 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
AnnaBridge 171:3a7713b1edbc 5593 #define USB_OBSERVE_DPPU_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5594 #define USB_OBSERVE_DPPU_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5595 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
AnnaBridge 171:3a7713b1edbc 5596
AnnaBridge 171:3a7713b1edbc 5597 /*! @name CONTROL - USB OTG Control register */
AnnaBridge 171:3a7713b1edbc 5598 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5599 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5600 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
AnnaBridge 171:3a7713b1edbc 5601
AnnaBridge 171:3a7713b1edbc 5602 /*! @name USBTRC0 - USB Transceiver Control register 0 */
AnnaBridge 171:3a7713b1edbc 5603 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5604 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5605 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5606 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5607 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5608 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
AnnaBridge 171:3a7713b1edbc 5609 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5610 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5611 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5612 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5613 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5614 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
AnnaBridge 171:3a7713b1edbc 5615 #define USB_USBTRC0_USBRESET_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5616 #define USB_USBTRC0_USBRESET_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5617 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
AnnaBridge 171:3a7713b1edbc 5618
AnnaBridge 171:3a7713b1edbc 5619 /*! @name USBFRMADJUST - Frame Adjust Register */
AnnaBridge 171:3a7713b1edbc 5620 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5621 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5622 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 5623
AnnaBridge 171:3a7713b1edbc 5624 /*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */
AnnaBridge 171:3a7713b1edbc 5625 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5626 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5627 #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5628 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5629 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5630 #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5631 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5632 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5633 #define USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_STOP_ACK_DLY_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5634 #define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5635 #define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5636 #define USB_KEEP_ALIVE_CTRL_AHB_DLY_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_AHB_DLY_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5637 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5638 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5639 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5640 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5641 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5642 #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK)
AnnaBridge 171:3a7713b1edbc 5643
AnnaBridge 171:3a7713b1edbc 5644 /*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */
AnnaBridge 171:3a7713b1edbc 5645 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 5646 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5647 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK)
AnnaBridge 171:3a7713b1edbc 5648 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 5649 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5650 #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK)
AnnaBridge 171:3a7713b1edbc 5651
AnnaBridge 171:3a7713b1edbc 5652 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
AnnaBridge 171:3a7713b1edbc 5653 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5654 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5655 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5656 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5657 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5658 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5659 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5660 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5661 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5662
AnnaBridge 171:3a7713b1edbc 5663 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
AnnaBridge 171:3a7713b1edbc 5664 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5665 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5666 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5667
AnnaBridge 171:3a7713b1edbc 5668 /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
AnnaBridge 171:3a7713b1edbc 5669 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5670 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5671 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5672
AnnaBridge 171:3a7713b1edbc 5673 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
AnnaBridge 171:3a7713b1edbc 5674 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5675 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5676 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 5677
AnnaBridge 171:3a7713b1edbc 5678
AnnaBridge 171:3a7713b1edbc 5679 /*!
AnnaBridge 171:3a7713b1edbc 5680 * @}
AnnaBridge 171:3a7713b1edbc 5681 */ /* end of group USB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5682
AnnaBridge 171:3a7713b1edbc 5683
AnnaBridge 171:3a7713b1edbc 5684 /* USB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5685 /** Peripheral USB0 base address */
AnnaBridge 171:3a7713b1edbc 5686 #define USB0_BASE (0x40072000u)
AnnaBridge 171:3a7713b1edbc 5687 /** Peripheral USB0 base pointer */
AnnaBridge 171:3a7713b1edbc 5688 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 171:3a7713b1edbc 5689 /** Array initializer of USB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5690 #define USB_BASE_ADDRS { USB0_BASE }
AnnaBridge 171:3a7713b1edbc 5691 /** Array initializer of USB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5692 #define USB_BASE_PTRS { USB0 }
AnnaBridge 171:3a7713b1edbc 5693 /** Interrupt vectors for the USB peripheral type */
AnnaBridge 171:3a7713b1edbc 5694 #define USB_IRQS { USB0_IRQn }
AnnaBridge 171:3a7713b1edbc 5695
AnnaBridge 171:3a7713b1edbc 5696 /*!
AnnaBridge 171:3a7713b1edbc 5697 * @}
AnnaBridge 171:3a7713b1edbc 5698 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5699
AnnaBridge 171:3a7713b1edbc 5700
AnnaBridge 171:3a7713b1edbc 5701 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5702 -- VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5703 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5704
AnnaBridge 171:3a7713b1edbc 5705 /*!
AnnaBridge 171:3a7713b1edbc 5706 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5707 * @{
AnnaBridge 171:3a7713b1edbc 5708 */
AnnaBridge 171:3a7713b1edbc 5709
AnnaBridge 171:3a7713b1edbc 5710 /** VREF - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5711 typedef struct {
AnnaBridge 171:3a7713b1edbc 5712 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5713 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5714 } VREF_Type;
AnnaBridge 171:3a7713b1edbc 5715
AnnaBridge 171:3a7713b1edbc 5716 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5717 -- VREF Register Masks
AnnaBridge 171:3a7713b1edbc 5718 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5719
AnnaBridge 171:3a7713b1edbc 5720 /*!
AnnaBridge 171:3a7713b1edbc 5721 * @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge 171:3a7713b1edbc 5722 * @{
AnnaBridge 171:3a7713b1edbc 5723 */
AnnaBridge 171:3a7713b1edbc 5724
AnnaBridge 171:3a7713b1edbc 5725 /*! @name TRM - VREF Trim Register */
AnnaBridge 171:3a7713b1edbc 5726 #define VREF_TRM_TRIM_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5727 #define VREF_TRM_TRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5728 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 5729 #define VREF_TRM_CHOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5730 #define VREF_TRM_CHOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5731 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 5732
AnnaBridge 171:3a7713b1edbc 5733 /*! @name SC - VREF Status and Control Register */
AnnaBridge 171:3a7713b1edbc 5734 #define VREF_SC_MODE_LV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5735 #define VREF_SC_MODE_LV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5736 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
AnnaBridge 171:3a7713b1edbc 5737 #define VREF_SC_VREFST_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5738 #define VREF_SC_VREFST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5739 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
AnnaBridge 171:3a7713b1edbc 5740 #define VREF_SC_ICOMPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5741 #define VREF_SC_ICOMPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5742 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
AnnaBridge 171:3a7713b1edbc 5743 #define VREF_SC_REGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5744 #define VREF_SC_REGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5745 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
AnnaBridge 171:3a7713b1edbc 5746 #define VREF_SC_VREFEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5747 #define VREF_SC_VREFEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5748 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
AnnaBridge 171:3a7713b1edbc 5749
AnnaBridge 171:3a7713b1edbc 5750
AnnaBridge 171:3a7713b1edbc 5751 /*!
AnnaBridge 171:3a7713b1edbc 5752 * @}
AnnaBridge 171:3a7713b1edbc 5753 */ /* end of group VREF_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5754
AnnaBridge 171:3a7713b1edbc 5755
AnnaBridge 171:3a7713b1edbc 5756 /* VREF - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5757 /** Peripheral VREF base address */
AnnaBridge 171:3a7713b1edbc 5758 #define VREF_BASE (0x40074000u)
AnnaBridge 171:3a7713b1edbc 5759 /** Peripheral VREF base pointer */
AnnaBridge 171:3a7713b1edbc 5760 #define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge 171:3a7713b1edbc 5761 /** Array initializer of VREF peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5762 #define VREF_BASE_ADDRS { VREF_BASE }
AnnaBridge 171:3a7713b1edbc 5763 /** Array initializer of VREF peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5764 #define VREF_BASE_PTRS { VREF }
AnnaBridge 171:3a7713b1edbc 5765
AnnaBridge 171:3a7713b1edbc 5766 /*!
AnnaBridge 171:3a7713b1edbc 5767 * @}
AnnaBridge 171:3a7713b1edbc 5768 */ /* end of group VREF_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5769
AnnaBridge 171:3a7713b1edbc 5770
AnnaBridge 171:3a7713b1edbc 5771 /*
AnnaBridge 171:3a7713b1edbc 5772 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 5773 */
AnnaBridge 171:3a7713b1edbc 5774
AnnaBridge 171:3a7713b1edbc 5775 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 5776 #pragma pop
AnnaBridge 171:3a7713b1edbc 5777 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 5778 #pragma pop
AnnaBridge 171:3a7713b1edbc 5779 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 5780 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 5781 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 5782 #pragma language=default
AnnaBridge 171:3a7713b1edbc 5783 #else
AnnaBridge 171:3a7713b1edbc 5784 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 5785 #endif
AnnaBridge 171:3a7713b1edbc 5786
AnnaBridge 171:3a7713b1edbc 5787 /*!
AnnaBridge 171:3a7713b1edbc 5788 * @}
AnnaBridge 171:3a7713b1edbc 5789 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 5790
AnnaBridge 171:3a7713b1edbc 5791
AnnaBridge 171:3a7713b1edbc 5792 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5793 -- SDK Compatibility
AnnaBridge 171:3a7713b1edbc 5794 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5795
AnnaBridge 171:3a7713b1edbc 5796 /*!
AnnaBridge 171:3a7713b1edbc 5797 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 171:3a7713b1edbc 5798 * @{
AnnaBridge 171:3a7713b1edbc 5799 */
AnnaBridge 171:3a7713b1edbc 5800
AnnaBridge 171:3a7713b1edbc 5801 /* No SDK compatibility issues. */
AnnaBridge 171:3a7713b1edbc 5802
AnnaBridge 171:3a7713b1edbc 5803 /*!
AnnaBridge 171:3a7713b1edbc 5804 * @}
AnnaBridge 171:3a7713b1edbc 5805 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 5806
AnnaBridge 171:3a7713b1edbc 5807
AnnaBridge 171:3a7713b1edbc 5808 #endif /* _MKL27Z644_H_ */
AnnaBridge 171:3a7713b1edbc 5809