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TARGET_K66F/TOOLCHAIN_IAR/fsl_port.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /*
AnnaBridge 143:86740a56073b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 143:86740a56073b 3 * Copyright 2016-2017 NXP
AnnaBridge 143:86740a56073b 4 *
AnnaBridge 143:86740a56073b 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 6 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 7 *
AnnaBridge 143:86740a56073b 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 143:86740a56073b 9 * of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 10 *
AnnaBridge 143:86740a56073b 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 143:86740a56073b 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 143:86740a56073b 13 * other materials provided with the distribution.
AnnaBridge 143:86740a56073b 14 *
AnnaBridge 143:86740a56073b 15 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 143:86740a56073b 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 143:86740a56073b 17 * software without specific prior written permission.
AnnaBridge 143:86740a56073b 18 *
AnnaBridge 143:86740a56073b 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 143:86740a56073b 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 143:86740a56073b 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 143:86740a56073b 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 143:86740a56073b 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 143:86740a56073b 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 143:86740a56073b 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 143:86740a56073b 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 143:86740a56073b 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 29 */
AnnaBridge 143:86740a56073b 30 #ifndef _FSL_PORT_H_
AnnaBridge 143:86740a56073b 31 #define _FSL_PORT_H_
AnnaBridge 143:86740a56073b 32
AnnaBridge 143:86740a56073b 33 #include "fsl_common.h"
AnnaBridge 143:86740a56073b 34
AnnaBridge 143:86740a56073b 35 /*!
AnnaBridge 143:86740a56073b 36 * @addtogroup port
AnnaBridge 143:86740a56073b 37 * @{
AnnaBridge 143:86740a56073b 38 */
AnnaBridge 143:86740a56073b 39
AnnaBridge 143:86740a56073b 40 /*******************************************************************************
AnnaBridge 143:86740a56073b 41 * Definitions
AnnaBridge 143:86740a56073b 42 ******************************************************************************/
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 /*! @name Driver version */
AnnaBridge 143:86740a56073b 45 /*@{*/
AnnaBridge 143:86740a56073b 46 /*! Version 2.0.2. */
AnnaBridge 143:86740a56073b 47 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
AnnaBridge 143:86740a56073b 48 /*@}*/
AnnaBridge 143:86740a56073b 49
AnnaBridge 143:86740a56073b 50 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
AnnaBridge 143:86740a56073b 51 /*! @brief Internal resistor pull feature selection */
AnnaBridge 143:86740a56073b 52 enum _port_pull
AnnaBridge 143:86740a56073b 53 {
AnnaBridge 143:86740a56073b 54 kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */
AnnaBridge 143:86740a56073b 55 kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */
AnnaBridge 143:86740a56073b 56 kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */
AnnaBridge 143:86740a56073b 57 };
AnnaBridge 143:86740a56073b 58 #endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
AnnaBridge 143:86740a56073b 59
AnnaBridge 143:86740a56073b 60 #if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
AnnaBridge 143:86740a56073b 61 /*! @brief Slew rate selection */
AnnaBridge 143:86740a56073b 62 enum _port_slew_rate
AnnaBridge 143:86740a56073b 63 {
AnnaBridge 143:86740a56073b 64 kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */
AnnaBridge 143:86740a56073b 65 kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */
AnnaBridge 143:86740a56073b 66 };
AnnaBridge 143:86740a56073b 67 #endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
AnnaBridge 143:86740a56073b 68
AnnaBridge 143:86740a56073b 69 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
AnnaBridge 143:86740a56073b 70 /*! @brief Open Drain feature enable/disable */
AnnaBridge 143:86740a56073b 71 enum _port_open_drain_enable
AnnaBridge 143:86740a56073b 72 {
AnnaBridge 143:86740a56073b 73 kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */
AnnaBridge 143:86740a56073b 74 kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */
AnnaBridge 143:86740a56073b 75 };
AnnaBridge 143:86740a56073b 76 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
AnnaBridge 143:86740a56073b 77
AnnaBridge 143:86740a56073b 78 #if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
AnnaBridge 143:86740a56073b 79 /*! @brief Passive filter feature enable/disable */
AnnaBridge 143:86740a56073b 80 enum _port_passive_filter_enable
AnnaBridge 143:86740a56073b 81 {
AnnaBridge 143:86740a56073b 82 kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */
AnnaBridge 143:86740a56073b 83 kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */
AnnaBridge 143:86740a56073b 84 };
AnnaBridge 143:86740a56073b 85 #endif
AnnaBridge 143:86740a56073b 86
AnnaBridge 143:86740a56073b 87 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
AnnaBridge 143:86740a56073b 88 /*! @brief Configures the drive strength. */
AnnaBridge 143:86740a56073b 89 enum _port_drive_strength
AnnaBridge 143:86740a56073b 90 {
AnnaBridge 143:86740a56073b 91 kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */
AnnaBridge 143:86740a56073b 92 kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */
AnnaBridge 143:86740a56073b 93 };
AnnaBridge 143:86740a56073b 94 #endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
AnnaBridge 143:86740a56073b 95
AnnaBridge 143:86740a56073b 96 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
AnnaBridge 143:86740a56073b 97 /*! @brief Unlock/lock the pin control register field[15:0] */
AnnaBridge 143:86740a56073b 98 enum _port_lock_register
AnnaBridge 143:86740a56073b 99 {
AnnaBridge 143:86740a56073b 100 kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
AnnaBridge 143:86740a56073b 101 kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
AnnaBridge 143:86740a56073b 102 };
AnnaBridge 143:86740a56073b 103 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
AnnaBridge 143:86740a56073b 104
AnnaBridge 143:86740a56073b 105 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
AnnaBridge 143:86740a56073b 106 /*! @brief Pin mux selection */
AnnaBridge 143:86740a56073b 107 typedef enum _port_mux
AnnaBridge 143:86740a56073b 108 {
AnnaBridge 143:86740a56073b 109 kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */
AnnaBridge 143:86740a56073b 110 kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */
AnnaBridge 143:86740a56073b 111 kPORT_MuxAlt2 = 2U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 112 kPORT_MuxAlt3 = 3U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 113 kPORT_MuxAlt4 = 4U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 114 kPORT_MuxAlt5 = 5U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 115 kPORT_MuxAlt6 = 6U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 116 kPORT_MuxAlt7 = 7U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 117 kPORT_MuxAlt8 = 8U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 118 kPORT_MuxAlt9 = 9U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 119 kPORT_MuxAlt10 = 10U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 120 kPORT_MuxAlt11 = 11U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 121 kPORT_MuxAlt12 = 12U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 122 kPORT_MuxAlt13 = 13U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 123 kPORT_MuxAlt14 = 14U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 124 kPORT_MuxAlt15 = 15U, /*!< Chip-specific */
AnnaBridge 143:86740a56073b 125 } port_mux_t;
AnnaBridge 143:86740a56073b 126 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
AnnaBridge 143:86740a56073b 127
AnnaBridge 143:86740a56073b 128 /*! @brief Configures the interrupt generation condition. */
AnnaBridge 143:86740a56073b 129 typedef enum _port_interrupt
AnnaBridge 143:86740a56073b 130 {
AnnaBridge 143:86740a56073b 131 kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
AnnaBridge 143:86740a56073b 132 #if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
AnnaBridge 143:86740a56073b 133 kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
AnnaBridge 143:86740a56073b 134 kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
AnnaBridge 143:86740a56073b 135 kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
AnnaBridge 143:86740a56073b 136 #endif
AnnaBridge 143:86740a56073b 137 #if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
AnnaBridge 143:86740a56073b 138 kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
AnnaBridge 143:86740a56073b 139 kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
AnnaBridge 143:86740a56073b 140 kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
AnnaBridge 143:86740a56073b 141 #endif
AnnaBridge 143:86740a56073b 142 kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
AnnaBridge 143:86740a56073b 143 kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
AnnaBridge 143:86740a56073b 144 kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
AnnaBridge 143:86740a56073b 145 kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
AnnaBridge 143:86740a56073b 146 kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
AnnaBridge 143:86740a56073b 147 #if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
AnnaBridge 143:86740a56073b 148 kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */
AnnaBridge 143:86740a56073b 149 kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */
AnnaBridge 143:86740a56073b 150 #endif
AnnaBridge 143:86740a56073b 151 } port_interrupt_t;
AnnaBridge 143:86740a56073b 152
AnnaBridge 143:86740a56073b 153 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
AnnaBridge 143:86740a56073b 154 /*! @brief Digital filter clock source selection */
AnnaBridge 143:86740a56073b 155 typedef enum _port_digital_filter_clock_source
AnnaBridge 143:86740a56073b 156 {
AnnaBridge 143:86740a56073b 157 kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
AnnaBridge 143:86740a56073b 158 kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
AnnaBridge 143:86740a56073b 159 } port_digital_filter_clock_source_t;
AnnaBridge 143:86740a56073b 160
AnnaBridge 143:86740a56073b 161 /*! @brief PORT digital filter feature configuration definition */
AnnaBridge 143:86740a56073b 162 typedef struct _port_digital_filter_config
AnnaBridge 143:86740a56073b 163 {
AnnaBridge 143:86740a56073b 164 uint32_t digitalFilterWidth; /*!< Set digital filter width */
AnnaBridge 143:86740a56073b 165 port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
AnnaBridge 143:86740a56073b 166 } port_digital_filter_config_t;
AnnaBridge 143:86740a56073b 167 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
AnnaBridge 143:86740a56073b 168
AnnaBridge 143:86740a56073b 169 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
AnnaBridge 143:86740a56073b 170 /*! @brief PORT pin configuration structure */
AnnaBridge 143:86740a56073b 171 typedef struct _port_pin_config
AnnaBridge 143:86740a56073b 172 {
AnnaBridge 143:86740a56073b 173 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
AnnaBridge 143:86740a56073b 174 uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */
AnnaBridge 143:86740a56073b 175 #else
AnnaBridge 143:86740a56073b 176 uint16_t : 2;
AnnaBridge 143:86740a56073b 177 #endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */
AnnaBridge 143:86740a56073b 178
AnnaBridge 143:86740a56073b 179 #if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE
AnnaBridge 143:86740a56073b 180 uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */
AnnaBridge 143:86740a56073b 181 #else
AnnaBridge 143:86740a56073b 182 uint16_t : 1;
AnnaBridge 143:86740a56073b 183 #endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */
AnnaBridge 143:86740a56073b 184
AnnaBridge 143:86740a56073b 185 uint16_t : 1;
AnnaBridge 143:86740a56073b 186
AnnaBridge 143:86740a56073b 187 #if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER
AnnaBridge 143:86740a56073b 188 uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */
AnnaBridge 143:86740a56073b 189 #else
AnnaBridge 143:86740a56073b 190 uint16_t : 1;
AnnaBridge 143:86740a56073b 191 #endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */
AnnaBridge 143:86740a56073b 192
AnnaBridge 143:86740a56073b 193 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
AnnaBridge 143:86740a56073b 194 uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */
AnnaBridge 143:86740a56073b 195 #else
AnnaBridge 143:86740a56073b 196 uint16_t : 1;
AnnaBridge 143:86740a56073b 197 #endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
AnnaBridge 143:86740a56073b 198
AnnaBridge 143:86740a56073b 199 #if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
AnnaBridge 143:86740a56073b 200 uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */
AnnaBridge 143:86740a56073b 201 #else
AnnaBridge 143:86740a56073b 202 uint16_t : 1;
AnnaBridge 143:86740a56073b 203 #endif
AnnaBridge 143:86740a56073b 204
AnnaBridge 143:86740a56073b 205 uint16_t : 1;
AnnaBridge 143:86740a56073b 206
AnnaBridge 143:86740a56073b 207 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
AnnaBridge 143:86740a56073b 208 uint16_t mux : 3; /*!< Pin mux Configure */
AnnaBridge 143:86740a56073b 209 #else
AnnaBridge 143:86740a56073b 210 uint16_t : 3;
AnnaBridge 143:86740a56073b 211 #endif
AnnaBridge 143:86740a56073b 212
AnnaBridge 143:86740a56073b 213 uint16_t : 4;
AnnaBridge 143:86740a56073b 214
AnnaBridge 143:86740a56073b 215 #if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
AnnaBridge 143:86740a56073b 216 uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */
AnnaBridge 143:86740a56073b 217 #else
AnnaBridge 143:86740a56073b 218 uint16_t : 1;
AnnaBridge 143:86740a56073b 219 #endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
AnnaBridge 143:86740a56073b 220 } port_pin_config_t;
AnnaBridge 143:86740a56073b 221 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
AnnaBridge 143:86740a56073b 222
AnnaBridge 143:86740a56073b 223 /*******************************************************************************
AnnaBridge 143:86740a56073b 224 * API
AnnaBridge 143:86740a56073b 225 ******************************************************************************/
AnnaBridge 143:86740a56073b 226
AnnaBridge 143:86740a56073b 227 #if defined(__cplusplus)
AnnaBridge 143:86740a56073b 228 extern "C" {
AnnaBridge 143:86740a56073b 229 #endif
AnnaBridge 143:86740a56073b 230
AnnaBridge 143:86740a56073b 231 #if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
AnnaBridge 143:86740a56073b 232 /*! @name Configuration */
AnnaBridge 143:86740a56073b 233 /*@{*/
AnnaBridge 143:86740a56073b 234
AnnaBridge 143:86740a56073b 235 /*!
AnnaBridge 143:86740a56073b 236 * @brief Sets the port PCR register.
AnnaBridge 143:86740a56073b 237 *
AnnaBridge 143:86740a56073b 238 * This is an example to define an input pin or output pin PCR configuration.
AnnaBridge 143:86740a56073b 239 * @code
AnnaBridge 143:86740a56073b 240 * // Define a digital input pin PCR configuration
AnnaBridge 143:86740a56073b 241 * port_pin_config_t config = {
AnnaBridge 143:86740a56073b 242 * kPORT_PullUp,
AnnaBridge 143:86740a56073b 243 * kPORT_FastSlewRate,
AnnaBridge 143:86740a56073b 244 * kPORT_PassiveFilterDisable,
AnnaBridge 143:86740a56073b 245 * kPORT_OpenDrainDisable,
AnnaBridge 143:86740a56073b 246 * kPORT_LowDriveStrength,
AnnaBridge 143:86740a56073b 247 * kPORT_MuxAsGpio,
AnnaBridge 143:86740a56073b 248 * kPORT_UnLockRegister,
AnnaBridge 143:86740a56073b 249 * };
AnnaBridge 143:86740a56073b 250 * @endcode
AnnaBridge 143:86740a56073b 251 *
AnnaBridge 143:86740a56073b 252 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 253 * @param pin PORT pin number.
AnnaBridge 143:86740a56073b 254 * @param config PORT PCR register configuration structure.
AnnaBridge 143:86740a56073b 255 */
AnnaBridge 143:86740a56073b 256 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
AnnaBridge 143:86740a56073b 257 {
AnnaBridge 143:86740a56073b 258 assert(config);
AnnaBridge 143:86740a56073b 259 uint32_t addr = (uint32_t)&base->PCR[pin];
AnnaBridge 143:86740a56073b 260 *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
AnnaBridge 143:86740a56073b 261 }
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263 /*!
AnnaBridge 143:86740a56073b 264 * @brief Sets the port PCR register for multiple pins.
AnnaBridge 143:86740a56073b 265 *
AnnaBridge 143:86740a56073b 266 * This is an example to define input pins or output pins PCR configuration.
AnnaBridge 143:86740a56073b 267 * @code
AnnaBridge 143:86740a56073b 268 * // Define a digital input pin PCR configuration
AnnaBridge 143:86740a56073b 269 * port_pin_config_t config = {
AnnaBridge 143:86740a56073b 270 * kPORT_PullUp ,
AnnaBridge 143:86740a56073b 271 * kPORT_PullEnable,
AnnaBridge 143:86740a56073b 272 * kPORT_FastSlewRate,
AnnaBridge 143:86740a56073b 273 * kPORT_PassiveFilterDisable,
AnnaBridge 143:86740a56073b 274 * kPORT_OpenDrainDisable,
AnnaBridge 143:86740a56073b 275 * kPORT_LowDriveStrength,
AnnaBridge 143:86740a56073b 276 * kPORT_MuxAsGpio,
AnnaBridge 143:86740a56073b 277 * kPORT_UnlockRegister,
AnnaBridge 143:86740a56073b 278 * };
AnnaBridge 143:86740a56073b 279 * @endcode
AnnaBridge 143:86740a56073b 280 *
AnnaBridge 143:86740a56073b 281 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 282 * @param mask PORT pin number macro.
AnnaBridge 143:86740a56073b 283 * @param config PORT PCR register configuration structure.
AnnaBridge 143:86740a56073b 284 */
AnnaBridge 143:86740a56073b 285 static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
AnnaBridge 143:86740a56073b 286 {
AnnaBridge 143:86740a56073b 287 assert(config);
AnnaBridge 143:86740a56073b 288
AnnaBridge 143:86740a56073b 289 uint16_t pcrl = *((const uint16_t *)config);
AnnaBridge 143:86740a56073b 290
AnnaBridge 143:86740a56073b 291 if (mask & 0xffffU)
AnnaBridge 143:86740a56073b 292 {
AnnaBridge 143:86740a56073b 293 base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
AnnaBridge 143:86740a56073b 294 }
AnnaBridge 143:86740a56073b 295 if (mask >> 16)
AnnaBridge 143:86740a56073b 296 {
AnnaBridge 143:86740a56073b 297 base->GPCHR = (mask & 0xffff0000U) | pcrl;
AnnaBridge 143:86740a56073b 298 }
AnnaBridge 143:86740a56073b 299 }
AnnaBridge 143:86740a56073b 300
AnnaBridge 143:86740a56073b 301 /*!
AnnaBridge 143:86740a56073b 302 * @brief Configures the pin muxing.
AnnaBridge 143:86740a56073b 303 *
AnnaBridge 143:86740a56073b 304 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 305 * @param pin PORT pin number.
AnnaBridge 143:86740a56073b 306 * @param mux pin muxing slot selection.
AnnaBridge 143:86740a56073b 307 * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
AnnaBridge 143:86740a56073b 308 * - #kPORT_MuxAsGpio : Set as GPIO.
AnnaBridge 143:86740a56073b 309 * - #kPORT_MuxAlt2 : chip-specific.
AnnaBridge 143:86740a56073b 310 * - #kPORT_MuxAlt3 : chip-specific.
AnnaBridge 143:86740a56073b 311 * - #kPORT_MuxAlt4 : chip-specific.
AnnaBridge 143:86740a56073b 312 * - #kPORT_MuxAlt5 : chip-specific.
AnnaBridge 143:86740a56073b 313 * - #kPORT_MuxAlt6 : chip-specific.
AnnaBridge 143:86740a56073b 314 * - #kPORT_MuxAlt7 : chip-specific.
AnnaBridge 143:86740a56073b 315 * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
AnnaBridge 143:86740a56073b 316 * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is
AnnaBridge 143:86740a56073b 317 * reset to zero : kPORT_PinDisabledOrAnalog).
AnnaBridge 143:86740a56073b 318 * This function is recommended to use to reset the pin mux
AnnaBridge 143:86740a56073b 319 *
AnnaBridge 143:86740a56073b 320 */
AnnaBridge 143:86740a56073b 321 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
AnnaBridge 143:86740a56073b 322 {
AnnaBridge 143:86740a56073b 323 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
AnnaBridge 143:86740a56073b 324 }
AnnaBridge 143:86740a56073b 325 #endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */
AnnaBridge 143:86740a56073b 326
AnnaBridge 143:86740a56073b 327 #if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
AnnaBridge 143:86740a56073b 328
AnnaBridge 143:86740a56073b 329 /*!
AnnaBridge 143:86740a56073b 330 * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
AnnaBridge 143:86740a56073b 331 *
AnnaBridge 143:86740a56073b 332 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 333 * @param mask PORT pin number macro.
AnnaBridge 143:86740a56073b 334 */
AnnaBridge 143:86740a56073b 335 static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
AnnaBridge 143:86740a56073b 336 {
AnnaBridge 143:86740a56073b 337 if (enable == true)
AnnaBridge 143:86740a56073b 338 {
AnnaBridge 143:86740a56073b 339 base->DFER |= mask;
AnnaBridge 143:86740a56073b 340 }
AnnaBridge 143:86740a56073b 341 else
AnnaBridge 143:86740a56073b 342 {
AnnaBridge 143:86740a56073b 343 base->DFER &= ~mask;
AnnaBridge 143:86740a56073b 344 }
AnnaBridge 143:86740a56073b 345 }
AnnaBridge 143:86740a56073b 346
AnnaBridge 143:86740a56073b 347 /*!
AnnaBridge 143:86740a56073b 348 * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
AnnaBridge 143:86740a56073b 349 *
AnnaBridge 143:86740a56073b 350 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 351 * @param config PORT digital filter configuration structure.
AnnaBridge 143:86740a56073b 352 */
AnnaBridge 143:86740a56073b 353 static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
AnnaBridge 143:86740a56073b 354 {
AnnaBridge 143:86740a56073b 355 assert(config);
AnnaBridge 143:86740a56073b 356
AnnaBridge 143:86740a56073b 357 base->DFCR = PORT_DFCR_CS(config->clockSource);
AnnaBridge 143:86740a56073b 358 base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
AnnaBridge 143:86740a56073b 359 }
AnnaBridge 143:86740a56073b 360
AnnaBridge 143:86740a56073b 361 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
AnnaBridge 143:86740a56073b 362
AnnaBridge 143:86740a56073b 363 /*@}*/
AnnaBridge 143:86740a56073b 364
AnnaBridge 143:86740a56073b 365 /*! @name Interrupt */
AnnaBridge 143:86740a56073b 366 /*@{*/
AnnaBridge 143:86740a56073b 367
AnnaBridge 143:86740a56073b 368 /*!
AnnaBridge 143:86740a56073b 369 * @brief Configures the port pin interrupt/DMA request.
AnnaBridge 143:86740a56073b 370 *
AnnaBridge 143:86740a56073b 371 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 372 * @param pin PORT pin number.
AnnaBridge 143:86740a56073b 373 * @param config PORT pin interrupt configuration.
AnnaBridge 143:86740a56073b 374 * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
AnnaBridge 143:86740a56073b 375 * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
AnnaBridge 143:86740a56073b 376 * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
AnnaBridge 143:86740a56073b 377 * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
AnnaBridge 143:86740a56073b 378 * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
AnnaBridge 143:86740a56073b 379 * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
AnnaBridge 143:86740a56073b 380 * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
AnnaBridge 143:86740a56073b 381 * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
AnnaBridge 143:86740a56073b 382 * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
AnnaBridge 143:86740a56073b 383 * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
AnnaBridge 143:86740a56073b 384 * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
AnnaBridge 143:86740a56073b 385 * - #kPORT_InterruptLogicOne : Interrupt when logic one.
AnnaBridge 143:86740a56073b 386 * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit).
AnnaBridge 143:86740a56073b 387 * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).
AnnaBridge 143:86740a56073b 388 */
AnnaBridge 143:86740a56073b 389 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
AnnaBridge 143:86740a56073b 390 {
AnnaBridge 143:86740a56073b 391 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
AnnaBridge 143:86740a56073b 392 }
AnnaBridge 143:86740a56073b 393
AnnaBridge 143:86740a56073b 394 /*!
AnnaBridge 143:86740a56073b 395 * @brief Reads the whole port status flag.
AnnaBridge 143:86740a56073b 396 *
AnnaBridge 143:86740a56073b 397 * If a pin is configured to generate the DMA request, the corresponding flag
AnnaBridge 143:86740a56073b 398 * is cleared automatically at the completion of the requested DMA transfer.
AnnaBridge 143:86740a56073b 399 * Otherwise, the flag remains set until a logic one is written to that flag.
AnnaBridge 143:86740a56073b 400 * If configured for a level sensitive interrupt that remains asserted, the flag
AnnaBridge 143:86740a56073b 401 * is set again immediately.
AnnaBridge 143:86740a56073b 402 *
AnnaBridge 143:86740a56073b 403 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 404 * @return Current port interrupt status flags, for example, 0x00010001 means the
AnnaBridge 143:86740a56073b 405 * pin 0 and 16 have the interrupt.
AnnaBridge 143:86740a56073b 406 */
AnnaBridge 143:86740a56073b 407 static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
AnnaBridge 143:86740a56073b 408 {
AnnaBridge 143:86740a56073b 409 return base->ISFR;
AnnaBridge 143:86740a56073b 410 }
AnnaBridge 143:86740a56073b 411
AnnaBridge 143:86740a56073b 412 /*!
AnnaBridge 143:86740a56073b 413 * @brief Clears the multiple pin interrupt status flag.
AnnaBridge 143:86740a56073b 414 *
AnnaBridge 143:86740a56073b 415 * @param base PORT peripheral base pointer.
AnnaBridge 143:86740a56073b 416 * @param mask PORT pin number macro.
AnnaBridge 143:86740a56073b 417 */
AnnaBridge 143:86740a56073b 418 static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
AnnaBridge 143:86740a56073b 419 {
AnnaBridge 143:86740a56073b 420 base->ISFR = mask;
AnnaBridge 143:86740a56073b 421 }
AnnaBridge 143:86740a56073b 422
AnnaBridge 143:86740a56073b 423 /*@}*/
AnnaBridge 143:86740a56073b 424
AnnaBridge 143:86740a56073b 425 #if defined(__cplusplus)
AnnaBridge 143:86740a56073b 426 }
AnnaBridge 143:86740a56073b 427 #endif
AnnaBridge 143:86740a56073b 428
AnnaBridge 143:86740a56073b 429 /*! @}*/
AnnaBridge 143:86740a56073b 430
AnnaBridge 143:86740a56073b 431 #endif /* _FSL_PORT_H_ */