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TARGET_EFM32PG_STK3401/TOOLCHAIN_IAR/efm32pg1b_devinfo.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32pg1b_devinfo.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32PG1B_DEVINFO register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32PG1B_DEVINFO |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 40 | |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IM uint32_t CAL; /**< CRC of DI-page and calibration temperature */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | uint32_t RESERVED0[9]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t EUI48L; /**< EUI48 OUI and Unique identifier */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IM uint32_t EUI48H; /**< OUI */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IM uint32_t CUSTOMINFO; /**< Custom information */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IM uint32_t MEMINFO; /**< Flash page size and misc. chip information */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IM uint32_t UNIQUEL; /**< Low 32 bits of device unique number */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IM uint32_t UNIQUEH; /**< High 32 bits of device unique number */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IM uint32_t MSIZE; /**< Flash and SRAM Memory size in kB */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IM uint32_t PART; /**< Part description */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IM uint32_t DEVINFOREV; /**< Device information page revision */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IM uint32_t EMUTEMP; /**< EMU Temperature Calibration Information */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | uint32_t RESERVED2[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 57 | __IM uint32_t ADC0CAL0; /**< ADC0 calibration register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IM uint32_t ADC0CAL1; /**< ADC0 calibration register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IM uint32_t ADC0CAL2; /**< ADC0 calibration register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IM uint32_t ADC0CAL3; /**< ADC0 calibration register 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | uint32_t RESERVED3[4]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 62 | __IM uint32_t HFRCOCAL0; /**< HFRCO Calibration Register (4 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | uint32_t RESERVED4[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 64 | __IM uint32_t HFRCOCAL3; /**< HFRCO Calibration Register (7 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t RESERVED5[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IM uint32_t HFRCOCAL6; /**< HFRCO Calibration Register (13 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IM uint32_t HFRCOCAL7; /**< HFRCO Calibration Register (16 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | __IM uint32_t HFRCOCAL8; /**< HFRCO Calibration Register (19 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t RESERVED6[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 70 | __IM uint32_t HFRCOCAL10; /**< HFRCO Calibration Register (26 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | __IM uint32_t HFRCOCAL11; /**< HFRCO Calibration Register (32 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | __IM uint32_t HFRCOCAL12; /**< HFRCO Calibration Register (38 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | uint32_t RESERVED7[11]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 74 | __IM uint32_t AUXHFRCOCAL0; /**< AUXHFRCO Calibration Register (4 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | uint32_t RESERVED8[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 76 | __IM uint32_t AUXHFRCOCAL3; /**< AUXHFRCO Calibration Register (7 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | uint32_t RESERVED9[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 78 | __IM uint32_t AUXHFRCOCAL6; /**< AUXHFRCO Calibration Register (13 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | __IM uint32_t AUXHFRCOCAL7; /**< AUXHFRCO Calibration Register (16 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | __IM uint32_t AUXHFRCOCAL8; /**< AUXHFRCO Calibration Register (19 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | uint32_t RESERVED10[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 82 | __IM uint32_t AUXHFRCOCAL10; /**< AUXHFRCO Calibration Register (26 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | __IM uint32_t AUXHFRCOCAL11; /**< AUXHFRCO Calibration Register (32 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | __IM uint32_t AUXHFRCOCAL12; /**< AUXHFRCO Calibration Register (38 MHz) */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t RESERVED11[11]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 86 | __IM uint32_t VMONCAL0; /**< VMON Calibration Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | __IM uint32_t VMONCAL1; /**< VMON Calibration Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | __IM uint32_t VMONCAL2; /**< VMON Calibration Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t RESERVED12[3]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 90 | __IM uint32_t IDAC0CAL0; /**< IDAC0 Calibration Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | __IM uint32_t IDAC0CAL1; /**< IDAC0 Calibration Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t RESERVED13[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 93 | __IM uint32_t DCDCLNVCTRL0; /**< DCDC Low-noise VREF Trim Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | __IM uint32_t DCDCLPVCTRL0; /**< DCDC Low-power VREF Trim Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | __IM uint32_t DCDCLPVCTRL1; /**< DCDC Low-power VREF Trim Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | __IM uint32_t DCDCLPVCTRL2; /**< DCDC Low-power VREF Trim Register 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | __IM uint32_t DCDCLPVCTRL3; /**< DCDC Low-power VREF Trim Register 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | __IM uint32_t DCDCLPCMPHYSSEL0; /**< DCDC LPCMPHYSSEL Trim Register 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | __IM uint32_t DCDCLPCMPHYSSEL1; /**< DCDC LPCMPHYSSEL Trim Register 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | } DEVINFO_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | |
| AnnaBridge | 171:3a7713b1edbc | 102 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 103 | * @defgroup EFM32PG1B_DEVINFO_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 104 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 105 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 106 | |
| AnnaBridge | 171:3a7713b1edbc | 107 | /* Bit fields for DEVINFO CAL */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define _DEVINFO_CAL_MASK 0x00FFFFFFUL /**< Mask for DEVINFO_CAL */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define _DEVINFO_CAL_CRC_SHIFT 0 /**< Shift value for CRC */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define _DEVINFO_CAL_CRC_MASK 0xFFFFUL /**< Bit mask for CRC */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define _DEVINFO_CAL_TEMP_SHIFT 16 /**< Shift value for TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define _DEVINFO_CAL_TEMP_MASK 0xFF0000UL /**< Bit mask for TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | |
| AnnaBridge | 171:3a7713b1edbc | 114 | /* Bit fields for DEVINFO EUI48L */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define _DEVINFO_EUI48L_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_EUI48L */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define _DEVINFO_EUI48L_UNIQUEID_SHIFT 0 /**< Shift value for UNIQUEID */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define _DEVINFO_EUI48L_UNIQUEID_MASK 0xFFFFFFUL /**< Bit mask for UNIQUEID */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define _DEVINFO_EUI48L_OUI48L_SHIFT 24 /**< Shift value for OUI48L */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define _DEVINFO_EUI48L_OUI48L_MASK 0xFF000000UL /**< Bit mask for OUI48L */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | |
| AnnaBridge | 171:3a7713b1edbc | 121 | /* Bit fields for DEVINFO EUI48H */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _DEVINFO_EUI48H_MASK 0x0000FFFFUL /**< Mask for DEVINFO_EUI48H */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _DEVINFO_EUI48H_OUI48H_SHIFT 0 /**< Shift value for OUI48H */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _DEVINFO_EUI48H_OUI48H_MASK 0xFFFFUL /**< Bit mask for OUI48H */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | |
| AnnaBridge | 171:3a7713b1edbc | 126 | /* Bit fields for DEVINFO CUSTOMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define _DEVINFO_CUSTOMINFO_MASK 0xFFFF0000UL /**< Mask for DEVINFO_CUSTOMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define _DEVINFO_CUSTOMINFO_PARTNO_SHIFT 16 /**< Shift value for PARTNO */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define _DEVINFO_CUSTOMINFO_PARTNO_MASK 0xFFFF0000UL /**< Bit mask for PARTNO */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | |
| AnnaBridge | 171:3a7713b1edbc | 131 | /* Bit fields for DEVINFO MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define _DEVINFO_MEMINFO_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define _DEVINFO_MEMINFO_TEMPGRADE_SHIFT 0 /**< Shift value for TEMPGRADE */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define _DEVINFO_MEMINFO_TEMPGRADE_MASK 0xFFUL /**< Bit mask for TEMPGRADE */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO85 0x00000000UL /**< Mode N40TO85 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO125 0x00000001UL /**< Mode N40TO125 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _DEVINFO_MEMINFO_TEMPGRADE_N40TO105 0x00000002UL /**< Mode N40TO105 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define _DEVINFO_MEMINFO_TEMPGRADE_N0TO70 0x00000003UL /**< Mode N0TO70 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define DEVINFO_MEMINFO_TEMPGRADE_N40TO85 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO85 << 0) /**< Shifted mode N40TO85 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define DEVINFO_MEMINFO_TEMPGRADE_N40TO125 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO125 << 0) /**< Shifted mode N40TO125 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define DEVINFO_MEMINFO_TEMPGRADE_N40TO105 (_DEVINFO_MEMINFO_TEMPGRADE_N40TO105 << 0) /**< Shifted mode N40TO105 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define DEVINFO_MEMINFO_TEMPGRADE_N0TO70 (_DEVINFO_MEMINFO_TEMPGRADE_N0TO70 << 0) /**< Shifted mode N0TO70 for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define _DEVINFO_MEMINFO_PKGTYPE_SHIFT 8 /**< Shift value for PKGTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define _DEVINFO_MEMINFO_PKGTYPE_MASK 0xFF00UL /**< Bit mask for PKGTYPE */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define _DEVINFO_MEMINFO_PKGTYPE_WLCSP 0x0000004AUL /**< Mode WLCSP for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define _DEVINFO_MEMINFO_PKGTYPE_QFN 0x0000004DUL /**< Mode QFN for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define _DEVINFO_MEMINFO_PKGTYPE_QFP 0x00000051UL /**< Mode QFP for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define DEVINFO_MEMINFO_PKGTYPE_WLCSP (_DEVINFO_MEMINFO_PKGTYPE_WLCSP << 8) /**< Shifted mode WLCSP for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define DEVINFO_MEMINFO_PKGTYPE_QFN (_DEVINFO_MEMINFO_PKGTYPE_QFN << 8) /**< Shifted mode QFN for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define DEVINFO_MEMINFO_PKGTYPE_QFP (_DEVINFO_MEMINFO_PKGTYPE_QFP << 8) /**< Shifted mode QFP for DEVINFO_MEMINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define _DEVINFO_MEMINFO_PINCOUNT_SHIFT 16 /**< Shift value for PINCOUNT */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define _DEVINFO_MEMINFO_PINCOUNT_MASK 0xFF0000UL /**< Bit mask for PINCOUNT */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT 24 /**< Shift value for FLASH_PAGE_SIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK 0xFF000000UL /**< Bit mask for FLASH_PAGE_SIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | |
| AnnaBridge | 171:3a7713b1edbc | 156 | /* Bit fields for DEVINFO UNIQUEL */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define _DEVINFO_UNIQUEL_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEL */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define _DEVINFO_UNIQUEL_UNIQUEL_SHIFT 0 /**< Shift value for UNIQUEL */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define _DEVINFO_UNIQUEL_UNIQUEL_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEL */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | |
| AnnaBridge | 171:3a7713b1edbc | 161 | /* Bit fields for DEVINFO UNIQUEH */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_UNIQUEH */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define _DEVINFO_UNIQUEH_UNIQUEH_SHIFT 0 /**< Shift value for UNIQUEH */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define _DEVINFO_UNIQUEH_UNIQUEH_MASK 0xFFFFFFFFUL /**< Bit mask for UNIQUEH */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | |
| AnnaBridge | 171:3a7713b1edbc | 166 | /* Bit fields for DEVINFO MSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define _DEVINFO_MSIZE_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_MSIZE */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define _DEVINFO_MSIZE_FLASH_SHIFT 0 /**< Shift value for FLASH */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define _DEVINFO_MSIZE_FLASH_MASK 0xFFFFUL /**< Bit mask for FLASH */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define _DEVINFO_MSIZE_SRAM_SHIFT 16 /**< Shift value for SRAM */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /**< Bit mask for SRAM */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | |
| AnnaBridge | 171:3a7713b1edbc | 173 | /* Bit fields for DEVINFO PART */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define _DEVINFO_PART_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT 0 /**< Shift value for DEVICE_NUMBER */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define _DEVINFO_PART_DEVICE_NUMBER_MASK 0xFFFFUL /**< Bit mask for DEVICE_NUMBER */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT 16 /**< Shift value for DEVICE_FAMILY */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define _DEVINFO_PART_DEVICE_FAMILY_MASK 0xFF0000UL /**< Bit mask for DEVICE_FAMILY */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P 0x00000010UL /**< Mode EFR32MG1P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B 0x00000011UL /**< Mode EFR32MG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V 0x00000012UL /**< Mode EFR32MG1V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P 0x00000013UL /**< Mode EFR32BG1P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B 0x00000014UL /**< Mode EFR32BG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V 0x00000015UL /**< Mode EFR32BG1V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P 0x00000019UL /**< Mode EFR32FG1P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B 0x0000001AUL /**< Mode EFR32FG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V 0x0000001BUL /**< Mode EFR32FG1V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P 0x0000001CUL /**< Mode EFR32MG12P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P 0x0000001CUL /**< Mode EFR32MG2P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B 0x0000001DUL /**< Mode EFR32MG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V 0x0000001EUL /**< Mode EFR32MG12V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P 0x0000001FUL /**< Mode EFR32BG12P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B 0x00000020UL /**< Mode EFR32BG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V 0x00000021UL /**< Mode EFR32BG12V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P 0x00000025UL /**< Mode EFR32FG12P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B 0x00000026UL /**< Mode EFR32FG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V 0x00000027UL /**< Mode EFR32FG12V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P 0x00000028UL /**< Mode EFR32MG13P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B 0x00000029UL /**< Mode EFR32MG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V 0x0000002AUL /**< Mode EFR32MG13V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P 0x0000002BUL /**< Mode EFR32BG13P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B 0x0000002CUL /**< Mode EFR32BG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V 0x0000002DUL /**< Mode EFR32BG13V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P 0x00000031UL /**< Mode EFR32FG13P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B 0x00000032UL /**< Mode EFR32FG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define _DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V 0x00000033UL /**< Mode EFR32FG13V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G 0x00000047UL /**< Mode EFM32G for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define _DEVINFO_PART_DEVICE_FAMILY_G 0x00000047UL /**< Mode G for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG 0x00000048UL /**< Mode EFM32GG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define _DEVINFO_PART_DEVICE_FAMILY_GG 0x00000048UL /**< Mode GG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define _DEVINFO_PART_DEVICE_FAMILY_TG 0x00000049UL /**< Mode TG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG 0x00000049UL /**< Mode EFM32TG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG 0x0000004AUL /**< Mode EFM32LG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define _DEVINFO_PART_DEVICE_FAMILY_LG 0x0000004AUL /**< Mode LG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG 0x0000004BUL /**< Mode EFM32WG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define _DEVINFO_PART_DEVICE_FAMILY_WG 0x0000004BUL /**< Mode WG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define _DEVINFO_PART_DEVICE_FAMILY_ZG 0x0000004CUL /**< Mode ZG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG 0x0000004CUL /**< Mode EFM32ZG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define _DEVINFO_PART_DEVICE_FAMILY_HG 0x0000004DUL /**< Mode HG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG 0x0000004DUL /**< Mode EFM32HG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B 0x00000051UL /**< Mode EFM32PG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B 0x00000053UL /**< Mode EFM32JG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B 0x00000055UL /**< Mode EFM32PG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B 0x00000057UL /**< Mode EFM32JG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B 0x00000059UL /**< Mode EFM32PG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define _DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B 0x0000005BUL /**< Mode EFM32JG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG 0x00000078UL /**< Mode EZR32LG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG 0x00000079UL /**< Mode EZR32WG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG 0x0000007AUL /**< Mode EZR32HG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1P << 16) /**< Shifted mode EFR32MG1P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1B << 16) /**< Shifted mode EFR32MG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG1V << 16) /**< Shifted mode EFR32MG1V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1P << 16) /**< Shifted mode EFR32BG1P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1B << 16) /**< Shifted mode EFR32BG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG1V << 16) /**< Shifted mode EFR32BG1V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1P << 16) /**< Shifted mode EFR32FG1P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1B << 16) /**< Shifted mode EFR32FG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG1V << 16) /**< Shifted mode EFR32FG1V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12P << 16) /**< Shifted mode EFR32MG12P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG2P << 16) /**< Shifted mode EFR32MG2P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12B << 16) /**< Shifted mode EFR32MG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG12V << 16) /**< Shifted mode EFR32MG12V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12P << 16) /**< Shifted mode EFR32BG12P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12B << 16) /**< Shifted mode EFR32BG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG12V << 16) /**< Shifted mode EFR32BG12V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12P << 16) /**< Shifted mode EFR32FG12P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12B << 16) /**< Shifted mode EFR32FG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG12V << 16) /**< Shifted mode EFR32FG12V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13P << 16) /**< Shifted mode EFR32MG13P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13B << 16) /**< Shifted mode EFR32MG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32MG13V << 16) /**< Shifted mode EFR32MG13V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13P << 16) /**< Shifted mode EFR32BG13P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13B << 16) /**< Shifted mode EFR32BG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32BG13V << 16) /**< Shifted mode EFR32BG13V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13P << 16) /**< Shifted mode EFR32FG13P for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13B << 16) /**< Shifted mode EFR32FG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V (_DEVINFO_PART_DEVICE_FAMILY_EFR32FG13V << 16) /**< Shifted mode EFR32FG13V for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32G (_DEVINFO_PART_DEVICE_FAMILY_EFM32G << 16) /**< Shifted mode EFM32G for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define DEVINFO_PART_DEVICE_FAMILY_G (_DEVINFO_PART_DEVICE_FAMILY_G << 16) /**< Shifted mode G for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32GG (_DEVINFO_PART_DEVICE_FAMILY_EFM32GG << 16) /**< Shifted mode EFM32GG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define DEVINFO_PART_DEVICE_FAMILY_GG (_DEVINFO_PART_DEVICE_FAMILY_GG << 16) /**< Shifted mode GG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define DEVINFO_PART_DEVICE_FAMILY_TG (_DEVINFO_PART_DEVICE_FAMILY_TG << 16) /**< Shifted mode TG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32TG (_DEVINFO_PART_DEVICE_FAMILY_EFM32TG << 16) /**< Shifted mode EFM32TG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32LG (_DEVINFO_PART_DEVICE_FAMILY_EFM32LG << 16) /**< Shifted mode EFM32LG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define DEVINFO_PART_DEVICE_FAMILY_LG (_DEVINFO_PART_DEVICE_FAMILY_LG << 16) /**< Shifted mode LG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32WG (_DEVINFO_PART_DEVICE_FAMILY_EFM32WG << 16) /**< Shifted mode EFM32WG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define DEVINFO_PART_DEVICE_FAMILY_WG (_DEVINFO_PART_DEVICE_FAMILY_WG << 16) /**< Shifted mode WG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define DEVINFO_PART_DEVICE_FAMILY_ZG (_DEVINFO_PART_DEVICE_FAMILY_ZG << 16) /**< Shifted mode ZG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32ZG (_DEVINFO_PART_DEVICE_FAMILY_EFM32ZG << 16) /**< Shifted mode EFM32ZG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define DEVINFO_PART_DEVICE_FAMILY_HG (_DEVINFO_PART_DEVICE_FAMILY_HG << 16) /**< Shifted mode HG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32HG (_DEVINFO_PART_DEVICE_FAMILY_EFM32HG << 16) /**< Shifted mode EFM32HG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG1B << 16) /**< Shifted mode EFM32PG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG1B << 16) /**< Shifted mode EFM32JG1B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG12B << 16) /**< Shifted mode EFM32PG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG12B << 16) /**< Shifted mode EFM32JG12B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32PG13B << 16) /**< Shifted mode EFM32PG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B (_DEVINFO_PART_DEVICE_FAMILY_EFM32JG13B << 16) /**< Shifted mode EFM32JG13B for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define DEVINFO_PART_DEVICE_FAMILY_EZR32LG (_DEVINFO_PART_DEVICE_FAMILY_EZR32LG << 16) /**< Shifted mode EZR32LG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define DEVINFO_PART_DEVICE_FAMILY_EZR32WG (_DEVINFO_PART_DEVICE_FAMILY_EZR32WG << 16) /**< Shifted mode EZR32WG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define DEVINFO_PART_DEVICE_FAMILY_EZR32HG (_DEVINFO_PART_DEVICE_FAMILY_EZR32HG << 16) /**< Shifted mode EZR32HG for DEVINFO_PART */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define _DEVINFO_PART_PROD_REV_SHIFT 24 /**< Shift value for PROD_REV */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /**< Bit mask for PROD_REV */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | |
| AnnaBridge | 171:3a7713b1edbc | 284 | /* Bit fields for DEVINFO DEVINFOREV */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define _DEVINFO_DEVINFOREV_MASK 0x000000FFUL /**< Mask for DEVINFO_DEVINFOREV */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define _DEVINFO_DEVINFOREV_DEVINFOREV_SHIFT 0 /**< Shift value for DEVINFOREV */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define _DEVINFO_DEVINFOREV_DEVINFOREV_MASK 0xFFUL /**< Bit mask for DEVINFOREV */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | |
| AnnaBridge | 171:3a7713b1edbc | 289 | /* Bit fields for DEVINFO EMUTEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define _DEVINFO_EMUTEMP_MASK 0x000000FFUL /**< Mask for DEVINFO_EMUTEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define _DEVINFO_EMUTEMP_EMUTEMPROOM_SHIFT 0 /**< Shift value for EMUTEMPROOM */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define _DEVINFO_EMUTEMP_EMUTEMPROOM_MASK 0xFFUL /**< Bit mask for EMUTEMPROOM */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | |
| AnnaBridge | 171:3a7713b1edbc | 294 | /* Bit fields for DEVINFO ADC0CAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define _DEVINFO_ADC0CAL0_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT 0 /**< Shift value for OFFSET1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define _DEVINFO_ADC0CAL0_OFFSET1V25_MASK 0xFUL /**< Bit mask for OFFSET1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT 4 /**< Shift value for NEGSEOFFSET1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT 8 /**< Shift value for GAIN1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define _DEVINFO_ADC0CAL0_GAIN1V25_MASK 0x7F00UL /**< Bit mask for GAIN1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT 16 /**< Shift value for OFFSET2V5 */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define _DEVINFO_ADC0CAL0_OFFSET2V5_MASK 0xF0000UL /**< Bit mask for OFFSET2V5 */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT 20 /**< Shift value for NEGSEOFFSET2V5 */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET2V5 */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT 24 /**< Shift value for GAIN2V5 */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define _DEVINFO_ADC0CAL0_GAIN2V5_MASK 0x7F000000UL /**< Bit mask for GAIN2V5 */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | |
| AnnaBridge | 171:3a7713b1edbc | 309 | /* Bit fields for DEVINFO ADC0CAL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _DEVINFO_ADC0CAL1_MASK 0x7FFF7FFFUL /**< Mask for DEVINFO_ADC0CAL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT 0 /**< Shift value for OFFSETVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define _DEVINFO_ADC0CAL1_OFFSETVDD_MASK 0xFUL /**< Bit mask for OFFSETVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT 4 /**< Shift value for NEGSEOFFSETVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSETVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define _DEVINFO_ADC0CAL1_GAINVDD_SHIFT 8 /**< Shift value for GAINVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define _DEVINFO_ADC0CAL1_GAINVDD_MASK 0x7F00UL /**< Bit mask for GAINVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT 16 /**< Shift value for OFFSET5VDIFF */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK 0xF0000UL /**< Bit mask for OFFSET5VDIFF */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT 20 /**< Shift value for NEGSEOFFSET5VDIFF */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK 0xF00000UL /**< Bit mask for NEGSEOFFSET5VDIFF */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT 24 /**< Shift value for GAIN5VDIFF */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK 0x7F000000UL /**< Bit mask for GAIN5VDIFF */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | /* Bit fields for DEVINFO ADC0CAL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define _DEVINFO_ADC0CAL2_MASK 0x000000FFUL /**< Mask for DEVINFO_ADC0CAL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT 0 /**< Shift value for OFFSET2XVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK 0xFUL /**< Bit mask for OFFSET2XVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT 4 /**< Shift value for NEGSEOFFSET2XVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK 0xF0UL /**< Bit mask for NEGSEOFFSET2XVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | |
| AnnaBridge | 171:3a7713b1edbc | 331 | /* Bit fields for DEVINFO ADC0CAL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define _DEVINFO_ADC0CAL3_MASK 0x0000FFF0UL /**< Mask for DEVINFO_ADC0CAL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_SHIFT 4 /**< Shift value for TEMPREAD1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _DEVINFO_ADC0CAL3_TEMPREAD1V25_MASK 0xFFF0UL /**< Bit mask for TEMPREAD1V25 */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | |
| AnnaBridge | 171:3a7713b1edbc | 336 | /* Bit fields for DEVINFO HFRCOCAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define _DEVINFO_HFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define _DEVINFO_HFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define _DEVINFO_HFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define _DEVINFO_HFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define _DEVINFO_HFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define _DEVINFO_HFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define _DEVINFO_HFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _DEVINFO_HFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _DEVINFO_HFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define _DEVINFO_HFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define _DEVINFO_HFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define _DEVINFO_HFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define _DEVINFO_HFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _DEVINFO_HFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define _DEVINFO_HFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define _DEVINFO_HFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | |
| AnnaBridge | 171:3a7713b1edbc | 355 | /* Bit fields for DEVINFO HFRCOCAL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define _DEVINFO_HFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define _DEVINFO_HFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define _DEVINFO_HFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define _DEVINFO_HFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _DEVINFO_HFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _DEVINFO_HFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define _DEVINFO_HFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define _DEVINFO_HFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define _DEVINFO_HFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define _DEVINFO_HFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define _DEVINFO_HFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define _DEVINFO_HFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define _DEVINFO_HFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define _DEVINFO_HFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _DEVINFO_HFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define _DEVINFO_HFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | |
| AnnaBridge | 171:3a7713b1edbc | 374 | /* Bit fields for DEVINFO HFRCOCAL6 */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define _DEVINFO_HFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL6 */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define _DEVINFO_HFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define _DEVINFO_HFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define _DEVINFO_HFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define _DEVINFO_HFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define _DEVINFO_HFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define _DEVINFO_HFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define _DEVINFO_HFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define _DEVINFO_HFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define _DEVINFO_HFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define _DEVINFO_HFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define _DEVINFO_HFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define _DEVINFO_HFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define _DEVINFO_HFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _DEVINFO_HFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define _DEVINFO_HFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | |
| AnnaBridge | 171:3a7713b1edbc | 393 | /* Bit fields for DEVINFO HFRCOCAL7 */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define _DEVINFO_HFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL7 */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _DEVINFO_HFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define _DEVINFO_HFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define _DEVINFO_HFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define _DEVINFO_HFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define _DEVINFO_HFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define _DEVINFO_HFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define _DEVINFO_HFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define _DEVINFO_HFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define _DEVINFO_HFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define _DEVINFO_HFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define _DEVINFO_HFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define _DEVINFO_HFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define _DEVINFO_HFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define _DEVINFO_HFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define _DEVINFO_HFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | |
| AnnaBridge | 171:3a7713b1edbc | 412 | /* Bit fields for DEVINFO HFRCOCAL8 */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define _DEVINFO_HFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL8 */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define _DEVINFO_HFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define _DEVINFO_HFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define _DEVINFO_HFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define _DEVINFO_HFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define _DEVINFO_HFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define _DEVINFO_HFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define _DEVINFO_HFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define _DEVINFO_HFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define _DEVINFO_HFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define _DEVINFO_HFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define _DEVINFO_HFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define _DEVINFO_HFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define _DEVINFO_HFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define _DEVINFO_HFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define _DEVINFO_HFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | |
| AnnaBridge | 171:3a7713b1edbc | 431 | /* Bit fields for DEVINFO HFRCOCAL10 */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define _DEVINFO_HFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL10 */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define _DEVINFO_HFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define _DEVINFO_HFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define _DEVINFO_HFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define _DEVINFO_HFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define _DEVINFO_HFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define _DEVINFO_HFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define _DEVINFO_HFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define _DEVINFO_HFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define _DEVINFO_HFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define _DEVINFO_HFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define _DEVINFO_HFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define _DEVINFO_HFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define _DEVINFO_HFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define _DEVINFO_HFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define _DEVINFO_HFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | |
| AnnaBridge | 171:3a7713b1edbc | 450 | /* Bit fields for DEVINFO HFRCOCAL11 */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define _DEVINFO_HFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL11 */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define _DEVINFO_HFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define _DEVINFO_HFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define _DEVINFO_HFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define _DEVINFO_HFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define _DEVINFO_HFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define _DEVINFO_HFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define _DEVINFO_HFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define _DEVINFO_HFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define _DEVINFO_HFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define _DEVINFO_HFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define _DEVINFO_HFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define _DEVINFO_HFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define _DEVINFO_HFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define _DEVINFO_HFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define _DEVINFO_HFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | |
| AnnaBridge | 171:3a7713b1edbc | 469 | /* Bit fields for DEVINFO HFRCOCAL12 */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define _DEVINFO_HFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_HFRCOCAL12 */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define _DEVINFO_HFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define _DEVINFO_HFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define _DEVINFO_HFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define _DEVINFO_HFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define _DEVINFO_HFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define _DEVINFO_HFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define _DEVINFO_HFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define _DEVINFO_HFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define _DEVINFO_HFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define _DEVINFO_HFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define _DEVINFO_HFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define _DEVINFO_HFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define _DEVINFO_HFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define _DEVINFO_HFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define _DEVINFO_HFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | |
| AnnaBridge | 171:3a7713b1edbc | 488 | /* Bit fields for DEVINFO AUXHFRCOCAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define _DEVINFO_AUXHFRCOCAL0_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define _DEVINFO_AUXHFRCOCAL0_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define _DEVINFO_AUXHFRCOCAL0_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define _DEVINFO_AUXHFRCOCAL0_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define _DEVINFO_AUXHFRCOCAL0_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define _DEVINFO_AUXHFRCOCAL0_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define _DEVINFO_AUXHFRCOCAL0_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define _DEVINFO_AUXHFRCOCAL0_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define _DEVINFO_AUXHFRCOCAL0_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define _DEVINFO_AUXHFRCOCAL0_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define _DEVINFO_AUXHFRCOCAL0_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | |
| AnnaBridge | 171:3a7713b1edbc | 507 | /* Bit fields for DEVINFO AUXHFRCOCAL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define _DEVINFO_AUXHFRCOCAL3_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define _DEVINFO_AUXHFRCOCAL3_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define _DEVINFO_AUXHFRCOCAL3_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define _DEVINFO_AUXHFRCOCAL3_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | #define _DEVINFO_AUXHFRCOCAL3_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define _DEVINFO_AUXHFRCOCAL3_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define _DEVINFO_AUXHFRCOCAL3_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define _DEVINFO_AUXHFRCOCAL3_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define _DEVINFO_AUXHFRCOCAL3_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define _DEVINFO_AUXHFRCOCAL3_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define _DEVINFO_AUXHFRCOCAL3_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | |
| AnnaBridge | 171:3a7713b1edbc | 526 | /* Bit fields for DEVINFO AUXHFRCOCAL6 */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define _DEVINFO_AUXHFRCOCAL6_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL6 */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define _DEVINFO_AUXHFRCOCAL6_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define _DEVINFO_AUXHFRCOCAL6_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define _DEVINFO_AUXHFRCOCAL6_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define _DEVINFO_AUXHFRCOCAL6_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define _DEVINFO_AUXHFRCOCAL6_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | #define _DEVINFO_AUXHFRCOCAL6_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define _DEVINFO_AUXHFRCOCAL6_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define _DEVINFO_AUXHFRCOCAL6_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define _DEVINFO_AUXHFRCOCAL6_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define _DEVINFO_AUXHFRCOCAL6_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | |
| AnnaBridge | 171:3a7713b1edbc | 545 | /* Bit fields for DEVINFO AUXHFRCOCAL7 */ |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define _DEVINFO_AUXHFRCOCAL7_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL7 */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define _DEVINFO_AUXHFRCOCAL7_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define _DEVINFO_AUXHFRCOCAL7_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define _DEVINFO_AUXHFRCOCAL7_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define _DEVINFO_AUXHFRCOCAL7_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define _DEVINFO_AUXHFRCOCAL7_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define _DEVINFO_AUXHFRCOCAL7_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define _DEVINFO_AUXHFRCOCAL7_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define _DEVINFO_AUXHFRCOCAL7_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define _DEVINFO_AUXHFRCOCAL7_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define _DEVINFO_AUXHFRCOCAL7_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | |
| AnnaBridge | 171:3a7713b1edbc | 564 | /* Bit fields for DEVINFO AUXHFRCOCAL8 */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define _DEVINFO_AUXHFRCOCAL8_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL8 */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define _DEVINFO_AUXHFRCOCAL8_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define _DEVINFO_AUXHFRCOCAL8_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define _DEVINFO_AUXHFRCOCAL8_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define _DEVINFO_AUXHFRCOCAL8_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define _DEVINFO_AUXHFRCOCAL8_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define _DEVINFO_AUXHFRCOCAL8_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define _DEVINFO_AUXHFRCOCAL8_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define _DEVINFO_AUXHFRCOCAL8_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define _DEVINFO_AUXHFRCOCAL8_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define _DEVINFO_AUXHFRCOCAL8_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | |
| AnnaBridge | 171:3a7713b1edbc | 583 | /* Bit fields for DEVINFO AUXHFRCOCAL10 */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | #define _DEVINFO_AUXHFRCOCAL10_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL10 */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define _DEVINFO_AUXHFRCOCAL10_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define _DEVINFO_AUXHFRCOCAL10_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define _DEVINFO_AUXHFRCOCAL10_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define _DEVINFO_AUXHFRCOCAL10_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define _DEVINFO_AUXHFRCOCAL10_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define _DEVINFO_AUXHFRCOCAL10_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define _DEVINFO_AUXHFRCOCAL10_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define _DEVINFO_AUXHFRCOCAL10_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | #define _DEVINFO_AUXHFRCOCAL10_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define _DEVINFO_AUXHFRCOCAL10_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | |
| AnnaBridge | 171:3a7713b1edbc | 602 | /* Bit fields for DEVINFO AUXHFRCOCAL11 */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define _DEVINFO_AUXHFRCOCAL11_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL11 */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define _DEVINFO_AUXHFRCOCAL11_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define _DEVINFO_AUXHFRCOCAL11_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define _DEVINFO_AUXHFRCOCAL11_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define _DEVINFO_AUXHFRCOCAL11_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define _DEVINFO_AUXHFRCOCAL11_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define _DEVINFO_AUXHFRCOCAL11_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define _DEVINFO_AUXHFRCOCAL11_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define _DEVINFO_AUXHFRCOCAL11_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define _DEVINFO_AUXHFRCOCAL11_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define _DEVINFO_AUXHFRCOCAL11_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | |
| AnnaBridge | 171:3a7713b1edbc | 621 | /* Bit fields for DEVINFO AUXHFRCOCAL12 */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define _DEVINFO_AUXHFRCOCAL12_MASK 0xFFFF3F7FUL /**< Mask for DEVINFO_AUXHFRCOCAL12 */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define _DEVINFO_AUXHFRCOCAL12_TUNING_SHIFT 0 /**< Shift value for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define _DEVINFO_AUXHFRCOCAL12_TUNING_MASK 0x7FUL /**< Bit mask for TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_SHIFT 8 /**< Shift value for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNING_MASK 0x3F00UL /**< Bit mask for FINETUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_SHIFT 16 /**< Shift value for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define _DEVINFO_AUXHFRCOCAL12_FREQRANGE_MASK 0x1F0000UL /**< Bit mask for FREQRANGE */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_SHIFT 21 /**< Shift value for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define _DEVINFO_AUXHFRCOCAL12_CMPBIAS_MASK 0xE00000UL /**< Bit mask for CMPBIAS */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define _DEVINFO_AUXHFRCOCAL12_LDOHP_SHIFT 24 /**< Shift value for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define _DEVINFO_AUXHFRCOCAL12_LDOHP_MASK 0x1000000UL /**< Bit mask for LDOHP */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_SHIFT 25 /**< Shift value for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define _DEVINFO_AUXHFRCOCAL12_CLKDIV_MASK 0x6000000UL /**< Bit mask for CLKDIV */ |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_SHIFT 27 /**< Shift value for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define _DEVINFO_AUXHFRCOCAL12_FINETUNINGEN_MASK 0x8000000UL /**< Bit mask for FINETUNINGEN */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define _DEVINFO_AUXHFRCOCAL12_VREFTC_SHIFT 28 /**< Shift value for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define _DEVINFO_AUXHFRCOCAL12_VREFTC_MASK 0xF0000000UL /**< Bit mask for VREFTC */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | |
| AnnaBridge | 171:3a7713b1edbc | 640 | /* Bit fields for DEVINFO VMONCAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | #define _DEVINFO_VMONCAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_SHIFT 0 /**< Shift value for AVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for AVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for AVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define _DEVINFO_VMONCAL0_AVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for AVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_SHIFT 8 /**< Shift value for AVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for AVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for AVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define _DEVINFO_VMONCAL0_AVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for AVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_SHIFT 16 /**< Shift value for ALTAVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for ALTAVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for ALTAVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 653 | #define _DEVINFO_VMONCAL0_ALTAVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for ALTAVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_SHIFT 24 /**< Shift value for ALTAVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for ALTAVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for ALTAVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 657 | #define _DEVINFO_VMONCAL0_ALTAVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for ALTAVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | |
| AnnaBridge | 171:3a7713b1edbc | 659 | /* Bit fields for DEVINFO VMONCAL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define _DEVINFO_VMONCAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_SHIFT 0 /**< Shift value for DVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for DVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for DVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define _DEVINFO_VMONCAL1_DVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for DVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_SHIFT 8 /**< Shift value for DVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for DVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for DVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define _DEVINFO_VMONCAL1_DVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for DVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_SHIFT 16 /**< Shift value for IO01V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 670 | #define _DEVINFO_VMONCAL1_IO01V86THRESFINE_MASK 0xF0000UL /**< Bit mask for IO01V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_SHIFT 20 /**< Shift value for IO01V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define _DEVINFO_VMONCAL1_IO01V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for IO01V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_SHIFT 24 /**< Shift value for IO02V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define _DEVINFO_VMONCAL1_IO02V98THRESFINE_MASK 0xF000000UL /**< Bit mask for IO02V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_SHIFT 28 /**< Shift value for IO02V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define _DEVINFO_VMONCAL1_IO02V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for IO02V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | |
| AnnaBridge | 171:3a7713b1edbc | 678 | /* Bit fields for DEVINFO VMONCAL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define _DEVINFO_VMONCAL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_VMONCAL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_SHIFT 0 /**< Shift value for PAVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESFINE_MASK 0xFUL /**< Bit mask for PAVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_SHIFT 4 /**< Shift value for PAVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define _DEVINFO_VMONCAL2_PAVDD1V86THRESCOARSE_MASK 0xF0UL /**< Bit mask for PAVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_SHIFT 8 /**< Shift value for PAVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESFINE_MASK 0xF00UL /**< Bit mask for PAVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_SHIFT 12 /**< Shift value for PAVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | #define _DEVINFO_VMONCAL2_PAVDD2V98THRESCOARSE_MASK 0xF000UL /**< Bit mask for PAVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 688 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_SHIFT 16 /**< Shift value for FVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESFINE_MASK 0xF0000UL /**< Bit mask for FVDD1V86THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_SHIFT 20 /**< Shift value for FVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 691 | #define _DEVINFO_VMONCAL2_FVDD1V86THRESCOARSE_MASK 0xF00000UL /**< Bit mask for FVDD1V86THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_SHIFT 24 /**< Shift value for FVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 693 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESFINE_MASK 0xF000000UL /**< Bit mask for FVDD2V98THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 694 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_SHIFT 28 /**< Shift value for FVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define _DEVINFO_VMONCAL2_FVDD2V98THRESCOARSE_MASK 0xF0000000UL /**< Bit mask for FVDD2V98THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | |
| AnnaBridge | 171:3a7713b1edbc | 697 | /* Bit fields for DEVINFO IDAC0CAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define _DEVINFO_IDAC0CAL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT 0 /**< Shift value for SOURCERANGE0TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK 0xFFUL /**< Bit mask for SOURCERANGE0TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT 8 /**< Shift value for SOURCERANGE1TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SOURCERANGE1TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT 16 /**< Shift value for SOURCERANGE2TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SOURCERANGE2TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT 24 /**< Shift value for SOURCERANGE3TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 706 | #define _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SOURCERANGE3TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | |
| AnnaBridge | 171:3a7713b1edbc | 708 | /* Bit fields for DEVINFO IDAC0CAL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define _DEVINFO_IDAC0CAL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_IDAC0CAL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT 0 /**< Shift value for SINKRANGE0TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK 0xFFUL /**< Bit mask for SINKRANGE0TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT 8 /**< Shift value for SINKRANGE1TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK 0xFF00UL /**< Bit mask for SINKRANGE1TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT 16 /**< Shift value for SINKRANGE2TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK 0xFF0000UL /**< Bit mask for SINKRANGE2TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT 24 /**< Shift value for SINKRANGE3TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK 0xFF000000UL /**< Bit mask for SINKRANGE3TUNING */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | |
| AnnaBridge | 171:3a7713b1edbc | 719 | /* Bit fields for DEVINFO DCDCLNVCTRL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define _DEVINFO_DCDCLNVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLNVCTRL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT 0 /**< Shift value for 1V2LNATT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK 0xFFUL /**< Bit mask for 1V2LNATT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 723 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT 8 /**< Shift value for 1V8LNATT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK 0xFF00UL /**< Bit mask for 1V8LNATT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT 16 /**< Shift value for 1V8LNATT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK 0xFF0000UL /**< Bit mask for 1V8LNATT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT 24 /**< Shift value for 3V0LNATT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK 0xFF000000UL /**< Bit mask for 3V0LNATT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | |
| AnnaBridge | 171:3a7713b1edbc | 730 | /* Bit fields for DEVINFO DCDCLPVCTRL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | #define _DEVINFO_DCDCLPVCTRL0_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 732 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | |
| AnnaBridge | 171:3a7713b1edbc | 741 | /* Bit fields for DEVINFO DCDCLPVCTRL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define _DEVINFO_DCDCLPVCTRL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V2LPATT0LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V2LPATT0LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT 8 /**< Shift value for 1V8LPATT0LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 1V8LPATT0LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 747 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V2LPATT0LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 748 | #define _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V2LPATT0LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 749 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT 24 /**< Shift value for 1V8LPATT0LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 1V8LPATT0LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | |
| AnnaBridge | 171:3a7713b1edbc | 752 | /* Bit fields for DEVINFO DCDCLPVCTRL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define _DEVINFO_DCDCLPVCTRL2_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL2 */ |
| AnnaBridge | 171:3a7713b1edbc | 754 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 755 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | #define _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 762 | |
| AnnaBridge | 171:3a7713b1edbc | 763 | /* Bit fields for DEVINFO DCDCLPVCTRL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define _DEVINFO_DCDCLPVCTRL3_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPVCTRL3 */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT 0 /**< Shift value for 1V8LPATT1LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK 0xFFUL /**< Bit mask for 1V8LPATT1LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT 8 /**< Shift value for 3V0LPATT1LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK 0xFF00UL /**< Bit mask for 3V0LPATT1LPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT 16 /**< Shift value for 1V8LPATT1LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK 0xFF0000UL /**< Bit mask for 1V8LPATT1LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 771 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT 24 /**< Shift value for 3V0LPATT1LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for 3V0LPATT1LPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 773 | |
| AnnaBridge | 171:3a7713b1edbc | 774 | /* Bit fields for DEVINFO DCDCLPCMPHYSSEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define _DEVINFO_DCDCLPCMPHYSSEL0_MASK 0x0000FFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL0 */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPATT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPATT0 */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPATT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPATT1 */ |
| AnnaBridge | 171:3a7713b1edbc | 780 | |
| AnnaBridge | 171:3a7713b1edbc | 781 | /* Bit fields for DEVINFO DCDCLPCMPHYSSEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define _DEVINFO_DCDCLPCMPHYSSEL1_MASK 0xFFFFFFFFUL /**< Mask for DEVINFO_DCDCLPCMPHYSSEL1 */ |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT 0 /**< Shift value for LPCMPHYSSELLPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK 0xFFUL /**< Bit mask for LPCMPHYSSELLPCMPBIAS0 */ |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT 8 /**< Shift value for LPCMPHYSSELLPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK 0xFF00UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS1 */ |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT 16 /**< Shift value for LPCMPHYSSELLPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK 0xFF0000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS2 */ |
| AnnaBridge | 171:3a7713b1edbc | 789 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT 24 /**< Shift value for LPCMPHYSSELLPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK 0xFF000000UL /**< Bit mask for LPCMPHYSSELLPCMPBIAS3 */ |
| AnnaBridge | 171:3a7713b1edbc | 791 | |
| AnnaBridge | 171:3a7713b1edbc | 792 | /** @} End of group EFM32PG1B_DEVINFO */ |
| AnnaBridge | 171:3a7713b1edbc | 793 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 794 |
